From 554a8f4026459406e7d3ed4e7017a88a57492ddf Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 3 Nov 2009 11:28:47 -0800
Subject: intel: Start adding defines and some bits for sandybridge bringup.

---
 src/mesa/drivers/dri/i965/brw_draw.c         |  4 ++
 src/mesa/drivers/dri/i965/brw_state_upload.c | 96 ++++++++++++++++++++++++++--
 2 files changed, 96 insertions(+), 4 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index e348d4686b..106cd31632 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -124,6 +124,10 @@ static void brw_emit_prim(struct brw_context *brw,
    struct brw_3d_primitive prim_packet;
    struct intel_context *intel = &brw->intel;
 
+   /* Last thing to hook up in the pipeline when brw_state_upload.c is done. */
+   if (IS_GEN6(intel->intelScreen->deviceID))
+      return;
+
    if (INTEL_DEBUG & DEBUG_PRIMS)
       printf("PRIM: %s %d %d\n", _mesa_lookup_enum_by_nr(prim->mode), 
 		   prim->start, prim->count);
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 4f477cfc6b..1ee4f4ab80 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -35,8 +35,15 @@
 #include "brw_state.h"
 #include "intel_batchbuffer.h"
 #include "intel_buffers.h"
+#include "intel_chipset.h"
 
-static const struct brw_tracked_state *atoms[] =
+/* This is used to initialize brw->state.atoms[].  We could use this
+ * list directly except for a single atom, brw_constant_buffer, which
+ * has a .dirty value which changes according to the parameters of the
+ * current fragment and vertex programs, and so cannot be a static
+ * value.
+ */
+static const struct brw_tracked_state *gen4_atoms[] =
 {
    &brw_check_fallback,
 
@@ -95,6 +102,66 @@ static const struct brw_tracked_state *atoms[] =
    &brw_constant_buffer
 };
 
+const struct brw_tracked_state *gen6_atoms[] =
+{
+   &brw_check_fallback,
+
+#if 0
+   &brw_wm_input_sizes,
+   &brw_vs_prog,
+   &brw_gs_prog,
+   &brw_clip_prog,
+   &brw_sf_prog,
+   &brw_wm_prog,
+
+   /* Once all the programs are done, we know how large urb entry
+    * sizes need to be and can decide if we need to change the urb
+    * layout.
+    */
+   &brw_curbe_offsets,
+   &brw_recalculate_urb_fence,
+
+   &brw_cc_vp,
+   &brw_cc_unit,
+
+   &brw_vs_surfaces,		/* must do before unit */
+   &brw_wm_constant_surface,	/* must do before wm surfaces/bind bo */
+   &brw_wm_surfaces,		/* must do before samplers and unit */
+   &brw_wm_samplers,
+
+   &brw_wm_unit,
+   &brw_sf_vp,
+   &brw_sf_unit,
+   &brw_vs_unit,		/* always required, enabled or not */
+   &brw_clip_unit,
+   &brw_gs_unit,
+
+   /* Command packets:
+    */
+   &brw_invarient_state,
+   &brw_state_base_address,
+
+   &brw_binding_table_pointers,
+   &brw_blend_constant_color,
+
+   &brw_depthbuffer,
+
+   &brw_polygon_stipple,
+   &brw_polygon_stipple_offset,
+
+   &brw_line_stipple,
+   &brw_aa_line_parameters,
+
+   &brw_psp_urb_cbs,
+
+   &brw_drawing_rect,
+   &brw_indices,
+   &brw_index_buffer,
+   &brw_vertices,
+
+   &brw_constant_buffer
+#endif
+};
 
 void brw_init_state( struct brw_context *brw )
 {
@@ -270,6 +337,8 @@ void brw_validate_state( struct brw_context *brw )
    struct intel_context *intel = &brw->intel;
    struct brw_state_flags *state = &brw->state.dirty;
    GLuint i;
+   const struct brw_tracked_state **atoms;
+   int num_atoms;
 
    brw_clear_validated_bos(brw);
 
@@ -278,6 +347,14 @@ void brw_validate_state( struct brw_context *brw )
 
    brw_add_validated_bo(brw, intel->batch->buf);
 
+   if (IS_GEN6(intel->intelScreen->deviceID)) {
+      atoms = gen6_atoms;
+      num_atoms = ARRAY_SIZE(gen6_atoms);
+   } else {
+      atoms = gen4_atoms;
+      num_atoms = ARRAY_SIZE(gen4_atoms);
+   }
+
    if (brw->emit_state_always) {
       state->mesa |= ~0;
       state->brw |= ~0;
@@ -305,7 +382,7 @@ void brw_validate_state( struct brw_context *brw )
    brw->intel.Fallback = GL_FALSE; /* boolean, not bitfield */
 
    /* do prepare stage for all atoms */
-   for (i = 0; i < Elements(atoms); i++) {
+   for (i = 0; i < num_atoms; i++) {
       const struct brw_tracked_state *atom = atoms[i];
 
       if (brw->intel.Fallback)
@@ -337,9 +414,20 @@ void brw_validate_state( struct brw_context *brw )
 
 void brw_upload_state(struct brw_context *brw)
 {
+   struct intel_context *intel = &brw->intel;
    struct brw_state_flags *state = &brw->state.dirty;
    int i;
    static int dirty_count = 0;
+   const struct brw_tracked_state **atoms;
+   int num_atoms;
+
+   if (IS_GEN6(intel->intelScreen->deviceID)) {
+      atoms = gen6_atoms;
+      num_atoms = ARRAY_SIZE(gen6_atoms);
+   } else {
+      atoms = gen4_atoms;
+      num_atoms = ARRAY_SIZE(gen4_atoms);
+   }
 
    brw_clear_validated_bos(brw);
 
@@ -352,7 +440,7 @@ void brw_upload_state(struct brw_context *brw)
       memset(&examined, 0, sizeof(examined));
       prev = *state;
 
-      for (i = 0; i < Elements(atoms); i++) {	 
+      for (i = 0; i < num_atoms; i++) {
 	 const struct brw_tracked_state *atom = atoms[i];
 	 struct brw_state_flags generated;
 
@@ -381,7 +469,7 @@ void brw_upload_state(struct brw_context *brw)
       }
    }
    else {
-      for (i = 0; i < Elements(atoms); i++) {	 
+      for (i = 0; i < num_atoms; i++) {
 	 const struct brw_tracked_state *atom = atoms[i];
 
 	 if (brw->intel.Fallback)
-- 
cgit v1.2.3


From 719f2b1d8570aa58b970bd28941221ee6c34af9b Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 3 Nov 2009 13:19:30 -0800
Subject: i965: Set up sandybridge depthbuffer.

---
 src/mesa/drivers/dri/i965/brw_misc_state.c   | 21 ++++++++++++++++++---
 src/mesa/drivers/dri/i965/brw_state_upload.c |  2 ++
 src/mesa/drivers/dri/intel/intel_decode.c    |  4 +++-
 3 files changed, 23 insertions(+), 4 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index f708ee0063..d6eb6162df 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -209,7 +209,14 @@ static void emit_depthbuffer(struct brw_context *brw)
 {
    struct intel_context *intel = &brw->intel;
    struct intel_region *region = brw->state.depth_region;
-   unsigned int len = (intel->is_g4x || intel->is_ironlake) ? 6 : 5;
+   unsigned int len;
+
+   if (intel->gen >= 6)
+      len = 7;
+   else if (intel->is_g4x || intel->is_ironlake)
+      len = 6;
+   else
+      len = 5;
 
    if (region == NULL) {
       BEGIN_BATCH(len);
@@ -220,9 +227,12 @@ static void emit_depthbuffer(struct brw_context *brw)
       OUT_BATCH(0);
       OUT_BATCH(0);
 
-      if (intel->is_g4x || intel->is_ironlake)
+      if (intel->is_g4x || intel->is_ironlake || intel->gen >= 6)
          OUT_BATCH(0);
 
+      if (intel->gen >= 6)
+	 OUT_BATCH(0);
+
       ADVANCE_BATCH();
    } else {
       unsigned int format;
@@ -243,6 +253,8 @@ static void emit_depthbuffer(struct brw_context *brw)
       }
 
       assert(region->tiling != I915_TILING_X);
+      if (IS_GEN6(intel->intelScreen->deviceID))
+	 assert(region->tiling != I915_TILING_NONE);
 
       BEGIN_BATCH(len);
       OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2));
@@ -259,9 +271,12 @@ static void emit_depthbuffer(struct brw_context *brw)
 		((region->height - 1) << 19));
       OUT_BATCH(0);
 
-      if (intel->is_g4x || intel->is_ironlake)
+      if (intel->is_g4x || intel->is_ironlake || intel->gen >= 6)
          OUT_BATCH(0);
 
+      if (intel->gen >= 6)
+	 OUT_BATCH(0);
+
       ADVANCE_BATCH();
    }
 }
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 1ee4f4ab80..4c12e68c0e 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -143,9 +143,11 @@ const struct brw_tracked_state *gen6_atoms[] =
 
    &brw_binding_table_pointers,
    &brw_blend_constant_color,
+#endif
 
    &brw_depthbuffer,
 
+#if 0
    &brw_polygon_stipple,
    &brw_polygon_stipple_offset,
 
diff --git a/src/mesa/drivers/dri/intel/intel_decode.c b/src/mesa/drivers/dri/intel/intel_decode.c
index a9dfe281cb..c3112d980a 100644
--- a/src/mesa/drivers/dri/intel/intel_decode.c
+++ b/src/mesa/drivers/dri/intel/intel_decode.c
@@ -1592,7 +1592,7 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, int *failures)
 	return len;
 
     case 0x7905:
-	if (len != 5 && len != 6)
+	if (len < 5 || len > 7)
 	    fprintf(out, "Bad count in 3DSTATE_DEPTH_BUFFER\n");
 	if (count < len)
 	    BUFFER_FAIL(count, len, "3DSTATE_DEPTH_BUFFER");
@@ -1611,6 +1611,8 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, int *failures)
 	instr_out(data, hw_offset, 4, "volume depth\n");
 	if (len == 6)
 	    instr_out(data, hw_offset, 5, "\n");
+	if (len == 7)
+	    instr_out(data, hw_offset, 6, "render target view extent\n");
 
 	return len;
 
-- 
cgit v1.2.3


From 0b9932ffde3f7228288717302b43aa01df0b5fa0 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 3 Nov 2009 13:41:22 -0800
Subject: i965: Update WM surface state setup for sandybridge's new
 BLEND_STATE.

---
 src/mesa/drivers/dri/i965/brw_state_upload.c     |  2 ++
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 39 +++++++++++++-----------
 2 files changed, 24 insertions(+), 17 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 4c12e68c0e..afa940962f 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -124,9 +124,11 @@ const struct brw_tracked_state *gen6_atoms[] =
    &brw_cc_vp,
    &brw_cc_unit,
 
+#endif
    &brw_vs_surfaces,		/* must do before unit */
    &brw_wm_constant_surface,	/* must do before wm surfaces/bind bo */
    &brw_wm_surfaces,		/* must do before samplers and unit */
+#if 0
    &brw_wm_samplers,
 
    &brw_wm_unit,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 1db438ae7b..a42067611c 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -509,7 +509,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
 				struct gl_renderbuffer *rb,
 				unsigned int unit)
 {
-   struct intel_context *intel = &brw->intel;;
+   struct intel_context *intel = &brw->intel;
    GLcontext *ctx = &intel->ctx;
    dri_bo *region_bo = NULL;
    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
@@ -576,18 +576,21 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
       key.draw_x = 0;
       key.draw_y = 0;
    }
-   /* _NEW_COLOR */
-   memcpy(key.color_mask, ctx->Color.ColorMask[unit],
-	  sizeof(key.color_mask));
 
-   /* As mentioned above, disable writes to the alpha component when the
-    * renderbuffer is XRGB.
-    */
-   if (ctx->DrawBuffer->Visual.alphaBits == 0)
-     key.color_mask[3] = GL_FALSE;
+   if (intel->gen < 6) {
+      /* _NEW_COLOR */
+      memcpy(key.color_mask, ctx->Color.ColorMask[unit],
+	     sizeof(key.color_mask));
+
+      /* As mentioned above, disable writes to the alpha component when the
+       * renderbuffer is XRGB.
+       */
+      if (ctx->DrawBuffer->Visual.alphaBits == 0)
+	 key.color_mask[3] = GL_FALSE;
 
-   key.color_blend = (!ctx->Color._LogicOpEnabled &&
-		      (ctx->Color.BlendEnabled & (1 << unit)));
+      key.color_blend = (!ctx->Color._LogicOpEnabled &&
+			 (ctx->Color.BlendEnabled & (1 << unit)));
+   }
 
    dri_bo_unreference(brw->wm.surf_bo[unit]);
    brw->wm.surf_bo[unit] = brw_search_cache(&brw->surface_cache,
@@ -639,12 +642,14 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
       brw_set_surface_tiling(&surf, key.tiling);
       surf.ss3.pitch = (key.pitch * key.cpp) - 1;
 
-      /* _NEW_COLOR */
-      surf.ss0.color_blend = key.color_blend;
-      surf.ss0.writedisable_red =   !key.color_mask[0];
-      surf.ss0.writedisable_green = !key.color_mask[1];
-      surf.ss0.writedisable_blue =  !key.color_mask[2];
-      surf.ss0.writedisable_alpha = !key.color_mask[3];
+      if (intel->gen < 6) {
+	 /* _NEW_COLOR */
+	 surf.ss0.color_blend = key.color_blend;
+	 surf.ss0.writedisable_red =   !key.color_mask[0];
+	 surf.ss0.writedisable_green = !key.color_mask[1];
+	 surf.ss0.writedisable_blue =  !key.color_mask[2];
+	 surf.ss0.writedisable_alpha = !key.color_mask[3];
+      }
 
       /* Key size will never match key size for textures, so we're safe. */
       brw->wm.surf_bo[unit] = brw_upload_cache(&brw->surface_cache,
-- 
cgit v1.2.3


From 9dce60f35b25f4f5605b22d75447bac5d9f55515 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 3 Nov 2009 14:02:24 -0800
Subject: i965: Set up sandybridge binding table pointers but don't enable it
 yet.

It hangs the GPU at the clipper stage, presumably because we're lacking
other setup.
---
 src/mesa/drivers/dri/i965/brw_defines.h    |  3 +++
 src/mesa/drivers/dri/i965/brw_misc_state.c | 35 ++++++++++++++++++++++++++++++
 src/mesa/drivers/dri/i965/brw_state.h      |  1 +
 3 files changed, 39 insertions(+)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index ea0d7e05d4..afdc5a1d85 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -778,6 +778,9 @@
 
 #define CMD_PIPELINED_STATE_POINTERS  0x7800
 #define CMD_BINDING_TABLE_PTRS        0x7801
+# define GEN6_BINDING_TABLE_MODIFY_VS	(1 << 8)
+# define GEN6_BINDING_TABLE_MODIFY_GS	(1 << 9)
+# define GEN6_BINDING_TABLE_MODIFY_PS	(1 << 10)
 
 #define CMD_VERTEX_BUFFER             0x7808
 # define BRW_VB0_INDEX_SHIFT		27
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index d6eb6162df..7d9e793ff2 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -136,6 +136,41 @@ const struct brw_tracked_state brw_binding_table_pointers = {
    .emit = upload_binding_table_pointers,
 };
 
+/**
+ * Upload the binding table pointers, which point each stage's array of surface
+ * state pointers.
+ *
+ * The binding table pointers are relative to the surface state base address,
+ * which is 0.
+ */
+static void upload_gen6_binding_table_pointers(struct brw_context *brw)
+{
+   struct intel_context *intel = &brw->intel;
+
+   BEGIN_BATCH(4);
+   OUT_BATCH(CMD_BINDING_TABLE_PTRS << 16 |
+	     GEN6_BINDING_TABLE_MODIFY_VS |
+	     GEN6_BINDING_TABLE_MODIFY_GS |
+	     GEN6_BINDING_TABLE_MODIFY_PS |
+	     (4 - 2));
+   if (brw->vs.bind_bo != NULL)
+      OUT_RELOC(brw->vs.bind_bo, I915_GEM_DOMAIN_SAMPLER, 0, 0); /* vs */
+   else
+      OUT_BATCH(0);
+   OUT_BATCH(0); /* gs */
+   OUT_RELOC(brw->wm.bind_bo, I915_GEM_DOMAIN_SAMPLER, 0, 0); /* wm/ps */
+   ADVANCE_BATCH();
+}
+
+const struct brw_tracked_state gen6_binding_table_pointers = {
+   .dirty = {
+      .mesa = 0,
+      .brw = BRW_NEW_BATCH,
+      .cache = CACHE_NEW_SURF_BIND,
+   },
+   .prepare = prepare_binding_table_pointers,
+   .emit = upload_gen6_binding_table_pointers,
+};
 
 /**
  * Upload pointers to the per-stage state.
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 536fe8b249..a24a02100c 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -90,6 +90,7 @@ const struct brw_tracked_state brw_drawing_rect;
 const struct brw_tracked_state brw_indices;
 const struct brw_tracked_state brw_vertices;
 const struct brw_tracked_state brw_index_buffer;
+const struct brw_tracked_state gen6_binding_table_pointers;
 
 /**
  * Use same key for WM and VS surfaces.
-- 
cgit v1.2.3


From 7ee590424c974cb10882e9c4664a6024595fc9de Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 29 Jan 2010 11:18:26 -0800
Subject: i965: Start adding support for the Sandybridge CC unit.

---
 src/mesa/drivers/dri/i965/Makefile            |   4 +-
 src/mesa/drivers/dri/i965/brw_context.h       |  15 +-
 src/mesa/drivers/dri/i965/brw_defines.h       |   1 +
 src/mesa/drivers/dri/i965/brw_state.h         |   4 +
 src/mesa/drivers/dri/i965/brw_state_cache.c   |   1 +
 src/mesa/drivers/dri/i965/brw_state_upload.c  |   7 +-
 src/mesa/drivers/dri/i965/brw_structs.h       | 100 ++++++++-
 src/mesa/drivers/dri/i965/gen6_cc.c           | 296 ++++++++++++++++++++++++++
 src/mesa/drivers/dri/i965/gen6_depthstencil.c | 169 +++++++++++++++
 9 files changed, 592 insertions(+), 5 deletions(-)
 create mode 100644 src/mesa/drivers/dri/i965/gen6_cc.c
 create mode 100644 src/mesa/drivers/dri/i965/gen6_depthstencil.c

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index 7758a792fd..7ce794d3aa 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -84,7 +84,9 @@ DRIVER_SOURCES = \
 	brw_wm_pass2.c \
 	brw_wm_sampler_state.c \
 	brw_wm_state.c \
-	brw_wm_surface_state.c 
+	brw_wm_surface_state.c \
+	gen6_cc.c \
+	gen6_depthstencil.c
 
 C_SOURCES = \
 	$(COMMON_SOURCES) \
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 21c4cd38a7..ea89d4f6fa 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -282,6 +282,9 @@ struct brw_vs_ouput_sizes {
 
 
 enum brw_cache_id {
+   BRW_BLEND_STATE,
+   BRW_DEPTH_STENCIL_STATE,
+   BRW_COLOR_CALC_STATE,
    BRW_CC_VP,
    BRW_CC_UNIT,
    BRW_WM_PROG,
@@ -354,6 +357,9 @@ struct brw_tracked_state {
 
 /* Flags for brw->state.cache.
  */
+#define CACHE_NEW_BLEND_STATE            (1<<BRW_BLEND_STATE)
+#define CACHE_NEW_DEPTH_STENCIL_STATE    (1<<BRW_DEPTH_STENCIL_STATE)
+#define CACHE_NEW_COLOR_CALC_STATE       (1<<BRW_COLOR_CALC_STATE)
 #define CACHE_NEW_CC_VP                  (1<<BRW_CC_VP)
 #define CACHE_NEW_CC_UNIT                (1<<BRW_CC_UNIT)
 #define CACHE_NEW_WM_PROG                (1<<BRW_WM_PROG)
@@ -643,9 +649,16 @@ struct brw_context
 
 
    struct {
+      /* gen4 */
       dri_bo *prog_bo;
-      dri_bo *state_bo;
       dri_bo *vp_bo;
+
+      /* gen6 */
+      dri_bo *blend_state_bo;
+      dri_bo *depth_stencil_state_bo;
+      dri_bo *color_calc_state_bo;
+
+      dri_bo *state_bo;
    } cc;
 
    struct {
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index afdc5a1d85..5d3b0a8b7a 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -807,6 +807,7 @@
 # define BRW_VE1_COMPONENT_3_SHIFT	16
 # define BRW_VE1_DST_OFFSET_SHIFT	0
 
+#define CMD_3D_CC_STATE_POINTERS      0x780e /* GEN6+ */
 #define CMD_INDEX_BUFFER              0x780a
 #define CMD_VF_STATISTICS_965         0x780b
 #define CMD_VF_STATISTICS_GM45        0x680b
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index a24a02100c..5112cd8016 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -91,6 +91,10 @@ const struct brw_tracked_state brw_indices;
 const struct brw_tracked_state brw_vertices;
 const struct brw_tracked_state brw_index_buffer;
 const struct brw_tracked_state gen6_binding_table_pointers;
+const struct brw_tracked_state gen6_blend_state;
+const struct brw_tracked_state gen6_cc_state_pointers;
+const struct brw_tracked_state gen6_color_calc_state;
+const struct brw_tracked_state gen6_depth_stencil_state;
 
 /**
  * Use same key for WM and VS surfaces.
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c b/src/mesa/drivers/dri/i965/brw_state_cache.c
index 4bb98d8d5d..c08cb45b75 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -390,6 +390,7 @@ brw_init_non_surface_cache(struct brw_context *brw)
    brw_init_cache_id(cache, "GS_UNIT", BRW_GS_UNIT);
 
    brw_init_cache_id(cache, "GS_PROG", BRW_GS_PROG);
+   brw_init_cache_id(cache, "BLEND_STATE", BRW_BLEND_STATE);
 }
 
 
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index afa940962f..ed9e18f33c 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -122,9 +122,13 @@ const struct brw_tracked_state *gen6_atoms[] =
    &brw_recalculate_urb_fence,
 
    &brw_cc_vp,
-   &brw_cc_unit,
 
 #endif
+   &gen6_blend_state,		/* must do before cc unit */
+   &gen6_color_calc_state,	/* must do before cc unit */
+   &gen6_depth_stencil_state,	/* must do before cc unit */
+   &gen6_cc_state_pointers,
+
    &brw_vs_surfaces,		/* must do before unit */
    &brw_wm_constant_surface,	/* must do before wm surfaces/bind bo */
    &brw_wm_surfaces,		/* must do before samplers and unit */
@@ -282,6 +286,7 @@ static struct dirty_bit_map brw_bits[] = {
 };
 
 static struct dirty_bit_map cache_bits[] = {
+   DEFINE_BIT(CACHE_NEW_BLEND_STATE),
    DEFINE_BIT(CACHE_NEW_CC_VP),
    DEFINE_BIT(CACHE_NEW_CC_UNIT),
    DEFINE_BIT(CACHE_NEW_WM_PROG),
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 66d4127271..10c0c62202 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -658,7 +658,105 @@ struct brw_clip_unit_state
    GLfloat viewport_ymax;  
 };
 
+struct gen6_blend_state
+{
+   struct {
+      GLuint dest_blend_factor:5;
+      GLuint source_blend_factor:5;
+      GLuint pad3:1;
+      GLuint blend_func:3;
+      GLuint pad2:1;
+      GLuint ia_dest_blend_factor:5;
+      GLuint ia_source_blend_factor:5;
+      GLuint pad1:1;
+      GLuint ia_blend_func:3;
+      GLuint pad0:1;
+      GLuint ia_blend_enable:1;
+      GLuint blend_enable:1;
+   } blend0;
+
+   struct {
+      GLuint post_blend_clamp_enable:1;
+      GLuint pre_blend_clamp_enable:1;
+      GLuint clamp_range:2;
+      GLuint pad0:4;
+      GLuint x_dither_offset:2;
+      GLuint y_dither_offset:2;
+      GLuint dither_enable:1;
+      GLuint alpha_test_func:3;
+      GLuint alpha_test_enable:1;
+      GLuint pad1:1;
+      GLuint logic_op_func:4;
+      GLuint logic_op_enable:1;
+      GLuint pad2:1;
+      GLuint write_disable_b:1;
+      GLuint write_disable_g:1;
+      GLuint write_disable_r:1;
+      GLuint write_disable_a:1;
+      GLuint pad3:1;
+      GLuint alpha_to_coverage_dither:1;
+      GLuint alpha_to_one:1;
+      GLuint alpha_to_coverage:1;
+   } blend1;
+};
 
+struct gen6_color_calc_state
+{
+   struct {
+      GLuint alpha_test_format:1;
+      GLuint pad0:14;
+      GLuint round_disable:1;
+      GLuint bf_stencil_ref:8;
+      GLuint stencil_ref:8;
+   } cc0;
+
+   union {
+      GLfloat alpha_ref_f;
+      struct {
+	 GLuint ui:8;
+	 GLuint pad0:24;
+      } alpha_ref_fi;
+   } cc1;
+
+   GLfloat constant_r;
+   GLfloat constant_g;
+   GLfloat constant_b;
+   GLfloat constant_a;
+};
+
+struct gen6_depth_stencil_state
+{
+   struct {
+      GLuint pad0:3;
+      GLuint bf_stencil_pass_depth_pass_op:3;
+      GLuint bf_stencil_pass_depth_fail_op:3;
+      GLuint bf_stencil_fail_op:3;
+      GLuint bf_stencil_func:3;
+      GLuint bf_stencil_enable:1;
+      GLuint pad1:2;
+      GLuint stencil_write_enable:1;
+      GLuint stencil_pass_depth_pass_op:3;
+      GLuint stencil_pass_depth_fail_op:3;
+      GLuint stencil_fail_op:3;
+      GLuint stencil_func:3;
+      GLuint stencil_enable:1;
+   } ds0;
+
+   struct {
+      GLuint bf_stencil_write_mask:8;
+      GLuint bf_stencil_test_mask:8;
+      GLuint stencil_write_mask:8;
+      GLuint stencil_test_mask:8;
+   } ds1;
+
+   struct {
+      GLuint pad0:25;
+      GLuint depth_write_enable:1;
+      GLuint depth_test_func:3;
+      GLuint pad1:1;
+      GLuint depth_test_enable:1;
+   } ds2;
+};
 
 struct brw_cc_unit_state
 {
@@ -752,8 +850,6 @@ struct brw_cc_unit_state
    } cc7;
 };
 
-
-
 struct brw_sf_unit_state
 {
    struct thread0 thread0;
diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c
new file mode 100644
index 0000000000..b1b6dc7db3
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -0,0 +1,296 @@
+/*
+ * Copyright © 2009 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Eric Anholt <eric@anholt.net>
+ *
+ */
+
+#include "brw_context.h"
+#include "brw_state.h"
+#include "brw_defines.h"
+#include "brw_util.h"
+#include "intel_batchbuffer.h"
+#include "main/macros.h"
+#include "main/enums.h"
+
+struct brw_blend_state_key {
+   GLboolean color_blend, alpha_enabled;
+
+   GLenum logic_op;
+
+   GLenum blend_eq_rgb, blend_eq_a;
+   GLenum blend_src_rgb, blend_src_a;
+   GLenum blend_dst_rgb, blend_dst_a;
+
+   GLenum alpha_func;
+
+   GLboolean dither;
+};
+
+static void
+blend_state_populate_key(struct brw_context *brw,
+			 struct brw_blend_state_key *key)
+{
+   GLcontext *ctx = &brw->intel.ctx;
+
+   memset(key, 0, sizeof(*key));
+
+   /* _NEW_COLOR */
+   if (ctx->Color._LogicOpEnabled)
+      key->logic_op = ctx->Color.LogicOp;
+   else
+      key->logic_op = GL_COPY;
+
+   /* _NEW_COLOR */
+   key->color_blend = ctx->Color.BlendEnabled;
+   if (key->color_blend) {
+      key->blend_eq_rgb = ctx->Color.BlendEquationRGB;
+      key->blend_eq_a = ctx->Color.BlendEquationA;
+      key->blend_src_rgb = ctx->Color.BlendSrcRGB;
+      key->blend_dst_rgb = ctx->Color.BlendDstRGB;
+      key->blend_src_a = ctx->Color.BlendSrcA;
+      key->blend_dst_a = ctx->Color.BlendDstA;
+   }
+
+   /* _NEW_COLOR */
+   key->alpha_enabled = ctx->Color.AlphaEnabled;
+   if (key->alpha_enabled) {
+      key->alpha_func = ctx->Color.AlphaFunc;
+   }
+
+   /* _NEW_COLOR */
+   key->dither = ctx->Color.DitherFlag;
+}
+
+/**
+ * Creates the state cache entry for the given CC unit key.
+ */
+static drm_intel_bo *
+blend_state_create_from_key(struct brw_context *brw,
+			    struct brw_blend_state_key *key)
+{
+   struct gen6_blend_state blend;
+   drm_intel_bo *bo;
+
+   memset(&blend, 0, sizeof(blend));
+
+   if (key->logic_op != GL_COPY) {
+      blend.blend1.logic_op_enable = 1;
+      blend.blend1.logic_op_func = intel_translate_logic_op(key->logic_op);
+   } else if (key->color_blend) {
+      GLenum eqRGB = key->blend_eq_rgb;
+      GLenum eqA = key->blend_eq_a;
+      GLenum srcRGB = key->blend_src_rgb;
+      GLenum dstRGB = key->blend_dst_rgb;
+      GLenum srcA = key->blend_src_a;
+      GLenum dstA = key->blend_dst_a;
+
+      if (eqRGB == GL_MIN || eqRGB == GL_MAX) {
+	 srcRGB = dstRGB = GL_ONE;
+      }
+
+      if (eqA == GL_MIN || eqA == GL_MAX) {
+	 srcA = dstA = GL_ONE;
+      }
+
+      blend.blend0.dest_blend_factor = brw_translate_blend_factor(dstRGB);
+      blend.blend0.source_blend_factor = brw_translate_blend_factor(srcRGB);
+      blend.blend0.blend_func = brw_translate_blend_equation(eqRGB);
+
+      blend.blend0.ia_dest_blend_factor = brw_translate_blend_factor(dstA);
+      blend.blend0.ia_source_blend_factor = brw_translate_blend_factor(srcA);
+      blend.blend0.ia_blend_func = brw_translate_blend_equation(eqA);
+
+      blend.blend0.blend_enable = 1;
+      blend.blend0.ia_blend_enable = (srcA != srcRGB ||
+				      dstA != dstRGB ||
+				      eqA != eqRGB);
+   }
+
+   if (key->alpha_enabled) {
+      blend.blend1.alpha_test_enable = 1;
+      blend.blend1.alpha_test_func = intel_translate_compare_func(key->alpha_func);
+
+   }
+
+   if (key->dither) {
+      blend.blend1.dither_enable = 1;
+      blend.blend1.y_dither_offset = 0;
+      blend.blend1.x_dither_offset = 0;
+   }
+
+   bo = brw_upload_cache(&brw->cache, BRW_BLEND_STATE,
+			 key, sizeof(*key),
+			 NULL, 0,
+			 &blend, sizeof(blend));
+
+   return bo;
+}
+
+static void
+prepare_blend_state(struct brw_context *brw)
+{
+   struct brw_blend_state_key key;
+
+   blend_state_populate_key(brw, &key);
+
+   drm_intel_bo_unreference(brw->cc.blend_state_bo);
+   brw->cc.blend_state_bo = brw_search_cache(&brw->cache, BRW_BLEND_STATE,
+					     &key, sizeof(key),
+					     NULL, 0,
+					     NULL);
+
+   if (brw->cc.blend_state_bo == NULL)
+      brw->cc.blend_state_bo = blend_state_create_from_key(brw, &key);
+}
+
+const struct brw_tracked_state gen6_blend_state = {
+   .dirty = {
+      .mesa = _NEW_COLOR,
+      .brw = 0,
+      .cache = 0,
+   },
+   .prepare = prepare_blend_state,
+};
+
+struct brw_color_calc_state_key {
+   GLubyte blend_constant_color[4];
+   GLclampf alpha_ref;
+   GLubyte stencil_ref[2];
+};
+
+static void
+color_calc_state_populate_key(struct brw_context *brw,
+			      struct brw_color_calc_state_key *key)
+{
+   GLcontext *ctx = &brw->intel.ctx;
+
+   memset(key, 0, sizeof(*key));
+
+   /* _NEW_STENCIL */
+   if (ctx->Stencil._Enabled) {
+      const unsigned back = ctx->Stencil._BackFace;
+
+      key->stencil_ref[0] = ctx->Stencil.Ref[0];
+      if (ctx->Stencil._TestTwoSide)
+	 key->stencil_ref[1] = ctx->Stencil.Ref[back];
+   }
+
+   /* _NEW_COLOR */
+   if (ctx->Color.AlphaEnabled)
+      key->alpha_ref = ctx->Color.AlphaRef;
+
+   key->blend_constant_color[0] = ctx->Color.BlendColor[0];
+   key->blend_constant_color[1] = ctx->Color.BlendColor[1];
+   key->blend_constant_color[2] = ctx->Color.BlendColor[2];
+   key->blend_constant_color[3] = ctx->Color.BlendColor[3];
+}
+
+/**
+ * Creates the state cache entry for the given CC state key.
+ */
+static drm_intel_bo *
+color_calc_state_create_from_key(struct brw_context *brw,
+				 struct brw_color_calc_state_key *key)
+{
+   struct gen6_color_calc_state cc;
+   drm_intel_bo *bo;
+
+   memset(&cc, 0, sizeof(cc));
+
+   cc.cc0.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8;
+   UNCLAMPED_FLOAT_TO_UBYTE(cc.cc1.alpha_ref_fi.ui, key->alpha_ref);
+
+   cc.cc0.stencil_ref = key->stencil_ref[0];
+   cc.cc0.bf_stencil_ref = key->stencil_ref[1];
+
+   cc.constant_r = key->blend_constant_color[0];
+   cc.constant_g = key->blend_constant_color[1];
+   cc.constant_b = key->blend_constant_color[2];
+   cc.constant_a = key->blend_constant_color[3];
+
+   bo = brw_upload_cache(&brw->cache, BRW_COLOR_CALC_STATE,
+			 key, sizeof(*key),
+			 NULL, 0,
+			 &cc, sizeof(cc));
+
+   return bo;
+}
+
+static void
+prepare_color_calc_state(struct brw_context *brw)
+{
+   struct brw_color_calc_state_key key;
+
+   color_calc_state_populate_key(brw, &key);
+
+   drm_intel_bo_unreference(brw->cc.state_bo);
+   brw->cc.state_bo = brw_search_cache(&brw->cache, BRW_COLOR_CALC_STATE,
+				       &key, sizeof(key),
+				       NULL, 0,
+				       NULL);
+
+   if (brw->cc.state_bo == NULL)
+      brw->cc.state_bo = color_calc_state_create_from_key(brw, &key);
+}
+
+const struct brw_tracked_state gen6_color_calc_state = {
+   .dirty = {
+      .mesa = _NEW_COLOR,
+      .brw = 0,
+      .cache = 0,
+   },
+   .prepare = prepare_color_calc_state,
+};
+
+static void upload_cc_state_pointers(struct brw_context *brw)
+{
+   struct intel_context *intel = &brw->intel;
+
+   BEGIN_BATCH(4);
+   OUT_BATCH(CMD_3D_CC_STATE_POINTERS << 16 | (4 - 2));
+   OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+   OUT_RELOC(brw->cc.blend_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+   OUT_RELOC(brw->cc.depth_stencil_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+   ADVANCE_BATCH();
+}
+
+
+static void prepare_cc_state_pointers(struct brw_context *brw)
+{
+   brw_add_validated_bo(brw, brw->cc.state_bo);
+   brw_add_validated_bo(brw, brw->cc.blend_state_bo);
+   brw_add_validated_bo(brw, brw->cc.depth_stencil_state_bo);
+}
+
+const struct brw_tracked_state gen6_cc_state_pointers = {
+   .dirty = {
+      .mesa = 0,
+      .brw = BRW_NEW_BATCH,
+      .cache = (CACHE_NEW_BLEND_STATE |
+		CACHE_NEW_COLOR_CALC_STATE |
+		CACHE_NEW_DEPTH_STENCIL_STATE)
+   },
+   .prepare = prepare_cc_state_pointers,
+   .emit = upload_cc_state_pointers,
+};
diff --git a/src/mesa/drivers/dri/i965/gen6_depthstencil.c b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
new file mode 100644
index 0000000000..960927164c
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright © 2009 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Eric Anholt <eric@anholt.net>
+ *
+ */
+
+#include "brw_context.h"
+#include "brw_state.h"
+#include "brw_defines.h"
+#include "brw_util.h"
+#include "main/macros.h"
+#include "main/enums.h"
+
+struct brw_depth_stencil_state_key {
+   GLenum depth_func;
+   GLboolean depth_test, depth_write;
+   GLboolean stencil, stencil_two_side;
+   GLenum stencil_func[2], stencil_fail_op[2];
+   GLenum stencil_pass_depth_fail_op[2], stencil_pass_depth_pass_op[2];
+   GLubyte stencil_write_mask[2], stencil_test_mask[2];
+};
+
+static void
+depth_stencil_state_populate_key(struct brw_context *brw,
+				 struct brw_depth_stencil_state_key *key)
+{
+   GLcontext *ctx = &brw->intel.ctx;
+   const unsigned back = ctx->Stencil._BackFace;
+
+   memset(key, 0, sizeof(*key));
+
+   /* _NEW_STENCIL */
+   key->stencil = ctx->Stencil._Enabled;
+   key->stencil_two_side = ctx->Stencil._TestTwoSide;
+
+   if (key->stencil) {
+      key->stencil_func[0] = ctx->Stencil.Function[0];
+      key->stencil_fail_op[0] = ctx->Stencil.FailFunc[0];
+      key->stencil_pass_depth_fail_op[0] = ctx->Stencil.ZFailFunc[0];
+      key->stencil_pass_depth_pass_op[0] = ctx->Stencil.ZPassFunc[0];
+      key->stencil_write_mask[0] = ctx->Stencil.WriteMask[0];
+      key->stencil_test_mask[0] = ctx->Stencil.ValueMask[0];
+   }
+   if (key->stencil_two_side) {
+      key->stencil_func[1] = ctx->Stencil.Function[back];
+      key->stencil_fail_op[1] = ctx->Stencil.FailFunc[back];
+      key->stencil_pass_depth_fail_op[1] = ctx->Stencil.ZFailFunc[back];
+      key->stencil_pass_depth_pass_op[1] = ctx->Stencil.ZPassFunc[back];
+      key->stencil_write_mask[1] = ctx->Stencil.WriteMask[back];
+      key->stencil_test_mask[1] = ctx->Stencil.ValueMask[back];
+   }
+
+   key->depth_test = ctx->Depth.Test;
+   if (key->depth_test) {
+      key->depth_func = ctx->Depth.Func;
+      key->depth_write = ctx->Depth.Mask;
+   }
+}
+
+/**
+ * Creates the state cache entry for the given DEPTH_STENCIL_STATE state key.
+ */
+static dri_bo *
+depth_stencil_state_create_from_key(struct brw_context *brw,
+				    struct brw_depth_stencil_state_key *key)
+{
+   struct gen6_depth_stencil_state ds;
+   dri_bo *bo;
+
+   memset(&ds, 0, sizeof(ds));
+
+   /* _NEW_STENCIL */
+   if (key->stencil) {
+      ds.ds0.stencil_enable = 1;
+      ds.ds0.stencil_func =
+	 intel_translate_compare_func(key->stencil_func[0]);
+      ds.ds0.stencil_fail_op =
+	 intel_translate_stencil_op(key->stencil_fail_op[0]);
+      ds.ds0.stencil_pass_depth_fail_op =
+	 intel_translate_stencil_op(key->stencil_pass_depth_fail_op[0]);
+      ds.ds0.stencil_pass_depth_pass_op =
+	 intel_translate_stencil_op(key->stencil_pass_depth_pass_op[0]);
+      ds.ds1.stencil_write_mask = key->stencil_write_mask[0];
+      ds.ds1.stencil_test_mask = key->stencil_test_mask[0];
+
+      if (key->stencil_two_side) {
+	 ds.ds0.bf_stencil_enable = 1;
+	 ds.ds0.bf_stencil_func =
+	    intel_translate_compare_func(key->stencil_func[1]);
+	 ds.ds0.bf_stencil_fail_op =
+	    intel_translate_stencil_op(key->stencil_fail_op[1]);
+	 ds.ds0.bf_stencil_pass_depth_fail_op =
+	    intel_translate_stencil_op(key->stencil_pass_depth_fail_op[1]);
+	 ds.ds0.bf_stencil_pass_depth_pass_op =
+	    intel_translate_stencil_op(key->stencil_pass_depth_pass_op[1]);
+	 ds.ds1.bf_stencil_write_mask = key->stencil_write_mask[1];
+	 ds.ds1.bf_stencil_test_mask = key->stencil_test_mask[1];
+      }
+
+      /* Not really sure about this:
+       */
+      if (key->stencil_write_mask[0] ||
+	  (key->stencil_two_side && key->stencil_write_mask[1]))
+	 ds.ds0.stencil_write_enable = 1;
+   }
+
+   /* _NEW_DEPTH */
+   if (key->depth_test) {
+      ds.ds2.depth_test_enable = 1;
+      ds.ds2.depth_test_func = intel_translate_compare_func(key->depth_func);
+      ds.ds2.depth_write_enable = key->depth_write;
+   }
+
+   bo = brw_upload_cache(&brw->cache, BRW_DEPTH_STENCIL_STATE,
+			 key, sizeof(*key),
+			 NULL, 0,
+			 &ds, sizeof(ds));
+
+   return bo;
+}
+
+static void
+prepare_depth_stencil_state(struct brw_context *brw)
+{
+   struct brw_depth_stencil_state_key key;
+
+   depth_stencil_state_populate_key(brw, &key);
+
+   dri_bo_unreference(brw->cc.depth_stencil_state_bo);
+   brw->cc.depth_stencil_state_bo = brw_search_cache(&brw->cache,
+						     BRW_DEPTH_STENCIL_STATE,
+						     &key, sizeof(key),
+						     NULL, 0,
+						     NULL);
+
+   if (brw->cc.depth_stencil_state_bo == NULL)
+      brw->cc.depth_stencil_state_bo =
+	 depth_stencil_state_create_from_key(brw, &key);
+}
+
+const struct brw_tracked_state gen6_depth_stencil_state = {
+   .dirty = {
+      .mesa = _NEW_DEPTH | _NEW_STENCIL,
+      .brw = 0,
+      .cache = 0,
+   },
+   .prepare = prepare_depth_stencil_state,
+};
-- 
cgit v1.2.3


From ba882d7827e5526e99c9d5c453d56c5e029c7476 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 16 Nov 2009 14:50:23 -0800
Subject: i965: Add untested Sandybridge passthrough VS setup.

---
 src/mesa/drivers/dri/i965/Makefile           |  3 +-
 src/mesa/drivers/dri/i965/brw_defines.h      | 23 ++++++++-
 src/mesa/drivers/dri/i965/brw_state.h        |  1 +
 src/mesa/drivers/dri/i965/brw_state_upload.c |  3 +-
 src/mesa/drivers/dri/i965/gen6_vs_state.c    | 75 ++++++++++++++++++++++++++++
 5 files changed, 101 insertions(+), 4 deletions(-)
 create mode 100644 src/mesa/drivers/dri/i965/gen6_vs_state.c

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index 7ce794d3aa..d21c921db3 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -86,7 +86,8 @@ DRIVER_SOURCES = \
 	brw_wm_state.c \
 	brw_wm_surface_state.c \
 	gen6_cc.c \
-	gen6_depthstencil.c
+	gen6_depthstencil.c \
+	gen6_vs_state.c
 
 C_SOURCES = \
 	$(COMMON_SOURCES) \
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 5d3b0a8b7a..7a7bcc4e79 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -807,10 +807,29 @@
 # define BRW_VE1_COMPONENT_3_SHIFT	16
 # define BRW_VE1_DST_OFFSET_SHIFT	0
 
-#define CMD_3D_CC_STATE_POINTERS      0x780e /* GEN6+ */
 #define CMD_INDEX_BUFFER              0x780a
-#define CMD_VF_STATISTICS_965         0x780b
+#define CMD_VF_STATISTICS_965          0x780b
 #define CMD_VF_STATISTICS_GM45        0x680b
+#define CMD_3D_CC_STATE_POINTERS      0x780e /* GEN6+ */
+
+#define CMD_3D_VS_STATE		      0x7810 /* GEN6+ */
+# define GEN6_VS_SPF_MODE				(1 << 31)
+# define GEN6_VS_VECTOR_MASK_ENABLE			(1 << 30)
+# define GEN6_VS_SAMPLER_COUNT_SHIFT			27
+# define GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT	18
+# define GEN6_VS_DISPATCH_START_GRF_SHIFT		20
+# define GEN6_VS_URB_READ_LENGTH_SHIFT			11
+# define GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT		0
+# define GEN6_VS_MAX_THREADS_SHIFT			25
+# define GEN6_VS_STATISTICS_ENABLE			(1 << 10)
+# define GEN6_VS_CACHE_DISABLE				(1 << 1)
+# define GEN6_VS_ENABLE					(1 << 0)
+
+#define CMD_3D_CONSTANT_VS_STATE	      0x7815 /* GEN6+ */
+# define GEN6_VS_BUFFER_3_ENABLE			(1 << 15)
+# define GEN6_VS_BUFFER_2_ENABLE			(1 << 14)
+# define GEN6_VS_BUFFER_1_ENABLE			(1 << 13)
+# define GEN6_VS_BUFFER_0_ENABLE			(1 << 12)
 
 #define CMD_DRAW_RECT                 0x7900
 #define CMD_BLEND_CONSTANT_COLOR      0x7901
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 5112cd8016..5066fe151b 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -95,6 +95,7 @@ const struct brw_tracked_state gen6_blend_state;
 const struct brw_tracked_state gen6_cc_state_pointers;
 const struct brw_tracked_state gen6_color_calc_state;
 const struct brw_tracked_state gen6_depth_stencil_state;
+const struct brw_tracked_state gen6_vs_state;
 
 /**
  * Use same key for WM and VS surfaces.
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index ed9e18f33c..b4b086dec4 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -132,13 +132,14 @@ const struct brw_tracked_state *gen6_atoms[] =
    &brw_vs_surfaces,		/* must do before unit */
    &brw_wm_constant_surface,	/* must do before wm surfaces/bind bo */
    &brw_wm_surfaces,		/* must do before samplers and unit */
+
+   &gen6_vs_state,
 #if 0
    &brw_wm_samplers,
 
    &brw_wm_unit,
    &brw_sf_vp,
    &brw_sf_unit,
-   &brw_vs_unit,		/* always required, enabled or not */
    &brw_clip_unit,
    &brw_gs_unit,
 
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
new file mode 100644
index 0000000000..4caabf32b0
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright © 2009 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Eric Anholt <eric@anholt.net>
+ *
+ */
+
+#include "brw_context.h"
+#include "brw_state.h"
+#include "brw_defines.h"
+#include "brw_util.h"
+#include "main/macros.h"
+#include "main/enums.h"
+#include "intel_batchbuffer.h"
+
+static void
+upload_vs_state(struct brw_context *brw)
+{
+   struct intel_context *intel = &brw->intel;
+
+   BEGIN_BATCH(6);
+   OUT_BATCH(CMD_3D_VS_STATE << 16 | (6 - 2));
+   OUT_BATCH(0); /* prog_bo */
+   /* OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); */
+   OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) |
+	     (brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
+   OUT_BATCH(0); /* scratch space base offset */
+   OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
+	     (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
+	     (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
+   OUT_BATCH((0 << GEN6_VS_MAX_THREADS_SHIFT) |
+	     GEN6_VS_STATISTICS_ENABLE);
+   ADVANCE_BATCH();
+
+   /* Disable all the constant buffers. */
+   BEGIN_BATCH(5);
+   OUT_BATCH(CMD_3D_CONSTANT_VS_STATE | (5 - 2));
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   ADVANCE_BATCH();
+}
+
+const struct brw_tracked_state gen6_vs_state = {
+   .dirty = {
+      .mesa  = _NEW_TRANSFORM,
+      .brw   = (BRW_NEW_CURBE_OFFSETS |
+                BRW_NEW_NR_VS_SURFACES |
+		BRW_NEW_URB_FENCE |
+		BRW_NEW_CONTEXT),
+      .cache = CACHE_NEW_VS_PROG
+   },
+   .emit = upload_vs_state,
+};
-- 
cgit v1.2.3


From 520b64ddfb4c2efa742bc2217fef96fdec5eea9b Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 26 Nov 2009 22:03:43 -0800
Subject: i965: Add untested passthrough GS setup.

---
 src/mesa/drivers/dri/i965/Makefile           |  1 +
 src/mesa/drivers/dri/i965/brw_defines.h      | 29 +++++++++--
 src/mesa/drivers/dri/i965/brw_state.h        |  1 +
 src/mesa/drivers/dri/i965/brw_state_upload.c |  2 +-
 src/mesa/drivers/dri/i965/gen6_gs_state.c    | 74 ++++++++++++++++++++++++++++
 5 files changed, 102 insertions(+), 5 deletions(-)
 create mode 100644 src/mesa/drivers/dri/i965/gen6_gs_state.c

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index d21c921db3..fb7ee096d9 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -87,6 +87,7 @@ DRIVER_SOURCES = \
 	brw_wm_surface_state.c \
 	gen6_cc.c \
 	gen6_depthstencil.c \
+	gen6_gs_state.c \
 	gen6_vs_state.c
 
 C_SOURCES = \
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 7a7bcc4e79..7ba1c77ebe 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -813,11 +813,13 @@
 #define CMD_3D_CC_STATE_POINTERS      0x780e /* GEN6+ */
 
 #define CMD_3D_VS_STATE		      0x7810 /* GEN6+ */
+/* DW2 */
 # define GEN6_VS_SPF_MODE				(1 << 31)
 # define GEN6_VS_VECTOR_MASK_ENABLE			(1 << 30)
 # define GEN6_VS_SAMPLER_COUNT_SHIFT			27
 # define GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT	18
 # define GEN6_VS_DISPATCH_START_GRF_SHIFT		20
+/* DW4 */
 # define GEN6_VS_URB_READ_LENGTH_SHIFT			11
 # define GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT		0
 # define GEN6_VS_MAX_THREADS_SHIFT			25
@@ -825,11 +827,30 @@
 # define GEN6_VS_CACHE_DISABLE				(1 << 1)
 # define GEN6_VS_ENABLE					(1 << 0)
 
+#define CMD_3D_GS_STATE		      0x7811 /* GEN6+ */
+/* DW2 */
+# define GEN6_GS_SPF_MODE				(1 << 31)
+# define GEN6_GS_VECTOR_MASK_ENABLE			(1 << 30)
+# define GEN6_GS_SAMPLER_COUNT_SHIFT			27
+# define GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT	18
+# define GEN6_GS_DISPATCH_START_GRF_SHIFT		20
+/* DW4 */
+# define GEN6_GS_URB_READ_LENGTH_SHIFT			11
+# define GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT		0
+/* DW5 */
+# define GEN6_GS_MAX_THREADS_SHIFT			25
+# define GEN6_GS_STATISTICS_ENABLE			(1 << 10)
+# define GEN6_GS_SO_STATISTICS_ENABLE			(1 << 9)
+# define GEN6_GS_RENDERING_ENABLE			(1 << 8)
+/* DW6 */
+# define GEN6_GS_ENABLE					(1 << 15)
+
 #define CMD_3D_CONSTANT_VS_STATE	      0x7815 /* GEN6+ */
-# define GEN6_VS_BUFFER_3_ENABLE			(1 << 15)
-# define GEN6_VS_BUFFER_2_ENABLE			(1 << 14)
-# define GEN6_VS_BUFFER_1_ENABLE			(1 << 13)
-# define GEN6_VS_BUFFER_0_ENABLE			(1 << 12)
+#define CMD_3D_CONSTANT_GS_STATE	      0x7816 /* GEN6+ */
+# define GEN6_CONSTANT_BUFFER_3_ENABLE			(1 << 15)
+# define GEN6_CONSTANT_BUFFER_2_ENABLE			(1 << 14)
+# define GEN6_CONSTANT_BUFFER_1_ENABLE			(1 << 13)
+# define GEN6_CONSTANT_BUFFER_0_ENABLE			(1 << 12)
 
 #define CMD_DRAW_RECT                 0x7900
 #define CMD_BLEND_CONSTANT_COLOR      0x7901
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 5066fe151b..c4d1f2556c 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -95,6 +95,7 @@ const struct brw_tracked_state gen6_blend_state;
 const struct brw_tracked_state gen6_cc_state_pointers;
 const struct brw_tracked_state gen6_color_calc_state;
 const struct brw_tracked_state gen6_depth_stencil_state;
+const struct brw_tracked_state gen6_gs_state;
 const struct brw_tracked_state gen6_vs_state;
 
 /**
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index b4b086dec4..dd797c42dd 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -134,6 +134,7 @@ const struct brw_tracked_state *gen6_atoms[] =
    &brw_wm_surfaces,		/* must do before samplers and unit */
 
    &gen6_vs_state,
+   &gen6_gs_state,
 #if 0
    &brw_wm_samplers,
 
@@ -141,7 +142,6 @@ const struct brw_tracked_state *gen6_atoms[] =
    &brw_sf_vp,
    &brw_sf_unit,
    &brw_clip_unit,
-   &brw_gs_unit,
 
    /* Command packets:
     */
diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c
new file mode 100644
index 0000000000..3a16bd368c
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright © 2009 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Eric Anholt <eric@anholt.net>
+ *
+ */
+
+#include "brw_context.h"
+#include "brw_state.h"
+#include "brw_defines.h"
+#include "brw_util.h"
+#include "main/macros.h"
+#include "main/enums.h"
+#include "intel_batchbuffer.h"
+
+static void
+upload_gs_state(struct brw_context *brw)
+{
+   struct intel_context *intel = &brw->intel;
+
+   BEGIN_BATCH(6);
+   OUT_BATCH(CMD_3D_GS_STATE << 16 | (6 - 2));
+   OUT_BATCH(0); /* prog_bo */
+   /* OUT_RELOC(brw->gs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); */
+   OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) |
+	     (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
+   OUT_BATCH(0); /* scratch space base offset */
+   OUT_BATCH((1 << GEN6_GS_DISPATCH_START_GRF_SHIFT) |
+	     (brw->gs.prog_data->urb_read_length << GEN6_GS_URB_READ_LENGTH_SHIFT) |
+	     (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT));
+   OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) |
+	     GEN6_GS_STATISTICS_ENABLE);
+   ADVANCE_BATCH();
+
+   /* Disable all the constant buffers. */
+   BEGIN_BATCH(5);
+   OUT_BATCH(CMD_3D_CONSTANT_GS_STATE << 16 | (5 - 2));
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   ADVANCE_BATCH();
+}
+
+const struct brw_tracked_state gen6_gs_state = {
+   .dirty = {
+      .mesa  = _NEW_TRANSFORM,
+      .brw   = (BRW_NEW_CURBE_OFFSETS |
+		BRW_NEW_URB_FENCE |
+		BRW_NEW_CONTEXT),
+      .cache = CACHE_NEW_GS_PROG
+   },
+   .emit = upload_gs_state,
+};
-- 
cgit v1.2.3


From f58fbcf7618bcc6ef9da8e8939100b14ea4d584b Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 29 Jan 2010 11:12:18 -0800
Subject: i965: Add untested REJECT_ALL clip state.

---
 src/mesa/drivers/dri/i965/Makefile           |  1 +
 src/mesa/drivers/dri/i965/brw_defines.h      | 21 ++++++++
 src/mesa/drivers/dri/i965/brw_state.h        |  1 +
 src/mesa/drivers/dri/i965/brw_state_upload.c |  3 +-
 src/mesa/drivers/dri/i965/gen6_clip_state.c  | 76 ++++++++++++++++++++++++++++
 5 files changed, 100 insertions(+), 2 deletions(-)
 create mode 100644 src/mesa/drivers/dri/i965/gen6_clip_state.c

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index fb7ee096d9..3bf14e8a77 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -86,6 +86,7 @@ DRIVER_SOURCES = \
 	brw_wm_state.c \
 	brw_wm_surface_state.c \
 	gen6_cc.c \
+	gen6_clip_state.c \
 	gen6_depthstencil.c \
 	gen6_gs_state.c \
 	gen6_vs_state.c
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 7ba1c77ebe..52960da682 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -845,6 +845,27 @@
 /* DW6 */
 # define GEN6_GS_ENABLE					(1 << 15)
 
+#define CMD_3D_CLIP_STATE		      0x7812 /* GEN6+ */
+/* DW1 */
+# define GEN6_CLIP_STATISTICS_ENABLE			(1 << 10)
+/* DW2 */
+# define GEN6_CLIP_ENABLE				(1 << 31)
+# define GEN6_CLIP_API_OGL				(1 << 30)
+# define GEN6_CLIP_XY_TEST				(1 << 28)
+# define GEN6_CLIP_Z_TEST				(1 << 27)
+# define GEN6_CLIP_GB_TEST				(1 << 26)
+# define GEN6_CLIP_MODE_NORMAL				(0 << 13)
+# define GEN6_CLIP_MODE_REJECT_ALL			(3 << 13)
+# define GEN6_CLIP_MODE_ACCEPT_ALL			(4 << 13)
+# define GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE		(1 << 9)
+# define GEN6_CLIP_BARYCENTRIC_ENABLE			(1 << 8)
+# define GEN6_CLIP_TRI_PROVOKE_SHIFT			4
+# define GEN6_CLIP_LINE_PROVOKE_SHIFT			2
+# define GEN6_CLIP_TRIFAN_PROVOKE_SHIFT			0
+/* DW3 */
+# define GEN6_CLIP_MIN_POINT_WIDTH_SHIFT		17
+# define GEN6_CLIP_MAX_POINT_WIDTH_SHIFT		6
+
 #define CMD_3D_CONSTANT_VS_STATE	      0x7815 /* GEN6+ */
 #define CMD_3D_CONSTANT_GS_STATE	      0x7816 /* GEN6+ */
 # define GEN6_CONSTANT_BUFFER_3_ENABLE			(1 << 15)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index c4d1f2556c..596a9cd3a0 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -93,6 +93,7 @@ const struct brw_tracked_state brw_index_buffer;
 const struct brw_tracked_state gen6_binding_table_pointers;
 const struct brw_tracked_state gen6_blend_state;
 const struct brw_tracked_state gen6_cc_state_pointers;
+const struct brw_tracked_state gen6_clip_state;
 const struct brw_tracked_state gen6_color_calc_state;
 const struct brw_tracked_state gen6_depth_stencil_state;
 const struct brw_tracked_state gen6_gs_state;
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index dd797c42dd..9f5d789e1e 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -110,7 +110,6 @@ const struct brw_tracked_state *gen6_atoms[] =
    &brw_wm_input_sizes,
    &brw_vs_prog,
    &brw_gs_prog,
-   &brw_clip_prog,
    &brw_sf_prog,
    &brw_wm_prog,
 
@@ -135,13 +134,13 @@ const struct brw_tracked_state *gen6_atoms[] =
 
    &gen6_vs_state,
    &gen6_gs_state,
+   &gen6_clip_state,
 #if 0
    &brw_wm_samplers,
 
    &brw_wm_unit,
    &brw_sf_vp,
    &brw_sf_unit,
-   &brw_clip_unit,
 
    /* Command packets:
     */
diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c b/src/mesa/drivers/dri/i965/gen6_clip_state.c
new file mode 100644
index 0000000000..f34e5f32cc
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright © 2009 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Eric Anholt <eric@anholt.net>
+ *
+ */
+
+#include "brw_context.h"
+#include "brw_state.h"
+#include "brw_defines.h"
+#include "brw_util.h"
+#include "main/macros.h"
+#include "main/enums.h"
+#include "intel_batchbuffer.h"
+
+static void
+upload_clip_state(struct brw_context *brw)
+{
+   struct intel_context *intel = &brw->intel;
+   GLcontext *ctx = &intel->ctx;
+   uint32_t depth_clamp = 0;
+   uint32_t provoking;
+
+   if (!ctx->Transform.DepthClamp)
+      depth_clamp = GEN6_CLIP_Z_TEST;
+
+   if (ctx->Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION) {
+      provoking = 0;
+   } else {
+      provoking =
+	 (2 << GEN6_CLIP_TRI_PROVOKE_SHIFT) |
+	 (2 << GEN6_CLIP_TRIFAN_PROVOKE_SHIFT) |
+	 (1 << GEN6_CLIP_LINE_PROVOKE_SHIFT);
+   }
+
+   BEGIN_BATCH(4);
+   OUT_BATCH(CMD_3D_CLIP_STATE << 16 | (4 - 2));
+   OUT_BATCH(0);
+   OUT_BATCH(GEN6_CLIP_ENABLE |
+	     GEN6_CLIP_API_OGL |
+	     GEN6_CLIP_MODE_REJECT_ALL | /* XXX: debug: get VS working */
+	     GEN6_CLIP_XY_TEST |
+	     depth_clamp |
+	     provoking);
+   OUT_BATCH(0);
+   ADVANCE_BATCH();
+}
+
+const struct brw_tracked_state gen6_clip_state = {
+   .dirty = {
+      .mesa  = _NEW_TRANSFORM,
+      .brw   = BRW_NEW_CONTEXT,
+      .cache = 0
+   },
+   .emit = upload_clip_state,
+};
-- 
cgit v1.2.3


From 98f9666f04eed9ae873fdea20c4c4b9db6cead84 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 3 Dec 2009 15:04:37 -0800
Subject: i965: Get vp-tri batchbuffers running (no rendering).

---
 src/mesa/drivers/dri/i965/brw_state_upload.c |  2 +-
 src/mesa/drivers/dri/i965/gen6_gs_state.c    | 40 +++++++++++++++++++---------
 src/mesa/drivers/dri/i965/gen6_vs_state.c    |  3 +--
 3 files changed, 29 insertions(+), 16 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 9f5d789e1e..f5446ed73b 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -106,10 +106,10 @@ const struct brw_tracked_state *gen6_atoms[] =
 {
    &brw_check_fallback,
 
-#if 0
    &brw_wm_input_sizes,
    &brw_vs_prog,
    &brw_gs_prog,
+#if 0
    &brw_sf_prog,
    &brw_wm_prog,
 
diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c
index 3a16bd368c..31da0dc088 100644
--- a/src/mesa/drivers/dri/i965/gen6_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c
@@ -38,19 +38,33 @@ upload_gs_state(struct brw_context *brw)
 {
    struct intel_context *intel = &brw->intel;
 
-   BEGIN_BATCH(6);
-   OUT_BATCH(CMD_3D_GS_STATE << 16 | (6 - 2));
-   OUT_BATCH(0); /* prog_bo */
-   /* OUT_RELOC(brw->gs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); */
-   OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) |
-	     (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
-   OUT_BATCH(0); /* scratch space base offset */
-   OUT_BATCH((1 << GEN6_GS_DISPATCH_START_GRF_SHIFT) |
-	     (brw->gs.prog_data->urb_read_length << GEN6_GS_URB_READ_LENGTH_SHIFT) |
-	     (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT));
-   OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) |
-	     GEN6_GS_STATISTICS_ENABLE);
-   ADVANCE_BATCH();
+   if (brw->gs.prog_bo) {
+      BEGIN_BATCH(6);
+      OUT_BATCH(CMD_3D_GS_STATE << 16 | (6 - 2));
+      OUT_RELOC(brw->gs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+      OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) |
+		(0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
+      OUT_BATCH(0); /* scratch space base offset */
+      OUT_BATCH((1 << GEN6_GS_DISPATCH_START_GRF_SHIFT) |
+		(brw->gs.prog_data->urb_read_length << GEN6_GS_URB_READ_LENGTH_SHIFT) |
+		(0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT));
+      OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) |
+		GEN6_GS_STATISTICS_ENABLE);
+      ADVANCE_BATCH();
+   } else {
+      BEGIN_BATCH(6);
+      OUT_BATCH(CMD_3D_GS_STATE << 16 | (6 - 2));
+      OUT_BATCH(0); /* prog_bo */
+      OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) |
+		(0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
+      OUT_BATCH(0); /* scratch space base offset */
+      OUT_BATCH((1 << GEN6_GS_DISPATCH_START_GRF_SHIFT) |
+		(0 << GEN6_GS_URB_READ_LENGTH_SHIFT) |
+		(0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT));
+      OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) |
+		GEN6_GS_STATISTICS_ENABLE);
+      ADVANCE_BATCH();
+   }
 
    /* Disable all the constant buffers. */
    BEGIN_BATCH(5);
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 4caabf32b0..d82319afa7 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -40,8 +40,7 @@ upload_vs_state(struct brw_context *brw)
 
    BEGIN_BATCH(6);
    OUT_BATCH(CMD_3D_VS_STATE << 16 | (6 - 2));
-   OUT_BATCH(0); /* prog_bo */
-   /* OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); */
+   OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
    OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) |
 	     (brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
    OUT_BATCH(0); /* scratch space base offset */
-- 
cgit v1.2.3


From eda1b50aa10031aeb07071f59fed93304b2fe2ca Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 3 Dec 2009 15:06:08 -0800
Subject: i965: Try turning on the VS.

---
 src/mesa/drivers/dri/i965/gen6_vs_state.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index d82319afa7..098a1d0b57 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -46,7 +46,8 @@ upload_vs_state(struct brw_context *brw)
    OUT_BATCH(0); /* scratch space base offset */
    OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
 	     (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
-	     (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
+	     (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT) |
+	     GEN6_VS_ENABLE);
    OUT_BATCH((0 << GEN6_VS_MAX_THREADS_SHIFT) |
 	     GEN6_VS_STATISTICS_ENABLE);
    ADVANCE_BATCH();
-- 
cgit v1.2.3


From 8485e100b81d5cf44cde7af0c7feb79a32bf3dd0 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 3 Dec 2009 15:20:06 -0800
Subject: i965: Try uploading SNB VS constants.

---
 src/mesa/drivers/dri/i965/gen6_vs_state.c | 61 ++++++++++++++++++++++++++-----
 1 file changed, 52 insertions(+), 9 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 098a1d0b57..d33b2b4d7d 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -31,12 +31,20 @@
 #include "brw_util.h"
 #include "main/macros.h"
 #include "main/enums.h"
+#include "shader/prog_parameter.h"
+#include "shader/prog_statevars.h"
 #include "intel_batchbuffer.h"
 
 static void
 upload_vs_state(struct brw_context *brw)
 {
    struct intel_context *intel = &brw->intel;
+   GLcontext *ctx = &intel->ctx;
+   const struct brw_vertex_program *vp =
+      brw_vertex_program_const(brw->vertex_program);
+   unsigned int nr_params = vp->program.Base.Parameters->NumParameters;
+   drm_intel_bo *constant_bo;
+   int i;
 
    BEGIN_BATCH(6);
    OUT_BATCH(CMD_3D_VS_STATE << 16 | (6 - 2));
@@ -52,19 +60,54 @@ upload_vs_state(struct brw_context *brw)
 	     GEN6_VS_STATISTICS_ENABLE);
    ADVANCE_BATCH();
 
-   /* Disable all the constant buffers. */
-   BEGIN_BATCH(5);
-   OUT_BATCH(CMD_3D_CONSTANT_VS_STATE | (5 - 2));
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
+   if (vp->use_const_buffer || nr_params == 0) {
+      /* Disable the push constant buffers. */
+      BEGIN_BATCH(5);
+      OUT_BATCH(CMD_3D_CONSTANT_VS_STATE << 16 | (5 - 2));
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      ADVANCE_BATCH();
+   } else {
+      if (brw->vertex_program->IsNVProgram)
+	 _mesa_load_tracked_matrices(ctx);
+
+      /* Updates the ParamaterValues[i] pointers for all parameters of the
+       * basic type of PROGRAM_STATE_VAR.
+       */
+      _mesa_load_state_parameters(ctx, vp->program.Base.Parameters);
+
+      constant_bo = drm_intel_bo_alloc(intel->bufmgr, "VS constant_bo",
+				       nr_params * 4 * sizeof(float),
+				       4096);
+      intel_bo_map_gtt_preferred(intel, constant_bo, GL_TRUE);
+      for (i = 0; i < nr_params; i++) {
+	 memcpy((char *)constant_bo->virtual + i * 4 * sizeof(float),
+		vp->program.Base.Parameters->ParameterValues[i],
+		4 * sizeof(float));
+      }
+      intel_bo_unmap_gtt_preferred(intel, constant_bo);
+
+      BEGIN_BATCH(5);
+      OUT_BATCH(CMD_3D_CONSTANT_VS_STATE << 16 |
+		GEN6_CONSTANT_BUFFER_0_ENABLE |
+		(5 - 2));
+      OUT_RELOC(constant_bo,
+		I915_GEM_DOMAIN_RENDER, 0, /* XXX: bad domain */
+		ALIGN(nr_params, 2) / 2 - 1);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      ADVANCE_BATCH();
+
+      drm_intel_bo_unreference(constant_bo);
+   }
 }
 
 const struct brw_tracked_state gen6_vs_state = {
    .dirty = {
-      .mesa  = _NEW_TRANSFORM,
+      .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
       .brw   = (BRW_NEW_CURBE_OFFSETS |
                 BRW_NEW_NR_VS_SURFACES |
 		BRW_NEW_URB_FENCE |
-- 
cgit v1.2.3


From 0da50fa67009535577dc84dde21672db5ec45134 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 3 Dec 2009 15:44:29 -0800
Subject: i965: Try sending prims down the pipeline.

Now things catch on fire.
---
 src/mesa/drivers/dri/i965/brw_draw.c | 4 ----
 1 file changed, 4 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 106cd31632..e348d4686b 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -124,10 +124,6 @@ static void brw_emit_prim(struct brw_context *brw,
    struct brw_3d_primitive prim_packet;
    struct intel_context *intel = &brw->intel;
 
-   /* Last thing to hook up in the pipeline when brw_state_upload.c is done. */
-   if (IS_GEN6(intel->intelScreen->deviceID))
-      return;
-
    if (INTEL_DEBUG & DEBUG_PRIMS)
       printf("PRIM: %s %d %d\n", _mesa_lookup_enum_by_nr(prim->mode), 
 		   prim->start, prim->count);
-- 
cgit v1.2.3


From c9dc6d425e645f2988118ff51cabe167a0cd3971 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 3 Dec 2009 17:08:32 -0800
Subject: i965: Set up the SNB URB.

even with vs disabled, still doesn't work.
---
 src/mesa/drivers/dri/i965/Makefile           |  1 +
 src/mesa/drivers/dri/i965/brw_context.h      |  3 +-
 src/mesa/drivers/dri/i965/brw_defines.h      |  6 +++
 src/mesa/drivers/dri/i965/brw_state.h        |  1 +
 src/mesa/drivers/dri/i965/brw_state_upload.c |  2 +-
 src/mesa/drivers/dri/i965/gen6_urb.c         | 81 ++++++++++++++++++++++++++++
 6 files changed, 92 insertions(+), 2 deletions(-)
 create mode 100644 src/mesa/drivers/dri/i965/gen6_urb.c

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index 3bf14e8a77..35093f014b 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -89,6 +89,7 @@ DRIVER_SOURCES = \
 	gen6_clip_state.c \
 	gen6_depthstencil.c \
 	gen6_gs_state.c \
+	gen6_urb.c \
 	gen6_vs_state.c
 
 C_SOURCES = \
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index ea89d4f6fa..c4b68ca05b 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -544,7 +544,8 @@ struct brw_context
       GLuint nr_sf_entries;
       GLuint nr_cs_entries;
 
-/*       GLuint vs_size; */
+      /* gen6 */
+      GLuint vs_size;
 /*       GLuint gs_size; */
 /*       GLuint clip_size; */
 /*       GLuint sf_size; */
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 52960da682..08eb2b2d91 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -812,6 +812,12 @@
 #define CMD_VF_STATISTICS_GM45        0x680b
 #define CMD_3D_CC_STATE_POINTERS      0x780e /* GEN6+ */
 
+#define CMD_URB					0x7805 /* GEN6+ */
+# define GEN6_URB_VS_SIZE_SHIFT				16
+# define GEN6_URB_VS_ENTRIES_SHIFT			0
+# define GEN6_URB_GS_SIZE_SHIFT				8
+# define GEN6_URB_GS_ENTRIES_SHIFT			0
+
 #define CMD_3D_VS_STATE		      0x7810 /* GEN6+ */
 /* DW2 */
 # define GEN6_VS_SPF_MODE				(1 << 31)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 596a9cd3a0..11489d477c 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -97,6 +97,7 @@ const struct brw_tracked_state gen6_clip_state;
 const struct brw_tracked_state gen6_color_calc_state;
 const struct brw_tracked_state gen6_depth_stencil_state;
 const struct brw_tracked_state gen6_gs_state;
+const struct brw_tracked_state gen6_urb;
 const struct brw_tracked_state gen6_vs_state;
 
 /**
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index f5446ed73b..fc30e60087 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -118,11 +118,11 @@ const struct brw_tracked_state *gen6_atoms[] =
     * layout.
     */
    &brw_curbe_offsets,
-   &brw_recalculate_urb_fence,
 
    &brw_cc_vp,
 
 #endif
+   &gen6_urb,
    &gen6_blend_state,		/* must do before cc unit */
    &gen6_color_calc_state,	/* must do before cc unit */
    &gen6_depth_stencil_state,	/* must do before cc unit */
diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c
new file mode 100644
index 0000000000..dea0aa7100
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen6_urb.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright © 2009 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Eric Anholt <eric@anholt.net>
+ *
+ */
+
+#include "main/macros.h"
+#include "intel_batchbuffer.h"
+#include "brw_context.h"
+#include "brw_state.h"
+#include "brw_defines.h"
+
+static void
+prepare_urb( struct brw_context *brw )
+{
+   brw->urb.nr_vs_entries = 24;
+   if (brw->gs.prog_bo)
+      brw->urb.nr_gs_entries = 4;
+   else
+      brw->urb.nr_gs_entries = 0;
+   /* CACHE_NEW_VS_PROG */
+   brw->urb.vs_size = MIN2(brw->vs.prog_data->urb_entry_size, 1);
+
+   /* Check that the number of URB rows (8 floats each) allocated is less
+    * than the URB space.
+    */
+   assert((brw->urb.nr_vs_entries +
+	   brw->urb.nr_gs_entries) * brw->urb.vs_size * 8 < 64 * 1024);
+}
+
+static void
+upload_urb(struct brw_context *brw)
+{
+   struct intel_context *intel = &brw->intel;
+
+   assert(brw->urb.nr_vs_entries % 4 == 0);
+   assert(brw->urb.nr_gs_entries % 4 == 0);
+   /* GS requirement */
+   assert(!brw->gs.prog_bo || brw->urb.vs_size < 5);
+
+   intel_batchbuffer_emit_mi_flush(intel->batch);
+
+   BEGIN_BATCH(3);
+   OUT_BATCH(CMD_URB << 16 | (3 - 2));
+   OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_VS_SIZE_SHIFT) |
+	     ((brw->urb.nr_vs_entries) << GEN6_URB_VS_SIZE_SHIFT));
+   OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) |
+	     ((brw->urb.nr_gs_entries) << GEN6_URB_GS_SIZE_SHIFT));
+   ADVANCE_BATCH();
+}
+
+const struct brw_tracked_state gen6_urb = {
+   .dirty = {
+      .mesa = 0,
+      .brw = BRW_NEW_CONTEXT,
+      .cache = CACHE_NEW_VS_PROG,
+   },
+   .prepare = prepare_urb,
+   .emit = upload_urb,
+};
-- 
cgit v1.2.3


From ff3997904ab988824e744fdbecde6eb79d9bf40f Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 3 Dec 2009 16:53:07 -0800
Subject: i965: Reconnect the index/vertex setup.

---
 src/mesa/drivers/dri/i965/brw_defines.h      |  5 ++++
 src/mesa/drivers/dri/i965/brw_draw_upload.c  | 42 +++++++++++++++++++++-------
 src/mesa/drivers/dri/i965/brw_state_upload.c |  5 ++--
 src/mesa/drivers/dri/i965/gen6_vs_state.c    |  3 +-
 4 files changed, 40 insertions(+), 15 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 08eb2b2d91..e280c2ee4e 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -784,14 +784,19 @@
 
 #define CMD_VERTEX_BUFFER             0x7808
 # define BRW_VB0_INDEX_SHIFT		27
+# define GEN6_VB0_INDEX_SHIFT		26
 # define BRW_VB0_ACCESS_VERTEXDATA	(0 << 26)
 # define BRW_VB0_ACCESS_INSTANCEDATA	(1 << 26)
+# define GEN6_VB0_ACCESS_VERTEXDATA	(0 << 20)
+# define GEN6_VB0_ACCESS_INSTANCEDATA	(1 << 20)
 # define BRW_VB0_PITCH_SHIFT		0
 
 #define CMD_VERTEX_ELEMENT            0x7809
 # define BRW_VE0_INDEX_SHIFT		27
+# define GEN6_VE0_INDEX_SHIFT		26
 # define BRW_VE0_FORMAT_SHIFT		16
 # define BRW_VE0_VALID			(1 << 26)
+# define GEN6_VE0_VALID			(1 << 25)
 # define BRW_VE0_SRC_OFFSET_SHIFT	0
 # define BRW_VE1_COMPONENT_NOSTORE	0
 # define BRW_VE1_COMPONENT_STORE_SRC	1
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 106454de4a..e6bfc567af 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -503,10 +503,17 @@ static void brw_emit_vertices(struct brw_context *brw)
    if (brw->vb.nr_enabled == 0) {
       BEGIN_BATCH(3);
       OUT_BATCH((CMD_VERTEX_ELEMENT << 16) | 1);
-      OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT) |
-		BRW_VE0_VALID |
-		(BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
-		(0 << BRW_VE0_SRC_OFFSET_SHIFT));
+      if (IS_GEN6(intel->intelScreen->deviceID)) {
+	 OUT_BATCH((0 << GEN6_VE0_INDEX_SHIFT) |
+		   GEN6_VE0_VALID |
+		   (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
+		   (0 << BRW_VE0_SRC_OFFSET_SHIFT));
+      } else {
+	 OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT) |
+		   BRW_VE0_VALID |
+		   (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
+		   (0 << BRW_VE0_SRC_OFFSET_SHIFT));
+      }
       OUT_BATCH((BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_0_SHIFT) |
 		(BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
 		(BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
@@ -527,9 +534,17 @@ static void brw_emit_vertices(struct brw_context *brw)
 
    for (i = 0; i < brw->vb.nr_enabled; i++) {
       struct brw_vertex_element *input = brw->vb.enabled[i];
+      uint32_t dw0;
 
-      OUT_BATCH((i << BRW_VB0_INDEX_SHIFT) |
-		BRW_VB0_ACCESS_VERTEXDATA |
+      if (IS_GEN6(intel->intelScreen->deviceID)) {
+	 dw0 = GEN6_VB0_ACCESS_VERTEXDATA |
+	    (i << GEN6_VB0_INDEX_SHIFT);
+      } else {
+	 dw0 = BRW_VB0_ACCESS_VERTEXDATA |
+	    (i << BRW_VB0_INDEX_SHIFT);
+      }
+
+      OUT_BATCH(dw0 |
 		(input->stride << BRW_VB0_PITCH_SHIFT));
       OUT_RELOC(input->bo,
 		I915_GEM_DOMAIN_VERTEX, 0,
@@ -565,10 +580,17 @@ static void brw_emit_vertices(struct brw_context *brw)
 	 break;
       }
 
-      OUT_BATCH((i << BRW_VE0_INDEX_SHIFT) |
-		BRW_VE0_VALID |
-		(format << BRW_VE0_FORMAT_SHIFT) |
-		(0 << BRW_VE0_SRC_OFFSET_SHIFT));
+      if (IS_GEN6(intel->intelScreen->deviceID)) {
+	 OUT_BATCH((i << GEN6_VE0_INDEX_SHIFT) |
+		   GEN6_VE0_VALID |
+		   (format << BRW_VE0_FORMAT_SHIFT) |
+		   (0 << BRW_VE0_SRC_OFFSET_SHIFT));
+      } else {
+	 OUT_BATCH((i << BRW_VE0_INDEX_SHIFT) |
+		   BRW_VE0_VALID |
+		   (format << BRW_VE0_FORMAT_SHIFT) |
+		   (0 << BRW_VE0_SRC_OFFSET_SHIFT));
+      }
 
       if (intel->is_ironlake)
           OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index fc30e60087..30386ef316 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -163,12 +163,11 @@ const struct brw_tracked_state *gen6_atoms[] =
    &brw_psp_urb_cbs,
 
    &brw_drawing_rect,
+#endif
+
    &brw_indices,
    &brw_index_buffer,
    &brw_vertices,
-
-   &brw_constant_buffer
-#endif
 };
 
 void brw_init_state( struct brw_context *brw )
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index d33b2b4d7d..0202871399 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -54,8 +54,7 @@ upload_vs_state(struct brw_context *brw)
    OUT_BATCH(0); /* scratch space base offset */
    OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
 	     (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
-	     (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT) |
-	     GEN6_VS_ENABLE);
+	     (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
    OUT_BATCH((0 << GEN6_VS_MAX_THREADS_SHIFT) |
 	     GEN6_VS_STATISTICS_ENABLE);
    ADVANCE_BATCH();
-- 
cgit v1.2.3


From d512aa3d6d9948f5c294110fdae7a24aaf37051f Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 3 Dec 2009 18:31:32 -0800
Subject: i965: Fix some defines of gen6 regs from docs comparison.

---
 src/mesa/drivers/dri/i965/brw_defines.h | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index e280c2ee4e..f727bf53f7 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -829,10 +829,11 @@
 # define GEN6_VS_VECTOR_MASK_ENABLE			(1 << 30)
 # define GEN6_VS_SAMPLER_COUNT_SHIFT			27
 # define GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT	18
-# define GEN6_VS_DISPATCH_START_GRF_SHIFT		20
 /* DW4 */
+# define GEN6_VS_DISPATCH_START_GRF_SHIFT		20
 # define GEN6_VS_URB_READ_LENGTH_SHIFT			11
-# define GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT		0
+# define GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT		4
+/* DW6 */
 # define GEN6_VS_MAX_THREADS_SHIFT			25
 # define GEN6_VS_STATISTICS_ENABLE			(1 << 10)
 # define GEN6_VS_CACHE_DISABLE				(1 << 1)
@@ -844,10 +845,10 @@
 # define GEN6_GS_VECTOR_MASK_ENABLE			(1 << 30)
 # define GEN6_GS_SAMPLER_COUNT_SHIFT			27
 # define GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT	18
-# define GEN6_GS_DISPATCH_START_GRF_SHIFT		20
 /* DW4 */
 # define GEN6_GS_URB_READ_LENGTH_SHIFT			11
-# define GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT		0
+# define GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT		4
+# define GEN6_GS_DISPATCH_START_GRF_SHIFT		0
 /* DW5 */
 # define GEN6_GS_MAX_THREADS_SHIFT			25
 # define GEN6_GS_STATISTICS_ENABLE			(1 << 10)
-- 
cgit v1.2.3


From d971375bc1872cb2d95a710e3d62f5b037fbe7f7 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 29 Jan 2010 10:42:17 -0800
Subject: i965: Giant pile of flushing to track down SNB bringup issues.

This should go away before we push the code.
---
 src/mesa/drivers/dri/i965/gen6_cc.c         | 2 ++
 src/mesa/drivers/dri/i965/gen6_clip_state.c | 2 ++
 src/mesa/drivers/dri/i965/gen6_gs_state.c   | 2 ++
 src/mesa/drivers/dri/i965/gen6_urb.c        | 2 ++
 src/mesa/drivers/dri/i965/gen6_vs_state.c   | 4 ++++
 5 files changed, 12 insertions(+)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c
index b1b6dc7db3..ba1e3abe83 100644
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -273,6 +273,8 @@ static void upload_cc_state_pointers(struct brw_context *brw)
    OUT_RELOC(brw->cc.blend_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
    OUT_RELOC(brw->cc.depth_stencil_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
    ADVANCE_BATCH();
+
+   intel_batchbuffer_emit_mi_flush(intel->batch);
 }
 
 
diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c b/src/mesa/drivers/dri/i965/gen6_clip_state.c
index f34e5f32cc..5ddfa9aad2 100644
--- a/src/mesa/drivers/dri/i965/gen6_clip_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c
@@ -64,6 +64,8 @@ upload_clip_state(struct brw_context *brw)
 	     provoking);
    OUT_BATCH(0);
    ADVANCE_BATCH();
+
+   intel_batchbuffer_emit_mi_flush(intel->batch);
 }
 
 const struct brw_tracked_state gen6_clip_state = {
diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c
index 31da0dc088..47702f7f30 100644
--- a/src/mesa/drivers/dri/i965/gen6_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c
@@ -74,6 +74,8 @@ upload_gs_state(struct brw_context *brw)
    OUT_BATCH(0);
    OUT_BATCH(0);
    ADVANCE_BATCH();
+
+   intel_batchbuffer_emit_mi_flush(intel->batch);
 }
 
 const struct brw_tracked_state gen6_gs_state = {
diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c
index dea0aa7100..55f7ac7727 100644
--- a/src/mesa/drivers/dri/i965/gen6_urb.c
+++ b/src/mesa/drivers/dri/i965/gen6_urb.c
@@ -68,6 +68,8 @@ upload_urb(struct brw_context *brw)
    OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) |
 	     ((brw->urb.nr_gs_entries) << GEN6_URB_GS_SIZE_SHIFT));
    ADVANCE_BATCH();
+
+   intel_batchbuffer_emit_mi_flush(intel->batch);
 }
 
 const struct brw_tracked_state gen6_urb = {
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 0202871399..ba00e4e1fb 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -59,6 +59,8 @@ upload_vs_state(struct brw_context *brw)
 	     GEN6_VS_STATISTICS_ENABLE);
    ADVANCE_BATCH();
 
+   intel_batchbuffer_emit_mi_flush(intel->batch);
+
    if (vp->use_const_buffer || nr_params == 0) {
       /* Disable the push constant buffers. */
       BEGIN_BATCH(5);
@@ -102,6 +104,8 @@ upload_vs_state(struct brw_context *brw)
 
       drm_intel_bo_unreference(constant_bo);
    }
+
+   intel_batchbuffer_emit_mi_flush(intel->batch);
 }
 
 const struct brw_tracked_state gen6_vs_state = {
-- 
cgit v1.2.3


From 2c3d6f8e3e714451c436d5496167747e9311c3df Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 3 Dec 2009 18:52:35 -0800
Subject: i965: Free gen6 state BOs on context destroy.

---
 src/mesa/drivers/dri/i965/brw_vtbl.c | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index 0b0be02dd2..27a2a3e8a7 100644
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -102,6 +102,9 @@ static void brw_destroy_context( struct intel_context *intel )
    dri_bo_release(&brw->cc.prog_bo);
    dri_bo_release(&brw->cc.state_bo);
    dri_bo_release(&brw->cc.vp_bo);
+   dri_bo_release(&brw->cc.blend_state_bo);
+   dri_bo_release(&brw->cc.depth_stencil_state_bo);
+   dri_bo_release(&brw->cc.color_calc_state_bo);
 }
 
 
-- 
cgit v1.2.3


From a38096aa94ef62dba73792f1680098059b697662 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 14 Dec 2009 14:11:14 -0800
Subject: i965: Set the state base address on Sandybridge.

---
 src/mesa/drivers/dri/i965/brw_misc_state.c   | 15 ++++++++++++++-
 src/mesa/drivers/dri/i965/brw_state_upload.c |  3 +++
 2 files changed, 17 insertions(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 7d9e793ff2..c36a287d81 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -559,7 +559,20 @@ static void upload_state_base_address( struct brw_context *brw )
    /* Output the structure (brw_state_base_address) directly to the
     * batchbuffer, so we can emit relocations inline.
     */
-   if (intel->is_ironlake) {
+   if (intel->gen >= 6) {
+       BEGIN_BATCH(10);
+       OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
+       OUT_BATCH(1); /* General state base address */
+       OUT_BATCH(1); /* Surface state base address */
+       OUT_BATCH(1); /* Dynamic state base address */
+       OUT_BATCH(1); /* Indirect object base address */
+       OUT_BATCH(1); /* Instruction base address */
+       OUT_BATCH(1); /* General state upper bound */
+       OUT_BATCH(1); /* Dynamic state upper bound */
+       OUT_BATCH(1); /* Indirect object upper bound */
+       OUT_BATCH(1); /* Instruction access upper bound */
+       ADVANCE_BATCH();
+   } else if (intel->is_ironlake) {
        BEGIN_BATCH(8);
        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
        OUT_BATCH(1); /* General state base address */
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 30386ef316..30a36956e2 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -145,8 +145,11 @@ const struct brw_tracked_state *gen6_atoms[] =
    /* Command packets:
     */
    &brw_invarient_state,
+#endif
+
    &brw_state_base_address,
 
+#if 0
    &brw_binding_table_pointers,
    &brw_blend_constant_color,
 #endif
-- 
cgit v1.2.3


From 93fcfc8369cc3fa42f6ba577c26474464f21e6ad Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 14 Dec 2009 14:17:00 -0800
Subject: i965: Fix up the VF stats packet header.

---
 src/mesa/drivers/dri/i965/brw_context.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 2ca29b7ae1..3614149966 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -150,7 +150,7 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis,
       MIN2(ctx->Const.FragmentProgram.MaxNativeParameters,
 	   ctx->Const.FragmentProgram.MaxEnvParams);
 
-   if (intel->is_ironlake || intel->is_g4x) {
+   if (intel->is_ironlake || intel->is_g4x || intel->gen >= 6) {
       brw->CMD_VF_STATISTICS = CMD_VF_STATISTICS_GM45;
       brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_GM45;
       brw->has_surface_tile_offset = GL_TRUE;
-- 
cgit v1.2.3


From 64e0c586a74553b2941f18feb199d8cddb192102 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 17 Dec 2009 08:20:32 -0800
Subject: i965: Add Sandybridge scissor state.

---
 src/mesa/drivers/dri/i965/Makefile             |   1 +
 src/mesa/drivers/dri/i965/brw_context.h        |   2 +-
 src/mesa/drivers/dri/i965/brw_defines.h        |   2 +
 src/mesa/drivers/dri/i965/brw_state.h          |   1 +
 src/mesa/drivers/dri/i965/brw_state_upload.c   |   3 +
 src/mesa/drivers/dri/i965/brw_structs.h        |   5 ++
 src/mesa/drivers/dri/i965/gen6_scissor_state.c | 108 +++++++++++++++++++++++++
 7 files changed, 121 insertions(+), 1 deletion(-)
 create mode 100644 src/mesa/drivers/dri/i965/gen6_scissor_state.c

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index 35093f014b..9426ffc0da 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -89,6 +89,7 @@ DRIVER_SOURCES = \
 	gen6_clip_state.c \
 	gen6_depthstencil.c \
 	gen6_gs_state.c \
+	gen6_scissor_state.c \
 	gen6_urb.c \
 	gen6_vs_state.c
 
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index c4b68ca05b..d6fc37e4d8 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -293,7 +293,7 @@ enum brw_cache_id {
    BRW_WM_UNIT,
    BRW_SF_PROG,
    BRW_SF_VP,
-   BRW_SF_UNIT,
+   BRW_SF_UNIT, /* scissor state on gen6 */
    BRW_VS_UNIT,
    BRW_VS_PROG,
    BRW_GS_UNIT,
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index f727bf53f7..b11ec7b165 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -823,6 +823,8 @@
 # define GEN6_URB_GS_SIZE_SHIFT				8
 # define GEN6_URB_GS_ENTRIES_SHIFT			0
 
+#define CMD_3D_SCISSOR_STATE_POINTERS		0x780f /* GEN6+ */
+
 #define CMD_3D_VS_STATE		      0x7810 /* GEN6+ */
 /* DW2 */
 # define GEN6_VS_SPF_MODE				(1 << 31)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 11489d477c..25e261dd15 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -97,6 +97,7 @@ const struct brw_tracked_state gen6_clip_state;
 const struct brw_tracked_state gen6_color_calc_state;
 const struct brw_tracked_state gen6_depth_stencil_state;
 const struct brw_tracked_state gen6_gs_state;
+const struct brw_tracked_state gen6_scissor_state;
 const struct brw_tracked_state gen6_urb;
 const struct brw_tracked_state gen6_vs_state;
 
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 30a36956e2..d36cc3aa1b 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -139,6 +139,9 @@ const struct brw_tracked_state *gen6_atoms[] =
    &brw_wm_samplers,
 
    &brw_wm_unit,
+#endif
+   &gen6_scissor_state,
+#if 0
    &brw_sf_vp,
    &brw_sf_unit,
 
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 10c0c62202..87d5c06cdc 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -909,6 +909,11 @@ struct brw_sf_unit_state
 
 };
 
+struct gen6_scissor_state
+{
+   GLuint ymin, xmin;
+   GLuint ymax, xmax;
+};
 
 struct brw_gs_unit_state
 {
diff --git a/src/mesa/drivers/dri/i965/gen6_scissor_state.c b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
new file mode 100644
index 0000000000..2d36f0056d
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright © 2009 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Eric Anholt <eric@anholt.net>
+ *
+ */
+
+#include "brw_context.h"
+#include "brw_state.h"
+#include "brw_defines.h"
+#include "brw_util.h"
+#include "intel_batchbuffer.h"
+#include "main/macros.h"
+#include "main/enums.h"
+
+static void
+prepare_scissor_state(struct brw_context *brw)
+{
+   GLcontext *ctx = &brw->intel.ctx;
+   const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
+   struct gen6_scissor_state scissor;
+
+   /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
+
+   /* The scissor only needs to handle the intersection of drawable and
+    * scissor rect.  Clipping to the boundaries of static shared buffers
+    * for front/back/depth is covered by looping over cliprects in brw_draw.c.
+    *
+    * Note that the hardware's coordinates are inclusive, while Mesa's min is
+    * inclusive but max is exclusive.
+    */
+   if (render_to_fbo) {
+      /* texmemory: Y=0=bottom */
+      scissor.xmin = ctx->DrawBuffer->_Xmin;
+      scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
+      scissor.ymin = ctx->DrawBuffer->_Ymin;
+      scissor.ymax = ctx->DrawBuffer->_Ymax - 1;
+   }
+   else {
+      /* memory: Y=0=top */
+      scissor.xmin = ctx->DrawBuffer->_Xmin;
+      scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
+      scissor.ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
+      scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
+   }
+
+   drm_intel_bo_unreference(brw->sf.state_bo);
+   brw->sf.state_bo = brw_cache_data(&brw->cache, BRW_SF_UNIT,
+				     &scissor, sizeof(scissor),
+				     NULL, 0);
+}
+
+const struct brw_tracked_state gen6_scissor_state = {
+   .dirty = {
+      .mesa = _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT,
+      .brw = 0,
+      .cache = 0,
+   },
+   .prepare = prepare_scissor_state,
+};
+
+static void upload_scissor_state_pointers(struct brw_context *brw)
+{
+   struct intel_context *intel = &brw->intel;
+
+   BEGIN_BATCH(2);
+   OUT_BATCH(CMD_3D_SCISSOR_STATE_POINTERS << 16 | (2 - 2));
+   OUT_RELOC(brw->sf.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+   ADVANCE_BATCH();
+
+   intel_batchbuffer_emit_mi_flush(intel->batch);
+}
+
+
+static void prepare_scissor_state_pointers(struct brw_context *brw)
+{
+   brw_add_validated_bo(brw, brw->sf.state_bo);
+}
+
+const struct brw_tracked_state gen6_scissor_state_pointers = {
+   .dirty = {
+      .mesa = 0,
+      .brw = BRW_NEW_BATCH,
+      .cache = CACHE_NEW_SF_UNIT
+   },
+   .prepare = prepare_scissor_state_pointers,
+   .emit = upload_scissor_state_pointers,
+};
-- 
cgit v1.2.3


From c9065cd61fd43a507ae3100d7c0ab957672cab70 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 17 Dec 2009 08:23:37 -0800
Subject: i965: Enable DRAWING_RECTANGLE emit on Sandybridge.

---
 src/mesa/drivers/dri/i965/brw_state_upload.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index d36cc3aa1b..086f82c992 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -167,9 +167,9 @@ const struct brw_tracked_state *gen6_atoms[] =
    &brw_aa_line_parameters,
 
    &brw_psp_urb_cbs,
+#endif
 
    &brw_drawing_rect,
-#endif
 
    &brw_indices,
    &brw_index_buffer,
-- 
cgit v1.2.3


From 1ae0cb5f286bbba10e99c8e3bc1c55d2aeb38b59 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 17 Dec 2009 09:38:50 -0800
Subject: i965: Add Sandybridge viewport setup.

---
 src/mesa/drivers/dri/i965/Makefile              |   1 +
 src/mesa/drivers/dri/i965/brw_defines.h         |   5 +
 src/mesa/drivers/dri/i965/brw_state.h           |   4 +
 src/mesa/drivers/dri/i965/brw_state_upload.c    |   8 +-
 src/mesa/drivers/dri/i965/brw_structs.h         |   9 ++
 src/mesa/drivers/dri/i965/gen6_viewport_state.c | 175 ++++++++++++++++++++++++
 6 files changed, 200 insertions(+), 2 deletions(-)
 create mode 100644 src/mesa/drivers/dri/i965/gen6_viewport_state.c

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index 9426ffc0da..32eb3f8fcd 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -91,6 +91,7 @@ DRIVER_SOURCES = \
 	gen6_gs_state.c \
 	gen6_scissor_state.c \
 	gen6_urb.c \
+	gen6_viewport_state.c \
 	gen6_vs_state.c
 
 C_SOURCES = \
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index b11ec7b165..3201de601a 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -823,6 +823,11 @@
 # define GEN6_URB_GS_SIZE_SHIFT				8
 # define GEN6_URB_GS_ENTRIES_SHIFT			0
 
+#define CMD_VIEWPORT_STATE_POINTERS			0x780d /* GEN6+ */
+# define GEN6_CC_VIEWPORT_MODIFY			(1 << 12)
+# define GEN6_SF_VIEWPORT_MODIFY			(1 << 11)
+# define GEN6_CLIP_VIEWPORT_MODIFY			(1 << 10)
+
 #define CMD_3D_SCISSOR_STATE_POINTERS		0x780f /* GEN6+ */
 
 #define CMD_3D_VS_STATE		      0x7810 /* GEN6+ */
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 25e261dd15..7c5819fc1b 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -93,12 +93,16 @@ const struct brw_tracked_state brw_index_buffer;
 const struct brw_tracked_state gen6_binding_table_pointers;
 const struct brw_tracked_state gen6_blend_state;
 const struct brw_tracked_state gen6_cc_state_pointers;
+const struct brw_tracked_state gen6_cc_vp;
 const struct brw_tracked_state gen6_clip_state;
+const struct brw_tracked_state gen6_clip_vp;
 const struct brw_tracked_state gen6_color_calc_state;
 const struct brw_tracked_state gen6_depth_stencil_state;
 const struct brw_tracked_state gen6_gs_state;
 const struct brw_tracked_state gen6_scissor_state;
+const struct brw_tracked_state gen6_sf_vp;
 const struct brw_tracked_state gen6_urb;
+const struct brw_tracked_state gen6_viewport_state;
 const struct brw_tracked_state gen6_vs_state;
 
 /**
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 086f82c992..3e6c967f53 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -119,9 +119,13 @@ const struct brw_tracked_state *gen6_atoms[] =
     */
    &brw_curbe_offsets,
 
-   &brw_cc_vp,
 
 #endif
+   &gen6_clip_vp,
+   &gen6_sf_vp,
+   &gen6_cc_vp,
+   &gen6_viewport_state,	/* must do after *_vp stages */
+
    &gen6_urb,
    &gen6_blend_state,		/* must do before cc unit */
    &gen6_color_calc_state,	/* must do before cc unit */
@@ -141,8 +145,8 @@ const struct brw_tracked_state *gen6_atoms[] =
    &brw_wm_unit,
 #endif
    &gen6_scissor_state,
+
 #if 0
-   &brw_sf_vp,
    &brw_sf_unit,
 
    /* Command packets:
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 87d5c06cdc..3c2adfc87d 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -1144,6 +1144,15 @@ struct brw_sf_viewport
    } scissor;
 };
 
+struct gen6_sf_viewport {
+   GLfloat m00;
+   GLfloat m11;
+   GLfloat m22;
+   GLfloat m30;
+   GLfloat m31;
+   GLfloat m32;
+};
+
 /* Documented in the subsystem/shared-functions/sampler chapter...
  */
 struct brw_surface_state
diff --git a/src/mesa/drivers/dri/i965/gen6_viewport_state.c b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
new file mode 100644
index 0000000000..13d2fc1b42
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright © 2009 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Eric Anholt <eric@anholt.net>
+ *
+ */
+
+#include "brw_context.h"
+#include "brw_state.h"
+#include "brw_defines.h"
+#include "brw_util.h"
+#include "intel_batchbuffer.h"
+#include "main/macros.h"
+#include "main/enums.h"
+
+/* The clip VP defines the guardband region where expensive clipping is skipped
+ * and fragments are allowed to be generated and clipped out cheaply by the SF.
+ *
+ * By setting it to NDC bounds of [-1,1], we don't do GB clipping.  It's
+ * supposed to cause seams to become visible in apps due to shared edges taking
+ * different clip/no clip paths depending on whether the rest of the prim ends
+ * up in the guardband or not.
+ */
+static void
+prepare_clip_vp(struct brw_context *brw)
+{
+   struct brw_clipper_viewport vp;
+
+   vp.xmin = -1.0;
+   vp.xmax = 1.0;
+   vp.ymin = -1.0;
+   vp.ymax = 1.0;
+
+   drm_intel_bo_unreference(brw->clip.vp_bo);
+   brw->clip.vp_bo = brw_cache_data(&brw->cache, BRW_CLIP_VP,
+				    &vp, sizeof(vp),
+				    NULL, 0);
+}
+
+const struct brw_tracked_state gen6_clip_vp = {
+   .dirty = {
+      .mesa = _NEW_VIEWPORT, /* XXX: not really, but we need nonzero */
+      .brw = 0,
+      .cache = 0,
+   },
+   .prepare = prepare_clip_vp,
+};
+
+static void
+prepare_sf_vp(struct brw_context *brw)
+{
+   GLcontext *ctx = &brw->intel.ctx;
+   const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
+   struct brw_sf_viewport sfv;
+   GLfloat y_scale, y_bias;
+   const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
+   const GLfloat *v = ctx->Viewport._WindowMap.m;
+
+   memset(&sfv, 0, sizeof(sfv));
+
+   /* _NEW_BUFFERS */
+   if (render_to_fbo) {
+      y_scale = 1.0;
+      y_bias = 0;
+   } else {
+      y_scale = -1.0;
+      y_bias = ctx->DrawBuffer->Height;
+   }
+
+   /* _NEW_VIEWPORT */
+   sfv.viewport.m00 = v[MAT_SX];
+   sfv.viewport.m11 = v[MAT_SY] * y_scale;
+   sfv.viewport.m22 = v[MAT_SZ] * depth_scale;
+   sfv.viewport.m30 = v[MAT_TX];
+   sfv.viewport.m31 = v[MAT_TY] * y_scale + y_bias;
+   sfv.viewport.m32 = v[MAT_TZ] * depth_scale;
+
+   drm_intel_bo_unreference(brw->sf.vp_bo);
+   brw->sf.vp_bo = brw_cache_data(&brw->cache, BRW_SF_VP,
+				  &sfv, sizeof(sfv),
+				  NULL, 0);
+}
+
+const struct brw_tracked_state gen6_sf_vp = {
+   .dirty = {
+      .mesa = _NEW_VIEWPORT | _NEW_BUFFERS,
+      .brw = 0,
+      .cache = 0,
+   },
+   .prepare = prepare_sf_vp,
+};
+
+static void
+prepare_cc_vp(struct brw_context *brw)
+{
+   GLcontext *ctx = &brw->intel.ctx;
+   struct brw_cc_viewport ccv;
+
+   /* _NEW_TRANSOFORM */
+   if (ctx->Transform.DepthClamp) {
+      /* _NEW_VIEWPORT */
+      ccv.min_depth = MIN2(ctx->Viewport.Near, ctx->Viewport.Far);
+      ccv.max_depth = MAX2(ctx->Viewport.Near, ctx->Viewport.Far);
+   } else {
+      ccv.min_depth = 0.0;
+      ccv.max_depth = 1.0;
+   }
+
+   drm_intel_bo_unreference(brw->cc.vp_bo);
+   brw->cc.vp_bo = brw_cache_data(&brw->cache, BRW_CC_VP, &ccv, sizeof(ccv),
+				  NULL, 0);
+}
+
+const struct brw_tracked_state gen6_cc_vp = {
+   .dirty = {
+      .mesa = _NEW_VIEWPORT | _NEW_TRANSFORM,
+      .brw = 0,
+      .cache = 0,
+   },
+   .prepare = prepare_cc_vp,
+};
+
+static void prepare_viewport_state_pointers(struct brw_context *brw)
+{
+   brw_add_validated_bo(brw, brw->sf.state_bo);
+}
+
+static void upload_viewport_state_pointers(struct brw_context *brw)
+{
+   struct intel_context *intel = &brw->intel;
+
+   BEGIN_BATCH(4);
+   OUT_BATCH(CMD_VIEWPORT_STATE_POINTERS << 16 | (4 - 2) |
+	     GEN6_CC_VIEWPORT_MODIFY |
+	     GEN6_SF_VIEWPORT_MODIFY |
+	     GEN6_CLIP_VIEWPORT_MODIFY);
+   OUT_RELOC(brw->clip.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+   OUT_RELOC(brw->sf.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+   OUT_RELOC(brw->cc.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+   ADVANCE_BATCH();
+
+   intel_batchbuffer_emit_mi_flush(intel->batch);
+}
+
+const struct brw_tracked_state gen6_viewport_state = {
+   .dirty = {
+      .mesa = 0,
+      .brw = BRW_NEW_BATCH,
+      .cache = (CACHE_NEW_CLIP_VP |
+		CACHE_NEW_SF_VP |
+		CACHE_NEW_CC_VP)
+   },
+   .prepare = prepare_viewport_state_pointers,
+   .emit = upload_viewport_state_pointers,
+};
-- 
cgit v1.2.3


From 0fbc0b0c172060ce5dd946fe33a43d9194ab45d0 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 17 Dec 2009 09:47:53 -0800
Subject: i965: Enable clip stats.

---
 src/mesa/drivers/dri/i965/gen6_clip_state.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c b/src/mesa/drivers/dri/i965/gen6_clip_state.c
index 5ddfa9aad2..9fabd05341 100644
--- a/src/mesa/drivers/dri/i965/gen6_clip_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c
@@ -55,7 +55,7 @@ upload_clip_state(struct brw_context *brw)
 
    BEGIN_BATCH(4);
    OUT_BATCH(CMD_3D_CLIP_STATE << 16 | (4 - 2));
-   OUT_BATCH(0);
+   OUT_BATCH(GEN6_CLIP_STATISTICS_ENABLE);
    OUT_BATCH(GEN6_CLIP_ENABLE |
 	     GEN6_CLIP_API_OGL |
 	     GEN6_CLIP_MODE_REJECT_ALL | /* XXX: debug: get VS working */
-- 
cgit v1.2.3


From 305b72154f6b05360d64feca4725a2eaa8c48a6e Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 17 Dec 2009 14:51:42 -0800
Subject: i965: fix typo in SNB GS register defines

---
 src/mesa/drivers/dri/i965/brw_defines.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 3201de601a..c1f041939e 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -853,9 +853,9 @@
 # define GEN6_GS_SAMPLER_COUNT_SHIFT			27
 # define GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT	18
 /* DW4 */
+# define GEN6_GS_DISPATCH_START_GRF_SHIFT		20
 # define GEN6_GS_URB_READ_LENGTH_SHIFT			11
 # define GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT		4
-# define GEN6_GS_DISPATCH_START_GRF_SHIFT		0
 /* DW5 */
 # define GEN6_GS_MAX_THREADS_SHIFT			25
 # define GEN6_GS_STATISTICS_ENABLE			(1 << 10)
-- 
cgit v1.2.3


From a935cb2acafab199ac5ed4f2484af77be2af6363 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 17 Dec 2009 15:51:43 -0800
Subject: i965: fix typo in SNB VS defines comment

---
 src/mesa/drivers/dri/i965/brw_defines.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index c1f041939e..fcf02e9e3b 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -840,7 +840,7 @@
 # define GEN6_VS_DISPATCH_START_GRF_SHIFT		20
 # define GEN6_VS_URB_READ_LENGTH_SHIFT			11
 # define GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT		4
-/* DW6 */
+/* DW5 */
 # define GEN6_VS_MAX_THREADS_SHIFT			25
 # define GEN6_VS_STATISTICS_ENABLE			(1 << 10)
 # define GEN6_VS_CACHE_DISABLE				(1 << 1)
-- 
cgit v1.2.3


From da577ee8800b940fcf416716c13133cd43c3d035 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 17 Dec 2009 15:52:17 -0800
Subject: i965: Fix up Sandybridge GS reg definitions

---
 src/mesa/drivers/dri/i965/brw_defines.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index fcf02e9e3b..ae16fab566 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -853,9 +853,9 @@
 # define GEN6_GS_SAMPLER_COUNT_SHIFT			27
 # define GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT	18
 /* DW4 */
-# define GEN6_GS_DISPATCH_START_GRF_SHIFT		20
 # define GEN6_GS_URB_READ_LENGTH_SHIFT			11
 # define GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT		4
+# define GEN6_GS_DISPATCH_START_GRF_SHIFT		0
 /* DW5 */
 # define GEN6_GS_MAX_THREADS_SHIFT			25
 # define GEN6_GS_STATISTICS_ENABLE			(1 << 10)
-- 
cgit v1.2.3


From dd743fa36fa9303c2a2d0e7d3798fdc00ef43287 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 17 Dec 2009 18:41:18 -0800
Subject: i965: Fixup Sandybridge GS packet from doc updates.

---
 src/mesa/drivers/dri/i965/gen6_gs_state.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c
index 47702f7f30..761059c96a 100644
--- a/src/mesa/drivers/dri/i965/gen6_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c
@@ -39,8 +39,8 @@ upload_gs_state(struct brw_context *brw)
    struct intel_context *intel = &brw->intel;
 
    if (brw->gs.prog_bo) {
-      BEGIN_BATCH(6);
-      OUT_BATCH(CMD_3D_GS_STATE << 16 | (6 - 2));
+      BEGIN_BATCH(7);
+      OUT_BATCH(CMD_3D_GS_STATE << 16 | (7 - 2));
       OUT_RELOC(brw->gs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
       OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) |
 		(0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
@@ -50,10 +50,11 @@ upload_gs_state(struct brw_context *brw)
 		(0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT));
       OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) |
 		GEN6_GS_STATISTICS_ENABLE);
+      OUT_BATCH(GEN6_GS_ENABLE);
       ADVANCE_BATCH();
    } else {
-      BEGIN_BATCH(6);
-      OUT_BATCH(CMD_3D_GS_STATE << 16 | (6 - 2));
+      BEGIN_BATCH(7);
+      OUT_BATCH(CMD_3D_GS_STATE << 16 | (7 - 2));
       OUT_BATCH(0); /* prog_bo */
       OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) |
 		(0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
@@ -63,6 +64,7 @@ upload_gs_state(struct brw_context *brw)
 		(0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT));
       OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) |
 		GEN6_GS_STATISTICS_ENABLE);
+      OUT_BATCH(0);
       ADVANCE_BATCH();
    }
 
-- 
cgit v1.2.3


From 70be48dff6bb68c61285641e4d976bfd53e0f00c Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 29 Jan 2010 11:03:04 -0800
Subject: i965: Untested Sandybridge SF setup.

---
 src/mesa/drivers/dri/i965/Makefile             |   1 +
 src/mesa/drivers/dri/i965/brw_defines.h        |  70 ++++++++++++
 src/mesa/drivers/dri/i965/brw_state.h          |   1 +
 src/mesa/drivers/dri/i965/brw_state_upload.c   |   7 +-
 src/mesa/drivers/dri/i965/gen6_sf_state.c      | 149 +++++++++++++++++++++++++
 src/mesa/drivers/dri/i965/gen6_vs_state.c      |   3 +-
 src/mesa/drivers/dri/intel/intel_batchbuffer.h |  13 +++
 7 files changed, 238 insertions(+), 6 deletions(-)
 create mode 100644 src/mesa/drivers/dri/i965/gen6_sf_state.c

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index 32eb3f8fcd..d614fbb6a9 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -90,6 +90,7 @@ DRIVER_SOURCES = \
 	gen6_depthstencil.c \
 	gen6_gs_state.c \
 	gen6_scissor_state.c \
+	gen6_sf_state.c \
 	gen6_urb.c \
 	gen6_viewport_state.c \
 	gen6_vs_state.c
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index ae16fab566..f34575355e 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -885,6 +885,76 @@
 # define GEN6_CLIP_MIN_POINT_WIDTH_SHIFT		17
 # define GEN6_CLIP_MAX_POINT_WIDTH_SHIFT		6
 
+#define CMD_3D_SF_STATE				0x7813 /* GEN6+ */
+/* DW1 */
+# define GEN6_SF_NUM_OUTPUTS_SHIFT			22
+# define GEN6_SF_SWIZZLE_ENABLE				(1 << 21)
+# define GEN6_SF_POINT_SPRITE_LOWERLEFT			(1 << 20)
+# define GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT		11
+# define GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT		4
+/* DW2 */
+# define GEN6_SF_LEGACY_GLOBAL_DEPTH_BIAS		(1 << 11)
+# define GEN6_SF_STATISTICS_ENABLE			(1 << 10)
+# define GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID		(1 << 9)
+# define GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME		(1 << 8)
+# define GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT		(1 << 7)
+# define GEN6_SF_FRONT_SOLID				(0 << 5)
+# define GEN6_SF_FRONT_WIREFRAME			(1 << 5)
+# define GEN6_SF_FRONT_POINT				(2 << 5)
+# define GEN6_SF_BACK_SOLID				(0 << 3)
+# define GEN6_SF_BACK_WIREFRAME				(1 << 3)
+# define GEN6_SF_BACK_POINT				(2 << 3)
+# define GEN6_SF_VIEWPORT_TRANSFORM_ENABLE		(1 << 1)
+# define GEN6_SF_WINDING_CCW				(1 << 0)
+/* DW3 */
+# define GEN6_SF_LINE_AA_ENABLE				(1 << 31)
+# define GEN6_SF_CULL_BOTH				(0 << 29)
+# define GEN6_SF_CULL_NONE				(1 << 29)
+# define GEN6_SF_CULL_FRONT				(2 << 29)
+# define GEN6_SF_CULL_BACK				(3 << 29)
+# define GEN6_SF_LINE_WIDTH_SHIFT			18 /* U3.7 */
+# define GEN6_SF_LINE_END_CAP_WIDTH_0_5			(0 << 16)
+# define GEN6_SF_LINE_END_CAP_WIDTH_1_0			(1 << 16)
+# define GEN6_SF_LINE_END_CAP_WIDTH_2_0			(2 << 16)
+# define GEN6_SF_LINE_END_CAP_WIDTH_4_0			(3 << 16)
+# define GEN6_SF_SCISSOR_ENABLE				(1 << 11)
+# define GEN6_SF_MSRAST_OFF_PIXEL			(0 << 8)
+# define GEN6_SF_MSRAST_OFF_PATTERN			(1 << 8)
+# define GEN6_SF_MSRAST_ON_PIXEL			(2 << 8)
+# define GEN6_SF_MSRAST_ON_PATTERN			(3 << 8)
+/* DW4 */
+# define GEN6_SF_TRI_PROVOKE_SHIFT			29
+# define GEN6_SF_LINE_PROVOKE_SHIFT			27
+# define GEN6_SF_TRIFAN_PROVOKE_SHIFT			25
+# define GEN6_SF_LINE_AA_MODE_MANHATTAN			(0 << 14)
+# define GEN6_SF_LINE_AA_MODE_TRUE			(1 << 14)
+# define GEN6_SF_VERTEX_SUBPIXEL_8BITS			(0 << 12)
+# define GEN6_SF_VERTEX_SUBPIXEL_4BITS			(1 << 12)
+# define GEN6_SF_USE_STATE_POINT_WIDTH			(1 << 11)
+# define GEN6_SF_POINT_WIDTH_SHIFT			0 /* U8.3 */
+/* DW5: depth offset constant */
+/* DW6: depth offset scale */
+/* DW7: depth offset clamp */
+/* DW8 */
+# define ATTRIBUTE_1_OVERRIDE_W				(1 << 31)
+# define ATTRIBUTE_1_OVERRIDE_Z				(1 << 30)
+# define ATTRIBUTE_1_OVERRIDE_Y				(1 << 29)
+# define ATTRIBUTE_1_OVERRIDE_X				(1 << 28)
+# define ATTRIBUTE_1_CONST_SOURCE_SHIFT			25
+# define ATTRIBUTE_1_SWIZZLE_SHIFT			22
+# define ATTRIBUTE_1_SOURCE_SHIFT			16
+# define ATTRIBUTE_0_OVERRIDE_W				(1 << 15)
+# define ATTRIBUTE_0_OVERRIDE_Z				(1 << 14)
+# define ATTRIBUTE_0_OVERRIDE_Y				(1 << 13)
+# define ATTRIBUTE_0_OVERRIDE_X				(1 << 12)
+# define ATTRIBUTE_0_CONST_SOURCE_SHIFT			9
+# define ATTRIBUTE_0_SWIZZLE_SHIFT			6
+# define ATTRIBUTE_0_SOURCE_SHIFT			0
+/* DW16: Point sprite texture coordinate enables */
+/* DW17: Constant interpolation enables */
+/* DW18: attr 0-7 wrap shortest enables */
+/* DW19: attr 8-16 wrap shortest enables */
+
 #define CMD_3D_CONSTANT_VS_STATE	      0x7815 /* GEN6+ */
 #define CMD_3D_CONSTANT_GS_STATE	      0x7816 /* GEN6+ */
 # define GEN6_CONSTANT_BUFFER_3_ENABLE			(1 << 15)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 7c5819fc1b..f2579d7cdc 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -100,6 +100,7 @@ const struct brw_tracked_state gen6_color_calc_state;
 const struct brw_tracked_state gen6_depth_stencil_state;
 const struct brw_tracked_state gen6_gs_state;
 const struct brw_tracked_state gen6_scissor_state;
+const struct brw_tracked_state gen6_sf_state;
 const struct brw_tracked_state gen6_sf_vp;
 const struct brw_tracked_state gen6_urb;
 const struct brw_tracked_state gen6_viewport_state;
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 3e6c967f53..9874d725bb 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -110,7 +110,6 @@ const struct brw_tracked_state *gen6_atoms[] =
    &brw_vs_prog,
    &brw_gs_prog,
 #if 0
-   &brw_sf_prog,
    &brw_wm_prog,
 
    /* Once all the programs are done, we know how large urb entry
@@ -118,8 +117,6 @@ const struct brw_tracked_state *gen6_atoms[] =
     * layout.
     */
    &brw_curbe_offsets,
-
-
 #endif
    &gen6_clip_vp,
    &gen6_sf_vp,
@@ -144,11 +141,11 @@ const struct brw_tracked_state *gen6_atoms[] =
 
    &brw_wm_unit,
 #endif
+   &gen6_sf_state,
+
    &gen6_scissor_state,
 
 #if 0
-   &brw_sf_unit,
-
    /* Command packets:
     */
    &brw_invarient_state,
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c
new file mode 100644
index 0000000000..548cdb9fca
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -0,0 +1,149 @@
+/*
+ * Copyright © 2009 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Eric Anholt <eric@anholt.net>
+ *
+ */
+
+#include "brw_context.h"
+#include "brw_state.h"
+#include "brw_defines.h"
+#include "brw_util.h"
+#include "main/macros.h"
+#include "main/enums.h"
+#include "intel_batchbuffer.h"
+
+static void
+upload_sf_state(struct brw_context *brw)
+{
+   struct intel_context *intel = &brw->intel;
+   GLcontext *ctx = &intel->ctx;
+   /* CACHE_NEW_VS_PROG */
+   uint32_t num_inputs = brw_count_bits(brw->vs.prog_data->outputs_written);
+   /* This should probably be FS inputs read */
+   uint32_t num_outputs = brw_count_bits(brw->vs.prog_data->outputs_written);
+   uint32_t dw1, dw2, dw3, dw4;
+   int i;
+   /* _NEW_BUFFER */
+   GLboolean render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
+
+   dw1 =
+      num_outputs << GEN6_SF_NUM_OUTPUTS_SHIFT |
+      num_inputs << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT |
+      3 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT;
+   dw2 = GEN6_SF_VIEWPORT_TRANSFORM_ENABLE |
+      GEN6_SF_STATISTICS_ENABLE;
+   dw3 = 0;
+   dw4 = 0;
+
+   /* _NEW_POLYGON */
+   if ((ctx->Polygon.FrontFace == GL_CCW) ^ render_to_fbo)
+      dw2 |= GEN6_SF_WINDING_CCW;
+
+   /* _NEW_SCISSOR */
+   if (ctx->Scissor.Enabled)
+      dw3 |= GEN6_SF_SCISSOR_ENABLE;
+
+   /* _NEW_POLYGON */
+   if (ctx->Polygon.CullFlag) {
+      switch (ctx->Polygon.CullFaceMode) {
+      case GL_FRONT:
+	 dw3 |= GEN6_SF_CULL_BOTH;
+	 break;
+      case GL_BACK:
+	 dw3 |= GEN6_SF_CULL_BACK;
+	 break;
+      case GL_FRONT_AND_BACK:
+	 dw3 |= GEN6_SF_CULL_BOTH;
+	 break;
+      default:
+	 assert(0);
+	 break;
+      }
+   } else {
+      dw3 |= GEN6_SF_CULL_NONE;
+   }
+
+   /* _NEW_LINE */
+   dw3 |= U_FIXED(CLAMP(ctx->Line.Width, 0.0, 7.99), 7) <<
+      GEN6_SF_LINE_WIDTH_SHIFT;
+   if (ctx->Line.SmoothFlag) {
+      dw3 |= GEN6_SF_LINE_AA_ENABLE;
+      dw3 |= GEN6_SF_LINE_AA_MODE_TRUE;
+      dw3 |= GEN6_SF_LINE_END_CAP_WIDTH_1_0;
+   }
+
+   /* _NEW_POINT */
+   if (ctx->Point._Attenuated)
+      dw4 |= GEN6_SF_USE_STATE_POINT_WIDTH;
+
+   dw4 |= U_FIXED(CLAMP(ctx->Point.Size, 0.125, 225.875), 3) <<
+      GEN6_SF_POINT_WIDTH_SHIFT;
+   if (render_to_fbo)
+      dw1 |= GEN6_SF_POINT_SPRITE_LOWERLEFT;
+
+   /* _NEW_LIGHT */
+   if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
+      dw4 |=
+	 (2 << GEN6_SF_TRI_PROVOKE_SHIFT) |
+	 (2 << GEN6_SF_TRIFAN_PROVOKE_SHIFT) |
+	 (1 << GEN6_SF_LINE_PROVOKE_SHIFT);
+   } else {
+      dw4 |=
+	 (1 << GEN6_SF_TRIFAN_PROVOKE_SHIFT);
+   }
+
+   BEGIN_BATCH(20);
+   OUT_BATCH(CMD_3D_SF_STATE << 16 | (20 - 2));
+   OUT_BATCH(dw1);
+   OUT_BATCH(dw2);
+   OUT_BATCH(dw3);
+   OUT_BATCH(dw4);
+   OUT_BATCH_F(ctx->Polygon.OffsetUnits * 2); /* constant.  copied from gen4 */
+   OUT_BATCH_F(ctx->Polygon.OffsetFactor); /* scale */
+   OUT_BATCH_F(0.0); /* XXX: global depth offset clamp */
+   for (i = 0; i < 8; i++) {
+      /* attribute overrides */
+      OUT_BATCH(0);
+   }
+   OUT_BATCH(0); /* point sprite texcoord bitmask */
+   OUT_BATCH(0); /* constant interp bitmask */
+   OUT_BATCH(0); /* wrapshortest enables 0-7 */
+   OUT_BATCH(0); /* wrapshortest enables 8-15 */
+   ADVANCE_BATCH();
+
+   intel_batchbuffer_emit_mi_flush(intel->batch);
+}
+
+const struct brw_tracked_state gen6_sf_state = {
+   .dirty = {
+      .mesa  = (_NEW_LIGHT |
+		_NEW_POLYGON |
+		_NEW_LINE |
+		_NEW_SCISSOR |
+		_NEW_BUFFERS),
+      .brw   = BRW_NEW_CONTEXT,
+      .cache = CACHE_NEW_VS_PROG
+   },
+   .emit = upload_sf_state,
+};
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index ba00e4e1fb..0299dc6768 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -56,7 +56,8 @@ upload_vs_state(struct brw_context *brw)
 	     (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
 	     (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
    OUT_BATCH((0 << GEN6_VS_MAX_THREADS_SHIFT) |
-	     GEN6_VS_STATISTICS_ENABLE);
+	     GEN6_VS_STATISTICS_ENABLE|
+	     GEN6_VS_ENABLE);
    ADVANCE_BATCH();
 
    intel_batchbuffer_emit_mi_flush(intel->batch);
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
index b052b724d8..4daada205a 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
@@ -96,6 +96,17 @@ intel_batchbuffer_require_space(struct intel_batchbuffer *batch,
       intel_batchbuffer_flush(batch);
 }
 
+static INLINE uint32_t float_as_int(float f)
+{
+   union {
+      float f;
+      uint32_t d;
+   } fi;
+
+   fi.f = f;
+   return fi.d;
+}
+
 /* Here are the crusty old macros, to be removed:
  */
 #define BATCH_LOCALS
@@ -108,6 +119,8 @@ intel_batchbuffer_require_space(struct intel_batchbuffer *batch,
 } while (0)
 
 #define OUT_BATCH(d) intel_batchbuffer_emit_dword(intel->batch, d)
+#define OUT_BATCH_F(f) intel_batchbuffer_emit_dword(intel->batch,	\
+						    float_as_int(f))
 
 #define OUT_RELOC(buf, read_domains, write_domain, delta) do {		\
    assert((unsigned) (delta) < buf->size);				\
-- 
cgit v1.2.3


From 737fac7ba220e4a2d66a8e2100ae0af620c274df Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 21 Dec 2009 11:22:14 -0800
Subject: i965: Hook up remaining Sandybridge state packets besides WM.

---
 src/mesa/drivers/dri/i965/brw_misc_state.c   |  4 +++-
 src/mesa/drivers/dri/i965/brw_state_upload.c | 30 ++++++----------------------
 2 files changed, 9 insertions(+), 25 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index c36a287d81..b4e7dd547f 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -485,6 +485,8 @@ const struct brw_tracked_state brw_line_stipple = {
 
 static void upload_invarient_state( struct brw_context *brw )
 {
+   struct intel_context *intel = &brw->intel;
+
    {
       /* 0x61040000  Pipeline Select */
       /*     PipelineSelect            : 0 */
@@ -496,7 +498,7 @@ static void upload_invarient_state( struct brw_context *brw )
       BRW_BATCH_STRUCT(brw, &ps);
    }
 
-   {
+   if (intel->gen < 6) {
       struct brw_global_depth_offset_clamp gdo;
       memset(&gdo, 0, sizeof(gdo));
 
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 9874d725bb..6f214b037e 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -109,18 +109,13 @@ const struct brw_tracked_state *gen6_atoms[] =
    &brw_wm_input_sizes,
    &brw_vs_prog,
    &brw_gs_prog,
-#if 0
    &brw_wm_prog,
 
-   /* Once all the programs are done, we know how large urb entry
-    * sizes need to be and can decide if we need to change the urb
-    * layout.
-    */
-   &brw_curbe_offsets,
-#endif
    &gen6_clip_vp,
    &gen6_sf_vp,
    &gen6_cc_vp,
+
+   /* Command packets: */
    &gen6_viewport_state,	/* must do after *_vp stages */
 
    &gen6_urb,
@@ -133,43 +128,30 @@ const struct brw_tracked_state *gen6_atoms[] =
    &brw_wm_constant_surface,	/* must do before wm surfaces/bind bo */
    &brw_wm_surfaces,		/* must do before samplers and unit */
 
+   &brw_wm_samplers,
+
    &gen6_vs_state,
    &gen6_gs_state,
    &gen6_clip_state,
-#if 0
-   &brw_wm_samplers,
-
-   &brw_wm_unit,
-#endif
    &gen6_sf_state,
+   /* &gen6_wm_state, */
 
    &gen6_scissor_state,
 
-#if 0
-   /* Command packets:
-    */
    &brw_invarient_state,
-#endif
 
    &brw_state_base_address,
 
-#if 0
-   &brw_binding_table_pointers,
-   &brw_blend_constant_color,
-#endif
+   &gen6_binding_table_pointers,
 
    &brw_depthbuffer,
 
-#if 0
    &brw_polygon_stipple,
    &brw_polygon_stipple_offset,
 
    &brw_line_stipple,
    &brw_aa_line_parameters,
 
-   &brw_psp_urb_cbs,
-#endif
-
    &brw_drawing_rect,
 
    &brw_indices,
-- 
cgit v1.2.3


From ab8c37fe18e0367e8718774198a0d0086fde0cf9 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 21 Dec 2009 11:48:32 -0800
Subject: i965: Untested Sandybridge WM packets.

---
 src/mesa/drivers/dri/i965/Makefile           |   3 +-
 src/mesa/drivers/dri/i965/brw_defines.h      |  62 ++++++++++
 src/mesa/drivers/dri/i965/brw_state.h        |   1 +
 src/mesa/drivers/dri/i965/brw_state_upload.c |   2 +-
 src/mesa/drivers/dri/i965/gen6_wm_state.c    | 162 +++++++++++++++++++++++++++
 5 files changed, 228 insertions(+), 2 deletions(-)
 create mode 100644 src/mesa/drivers/dri/i965/gen6_wm_state.c

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index d614fbb6a9..f84e87e7e6 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -93,7 +93,8 @@ DRIVER_SOURCES = \
 	gen6_sf_state.c \
 	gen6_urb.c \
 	gen6_viewport_state.c \
-	gen6_vs_state.c
+	gen6_vs_state.c \
+	gen6_wm_state.c
 
 C_SOURCES = \
 	$(COMMON_SOURCES) \
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index f34575355e..be32a8fa82 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -955,8 +955,70 @@
 /* DW18: attr 0-7 wrap shortest enables */
 /* DW19: attr 8-16 wrap shortest enables */
 
+#define CMD_3D_WM_STATE		      0x7814 /* GEN6+ */
+/* DW1: kernel pointer */
+/* DW2 */
+# define GEN6_WM_SPF_MODE				(1 << 31)
+# define GEN6_WM_VECTOR_MASK_ENABLE			(1 << 30)
+# define GEN6_WM_SAMPLER_COUNT_SHIFT			27
+# define GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT	18
+/* DW3: scratch space */
+/* DW4 */
+# define GEN6_WM_STATISTICS_ENABLE			(1 << 31)
+# define GEN6_WM_DEPTH_CLEAR				(1 << 30)
+# define GEN6_WM_DEPTH_RESOLVE				(1 << 28)
+# define GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE		(1 << 27)
+# define GEN6_WM_DISPATCH_START_GRF_SHIFT_0		16
+# define GEN6_WM_DISPATCH_START_GRF_SHIFT_1		8
+# define GEN6_WM_DISPATCH_START_GRF_SHIFT_2		0
+/* DW5 */
+# define GEN6_WM_MAX_THREADS_SHIFT			25
+# define GEN6_WM_KILL_ENABLE				(1 << 22)
+# define GEN6_WM_COMPUTED_DEPTH				(1 << 21)
+# define GEN6_WM_USES_SOURCE_DEPTH			(1 << 20)
+# define GEN6_WM_DISPATCH_ENABLE			(1 << 19)
+# define GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5		(0 << 16)
+# define GEN6_WM_LINE_END_CAP_AA_WIDTH_1_0		(1 << 16)
+# define GEN6_WM_LINE_END_CAP_AA_WIDTH_2_0		(2 << 16)
+# define GEN6_WM_LINE_END_CAP_AA_WIDTH_4_0		(3 << 16)
+# define GEN6_WM_LINE_AA_WIDTH_0_5			(0 << 14)
+# define GEN6_WM_LINE_AA_WIDTH_1_0			(1 << 14)
+# define GEN6_WM_LINE_AA_WIDTH_2_0			(2 << 14)
+# define GEN6_WM_LINE_AA_WIDTH_4_0			(3 << 14)
+# define GEN6_WM_POLYGON_STIPPLE_ENABLE			(1 << 13)
+# define GEN6_WM_LINE_STIPPLE_ENABLE			(1 << 12)
+# define GEN6_WM_OMASK_TO_RENDER_TARGET			(1 << 9)
+# define GEN6_WM_USES_SOURCE_W				(1 << 8)
+# define GEN6_WM_DUAL_SOURCE_BLEND_ENABLE		(1 << 7)
+# define GEN6_WM_32_DISPATCH_ENABLE			(1 << 2)
+# define GEN6_WM_16_DISPATCH_ENABLE			(1 << 1)
+# define GEN6_WM_8_DISPATCH_ENABLE			(1 << 0)
+/* DW6 */
+# define GEN6_WM_NUM_SF_OUTPUTS_SHIFT			20
+# define GEN6_WM_POSOFFSET_NONE				(0 << 18)
+# define GEN6_WM_POSOFFSET_CENTROID			(2 << 18)
+# define GEN6_WM_POSOFFSET_SAMPLE			(3 << 18)
+# define GEN6_WM_POSITION_ZW_PIXEL			(0 << 16)
+# define GEN6_WM_POSITION_ZW_CENTROID			(2 << 16)
+# define GEN6_WM_POSITION_ZW_SAMPLE			(3 << 16)
+# define GEN6_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC	(1 << 15)
+# define GEN6_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC	(1 << 14)
+# define GEN6_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC	(1 << 13)
+# define GEN6_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC		(1 << 12)
+# define GEN6_WM_PERSPECTIVE_CENTROID_BARYCENTRIC	(1 << 11)
+# define GEN6_WM_PERSPECTIVE_PIXEL_BARYCENTRIC		(1 << 10)
+# define GEN6_WM_POINT_RASTRULE_UPPER_RIGHT		(1 << 9)
+# define GEN6_WM_MSRAST_OFF_PIXEL			(0 << 1)
+# define GEN6_WM_MSRAST_OFF_PATTERN			(1 << 1)
+# define GEN6_WM_MSRAST_ON_PIXEL			(2 << 1)
+# define GEN6_WM_MSRAST_ON_PATTERN			(3 << 1)
+# define GEN6_WM_MSDISPMODE_PERPIXEL			(1 << 0)
+/* DW7: kernel 1 pointer */
+/* DW8: kernel 2 pointer */
+
 #define CMD_3D_CONSTANT_VS_STATE	      0x7815 /* GEN6+ */
 #define CMD_3D_CONSTANT_GS_STATE	      0x7816 /* GEN6+ */
+#define CMD_3D_CONSTANT_PS_STATE	      0x7817 /* GEN6+ */
 # define GEN6_CONSTANT_BUFFER_3_ENABLE			(1 << 15)
 # define GEN6_CONSTANT_BUFFER_2_ENABLE			(1 << 14)
 # define GEN6_CONSTANT_BUFFER_1_ENABLE			(1 << 13)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index f2579d7cdc..990eaf7e67 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -105,6 +105,7 @@ const struct brw_tracked_state gen6_sf_vp;
 const struct brw_tracked_state gen6_urb;
 const struct brw_tracked_state gen6_viewport_state;
 const struct brw_tracked_state gen6_vs_state;
+const struct brw_tracked_state gen6_wm_state;
 
 /**
  * Use same key for WM and VS surfaces.
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 6f214b037e..824502ca6e 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -134,7 +134,7 @@ const struct brw_tracked_state *gen6_atoms[] =
    &gen6_gs_state,
    &gen6_clip_state,
    &gen6_sf_state,
-   /* &gen6_wm_state, */
+   &gen6_wm_state,
 
    &gen6_scissor_state,
 
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
new file mode 100644
index 0000000000..d896f7dcc0
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright © 2009 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Eric Anholt <eric@anholt.net>
+ *
+ */
+
+#include "brw_context.h"
+#include "brw_state.h"
+#include "brw_defines.h"
+#include "brw_util.h"
+#include "main/macros.h"
+#include "main/enums.h"
+#include "shader/prog_parameter.h"
+#include "shader/prog_statevars.h"
+#include "intel_batchbuffer.h"
+
+static void
+upload_wm_state(struct brw_context *brw)
+{
+   struct intel_context *intel = &brw->intel;
+   GLcontext *ctx = &intel->ctx;
+   const struct brw_fragment_program *fp =
+      brw_fragment_program_const(brw->fragment_program);
+   unsigned int nr_params = fp->program.Base.Parameters->NumParameters;
+   drm_intel_bo *constant_bo;
+   int i;
+   uint32_t dw2, dw4, dw5, dw6;
+
+   dw2 = dw4 = dw5 = dw6 = 0;
+   dw4 |= GEN6_WM_STATISTICS_ENABLE;
+   dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
+   dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
+
+   /* BRW_NEW_NR_SURFACES */
+   dw2 |= brw->wm.nr_surfaces << GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT;
+
+   /* CACHE_NEW_SAMPLER */
+   dw2 |= (ALIGN(brw->wm.sampler_count, 4) / 4) << GEN6_WM_SAMPLER_COUNT_SHIFT;
+   dw4 |= (1 << GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
+
+   dw5 |= (40 - 1) << GEN6_WM_MAX_THREADS_SHIFT;
+   dw5 |= GEN6_WM_DISPATCH_ENABLE;
+
+   /* BRW_NEW_FRAGMENT_PROGRAM */
+   if (fp->isGLSL)
+      dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
+   else
+      dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
+
+   /* _NEW_LINE */
+   if (ctx->Line.StippleFlag)
+      dw5 |= GEN6_WM_LINE_STIPPLE_ENABLE;
+
+   /* _NEW_POLYGONSTIPPLE */
+   if (ctx->Polygon.StippleFlag)
+      dw5 |= GEN6_WM_POLYGON_STIPPLE_ENABLE;
+
+   /* BRW_NEW_FRAGMENT_PROGRAM */
+   if (fp->program.Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
+      dw5 |= GEN6_WM_USES_SOURCE_DEPTH | GEN6_WM_USES_SOURCE_W;
+   if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
+      dw5 |= GEN6_WM_COMPUTED_DEPTH;
+
+   /* _NEW_COLOR */
+   if (fp->program.UsesKill || ctx->Color.AlphaEnabled)
+      dw5 |= GEN6_WM_KILL_ENABLE;
+
+   /* This should probably be FS inputs read */
+   dw6 |= brw_count_bits(brw->vs.prog_data->outputs_written) <<
+      GEN6_WM_NUM_SF_OUTPUTS_SHIFT;
+
+   BEGIN_BATCH(9);
+   OUT_BATCH(CMD_3D_WM_STATE << 16 | (9 - 2));
+   OUT_RELOC(brw->wm.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+   OUT_BATCH(dw2);
+   OUT_BATCH(0); /* scratch space base offset */
+   OUT_BATCH(dw4);
+   OUT_BATCH(dw5);
+   OUT_BATCH(dw6);
+   OUT_BATCH(0); /* kernel 1 pointer */
+   OUT_BATCH(0); /* kernel 2 pointer */
+   ADVANCE_BATCH();
+
+   intel_batchbuffer_emit_mi_flush(intel->batch);
+
+   if (fp->use_const_buffer || nr_params == 0) {
+      /* Disable the push constant buffers. */
+      BEGIN_BATCH(5);
+      OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 | (5 - 2));
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      ADVANCE_BATCH();
+   } else {
+      /* Updates the ParamaterValues[i] pointers for all parameters of the
+       * basic type of PROGRAM_STATE_VAR.
+       */
+      _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
+
+      constant_bo = drm_intel_bo_alloc(intel->bufmgr, "WM constant_bo",
+				       nr_params * 4 * sizeof(float),
+				       4096);
+      intel_bo_map_gtt_preferred(intel, constant_bo, GL_TRUE);
+      for (i = 0; i < nr_params; i++) {
+	 memcpy((char *)constant_bo->virtual + i * 4 * sizeof(float),
+		fp->program.Base.Parameters->ParameterValues[i],
+		4 * sizeof(float));
+      }
+      intel_bo_unmap_gtt_preferred(intel, constant_bo);
+
+      BEGIN_BATCH(5);
+      OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 |
+		GEN6_CONSTANT_BUFFER_0_ENABLE |
+		(5 - 2));
+      OUT_RELOC(constant_bo,
+		I915_GEM_DOMAIN_RENDER, 0, /* XXX: bad domain */
+		ALIGN(nr_params, 2) / 2 - 1);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      ADVANCE_BATCH();
+
+      drm_intel_bo_unreference(constant_bo);
+   }
+
+   intel_batchbuffer_emit_mi_flush(intel->batch);
+}
+
+const struct brw_tracked_state gen6_wm_state = {
+   .dirty = {
+      .mesa  = _NEW_LINE | _NEW_POLYGONSTIPPLE | _NEW_COLOR,
+      .brw   = (BRW_NEW_CURBE_OFFSETS |
+		BRW_NEW_FRAGMENT_PROGRAM |
+                BRW_NEW_NR_WM_SURFACES |
+		BRW_NEW_URB_FENCE |
+		BRW_NEW_BATCH),
+      .cache = CACHE_NEW_SAMPLER
+   },
+   .emit = upload_wm_state,
+};
-- 
cgit v1.2.3


From 591a996ab6a8ef96a46e88317071330d94c4138f Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 21 Dec 2009 13:08:41 -0800
Subject: i965: Move PIPELINE_SELECT to the top of gen6 3d pipeline setup.

---
 src/mesa/drivers/dri/i965/brw_state_upload.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 824502ca6e..aa83d7ad18 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -116,6 +116,8 @@ const struct brw_tracked_state *gen6_atoms[] =
    &gen6_cc_vp,
 
    /* Command packets: */
+   &brw_invarient_state,
+
    &gen6_viewport_state,	/* must do after *_vp stages */
 
    &gen6_urb,
@@ -138,8 +140,6 @@ const struct brw_tracked_state *gen6_atoms[] =
 
    &gen6_scissor_state,
 
-   &brw_invarient_state,
-
    &brw_state_base_address,
 
    &gen6_binding_table_pointers,
-- 
cgit v1.2.3


From 1489f108f4a9b53b42d3d4123da64ccdb7aafdde Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 21 Dec 2009 14:28:18 -0800
Subject: i965: Fix up some Sandybridge define checks for the structure rebase.

---
 src/mesa/drivers/dri/i965/brw_draw_upload.c | 6 +++---
 src/mesa/drivers/dri/intel/intel_context.c  | 2 ++
 2 files changed, 5 insertions(+), 3 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index e6bfc567af..f0a4e8ad65 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -536,7 +536,7 @@ static void brw_emit_vertices(struct brw_context *brw)
       struct brw_vertex_element *input = brw->vb.enabled[i];
       uint32_t dw0;
 
-      if (IS_GEN6(intel->intelScreen->deviceID)) {
+      if (intel->gen >= 6) {
 	 dw0 = GEN6_VB0_ACCESS_VERTEXDATA |
 	    (i << GEN6_VB0_INDEX_SHIFT);
       } else {
@@ -549,7 +549,7 @@ static void brw_emit_vertices(struct brw_context *brw)
       OUT_RELOC(input->bo,
 		I915_GEM_DOMAIN_VERTEX, 0,
 		input->offset);
-      if (intel->is_ironlake) {
+      if (intel->is_ironlake || intel->gen >= 6) {
 	 OUT_RELOC(input->bo,
 		   I915_GEM_DOMAIN_VERTEX, 0,
 		   input->bo->size - 1);
@@ -592,7 +592,7 @@ static void brw_emit_vertices(struct brw_context *brw)
 		   (0 << BRW_VE0_SRC_OFFSET_SHIFT));
       }
 
-      if (intel->is_ironlake)
+      if (intel->is_ironlake || intel->gen >= 6)
           OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
                     (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
                     (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 8af7a23385..767ad8c9d2 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -612,6 +612,8 @@ intelInitContext(struct intel_context *intel,
 
    if (IS_GEN6(intel->intelScreen->deviceID)) {
       intel->gen = 6;
+      intel->needs_ff_sync = GL_TRUE;
+      intel->has_luminance_srgb = GL_TRUE;
    } else if (IS_965(intel->intelScreen->deviceID)) {
       intel->gen = 4;
    } else if (IS_9XX(intel->intelScreen->deviceID)) {
-- 
cgit v1.2.3


From 2ab3bf2fa37042386a2d50f60b1d0e32e26b91c2 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 25 Jan 2010 14:48:06 -0800
Subject: i965: Re-disable the VS.

There's stuff that needs to happen in the ISA before we can play with
actually executing anything in the VS.
---
 src/mesa/drivers/dri/i965/brw_defines.h   | 2 +-
 src/mesa/drivers/dri/i965/gen6_vs_state.c | 3 +--
 2 files changed, 2 insertions(+), 3 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index be32a8fa82..50c4d6d0a4 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -796,7 +796,7 @@
 # define GEN6_VE0_INDEX_SHIFT		26
 # define BRW_VE0_FORMAT_SHIFT		16
 # define BRW_VE0_VALID			(1 << 26)
-# define GEN6_VE0_VALID			(1 << 25)
+# define GEN6_VE0_VALID			(0 << 25)
 # define BRW_VE0_SRC_OFFSET_SHIFT	0
 # define BRW_VE1_COMPONENT_NOSTORE	0
 # define BRW_VE1_COMPONENT_STORE_SRC	1
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 0299dc6768..ba00e4e1fb 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -56,8 +56,7 @@ upload_vs_state(struct brw_context *brw)
 	     (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
 	     (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
    OUT_BATCH((0 << GEN6_VS_MAX_THREADS_SHIFT) |
-	     GEN6_VS_STATISTICS_ENABLE|
-	     GEN6_VS_ENABLE);
+	     GEN6_VS_STATISTICS_ENABLE);
    ADVANCE_BATCH();
 
    intel_batchbuffer_emit_mi_flush(intel->batch);
-- 
cgit v1.2.3


From f69d46150c308285a518391db02cc9cba0f2a12d Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 1 Feb 2010 09:04:12 -0800
Subject: i965: Add a couple SNB state packets I saw in other batchbuffer
 dumps.

---
 src/mesa/drivers/dri/i965/brw_defines.h    | 21 ++++++++++++++++++
 src/mesa/drivers/dri/i965/brw_misc_state.c | 34 ++++++++++++++++++++++++++++++
 2 files changed, 55 insertions(+)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 50c4d6d0a4..52cd12df59 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1024,6 +1024,8 @@
 # define GEN6_CONSTANT_BUFFER_1_ENABLE			(1 << 13)
 # define GEN6_CONSTANT_BUFFER_0_ENABLE			(1 << 12)
 
+#define CMD_3D_SAMPLE_MASK			0x7818 /* GEN6+ */
+
 #define CMD_DRAW_RECT                 0x7900
 #define CMD_BLEND_CONSTANT_COLOR      0x7901
 #define CMD_CHROMA_KEY                0x7904
@@ -1034,6 +1036,25 @@
 #define CMD_GLOBAL_DEPTH_OFFSET_CLAMP 0x7909
 #define CMD_AA_LINE_PARAMETERS        0x790a
 
+#define CMD_GS_SVB_INDEX			0x790b /* CTG+ */
+/* DW1 */
+# define SVB_INDEX_SHIFT				29
+# define SVB_LOAD_INTERNAL_VERTEX_COUNT			(1 << 0) /* SNB+ */
+/* DW2: SVB index */
+/* DW3: SVB maximum index */
+
+#define CMD_3D_MULTISAMPLE			0x790d /* SNB+ */
+/* DW1 */
+# define MS_PIXEL_LOCATION_CENTER			(0 << 4)
+# define MS_PIXEL_LOCATION_UPPER_LEFT			(1 << 4)
+# define MS_NUMSAMPLES_1				(0 << 1)
+# define MS_NUMSAMPLES_4				(2 << 1)
+# define MS_NUMSAMPLES_8				(3 << 1)
+
+#define CMD_3D_CLEAR_PARAMS			0x7910 /* ILK+ */
+# define DEPTH_CLEAR_VALID				(1 << 15)
+/* DW1: depth clear value */
+
 #define CMD_PIPE_CONTROL              0x7a00
 
 #define CMD_3D_PRIM                   0x7b00
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index b4e7dd547f..d030ed41f4 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -314,6 +314,14 @@ static void emit_depthbuffer(struct brw_context *brw)
 
       ADVANCE_BATCH();
    }
+
+   /* Initialize it for safety. */
+   if (intel->gen >= 6) {
+      BEGIN_BATCH(2);
+      OUT_BATCH(CMD_3D_CLEAR_PARAMS << 16 | (2 - 2));
+      OUT_BATCH(0);
+      ADVANCE_BATCH();
+   }
 }
 
 const struct brw_tracked_state brw_depthbuffer = {
@@ -511,6 +519,32 @@ static void upload_invarient_state( struct brw_context *brw )
       BRW_BATCH_STRUCT(brw, &gdo);
    }
 
+   intel_batchbuffer_emit_mi_flush(intel->batch);
+
+   if (intel->gen >= 6) {
+      int i;
+
+      BEGIN_BATCH(3);
+      OUT_BATCH(CMD_3D_MULTISAMPLE << 16 | (3 - 2));
+      OUT_BATCH(MS_PIXEL_LOCATION_CENTER |
+		MS_NUMSAMPLES_1);
+      OUT_BATCH(0); /* positions for 4/8-sample */
+      ADVANCE_BATCH();
+
+      BEGIN_BATCH(2);
+      OUT_BATCH(CMD_3D_SAMPLE_MASK << 16 | (2 - 2));
+      OUT_BATCH(1);
+      ADVANCE_BATCH();
+
+      for (i = 0; i < 4; i++) {
+	 BEGIN_BATCH(4);
+	 OUT_BATCH(CMD_GS_SVB_INDEX << 16 | (4 - 2));
+	 OUT_BATCH(i << SVB_INDEX_SHIFT);
+	 OUT_BATCH(0);
+	 OUT_BATCH(0xffffffff);
+	 ADVANCE_BATCH();
+      }
+   }
 
    /* 0x61020000  State Instruction Pointer */
    {
-- 
cgit v1.2.3


From 5878c841e90a8006715877045aa95a752472eaab Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 1 Feb 2010 09:41:26 -0800
Subject: i965: Set GS rendering enabled even when the GS stage is disabled.

This is copying the behavior of other drivers.
---
 src/mesa/drivers/dri/i965/gen6_gs_state.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c
index 761059c96a..9a4a13810a 100644
--- a/src/mesa/drivers/dri/i965/gen6_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c
@@ -49,7 +49,8 @@ upload_gs_state(struct brw_context *brw)
 		(brw->gs.prog_data->urb_read_length << GEN6_GS_URB_READ_LENGTH_SHIFT) |
 		(0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT));
       OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) |
-		GEN6_GS_STATISTICS_ENABLE);
+		GEN6_GS_STATISTICS_ENABLE |
+		GEN6_GS_RENDERING_ENABLE);
       OUT_BATCH(GEN6_GS_ENABLE);
       ADVANCE_BATCH();
    } else {
@@ -63,7 +64,8 @@ upload_gs_state(struct brw_context *brw)
 		(0 << GEN6_GS_URB_READ_LENGTH_SHIFT) |
 		(0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT));
       OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) |
-		GEN6_GS_STATISTICS_ENABLE);
+		GEN6_GS_STATISTICS_ENABLE |
+		GEN6_GS_RENDERING_ENABLE);
       OUT_BATCH(0);
       ADVANCE_BATCH();
    }
-- 
cgit v1.2.3


From c791f8a1e532834ae7a517c042e9efe262b62233 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 1 Feb 2010 09:55:18 -0800
Subject: i965: Set up the SNB sampler state pointers.

---
 src/mesa/drivers/dri/i965/Makefile             |  1 +
 src/mesa/drivers/dri/i965/brw_defines.h        |  8 +++
 src/mesa/drivers/dri/i965/brw_state.h          |  1 +
 src/mesa/drivers/dri/i965/brw_state_upload.c   |  1 +
 src/mesa/drivers/dri/i965/gen6_sampler_state.c | 74 ++++++++++++++++++++++++++
 5 files changed, 85 insertions(+)
 create mode 100644 src/mesa/drivers/dri/i965/gen6_sampler_state.c

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index f84e87e7e6..f98a1a27db 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -89,6 +89,7 @@ DRIVER_SOURCES = \
 	gen6_clip_state.c \
 	gen6_depthstencil.c \
 	gen6_gs_state.c \
+	gen6_sampler_state.c \
 	gen6_scissor_state.c \
 	gen6_sf_state.c \
 	gen6_urb.c \
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 52cd12df59..9ed49e0dc3 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -782,6 +782,14 @@
 # define GEN6_BINDING_TABLE_MODIFY_GS	(1 << 9)
 # define GEN6_BINDING_TABLE_MODIFY_PS	(1 << 10)
 
+#define CMD_3D_SAMPLER_STATE_POINTERS			0x7802 /* SNB+ */
+# define PS_SAMPLER_STATE_CHANGE				(1 << 12)
+# define GS_SAMPLER_STATE_CHANGE				(1 << 9)
+# define VS_SAMPLER_STATE_CHANGE				(1 << 8)
+/* DW1: VS */
+/* DW2: GS */
+/* DW3: PS */
+
 #define CMD_VERTEX_BUFFER             0x7808
 # define BRW_VB0_INDEX_SHIFT		27
 # define GEN6_VB0_INDEX_SHIFT		26
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 990eaf7e67..f790cfabe2 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -99,6 +99,7 @@ const struct brw_tracked_state gen6_clip_vp;
 const struct brw_tracked_state gen6_color_calc_state;
 const struct brw_tracked_state gen6_depth_stencil_state;
 const struct brw_tracked_state gen6_gs_state;
+const struct brw_tracked_state gen6_sampler_state;
 const struct brw_tracked_state gen6_scissor_state;
 const struct brw_tracked_state gen6_sf_state;
 const struct brw_tracked_state gen6_sf_vp;
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index aa83d7ad18..9e54f29f0f 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -131,6 +131,7 @@ const struct brw_tracked_state *gen6_atoms[] =
    &brw_wm_surfaces,		/* must do before samplers and unit */
 
    &brw_wm_samplers,
+   &gen6_sampler_state,
 
    &gen6_vs_state,
    &gen6_gs_state,
diff --git a/src/mesa/drivers/dri/i965/gen6_sampler_state.c b/src/mesa/drivers/dri/i965/gen6_sampler_state.c
new file mode 100644
index 0000000000..641d8859b3
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen6_sampler_state.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Eric Anholt <eric@anholt.net>
+ *
+ */
+
+#include "brw_context.h"
+#include "brw_state.h"
+#include "brw_defines.h"
+#include "brw_util.h"
+#include "intel_batchbuffer.h"
+#include "main/macros.h"
+#include "main/enums.h"
+
+static void
+upload_sampler_state_pointers(struct brw_context *brw)
+{
+   struct intel_context *intel = &brw->intel;
+
+   BEGIN_BATCH(4);
+   OUT_BATCH(CMD_3D_SAMPLER_STATE_POINTERS << 16 |
+	     VS_SAMPLER_STATE_CHANGE |
+	     GS_SAMPLER_STATE_CHANGE |
+	     PS_SAMPLER_STATE_CHANGE |
+	     (4 - 2));
+   OUT_BATCH(0); /* VS */
+   OUT_BATCH(0); /* GS */
+   if (brw->wm.sampler_bo)
+      OUT_RELOC(brw->wm.sampler_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+   else
+      OUT_BATCH(0);
+
+   ADVANCE_BATCH();
+
+   intel_batchbuffer_emit_mi_flush(intel->batch);
+}
+
+
+static void
+prepare_sampler_state_pointers(struct brw_context *brw)
+{
+   brw_add_validated_bo(brw, brw->wm.sampler_bo);
+}
+
+const struct brw_tracked_state gen6_sampler_state = {
+   .dirty = {
+      .mesa = 0,
+      .brw = BRW_NEW_BATCH,
+      .cache = CACHE_NEW_SAMPLER
+   },
+   .prepare = prepare_sampler_state_pointers,
+   .emit = upload_sampler_state_pointers,
+};
-- 
cgit v1.2.3


From 078e7b62f69658e40aedea59cf6f005162a29f83 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 23 Feb 2010 17:42:20 -0800
Subject: i965: Emit SNB FF unit state after the unit's push constants.

There's a BUN for the WM unit that says WM_STATE must immediately
follow PS_CONSTANTS, which this addresses.  Presumably other units are
roughly the same, too.
---
 src/mesa/drivers/dri/i965/gen6_gs_state.c | 22 ++++----
 src/mesa/drivers/dri/i965/gen6_vs_state.c | 30 +++++------
 src/mesa/drivers/dri/i965/gen6_wm_state.c | 86 +++++++++++++++----------------
 3 files changed, 69 insertions(+), 69 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c
index 9a4a13810a..4032605a85 100644
--- a/src/mesa/drivers/dri/i965/gen6_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c
@@ -38,6 +38,17 @@ upload_gs_state(struct brw_context *brw)
 {
    struct intel_context *intel = &brw->intel;
 
+   /* Disable all the constant buffers. */
+   BEGIN_BATCH(5);
+   OUT_BATCH(CMD_3D_CONSTANT_GS_STATE << 16 | (5 - 2));
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   ADVANCE_BATCH();
+
+   intel_batchbuffer_emit_mi_flush(intel->batch);
+
    if (brw->gs.prog_bo) {
       BEGIN_BATCH(7);
       OUT_BATCH(CMD_3D_GS_STATE << 16 | (7 - 2));
@@ -69,17 +80,6 @@ upload_gs_state(struct brw_context *brw)
       OUT_BATCH(0);
       ADVANCE_BATCH();
    }
-
-   /* Disable all the constant buffers. */
-   BEGIN_BATCH(5);
-   OUT_BATCH(CMD_3D_CONSTANT_GS_STATE << 16 | (5 - 2));
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
-
-   intel_batchbuffer_emit_mi_flush(intel->batch);
 }
 
 const struct brw_tracked_state gen6_gs_state = {
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index ba00e4e1fb..04fc16e679 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -46,21 +46,6 @@ upload_vs_state(struct brw_context *brw)
    drm_intel_bo *constant_bo;
    int i;
 
-   BEGIN_BATCH(6);
-   OUT_BATCH(CMD_3D_VS_STATE << 16 | (6 - 2));
-   OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
-   OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) |
-	     (brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
-   OUT_BATCH(0); /* scratch space base offset */
-   OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
-	     (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
-	     (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
-   OUT_BATCH((0 << GEN6_VS_MAX_THREADS_SHIFT) |
-	     GEN6_VS_STATISTICS_ENABLE);
-   ADVANCE_BATCH();
-
-   intel_batchbuffer_emit_mi_flush(intel->batch);
-
    if (vp->use_const_buffer || nr_params == 0) {
       /* Disable the push constant buffers. */
       BEGIN_BATCH(5);
@@ -106,6 +91,21 @@ upload_vs_state(struct brw_context *brw)
    }
 
    intel_batchbuffer_emit_mi_flush(intel->batch);
+
+   BEGIN_BATCH(6);
+   OUT_BATCH(CMD_3D_VS_STATE << 16 | (6 - 2));
+   OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+   OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) |
+	     (brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
+   OUT_BATCH(0); /* scratch space base offset */
+   OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
+	     (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
+	     (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
+   OUT_BATCH((0 << GEN6_VS_MAX_THREADS_SHIFT) |
+	     GEN6_VS_STATISTICS_ENABLE);
+   ADVANCE_BATCH();
+
+   intel_batchbuffer_emit_mi_flush(intel->batch);
 }
 
 const struct brw_tracked_state gen6_vs_state = {
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index d896f7dcc0..f4ae7ed750 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -47,6 +47,49 @@ upload_wm_state(struct brw_context *brw)
    int i;
    uint32_t dw2, dw4, dw5, dw6;
 
+   if (fp->use_const_buffer || nr_params == 0) {
+      /* Disable the push constant buffers. */
+      BEGIN_BATCH(5);
+      OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 | (5 - 2));
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      ADVANCE_BATCH();
+   } else {
+      /* Updates the ParamaterValues[i] pointers for all parameters of the
+       * basic type of PROGRAM_STATE_VAR.
+       */
+      _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
+
+      constant_bo = drm_intel_bo_alloc(intel->bufmgr, "WM constant_bo",
+				       nr_params * 4 * sizeof(float),
+				       4096);
+      intel_bo_map_gtt_preferred(intel, constant_bo, GL_TRUE);
+      for (i = 0; i < nr_params; i++) {
+	 memcpy((char *)constant_bo->virtual + i * 4 * sizeof(float),
+		fp->program.Base.Parameters->ParameterValues[i],
+		4 * sizeof(float));
+      }
+      intel_bo_unmap_gtt_preferred(intel, constant_bo);
+
+      BEGIN_BATCH(5);
+      OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 |
+		GEN6_CONSTANT_BUFFER_0_ENABLE |
+		(5 - 2));
+      OUT_RELOC(constant_bo,
+		I915_GEM_DOMAIN_RENDER, 0, /* XXX: bad domain */
+		ALIGN(nr_params, 2) / 2 - 1);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      ADVANCE_BATCH();
+
+      drm_intel_bo_unreference(constant_bo);
+   }
+
+   intel_batchbuffer_emit_mi_flush(intel->batch);
+
    dw2 = dw4 = dw5 = dw6 = 0;
    dw4 |= GEN6_WM_STATISTICS_ENABLE;
    dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
@@ -103,49 +146,6 @@ upload_wm_state(struct brw_context *brw)
    ADVANCE_BATCH();
 
    intel_batchbuffer_emit_mi_flush(intel->batch);
-
-   if (fp->use_const_buffer || nr_params == 0) {
-      /* Disable the push constant buffers. */
-      BEGIN_BATCH(5);
-      OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 | (5 - 2));
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      ADVANCE_BATCH();
-   } else {
-      /* Updates the ParamaterValues[i] pointers for all parameters of the
-       * basic type of PROGRAM_STATE_VAR.
-       */
-      _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
-
-      constant_bo = drm_intel_bo_alloc(intel->bufmgr, "WM constant_bo",
-				       nr_params * 4 * sizeof(float),
-				       4096);
-      intel_bo_map_gtt_preferred(intel, constant_bo, GL_TRUE);
-      for (i = 0; i < nr_params; i++) {
-	 memcpy((char *)constant_bo->virtual + i * 4 * sizeof(float),
-		fp->program.Base.Parameters->ParameterValues[i],
-		4 * sizeof(float));
-      }
-      intel_bo_unmap_gtt_preferred(intel, constant_bo);
-
-      BEGIN_BATCH(5);
-      OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 |
-		GEN6_CONSTANT_BUFFER_0_ENABLE |
-		(5 - 2));
-      OUT_RELOC(constant_bo,
-		I915_GEM_DOMAIN_RENDER, 0, /* XXX: bad domain */
-		ALIGN(nr_params, 2) / 2 - 1);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      ADVANCE_BATCH();
-
-      drm_intel_bo_unreference(constant_bo);
-   }
-
-   intel_batchbuffer_emit_mi_flush(intel->batch);
 }
 
 const struct brw_tracked_state gen6_wm_state = {
-- 
cgit v1.2.3


From 38c449409207c8948c1961a3132475bbd422f8f1 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 24 Feb 2010 09:16:19 -0800
Subject: i965: Add SNB math opcode support.

This is untested at this point.
---
 src/mesa/drivers/dri/i965/brw_defines.h |  4 ++-
 src/mesa/drivers/dri/i965/brw_eu_emit.c | 50 +++++++++++++++++++++------------
 src/mesa/drivers/dri/i965/brw_vs_emit.c | 12 +++++---
 3 files changed, 43 insertions(+), 23 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 9ed49e0dc3..2bb3448da7 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -530,6 +530,7 @@
 #define BRW_OPCODE_POP        47
 #define BRW_OPCODE_WAIT       48
 #define BRW_OPCODE_SEND       49
+#define BRW_OPCODE_MATH       56
 #define BRW_OPCODE_ADD        64
 #define BRW_OPCODE_MUL        65
 #define BRW_OPCODE_AVG        66
@@ -727,7 +728,8 @@
 #define BRW_MATH_FUNCTION_SIN                              6 /* was 7 */
 #define BRW_MATH_FUNCTION_COS                              7 /* was 8 */
 #define BRW_MATH_FUNCTION_SINCOS                           8 /* was 6 */
-#define BRW_MATH_FUNCTION_TAN                              9
+#define BRW_MATH_FUNCTION_TAN                              9 /* gen4 */
+#define BRW_MATH_FUNCTION_FDIV                             9 /* gen6+ */
 #define BRW_MATH_FUNCTION_POW                              10
 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER   11
 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT                 12
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index b832c7165d..2d55299ddb 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -917,26 +917,40 @@ void brw_math( struct brw_compile *p,
 	       GLuint data_type,
 	       GLuint precision )
 {
-   struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
-   GLuint msg_length = (function == BRW_MATH_FUNCTION_POW) ? 2 : 1; 
-   GLuint response_length = (function == BRW_MATH_FUNCTION_SINCOS) ? 2 : 1; 
+   struct intel_context *intel = &p->brw->intel;
 
-   /* Example code doesn't set predicate_control for send
-    * instructions.
-    */
-   insn->header.predicate_control = 0; 
-   insn->header.destreg__conditionalmod = msg_reg_nr;
+   if (intel->gen >= 6) {
+      struct brw_instruction *insn = next_insn(p, BRW_OPCODE_MATH);
 
-   brw_set_dest(insn, dest);
-   brw_set_src0(insn, src);
-   brw_set_math_message(p->brw,
-			insn, 
-			msg_length, response_length, 
-			function,
-			BRW_MATH_INTEGER_UNSIGNED,
-			precision,
-			saturate,
-			data_type);
+      /* Math is the same ISA format as other opcodes, except that CondModifier
+       * becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
+       */
+      insn->header.destreg__conditionalmod = function;
+
+      brw_set_dest(insn, dest);
+      brw_set_src0(insn, src);
+      brw_set_src1(insn, brw_null_reg());
+   } else {
+      struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
+      GLuint msg_length = (function == BRW_MATH_FUNCTION_POW) ? 2 : 1;
+      GLuint response_length = (function == BRW_MATH_FUNCTION_SINCOS) ? 2 : 1;
+      /* Example code doesn't set predicate_control for send
+       * instructions.
+       */
+      insn->header.predicate_control = 0;
+      insn->header.destreg__conditionalmod = msg_reg_nr;
+
+      brw_set_dest(insn, dest);
+      brw_set_src0(insn, src);
+      brw_set_math_message(p->brw,
+			   insn,
+			   msg_length, response_length,
+			   function,
+			   BRW_MATH_INTEGER_UNSIGNED,
+			   precision,
+			   saturate,
+			   data_type);
+   }
 }
 
 /**
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index 88327d9927..b6e5f945eb 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -479,9 +479,11 @@ static void emit_math1( struct brw_vs_compile *c,
     * whether that turns out to be a simulator bug or not:
     */
    struct brw_compile *p = &c->func;
+   struct intel_context *intel = &p->brw->intel;
    struct brw_reg tmp = dst;
-   GLboolean need_tmp = (dst.dw1.bits.writemask != 0xf ||
-			 dst.file != BRW_GENERAL_REGISTER_FILE);
+   GLboolean need_tmp = (intel->gen < 6 &&
+			 (dst.dw1.bits.writemask != 0xf ||
+			  dst.file != BRW_GENERAL_REGISTER_FILE));
 
    if (need_tmp) 
       tmp = get_tmp(c);
@@ -510,9 +512,11 @@ static void emit_math2( struct brw_vs_compile *c,
 			GLuint precision)
 {
    struct brw_compile *p = &c->func;
+   struct intel_context *intel = &p->brw->intel;
    struct brw_reg tmp = dst;
-   GLboolean need_tmp = (dst.dw1.bits.writemask != 0xf ||
-			 dst.file != BRW_GENERAL_REGISTER_FILE);
+   GLboolean need_tmp = (intel->gen < 6 &&
+			 (dst.dw1.bits.writemask != 0xf ||
+			  dst.file != BRW_GENERAL_REGISTER_FILE));
 
    if (need_tmp) 
       tmp = get_tmp(c);
-- 
cgit v1.2.3


From 17ddb7c7e897719fa28fb64ac3ecbc7b7e9f8d24 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 25 Feb 2010 13:46:45 -0800
Subject: i965: Fix the SNB URB entry count setup.

---
 src/mesa/drivers/dri/i965/gen6_urb.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c
index 55f7ac7727..5445e4035a 100644
--- a/src/mesa/drivers/dri/i965/gen6_urb.c
+++ b/src/mesa/drivers/dri/i965/gen6_urb.c
@@ -64,9 +64,9 @@ upload_urb(struct brw_context *brw)
    BEGIN_BATCH(3);
    OUT_BATCH(CMD_URB << 16 | (3 - 2));
    OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_VS_SIZE_SHIFT) |
-	     ((brw->urb.nr_vs_entries) << GEN6_URB_VS_SIZE_SHIFT));
+	     ((brw->urb.nr_vs_entries) << GEN6_URB_VS_ENTRIES_SHIFT));
    OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) |
-	     ((brw->urb.nr_gs_entries) << GEN6_URB_GS_SIZE_SHIFT));
+	     ((brw->urb.nr_gs_entries) << GEN6_URB_GS_ENTRIES_SHIFT));
    ADVANCE_BATCH();
 
    intel_batchbuffer_emit_mi_flush(intel->batch);
-- 
cgit v1.2.3


From dedfc0e6e606594b9b1772c6b0689f7fa547c3aa Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 25 Feb 2010 14:05:27 -0800
Subject: i965: Fix the SNB clip near VP API bit.

---
 src/mesa/drivers/dri/i965/brw_defines.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 2bb3448da7..76ae17c96a 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -879,7 +879,8 @@
 # define GEN6_CLIP_STATISTICS_ENABLE			(1 << 10)
 /* DW2 */
 # define GEN6_CLIP_ENABLE				(1 << 31)
-# define GEN6_CLIP_API_OGL				(1 << 30)
+# define GEN6_CLIP_API_OGL				(0 << 30)
+# define GEN6_CLIP_API_D3D				(1 << 30)
 # define GEN6_CLIP_XY_TEST				(1 << 28)
 # define GEN6_CLIP_Z_TEST				(1 << 27)
 # define GEN6_CLIP_GB_TEST				(1 << 26)
-- 
cgit v1.2.3


From 89cce536cbc55460bc534acc06ea9f4d9ae71016 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 25 Feb 2010 14:24:36 -0800
Subject: i965: Don't include SNB in has_negative_rhw_bug.

---
 src/mesa/drivers/dri/i965/brw_context.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 3614149966..a512896f31 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -170,7 +170,7 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis,
       brw->urb.size = 384;
       brw->vs_max_threads = 32;
       brw->wm_max_threads = 10 * 5;
-   } else {
+   } else if (intel->gen < 6) {
       brw->urb.size = 256;
       brw->vs_max_threads = 16;
       brw->wm_max_threads = 8 * 4;
-- 
cgit v1.2.3


From d790564f9452d6fa0378346a85c792aa346c1a57 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 25 Feb 2010 15:22:20 -0800
Subject: i965: Fix the SNB VE valid bit.

So, when the docs say that 0 means enabled now?  That's a lie.
---
 src/mesa/drivers/dri/i965/brw_defines.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 76ae17c96a..bb1b5f5ef0 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -806,7 +806,7 @@
 # define GEN6_VE0_INDEX_SHIFT		26
 # define BRW_VE0_FORMAT_SHIFT		16
 # define BRW_VE0_VALID			(1 << 26)
-# define GEN6_VE0_VALID			(0 << 25)
+# define GEN6_VE0_VALID			(1 << 25)
 # define BRW_VE0_SRC_OFFSET_SHIFT	0
 # define BRW_VE1_COMPONENT_NOSTORE	0
 # define BRW_VE1_COMPONENT_STORE_SRC	1
-- 
cgit v1.2.3


From 1d7aec053b061caef928cfffc786660603d5f14c Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 25 Feb 2010 15:23:13 -0800
Subject: i965: Lump SNB in with Ironlake for bigger VUEs.

This gets the VS to the point of accepting vertices.  \o/
---
 src/mesa/drivers/dri/i965/brw_vs_emit.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index b6e5f945eb..4e3338293b 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -279,7 +279,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
     */
    attributes_in_vue = MAX2(c->nr_outputs, c->nr_inputs);
 
-   if (intel->is_ironlake)
+   if (intel->is_ironlake || intel->gen >= 6)
        c->prog_data.urb_entry_size = (attributes_in_vue + 6 + 3) / 4;
    else
        c->prog_data.urb_entry_size = (attributes_in_vue + 2 + 3) / 4;
@@ -1273,7 +1273,7 @@ static void emit_vertex_write( struct brw_vs_compile *c)
    brw_set_access_mode(p, BRW_ALIGN_1);
    brw_MOV(p, offset(m0, 2), ndc);
 
-   if (intel->is_ironlake) {
+   if (intel->is_ironlake || intel->gen >= 6) {
        /* There are 20 DWs (D0-D19) in VUE vertex header on Ironlake */
        brw_MOV(p, offset(m0, 3), pos); /* a portion of vertex header */
        /* m4, m5 contain the distances from vertex to the user clip planeXXX. 
-- 
cgit v1.2.3


From 54ea39f768871eb10286b195e1cd77f757c99752 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 25 Feb 2010 16:25:17 -0800
Subject: i965: Don't set a nonexistent enable bit in several SNB state
 pointers.

The modify bit is now usually in the instruction header.  The
exception is CC state pointers.
---
 src/mesa/drivers/dri/i965/gen6_sampler_state.c  | 2 +-
 src/mesa/drivers/dri/i965/gen6_scissor_state.c  | 2 +-
 src/mesa/drivers/dri/i965/gen6_viewport_state.c | 6 +++---
 3 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/gen6_sampler_state.c b/src/mesa/drivers/dri/i965/gen6_sampler_state.c
index 641d8859b3..f5d537b1cf 100644
--- a/src/mesa/drivers/dri/i965/gen6_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sampler_state.c
@@ -47,7 +47,7 @@ upload_sampler_state_pointers(struct brw_context *brw)
    OUT_BATCH(0); /* VS */
    OUT_BATCH(0); /* GS */
    if (brw->wm.sampler_bo)
-      OUT_RELOC(brw->wm.sampler_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+      OUT_RELOC(brw->wm.sampler_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
    else
       OUT_BATCH(0);
 
diff --git a/src/mesa/drivers/dri/i965/gen6_scissor_state.c b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
index 2d36f0056d..81ebbf4ddf 100644
--- a/src/mesa/drivers/dri/i965/gen6_scissor_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
@@ -85,7 +85,7 @@ static void upload_scissor_state_pointers(struct brw_context *brw)
 
    BEGIN_BATCH(2);
    OUT_BATCH(CMD_3D_SCISSOR_STATE_POINTERS << 16 | (2 - 2));
-   OUT_RELOC(brw->sf.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+   OUT_RELOC(brw->sf.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
    ADVANCE_BATCH();
 
    intel_batchbuffer_emit_mi_flush(intel->batch);
diff --git a/src/mesa/drivers/dri/i965/gen6_viewport_state.c b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
index 13d2fc1b42..df3cbfb224 100644
--- a/src/mesa/drivers/dri/i965/gen6_viewport_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
@@ -154,9 +154,9 @@ static void upload_viewport_state_pointers(struct brw_context *brw)
 	     GEN6_CC_VIEWPORT_MODIFY |
 	     GEN6_SF_VIEWPORT_MODIFY |
 	     GEN6_CLIP_VIEWPORT_MODIFY);
-   OUT_RELOC(brw->clip.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
-   OUT_RELOC(brw->sf.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
-   OUT_RELOC(brw->cc.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+   OUT_RELOC(brw->clip.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+   OUT_RELOC(brw->sf.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+   OUT_RELOC(brw->cc.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
    ADVANCE_BATCH();
 
    intel_batchbuffer_emit_mi_flush(intel->batch);
-- 
cgit v1.2.3


From c8e5100a3910fd9b36d4424ef94c0581982f0b1a Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 25 Feb 2010 17:58:04 -0800
Subject: i965: Fix up the VUE handling for SNB, and hopefully clarify
 comments.

---
 src/mesa/drivers/dri/i965/brw_vs_emit.c | 74 ++++++++++++++++++++++-----------
 1 file changed, 49 insertions(+), 25 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index 4e3338293b..e0be3cc6e3 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -180,10 +180,12 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
    c->first_output = reg;
    c->first_overflow_output = 0;
 
-   if (intel->is_ironlake)
-       mrf = 8;
+   if (intel->gen >= 6)
+      mrf = 6;
+   else if (intel->is_ironlake)
+      mrf = 8;
    else
-       mrf = 4;
+      mrf = 4;
 
    for (i = 0; i < VERT_RESULT_MAX; i++) {
       if (c->prog_data.outputs_written & BITFIELD64_BIT(i)) {
@@ -1195,7 +1197,7 @@ static void emit_vertex_write( struct brw_vs_compile *c)
    struct brw_reg pos = c->regs[PROGRAM_OUTPUT][VERT_RESULT_HPOS];
    struct brw_reg ndc;
    int eot;
-   GLuint len_vertext_header = 2;
+   GLuint len_vertex_header = 2;
 
    if (c->key.copy_edgeflag) {
       brw_MOV(p, 
@@ -1203,12 +1205,14 @@ static void emit_vertex_write( struct brw_vs_compile *c)
 	      get_reg(c, PROGRAM_INPUT, VERT_ATTRIB_EDGEFLAG));
    }
 
-   /* Build ndc coords */
-   ndc = get_tmp(c);
-   /* ndc = 1.0 / pos.w */
-   emit_math1(c, BRW_MATH_FUNCTION_INV, ndc, brw_swizzle1(pos, 3), BRW_MATH_PRECISION_FULL);
-   /* ndc.xyz = pos * ndc */
-   brw_MUL(p, brw_writemask(ndc, WRITEMASK_XYZ), pos, ndc);
+   if (intel->gen < 6) {
+      /* Build ndc coords */
+      ndc = get_tmp(c);
+      /* ndc = 1.0 / pos.w */
+      emit_math1(c, BRW_MATH_FUNCTION_INV, ndc, brw_swizzle1(pos, 3), BRW_MATH_PRECISION_FULL);
+      /* ndc.xyz = pos * ndc */
+      brw_MUL(p, brw_writemask(ndc, WRITEMASK_XYZ), pos, ndc);
+   }
 
    /* Update the header for point size, user clipping flags, and -ve rhw
     * workaround.
@@ -1271,21 +1275,41 @@ static void emit_vertex_write( struct brw_vs_compile *c)
     * of zeros followed by two sets of NDC coordinates:
     */
    brw_set_access_mode(p, BRW_ALIGN_1);
-   brw_MOV(p, offset(m0, 2), ndc);
-
-   if (intel->is_ironlake || intel->gen >= 6) {
-       /* There are 20 DWs (D0-D19) in VUE vertex header on Ironlake */
-       brw_MOV(p, offset(m0, 3), pos); /* a portion of vertex header */
-       /* m4, m5 contain the distances from vertex to the user clip planeXXX. 
-        * Seems it is useless for us.
-        * m6 is used for aligning, so that the remainder of vertex element is 
-        * reg-aligned.
-        */
-       brw_MOV(p, offset(m0, 7), pos); /* the remainder of vertex element */
-       len_vertext_header = 6;
+
+   if (intel->gen >= 6) {
+      /* There are 16 DWs (D0-D15) in VUE header on Sandybridge:
+       * dword 0-3 (m1) of the header is indices, point width, clip flags.
+       * dword 4-7 (m2) is the 4D space position
+       * dword 8-15 (m3,m4) of the vertex header is the user clip distance.
+       * m5 is the first vertex data we fill, which is the vertex position.
+       */
+      brw_MOV(p, offset(m0, 2), pos);
+      brw_MOV(p, offset(m0, 5), pos);
+      len_vertex_header = 4;
+   } else if (intel->is_ironlake) {
+      /* There are 20 DWs (D0-D19) in VUE header on Ironlake:
+       * dword 0-3 (m1) of the header is indices, point width, clip flags.
+       * dword 4-7 (m2) is the ndc position (set above)
+       * dword 8-11 (m3) of the vertex header is the 4D space position
+       * dword 12-19 (m4,m5) of the vertex header is the user clip distance.
+       * m6 is a pad so that the vertex element data is aligned
+       * m7 is the first vertex data we fill, which is the vertex position.
+       */
+      brw_MOV(p, offset(m0, 2), ndc);
+      brw_MOV(p, offset(m0, 3), pos);
+      brw_MOV(p, offset(m0, 7), pos);
+      len_vertex_header = 6;
    } else {
-       brw_MOV(p, offset(m0, 3), pos);
-       len_vertext_header = 2;
+      /* There are 8 dwords in VUE header pre-Ironlake:
+       * dword 0-3 (m1) is indices, point width, clip flags.
+       * dword 4-7 (m2) is ndc position (set above)
+       *
+       * dword 8-11 (m3) is the first vertex data, which we always have be the
+       * vertex position.
+       */
+      brw_MOV(p, offset(m0, 2), ndc);
+      brw_MOV(p, offset(m0, 3), pos);
+      len_vertex_header = 2;
    }
 
    eot = (c->first_overflow_output == 0);
@@ -1296,7 +1320,7 @@ static void emit_vertex_write( struct brw_vs_compile *c)
 		 c->r0,		/* src */
 		 0,		/* allocate */
 		 1,		/* used */
-		 MIN2(c->nr_outputs + 1 + len_vertext_header, (BRW_MAX_MRF-1)), /* msg len */
+		 MIN2(c->nr_outputs + 1 + len_vertex_header, (BRW_MAX_MRF-1)), /* msg len */
 		 0,		/* response len */
 		 eot, 		/* eot */
 		 eot, 		/* writes complete */
-- 
cgit v1.2.3


From 839e6bd8b90a124e88020d54ded46460b2a3bc2d Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 25 Feb 2010 18:35:08 -0800
Subject: i965: Try to hook up the Sandybridge URB_WRITE SEND message.

My units still hang when doing this if the VS is enabled.
---
 src/mesa/drivers/dri/i965/brw_eu_emit.c | 32 +++++++++++++++++++++++++-------
 1 file changed, 25 insertions(+), 7 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 2d55299ddb..f69d529613 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -102,8 +102,6 @@ static void brw_set_dest( struct brw_instruction *insn,
 static void brw_set_src0( struct brw_instruction *insn,
                           struct brw_reg reg )
 {
-   assert(reg.file != BRW_MESSAGE_REGISTER_FILE);
-
    if (reg.type != BRW_ARCHITECTURE_REGISTER_FILE)
       assert(reg.nr < 128);
 
@@ -323,7 +321,7 @@ static void brw_set_urb_message( struct brw_context *brw,
     struct intel_context *intel = &brw->intel;
     brw_set_src1(insn, brw_imm_d(0));
 
-    if (intel->is_ironlake) {
+    if (intel->is_ironlake || intel->gen >= 6) {
         insn->bits3.urb_igdng.opcode = 0;	/* ? */
         insn->bits3.urb_igdng.offset = offset;
         insn->bits3.urb_igdng.swizzle_control = swizzle_control;
@@ -334,8 +332,16 @@ static void brw_set_urb_message( struct brw_context *brw,
         insn->bits3.urb_igdng.response_length = response_length;
         insn->bits3.urb_igdng.msg_length = msg_length;
         insn->bits3.urb_igdng.end_of_thread = end_of_thread;
-        insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_URB;
-        insn->bits2.send_igdng.end_of_thread = end_of_thread;
+	if (intel->gen >= 6) {
+	   /* For SNB, the SFID bits moved to the condmod bits, and
+	    * EOT stayed in bits3 above.  Does the EOT bit setting
+	    * below on Ironlake even do anything?
+	    */
+	   insn->header.destreg__conditionalmod = BRW_MESSAGE_TARGET_URB;
+	} else {
+	   insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_URB;
+	   insn->bits2.send_igdng.end_of_thread = end_of_thread;
+	}
     } else {
         insn->bits3.urb.opcode = 0;	/* ? */
         insn->bits3.urb.offset = offset;
@@ -1391,7 +1397,18 @@ void brw_urb_WRITE(struct brw_compile *p,
 		   GLuint offset,
 		   GLuint swizzle)
 {
-   struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
+   struct intel_context *intel = &p->brw->intel;
+   struct brw_instruction *insn;
+
+   /* Sandybridge doesn't have the implied move for SENDs,
+    * and the first message register index comes from src0.
+    */
+   if (intel->gen >= 6) {
+      brw_MOV(p, brw_message_reg(msg_reg_nr), src0);
+      src0 = brw_message_reg(msg_reg_nr);
+   }
+
+   insn = next_insn(p, BRW_OPCODE_SEND);
 
    assert(msg_length < BRW_MAX_MRF);
 
@@ -1399,7 +1416,8 @@ void brw_urb_WRITE(struct brw_compile *p,
    brw_set_src0(insn, src0);
    brw_set_src1(insn, brw_imm_d(0));
 
-   insn->header.destreg__conditionalmod = msg_reg_nr;
+   if (intel->gen < 6)
+      insn->header.destreg__conditionalmod = msg_reg_nr;
 
    brw_set_urb_message(p->brw,
 		       insn,
-- 
cgit v1.2.3


From c76d4db25260dd68684bf784efacd7323c7cab8b Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Thu, 25 Feb 2010 23:51:05 -0800
Subject: i965: Remove unnecessary headers.

---
 src/mesa/drivers/dri/i965/gen6_cc.c             | 2 --
 src/mesa/drivers/dri/i965/gen6_clip_state.c     | 3 ---
 src/mesa/drivers/dri/i965/gen6_depthstencil.c   | 4 ----
 src/mesa/drivers/dri/i965/gen6_gs_state.c       | 3 ---
 src/mesa/drivers/dri/i965/gen6_sampler_state.c  | 3 ---
 src/mesa/drivers/dri/i965/gen6_scissor_state.c  | 3 ---
 src/mesa/drivers/dri/i965/gen6_sf_state.c       | 1 -
 src/mesa/drivers/dri/i965/gen6_viewport_state.c | 2 --
 src/mesa/drivers/dri/i965/gen6_vs_state.c       | 2 --
 src/mesa/drivers/dri/i965/gen6_wm_state.c       | 2 --
 10 files changed, 25 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c
index ba1e3abe83..65e16e70c7 100644
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -30,8 +30,6 @@
 #include "brw_defines.h"
 #include "brw_util.h"
 #include "intel_batchbuffer.h"
-#include "main/macros.h"
-#include "main/enums.h"
 
 struct brw_blend_state_key {
    GLboolean color_blend, alpha_enabled;
diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c b/src/mesa/drivers/dri/i965/gen6_clip_state.c
index 9fabd05341..06f8145e32 100644
--- a/src/mesa/drivers/dri/i965/gen6_clip_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c
@@ -28,9 +28,6 @@
 #include "brw_context.h"
 #include "brw_state.h"
 #include "brw_defines.h"
-#include "brw_util.h"
-#include "main/macros.h"
-#include "main/enums.h"
 #include "intel_batchbuffer.h"
 
 static void
diff --git a/src/mesa/drivers/dri/i965/gen6_depthstencil.c b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
index 960927164c..4924f0fd55 100644
--- a/src/mesa/drivers/dri/i965/gen6_depthstencil.c
+++ b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
@@ -27,10 +27,6 @@
 
 #include "brw_context.h"
 #include "brw_state.h"
-#include "brw_defines.h"
-#include "brw_util.h"
-#include "main/macros.h"
-#include "main/enums.h"
 
 struct brw_depth_stencil_state_key {
    GLenum depth_func;
diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c
index 4032605a85..161e7b85c2 100644
--- a/src/mesa/drivers/dri/i965/gen6_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c
@@ -28,9 +28,6 @@
 #include "brw_context.h"
 #include "brw_state.h"
 #include "brw_defines.h"
-#include "brw_util.h"
-#include "main/macros.h"
-#include "main/enums.h"
 #include "intel_batchbuffer.h"
 
 static void
diff --git a/src/mesa/drivers/dri/i965/gen6_sampler_state.c b/src/mesa/drivers/dri/i965/gen6_sampler_state.c
index f5d537b1cf..ab8e7516d2 100644
--- a/src/mesa/drivers/dri/i965/gen6_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sampler_state.c
@@ -28,10 +28,7 @@
 #include "brw_context.h"
 #include "brw_state.h"
 #include "brw_defines.h"
-#include "brw_util.h"
 #include "intel_batchbuffer.h"
-#include "main/macros.h"
-#include "main/enums.h"
 
 static void
 upload_sampler_state_pointers(struct brw_context *brw)
diff --git a/src/mesa/drivers/dri/i965/gen6_scissor_state.c b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
index 81ebbf4ddf..2e21e5f733 100644
--- a/src/mesa/drivers/dri/i965/gen6_scissor_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
@@ -28,10 +28,7 @@
 #include "brw_context.h"
 #include "brw_state.h"
 #include "brw_defines.h"
-#include "brw_util.h"
 #include "intel_batchbuffer.h"
-#include "main/macros.h"
-#include "main/enums.h"
 
 static void
 prepare_scissor_state(struct brw_context *brw)
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 548cdb9fca..08e6753a91 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -30,7 +30,6 @@
 #include "brw_defines.h"
 #include "brw_util.h"
 #include "main/macros.h"
-#include "main/enums.h"
 #include "intel_batchbuffer.h"
 
 static void
diff --git a/src/mesa/drivers/dri/i965/gen6_viewport_state.c b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
index df3cbfb224..0c2aa4206c 100644
--- a/src/mesa/drivers/dri/i965/gen6_viewport_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
@@ -28,10 +28,8 @@
 #include "brw_context.h"
 #include "brw_state.h"
 #include "brw_defines.h"
-#include "brw_util.h"
 #include "intel_batchbuffer.h"
 #include "main/macros.h"
-#include "main/enums.h"
 
 /* The clip VP defines the guardband region where expensive clipping is skipped
  * and fragments are allowed to be generated and clipped out cheaply by the SF.
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 04fc16e679..211a6231c9 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -29,8 +29,6 @@
 #include "brw_state.h"
 #include "brw_defines.h"
 #include "brw_util.h"
-#include "main/macros.h"
-#include "main/enums.h"
 #include "shader/prog_parameter.h"
 #include "shader/prog_statevars.h"
 #include "intel_batchbuffer.h"
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index f4ae7ed750..e355261769 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -29,8 +29,6 @@
 #include "brw_state.h"
 #include "brw_defines.h"
 #include "brw_util.h"
-#include "main/macros.h"
-#include "main/enums.h"
 #include "shader/prog_parameter.h"
 #include "shader/prog_statevars.h"
 #include "intel_batchbuffer.h"
-- 
cgit v1.2.3


From cb099c2ecfe3cf8d8ff21c3031e3c2d43efd0e69 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Tue, 2 Mar 2010 07:47:56 -0700
Subject: i965: include macros.h to get CLAMP macro

---
 src/mesa/drivers/dri/i965/gen6_cc.c | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c
index 65e16e70c7..42b41f3210 100644
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -30,6 +30,7 @@
 #include "brw_defines.h"
 #include "brw_util.h"
 #include "intel_batchbuffer.h"
+#include "main/macros.h"
 
 struct brw_blend_state_key {
    GLboolean color_blend, alpha_enabled;
-- 
cgit v1.2.3


From a3593833dc2c14948c41654ed015c91634a78af3 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 2 Mar 2010 10:27:51 -0800
Subject: i965: Fix up Sandybridge VS sizing.

---
 src/mesa/drivers/dri/i965/brw_vs_emit.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index e0be3cc6e3..a7c4b58972 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -281,10 +281,12 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
     */
    attributes_in_vue = MAX2(c->nr_outputs, c->nr_inputs);
 
-   if (intel->is_ironlake || intel->gen >= 6)
-       c->prog_data.urb_entry_size = (attributes_in_vue + 6 + 3) / 4;
+   if (intel->gen >= 6)
+      c->prog_data.urb_entry_size = (attributes_in_vue + 4 + 7) / 8;
+   else if (intel->is_ironlake)
+      c->prog_data.urb_entry_size = (attributes_in_vue + 6 + 3) / 4;
    else
-       c->prog_data.urb_entry_size = (attributes_in_vue + 2 + 3) / 4;
+      c->prog_data.urb_entry_size = (attributes_in_vue + 2 + 3) / 4;
 
    c->prog_data.total_grf = reg;
 
-- 
cgit v1.2.3


From bb35000b4b6dfe60048b2f5d60bc102c4a7fd791 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 4 Mar 2010 15:47:19 -0800
Subject: intel: Remove non-kernel-exec-fencing support.

Shaves 60k off the driver from removing the broken spans code.  This
means we now require 2.6.29, which seems fair given that it's a year
old and we've removed support for non-KMS already in the last release
of 2D.
---
 src/mesa/drivers/dri/i965/brw_curbe.c             |   5 +-
 src/mesa/drivers/dri/i965/brw_draw_upload.c       |  63 +--
 src/mesa/drivers/dri/i965/brw_vs_surface_state.c  |   4 +-
 src/mesa/drivers/dri/i965/brw_vtbl.c              |   2 +-
 src/mesa/drivers/dri/i965/gen6_vs_state.c         |   4 +-
 src/mesa/drivers/dri/i965/gen6_wm_state.c         |   4 +-
 src/mesa/drivers/dri/intel/intel_blit.c           |   8 +-
 src/mesa/drivers/dri/intel/intel_buffer_objects.c |   8 +-
 src/mesa/drivers/dri/intel/intel_context.c        |   6 -
 src/mesa/drivers/dri/intel/intel_context.h        |  21 -
 src/mesa/drivers/dri/intel/intel_depthtmp.h       |  64 ---
 src/mesa/drivers/dri/intel/intel_fbo.c            |   3 -
 src/mesa/drivers/dri/intel/intel_fbo.h            |   3 -
 src/mesa/drivers/dri/intel/intel_mipmap_tree.c    |   3 +-
 src/mesa/drivers/dri/intel/intel_regions.c        |   6 +-
 src/mesa/drivers/dri/intel/intel_screen.c         |   9 +-
 src/mesa/drivers/dri/intel/intel_screen.h         |   1 -
 src/mesa/drivers/dri/intel/intel_span.c           | 451 +++-------------------
 src/mesa/drivers/dri/intel/intel_spantmp.h        |  67 ----
 19 files changed, 94 insertions(+), 638 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/intel/intel_depthtmp.h
 delete mode 100644 src/mesa/drivers/dri/intel/intel_spantmp.h

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index 6f2ead793d..4e78b08cfe 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -179,7 +179,6 @@ static GLfloat fixed_plane[6][4] = {
  */
 static void prepare_constant_buffer(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
    GLcontext *ctx = &brw->intel.ctx;
    const struct brw_vertex_program *vp =
       brw_vertex_program_const(brw->vertex_program);
@@ -307,7 +306,7 @@ static void prepare_constant_buffer(struct brw_context *brw)
       if (brw->curbe.curbe_bo != NULL &&
 	  brw->curbe.curbe_next_offset + bufsz > brw->curbe.curbe_bo->size)
       {
-	 intel_bo_unmap_gtt_preferred(intel, brw->curbe.curbe_bo);
+	 drm_intel_gem_bo_unmap_gtt(brw->curbe.curbe_bo);
 	 dri_bo_unreference(brw->curbe.curbe_bo);
 	 brw->curbe.curbe_bo = NULL;
       }
@@ -319,7 +318,7 @@ static void prepare_constant_buffer(struct brw_context *brw)
 	 brw->curbe.curbe_bo = dri_bo_alloc(brw->intel.bufmgr, "CURBE",
 					    4096, 1 << 6);
 	 brw->curbe.curbe_next_offset = 0;
-	 intel_bo_map_gtt_preferred(intel, brw->curbe.curbe_bo, GL_TRUE);
+	 drm_intel_gem_bo_map_gtt(brw->curbe.curbe_bo);
       }
 
       brw->curbe.curbe_offset = brw->curbe.curbe_next_offset;
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index f0a4e8ad65..71a43577bf 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -276,7 +276,6 @@ copy_array_to_vbo_array( struct brw_context *brw,
 			 struct brw_vertex_element *element,
 			 GLuint dst_stride)
 {
-   struct intel_context *intel = &brw->intel;
    GLuint size = element->count * dst_stride;
 
    get_space(brw, size, &element->bo, &element->offset);
@@ -289,52 +288,26 @@ copy_array_to_vbo_array( struct brw_context *brw,
    }
 
    if (dst_stride == element->glarray->StrideB) {
-      if (intel->intelScreen->kernel_exec_fencing) {
-	 drm_intel_gem_bo_map_gtt(element->bo);
-	 memcpy((char *)element->bo->virtual + element->offset,
-		element->glarray->Ptr, size);
-	 drm_intel_gem_bo_unmap_gtt(element->bo);
-      } else {
-	 dri_bo_subdata(element->bo,
-			element->offset,
-			size,
-			element->glarray->Ptr);
-      }
+      drm_intel_gem_bo_map_gtt(element->bo);
+      memcpy((char *)element->bo->virtual + element->offset,
+	     element->glarray->Ptr, size);
+      drm_intel_gem_bo_unmap_gtt(element->bo);
    } else {
       char *dest;
       const unsigned char *src = element->glarray->Ptr;
       int i;
 
-      if (intel->intelScreen->kernel_exec_fencing) {
-	 drm_intel_gem_bo_map_gtt(element->bo);
-	 dest = element->bo->virtual;
-	 dest += element->offset;
-
-	 for (i = 0; i < element->count; i++) {
-	    memcpy(dest, src, dst_stride);
-	    src += element->glarray->StrideB;
-	    dest += dst_stride;
-	 }
-
-	 drm_intel_gem_bo_unmap_gtt(element->bo);
-      } else {
-	 void *data;
-
-	 data = malloc(dst_stride * element->count);
-	 dest = data;
-	 for (i = 0; i < element->count; i++) {
-	    memcpy(dest, src, dst_stride);
-	    src += element->glarray->StrideB;
-	    dest += dst_stride;
-	 }
-
-	 dri_bo_subdata(element->bo,
-			element->offset,
-			size,
-			data);
+      drm_intel_gem_bo_map_gtt(element->bo);
+      dest = element->bo->virtual;
+      dest += element->offset;
 
-	 free(data);
+      for (i = 0; i < element->count; i++) {
+	 memcpy(dest, src, dst_stride);
+	 src += element->glarray->StrideB;
+	 dest += dst_stride;
       }
+
+      drm_intel_gem_bo_unmap_gtt(element->bo);
    }
 }
 
@@ -646,13 +619,9 @@ static void brw_prepare_indices(struct brw_context *brw)
 
       /* Straight upload
        */
-      if (intel->intelScreen->kernel_exec_fencing) {
-	 drm_intel_gem_bo_map_gtt(bo);
-	 memcpy((char *)bo->virtual + offset, index_buffer->ptr, ib_size);
-	 drm_intel_gem_bo_unmap_gtt(bo);
-      } else {
-	 dri_bo_subdata(bo, offset, ib_size, index_buffer->ptr);
-      }
+      drm_intel_gem_bo_map_gtt(bo);
+      memcpy((char *)bo->virtual + offset, index_buffer->ptr, ib_size);
+      drm_intel_gem_bo_unmap_gtt(bo);
    } else {
       offset = (GLuint) (unsigned long) index_buffer->ptr;
       brw->ib.start_vertex_offset = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
index ead623fc0e..950d075aa1 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
@@ -67,13 +67,13 @@ brw_vs_update_constant_buffer(struct brw_context *brw)
     */
    _mesa_load_state_parameters(&brw->intel.ctx, vp->program.Base.Parameters);
 
-   intel_bo_map_gtt_preferred(intel, const_buffer, GL_TRUE);
+   drm_intel_gem_bo_map_gtt(const_buffer);
    for (i = 0; i < params->NumParameters; i++) {
       memcpy(const_buffer->virtual + i * 4 * sizeof(float),
 	     params->ParameterValues[i],
 	     4 * sizeof(float));
    }
-   intel_bo_unmap_gtt_preferred(intel, const_buffer);
+   drm_intel_gem_bo_unmap_gtt(const_buffer);
 
    return const_buffer;
 }
diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index 27a2a3e8a7..96a44bfbec 100644
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -144,7 +144,7 @@ static void brw_finish_batch(struct intel_context *intel)
    brw_emit_query_end(brw);
 
    if (brw->curbe.curbe_bo) {
-      intel_bo_unmap_gtt_preferred(intel, brw->curbe.curbe_bo);
+      drm_intel_gem_bo_unmap_gtt(brw->curbe.curbe_bo);
       drm_intel_bo_unreference(brw->curbe.curbe_bo);
       brw->curbe.curbe_bo = NULL;
    }
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 211a6231c9..fe597dfb94 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -65,13 +65,13 @@ upload_vs_state(struct brw_context *brw)
       constant_bo = drm_intel_bo_alloc(intel->bufmgr, "VS constant_bo",
 				       nr_params * 4 * sizeof(float),
 				       4096);
-      intel_bo_map_gtt_preferred(intel, constant_bo, GL_TRUE);
+      drm_intel_gem_bo_map_gtt(constant_bo);
       for (i = 0; i < nr_params; i++) {
 	 memcpy((char *)constant_bo->virtual + i * 4 * sizeof(float),
 		vp->program.Base.Parameters->ParameterValues[i],
 		4 * sizeof(float));
       }
-      intel_bo_unmap_gtt_preferred(intel, constant_bo);
+      drm_intel_gem_bo_unmap_gtt(constant_bo);
 
       BEGIN_BATCH(5);
       OUT_BATCH(CMD_3D_CONSTANT_VS_STATE << 16 |
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index e355261769..1eb17ca627 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -63,13 +63,13 @@ upload_wm_state(struct brw_context *brw)
       constant_bo = drm_intel_bo_alloc(intel->bufmgr, "WM constant_bo",
 				       nr_params * 4 * sizeof(float),
 				       4096);
-      intel_bo_map_gtt_preferred(intel, constant_bo, GL_TRUE);
+      drm_intel_gem_bo_map_gtt(constant_bo);
       for (i = 0; i < nr_params; i++) {
 	 memcpy((char *)constant_bo->virtual + i * 4 * sizeof(float),
 		fp->program.Base.Parameters->ParameterValues[i],
 		4 * sizeof(float));
       }
-      intel_bo_unmap_gtt_preferred(intel, constant_bo);
+      drm_intel_gem_bo_unmap_gtt(constant_bo);
 
       BEGIN_BATCH(5);
       OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 |
diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c
index 6d6af86347..f2769aa3e8 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -122,8 +122,8 @@ intelEmitCopyBlit(struct intel_context *intel,
    intel_prepare_render(intel);
 
    if (pass >= 2) {
-      intel_bo_map_gtt_preferred(intel, dst_buffer, GL_TRUE);
-      intel_bo_map_gtt_preferred(intel, src_buffer, GL_FALSE);
+      drm_intel_gem_bo_map_gtt(dst_buffer);
+      drm_intel_gem_bo_map_gtt(src_buffer);
       _mesa_copy_rect((GLubyte *)dst_buffer->virtual + dst_offset,
 		      cpp,
 		      dst_pitch,
@@ -132,8 +132,8 @@ intelEmitCopyBlit(struct intel_context *intel,
 		      (GLubyte *)src_buffer->virtual + src_offset,
 		      src_pitch,
 		      src_x, src_y);
-      intel_bo_unmap_gtt_preferred(intel, src_buffer);
-      intel_bo_unmap_gtt_preferred(intel, dst_buffer);
+      drm_intel_gem_bo_unmap_gtt(src_buffer);
+      drm_intel_gem_bo_unmap_gtt(dst_buffer);
 
       return GL_TRUE;
    }
diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.c b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
index 312866d865..8fe3a0e6f3 100644
--- a/src/mesa/drivers/dri/intel/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
@@ -285,7 +285,7 @@ intel_bufferobj_map(GLcontext * ctx,
       return NULL;
    }
 
-   if (write_only && intel->intelScreen->kernel_exec_fencing) {
+   if (write_only) {
       drm_intel_gem_bo_map_gtt(intel_obj->buffer);
       intel_obj->mapped_gtt = GL_TRUE;
    } else {
@@ -379,8 +379,7 @@ intel_bufferobj_map_range(GLcontext * ctx,
 	 intel_obj->range_map_bo = drm_intel_bo_alloc(intel->bufmgr,
 						      "range map",
 						      length, 64);
-	 if (!(access & GL_MAP_READ_BIT) &&
-	     intel->intelScreen->kernel_exec_fencing) {
+	 if (!(access & GL_MAP_READ_BIT)) {
 	    drm_intel_gem_bo_map_gtt(intel_obj->range_map_bo);
 	    intel_obj->mapped_gtt = GL_TRUE;
 	 } else {
@@ -393,8 +392,7 @@ intel_bufferobj_map_range(GLcontext * ctx,
       return obj->Pointer;
    }
 
-   if (!(access & GL_MAP_READ_BIT) &&
-       intel->intelScreen->kernel_exec_fencing) {
+   if (!(access & GL_MAP_READ_BIT)) {
       drm_intel_gem_bo_map_gtt(intel_obj->buffer);
       intel_obj->mapped_gtt = GL_TRUE;
    } else {
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index ec379a77ac..d6a1ba6952 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -755,12 +755,6 @@ intelInitContext(struct intel_context *intel,
    }
    intel->use_texture_tiling = driQueryOptionb(&intel->optionCache,
 					       "texture_tiling");
-   if (intel->use_texture_tiling &&
-       !intel->intelScreen->kernel_exec_fencing) {
-      fprintf(stderr, "No kernel support for execution fencing, "
-	      "disabling texture tiling\n");
-      intel->use_texture_tiling = GL_FALSE;
-   }
    intel->use_early_z = driQueryOptionb(&intel->optionCache, "early_z");
 
    intel->prim.primitive = ~0;
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index d20d44497e..22736a9327 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -475,25 +475,4 @@ is_power_of_two(uint32_t value)
    return (value & (value - 1)) == 0;
 }
 
-static INLINE void
-intel_bo_map_gtt_preferred(struct intel_context *intel,
-			   drm_intel_bo *bo,
-			   GLboolean write)
-{
-   if (intel->intelScreen->kernel_exec_fencing)
-      drm_intel_gem_bo_map_gtt(bo);
-   else
-      drm_intel_bo_map(bo, write);
-}
-
-static INLINE void
-intel_bo_unmap_gtt_preferred(struct intel_context *intel,
-			     drm_intel_bo *bo)
-{
-   if (intel->intelScreen->kernel_exec_fencing)
-      drm_intel_gem_bo_unmap_gtt(bo);
-   else
-      drm_intel_bo_unmap(bo);
-}
-
 #endif
diff --git a/src/mesa/drivers/dri/intel/intel_depthtmp.h b/src/mesa/drivers/dri/intel/intel_depthtmp.h
deleted file mode 100644
index a9c75d44cf..0000000000
--- a/src/mesa/drivers/dri/intel/intel_depthtmp.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *    Eric Anholt <eric@anholt.net>
- *
- */
-
-/**
- * Wrapper around the depthtmp.h macrofest to generate spans code for
- * all the tiling styles.
- */
-
-#define VALUE_TYPE INTEL_VALUE_TYPE
-#define WRITE_DEPTH(_x, _y, d) \
-   (*(INTEL_VALUE_TYPE *)(irb->region->buffer->virtual +	\
-			  NO_TILE(_x, _y)) = d)
-#define READ_DEPTH(d, _x, _y) \
-   d = *(INTEL_VALUE_TYPE *)(irb->region->buffer->virtual +	\
-			     NO_TILE(_x, _y))
-#define TAG(x) INTEL_TAG(intel_gttmap_##x)
-#include "depthtmp.h"
-
-#define VALUE_TYPE INTEL_VALUE_TYPE
-#define WRITE_DEPTH(_x, _y, d) INTEL_WRITE_DEPTH(NO_TILE(_x, _y), d)
-#define READ_DEPTH(d, _x, _y) d = INTEL_READ_DEPTH(NO_TILE(_x, _y))
-#define TAG(x) INTEL_TAG(intel##x)
-#include "depthtmp.h"
-
-#define VALUE_TYPE INTEL_VALUE_TYPE
-#define WRITE_DEPTH(_x, _y, d) INTEL_WRITE_DEPTH(X_TILE(_x, _y), d)
-#define READ_DEPTH(d, _x, _y) d = INTEL_READ_DEPTH(X_TILE(_x, _y))
-#define TAG(x) INTEL_TAG(intel_XTile_##x)
-#include "depthtmp.h"
-
-#define VALUE_TYPE INTEL_VALUE_TYPE
-#define WRITE_DEPTH(_x, _y, d) INTEL_WRITE_DEPTH(Y_TILE(_x, _y), d)
-#define READ_DEPTH(d, _x, _y) d = INTEL_READ_DEPTH(Y_TILE(_x, _y))
-#define TAG(x) INTEL_TAG(intel_YTile_##x)
-#include "depthtmp.h"
-
-#undef INTEL_VALUE_TYPE
-#undef INTEL_WRITE_DEPTH
-#undef INTEL_READ_DEPTH
-#undef INTEL_TAG
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index b388a3de2e..a429f8d003 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -70,9 +70,6 @@ intel_delete_renderbuffer(struct gl_renderbuffer *rb)
 
    ASSERT(irb);
 
-   if (irb->span_cache != NULL)
-      free(irb->span_cache);
-
    if (intel && irb->region) {
       intel_region_release(&irb->region);
    }
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h
index 586dbbbb25..72413f7369 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -40,9 +40,6 @@ struct intel_renderbuffer
 {
    struct gl_renderbuffer Base;
    struct intel_region *region;
-
-   uint8_t *span_cache;
-   unsigned long span_cache_offset;
 };
 
 
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index a20ea5afdb..4f14946ec7 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -119,8 +119,7 @@ intel_miptree_create(struct intel_context *intel,
    struct intel_mipmap_tree *mt;
    uint32_t tiling;
 
-   if (intel->use_texture_tiling && compress_byte == 0 &&
-       intel->intelScreen->kernel_exec_fencing) {
+   if (intel->use_texture_tiling && compress_byte == 0) {
       if (intel->gen >= 4 &&
 	  (base_format == GL_DEPTH_COMPONENT ||
 	   base_format == GL_DEPTH_STENCIL_EXT))
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index e3c0635e5b..f042bcbc28 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -118,8 +118,7 @@ intel_region_map(struct intel_context *intel, struct intel_region *region)
       if (region->pbo)
          intel_region_cow(intel, region);
 
-      if (region->tiling != I915_TILING_NONE &&
-	  intel->intelScreen->kernel_exec_fencing)
+      if (region->tiling != I915_TILING_NONE)
 	 drm_intel_gem_bo_map_gtt(region->buffer);
       else
 	 dri_bo_map(region->buffer, GL_TRUE);
@@ -134,8 +133,7 @@ intel_region_unmap(struct intel_context *intel, struct intel_region *region)
 {
    _DBG("%s %p\n", __FUNCTION__, region);
    if (!--region->map_refcount) {
-      if (region->tiling != I915_TILING_NONE &&
-	  intel->intelScreen->kernel_exec_fencing)
+      if (region->tiling != I915_TILING_NONE)
 	 drm_intel_gem_bo_unmap_gtt(region->buffer);
       else
 	 dri_bo_unmap(region->buffer);
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 959ccfb8b1..9ff76c4803 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -416,10 +416,11 @@ intel_init_bufmgr(struct intel_screen *intelScreen)
       return GL_FALSE;
    }
 
-   if (intel_get_param(spriv, I915_PARAM_NUM_FENCES_AVAIL, &num_fences))
-      intelScreen->kernel_exec_fencing = !!num_fences;
-   else
-      intelScreen->kernel_exec_fencing = GL_FALSE;
+   if (!intel_get_param(spriv, I915_PARAM_NUM_FENCES_AVAIL, &num_fences) ||
+       num_fences == 0) {
+      fprintf(stderr, "[%s: %u] Kernel 2.6.29 required.\n", __func__, __LINE__);
+      return GL_FALSE;
+   }
 
    drm_intel_bufmgr_gem_enable_fenced_relocs(intelScreen->bufmgr);
 
diff --git a/src/mesa/drivers/dri/intel/intel_screen.h b/src/mesa/drivers/dri/intel/intel_screen.h
index 1ce476daca..5863093f00 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.h
+++ b/src/mesa/drivers/dri/intel/intel_screen.h
@@ -46,7 +46,6 @@ struct intel_screen
 
    GLboolean no_vbo;
    dri_bufmgr *bufmgr;
-   GLboolean kernel_exec_fencing;
    struct _mesa_HashTable *named_regions;
 
    /**
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 2fcb2d843c..fb5c01bc4d 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -43,218 +43,6 @@ static void
 intel_set_span_functions(struct intel_context *intel,
 			 struct gl_renderbuffer *rb);
 
-#define SPAN_CACHE_SIZE		4096
-
-static void
-get_span_cache(struct intel_renderbuffer *irb, uint32_t offset)
-{
-   if (irb->span_cache == NULL) {
-      irb->span_cache = malloc(SPAN_CACHE_SIZE);
-      irb->span_cache_offset = -1;
-   }
-
-   if ((offset & ~(SPAN_CACHE_SIZE - 1)) != irb->span_cache_offset) {
-      irb->span_cache_offset = offset & ~(SPAN_CACHE_SIZE - 1);
-      dri_bo_get_subdata(irb->region->buffer, irb->span_cache_offset,
-			 SPAN_CACHE_SIZE, irb->span_cache);
-   }
-}
-
-static void
-clear_span_cache(struct intel_renderbuffer *irb)
-{
-   irb->span_cache_offset = -1;
-}
-
-static uint32_t
-pread_32(struct intel_renderbuffer *irb, uint32_t offset)
-{
-   get_span_cache(irb, offset);
-
-   return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
-}
-
-static uint32_t
-pread_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset)
-{
-   get_span_cache(irb, offset);
-
-   return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))) |
-      0xff000000;
-}
-
-static uint16_t
-pread_16(struct intel_renderbuffer *irb, uint32_t offset)
-{
-   get_span_cache(irb, offset);
-
-   return *(uint16_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
-}
-
-static uint8_t
-pread_8(struct intel_renderbuffer *irb, uint32_t offset)
-{
-   get_span_cache(irb, offset);
-
-   return *(uint8_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
-}
-
-static void
-pwrite_32(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
-{
-   clear_span_cache(irb);
-
-   dri_bo_subdata(irb->region->buffer, offset, 4, &val);
-}
-
-static void
-pwrite_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
-{
-   clear_span_cache(irb);
-
-   dri_bo_subdata(irb->region->buffer, offset, 3, &val);
-}
-
-static void
-pwrite_16(struct intel_renderbuffer *irb, uint32_t offset, uint16_t val)
-{
-   clear_span_cache(irb);
-
-   dri_bo_subdata(irb->region->buffer, offset, 2, &val);
-}
-
-static void
-pwrite_8(struct intel_renderbuffer *irb, uint32_t offset, uint8_t val)
-{
-   clear_span_cache(irb);
-
-   dri_bo_subdata(irb->region->buffer, offset, 1, &val);
-}
-
-static uint32_t no_tile_swizzle(struct intel_renderbuffer *irb,
-				int x, int y)
-{
-	return (y * irb->region->pitch + x) * irb->region->cpp;
-}
-
-/*
- * Deal with tiled surfaces
- */
-
-static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb,
-			       int x, int y)
-{
-	int	tile_stride;
-	int	xbyte;
-	int	x_tile_off, y_tile_off;
-	int	x_tile_number, y_tile_number;
-	int	tile_off, tile_base;
-	
-        x += irb->region->draw_x;
-        y += irb->region->draw_y;
-
-	tile_stride = (irb->region->pitch * irb->region->cpp) << 3;
-
-	xbyte = x * irb->region->cpp;
-
-	x_tile_off = xbyte & 0x1ff;
-	y_tile_off = y & 7;
-
-	x_tile_number = xbyte >> 9;
-	y_tile_number = y >> 3;
-
-	tile_off = (y_tile_off << 9) + x_tile_off;
-
-	switch (irb->region->bit_6_swizzle) {
-	case I915_BIT_6_SWIZZLE_NONE:
-	   break;
-	case I915_BIT_6_SWIZZLE_9:
-	   tile_off ^= ((tile_off >> 3) & 64);
-	   break;
-	case I915_BIT_6_SWIZZLE_9_10:
-	   tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
-	   break;
-	case I915_BIT_6_SWIZZLE_9_11:
-	   tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
-	   break;
-	case I915_BIT_6_SWIZZLE_9_10_11:
-	   tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
-	      ((tile_off >> 5) & 64);
-	   break;
-	default:
-	   fprintf(stderr, "Unknown tile swizzling mode %d\n",
-		   irb->region->bit_6_swizzle);
-	   exit(1);
-	}
-
-	tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
-
-#if 0
-	printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
-	       x, y, tile_off, tile_base,
-	       tile_off + tile_base,
-	       irb->region->pitch, tile_stride);
-#endif
-
-	return tile_base + tile_off;
-}
-
-static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
-			       int x, int y)
-{
-	int	tile_stride;
-	int	xbyte;
-	int	x_tile_off, y_tile_off;
-	int	x_tile_number, y_tile_number;
-	int	tile_off, tile_base;
-	
-        x += irb->region->draw_x;
-        y += irb->region->draw_y;
-
-	tile_stride = (irb->region->pitch * irb->region->cpp) << 5;
-
-	xbyte = x * irb->region->cpp;
-
-	x_tile_off = xbyte & 0x7f;
-	y_tile_off = y & 0x1f;
-
-	x_tile_number = xbyte >> 7;
-	y_tile_number = y >> 5;
-
-	tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
-	   (x_tile_off & 0xf);
-
-	switch (irb->region->bit_6_swizzle) {
-	case I915_BIT_6_SWIZZLE_NONE:
-	   break;
-	case I915_BIT_6_SWIZZLE_9:
-	   tile_off ^= ((tile_off >> 3) & 64);
-	   break;
-	case I915_BIT_6_SWIZZLE_9_10:
-	   tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
-	   break;
-	case I915_BIT_6_SWIZZLE_9_11:
-	   tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
-	   break;
-	case I915_BIT_6_SWIZZLE_9_10_11:
-	   tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
-	      ((tile_off >> 5) & 64);
-	   break;
-	default:
-	   fprintf(stderr, "Unknown tile swizzling mode %d\n",
-		   irb->region->bit_6_swizzle);
-	   exit(1);
-	}
-
-	tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
-
-	return tile_base + tile_off;
-}
-
-/*
-  break intelWriteRGBASpan_ARGB8888
-*/
-
 #undef DBG
 #define DBG 0
 
@@ -280,50 +68,43 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
 
 #define HW_UNLOCK()
 
-/* Convenience macros to avoid typing the swizzle argument over and over */
-#define NO_TILE(_X, _Y) no_tile_swizzle(irb, (_X), (_Y))
-#define X_TILE(_X, _Y) x_tile_swizzle(irb, (_X), (_Y))
-#define Y_TILE(_X, _Y) y_tile_swizzle(irb, (_X), (_Y))
+/* Convenience macros to avoid typing the address argument over and over */
+#define NO_TILE(_X, _Y) (((_Y) * irb->region->pitch + (_X)) * irb->region->cpp)
 
 /* r5g6b5 color span and pixel functions */
-#define INTEL_PIXEL_FMT GL_RGB
-#define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
-#define INTEL_READ_VALUE(offset) pread_16(irb, offset)
-#define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
-#define INTEL_TAG(x) x##_RGB565
-#include "intel_spantmp.h"
+#define SPANTMP_PIXEL_FMT GL_RGB
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
+#define TAG(x) intel_##x##_RGB565
+#define TAG2(x,y) intel_##x##y_RGB565
+#include "spantmp2.h"
 
 /* a4r4g4b4 color span and pixel functions */
-#define INTEL_PIXEL_FMT GL_BGRA
-#define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4_REV
-#define INTEL_READ_VALUE(offset) pread_16(irb, offset)
-#define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
-#define INTEL_TAG(x) x##_ARGB4444
-#include "intel_spantmp.h"
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4_REV
+#define TAG(x) intel_##x##_ARGB4444
+#define TAG2(x,y) intel_##x##y_ARGB4444
+#include "spantmp2.h"
 
 /* a1r5g5b5 color span and pixel functions */
-#define INTEL_PIXEL_FMT GL_BGRA
-#define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5_REV
-#define INTEL_READ_VALUE(offset) pread_16(irb, offset)
-#define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
-#define INTEL_TAG(x) x##_ARGB1555
-#include "intel_spantmp.h"
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5_REV
+#define TAG(x) intel_##x##_ARGB1555
+#define TAG2(x,y) intel_##x##y##_ARGB1555
+#include "spantmp2.h"
 
 /* a8r8g8b8 color span and pixel functions */
-#define INTEL_PIXEL_FMT GL_BGRA
-#define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
-#define INTEL_READ_VALUE(offset) pread_32(irb, offset)
-#define INTEL_WRITE_VALUE(offset, v) pwrite_32(irb, offset, v)
-#define INTEL_TAG(x) x##_ARGB8888
-#include "intel_spantmp.h"
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
+#define TAG(x) intel_##x##_ARGB8888
+#define TAG2(x,y) intel_##x##y##_ARGB8888
+#include "spantmp2.h"
 
 /* x8r8g8b8 color span and pixel functions */
-#define INTEL_PIXEL_FMT GL_BGR
-#define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
-#define INTEL_READ_VALUE(offset) pread_xrgb8888(irb, offset)
-#define INTEL_WRITE_VALUE(offset, v) pwrite_xrgb8888(irb, offset, v)
-#define INTEL_TAG(x) x##_xRGB8888
-#include "intel_spantmp.h"
+#define SPANTMP_PIXEL_FMT GL_BGR
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
+#define TAG(x) intel_##x##_xRGB8888
+#define TAG2(x,y) intel_##x##y##_xRGB8888
+#include "spantmp2.h"
 
 #define LOCAL_DEPTH_VARS						\
    struct intel_renderbuffer *irb = intel_renderbuffer(rb);		\
@@ -339,18 +120,22 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
 
 /* z16 depthbuffer functions. */
-#define INTEL_VALUE_TYPE GLushort
-#define INTEL_WRITE_DEPTH(offset, d) pwrite_16(irb, offset, d)
-#define INTEL_READ_DEPTH(offset) pread_16(irb, offset)
-#define INTEL_TAG(name) name##_z16
-#include "intel_depthtmp.h"
-
-/* z24x8 depthbuffer functions. */
-#define INTEL_VALUE_TYPE GLuint
-#define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, d)
-#define INTEL_READ_DEPTH(offset) pread_32(irb, offset)
-#define INTEL_TAG(name) name##_z24_x8
-#include "intel_depthtmp.h"
+#define VALUE_TYPE GLushort
+#define WRITE_DEPTH(_x, _y, d) \
+   (*(uint16_t *)(irb->region->buffer->virtual + NO_TILE(_x, _y)) = d)
+#define READ_DEPTH(d, _x, _y) \
+   d = *(uint16_t *)(irb->region->buffer->virtual + NO_TILE(_x, _y))
+#define TAG(x) intel_##x##_z16
+#include "depthtmp.h"
+
+/* z24_s8 and z24_x8 depthbuffer functions. */
+#define VALUE_TYPE GLuint
+#define WRITE_DEPTH(_x, _y, d) \
+   (*(uint32_t *)(irb->region->buffer->virtual + NO_TILE(_x, _y)) = d)
+#define READ_DEPTH(d, _x, _y) \
+   d = *(uint32_t *)(irb->region->buffer->virtual + NO_TILE(_x, _y))
+#define TAG(x) intel_##x##_z24_x8
+#include "depthtmp.h"
 
 void
 intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
@@ -360,8 +145,7 @@ intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
    if (irb == NULL || irb->region == NULL)
       return;
 
-   if (intel->intelScreen->kernel_exec_fencing)
-      drm_intel_gem_bo_map_gtt(irb->region->buffer);
+   drm_intel_gem_bo_map_gtt(irb->region->buffer);
 
    intel_set_span_functions(intel, rb);
 }
@@ -375,10 +159,7 @@ intel_renderbuffer_unmap(struct intel_context *intel,
    if (irb == NULL || irb->region == NULL)
       return;
 
-   if (intel->intelScreen->kernel_exec_fencing)
-      drm_intel_gem_bo_unmap_gtt(irb->region->buffer);
-   else
-      clear_span_cache(irb);
+   drm_intel_gem_bo_unmap_gtt(irb->region->buffer);
 
    rb->GetRow = NULL;
    rb->PutRow = NULL;
@@ -558,158 +339,34 @@ intel_set_span_functions(struct intel_context *intel,
 			 struct gl_renderbuffer *rb)
 {
    struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
-   uint32_t tiling = irb->region->tiling;
-
-   if (intel->intelScreen->kernel_exec_fencing) {
-      switch (irb->Base.Format) {
-      case MESA_FORMAT_RGB565:
-	 intel_gttmap_InitPointers_RGB565(rb);
-	 break;
-      case MESA_FORMAT_ARGB4444:
-	 intel_gttmap_InitPointers_ARGB4444(rb);
-	 break;
-      case MESA_FORMAT_ARGB1555:
-	 intel_gttmap_InitPointers_ARGB1555(rb);
-	 break;
-      case MESA_FORMAT_XRGB8888:
-         intel_gttmap_InitPointers_xRGB8888(rb);
-	 break;
-      case MESA_FORMAT_ARGB8888:
-	 intel_gttmap_InitPointers_ARGB8888(rb);
-	 break;
-      case MESA_FORMAT_Z16:
-	 intel_gttmap_InitDepthPointers_z16(rb);
-	 break;
-      case MESA_FORMAT_X8_Z24:
-      case MESA_FORMAT_S8_Z24:
-	 intel_gttmap_InitDepthPointers_z24_x8(rb);
-	 break;
-      default:
-	 _mesa_problem(NULL,
-		       "Unexpected MesaFormat %d in intelSetSpanFunctions",
-		       irb->Base.Format);
-	 break;
-      }
-      return;
-   }
 
-   /* If in GEM mode, we need to do the tile address swizzling ourselves,
-    * instead of the fence registers handling it.
-    */
    switch (irb->Base.Format) {
    case MESA_FORMAT_RGB565:
-      switch (tiling) {
-      case I915_TILING_NONE:
-      default:
-	 intelInitPointers_RGB565(rb);
-	 break;
-      case I915_TILING_X:
-	 intel_XTile_InitPointers_RGB565(rb);
-	 break;
-      case I915_TILING_Y:
-	 intel_YTile_InitPointers_RGB565(rb);
-	 break;
-      }
+      intel_InitPointers_RGB565(rb);
       break;
    case MESA_FORMAT_ARGB4444:
-      switch (tiling) {
-      case I915_TILING_NONE:
-      default:
-	 intelInitPointers_ARGB4444(rb);
-	 break;
-      case I915_TILING_X:
-	 intel_XTile_InitPointers_ARGB4444(rb);
-	 break;
-      case I915_TILING_Y:
-	 intel_YTile_InitPointers_ARGB4444(rb);
-	 break;
-      }
+      intel_InitPointers_ARGB4444(rb);
       break;
    case MESA_FORMAT_ARGB1555:
-      switch (tiling) {
-      case I915_TILING_NONE:
-      default:
-	 intelInitPointers_ARGB1555(rb);
-	 break;
-      case I915_TILING_X:
-	 intel_XTile_InitPointers_ARGB1555(rb);
-	 break;
-      case I915_TILING_Y:
-	 intel_YTile_InitPointers_ARGB1555(rb);
-	 break;
-      }
+      intel_InitPointers_ARGB1555(rb);
       break;
    case MESA_FORMAT_XRGB8888:
-      switch (tiling) {
-      case I915_TILING_NONE:
-      default:
-         intelInitPointers_xRGB8888(rb);
-         break;
-      case I915_TILING_X:
-         intel_XTile_InitPointers_xRGB8888(rb);
-         break;
-      case I915_TILING_Y:
-         intel_YTile_InitPointers_xRGB8888(rb);
-         break;
-      }
+      intel_InitPointers_xRGB8888(rb);
       break;
    case MESA_FORMAT_ARGB8888:
-      /* 8888 RGBA */
-      switch (tiling) {
-      case I915_TILING_NONE:
-      default:
-	 intelInitPointers_ARGB8888(rb);
-	 break;
-      case I915_TILING_X:
-	 intel_XTile_InitPointers_ARGB8888(rb);
-	 break;
-      case I915_TILING_Y:
-	 intel_YTile_InitPointers_ARGB8888(rb);
-	 break;
-      }
+      intel_InitPointers_ARGB8888(rb);
       break;
    case MESA_FORMAT_Z16:
-      switch (tiling) {
-      case I915_TILING_NONE:
-      default:
-	 intelInitDepthPointers_z16(rb);
-	 break;
-      case I915_TILING_X:
-	 intel_XTile_InitDepthPointers_z16(rb);
-	 break;
-      case I915_TILING_Y:
-	 intel_YTile_InitDepthPointers_z16(rb);
-	 break;
-      }
+      intel_InitDepthPointers_z16(rb);
       break;
    case MESA_FORMAT_X8_Z24:
    case MESA_FORMAT_S8_Z24:
-      /* There are a few different ways SW asks us to access the S8Z24 data:
-       * Z24 depth-only depth reads
-       * S8Z24 depth reads
-       * S8Z24 stencil reads.
-       */
-      if (rb->Format == MESA_FORMAT_S8_Z24) {
-	 switch (tiling) {
-	 case I915_TILING_NONE:
-	 default:
-	    intelInitDepthPointers_z24_x8(rb);
-	    break;
-	 case I915_TILING_X:
-	    intel_XTile_InitDepthPointers_z24_x8(rb);
-	    break;
-	 case I915_TILING_Y:
-	    intel_YTile_InitDepthPointers_z24_x8(rb);
-	    break;
-	 }
-      } else {
-	 _mesa_problem(NULL,
-		       "Unexpected ActualFormat in intelSetSpanFunctions");
-      }
+      intel_InitDepthPointers_z24_x8(rb);
       break;
    default:
       _mesa_problem(NULL,
-                    "Unexpected MesaFormat in intelSetSpanFunctions");
+		    "Unexpected MesaFormat %d in intelSetSpanFunctions",
+		    irb->Base.Format);
       break;
    }
 }
diff --git a/src/mesa/drivers/dri/intel/intel_spantmp.h b/src/mesa/drivers/dri/intel/intel_spantmp.h
deleted file mode 100644
index bad03398f6..0000000000
--- a/src/mesa/drivers/dri/intel/intel_spantmp.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *    Eric Anholt <eric@anholt.net>
- *
- */
-
-/**
- * Wrapper around the spantmp.h macrofest to generate spans code for
- * all the tiling styles.
- */
-
-#define SPANTMP_PIXEL_FMT INTEL_PIXEL_FMT
-#define SPANTMP_PIXEL_TYPE INTEL_PIXEL_TYPE
-#define TAG(x) INTEL_TAG(intel_gttmap_##x)
-#define TAG2(x, y) INTEL_TAG(intel_gttmap_##x##y)
-#include "spantmp2.h"
-
-#define SPANTMP_PIXEL_FMT INTEL_PIXEL_FMT
-#define SPANTMP_PIXEL_TYPE INTEL_PIXEL_TYPE
-#define PUT_VALUE(_x, _y, v) INTEL_WRITE_VALUE(NO_TILE(_x, _y), v)
-#define GET_VALUE(_x, _y) INTEL_READ_VALUE(NO_TILE(_x, _y))
-#define TAG(x) INTEL_TAG(intel##x)
-#define TAG2(x, y) INTEL_TAG(intel##x)##y
-#include "spantmp2.h"
-
-#define SPANTMP_PIXEL_FMT INTEL_PIXEL_FMT
-#define SPANTMP_PIXEL_TYPE INTEL_PIXEL_TYPE
-#define PUT_VALUE(_x, _y, v) INTEL_WRITE_VALUE(X_TILE(_x, _y), v)
-#define GET_VALUE(_x, _y) INTEL_READ_VALUE(X_TILE(_x, _y))
-#define TAG(x) INTEL_TAG(intel_XTile_##x)
-#define TAG2(x, y) INTEL_TAG(intel_XTile_##x)##y
-#include "spantmp2.h"
-
-#define SPANTMP_PIXEL_FMT INTEL_PIXEL_FMT
-#define SPANTMP_PIXEL_TYPE INTEL_PIXEL_TYPE
-#define PUT_VALUE(_x, _y, v) INTEL_WRITE_VALUE(Y_TILE(_x, _y), v)
-#define GET_VALUE(_x, _y) INTEL_READ_VALUE(Y_TILE(_x, _y))
-#define TAG(x) INTEL_TAG(intel_YTile_##x)
-#define TAG2(x, y) INTEL_TAG(intel_YTile_##x)##y
-#include "spantmp2.h"
-
-#undef INTEL_PIXEL_FMT
-#undef INTEL_PIXEL_TYPE
-#undef INTEL_WRITE_VALUE
-#undef INTEL_READ_VALUE
-#undef INTEL_TAG
-- 
cgit v1.2.3


From 3b9612645e537c3d293b09f27ef199a3eb52d840 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 4 Mar 2010 18:26:33 -0800
Subject: i965: Fix the SNB SF input size.

---
 src/mesa/drivers/dri/i965/gen6_sf_state.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 08e6753a91..18fab61556 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -48,7 +48,7 @@ upload_sf_state(struct brw_context *brw)
 
    dw1 =
       num_outputs << GEN6_SF_NUM_OUTPUTS_SHIFT |
-      num_inputs << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT |
+      (num_inputs + 1) / 2 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT |
       3 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT;
    dw2 = GEN6_SF_VIEWPORT_TRANSFORM_ENABLE |
       GEN6_SF_STATISTICS_ENABLE;
-- 
cgit v1.2.3


From f6f5e8767926932dc276015ce84b74a0d01ade65 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 5 Mar 2010 12:27:25 -0800
Subject: i965: Try to assign SNB SF inputs to outputs.

---
 src/mesa/drivers/dri/i965/gen6_sf_state.c | 43 +++++++++++++++++++++++++++++--
 1 file changed, 41 insertions(+), 2 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 18fab61556..8d96b44f1d 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -32,6 +32,25 @@
 #include "main/macros.h"
 #include "intel_batchbuffer.h"
 
+static uint32_t
+get_attr_override(struct brw_context *brw, int attr)
+{
+   uint32_t attr_override;
+   int attr_index = 0, i;
+
+   /* Find the source index (0 = first attribute after the 4D position)
+    * for this output attribute.  attr is currently a VERT_RESULT_* but should
+    * be FRAG_ATTRIB_*.
+    */
+   for (i = 0; i < attr; i++) {
+      if (brw->vs.prog_data->outputs_written & BITFIELD64_BIT(i))
+	 attr_index++;
+   }
+   attr_override = attr_index;
+
+   return attr_index;
+}
+
 static void
 upload_sf_state(struct brw_context *brw)
 {
@@ -45,6 +64,7 @@ upload_sf_state(struct brw_context *brw)
    int i;
    /* _NEW_BUFFER */
    GLboolean render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
+   int attr = 0;
 
    dw1 =
       num_outputs << GEN6_SF_NUM_OUTPUTS_SHIFT |
@@ -122,8 +142,27 @@ upload_sf_state(struct brw_context *brw)
    OUT_BATCH_F(ctx->Polygon.OffsetFactor); /* scale */
    OUT_BATCH_F(0.0); /* XXX: global depth offset clamp */
    for (i = 0; i < 8; i++) {
-      /* attribute overrides */
-      OUT_BATCH(0);
+      uint32_t attr_overrides = 0;
+
+      /* These should be generating FS inputs read instead of VS
+       * outputs written
+       */
+      for (; attr < 64; attr++) {
+	 if (brw->vs.prog_data->outputs_written & BITFIELD64_BIT(attr)) {
+	    attr_overrides |= get_attr_override(brw, attr);
+	    attr++;
+	    break;
+	 }
+      }
+
+      for (; attr < 64; attr++) {
+	 if (brw->vs.prog_data->outputs_written & BITFIELD64_BIT(attr)) {
+	    attr_overrides |= get_attr_override(brw, attr) << 16;
+	    attr++;
+	    break;
+	 }
+      }
+      OUT_BATCH(attr_overrides);
    }
    OUT_BATCH(0); /* point sprite texcoord bitmask */
    OUT_BATCH(0); /* constant interp bitmask */
-- 
cgit v1.2.3


From 5d18e86971bdcf0a4dff3cb62581d7ae54c5e67a Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 5 Mar 2010 13:18:13 -0800
Subject: i965: Pack gen6 blend_state_key structure.

---
 src/mesa/drivers/dri/i965/gen6_cc.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c
index 42b41f3210..6418fc6d81 100644
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -34,6 +34,7 @@
 
 struct brw_blend_state_key {
    GLboolean color_blend, alpha_enabled;
+   GLboolean dither;
 
    GLenum logic_op;
 
@@ -42,8 +43,6 @@ struct brw_blend_state_key {
    GLenum blend_dst_rgb, blend_dst_a;
 
    GLenum alpha_func;
-
-   GLboolean dither;
 };
 
 static void
-- 
cgit v1.2.3


From 879ea6f27972766c792fe78971a36c5c7b9f1884 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 5 Mar 2010 13:19:09 -0800
Subject: i965: Rename SNB brw_*_key structs to gen6_*_key structs.

---
 src/mesa/drivers/dri/i965/gen6_cc.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c
index 6418fc6d81..f7acad6912 100644
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -32,7 +32,7 @@
 #include "intel_batchbuffer.h"
 #include "main/macros.h"
 
-struct brw_blend_state_key {
+struct gen6_blend_state_key {
    GLboolean color_blend, alpha_enabled;
    GLboolean dither;
 
@@ -47,7 +47,7 @@ struct brw_blend_state_key {
 
 static void
 blend_state_populate_key(struct brw_context *brw,
-			 struct brw_blend_state_key *key)
+			 struct gen6_blend_state_key *key)
 {
    GLcontext *ctx = &brw->intel.ctx;
 
@@ -85,7 +85,7 @@ blend_state_populate_key(struct brw_context *brw,
  */
 static drm_intel_bo *
 blend_state_create_from_key(struct brw_context *brw,
-			    struct brw_blend_state_key *key)
+			    struct gen6_blend_state_key *key)
 {
    struct gen6_blend_state blend;
    drm_intel_bo *bo;
@@ -148,7 +148,7 @@ blend_state_create_from_key(struct brw_context *brw,
 static void
 prepare_blend_state(struct brw_context *brw)
 {
-   struct brw_blend_state_key key;
+   struct gen6_blend_state_key key;
 
    blend_state_populate_key(brw, &key);
 
@@ -171,7 +171,7 @@ const struct brw_tracked_state gen6_blend_state = {
    .prepare = prepare_blend_state,
 };
 
-struct brw_color_calc_state_key {
+struct gen6_color_calc_state_key {
    GLubyte blend_constant_color[4];
    GLclampf alpha_ref;
    GLubyte stencil_ref[2];
@@ -179,7 +179,7 @@ struct brw_color_calc_state_key {
 
 static void
 color_calc_state_populate_key(struct brw_context *brw,
-			      struct brw_color_calc_state_key *key)
+			      struct gen6_color_calc_state_key *key)
 {
    GLcontext *ctx = &brw->intel.ctx;
 
@@ -209,7 +209,7 @@ color_calc_state_populate_key(struct brw_context *brw,
  */
 static drm_intel_bo *
 color_calc_state_create_from_key(struct brw_context *brw,
-				 struct brw_color_calc_state_key *key)
+				 struct gen6_color_calc_state_key *key)
 {
    struct gen6_color_calc_state cc;
    drm_intel_bo *bo;
@@ -238,7 +238,7 @@ color_calc_state_create_from_key(struct brw_context *brw,
 static void
 prepare_color_calc_state(struct brw_context *brw)
 {
-   struct brw_color_calc_state_key key;
+   struct gen6_color_calc_state_key key;
 
    color_calc_state_populate_key(brw, &key);
 
-- 
cgit v1.2.3


From 9a38f76044761f9555bf84ebbc520c015ec88d78 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 5 Mar 2010 13:24:24 -0800
Subject: i965: Remove the unused SDC BO pointer from the sampler state key.

Since it's a BO pointer, it already lives outside the key in
brw->wm.sdc_bo[] which is used for sampler state lookup and setup.
---
 src/mesa/drivers/dri/i965/brw_wm_sampler_state.c | 1 -
 1 file changed, 1 deletion(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
index c232cd2791..3a33996452 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
@@ -89,7 +89,6 @@ struct wm_sampler_key {
       float max_aniso;
       GLenum minfilter, magfilter;
       GLenum comparemode, comparefunc;
-      dri_bo *sdc_bo;
 
       /** If target is cubemap, take context setting.
        */
-- 
cgit v1.2.3


From 20952f0378247f69849b6e37a7374bc9c94437a0 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 5 Mar 2010 13:38:02 -0800
Subject: i965: Remove the paths for making a const surface object for a NULL
 BO.

---
 src/mesa/drivers/dri/i965/brw_vs_surface_state.c |  4 ++--
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 29 +++++++++---------------
 2 files changed, 13 insertions(+), 20 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
index 950d075aa1..4007b5a15c 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
@@ -104,7 +104,7 @@ brw_update_vs_constant_surface( GLcontext *ctx,
    /* If there's no constant buffer, then no surface BO is needed to point at
     * it.
     */
-   if (vp->const_buffer == 0) {
+   if (vp->const_buffer == NULL) {
       drm_intel_bo_unreference(brw->vs.surf_bo[surf]);
       brw->vs.surf_bo[surf] = NULL;
       return;
@@ -132,7 +132,7 @@ brw_update_vs_constant_surface( GLcontext *ctx,
    brw->vs.surf_bo[surf] = brw_search_cache(&brw->surface_cache,
                                             BRW_SS_SURFACE,
                                             &key, sizeof(key),
-                                            &key.bo, key.bo ? 1 : 0,
+                                            &key.bo, 1,
                                             NULL);
    if (brw->vs.surf_bo[surf] == NULL) {
       brw->vs.surf_bo[surf] = brw_create_constant_surface(brw, &key);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index a42067611c..b1ab79b783 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -336,10 +336,7 @@ brw_create_constant_surface( struct brw_context *brw,
    surf.ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 
    assert(key->bo);
-   if (key->bo)
-      surf.ss1.base_addr = key->bo->offset; /* reloc */
-   else
-      surf.ss1.base_addr = key->offset;
+   surf.ss1.base_addr = key->bo->offset; /* reloc */
 
    surf.ss2.width = w & 0x7f;            /* bits 6:0 of size or width */
    surf.ss2.height = (w >> 7) & 0x1fff;  /* bits 19:7 of size or width */
@@ -349,20 +346,16 @@ brw_create_constant_surface( struct brw_context *brw,
  
    bo = brw_upload_cache(&brw->surface_cache, BRW_SS_SURFACE,
 			 key, sizeof(*key),
-			 &key->bo, key->bo ? 1 : 0,
+			 &key->bo, 1,
 			 &surf, sizeof(surf));
 
-   if (key->bo) {
-      /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
-       * bspec ("Data Cache") says that the data cache does not exist as
-       * a separate cache and is just the sampler cache.
-       */
-      dri_bo_emit_reloc(bo,
-			I915_GEM_DOMAIN_SAMPLER, 0,
-			0,
-			offsetof(struct brw_surface_state, ss1),
-			key->bo);
-   }
+   /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
+    * bspec ("Data Cache") says that the data cache does not exist as
+    * a separate cache and is just the sampler cache.
+    */
+   drm_intel_bo_emit_reloc(bo, offsetof(struct brw_surface_state, ss1),
+			   key->bo, 0,
+			   I915_GEM_DOMAIN_SAMPLER, 0);
 
    return bo;
 }
@@ -420,7 +413,7 @@ brw_update_wm_constant_surface( GLcontext *ctx,
    /* If there's no constant buffer, then no surface BO is needed to point at
     * it.
     */
-   if (fp->const_buffer == 0) {
+   if (fp->const_buffer == NULL) {
       drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
       brw->wm.surf_bo[surf] = NULL;
       return;
@@ -448,7 +441,7 @@ brw_update_wm_constant_surface( GLcontext *ctx,
    brw->wm.surf_bo[surf] = brw_search_cache(&brw->surface_cache,
                                             BRW_SS_SURFACE,
                                             &key, sizeof(key),
-                                            &key.bo, key.bo ? 1 : 0,
+                                            &key.bo, 1,
                                             NULL);
    if (brw->wm.surf_bo[surf] == NULL) {
       brw->wm.surf_bo[surf] = brw_create_constant_surface(brw, &key);
-- 
cgit v1.2.3


From a232cc59e3f8ac8462c23b1a83e0ba60b451e681 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 5 Mar 2010 13:48:41 -0800
Subject: intel: Remove support for the DRI1 TFP extension.

---
 src/mesa/drivers/dri/i915/i830_texstate.c        | 49 ++++++------------
 src/mesa/drivers/dri/i915/i915_texstate.c        | 36 +++-----------
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 63 +++++++-----------------
 src/mesa/drivers/dri/intel/intel_screen.c        |  6 ---
 src/mesa/drivers/dri/intel/intel_tex.h           |  2 -
 src/mesa/drivers/dri/intel/intel_tex_image.c     | 23 ---------
 src/mesa/drivers/dri/intel/intel_tex_obj.h       |  4 --
 7 files changed, 39 insertions(+), 144 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c
index 7525f9f2e0..e8f7e378ec 100644
--- a/src/mesa/drivers/dri/i915/i830_texstate.c
+++ b/src/mesa/drivers/dri/i915/i830_texstate.c
@@ -122,6 +122,7 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
    GLuint *state = i830->state.Tex[unit], format, pitch;
    GLint lodbias;
    GLubyte border[4];
+   GLuint dst_x, dst_y;
 
    memset(state, 0, sizeof(state));
 
@@ -132,7 +133,7 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
        i830->state.tex_buffer[unit] = NULL;
    }
 
-   if (!intelObj->imageOverride && !intel_finalize_mipmap_tree(intel, unit))
+   if (!intel_finalize_mipmap_tree(intel, unit))
       return GL_FALSE;
 
    /* Get first image here, since intelObj->firstLevel will get set in
@@ -140,42 +141,20 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
     */
    firstImage = tObj->Image[0][intelObj->firstLevel];
 
-   if (intelObj->imageOverride) {
-      i830->state.tex_buffer[unit] = NULL;
-      i830->state.tex_offset[unit] = intelObj->textureOffset;
+   intel_miptree_get_image_offset(intelObj->mt, intelObj->firstLevel, 0, 0,
+				  &dst_x, &dst_y);
 
-      switch (intelObj->depthOverride) {
-      case 32:
-	 format = MAPSURF_32BIT | MT_32BIT_ARGB8888;
-	 break;
-      case 24:
-      default:
-	 format = MAPSURF_32BIT | MT_32BIT_XRGB8888;
-	 break;
-      case 16:
-	 format = MAPSURF_16BIT | MT_16BIT_RGB565;
-	 break;
-      }
-
-      pitch = intelObj->pitchOverride;
-   } else {
-      GLuint dst_x, dst_y;
-
-      intel_miptree_get_image_offset(intelObj->mt, intelObj->firstLevel, 0, 0,
-				     &dst_x, &dst_y);
-
-      dri_bo_reference(intelObj->mt->region->buffer);
-      i830->state.tex_buffer[unit] = intelObj->mt->region->buffer;
-      /* XXX: This calculation is probably broken for tiled images with
-       * a non-page-aligned offset.
-       */
-      i830->state.tex_offset[unit] = (dst_x + dst_y * intelObj->mt->pitch) *
-	 intelObj->mt->cpp;
+   dri_bo_reference(intelObj->mt->region->buffer);
+   i830->state.tex_buffer[unit] = intelObj->mt->region->buffer;
+   /* XXX: This calculation is probably broken for tiled images with
+    * a non-page-aligned offset.
+    */
+   i830->state.tex_offset[unit] = (dst_x + dst_y * intelObj->mt->pitch) *
+      intelObj->mt->cpp;
 
-      format = translate_texture_format(firstImage->TexFormat,
-					firstImage->InternalFormat);
-      pitch = intelObj->mt->pitch * intelObj->mt->cpp;
-   }
+   format = translate_texture_format(firstImage->TexFormat,
+				     firstImage->InternalFormat);
+   pitch = intelObj->mt->pitch * intelObj->mt->cpp;
 
    state[I830_TEXREG_TM0LI] = (_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
                                (LOAD_TEXTURE_MAP0 << unit) | 4);
diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c
index 3ee4c8653a..a1ab8f8b6d 100644
--- a/src/mesa/drivers/dri/i915/i915_texstate.c
+++ b/src/mesa/drivers/dri/i915/i915_texstate.c
@@ -150,7 +150,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
        i915->state.tex_buffer[unit] = NULL;
    }
 
-   if (!intelObj->imageOverride && !intel_finalize_mipmap_tree(intel, unit))
+   if (!intel_finalize_mipmap_tree(intel, unit))
       return GL_FALSE;
 
    /* Get first image here, since intelObj->firstLevel will get set in
@@ -158,34 +158,14 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
     */
    firstImage = tObj->Image[0][intelObj->firstLevel];
 
-   if (intelObj->imageOverride) {
-      i915->state.tex_buffer[unit] = NULL;
-      i915->state.tex_offset[unit] = intelObj->textureOffset;
+   dri_bo_reference(intelObj->mt->region->buffer);
+   i915->state.tex_buffer[unit] = intelObj->mt->region->buffer;
+   i915->state.tex_offset[unit] = 0; /* Always the origin of the miptree */
 
-      switch (intelObj->depthOverride) {
-      case 32:
-	 format = MAPSURF_32BIT | MT_32BIT_ARGB8888;
-	 break;
-      case 24:
-      default:
-	 format = MAPSURF_32BIT | MT_32BIT_XRGB8888;
-	 break;
-      case 16:
-	 format = MAPSURF_16BIT | MT_16BIT_RGB565;
-	 break;
-      }
-
-      pitch = intelObj->pitchOverride;
-   } else {
-      dri_bo_reference(intelObj->mt->region->buffer);
-      i915->state.tex_buffer[unit] = intelObj->mt->region->buffer;
-      i915->state.tex_offset[unit] = 0; /* Always the origin of the miptree */
-
-      format = translate_texture_format(firstImage->TexFormat,
-					firstImage->InternalFormat,
-					tObj->DepthMode);
-      pitch = intelObj->mt->pitch * intelObj->mt->cpp;
-   }
+   format = translate_texture_format(firstImage->TexFormat,
+				     firstImage->InternalFormat,
+				     tObj->DepthMode);
+   pitch = intelObj->mt->pitch * intelObj->mt->cpp;
 
    state[I915_TEXREG_MS3] =
       (((firstImage->Height - 1) << MS3_HEIGHT_SHIFT) |
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index b1ab79b783..ce0bf0b97d 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -207,33 +207,14 @@ brw_create_texture_surface( struct brw_context *brw,
 
    surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
    surf.ss0.surface_type = translate_tex_target(key->target);
-   if (key->bo) {
-      surf.ss0.surface_format = translate_tex_format(key->format,
-						     key->internal_format,
-						     key->depthmode);
-   }
-   else {
-      switch (key->depth) {
-      case 32:
-         surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
-         break;
-      default:
-      case 24:
-         surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8X8_UNORM;
-         break;
-      case 16:
-         surf.ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
-         break;
-      }
-   }
+   surf.ss0.surface_format = translate_tex_format(key->format,
+						  key->internal_format,
+						  key->depthmode);
 
    /* This is ok for all textures with channel width 8bit or less:
     */
 /*    surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
-   if (key->bo)
-      surf.ss1.base_addr = key->bo->offset; /* reloc */
-   else
-      surf.ss1.base_addr = key->offset;
+   surf.ss1.base_addr = key->bo->offset; /* reloc */
 
    surf.ss2.mip_count = key->last_level - key->first_level;
    surf.ss2.width = key->width - 1;
@@ -255,17 +236,14 @@ brw_create_texture_surface( struct brw_context *brw,
 
    bo = brw_upload_cache(&brw->surface_cache, BRW_SS_SURFACE,
 			 key, sizeof(*key),
-			 &key->bo, key->bo ? 1 : 0,
+			 &key->bo, 1,
 			 &surf, sizeof(surf));
 
-   if (key->bo) {
-      /* Emit relocation to surface contents */
-      dri_bo_emit_reloc(bo,
-			I915_GEM_DOMAIN_SAMPLER, 0,
-			0,
-			offsetof(struct brw_surface_state, ss1),
-			key->bo);
-   }
+   /* Emit relocation to surface contents */
+   drm_intel_bo_emit_reloc(bo, offsetof(struct brw_surface_state, ss1),
+			   key->bo, 0,
+			   I915_GEM_DOMAIN_SAMPLER, 0);
+
    return bo;
 }
 
@@ -281,19 +259,12 @@ brw_update_texture_surface( GLcontext *ctx, GLuint unit )
 
    memset(&key, 0, sizeof(key));
 
-   if (intelObj->imageOverride) {
-      key.pitch = intelObj->pitchOverride / intelObj->mt->cpp;
-      key.depth = intelObj->depthOverride;
-      key.bo = NULL;
-      key.offset = intelObj->textureOffset;
-   } else {
-      key.format = firstImage->TexFormat;
-      key.internal_format = firstImage->InternalFormat;
-      key.pitch = intelObj->mt->pitch;
-      key.depth = firstImage->Depth;
-      key.bo = intelObj->mt->region->buffer;
-      key.offset = 0;
-   }
+   key.format = firstImage->TexFormat;
+   key.internal_format = firstImage->InternalFormat;
+   key.pitch = intelObj->mt->pitch;
+   key.depth = firstImage->Depth;
+   key.bo = intelObj->mt->region->buffer;
+   key.offset = 0;
 
    key.target = tObj->Target;
    key.depthmode = tObj->DepthMode;
@@ -308,7 +279,7 @@ brw_update_texture_surface( GLcontext *ctx, GLuint unit )
    brw->wm.surf_bo[surf] = brw_search_cache(&brw->surface_cache,
                                             BRW_SS_SURFACE,
                                             &key, sizeof(key),
-                                            &key.bo, key.bo ? 1 : 0,
+                                            &key.bo, 1,
                                             NULL);
    if (brw->wm.surf_bo[surf] == NULL) {
       brw->wm.surf_bo[surf] = brw_create_texture_surface(brw, &key);
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 9ff76c4803..6e4bb64365 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -96,11 +96,6 @@ const GLuint __driNConfigOptions = 11;
 static PFNGLXCREATECONTEXTMODES create_context_modes = NULL;
 #endif /*USE_NEW_INTERFACE */
 
-static const __DRItexOffsetExtension intelTexOffsetExtension = {
-   { __DRI_TEX_OFFSET },
-   intelSetTexOffset,
-};
-
 static const __DRItexBufferExtension intelTexBufferExtension = {
     { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
    intelSetTexBuffer,
@@ -227,7 +222,6 @@ static struct __DRIimageExtensionRec intelImageExtension = {
 
 static const __DRIextension *intelScreenExtensions[] = {
     &driReadDrawableExtension,
-    &intelTexOffsetExtension.base,
     &intelTexBufferExtension.base,
     &intelFlushExtension.base,
     &intelImageExtension.base,
diff --git a/src/mesa/drivers/dri/intel/intel_tex.h b/src/mesa/drivers/dri/intel/intel_tex.h
index f3cc0fff5c..4bb012dc65 100644
--- a/src/mesa/drivers/dri/intel/intel_tex.h
+++ b/src/mesa/drivers/dri/intel/intel_tex.h
@@ -45,8 +45,6 @@ void intelInitTextureCopyImageFuncs(struct dd_function_table *functions);
 gl_format intelChooseTextureFormat(GLcontext *ctx, GLint internalFormat,
                                    GLenum format, GLenum type);
 
-void intelSetTexOffset(__DRIcontext *pDRICtx, GLint texname,
-		       unsigned long long offset, GLint depth, GLuint pitch);
 void intelSetTexBuffer(__DRIcontext *pDRICtx,
 		       GLint target, __DRIdrawable *pDraw);
 void intelSetTexBuffer2(__DRIcontext *pDRICtx,
diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c
index f586aee992..bac36eeb56 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -706,29 +706,6 @@ intelGetCompressedTexImage(GLcontext *ctx, GLenum target, GLint level,
 		       texObj, texImage, GL_TRUE);
 }
 
-
-void
-intelSetTexOffset(__DRIcontext *pDRICtx, GLint texname,
-		  unsigned long long offset, GLint depth, GLuint pitch)
-{
-   struct intel_context *intel = pDRICtx->driverPrivate;
-   struct gl_texture_object *tObj = _mesa_lookup_texture(&intel->ctx, texname);
-   struct intel_texture_object *intelObj = intel_texture_object(tObj);
-
-   if (!intelObj)
-      return;
-
-   if (intelObj->mt)
-      intel_miptree_release(intel, &intelObj->mt);
-
-   intelObj->imageOverride = GL_TRUE;
-   intelObj->depthOverride = depth;
-   intelObj->pitchOverride = pitch;
-
-   if (offset)
-      intelObj->textureOffset = offset;
-}
-
 void
 intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
 		   GLint texture_format,
diff --git a/src/mesa/drivers/dri/intel/intel_tex_obj.h b/src/mesa/drivers/dri/intel/intel_tex_obj.h
index 3ad10d3d23..5f60e0ea4f 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_obj.h
+++ b/src/mesa/drivers/dri/intel/intel_tex_obj.h
@@ -46,10 +46,6 @@ struct intel_texture_object
     * regions will be copied to this region and the old storage freed.
     */
    struct intel_mipmap_tree *mt;
-
-   GLboolean imageOverride;
-   GLint depthOverride;
-   GLuint pitchOverride;
 };
 
 struct intel_texture_image
-- 
cgit v1.2.3


From 8c8e664f1086e702e1102ee7f5043c8c12c037bd Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 5 Mar 2010 14:13:24 -0800
Subject: i965: Only use the effective subset of the WM sampler key.

The whole structure is 836 bytes, but if only the first one or two
samplers are used (as is common), the part that matters is only 56 or
108 bytes.  By using just that subset as the key (since the key size
is also part of the key), we improve firefox-talos-gfx performance by
1%.
---
 src/mesa/drivers/dri/i965/brw_wm_sampler_state.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
index 3a33996452..d7650af3d9 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
@@ -229,7 +229,7 @@ brw_wm_sampler_populate_key(struct brw_context *brw,
    GLcontext *ctx = &brw->intel.ctx;
    int unit;
 
-   memset(key, 0, sizeof(*key));
+   key->sampler_count = 0;
 
    for (unit = 0; unit < BRW_MAX_TEX_UNIT; unit++) {
       if (ctx->Texture.Unit[unit]._ReallyEnabled) {
@@ -240,6 +240,8 @@ brw_wm_sampler_populate_key(struct brw_context *brw,
 	 struct gl_texture_image *firstImage =
 	    texObj->Image[0][intelObj->firstLevel];
 
+	 memset(entry, 0, sizeof(*entry));
+
          entry->tex_target = texObj->Target;
 
 	 entry->seamless_cube_map = (texObj->Target == GL_TEXTURE_CUBE_MAP)
@@ -288,7 +290,7 @@ static void upload_wm_samplers( struct brw_context *brw )
 {
    GLcontext *ctx = &brw->intel.ctx;
    struct wm_sampler_key key;
-   int i;
+   int i, sampler_key_size;
 
    brw_wm_sampler_populate_key(brw, &key);
 
@@ -302,8 +304,11 @@ static void upload_wm_samplers( struct brw_context *brw )
    if (brw->wm.sampler_count == 0)
       return;
 
+   /* Only include the populated portion of the key in the search. */
+   sampler_key_size = offsetof(struct wm_sampler_key,
+			       sampler[key.sampler_count]);
    brw->wm.sampler_bo = brw_search_cache(&brw->cache, BRW_SAMPLER,
-					 &key, sizeof(key),
+					 &key, sampler_key_size,
 					 brw->wm.sdc_bo, key.sampler_count,
 					 NULL);
 
@@ -323,7 +328,7 @@ static void upload_wm_samplers( struct brw_context *brw )
       }
 
       brw->wm.sampler_bo = brw_upload_cache(&brw->cache, BRW_SAMPLER,
-					    &key, sizeof(key),
+					    &key, sampler_key_size,
 					    brw->wm.sdc_bo, key.sampler_count,
 					    &sampler, sizeof(sampler));
 
-- 
cgit v1.2.3


From 8953bfce0eb7e56f13d4527ef86cdf4cf2db037f Mon Sep 17 00:00:00 2001
From: George Sapountzis <gsapountzis@gmail.com>
Date: Sat, 6 Mar 2010 06:33:20 +0200
Subject: dri: drop MINIGLX_SOURCES

---
 src/mesa/drivers/dri/i810/Makefile      | 3 ---
 src/mesa/drivers/dri/i915/Makefile      | 2 --
 src/mesa/drivers/dri/i965/Makefile      | 1 -
 src/mesa/drivers/dri/mach64/Makefile    | 3 ---
 src/mesa/drivers/dri/mga/Makefile       | 2 --
 src/mesa/drivers/dri/nouveau/Makefile   | 2 --
 src/mesa/drivers/dri/r128/Makefile      | 2 --
 src/mesa/drivers/dri/r200/Makefile      | 2 --
 src/mesa/drivers/dri/r300/Makefile      | 2 --
 src/mesa/drivers/dri/r600/Makefile      | 2 --
 src/mesa/drivers/dri/radeon/Makefile    | 2 --
 src/mesa/drivers/dri/savage/Makefile    | 3 ---
 src/mesa/drivers/dri/sis/Makefile       | 4 ----
 src/mesa/drivers/dri/tdfx/Makefile      | 3 ---
 src/mesa/drivers/dri/unichrome/Makefile | 2 --
 15 files changed, 35 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i810/Makefile b/src/mesa/drivers/dri/i810/Makefile
index 3874faee51..54a837d5ea 100644
--- a/src/mesa/drivers/dri/i810/Makefile
+++ b/src/mesa/drivers/dri/i810/Makefile
@@ -5,9 +5,6 @@ include $(TOP)/configs/current
 
 LIBNAME = i810_dri.so
 
-# Not yet
-# MINIGLX_SOURCES = server/i810_dri.c 
-
 DRIVER_SOURCES = \
 	i810context.c \
 	i810ioctl.c \
diff --git a/src/mesa/drivers/dri/i915/Makefile b/src/mesa/drivers/dri/i915/Makefile
index dc15ae425c..5b49d0c77c 100644
--- a/src/mesa/drivers/dri/i915/Makefile
+++ b/src/mesa/drivers/dri/i915/Makefile
@@ -4,8 +4,6 @@ include $(TOP)/configs/current
 
 LIBNAME = i915_dri.so
 
-MINIGLX_SOURCES = server/intel_dri.c
-
 DRIVER_SOURCES = \
 	i830_context.c \
 	i830_state.c \
diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index f98a1a27db..a242580273 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -99,7 +99,6 @@ DRIVER_SOURCES = \
 
 C_SOURCES = \
 	$(COMMON_SOURCES) \
-	$(MINIGLX_SOURCES) \
 	$(DRIVER_SOURCES)
 
 ASM_SOURCES = 
diff --git a/src/mesa/drivers/dri/mach64/Makefile b/src/mesa/drivers/dri/mach64/Makefile
index a8f463e9fd..c20fdece29 100644
--- a/src/mesa/drivers/dri/mach64/Makefile
+++ b/src/mesa/drivers/dri/mach64/Makefile
@@ -5,9 +5,6 @@ include $(TOP)/configs/current
 
 LIBNAME = mach64_dri.so
 
-# Not yet
-# MINIGLX_SOURCES = server/mach64_dri.c 
-
 DRIVER_SOURCES = \
 	mach64_context.c \
 	mach64_ioctl.c \
diff --git a/src/mesa/drivers/dri/mga/Makefile b/src/mesa/drivers/dri/mga/Makefile
index 0cc329fb22..92533bccc2 100644
--- a/src/mesa/drivers/dri/mga/Makefile
+++ b/src/mesa/drivers/dri/mga/Makefile
@@ -5,8 +5,6 @@ include $(TOP)/configs/current
 
 LIBNAME = mga_dri.so
 
-MINIGLX_SOURCES = server/mga_dri.c 
-
 DRIVER_SOURCES = \
 	mgadd.c \
 	mgaioctl.c \
diff --git a/src/mesa/drivers/dri/nouveau/Makefile b/src/mesa/drivers/dri/nouveau/Makefile
index 49e8933561..7be19b26fd 100644
--- a/src/mesa/drivers/dri/nouveau/Makefile
+++ b/src/mesa/drivers/dri/nouveau/Makefile
@@ -8,8 +8,6 @@ DRI_LIB_DEPS += $(shell pkg-config libdrm_nouveau --libs)
 
 LIBNAME = nouveau_vieux_dri.so
 
-MINIGLX_SOURCES =
-
 DRIVER_SOURCES = \
 	nouveau_screen.c \
 	nouveau_context.c \
diff --git a/src/mesa/drivers/dri/r128/Makefile b/src/mesa/drivers/dri/r128/Makefile
index 52c5a38a70..8144c9b43f 100644
--- a/src/mesa/drivers/dri/r128/Makefile
+++ b/src/mesa/drivers/dri/r128/Makefile
@@ -5,8 +5,6 @@ include $(TOP)/configs/current
 
 LIBNAME = r128_dri.so
 
-MINIGLX_SOURCES = server/r128_dri.c 
-
 DRIVER_SOURCES = \
 	r128_context.c \
 	r128_lock.c \
diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile
index 14eb96c1ba..2e86e8b941 100644
--- a/src/mesa/drivers/dri/r200/Makefile
+++ b/src/mesa/drivers/dri/r200/Makefile
@@ -7,8 +7,6 @@ CFLAGS += $(RADEON_CFLAGS)
 
 LIBNAME = r200_dri.so
 
-MINIGLX_SOURCES = server/radeon_dri.c 
-
 ifeq ($(RADEON_LDFLAGS),)
 CS_SOURCES = radeon_cs_space_drm.c radeon_bo.c radeon_cs.c
 endif
diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile
index 04459c2ddf..08934fc996 100644
--- a/src/mesa/drivers/dri/r300/Makefile
+++ b/src/mesa/drivers/dri/r300/Makefile
@@ -7,8 +7,6 @@ CFLAGS += $(RADEON_CFLAGS)
 
 LIBNAME = r300_dri.so
 
-MINIGLX_SOURCES = server/radeon_dri.c
-
 ifeq ($(RADEON_LDFLAGS),)
 CS_SOURCES = radeon_cs_space_drm.c radeon_bo.c radeon_cs.c
 endif
diff --git a/src/mesa/drivers/dri/r600/Makefile b/src/mesa/drivers/dri/r600/Makefile
index 5d50941539..2478b12658 100644
--- a/src/mesa/drivers/dri/r600/Makefile
+++ b/src/mesa/drivers/dri/r600/Makefile
@@ -7,8 +7,6 @@ CFLAGS += $(RADEON_CFLAGS)
 
 LIBNAME = r600_dri.so
 
-MINIGLX_SOURCES = server/radeon_dri.c
-
 ifeq ($(RADEON_LDFLAGS),)
 CS_SOURCES = radeon_cs_space_drm.c radeon_bo.c radeon_cs.c
 endif
diff --git a/src/mesa/drivers/dri/radeon/Makefile b/src/mesa/drivers/dri/radeon/Makefile
index a54ea16ec6..fc6d1c8e89 100644
--- a/src/mesa/drivers/dri/radeon/Makefile
+++ b/src/mesa/drivers/dri/radeon/Makefile
@@ -8,8 +8,6 @@ CFLAGS += $(RADEON_CFLAGS)
 
 LIBNAME = radeon_dri.so
 
-MINIGLX_SOURCES = server/radeon_dri.c 
-
 ifeq ($(RADEON_LDFLAGS),)
 CS_SOURCES = radeon_cs_space_drm.c radeon_bo.c radeon_cs.c
 endif
diff --git a/src/mesa/drivers/dri/savage/Makefile b/src/mesa/drivers/dri/savage/Makefile
index 2e5c40802c..53511552c6 100644
--- a/src/mesa/drivers/dri/savage/Makefile
+++ b/src/mesa/drivers/dri/savage/Makefile
@@ -5,9 +5,6 @@ include $(TOP)/configs/current
 
 LIBNAME = savage_dri.so
 
-# Doesn't exist yet.
-#MINIGLX_SOURCES = server/savage_dri.c 
-
 DRIVER_SOURCES = \
 	savage_xmesa.c \
 	savagedd.c \
diff --git a/src/mesa/drivers/dri/sis/Makefile b/src/mesa/drivers/dri/sis/Makefile
index ad009fc239..6b4f938bab 100644
--- a/src/mesa/drivers/dri/sis/Makefile
+++ b/src/mesa/drivers/dri/sis/Makefile
@@ -5,10 +5,6 @@ include $(TOP)/configs/current
 
 LIBNAME = sis_dri.so
 
-
-# Not yet
-# MINIGLX_SOURCES = server/sis_dri.c 
-
 DRIVER_SOURCES = \
 	sis6326_state.c \
 	sis6326_clear.c \
diff --git a/src/mesa/drivers/dri/tdfx/Makefile b/src/mesa/drivers/dri/tdfx/Makefile
index b9f25db4fe..96bd8f8202 100644
--- a/src/mesa/drivers/dri/tdfx/Makefile
+++ b/src/mesa/drivers/dri/tdfx/Makefile
@@ -5,9 +5,6 @@ include $(TOP)/configs/current
 
 LIBNAME = tdfx_dri.so
 
-# not yet
-# MINIGLX_SOURCES = server/tdfx_dri.c 
-
 DRIVER_SOURCES = \
 	tdfx_context.c \
 	tdfx_dd.c \
diff --git a/src/mesa/drivers/dri/unichrome/Makefile b/src/mesa/drivers/dri/unichrome/Makefile
index 344d34fce3..14cf9f3038 100644
--- a/src/mesa/drivers/dri/unichrome/Makefile
+++ b/src/mesa/drivers/dri/unichrome/Makefile
@@ -5,8 +5,6 @@ include $(TOP)/configs/current
 
 LIBNAME = unichrome_dri.so
 
-MINIGLX_SOURCES = server/via_dri.c 
-
 DRIVER_SOURCES = \
 	via_context.c \
 	via_fb.c \
-- 
cgit v1.2.3


From 419f0f9d0426bc1eb40ceb60e7764af4013947a0 Mon Sep 17 00:00:00 2001
From: George Sapountzis <gsapountzis@gmail.com>
Date: Sat, 6 Mar 2010 06:33:21 +0200
Subject: dri: drop MINIGLX_SOURCES (2)

---
 src/mesa/drivers/dri/i810/server/i810_dri.c     |  975 -----------------
 src/mesa/drivers/dri/i915/server/intel_dri.c    |    1 -
 src/mesa/drivers/dri/i965/server/intel_dri.c    |    1 -
 src/mesa/drivers/dri/intel/server/intel_dri.c   | 1306 ----------------------
 src/mesa/drivers/dri/mga/server/mga_dri.c       | 1088 ------------------
 src/mesa/drivers/dri/r128/server/r128_dri.c     | 1112 -------------------
 src/mesa/drivers/dri/r200/server/radeon_dri.c   |    1 -
 src/mesa/drivers/dri/r300/server/radeon_dri.c   |    1 -
 src/mesa/drivers/dri/r600/server/radeon_dri.c   |    1 -
 src/mesa/drivers/dri/radeon/server/radeon_dri.c | 1337 -----------------------
 src/mesa/drivers/dri/tdfx/server/tdfx_dri.c     |  471 --------
 src/mesa/drivers/dri/unichrome/server/via_dri.c | 1251 ---------------------
 12 files changed, 7545 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i810/server/i810_dri.c
 delete mode 120000 src/mesa/drivers/dri/i915/server/intel_dri.c
 delete mode 120000 src/mesa/drivers/dri/i965/server/intel_dri.c
 delete mode 100644 src/mesa/drivers/dri/intel/server/intel_dri.c
 delete mode 100644 src/mesa/drivers/dri/mga/server/mga_dri.c
 delete mode 100644 src/mesa/drivers/dri/r128/server/r128_dri.c
 delete mode 120000 src/mesa/drivers/dri/r200/server/radeon_dri.c
 delete mode 120000 src/mesa/drivers/dri/r300/server/radeon_dri.c
 delete mode 120000 src/mesa/drivers/dri/r600/server/radeon_dri.c
 delete mode 100644 src/mesa/drivers/dri/radeon/server/radeon_dri.c
 delete mode 100644 src/mesa/drivers/dri/tdfx/server/tdfx_dri.c
 delete mode 100644 src/mesa/drivers/dri/unichrome/server/via_dri.c

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i810/server/i810_dri.c b/src/mesa/drivers/dri/i810/server/i810_dri.c
deleted file mode 100644
index f52797c5ed..0000000000
--- a/src/mesa/drivers/dri/i810/server/i810_dri.c
+++ /dev/null
@@ -1,975 +0,0 @@
-/**
- * \file server/i810_dri.c
- * \brief File to perform the device-specific initialization tasks typically
- * done in the X server.
- *
- * Here they are converted to run in the client (or perhaps a standalone
- * process), and to work with the frame buffer device rather than the X
- * server infrastructure.
- * 
- * Copyright (C) 2004 Dave Airlie (airlied@linux.ie)
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <errno.h>
-#include <unistd.h>
-
-#include "driver.h"
-#include "drm.h"
-
-#include "i810.h"
-#include "i810_dri.h"
-#include "i810_reg.h"
-
-
-static int i810_pitches[] = {
-   512,
-   1024,
-   2048,
-   4096,
-   0
-};
-
-static int i810_pitch_flags[] = {
-   0x0,
-   0x1,
-   0x2,
-   0x3,
-   0
-};
-
-static unsigned int i810_drm_version = 0;
-
-static int
-I810AllocLow(I810MemRange * result, I810MemRange * pool, int size)
-{
-   if (size > pool->Size)
-      return 0;
-
-   pool->Size -= size;
-   result->Size = size;
-   result->Start = pool->Start;
-   result->End = pool->Start += size;
-
-   return 1;
-}
-
-static int
-I810AllocHigh(I810MemRange * result, I810MemRange * pool, int size)
-{
-   if (size > pool->Size)
-      return 0;
-
-   pool->Size -= size;
-   result->Size = size;
-   result->End = pool->End;
-   result->Start = pool->End -= size;
-
-   return 1;
-}
-
-
-/**
- * \brief Wait for free FIFO entries.
- *
- * \param ctx display handle.
- * \param entries number of free entries to wait.
- *
- * It polls the free entries from the chip until it reaches the requested value
- * or a timeout (3000 tries) occurs. Aborts the program if the FIFO times out.
- */
-static void I810WaitForFifo( const DRIDriverContext *ctx,
-			       int entries )
-{
-}
-
-/**
- * \brief Reset graphics card to known state.
- *
- * \param ctx display handle.
- *
- * Resets the values of several I810 registers.
- */
-static void I810EngineReset( const DRIDriverContext *ctx )
-{
-   unsigned char *I810MMIO = ctx->MMIOAddress;
-}
-
-/**
- * \brief Restore the drawing engine.
- *
- * \param ctx display handle
- *
- * Resets the graphics card and sets initial values for several registers of
- * the card's drawing engine.
- *
- * Turns on the i810 command processor engine (i.e., the ringbuffer).
- */
-static int I810EngineRestore( const DRIDriverContext *ctx )
-{
-   I810Ptr info = ctx->driverPrivate;
-   unsigned char *I810MMIO = ctx->MMIOAddress;
-
-   fprintf(stderr, "%s\n", __FUNCTION__);
-
-   return 1;
-}
-
-
-/**
- * \brief Shutdown the drawing engine.
- *
- * \param ctx display handle
- *
- * Turns off the command processor engine & restores the graphics card
- * to a state that fbdev understands.
- */
-static int I810EngineShutdown( const DRIDriverContext *ctx )
-{
-  drmI810Init info;
-  int ret;
-
-  memset(&info, 0, sizeof(drmI810Init));
-  info.func = I810_CLEANUP_DMA;
-  
-  ret = drmCommandWrite(ctx->drmFD, DRM_I810_INIT, &info, sizeof(drmI810Init));
-  if (ret>0)
-  {
-    fprintf(stderr,"[dri] I810 DMA Cleanup failed\n");
-    return -errno;
-  }
-  return 0;
-}
-
-/**
- * \brief Compute base 2 logarithm.
- *
- * \param val value.
- * 
- * \return base 2 logarithm of \p val.
- */
-static int I810MinBits(int val)
-{
-   int  bits;
-
-   if (!val) return 1;
-   for (bits = 0; val; val >>= 1, ++bits);
-   return bits;
-}
-
-static int I810DRIAgpPreInit( const DRIDriverContext *ctx, I810Ptr info)
-{
-
-  if (drmAgpAcquire(ctx->drmFD) < 0) {
-    fprintf(stderr, "[gart] AGP not available\n");
-    return 0;
-  }
-  
-  
-  if (drmAgpEnable(ctx->drmFD, 0) < 0) {
-    fprintf(stderr, "[gart] AGP not enabled\n");
-    drmAgpRelease(ctx->drmFD);
-    return 0;
-  }
-}
-
-/**
- * \brief Initialize the AGP state
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return one on success, or zero on failure.
- * 
- * Acquires and enables the AGP device. Reserves memory in the AGP space for
- * the ring buffer, vertex buffers and textures. Initialize the I810
- * registers to point to that memory and add client mappings.
- */
-static int I810DRIAgpInit( const DRIDriverContext *ctx, I810Ptr info)
-{
-   unsigned char *I810MMIO = ctx->MMIOAddress;
-   int            ret;
-   int            s, l;
-   unsigned long dcacheHandle;
-   unsigned long agpHandle;
-   int pitch_idx = 0;
-   int back_size = 0;
-   int sysmem_size = 0;
-   int width = ctx->shared.virtualWidth * ctx->cpp;
-
-
-   info->backHandle = DRM_AGP_NO_HANDLE;
-   info->zHandle = DRM_AGP_NO_HANDLE;
-   info->sysmemHandle = DRM_AGP_NO_HANDLE;
-   info->dcacheHandle = DRM_AGP_NO_HANDLE;
-
-   memset(&info->DcacheMem, 0, sizeof(I810MemRange));
-   memset(&info->BackBuffer, 0, sizeof(I810MemRange));
-   memset(&info->DepthBuffer, 0, sizeof(I810MemRange));
-   
-   drmAgpAlloc(ctx->drmFD, 4096 * 1024, 1, NULL, &dcacheHandle);
-   info->dcacheHandle = dcacheHandle;
-   
-   fprintf(stderr, "[agp] dcacheHandle : 0x%x\n", dcacheHandle);
-
-#define Elements(x) sizeof(x)/sizeof(*x)
-   for (pitch_idx = 0; pitch_idx < Elements(i810_pitches); pitch_idx++)
-     if (width <= i810_pitches[pitch_idx])
-       break;
-   
-   if (pitch_idx == Elements(i810_pitches)) {
-     fprintf(stderr,"[dri] Couldn't find depth/back buffer pitch\n");
-     exit(-1);
-   }
-   else
-   {
-     int lines = (ctx->shared.virtualWidth + 15) / 16 * 16;
-     back_size = i810_pitches[pitch_idx] * lines;
-     back_size = ((back_size + 4096 - 1) / 4096) * 4096;
-   }
-
-   sysmem_size = ctx->shared.fbSize;
-   fprintf(stderr,"sysmem_size is %lu back_size is %lu\n", sysmem_size, back_size);
-   if (dcacheHandle != DRM_AGP_NO_HANDLE) {
-     if (back_size > 4 * 1024 * 1024) {
-       fprintf(stderr,"[dri] Backsize is larger then 4 meg\n");
-       sysmem_size = sysmem_size - 2 * back_size;
-       drmAgpFree(ctx->drmFD, dcacheHandle);
-       info->dcacheHandle = dcacheHandle = DRM_AGP_NO_HANDLE;
-     } else {
-       sysmem_size = sysmem_size - back_size;
-     }
-   } else {
-     sysmem_size = sysmem_size - 2 * back_size;
-   }
-   
-   info->SysMem.Start=0;
-   info->SysMem.Size = sysmem_size;
-   info->SysMem.End = sysmem_size;
-   
-   if (dcacheHandle != DRM_AGP_NO_HANDLE) {
-      if (drmAgpBind(ctx->drmFD, dcacheHandle, info->DepthOffset) == 0) {
-	memset(&info->DcacheMem, 0, sizeof(I810MemRange));
-	fprintf(stderr,"[agp] GART: Found 4096K Z buffer memory\n");
-	info->DcacheMem.Start = info->DepthOffset;
-	 info->DcacheMem.Size = 1024 * 4096;
-	 info->DcacheMem.End =  info->DcacheMem.Start + info->DcacheMem.Size;
-      } else {
-	fprintf(stderr, "[agp] GART: dcache bind failed\n");
-	drmAgpFree(ctx->drmFD, dcacheHandle);
-	info->dcacheHandle = dcacheHandle = DRM_AGP_NO_HANDLE;
-      }
-   } else {
-     fprintf(stderr, "[agp] GART: no dcache memory found\n");
-   }
-   
-   drmAgpAlloc(ctx->drmFD, back_size, 0, NULL, &agpHandle);
-   info->backHandle = agpHandle;
-
-   if (agpHandle != DRM_AGP_NO_HANDLE) {
-      if (drmAgpBind(ctx->drmFD, agpHandle, info->BackOffset) == 0) {
-	fprintf(stderr, "[agp] Bound backbuffer memory\n");
-
-	info->BackBuffer.Start = info->BackOffset;
-	info->BackBuffer.Size = back_size;
-	info->BackBuffer.End = (info->BackBuffer.Start +
-				 info->BackBuffer.Size);
-      } else {
-	fprintf(stderr,"[agp] Unable to bind backbuffer.  Disabling DRI.\n");
-	return 0;
-      }
-   } else {
-     fprintf(stderr, "[dri] Unable to allocate backbuffer memory.  Disabling DRI.\n");
-     return 0;
-   }
-
-   if (dcacheHandle == DRM_AGP_NO_HANDLE) {
-     drmAgpAlloc(ctx->drmFD, back_size, 0, NULL, &agpHandle);
-
-     info->zHandle = agpHandle;
-
-     if (agpHandle != DRM_AGP_NO_HANDLE) {
-       if (drmAgpBind(ctx->drmFD, agpHandle, info->DepthOffset) == 0) {
-	 fprintf(stderr,"[agp] Bound depthbuffer memory\n");
-	 info->DepthBuffer.Start = info->DepthOffset;
-	 info->DepthBuffer.Size = back_size;
-	 info->DepthBuffer.End = (info->DepthBuffer.Start +
-				   info->DepthBuffer.Size);
-       } else {
-	 fprintf(stderr,"[agp] Unable to bind depthbuffer.  Disabling DRI.\n");
-	 return 0;
-       }
-     } else {
-       fprintf(stderr,"[agp] Unable to allocate depthbuffer memory.  Disabling DRI.\n");
-       return 0;
-     }
-   }
-
-   /* Now allocate and bind the agp space.  This memory will include the
-    * regular framebuffer as well as texture memory.
-    */
-   drmAgpAlloc(ctx->drmFD, sysmem_size, 0, NULL, &agpHandle);
-   info->sysmemHandle = agpHandle;
-   
-   if (agpHandle != DRM_AGP_NO_HANDLE) {
-     if (drmAgpBind(ctx->drmFD, agpHandle, 0) == 0) {
-       fprintf(stderr, "[agp] Bound System Texture Memory\n");
-     } else {
-       fprintf(stderr, "[agp] Unable to bind system texture memory. Disabling DRI.\n");
-       return 0;
-     }
-   } else {
-     fprintf(stderr, "[agp] Unable to allocate system texture memory. Disabling DRI.\n");
-     return 0;
-   }
-   
-   info->auxPitch = i810_pitches[pitch_idx];
-   info->auxPitchBits = i810_pitch_flags[pitch_idx];
-   
-   return 1;
-}
-
-
-/**
- * \brief Initialize the kernel data structures and enable the CP engine.
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return non-zero on success, or zero on failure.
- *
- * This function is a wrapper around the DRM_I810_CP_INIT command, passing
- * all the parameters in a drmI810Init structure.
- */
-static int I810DRIKernelInit( const DRIDriverContext *ctx,
-			       I810Ptr info)
-{
-   int cpp = ctx->bpp / 8;
-   drmI810Init  drmInfo;
-   int ret;
-   I810RingBuffer *ring = &(info->LpRing);
-
-   /* This is the struct passed to the kernel module for its initialization */
-   memset(&drmInfo, 0, sizeof(drmI810Init));
-   
-   /* make sure we have at least 1.4 */
-   drmInfo.func             = I810_INIT_DMA_1_4;
-
-   drmInfo.ring_start = ring->mem.Start;
-   drmInfo.ring_end = ring->mem.End;
-   drmInfo.ring_size = ring->mem.Size;
-
-   drmInfo.mmio_offset         = (unsigned int)info->regs;
-   drmInfo.buffers_offset      = (unsigned int)info->buffer_map;
-   drmInfo.sarea_priv_offset   = sizeof(drm_sarea_t);
-
-   drmInfo.front_offset        = 0;
-   drmInfo.back_offset         = info->BackBuffer.Start;
-   drmInfo.depth_offset        = info->DepthBuffer.Start;
-
-   drmInfo.w                   = ctx->shared.virtualWidth;
-   drmInfo.h                   = ctx->shared.virtualHeight;
-   drmInfo.pitch               = info->auxPitch;
-   drmInfo.pitch_bits          = info->auxPitchBits;
-   
-
-   ret = drmCommandWrite(ctx->drmFD, DRM_I810_INIT, &drmInfo, 
-			 sizeof(drmI810Init));
-
-   return ret >= 0;
-}
-
-
-/**
- * \brief Add a map for the vertex buffers that will be accessed by any
- * DRI-based clients.
- * 
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return one on success, or zero on failure.
- *
- * Calls drmAddBufs() with the previously allocated vertex buffers.
- */
-static int I810DRIBufInit( const DRIDriverContext *ctx, I810Ptr info )
-{
-   /* Initialize vertex buffers */
-   info->bufNumBufs = drmAddBufs(ctx->drmFD,
-				 I810_DMA_BUF_NR,
-				 I810_DMA_BUF_SZ,
-				 DRM_AGP_BUFFER,
-				 info->BufferMem.Start);
-
-   if (info->bufNumBufs <= 0) {
-      fprintf(stderr,
-	      "[drm] Could not create vertex/indirect buffers list\n");
-      return 0;
-   }
-   fprintf(stderr,
-	   "[drm] Added %d %d byte vertex/indirect buffers\n",
-	   info->bufNumBufs, I810_DMA_BUF_SZ);
-   
-   return 1;
-}
-
-/**
- * \brief Install an IRQ handler.
- * 
- * \param ctx display handle.
- * \param info driver private data.
- *
- * Attempts to install an IRQ handler via drmCtlInstHandler(), falling back to
- * IRQ-free operation on failure.
- */
-static void I810DRIIrqInit(const DRIDriverContext *ctx,
-			     I810Ptr info)
-{
-   if (!info->irq) {
-      info->irq = drmGetInterruptFromBusID(ctx->drmFD,
-					   ctx->pciBus,
-					   ctx->pciDevice,
-					   ctx->pciFunc);
-
-      if ((drmCtlInstHandler(ctx->drmFD, info->irq)) != 0) {
-	 fprintf(stderr,
-		 "[drm] failure adding irq handler, "
-		 "there is a device already using that irq\n"
-		 "[drm] falling back to irq-free operation\n");
-	 info->irq = 0;
-      }
-   }
-
-   if (info->irq)
-      fprintf(stderr,
-	      "[drm] dma control initialized, using IRQ %d\n",
-	      info->irq);
-}
-
-static int I810CheckDRMVersion( const DRIDriverContext *ctx,
-				  I810Ptr info )
-{
-   drmVersionPtr  version;
-
-   version = drmGetVersion(ctx->drmFD);
-   if (version) {
-      int req_minor, req_patch;
-
-      req_minor = 4;
-      req_patch = 0;	
-
-      i810_drm_version = (version->version_major<<16) | version->version_minor;
-      if (version->version_major != 1 ||
-	  version->version_minor < req_minor ||
-	  (version->version_minor == req_minor && 
-	   version->version_patchlevel < req_patch)) {
-	 /* Incompatible drm version */
-	 fprintf(stderr,
-		 "[dri] I810DRIScreenInit failed because of a version "
-		 "mismatch.\n"
-		 "[dri] i810.o kernel module version is %d.%d.%d "
-		 "but version 1.%d.%d or newer is needed.\n"
-		 "[dri] Disabling DRI.\n",
-		 version->version_major,
-		 version->version_minor,
-		 version->version_patchlevel,
-		 req_minor,
-		 req_patch);
-	 drmFreeVersion(version);
-	 return 0;
-      }
-
-      info->drmMinor = version->version_minor;
-      drmFreeVersion(version);
-   }
-
-   return 1;
-}
-
-static int I810MemoryInit( const DRIDriverContext *ctx, I810Ptr info )
-{
-   int        width_bytes = ctx->shared.virtualWidth * ctx->cpp;
-   int        cpp         = ctx->cpp;
-   int        bufferSize  = (ctx->shared.virtualHeight * width_bytes);
-   int        depthSize   = (((ctx->shared.virtualHeight+15) & ~15) * width_bytes);
-   int        l;
-
-   if (drmAddMap(ctx->drmFD, (drm_handle_t) info->BackBuffer.Start,
-		 info->BackBuffer.Size, DRM_AGP, 0,
-		 &info->backbuffer) < 0) {
-     fprintf(stderr, "[drm] drmAddMap(backbuffer) failed.  Disabling DRI\n");
-     return 0;
-   }
-   
-   if (drmAddMap(ctx->drmFD, (drm_handle_t) info->DepthBuffer.Start,
-		 info->DepthBuffer.Size, DRM_AGP, 0,
-		 &info->depthbuffer) < 0) {
-     fprintf(stderr, "[drm] drmAddMap(depthbuffer) failed.  Disabling DRI.\n");
-      return 0;
-   }
-
-   if (!I810AllocLow(&(info->FrontBuffer), &(info->SysMem), (((ctx->shared.virtualHeight * width_bytes) + 4095) & ~4095)))
-   {
-     fprintf(stderr,"Framebuffer allocation failed\n");
-     return 0;
-   }
-   else
-     fprintf(stderr,"Frame buffer at 0x%.8x (%luk, %lu bytes)\n",
-	     info->FrontBuffer.Start,
-	     info->FrontBuffer.Size / 1024, info->FrontBuffer.Size);
-   
-   memset(&(info->LpRing), 0, sizeof(I810RingBuffer));
-   if (I810AllocLow(&(info->LpRing.mem), &(info->SysMem), 16 * 4096)) {
-     fprintf(stderr,
-	    "Ring buffer at 0x%.8x (%luk, %lu bytes)\n",
-	     info->LpRing.mem.Start,
-	     info->LpRing.mem.Size / 1024, info->LpRing.mem.Size);
-     
-     info->LpRing.tail_mask = info->LpRing.mem.Size - 1;
-     info->LpRing.virtual_start = info->LpRing.mem.Start;
-     info->LpRing.head = 0;
-     info->LpRing.tail = 0;
-     info->LpRing.space = 0;
-   } else {
-     fprintf(stderr, "Ring buffer allocation failed\n");
-     return (0);
-   }
-
-   /* Allocate buffer memory */
-   I810AllocHigh(&(info->BufferMem), &(info->SysMem),
-		 I810_DMA_BUF_NR * I810_DMA_BUF_SZ);
-   
-
-   fprintf(stderr, "[dri] Buffer map : %lx\n",
-	      info->BufferMem.Start);
-
-   if (info->BufferMem.Start == 0 ||
-       info->BufferMem.End - info->BufferMem.Start >
-       I810_DMA_BUF_NR * I810_DMA_BUF_SZ) {
-     fprintf(stderr,"[dri] Not enough memory for dma buffers.  Disabling DRI.\n");
-     return 0;
-   }
-
-   if (drmAddMap(ctx->drmFD, (drm_handle_t) info->BufferMem.Start,
-		 info->BufferMem.Size, DRM_AGP, 0, &info->buffer_map) < 0) {
-     fprintf(stderr, "[drm] drmAddMap(buffer_map) failed.  Disabling DRI.\n");
-     return 0;
-   }
-
-   if (drmAddMap(ctx->drmFD, (drm_handle_t) info->LpRing.mem.Start,
-		 info->LpRing.mem.Size, DRM_AGP, 0, &info->ring_map) < 0) {
-     fprintf(stderr, "[drm] drmAddMap(ring_map) failed.  Disabling DRI. \n");
-     return 0;
-   }
-
-   /* Front, back and depth buffers - everything else texture??
-    */
-   info->textureSize = info->SysMem.Size;
-
-   if (info->textureSize < 0) 
-      return 0;
-
-   
-   l = I810MinBits((info->textureSize-1) / I810_NR_TEX_REGIONS);
-   if (l < I810_LOG_MIN_TEX_REGION_SIZE) l = I810_LOG_MIN_TEX_REGION_SIZE;
-
-   /* Round the texture size up to the nearest whole number of
-    * texture regions.  Again, be greedy about this, don't
-    * round down.
-    */
-   info->logTextureGranularity = l;
-   info->textureSize = (info->textureSize >> l) << l;
-
-   /* Set a minimum usable local texture heap size.  This will fit
-    * two 256x256x32bpp textures.
-    */
-   if (info->textureSize < 512 * 1024) {
-      info->textureOffset = 0;
-      info->textureSize = 0;
-   }
-
-   I810AllocLow(&(info->TexMem), &(info->SysMem), info->textureSize);
-
-   if (drmAddMap(ctx->drmFD, (drm_handle_t) info->TexMem.Start,
-		 info->TexMem.Size, DRM_AGP, 0, &info->textures) < 0) {
-     fprintf(stderr,
-		 "[drm] drmAddMap(textures) failed.  Disabling DRI.\n");
-      return 0;
-   }
-
-   /* Reserve space for textures */
-   fprintf(stderr, 
-	   "Will use back buffer at offset 0x%x\n",
-	   info->BackOffset);
-   fprintf(stderr, 
-	   "Will use depth buffer at offset 0x%x\n",
-	   info->DepthOffset);
-   fprintf(stderr, 
-	   "Will use %d kb for textures at offset 0x%x\n",
-	   info->TexMem.Size/1024, info->TexMem.Start);
-
-   return 1;
-} 
-
-
-
-/**
- * Called at the start of each server generation.
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return non-zero on success, or zero on failure.
- *
- * Performs static frame buffer allocation. Opens the DRM device and add maps
- * to the SAREA, framebuffer and MMIO regions. Fills in \p info with more
- * information. Creates a \e server context to grab the lock for the
- * initialization ioctls and calls the other initilization functions in this
- * file. Starts the CP engine via the DRM_I810_CP_START command.
- *
- * Setups a I810DRIRec structure to be passed to i810_dri.so for its
- * initialization.
- */
-static int I810ScreenInit( DRIDriverContext *ctx, I810Ptr info )
-{
-   I810DRIPtr   pI810DRI;
-   int err;
-
-   usleep(100);
-   /*assert(!ctx->IsClient);*/
-
-   /* from XFree86 driver */
-   info->DepthOffset = 0x3000000;
-   info->BackOffset = 0x3800000;
-   {
-      int  width_bytes = (ctx->shared.virtualWidth * ctx->cpp);
-      int  maxy        = ctx->shared.fbSize / width_bytes;
-
-
-      if (maxy <= ctx->shared.virtualHeight * 3) {
-	 fprintf(stderr, 
-		 "Static buffer allocation failed -- "
-		 "need at least %d kB video memory (have %d kB)\n",
-		 (ctx->shared.virtualWidth * ctx->shared.virtualHeight *
-		  ctx->cpp * 3 + 1023) / 1024,
-		 ctx->shared.fbSize / 1024);
-	 return 0;
-      } 
-   }
-
-
-   info->regsSize = ctx->MMIOSize;
-   ctx->shared.SAREASize = 0x2000;
-
-   /* Note that drmOpen will try to load the kernel module, if needed. */
-   ctx->drmFD = drmOpen("i810", NULL );
-   if (ctx->drmFD < 0) {
-      fprintf(stderr, "[drm] drmOpen failed\n");
-      return 0;
-   }
-
-   if ((err = drmSetBusid(ctx->drmFD, ctx->pciBusID)) < 0) {
-      fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n",
-	      ctx->drmFD, ctx->pciBusID, strerror(-err));
-      return 0;
-   }
-
-   if (drmAddMap( ctx->drmFD,
-		  0,
-		  ctx->shared.SAREASize,
-		  DRM_SHM,
-		  DRM_CONTAINS_LOCK,
-		  &ctx->shared.hSAREA) < 0)
-   {
-      fprintf(stderr, "[drm] drmAddMap failed\n");
-      return 0;
-   }
-   fprintf(stderr, "[drm] added %d byte SAREA at 0x%08lx\n",
-	   ctx->shared.SAREASize, ctx->shared.hSAREA);
-
-   if (drmMap( ctx->drmFD,
-	       ctx->shared.hSAREA,
-	       ctx->shared.SAREASize,
-	       (drmAddressPtr)(&ctx->pSAREA)) < 0)
-   {
-      fprintf(stderr, "[drm] drmMap failed\n");
-      return 0;
-   }
-   memset(ctx->pSAREA, 0, ctx->shared.SAREASize);
-   fprintf(stderr, "[drm] mapped SAREA 0x%08lx to %p, size %d\n",
-	   ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize);
-
-   if (drmAddMap(ctx->drmFD, 
-		 ctx->MMIOStart,
-		 ctx->MMIOSize,
-		 DRM_REGISTERS, 
-		 DRM_READ_ONLY, 
-		 &info->regs) < 0) {
-      fprintf(stderr, "[drm] drmAddMap mmio failed\n");	
-      return 0;
-   }
-   fprintf(stderr,
-	   "[drm] register handle = 0x%08x\n", info->regs);
-
-   I810DRIAgpPreInit(ctx, info);
-   /* Need to AddMap the framebuffer and mmio regions here:
-    */
-   if (drmAddMap( ctx->drmFD,
-		  (drm_handle_t)ctx->FBStart,
-		  ctx->FBSize,
-		  DRM_FRAME_BUFFER,
-#ifndef _EMBEDDED
-		  0,
-#else
-		  DRM_READ_ONLY,
-#endif
-		  &ctx->shared.hFrameBuffer) < 0)
-   {
-      fprintf(stderr, "[drm] drmAddMap framebuffer failed\n");
-      return 0;
-   }
-
-   fprintf(stderr, "[drm] framebuffer handle = 0x%08lx\n",
-	   ctx->shared.hFrameBuffer);
-
-   /* Check the i810 DRM version */
-   if (!I810CheckDRMVersion(ctx, info)) {
-      return 0;
-   }
-
-   /* Initialize AGP */
-   if (!I810DRIAgpInit(ctx, info)) {
-      return 0;
-   }
-
-
-   /* Memory manager setup */
-   if (!I810MemoryInit(ctx, info)) {
-      return 0;
-   }
-
-   /* Initialize the SAREA private data structure */
-   {
-      I810SAREAPtr pSAREAPriv;
-      pSAREAPriv = (I810SAREAPtr)(((char*)ctx->pSAREA) + 
-					sizeof(drm_sarea_t));
-      memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
-      //      pSAREAPriv->pf_enabled=1;
-   }
-
-
-   /* Create a 'server' context so we can grab the lock for
-    * initialization ioctls.
-    */
-   if ((err = drmCreateContext(ctx->drmFD, &ctx->serverContext)) != 0) {
-      fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err);
-      return 0;
-   }
-
-   DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0); 
-
-   /* Initialize the vertex buffers list */
-   if (!I810DRIBufInit(ctx, info)) {
-      fprintf(stderr, "I810DRIBufInit failed\n");
-      DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext);
-      return 0;
-   }
-
-   /* Initialize the kernel data structures */
-   if (!I810DRIKernelInit(ctx, info)) {
-      fprintf(stderr, "I810DRIKernelInit failed\n");
-      DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext);
-      return 0;
-   }
-
-   /* Initialize IRQ */
-   I810DRIIrqInit(ctx, info);
-
-   /* Quick hack to clear the front & back buffers.  Could also use
-    * the clear ioctl to do this, but would need to setup hw state
-    * first.
-    */
-#if 0
-   memset((char *)ctx->FBAddress,
-	  0,
-	  info->auxPitch * ctx->cpp * ctx->shared.virtualHeight );
-
-   memset((char *)info->backbuffer,
-	  0,
-	  info->auxPitch * ctx->cpp * ctx->shared.virtualHeight );
-#endif
-
-   /* This is the struct passed to i810_dri.so for its initialization */
-   ctx->driverClientMsg = malloc(sizeof(I810DRIRec));
-   ctx->driverClientMsgSize = sizeof(I810DRIRec);
-   pI810DRI                    = (I810DRIPtr)ctx->driverClientMsg;
-
-   pI810DRI->regs              = info->regs;
-   pI810DRI->regsSize          = info->regsSize;
-   // regsMap is unused
-
-   pI810DRI->backbufferSize    = info->BackBuffer.Size;
-   pI810DRI->backbuffer        = info->backbuffer;
-
-   pI810DRI->depthbufferSize   = info->DepthBuffer.Size;
-   pI810DRI->depthbuffer       = info->depthbuffer;
-
-   pI810DRI->textures          = info->textures;
-   pI810DRI->textureSize       = info->textureSize;
-
-   pI810DRI->agp_buffers       = info->buffer_map;
-   pI810DRI->agp_buf_size      = info->BufferMem.Size;
-
-   pI810DRI->deviceID          = info->Chipset;
-   pI810DRI->width             = ctx->shared.virtualWidth;
-   pI810DRI->height            = ctx->shared.virtualHeight;
-   pI810DRI->mem               = ctx->shared.fbSize;
-   pI810DRI->cpp               = ctx->bpp / 8;
-   pI810DRI->bitsPerPixel      = ctx->bpp;
-   pI810DRI->fbOffset          = info->FrontBuffer.Start;
-   pI810DRI->fbStride          = info->auxPitch;
-   
-   pI810DRI->backOffset        = info->BackBuffer.Start;
-   pI810DRI->depthOffset       = info->DepthBuffer.Start;
-
-   pI810DRI->auxPitch          = info->auxPitch;
-   pI810DRI->auxPitchBits      = info->auxPitchBits;
-
-   pI810DRI->logTextureGranularity = info->logTextureGranularity;
-   pI810DRI->textureOffset     = info->TexMem.Start;
-  
-   pI810DRI->ringOffset        = info->LpRing.mem.Start;
-   pI810DRI->ringSize          = info->LpRing.mem.Size;
-
-   // drmBufs looks unused 
-   pI810DRI->irq               = info->irq;
-   pI810DRI->sarea_priv_offset = sizeof(drm_sarea_t);
-
-   /* Don't release the lock now - let the VT switch handler do it. */
-   return 1;
-}
-
-
-/**
- * \brief Validate the fbdev mode.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Saves some registers and returns 1.
- *
- * \sa i810ValidateMode().
- */
-static int i810ValidateMode( const DRIDriverContext *ctx )
-{
-   unsigned char *I810MMIO = ctx->MMIOAddress;
-   I810Ptr info = ctx->driverPrivate;
-
-   return 1;
-}
-
-
-/**
- * \brief Examine mode returned by fbdev.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Restores registers that fbdev has clobbered and returns 1.
- *
- * \sa i810ValidateMode().
- */
-static int i810PostValidateMode( const DRIDriverContext *ctx )
-{
-   unsigned char *I810MMIO = ctx->MMIOAddress;
-   I810Ptr info = ctx->driverPrivate;
-
-   return 1;
-}
-
-
-/**
- * \brief Initialize the framebuffer device mode
- *
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Fills in \p info with some default values and some information from \p ctx
- * and then calls I810ScreenInit() for the screen initialization.
- * 
- * Before exiting clears the framebuffer memory accessing it directly.
- */
-static int i810InitFBDev( DRIDriverContext *ctx )
-{
-  I810Ptr info = calloc(1, sizeof(*info));
-
-   {
-      int  dummy = ctx->shared.virtualWidth;
-
-      switch (ctx->bpp / 8) {
-      case 1: dummy = (ctx->shared.virtualWidth + 127) & ~127; break;
-      case 2: dummy = (ctx->shared.virtualWidth +  31) &  ~31; break;
-      case 3:
-      case 4: dummy = (ctx->shared.virtualWidth +  15) &  ~15; break;
-      }
-
-      ctx->shared.virtualWidth = dummy;
-   }
-
-   ctx->driverPrivate = (void *)info;
-   
-   info->Chipset = ctx->chipset;
-
-   if (!I810ScreenInit( ctx, info ))
-      return 0;
-
-
-   return 1;
-}
-
-
-/**
- * \brief The screen is being closed, so clean up any state and free any
- * resources used by the DRI.
- *
- * \param ctx display handle.
- *
- * Unmaps the SAREA, closes the DRM device file descriptor and frees the driver
- * private data.
- */
-static void i810HaltFBDev( DRIDriverContext *ctx )
-{
-    drmUnmap( ctx->pSAREA, ctx->shared.SAREASize );
-    drmClose(ctx->drmFD);
-
-    if (ctx->driverPrivate) {
-       free(ctx->driverPrivate);
-       ctx->driverPrivate = 0;
-    }
-}
-
-
-extern void i810NotifyFocus( int );
-
-/**
- * \brief Exported driver interface for Mini GLX.
- *
- * \sa DRIDriverRec.
- */
-const struct DRIDriverRec __driDriver = {
-   i810ValidateMode,
-   i810PostValidateMode,
-   i810InitFBDev,
-   i810HaltFBDev,
-   I810EngineShutdown,
-   I810EngineRestore,  
-#ifndef _EMBEDDED
-   0,
-#else
-   i810NotifyFocus, 
-#endif
-};
diff --git a/src/mesa/drivers/dri/i915/server/intel_dri.c b/src/mesa/drivers/dri/i915/server/intel_dri.c
deleted file mode 120000
index effdd26448..0000000000
--- a/src/mesa/drivers/dri/i915/server/intel_dri.c
+++ /dev/null
@@ -1 +0,0 @@
-../../intel/server/intel_dri.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/i965/server/intel_dri.c b/src/mesa/drivers/dri/i965/server/intel_dri.c
deleted file mode 120000
index effdd26448..0000000000
--- a/src/mesa/drivers/dri/i965/server/intel_dri.c
+++ /dev/null
@@ -1 +0,0 @@
-../../intel/server/intel_dri.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/intel/server/intel_dri.c b/src/mesa/drivers/dri/intel/server/intel_dri.c
deleted file mode 100644
index e49c4214ad..0000000000
--- a/src/mesa/drivers/dri/intel/server/intel_dri.c
+++ /dev/null
@@ -1,1306 +0,0 @@
-/**
- * \file server/intel_dri.c
- * \brief File to perform the device-specific initialization tasks typically
- * done in the X server.
- *
- * Here they are converted to run in the client (or perhaps a standalone
- * process), and to work with the frame buffer device rather than the X
- * server infrastructure.
- * 
- * Copyright (C) 2006 Dave Airlie (airlied@linux.ie)
-
- Permission is hereby granted, free of charge, to any person obtaining a
- copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sub license, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
- 
- The above copyright notice and this permission notice (including the
- next paragraph) shall be included in all copies or substantial portions
- of the Software.
- 
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- IN NO EVENT SHALL THE COPYRIGHT HOLDERS AND/OR THEIR SUPPLIERS BE LIABLE FOR
- ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <errno.h>
-#include <unistd.h>
-
-#include "driver.h"
-#include "drm.h"
-
-#include "intel.h"
-#include "i830_dri.h"
-
-#include "memops.h"
-#include "pciaccess.h"
-
-static size_t drm_page_size;
-static int nextTile = 0;
-#define xf86DrvMsg(...) do {} while(0)
-
-static const int pitches[] = {
-  128 * 8,
-  128 * 16,
-  128 * 32,
-  128 * 64,
-  0
-};
-
-static Bool I830DRIDoMappings(DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea);
-
-static unsigned long
-GetBestTileAlignment(unsigned long size)
-{
-   unsigned long i;
-
-   for (i = KB(512); i < size; i <<= 1)
-      ;
-
-   if (i > MB(64))
-      i = MB(64);
-
-   return i;
-}
-
-static void SetFenceRegs(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-  int i;
-  unsigned char *MMIO = ctx->MMIOAddress;
-
-  for (i = 0; i < 8; i++) {
-    OUTREG(FENCE + i * 4, pI830->Fence[i]);
-    //    if (I810_DEBUG & DEBUG_VERBOSE_VGA)
-    fprintf(stderr,"Fence Register : %x\n", pI830->Fence[i]);
-  }
-}
-
-/* Tiled memory is good... really, really good...
- *
- * Need to make it less likely that we miss out on this - probably
- * need to move the frontbuffer away from the 'guarenteed' alignment
- * of the first memory segment, or perhaps allocate a discontigous
- * framebuffer to get more alignment 'sweet spots'.
- */
-static void
-SetFence(const DRIDriverContext *ctx, I830Rec *pI830,
-	 int nr, unsigned int start, unsigned int pitch,
-         unsigned int size)
-{
-   unsigned int val;
-   unsigned int fence_mask = 0;
-   unsigned int fence_pitch;
-
-   if (nr < 0 || nr > 7) {
-      fprintf(stderr,
-		 "SetFence: fence %d out of range\n",nr);
-      return;
-   }
-
-   pI830->Fence[nr] = 0;
-
-   if (IS_I9XX(pI830))
-   	fence_mask = ~I915G_FENCE_START_MASK;
-   else
-   	fence_mask = ~I830_FENCE_START_MASK;
-
-   if (start & fence_mask) {
-      fprintf(stderr,
-		 "SetFence: %d: start (0x%08x) is not %s aligned\n",
-		 nr, start, (IS_I9XX(pI830)) ? "1MB" : "512k");
-      return;
-   }
-
-   if (start % size) {
-      fprintf(stderr,
-		 "SetFence: %d: start (0x%08x) is not size (%dk) aligned\n",
-		 nr, start, size / 1024);
-      return;
-   }
-
-   if (pitch & 127) {
-      fprintf(stderr,
-		 "SetFence: %d: pitch (%d) not a multiple of 128 bytes\n",
-		 nr, pitch);
-      return;
-   }
-
-   val = (start | FENCE_X_MAJOR | FENCE_VALID);
-
-   if (IS_I9XX(pI830)) {
-   	switch (size) {
-	   case MB(1):
-      		val |= I915G_FENCE_SIZE_1M;
-      		break;
-   	   case MB(2):
-      		val |= I915G_FENCE_SIZE_2M;
-      		break;
-   	   case MB(4):
-      		val |= I915G_FENCE_SIZE_4M;
-      		break;
-   	   case MB(8):
-      		val |= I915G_FENCE_SIZE_8M;
-      		break;
-   	   case MB(16):
-      		val |= I915G_FENCE_SIZE_16M;
-      		break;
-   	   case MB(32):
-      		val |= I915G_FENCE_SIZE_32M;
-      		break;
-   	   case MB(64):
-      		val |= I915G_FENCE_SIZE_64M;
-      		break;
-   	   default:
-      		fprintf(stderr,
-		 "SetFence: %d: illegal size (%d kByte)\n", nr, size / 1024);
-      		return;
-   	}
-    } else {
-   	switch (size) {
-	   case KB(512):
-      		val |= FENCE_SIZE_512K;
-      		break;
-	   case MB(1):
-      		val |= FENCE_SIZE_1M;
-      		break;
-   	   case MB(2):
-      		val |= FENCE_SIZE_2M;
-      		break;
-   	   case MB(4):
-      		val |= FENCE_SIZE_4M;
-      		break;
-   	   case MB(8):
-      		val |= FENCE_SIZE_8M;
-      		break;
-   	   case MB(16):
-      		val |= FENCE_SIZE_16M;
-      		break;
-   	   case MB(32):
-      		val |= FENCE_SIZE_32M;
-      		break;
-   	   case MB(64):
-      		val |= FENCE_SIZE_64M;
-      		break;
-   	   default:
-      		fprintf(stderr,
-		 "SetFence: %d: illegal size (%d kByte)\n", nr, size / 1024);
-      		return;
-   	}
-   }
-
-   if (IS_I9XX(pI830))
-	fence_pitch = pitch / 512;
-   else
-	fence_pitch = pitch / 128;
-
-   switch (fence_pitch) {
-   case 1:
-      val |= FENCE_PITCH_1;
-      break;
-   case 2:
-      val |= FENCE_PITCH_2;
-      break;
-   case 4:
-      val |= FENCE_PITCH_4;
-      break;
-   case 8:
-      val |= FENCE_PITCH_8;
-      break;
-   case 16:
-      val |= FENCE_PITCH_16;
-      break;
-   case 32:
-      val |= FENCE_PITCH_32;
-      break;
-   case 64:
-      val |= FENCE_PITCH_64;
-      break;
-   default:
-      fprintf(stderr,
-		 "SetFence: %d: illegal pitch (%d)\n", nr, pitch);
-      return;
-   }
-
-   pI830->Fence[nr] = val;
-}
-
-static Bool
-MakeTiles(const DRIDriverContext *ctx, I830Rec *pI830, I830MemRange *pMem)
-{
-   int pitch, ntiles, i;
-
-   pitch = pMem->Pitch * ctx->cpp;
-   /*
-    * Simply try to break the region up into at most four pieces of size
-    * equal to the alignment.
-    */
-   ntiles = ROUND_TO(pMem->Size, pMem->Alignment) / pMem->Alignment;
-   if (ntiles >= 4) {
-      return FALSE;
-   }
-
-   for (i = 0; i < ntiles; i++, nextTile++) {
-     SetFence(ctx, pI830, nextTile, pMem->Start + i * pMem->Alignment,
-	       pitch, pMem->Alignment);
-   }
-   return TRUE;
-}
-
-static void I830SetupMemoryTiling(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-  int i;
-
-  /* Clear out */
-  for (i = 0; i < 8; i++)
-    pI830->Fence[i] = 0;
-  
-  nextTile = 0;
-
-  if (pI830->BackBuffer.Alignment >= KB(512)) {
-    if (MakeTiles(ctx, pI830, &(pI830->BackBuffer))) {
-      fprintf(stderr,
-		 "Activating tiled memory for the back buffer.\n");
-    } else {
-      fprintf(stderr,
-		 "MakeTiles failed for the back buffer.\n");
-      pI830->allowPageFlip = FALSE;
-    }
-  }
-  
-  if (pI830->DepthBuffer.Alignment >= KB(512)) {
-    if (MakeTiles(ctx, pI830, &(pI830->DepthBuffer))) {
-      fprintf(stderr,
-		 "Activating tiled memory for the depth buffer.\n");
-    } else {
-      fprintf(stderr,
-		 "MakeTiles failed for the depth buffer.\n");
-    }
-  }
-
-  return;
-}
-
-static int I830DetectMemory(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-  struct pci_device host_bridge, ig_dev;
-  uint32_t gmch_ctrl;
-  int memsize = 0;
-  int range;
-  uint32_t aper_size;
-  uint32_t membase2 = 0;
-      
-  memset(&host_bridge, 0, sizeof(host_bridge));
-  memset(&ig_dev, 0, sizeof(ig_dev));
-
-  ig_dev.dev = 2;
-
-  pci_device_cfg_read_u32(&host_bridge, &gmch_ctrl, I830_GMCH_CTRL);
-
-  if (IS_I830(pI830) || IS_845G(pI830)) {
-    if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
-      aper_size = 0x80000000;
-    } else {
-      aper_size = 0x40000000;
-    }
-  } else {
-    if (IS_I9XX(pI830)) {
-      int ret;
-      ret = pci_device_cfg_read_u32(&ig_dev, &membase2, 0x18);
-      if (membase2 & 0x08000000)
-	aper_size = 0x8000000;
-      else
-	aper_size = 0x10000000;
-
-      fprintf(stderr,"aper size is %08X %08x %d\n", aper_size, membase2, ret);
-    } else
-      aper_size = 0x8000000;
-  }
-
-  pI830->aper_size = aper_size;
-
-
-  /* We need to reduce the stolen size, by the GTT and the popup.
-   * The GTT varying according the the FbMapSize and the popup is 4KB */
-  range = (ctx->shared.fbSize / (1024*1024)) + 4;
-
-   if (IS_I85X(pI830) || IS_I865G(pI830) || IS_I9XX(pI830)) {
-      switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
-      case I855_GMCH_GMS_STOLEN_1M:
-	 memsize = MB(1) - KB(range);
-	 break;
-      case I855_GMCH_GMS_STOLEN_4M:
-	 memsize = MB(4) - KB(range);
-	 break;
-      case I855_GMCH_GMS_STOLEN_8M:
-	 memsize = MB(8) - KB(range);
-	 break;
-      case I855_GMCH_GMS_STOLEN_16M:
-	 memsize = MB(16) - KB(range);
-	 break;
-      case I855_GMCH_GMS_STOLEN_32M:
-	 memsize = MB(32) - KB(range);
-	 break;
-      case I915G_GMCH_GMS_STOLEN_48M:
-	 if (IS_I9XX(pI830))
-	    memsize = MB(48) - KB(range);
-	 break;
-      case I915G_GMCH_GMS_STOLEN_64M:
-	 if (IS_I9XX(pI830))
-	    memsize = MB(64) - KB(range);
-	 break;
-      }
-   } else {
-      switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
-      case I830_GMCH_GMS_STOLEN_512:
-	 memsize = KB(512) - KB(range);
-	 break;
-      case I830_GMCH_GMS_STOLEN_1024:
-	 memsize = MB(1) - KB(range);
-	 break;
-      case I830_GMCH_GMS_STOLEN_8192:
-	 memsize = MB(8) - KB(range);
-	 break;
-      case I830_GMCH_GMS_LOCAL:
-	 memsize = 0;
-	 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
-		    "Local memory found, but won't be used.\n");
-	 break;
-      }
-   }
-   if (memsize > 0) {
-     fprintf(stderr,
-		 "detected %d kB stolen memory.\n", memsize / 1024);
-   } else {
-     fprintf(stderr,
-		 "no video memory detected.\n");
-   }
-   return memsize;
-}
-
-static int AgpInit(const DRIDriverContext *ctx, I830Rec *info)
-{
-  unsigned long mode = 0x4;
-
-  if (drmAgpAcquire(ctx->drmFD) < 0) {
-    fprintf(stderr, "[gart] AGP not available\n");
-    return 0;
-  }
-  
-  if (drmAgpEnable(ctx->drmFD, mode) < 0) {
-    fprintf(stderr, "[gart] AGP not enabled\n");
-    drmAgpRelease(ctx->drmFD);
-    return 0;
-  }
-  else
-    fprintf(stderr, "[gart] AGP enabled at %dx\n", ctx->agpmode);
-
-  return 1;
-}
-
-/*
- * Allocate memory from the given pool.  Grow the pool if needed and if
- * possible.
- */
-static unsigned long
-AllocFromPool(const DRIDriverContext *ctx, I830Rec *pI830, 
-	      I830MemRange *result, I830MemPool *pool,
-	      long size, unsigned long alignment, int flags)
-{
-   long needed, start, end;
-
-   if (!result || !pool || !size)
-      return 0;
-
-   /* Calculate how much space is needed. */
-   if (alignment <= GTT_PAGE_SIZE)
-      needed = size;
-   else {
-	 start = ROUND_TO(pool->Free.Start, alignment);
-	 end = ROUND_TO(start + size, alignment);
-	 needed = end - pool->Free.Start;
-   }
-   if (needed > pool->Free.Size) {
-     return 0;
-   }
-
-   result->Start = ROUND_TO(pool->Free.Start, alignment);
-   pool->Free.Start += needed;
-   result->End = pool->Free.Start;
-
-   pool->Free.Size = pool->Free.End - pool->Free.Start;
-   result->Size = result->End - result->Start;
-   result->Pool = pool;
-   result->Alignment = alignment;
-   return needed;
-}
-
-static unsigned long AllocFromAGP(const DRIDriverContext *ctx, I830Rec *pI830, long size, unsigned long alignment, I830MemRange  *result)
-{
-   unsigned long start, end;
-   unsigned long newApStart, newApEnd;
-   int ret;
-   if (!result || !size)
-      return 0;
-   
-   if (!alignment)
-     alignment = 4;
-
-   start = ROUND_TO(pI830->MemoryAperture.Start, alignment);
-   end = ROUND_TO(start + size, alignment);
-   newApStart = end;
-   newApEnd = pI830->MemoryAperture.End;
-
-   ret=drmAgpAlloc(ctx->drmFD, size, 0, &(result->Physical), (drm_handle_t *)&(result->Key));
-   
-   if (ret)
-   {
-     fprintf(stderr,"drmAgpAlloc failed %d\n", ret);
-     return 0;
-   }
-   pI830->allocatedMemory += size;
-   pI830->MemoryAperture.Start = newApStart;
-   pI830->MemoryAperture.End = newApEnd;
-   pI830->MemoryAperture.Size = newApEnd - newApStart;
-   //   pI830->FreeMemory -= size;
-   result->Start = start;
-   result->End = start + size;
-   result->Size = size;
-   result->Offset = start;
-   result->Alignment = alignment;
-   result->Pool = NULL;
-  
-   return size;
-}
-
-unsigned long
-I830AllocVidMem(const DRIDriverContext *ctx, I830Rec *pI830,
-                I830MemRange *result, I830MemPool *pool, long size,
-                unsigned long alignment, int flags)
-{
-   unsigned long ret;
-
-   if (!result)
-      return 0;
-
-   /* Make sure these are initialised. */
-   result->Size = 0;
-   result->Key = -1;
-
-   if (!size) {
-      return 0;
-   }
-
-   if (pool->Free.Size < size) {
-      ret = AllocFromAGP(ctx, pI830, size, alignment, result);
-   }
-   else {
-      ret = AllocFromPool(ctx, pI830, result, pool, size, alignment, flags);
-      if (ret == 0)
-         ret = AllocFromAGP(ctx, pI830, size, alignment, result);
-   }
-   return ret;
-}
-
-static Bool BindAgpRange(const DRIDriverContext *ctx, I830MemRange *mem)
-{
-  if (!mem)
-    return FALSE;
-  
-  if (mem->Key == -1)
-    return TRUE;
-
-  return !drmAgpBind(ctx->drmFD, mem->Key, mem->Offset);
-}
-
-/* simple memory allocation routines needed */
-/* put ring buffer in low memory */
-/* need to allocate front, back, depth buffers aligned correctly,
-   allocate ring buffer, 
-*/
-
-/* */
-static Bool
-I830AllocateMemory(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-  unsigned long size, ret;
-  unsigned long lines, lineSize, align;
-
-  /* allocate ring buffer */
-  memset(pI830->LpRing, 0, sizeof(I830RingBuffer));
-  pI830->LpRing->mem.Key = -1;
-
-  size = PRIMARY_RINGBUFFER_SIZE;
-  
-  ret = I830AllocVidMem(ctx, pI830, &pI830->LpRing->mem, &pI830->StolenPool, size, 0x1000, 0);
-  
-  if (ret != size)
-  {
-    fprintf(stderr,"unable to allocate ring buffer %ld\n", ret);
-    return FALSE;
-  }
-
-  pI830->LpRing->tail_mask = pI830->LpRing->mem.Size - 1;
-
-  
-  /* allocate front buffer */
-  memset(&(pI830->FrontBuffer), 0, sizeof(pI830->FrontBuffer));
-  pI830->FrontBuffer.Key = -1;
-  pI830->FrontBuffer.Pitch = ctx->shared.virtualWidth;
-
-  align = KB(512);  
-
-  lineSize = ctx->shared.virtualWidth * ctx->cpp;
-  lines = (ctx->shared.virtualHeight + 15) / 16 * 16;
-  size = lineSize * lines;
-  size = ROUND_TO_PAGE(size);
-
-  align = GetBestTileAlignment(size);
-
-  ret = I830AllocVidMem(ctx, pI830, &pI830->FrontBuffer, &pI830->StolenPool, size, align, 0);
-  if (ret < size)
-  {
-    fprintf(stderr,"unable to allocate front buffer %ld\n", ret);
-    return FALSE;
-  }
-
-  memset(&(pI830->BackBuffer), 0, sizeof(pI830->BackBuffer));
-  pI830->BackBuffer.Key = -1;
-  pI830->BackBuffer.Pitch = ctx->shared.virtualWidth;
-
-  ret = I830AllocVidMem(ctx, pI830, &pI830->BackBuffer, &pI830->StolenPool, size, align, 0);
-  if (ret < size)
-  {
-    fprintf(stderr,"unable to allocate back buffer %ld\n", ret);
-    return FALSE;
-  }
-  
-  memset(&(pI830->DepthBuffer), 0, sizeof(pI830->DepthBuffer));
-  pI830->DepthBuffer.Key = -1;
-  pI830->DepthBuffer.Pitch = ctx->shared.virtualWidth;
-
-  ret = I830AllocVidMem(ctx, pI830, &pI830->DepthBuffer, &pI830->StolenPool, size, align, 0);
-  if (ret < size)
-  {
-    fprintf(stderr,"unable to allocate depth buffer %ld\n", ret);
-    return FALSE;
-  }
-
-  memset(&(pI830->ContextMem), 0, sizeof(pI830->ContextMem));
-  pI830->ContextMem.Key = -1;
-  size = KB(32);
-
-  ret = I830AllocVidMem(ctx, pI830, &pI830->ContextMem, &pI830->StolenPool, size, align, 0);
-  if (ret < size)
-  {
-    fprintf(stderr,"unable to allocate context buffer %ld\n", ret);
-    return FALSE;
-  }
-
-#if 0  
-  memset(&(pI830->TexMem), 0, sizeof(pI830->TexMem));
-  pI830->TexMem.Key = -1;
-
-  size = 32768 * 1024;
-  ret = AllocFromAGP(ctx, pI830, size, align, &pI830->TexMem);
-  if (ret < size)
-  {
-    fprintf(stderr,"unable to allocate texture memory %ld\n", ret);
-    return FALSE;
-  }
-#endif
-
-  return TRUE;
-}
-
-static Bool
-I830BindMemory(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-  if (!BindAgpRange(ctx, &pI830->LpRing->mem))
-    return FALSE;
-  if (!BindAgpRange(ctx, &pI830->FrontBuffer))
-    return FALSE;
-  if (!BindAgpRange(ctx, &pI830->BackBuffer))
-    return FALSE;
-  if (!BindAgpRange(ctx, &pI830->DepthBuffer))
-    return FALSE;
-  if (!BindAgpRange(ctx, &pI830->ContextMem))
-    return FALSE;
-#if 0
-  if (!BindAgpRange(ctx, &pI830->TexMem))
-    return FALSE;
-#endif
-  return TRUE;
-}
-
-static void SetupDRIMM(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-  unsigned long aperEnd = ROUND_DOWN_TO(pI830->aper_size, GTT_PAGE_SIZE) / GTT_PAGE_SIZE;
-  unsigned long aperStart = ROUND_TO(pI830->aper_size - KB(32768), GTT_PAGE_SIZE) / GTT_PAGE_SIZE;
-
-  fprintf(stderr, "aper size is %08X\n", ctx->shared.fbSize);
-  if (drmMMInit(ctx->drmFD, aperStart, aperEnd - aperStart, DRM_BO_MEM_TT)) {
-      fprintf(stderr,
-	      "DRM MM Initialization Failed\n");
-  } else {
-    fprintf(stderr,
-	    "DRM MM Initialized at offset 0x%lx length %d page\n", aperStart, aperEnd-aperStart);
-  }
-
-}
-
-static Bool
-I830CleanupDma(const DRIDriverContext *ctx)
-{
-   drmI830Init info;
-
-   memset(&info, 0, sizeof(drmI830Init));
-   info.func = I830_CLEANUP_DMA;
-
-   if (drmCommandWrite(ctx->drmFD, DRM_I830_INIT,
-		       &info, sizeof(drmI830Init))) {
-     fprintf(stderr, "I830 Dma Cleanup Failed\n");
-      return FALSE;
-   }
-
-   return TRUE;
-}
-
-static Bool
-I830InitDma(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-   I830RingBuffer *ring = pI830->LpRing;
-   drmI830Init info;
-
-   memset(&info, 0, sizeof(drmI830Init));
-   info.func = I830_INIT_DMA;
-
-   info.ring_start = ring->mem.Start + pI830->LinearAddr;
-   info.ring_end = ring->mem.End + pI830->LinearAddr;
-   info.ring_size = ring->mem.Size;
-
-   info.mmio_offset = (unsigned int)ctx->MMIOStart;
-
-   info.sarea_priv_offset = sizeof(drm_sarea_t);
-
-   info.front_offset = pI830->FrontBuffer.Start;
-   info.back_offset = pI830->BackBuffer.Start;
-   info.depth_offset = pI830->DepthBuffer.Start;
-   info.w = ctx->shared.virtualWidth;
-   info.h = ctx->shared.virtualHeight;
-   info.pitch = ctx->shared.virtualWidth;
-   info.back_pitch = pI830->BackBuffer.Pitch;
-   info.depth_pitch = pI830->DepthBuffer.Pitch;
-   info.cpp = ctx->cpp;
-
-   if (drmCommandWrite(ctx->drmFD, DRM_I830_INIT,
-		       &info, sizeof(drmI830Init))) {
-      fprintf(stderr,
-		 "I830 Dma Initialization Failed\n");
-      return FALSE;
-   }
-
-   return TRUE;
-}
-
-static int I830CheckDRMVersion( const DRIDriverContext *ctx,
-				  I830Rec *pI830 )
-{
-   drmVersionPtr  version;
-
-   version = drmGetVersion(ctx->drmFD);
-
-   if (version) {
-     int req_minor, req_patch;
-
-     req_minor = 4;
-     req_patch = 0;	
-
-     if (version->version_major != 1 ||
-	 version->version_minor < req_minor ||
-	 (version->version_minor == req_minor && 
-	  version->version_patchlevel < req_patch)) {
-       /* Incompatible drm version */
-       fprintf(stderr,
-	       "[dri] I830DRIScreenInit failed because of a version "
-	       "mismatch.\n"
-	       "[dri] i915.o kernel module version is %d.%d.%d "
-	       "but version 1.%d.%d or newer is needed.\n"
-	       "[dri] Disabling DRI.\n",
-	       version->version_major,
-	       version->version_minor,
-	       version->version_patchlevel,
-	       req_minor,
-	       req_patch);
-       drmFreeVersion(version);
-       return 0;
-     }
-     
-     pI830->drmMinor = version->version_minor;
-     drmFreeVersion(version);
-   }
-   return 1;
-}
-
-static void
-I830SetRingRegs(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-  unsigned int itemp;
-  unsigned char *MMIO = ctx->MMIOAddress;
-
-   OUTREG(LP_RING + RING_LEN, 0);
-   OUTREG(LP_RING + RING_TAIL, 0);
-   OUTREG(LP_RING + RING_HEAD, 0);
-
-   if ((long)(pI830->LpRing->mem.Start & I830_RING_START_MASK) !=
-       pI830->LpRing->mem.Start) {
-      fprintf(stderr,
-		 "I830SetRingRegs: Ring buffer start (%lx) violates its "
-		 "mask (%x)\n", pI830->LpRing->mem.Start, I830_RING_START_MASK);
-   }
-   /* Don't care about the old value.  Reserved bits must be zero anyway. */
-   itemp = pI830->LpRing->mem.Start & I830_RING_START_MASK;
-   OUTREG(LP_RING + RING_START, itemp);
-
-   if (((pI830->LpRing->mem.Size - 4096) & I830_RING_NR_PAGES) !=
-       pI830->LpRing->mem.Size - 4096) {
-      fprintf(stderr,
-		 "I830SetRingRegs: Ring buffer size - 4096 (%lx) violates its "
-		 "mask (%x)\n", pI830->LpRing->mem.Size - 4096,
-		 I830_RING_NR_PAGES);
-   }
-   /* Don't care about the old value.  Reserved bits must be zero anyway. */
-   itemp = (pI830->LpRing->mem.Size - 4096) & I830_RING_NR_PAGES;
-   itemp |= (RING_NO_REPORT | RING_VALID);
-   OUTREG(LP_RING + RING_LEN, itemp);
-
-   pI830->LpRing->head = INREG(LP_RING + RING_HEAD) & I830_HEAD_MASK;
-   pI830->LpRing->tail = INREG(LP_RING + RING_TAIL);
-   pI830->LpRing->space = pI830->LpRing->head - (pI830->LpRing->tail + 8);
-   if (pI830->LpRing->space < 0)
-      pI830->LpRing->space += pI830->LpRing->mem.Size;
-
-   SetFenceRegs(ctx, pI830);
-   
-   /* RESET THE DISPLAY PIPE TO POINT TO THE FRONTBUFFER - hacky
-      hacky hacky */
-   OUTREG(DSPABASE, pI830->FrontBuffer.Start + pI830->LinearAddr);
-
-}
-
-static Bool
-I830SetParam(const DRIDriverContext *ctx, int param, int value)
-{
-   drmI830SetParam sp;
-
-   memset(&sp, 0, sizeof(sp));
-   sp.param = param;
-   sp.value = value;
-
-   if (drmCommandWrite(ctx->drmFD, DRM_I830_SETPARAM, &sp, sizeof(sp))) {
-      fprintf(stderr, "I830 SetParam Failed\n");
-      return FALSE;
-   }
-
-   return TRUE;
-}
-
-static Bool
-I830DRIMapScreenRegions(DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea)
-{
-   fprintf(stderr,
-              "[drm] Mapping front buffer\n");
-
-   if (drmAddMap(ctx->drmFD,
-                 (drm_handle_t)(sarea->front_offset + pI830->LinearAddr),
-                 sarea->front_size,
-                 DRM_FRAME_BUFFER,  /*DRM_AGP,*/
-                 0,
-                 &sarea->front_handle) < 0) {
-     fprintf(stderr,
-	     "[drm] drmAddMap(front_handle) failed. Disabling DRI\n");
-      return FALSE;
-   }
-   ctx->shared.hFrameBuffer = sarea->front_handle;
-   ctx->shared.fbSize = sarea->front_size;
-   fprintf(stderr, "[drm] Front Buffer = 0x%08x\n",
-	   sarea->front_handle);
-
-   if (drmAddMap(ctx->drmFD,
-                 (drm_handle_t)(sarea->back_offset),
-                 sarea->back_size, DRM_AGP, 0,
-                 &sarea->back_handle) < 0) {
-      fprintf(stderr,
-                 "[drm] drmAddMap(back_handle) failed. Disabling DRI\n");
-      return FALSE;
-   }
-   fprintf(stderr, "[drm] Back Buffer = 0x%08x\n",
-              sarea->back_handle);
-
-   if (drmAddMap(ctx->drmFD,
-                 (drm_handle_t)sarea->depth_offset,
-                 sarea->depth_size, DRM_AGP, 0,
-                 &sarea->depth_handle) < 0) {
-      fprintf(stderr,
-                 "[drm] drmAddMap(depth_handle) failed. Disabling DRI\n");
-      return FALSE;
-   }
-   fprintf(stderr, "[drm] Depth Buffer = 0x%08x\n",
-              sarea->depth_handle);
-
-#if 0
-   if (drmAddMap(ctx->drmFD,
-		 (drm_handle_t)sarea->tex_offset,
-		 sarea->tex_size, DRM_AGP, 0,
-		 &sarea->tex_handle) < 0) {
-      fprintf(stderr,
-		 "[drm] drmAddMap(tex_handle) failed. Disabling DRI\n");
-      return FALSE;
-   }
-   fprintf(stderr, "[drm] textures = 0x%08x\n",
-	      sarea->tex_handle);
-#endif
-   return TRUE;
-}
-
-
-static void
-I830DRIUnmapScreenRegions(const DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea)
-{
-#if 1
-   if (sarea->front_handle) {
-      drmRmMap(ctx->drmFD, sarea->front_handle);
-      sarea->front_handle = 0;
-   }
-#endif
-   if (sarea->back_handle) {
-      drmRmMap(ctx->drmFD, sarea->back_handle);
-      sarea->back_handle = 0;
-   }
-   if (sarea->depth_handle) {
-      drmRmMap(ctx->drmFD, sarea->depth_handle);
-      sarea->depth_handle = 0;
-   }
-   if (sarea->tex_handle) {
-      drmRmMap(ctx->drmFD, sarea->tex_handle);
-      sarea->tex_handle = 0;
-   }
-}
-
-static Bool
-I830DRIDoMappings(DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea)
-{
-  if (drmAddMap(ctx->drmFD,
-		(drm_handle_t)pI830->LpRing->mem.Start,
-		pI830->LpRing->mem.Size, DRM_AGP, 0,
-		&pI830->ring_map) < 0) {
-    fprintf(stderr,
-	    "[drm] drmAddMap(ring_map) failed. Disabling DRI\n");
-    return FALSE;
-  }
-  fprintf(stderr, "[drm] ring buffer = 0x%08x\n",
-	  pI830->ring_map);
-
-  if (I830InitDma(ctx, pI830) == FALSE) {
-    return FALSE;
-  }
-  
-   /* init to zero to be safe */
-
-  I830DRIMapScreenRegions(ctx, pI830, sarea);
-  SetupDRIMM(ctx, pI830);
-
-   if (ctx->pciDevice != PCI_CHIP_845_G &&
-       ctx->pciDevice != PCI_CHIP_I830_M) {
-      I830SetParam(ctx, I830_SETPARAM_USE_MI_BATCHBUFFER_START, 1 );
-   }
-
-   /* Okay now initialize the dma engine */
-   {
-      pI830->irq = drmGetInterruptFromBusID(ctx->drmFD,
-					    ctx->pciBus,
-					    ctx->pciDevice,
-					    ctx->pciFunc);
-
-      if (drmCtlInstHandler(ctx->drmFD, pI830->irq)) {
-	 fprintf(stderr,
-		    "[drm] failure adding irq handler\n");
-	 pI830->irq = 0;
-	 return FALSE;
-      }
-      else
-	 fprintf(stderr,
-		    "[drm] dma control initialized, using IRQ %d\n",
-		    pI830->irq);
-   }
-
-   fprintf(stderr, "[dri] visual configs initialized\n");
-
-   return TRUE;
-}
-
-static Bool
-I830ClearScreen(DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea)
-{
-  /* need to drmMap front and back buffers and zero them */
-  drmAddress map_addr;
-  int ret;
-
-  ret = drmMap(ctx->drmFD,
-	       sarea->front_handle,
-	       sarea->front_size,
-	       &map_addr);
-
-  if (ret)
-  {
-    fprintf(stderr, "Unable to map front buffer\n");
-    return FALSE;
-  }
-
-  drimemsetio((char *)map_addr,
-	      0,
-	      sarea->front_size);
-  drmUnmap(map_addr, sarea->front_size);
-
-
-  ret = drmMap(ctx->drmFD,
-	       sarea->back_handle,
-	       sarea->back_size,
-	       &map_addr);
-
-  if (ret)
-  {
-    fprintf(stderr, "Unable to map back buffer\n");
-    return FALSE;
-  }
-
-  drimemsetio((char *)map_addr,
-	      0,
-	      sarea->back_size);
-  drmUnmap(map_addr, sarea->back_size);
-
-  return TRUE;
-}
-
-static Bool
-I830ScreenInit(DRIDriverContext *ctx, I830Rec *pI830)
-		  
-{
-   I830DRIPtr pI830DRI;
-   drmI830Sarea *pSAREAPriv;
-   int err;
-      
-   drm_page_size = getpagesize();   
-
-   pI830->registerSize = ctx->MMIOSize;
-   /* This is a hack for now.  We have to have more than a 4k page here
-    * because of the size of the state.  However, the state should be
-    * in a per-context mapping.  This will be added in the Mesa 3.5 port
-    * of the I830 driver.
-    */
-   ctx->shared.SAREASize = SAREA_MAX;
-
-   /* Note that drmOpen will try to load the kernel module, if needed. */
-   ctx->drmFD = drmOpen("i915", NULL );
-   if (ctx->drmFD < 0) {
-      fprintf(stderr, "[drm] drmOpen failed\n");
-      return 0;
-   }
-
-   if ((err = drmSetBusid(ctx->drmFD, ctx->pciBusID)) < 0) {
-      fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n",
-	      ctx->drmFD, ctx->pciBusID, strerror(-err));
-      return 0;
-   }
-
-   if (drmAddMap( ctx->drmFD,
-		  0,
-		  ctx->shared.SAREASize,
-		  DRM_SHM,
-		  DRM_CONTAINS_LOCK,
-		  &ctx->shared.hSAREA) < 0)
-   {
-     fprintf(stderr, "[drm] drmAddMap failed\n");
-     return 0;
-   }
-
-   fprintf(stderr, "[drm] added %d byte SAREA at 0x%08x\n",
-	   ctx->shared.SAREASize, ctx->shared.hSAREA);
-   
-   if (drmMap( ctx->drmFD,
-	       ctx->shared.hSAREA,
-	       ctx->shared.SAREASize,
-	       (drmAddressPtr)(&ctx->pSAREA)) < 0)
-   {
-      fprintf(stderr, "[drm] drmMap failed\n");
-      return 0;
-   
-   }
-   
-   memset(ctx->pSAREA, 0, ctx->shared.SAREASize);
-   fprintf(stderr, "[drm] mapped SAREA 0x%08x to %p, size %d\n",
-	   ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize);
-   
-
-   if (drmAddMap(ctx->drmFD, 
-		 ctx->MMIOStart,
-		 ctx->MMIOSize,
-		 DRM_REGISTERS, 
-		 DRM_READ_ONLY, 
-		 &pI830->registerHandle) < 0) {
-      fprintf(stderr, "[drm] drmAddMap mmio failed\n");	
-      return 0;
-   }
-   fprintf(stderr,
-	   "[drm] register handle = 0x%08x\n", pI830->registerHandle);
-
-
-   if (!I830CheckDRMVersion(ctx, pI830)) {
-     return FALSE;
-   }
-
-   /* Create a 'server' context so we can grab the lock for
-    * initialization ioctls.
-    */
-   if ((err = drmCreateContext(ctx->drmFD, &ctx->serverContext)) != 0) {
-      fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err);
-      return 0;
-   }
-
-   DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0); 
-
-   /* Initialize the SAREA private data structure */
-   pSAREAPriv = (drmI830Sarea *)(((char*)ctx->pSAREA) + 
-				 sizeof(drm_sarea_t));
-   memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
-
-   pI830->StolenMemory.Size = I830DetectMemory(ctx, pI830);
-   pI830->StolenMemory.Start = 0;
-   pI830->StolenMemory.End = pI830->StolenMemory.Size;
-
-   pI830->MemoryAperture.Start = pI830->StolenMemory.End;
-   pI830->MemoryAperture.End = KB(40000);
-   pI830->MemoryAperture.Size = pI830->MemoryAperture.End - pI830->MemoryAperture.Start;
-
-   pI830->StolenPool.Fixed = pI830->StolenMemory;
-   pI830->StolenPool.Total = pI830->StolenMemory;
-   pI830->StolenPool.Free = pI830->StolenPool.Total;
-   pI830->FreeMemory = pI830->StolenPool.Total.Size;
-
-   if (!AgpInit(ctx, pI830))
-     return FALSE;
-
-   if (I830AllocateMemory(ctx, pI830) == FALSE)
-   {
-     return FALSE;
-   }
-
-   if (I830BindMemory(ctx, pI830) == FALSE)
-   {
-     return FALSE;
-   }
-
-   pSAREAPriv->rotated_offset = -1;
-   pSAREAPriv->rotated_size = 0;
-   pSAREAPriv->rotated_pitch = ctx->shared.virtualWidth;
-
-   pSAREAPriv->front_offset = pI830->FrontBuffer.Start;
-   pSAREAPriv->front_size = pI830->FrontBuffer.Size;
-   pSAREAPriv->width = ctx->shared.virtualWidth;
-   pSAREAPriv->height = ctx->shared.virtualHeight;
-   pSAREAPriv->pitch = ctx->shared.virtualWidth;
-   pSAREAPriv->virtualX = ctx->shared.virtualWidth;
-   pSAREAPriv->virtualY = ctx->shared.virtualHeight;
-   pSAREAPriv->back_offset = pI830->BackBuffer.Start;
-   pSAREAPriv->back_size = pI830->BackBuffer.Size;
-   pSAREAPriv->depth_offset = pI830->DepthBuffer.Start;
-   pSAREAPriv->depth_size = pI830->DepthBuffer.Size;
-#if 0
-   pSAREAPriv->tex_offset = pI830->TexMem.Start;
-   pSAREAPriv->tex_size = pI830->TexMem.Size;
-#endif
-   pSAREAPriv->log_tex_granularity = pI830->TexGranularity;
-
-   ctx->driverClientMsg = malloc(sizeof(I830DRIRec));
-   ctx->driverClientMsgSize = sizeof(I830DRIRec);
-   pI830DRI = (I830DRIPtr)ctx->driverClientMsg;
-   pI830DRI->deviceID = pI830->Chipset;
-   pI830DRI->regsSize = I830_REG_SIZE;
-   pI830DRI->width = ctx->shared.virtualWidth;
-   pI830DRI->height = ctx->shared.virtualHeight;
-   pI830DRI->mem = ctx->shared.fbSize;
-   pI830DRI->cpp = ctx->cpp;
-
-   pI830DRI->bitsPerPixel = ctx->bpp;
-   pI830DRI->sarea_priv_offset = sizeof(drm_sarea_t);
-   
-   err = I830DRIDoMappings(ctx, pI830, pSAREAPriv);
-   if (err == FALSE)
-       return FALSE;
-
-   I830SetupMemoryTiling(ctx, pI830);
-
-   /* Quick hack to clear the front & back buffers.  Could also use
-    * the clear ioctl to do this, but would need to setup hw state
-    * first.
-    */
-   I830ClearScreen(ctx, pI830, pSAREAPriv);
-
-   I830SetRingRegs(ctx, pI830);
-
-   return TRUE;
-}
-
-
-/**
- * \brief Validate the fbdev mode.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Saves some registers and returns 1.
- *
- * \sa radeonValidateMode().
- */
-static int i830ValidateMode( const DRIDriverContext *ctx )
-{
-  return 1;
-}
-
-/**
- * \brief Examine mode returned by fbdev.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Restores registers that fbdev has clobbered and returns 1.
- *
- * \sa i810ValidateMode().
- */
-static int i830PostValidateMode( const DRIDriverContext *ctx )
-{
-  I830Rec *pI830 = ctx->driverPrivate;
-
-  I830SetRingRegs(ctx, pI830);
-  return 1;
-}
-
-
-/**
- * \brief Initialize the framebuffer device mode
- *
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Fills in \p info with some default values and some information from \p ctx
- * and then calls I810ScreenInit() for the screen initialization.
- * 
- * Before exiting clears the framebuffer memory accessing it directly.
- */
-static int i830InitFBDev( DRIDriverContext *ctx )
-{
-  I830Rec *pI830 = calloc(1, sizeof(I830Rec));
-  int i;
-
-   {
-      int  dummy = ctx->shared.virtualWidth;
-
-      switch (ctx->bpp / 8) {
-      case 1: dummy = (ctx->shared.virtualWidth + 127) & ~127; break;
-      case 2: dummy = (ctx->shared.virtualWidth +  31) &  ~31; break;
-      case 3:
-      case 4: dummy = (ctx->shared.virtualWidth +  15) &  ~15; break;
-      }
-
-      ctx->shared.virtualWidth = dummy;
-      ctx->shared.Width = ctx->shared.virtualWidth;
-   }
-
-
-   for (i = 0; pitches[i] != 0; i++) {
-     if (pitches[i] >= ctx->shared.virtualWidth) {
-       ctx->shared.virtualWidth = pitches[i];
-       break;
-     }
-   }
-
-   ctx->driverPrivate = (void *)pI830;
-   
-   pI830->LpRing = calloc(1, sizeof(I830RingBuffer));
-   pI830->Chipset = ctx->chipset;
-   pI830->LinearAddr = ctx->FBStart;
-
-   if (!I830ScreenInit( ctx, pI830 ))
-      return 0;
-
-   
-   return 1;
-}
-
-
-/**
- * \brief The screen is being closed, so clean up any state and free any
- * resources used by the DRI.
- *
- * \param ctx display handle.
- *
- * Unmaps the SAREA, closes the DRM device file descriptor and frees the driver
- * private data.
- */
-static void i830HaltFBDev( DRIDriverContext *ctx )
-{
-  drmI830Sarea *pSAREAPriv;
-  I830Rec *pI830 = ctx->driverPrivate;
-
-   if (pI830->irq) {
-       drmCtlUninstHandler(ctx->drmFD);
-       pI830->irq = 0;   }
-
-   I830CleanupDma(ctx);
-
-  pSAREAPriv = (drmI830Sarea *)(((char*)ctx->pSAREA) + 
-				sizeof(drm_sarea_t));
-
-  I830DRIUnmapScreenRegions(ctx, pI830, pSAREAPriv);
-  drmUnmap( ctx->pSAREA, ctx->shared.SAREASize );
-  drmClose(ctx->drmFD);
-  
-  if (ctx->driverPrivate) {
-    free(ctx->driverPrivate);
-    ctx->driverPrivate = 0;
-  }
-}
-
-
-extern void i810NotifyFocus( int );
-
-/**
- * \brief Exported driver interface for Mini GLX.
- *
- * \sa DRIDriverRec.
- */
-const struct DRIDriverRec __driDriver = {
-   i830ValidateMode,
-   i830PostValidateMode,
-   i830InitFBDev,
-   i830HaltFBDev,
-   NULL,//I830EngineShutdown,
-   NULL, //I830EngineRestore,  
-#ifndef _EMBEDDED
-   0,
-#else
-   i810NotifyFocus, 
-#endif
-};
diff --git a/src/mesa/drivers/dri/mga/server/mga_dri.c b/src/mesa/drivers/dri/mga/server/mga_dri.c
deleted file mode 100644
index bc575e62ee..0000000000
--- a/src/mesa/drivers/dri/mga/server/mga_dri.c
+++ /dev/null
@@ -1,1088 +0,0 @@
-
-/*
- * Copyright 2000 VA Linux Systems Inc., Fremont, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES
- * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Keith Whitwell <keith@tungstengraphics.com>
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-#include <errno.h>
-#include <unistd.h>
-#include <string.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <inttypes.h>
-
-#include "driver.h"
-#include "drm.h"
-#include "memops.h"
-
-#include "mga_reg.h"
-#include "mga.h"
-#include "mga_macros.h"
-#include "mga_dri.h"
-
-
-/* Quiescence, locking
- */
-#define MGA_TIMEOUT		2048
-
-static void MGAWaitForIdleDMA( struct DRIDriverContextRec *ctx, MGAPtr pMga )
-{
-   drm_lock_t lock;
-   int ret;
-   int i = 0;
-
-   memset( &lock, 0, sizeof(lock) );
-
-   for (;;) {
-      do {
-         /* first ask for quiescent and flush */
-         lock.flags = DRM_LOCK_QUIESCENT | DRM_LOCK_FLUSH;
-         do {
-	    ret = drmCommandWrite( ctx->drmFD, DRM_MGA_FLUSH,
-                                   &lock, sizeof( lock ) );
-         } while ( ret == -EBUSY && i++ < DRM_MGA_IDLE_RETRY );
-
-         /* if it's still busy just try quiescent */
-         if ( ret == -EBUSY ) { 
-            lock.flags = DRM_LOCK_QUIESCENT;
-            do {
-	       ret = drmCommandWrite( ctx->drmFD, DRM_MGA_FLUSH,
-                                      &lock, sizeof( lock ) );
-            } while ( ret == -EBUSY && i++ < DRM_MGA_IDLE_RETRY );
-         }
-      } while ( ( ret == -EBUSY ) && ( i++ < MGA_TIMEOUT ) );
-
-      if ( ret == 0 )
-	 return;
-
-      fprintf( stderr,
-               "[dri] Idle timed out, resetting engine...\n" );
-
-      drmCommandNone( ctx->drmFD, DRM_MGA_RESET );
-   }
-}
-
-static unsigned int mylog2( unsigned int n )
-{
-   unsigned int log2 = 1;
-   while ( n > 1 ) n >>= 1, log2++;
-   return log2;
-}
-
-static int MGADRIAgpInit(struct DRIDriverContextRec *ctx, MGAPtr pMga)
-{
-   unsigned long mode;
-   unsigned int vendor, device;
-   int ret, count, i;
-
-   if(pMga->agpSize < 12)pMga->agpSize = 12;
-   if(pMga->agpSize > 64)pMga->agpSize = 64; /* cap */
-
-   /* FIXME: Make these configurable...
-    */
-   pMga->agp.size = pMga->agpSize * 1024 * 1024;
-
-   pMga->warp.offset = 0;
-   pMga->warp.size = MGA_WARP_UCODE_SIZE;
-
-   pMga->primary.offset = (pMga->warp.offset +
-				    pMga->warp.size);
-   pMga->primary.size = 1024 * 1024;
-
-   pMga->buffers.offset = (pMga->primary.offset +
-				    pMga->primary.size);
-   pMga->buffers.size = MGA_NUM_BUFFERS * MGA_BUFFER_SIZE;
-
-
-   pMga->agpTextures.offset = (pMga->buffers.offset +
-                                    pMga->buffers.size);
-
-   pMga->agpTextures.size = pMga->agp.size -
-                                     pMga->agpTextures.offset;
-
-   if ( drmAgpAcquire( ctx->drmFD ) < 0 ) {
-     fprintf( stderr, "[agp] AGP not available\n" );
-      return 0;
-   }
-
-   mode   = drmAgpGetMode( ctx->drmFD );        /* Default mode */
-   vendor = drmAgpVendorId( ctx->drmFD );
-   device = drmAgpDeviceId( ctx->drmFD );
-
-   mode &= ~MGA_AGP_MODE_MASK;
-   switch ( pMga->agpMode ) {
-   case 4:
-      mode |= MGA_AGP_4X_MODE;
-   case 2:
-      mode |= MGA_AGP_2X_MODE;
-   case 1:
-   default:
-      mode |= MGA_AGP_1X_MODE;
-   }
-
-#if 0
-   fprintf( stderr,
-            "[agp] Mode 0x%08lx [AGP 0x%04x/0x%04x; Card 0x%04x/0x%04x]\n",
-            mode, vendor, device,
-            ctx->pciVendor,
-            ctx->pciChipType );
-#endif
-
-   if ( drmAgpEnable( ctx->drmFD, mode ) < 0 ) {
-     fprintf( stderr, "[agp] AGP not enabled\n" );
-      drmAgpRelease( ctx->drmFD );
-      return 0;
-   }
-
-   if ( pMga->Chipset == PCI_CHIP_MGAG200 ) {
-      switch ( pMga->agpMode ) {
-      case 2:
-	 fprintf( stderr,
-		     "[drm] Enabling AGP 2x PLL encoding\n" );
-	 OUTREG( MGAREG_AGP_PLL, MGA_AGP2XPLL_ENABLE );
-	 break;
-
-      case 1:
-      default:
-	 fprintf( stderr,
-		     "[drm] Disabling AGP 2x PLL encoding\n" );
-	 OUTREG( MGAREG_AGP_PLL, MGA_AGP2XPLL_DISABLE );
-	 pMga->agpMode = 1;
-	 break;
-      }
-   }
-
-   ret = drmAgpAlloc( ctx->drmFD, pMga->agp.size,
-		      0, NULL, &pMga->agp.handle );
-   if ( ret < 0 ) {
-      fprintf( stderr, "[agp] Out of memory (%d)\n", ret );
-      drmAgpRelease( ctx->drmFD );
-      return 0;
-   }
-   fprintf( stderr,
-	       "[agp] %d kB allocated with handle 0x%08x\n",
-	       pMga->agp.size/1024, (unsigned int)pMga->agp.handle );
-
-   if ( drmAgpBind( ctx->drmFD, pMga->agp.handle, 0 ) < 0 ) {
-      fprintf( stderr, "[agp] Could not bind memory\n" );
-      drmAgpFree( ctx->drmFD, pMga->agp.handle );
-      drmAgpRelease( ctx->drmFD );
-      return 0;
-   }
-
-   /* WARP microcode space
-    */
-   if ( drmAddMap( ctx->drmFD,
-		   pMga->warp.offset,
-		   pMga->warp.size,
-		   DRM_AGP, DRM_READ_ONLY,
-		   &pMga->warp.handle ) < 0 ) {
-      fprintf( stderr,
-		  "[agp] Could not add WARP microcode mapping\n" );
-      return 0;
-   }
-   fprintf( stderr,
- 	       "[agp] WARP microcode handle = 0x%08x\n",
-	       pMga->warp.handle );
-
-   if ( drmMap( ctx->drmFD,
-		pMga->warp.handle,
-		pMga->warp.size,
-		&pMga->warp.map ) < 0 ) {
-      fprintf( stderr,
-		  "[agp] Could not map WARP microcode\n" );
-      return 0;
-   }
-   fprintf( stderr,
-	       "[agp] WARP microcode mapped at 0x%08lx\n",
-	       (unsigned long)pMga->warp.map );
-
-   /* Primary DMA space
-    */
-   if ( drmAddMap( ctx->drmFD,
-		   pMga->primary.offset,
-		   pMga->primary.size,
-		   DRM_AGP, DRM_READ_ONLY,
-		   &pMga->primary.handle ) < 0 ) {
-      fprintf( stderr,
-		  "[agp] Could not add primary DMA mapping\n" );
-      return 0;
-   }
-   fprintf( stderr,
- 	       "[agp] Primary DMA handle = 0x%08x\n",
-	       pMga->primary.handle );
-
-   if ( drmMap( ctx->drmFD,
-		pMga->primary.handle,
-		pMga->primary.size,
-		&pMga->primary.map ) < 0 ) {
-      fprintf( stderr,
-		  "[agp] Could not map primary DMA\n" );
-      return 0;
-   }
-   fprintf( stderr,
-	       "[agp] Primary DMA mapped at 0x%08lx\n",
-	       (unsigned long)pMga->primary.map );
-
-   /* DMA buffers
-    */
-   if ( drmAddMap( ctx->drmFD,
-		   pMga->buffers.offset,
-		   pMga->buffers.size,
-		   DRM_AGP, 0,
-		   &pMga->buffers.handle ) < 0 ) {
-      fprintf( stderr,
-		  "[agp] Could not add DMA buffers mapping\n" );
-      return 0;
-   }
-   fprintf( stderr,
- 	       "[agp] DMA buffers handle = 0x%08x\n",
-	       pMga->buffers.handle );
-
-   if ( drmMap( ctx->drmFD,
-		pMga->buffers.handle,
-		pMga->buffers.size,
-		&pMga->buffers.map ) < 0 ) {
-      fprintf( stderr,
-		  "[agp] Could not map DMA buffers\n" );
-      return 0;
-   }
-   fprintf( stderr,
-	       "[agp] DMA buffers mapped at 0x%08lx\n",
-	       (unsigned long)pMga->buffers.map );
-
-   count = drmAddBufs( ctx->drmFD,
-		       MGA_NUM_BUFFERS, MGA_BUFFER_SIZE,
-		       DRM_AGP_BUFFER, pMga->buffers.offset );
-   if ( count <= 0 ) {
-      fprintf( stderr,
-		  "[drm] failure adding %d %d byte DMA buffers\n",
-		  MGA_NUM_BUFFERS, MGA_BUFFER_SIZE );
-      return 0;
-   }
-   fprintf( stderr,
-	       "[drm] Added %d %d byte DMA buffers\n",
-	       count, MGA_BUFFER_SIZE );
-
-   i = mylog2(pMga->agpTextures.size / MGA_NR_TEX_REGIONS);
-   if(i < MGA_LOG_MIN_TEX_REGION_SIZE)
-      i = MGA_LOG_MIN_TEX_REGION_SIZE;
-   pMga->agpTextures.size = (pMga->agpTextures.size >> i) << i;
-
-   if ( drmAddMap( ctx->drmFD,
-                   pMga->agpTextures.offset,
-                   pMga->agpTextures.size,
-                   DRM_AGP, 0,
-                   &pMga->agpTextures.handle ) < 0 ) {
-      fprintf( stderr,
-                  "[agp] Could not add agpTexture mapping\n" );
-      return 0;
-   }
-/* should i map it ? */
-   fprintf( stderr,
-               "[agp] agpTexture handle = 0x%08x\n",
-               pMga->agpTextures.handle );
-   fprintf( stderr,
-               "[agp] agpTexture size: %d kb\n", pMga->agpTextures.size/1024 );
-
-   return 1;
-}
-
-static int MGADRIMapInit( struct DRIDriverContextRec *ctx, MGAPtr pMga )
-{
-   pMga->registers.size = MGAIOMAPSIZE;
-
-   if ( drmAddMap( ctx->drmFD,
-		   (drm_handle_t)pMga->IOAddress,
-		   pMga->registers.size,
-		   DRM_REGISTERS, DRM_READ_ONLY,
-		   &pMga->registers.handle ) < 0 ) {
-      fprintf( stderr,
-		  "[drm] Could not add MMIO registers mapping\n" );
-      return 0;
-   }
-   fprintf( stderr,
-	       "[drm] Registers handle = 0x%08lx\n",
-	       pMga->registers.handle );
-
-   pMga->status.size = SAREA_MAX;
-
-   if ( drmAddMap( ctx->drmFD, 0, pMga->status.size,
-		   DRM_SHM, DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL,
-		   &pMga->status.handle ) < 0 ) {
-      fprintf( stderr,
-		  "[drm] Could not add status page mapping\n" );
-      return 0;
-   }
-   fprintf( stderr,
- 	       "[drm] Status handle = 0x%08x\n",
-	       pMga->status.handle );
-
-   if ( drmMap( ctx->drmFD,
-		pMga->status.handle,
-		pMga->status.size,
-		&pMga->status.map ) < 0 ) {
-      fprintf( stderr,
-		  "[agp] Could not map status page\n" );
-      return 0;
-   }
-   fprintf( stderr,
-	       "[agp] Status page mapped at 0x%08lx\n",
-	       (unsigned long)pMga->status.map );
-
-   return 1;
-}
-
-static int MGADRIKernelInit( struct DRIDriverContextRec *ctx, MGAPtr pMga )
-{
-   drm_mga_init_t init;
-   int ret;
-
-   memset( &init, 0, sizeof(init) );
-
-   init.func = MGA_INIT_DMA;
-   init.sarea_priv_offset = sizeof(drm_sarea_t);
-
-   switch ( pMga->Chipset ) {
-   case PCI_CHIP_MGAG550:
-   case PCI_CHIP_MGAG400:
-      init.chipset = MGA_CARD_TYPE_G400;
-      break;
-   case PCI_CHIP_MGAG200:
-   case PCI_CHIP_MGAG200_PCI:
-      init.chipset = MGA_CARD_TYPE_G200;
-      break;
-   default:
-      return 0;
-   }
-
-   init.sgram = 0; /* FIXME !pMga->HasSDRAM; */
-
-
-   switch (ctx->bpp)
-     {
-     case 16:
-       init.maccess = MGA_MACCESS_PW16;
-       break;
-     case 32:
-       init.maccess = MGA_MACCESS_PW32;
-       break;
-     default:
-       fprintf( stderr, "[mga] invalid bpp (%d)\n", ctx->bpp );
-       return 0;
-     }
-
-
-   init.fb_cpp		= ctx->bpp / 8;
-   init.front_offset	= pMga->frontOffset;
-   init.front_pitch	= pMga->frontPitch / init.fb_cpp;
-   init.back_offset	= pMga->backOffset;
-   init.back_pitch	= pMga->backPitch / init.fb_cpp;
-
-   init.depth_cpp	= ctx->bpp / 8;
-   init.depth_offset	= pMga->depthOffset;
-   init.depth_pitch	= pMga->depthPitch / init.depth_cpp;
-
-   init.texture_offset[0] = pMga->textureOffset;
-   init.texture_size[0] = pMga->textureSize;
-
-   init.fb_offset = ctx->shared.hFrameBuffer;
-   init.mmio_offset = pMga->registers.handle;
-   init.status_offset = pMga->status.handle;
-
-   init.warp_offset = pMga->warp.handle;
-   init.primary_offset = pMga->primary.handle;
-   init.buffers_offset = pMga->buffers.handle;
-
-   init.texture_offset[1] = pMga->agpTextures.handle;
-   init.texture_size[1] = pMga->agpTextures.size;
-
-   ret = drmCommandWrite( ctx->drmFD, DRM_MGA_INIT, &init, sizeof(init));
-   if ( ret < 0 ) {
-      fprintf( stderr,
-		  "[drm] Failed to initialize DMA! (%d)\n", ret );
-      return 0;
-   }
-
-   return 1;
-}
-
-static void MGADRIIrqInit(struct DRIDriverContextRec *ctx, MGAPtr pMga)
-{
-  if (!pMga->irq)
-    {
-      pMga->irq = drmGetInterruptFromBusID(ctx->drmFD,
-                                           ctx->pciBus,
-                                           ctx->pciDevice,
-                                           ctx->pciFunc);
-
-      fprintf(stderr, "[drm] got IRQ %d\n", pMga->irq);
-
-    if((drmCtlInstHandler(ctx->drmFD, pMga->irq)) != 0)
-      {
-        fprintf(stderr,
-                "[drm] failure adding irq handler, "
-                "there is a device already using that irq\n"
-                "[drm] falling back to irq-free operation\n");
-        pMga->irq = 0;
-      }
-    else
-      {
-        pMga->reg_ien = INREG( MGAREG_IEN );
-      }
-    }
-
-  if (pMga->irq)
-    fprintf(stderr,
-            "[drm] dma control initialized, using IRQ %d\n",
-            pMga->irq);
-}
-
-static int MGADRIBuffersInit( struct DRIDriverContextRec *ctx, MGAPtr pMga )
-{
-   pMga->drmBuffers = drmMapBufs( ctx->drmFD );
-   if ( !pMga->drmBuffers )
-     {
-       fprintf( stderr,
-                "[drm] Failed to map DMA buffers list\n" );
-       return 0;
-     }
-   
-   fprintf( stderr,
-            "[drm] Mapped %d DMA buffers\n",
-            pMga->drmBuffers->count );
-
-   return 1;
-}
-
-static int MGAMemoryInit( struct DRIDriverContextRec *ctx, MGAPtr pMga )
-{
-   int        width_bytes = ctx->shared.virtualWidth * ctx->cpp;
-   int        bufferSize  = ((ctx->shared.virtualHeight * width_bytes
-			      + MGA_BUFFER_ALIGN)
-			     & ~MGA_BUFFER_ALIGN);
-   int        depthSize   = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes
-			      + MGA_BUFFER_ALIGN)
-			     & ~MGA_BUFFER_ALIGN);
-   int        l;
-
-   pMga->frontOffset = 0;
-   pMga->frontPitch = ctx->shared.virtualWidth * ctx->cpp;
-
-   fprintf(stderr, 
-	   "Using %d MB AGP aperture\n", pMga->agpSize);
-   fprintf(stderr, 
-	   "Using %d MB for vertex/indirect buffers\n", pMga->buffers.size>>20);
-   fprintf(stderr, 
-	   "Using %d MB for AGP textures\n", pMga->agpTextures.size>>20);
-
-   /* Front, back and depth buffers - everything else texture??
-    */
-   pMga->textureSize = ctx->shared.fbSize - 2 * bufferSize - depthSize;
-
-   if (pMga->textureSize < 0) 
-      return 0;
-
-   l = mylog2( pMga->textureSize / MGA_NR_TEX_REGIONS );
-   if ( l < MGA_LOG_MIN_TEX_REGION_SIZE )
-      l = MGA_LOG_MIN_TEX_REGION_SIZE;
-
-   /* Round the texture size up to the nearest whole number of
-    * texture regions.  Again, be greedy about this, don't
-    * round down.
-    */
-   pMga->logTextureGranularity = l;
-   pMga->textureSize = (pMga->textureSize >> l) << l;
-
-   /* Set a minimum usable local texture heap size.  This will fit
-    * two 256x256x32bpp textures.
-    */
-   if (pMga->textureSize < 512 * 1024) {
-      pMga->textureOffset = 0;
-      pMga->textureSize = 0;
-   }
-
-   /* Reserve space for textures */
-   pMga->textureOffset = ((ctx->shared.fbSize - pMga->textureSize +
-			   MGA_BUFFER_ALIGN) &
-			  ~MGA_BUFFER_ALIGN);
-
-   /* Reserve space for the shared depth
-    * buffer.
-    */
-   pMga->depthOffset = ((pMga->textureOffset - depthSize +
-			 MGA_BUFFER_ALIGN) &
-			~MGA_BUFFER_ALIGN);
-   pMga->depthPitch = ctx->shared.virtualWidth * ctx->cpp;
-
-   pMga->backOffset = ((pMga->depthOffset - bufferSize +
-			MGA_BUFFER_ALIGN) &
-                        ~MGA_BUFFER_ALIGN);
-   pMga->backPitch = ctx->shared.virtualWidth * ctx->cpp;
-
-
-   fprintf(stderr, 
-	   "Will use back buffer at offset 0x%x\n",
-	   pMga->backOffset);
-   fprintf(stderr, 
-	   "Will use depth buffer at offset 0x%x\n",
-	   pMga->depthOffset);
-   fprintf(stderr, 
-	   "Will use %d kb for textures at offset 0x%x\n",
-	   pMga->textureSize/1024, pMga->textureOffset);
-
-   return 1;
-} 
-
-static int MGACheckDRMVersion( struct DRIDriverContextRec *ctx, MGAPtr pMga )
-{
-  drmVersionPtr version;
-
-  /* Check the MGA DRM version */
-  version = drmGetVersion(ctx->drmFD);
-  if ( version ) {
-    if ( version->version_major != 3 ||
-         version->version_minor < 0 ) {
-            /* incompatible drm version */
-      fprintf( stderr,
-               "[dri] MGADRIScreenInit failed because of a version mismatch.\n"
-               "[dri] mga.o kernel module version is %d.%d.%d but version 3.0.x is needed.\n"
-               "[dri] Disabling DRI.\n",
-               version->version_major,
-               version->version_minor,
-               version->version_patchlevel );
-      drmFreeVersion( version );
-      return 0;
-    }
-    drmFreeVersion( version );
-  }
-
-  return 1;
-}
-
-static void print_client_msg( MGADRIPtr pMGADRI )
-{
-  fprintf( stderr, "chipset:                  %d\n", pMGADRI->chipset );
-
-  fprintf( stderr, "width:                    %d\n", pMGADRI->width );
-  fprintf( stderr, "height:                   %d\n", pMGADRI->height );
-  fprintf( stderr, "mem:                      %d\n", pMGADRI->mem );
-  fprintf( stderr, "cpp:                      %d\n", pMGADRI->cpp );
-
-  fprintf( stderr, "agpMode:                  %d\n", pMGADRI->agpMode );
-
-  fprintf( stderr, "frontOffset:              %d\n", pMGADRI->frontOffset );
-  fprintf( stderr, "frontPitch:               %d\n", pMGADRI->frontPitch );
-
-  fprintf( stderr, "backOffset:               %d\n", pMGADRI->backOffset );
-  fprintf( stderr, "backPitch:                %d\n", pMGADRI->backPitch );
-
-  fprintf( stderr, "depthOffset:              %d\n", pMGADRI->depthOffset );
-  fprintf( stderr, "depthPitch:               %d\n", pMGADRI->depthPitch );
-
-  fprintf( stderr, "textureOffset:            %d\n", pMGADRI->textureOffset );
-  fprintf( stderr, "textureSize:              %d\n", pMGADRI->textureSize );
-
-  fprintf( stderr, "logTextureGranularity:    %d\n", pMGADRI->logTextureGranularity );
-  fprintf( stderr, "logAgpTextureGranularity: %d\n", pMGADRI->logAgpTextureGranularity );
-
-  fprintf( stderr, "agpTextureHandle:         %u\n", (unsigned int)pMGADRI->agpTextureOffset );
-  fprintf( stderr, "agpTextureSize:           %u\n", (unsigned int)pMGADRI->agpTextureSize );
-
-#if 0
-   pMGADRI->registers.handle	= pMga->registers.handle;
-   pMGADRI->registers.size	= pMga->registers.size;
-   pMGADRI->status.handle	= pMga->status.handle;
-   pMGADRI->status.size		= pMga->status.size;
-   pMGADRI->primary.handle	= pMga->primary.handle;
-   pMGADRI->primary.size	= pMga->primary.size;
-   pMGADRI->buffers.handle	= pMga->buffers.handle;
-   pMGADRI->buffers.size	= pMga->buffers.size;
-   pMGADRI->sarea_priv_offset = sizeof(drm_sarea_t);
-#endif
-}
-
-static int MGAScreenInit( struct DRIDriverContextRec *ctx, MGAPtr pMga )
-{
-  int       i;
-  int       err;
-  MGADRIPtr pMGADRI;
-
-  usleep(100);
-  /*assert(!ctx->IsClient);*/
-
-   {
-      int  width_bytes = (ctx->shared.virtualWidth * ctx->cpp);
-      int  maxy        = ctx->shared.fbSize / width_bytes;
-
-
-      if (maxy <= ctx->shared.virtualHeight * 3) {
-	 fprintf(stderr, 
-		 "Static buffer allocation failed -- "
-		 "need at least %d kB video memory (have %d kB)\n",
-		 (ctx->shared.virtualWidth * ctx->shared.virtualHeight *
-		  ctx->cpp * 3 + 1023) / 1024,
-		 ctx->shared.fbSize / 1024);
-	 return 0;
-      } 
-   }
-
-   switch(pMga->Chipset) {
-   case PCI_CHIP_MGAG550:
-   case PCI_CHIP_MGAG400:
-   case PCI_CHIP_MGAG200:
-#if 0
-   case PCI_CHIP_MGAG200_PCI:
-#endif
-      break;
-   default:
-      fprintf(stderr, "[drm] Direct rendering only supported with G200/G400/G550 AGP\n");
-      return 0;
-   }
-
-   fprintf( stderr,
-	       "[drm] bpp: %d depth: %d\n",
-            ctx->bpp, ctx->bpp /* FIXME: depth */ );
-
-   if ( (ctx->bpp / 8) != 2 &&
-	(ctx->bpp / 8) != 4 ) {
-      fprintf( stderr,
-		  "[dri] Direct rendering only supported in 16 and 32 bpp modes\n" );
-      return 0;
-   }
-
-   ctx->shared.SAREASize = SAREA_MAX;
-
-
-   /* Note that drmOpen will try to load the kernel module, if needed. */
-   ctx->drmFD = drmOpen("mga", NULL );
-   if (ctx->drmFD < 0) {
-      fprintf(stderr, "[drm] drmOpen failed\n");
-      return 0;
-   }
-
-   if ((err = drmSetBusid(ctx->drmFD, ctx->pciBusID)) < 0) {
-      fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n",
-	      ctx->drmFD, ctx->pciBusID, strerror(-err));
-      return 0;
-   }
-
-     
-   if (drmAddMap( ctx->drmFD,
-		  0,
-		  ctx->shared.SAREASize,
-		  DRM_SHM,
-		  DRM_CONTAINS_LOCK,
-		  &ctx->shared.hSAREA) < 0)
-   {
-      fprintf(stderr, "[drm] drmAddMap failed\n");
-      return 0;
-   }
-   fprintf(stderr, "[drm] added %d byte SAREA at 0x%08lx\n",
-	   ctx->shared.SAREASize, ctx->shared.hSAREA);
-
-   if (drmMap( ctx->drmFD,
-	       ctx->shared.hSAREA,
-	       ctx->shared.SAREASize,
-	       (drmAddressPtr)(&ctx->pSAREA)) < 0)
-   {
-      fprintf(stderr, "[drm] drmMap failed\n");
-      return 0;
-   }
-   memset(ctx->pSAREA, 0, ctx->shared.SAREASize);
-   fprintf(stderr, "[drm] mapped SAREA 0x%08lx to %p, size %d\n",
-	   ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize);
-   
-   /* Need to AddMap the framebuffer and mmio regions here:
-    */
-   if (drmAddMap( ctx->drmFD,
-		  (drm_handle_t)ctx->FBStart,
-		  ctx->FBSize,
-		  DRM_FRAME_BUFFER,
-		  0,
-		  &ctx->shared.hFrameBuffer) < 0)
-   {
-      fprintf(stderr, "[drm] drmAddMap framebuffer failed\n");
-      return 0;
-   }
-   fprintf(stderr, "[drm] framebuffer handle = 0x%08lx\n",
-	   ctx->shared.hFrameBuffer);
-
-
-#if 0 /* will be done in MGADRIMapInit */
-   if (drmAddMap(ctx->drmFD, 
-		 ctx->FixedInfo.mmio_start,
-		 ctx->FixedInfo.mmio_len,
-		 DRM_REGISTERS, 
-		 DRM_READ_ONLY, 
-		 &pMga->registers.handle) < 0) {
-      fprintf(stderr, "[drm] drmAddMap mmio failed\n");	
-      return 0;
-   }
-   fprintf(stderr,
-	   "[drm] register handle = 0x%08lx\n", pMga->registers.handle);
-#endif
-
-
-   /* Check the mga DRM version */
-   if (!MGACheckDRMVersion(ctx, pMga)) {
-      return 0;
-   }
-
-   if ( !MGADRIAgpInit( ctx, pMga ) ) {
-      return 0;
-   }
-
-   if ( !MGADRIMapInit( ctx, pMga ) ) {
-      return 0;
-   }
-
-   /* Memory manager setup */
-   if (!MGAMemoryInit(ctx, pMga)) {
-      return 0;
-   }
-
-
-   /* Create a 'server' context so we can grab the lock for
-    * initialization ioctls.
-    */
-   if ((err = drmCreateContext(ctx->drmFD, &ctx->serverContext)) != 0) {
-      fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err);
-      return 0;
-   }
-
-   DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0); 
-
-   /* Initialize the kernel data structures */
-   if (!MGADRIKernelInit(ctx, pMga)) {
-      fprintf(stderr, "MGADRIKernelInit failed\n");
-      DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext);
-      return 0;
-   }
-
-   /* Initialize the vertex buffers list */
-   if (!MGADRIBuffersInit(ctx, pMga)) {
-      fprintf(stderr, "MGADRIBuffersInit failed\n");
-      DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext);
-      return 0;
-   }
-
-   /* Initialize IRQ */
-   MGADRIIrqInit(ctx, pMga);
-
-
-   /* Initialize the SAREA private data structure */
-   {
-      drm_mga_sarea_t *pSAREAPriv;
-      pSAREAPriv = (drm_mga_sarea_t *)(((char*)ctx->pSAREA) + 
-					sizeof(drm_sarea_t));
-      memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
-   }
-
-   /* Quick hack to clear the front & back buffers.  Could also use
-    * the clear ioctl to do this, but would need to setup hw state
-    * first.
-    */
-   drimemsetio((char *)ctx->FBAddress + pMga->frontOffset,
-	  0,
-	  pMga->frontPitch * ctx->shared.virtualHeight );
-
-   drimemsetio((char *)ctx->FBAddress + pMga->backOffset,
-	  0,
-	  pMga->backPitch * ctx->shared.virtualHeight );
-
-   /* Can release the lock now */
-/*   DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext);*/
-
-   /* This is the struct passed to radeon_dri.so for its initialization */
-   ctx->driverClientMsg = malloc(sizeof(MGADRIRec));
-   ctx->driverClientMsgSize = sizeof(MGADRIRec);
-
-   pMGADRI                    = (MGADRIPtr)ctx->driverClientMsg;
-
-
-   switch(pMga->Chipset) {
-   case PCI_CHIP_MGAG550:
-   case PCI_CHIP_MGAG400:
-      pMGADRI->chipset = MGA_CARD_TYPE_G400;
-      break;
-   case PCI_CHIP_MGAG200:
-   case PCI_CHIP_MGAG200_PCI:
-      pMGADRI->chipset = MGA_CARD_TYPE_G200;
-      break;
-   default:
-      return 0;
-   }
-   pMGADRI->width		= ctx->shared.virtualWidth;
-   pMGADRI->height		= ctx->shared.virtualHeight;
-   pMGADRI->mem			= ctx->shared.fbSize;
-   pMGADRI->cpp			= ctx->bpp / 8;
-
-   pMGADRI->agpMode		= pMga->agpMode;
-
-   pMGADRI->frontOffset		= pMga->frontOffset;
-   pMGADRI->frontPitch		= pMga->frontPitch;
-   pMGADRI->backOffset		= pMga->backOffset;
-   pMGADRI->backPitch		= pMga->backPitch;
-   pMGADRI->depthOffset		= pMga->depthOffset;
-   pMGADRI->depthPitch		= pMga->depthPitch;
-   pMGADRI->textureOffset	= pMga->textureOffset;
-   pMGADRI->textureSize		= pMga->textureSize;
-   pMGADRI->logTextureGranularity = pMga->logTextureGranularity;
-
-   i = mylog2( pMga->agpTextures.size / MGA_NR_TEX_REGIONS );
-   if ( i < MGA_LOG_MIN_TEX_REGION_SIZE )
-      i = MGA_LOG_MIN_TEX_REGION_SIZE;
-
-   pMGADRI->logAgpTextureGranularity = i;
-   pMGADRI->agpTextureOffset = (unsigned int)pMga->agpTextures.handle;
-   pMGADRI->agpTextureSize = (unsigned int)pMga->agpTextures.size;
-
-   pMGADRI->registers.handle	= pMga->registers.handle;
-   pMGADRI->registers.size	= pMga->registers.size;
-   pMGADRI->status.handle	= pMga->status.handle;
-   pMGADRI->status.size		= pMga->status.size;
-   pMGADRI->primary.handle	= pMga->primary.handle;
-   pMGADRI->primary.size	= pMga->primary.size;
-   pMGADRI->buffers.handle	= pMga->buffers.handle;
-   pMGADRI->buffers.size	= pMga->buffers.size;
-   pMGADRI->sarea_priv_offset = sizeof(drm_sarea_t);
-
-   print_client_msg( pMGADRI );
-
-   return 1;
-}
-
-
-/**
- * \brief Validate the fbdev mode.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Saves some registers and returns 1.
- *
- * \sa mgaValidateMode().
- */
-static int mgaValidateMode( const DRIDriverContext *ctx )
-{
-   return 1;
-}
-
-
-/**
- * \brief Examine mode returned by fbdev.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Restores registers that fbdev has clobbered and returns 1.
- *
- * \sa mgaValidateMode().
- */
-static int mgaPostValidateMode( const DRIDriverContext *ctx )
-{
-   return 1;
-}
-
-
-/**
- * \brief Initialize the framebuffer device mode
- *
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Fills in \p info with some default values and some information from \p ctx
- * and then calls MGAScreenInit() for the screen initialization.
- * 
- * Before exiting clears the framebuffer memomry accessing it directly.
- */
-static int mgaInitFBDev( struct DRIDriverContextRec *ctx )
-{
-   MGAPtr pMga = calloc(1, sizeof(*pMga));
-
-   {
-      int  dummy = ctx->shared.virtualWidth;
-
-      switch (ctx->bpp / 8) {
-      case 1: dummy = (ctx->shared.virtualWidth + 127) & ~127; break;
-      case 2: dummy = (ctx->shared.virtualWidth +  31) &  ~31; break;
-      case 3:
-      case 4: dummy = (ctx->shared.virtualWidth +  15) &  ~15; break;
-      }
-
-      ctx->shared.virtualWidth = dummy;
-   }
-
-   ctx->driverPrivate = (void *)pMga;
-   
-   pMga->agpMode       = MGA_DEFAULT_AGP_MODE;
-   pMga->agpSize       = MGA_DEFAULT_AGP_SIZE;
-  
-   pMga->Chipset = ctx->chipset;
-
-   pMga->IOAddress = ctx->MMIOStart;
-   pMga->IOBase    = ctx->MMIOAddress;
-
-   pMga->frontPitch = ctx->shared.virtualWidth * ctx->cpp;
-
-   if (!MGAScreenInit( ctx, pMga ))
-      return 0;
-
-   return 1;
-}
-
-
-/**
- * \brief The screen is being closed, so clean up any state and free any
- * resources used by the DRI.
- *
- * \param ctx display handle.
- *
- * Unmaps the SAREA, closes the DRM device file descriptor and frees the driver
- * private data.
- */
-static void mgaHaltFBDev( struct DRIDriverContextRec *ctx )
-{
-    drmUnmap( ctx->pSAREA, ctx->shared.SAREASize );
-    drmClose(ctx->drmFD);
-
-    if (ctx->driverPrivate) {
-       free(ctx->driverPrivate);
-       ctx->driverPrivate = NULL;
-    }
-}
-
-
-static int mgaEngineShutdown( const DRIDriverContext *ctx )
-{
-   fprintf(stderr, "%s() is not yet implemented!\n", __FUNCTION__);
-
-   return 1;
-}
-
-static int mgaEngineRestore( const DRIDriverContext *ctx )
-{
-   fprintf(stderr, "%s() is not yet implemented!\n", __FUNCTION__);
-
-   return 1;
-}
-
-/**
- * \brief Exported driver interface for Mini GLX.
- *
- * \sa DRIDriverRec.
- */
-struct DRIDriverRec __driDriver = {
-   mgaValidateMode,
-   mgaPostValidateMode,
-   mgaInitFBDev,
-   mgaHaltFBDev,
-   mgaEngineShutdown,
-   mgaEngineRestore,
-   0
-};
-
-
-
-
-#if 0
-void MGADRICloseScreen( ScreenPtr pScreen )
-{
-   ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
-   MGAPtr pMga = MGAPTR(pScrn);
-   MGADRIServerPrivatePtr pMga = pMga->DRIServerInfo;
-   drmMGAInit init;
-
-   if ( pMga->drmBuffers ) {
-      drmUnmapBufs( pMga->drmBuffers );
-      pMga->drmBuffers = NULL;
-   }
-
-   if (pMga->irq) {
-      drmCtlUninstHandler(ctx->drmFD);
-      pMga->irq = 0;
-   }
-
-   /* Cleanup DMA */
-   memset( &init, 0, sizeof(drmMGAInit) );
-   init.func = MGA_CLEANUP_DMA;
-   drmCommandWrite( ctx->drmFD, DRM_MGA_INIT, &init, sizeof(drmMGAInit) );
-
-   if ( pMga->status.map ) {
-      drmUnmap( pMga->status.map, pMga->status.size );
-      pMga->status.map = NULL;
-   }
-   if ( pMga->buffers.map ) {
-      drmUnmap( pMga->buffers.map, pMga->buffers.size );
-      pMga->buffers.map = NULL;
-   }
-   if ( pMga->primary.map ) {
-      drmUnmap( pMga->primary.map, pMga->primary.size );
-      pMga->primary.map = NULL;
-   }
-   if ( pMga->warp.map ) {
-      drmUnmap( pMga->warp.map, pMga->warp.size );
-      pMga->warp.map = NULL;
-   }
-
-   if ( pMga->agpTextures.map ) {
-      drmUnmap( pMga->agpTextures.map, pMga->agpTextures.size );
-      pMga->agpTextures.map = NULL;
-   }
-
-   if ( pMga->agp.handle ) {
-      drmAgpUnbind( ctx->drmFD, pMga->agp.handle );
-      drmAgpFree( ctx->drmFD, pMga->agp.handle );
-      pMga->agp.handle = 0;
-      drmAgpRelease( ctx->drmFD );
-   }
-
-   DRICloseScreen( pScreen );
-
-   if ( pMga->pDRIInfo ) {
-      if ( pMga->pDRIpMga->devPrivate ) {
-	 xfree( pMga->pDRIpMga->devPrivate );
-	 pMga->pDRIpMga->devPrivate = 0;
-      }
-      DRIDestroyInfoRec( pMga->pDRIInfo );
-      pMga->pDRIInfo = 0;
-   }
-   if ( pMga->DRIServerInfo ) {
-      xfree( pMga->DRIServerInfo );
-      pMga->DRIServerInfo = 0;
-   }
-   if ( pMga->pVisualConfigs ) {
-      xfree( pMga->pVisualConfigs );
-   }
-   if ( pMga->pVisualConfigsPriv ) {
-      xfree( pMga->pVisualConfigsPriv );
-   }
-}
-#endif
diff --git a/src/mesa/drivers/dri/r128/server/r128_dri.c b/src/mesa/drivers/dri/r128/server/r128_dri.c
deleted file mode 100644
index 6e3db948af..0000000000
--- a/src/mesa/drivers/dri/r128/server/r128_dri.c
+++ /dev/null
@@ -1,1112 +0,0 @@
-/*
- * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
- *                      Precision Insight, Inc., Cedar Park, Texas, and
- *                      VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX
- * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- *   Kevin E. Martin <martin@valinux.com>
- *   Rickard E. Faith <faith@valinux.com>
- *   Daryll Strauss <daryll@valinux.com>
- *   Gareth Hughes <gareth@valinux.com>
- *
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <errno.h>
-#include <unistd.h>
-// Fix this to use kernel pci_ids.h when all of these IDs make it into the kernel 
-#include "pci_ids.h"
-
-#include "driver.h"
-#include "drm.h"
-#include "memops.h"
-
-#include "r128.h"
-#include "r128_dri.h"
-#include "r128_macros.h"
-#include "r128_reg.h"
-#include "r128_version.h"
-#include "r128_drm.h"
-
-static size_t r128_drm_page_size;
-
-/* Compute log base 2 of val. */
-static int R128MinBits(int val)
-{
-    int bits;
-
-    if (!val) return 1;
-    for (bits = 0; val; val >>= 1, ++bits);
-    return bits;
-}
-
-/* Initialize the AGP state.  Request memory for use in AGP space, and
-   initialize the Rage 128 registers to point to that memory. */
-static GLboolean R128DRIAgpInit(const DRIDriverContext *ctx)
-{
-    unsigned char *R128MMIO = ctx->MMIOAddress;
-    R128InfoPtr info = ctx->driverPrivate;
-    unsigned long mode;
-    unsigned int  vendor, device;
-    int           ret;
-    unsigned long cntl, chunk;
-    int           s, l;
-    int           flags;
-    unsigned long agpBase;
-
-    if (drmAgpAcquire(ctx->drmFD) < 0) {
-	fprintf(stderr, "[agp] AGP not available\n");
-	return GL_FALSE;
-    }
-
-				/* Modify the mode if the default mode is
-				   not appropriate for this particular
-				   combination of graphics card and AGP
-				   chipset. */
-
-    mode   = drmAgpGetMode(ctx->drmFD);        /* Default mode */
-    vendor = drmAgpVendorId(ctx->drmFD);
-    device = drmAgpDeviceId(ctx->drmFD);
-
-    mode &= ~R128_AGP_MODE_MASK;
-    switch (info->agpMode) {
-    case 4:          mode |= R128_AGP_4X_MODE;
-    case 2:          mode |= R128_AGP_2X_MODE;
-    case 1: default: mode |= R128_AGP_1X_MODE;
-    }
-
-    fprintf(stderr,
-	       "[agp] Mode 0x%08lx [AGP 0x%04x/0x%04x; Card 0x%04x/0x%04x]\n",
-	       mode, vendor, device,
-	       0x1002,
-	       info->Chipset);
-
-    if (drmAgpEnable(ctx->drmFD, mode) < 0) {
-	fprintf(stderr, "[agp] AGP not enabled\n");
-	drmAgpRelease(ctx->drmFD);
-	return GL_FALSE;
-    }
-
-    info->agpOffset = 0;
-
-    if ((ret = drmAgpAlloc(ctx->drmFD, info->agpSize*1024*1024, 0, NULL,
-			   &info->agpMemHandle)) < 0) {
-	fprintf(stderr, "[agp] Out of memory (%d)\n", ret);
-	drmAgpRelease(ctx->drmFD);
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[agp] %d kB allocated with handle 0x%08x\n",
-	       info->agpSize*1024, info->agpMemHandle);
-
-    if (drmAgpBind(ctx->drmFD, info->agpMemHandle, info->agpOffset) < 0) {
-	fprintf(stderr, "[agp] Could not bind\n");
-	drmAgpFree(ctx->drmFD, info->agpMemHandle);
-	drmAgpRelease(ctx->drmFD);
-	return GL_FALSE;
-    }
-
-				/* Initialize the CCE ring buffer data */
-    info->ringStart       = info->agpOffset;
-    info->ringMapSize     = info->ringSize*1024*1024 + r128_drm_page_size;
-    info->ringSizeLog2QW  = R128MinBits(info->ringSize*1024*1024/8) - 1;
-
-    info->ringReadOffset  = info->ringStart + info->ringMapSize;
-    info->ringReadMapSize = r128_drm_page_size;
-
-				/* Reserve space for vertex/indirect buffers */
-    info->bufStart        = info->ringReadOffset + info->ringReadMapSize;
-    info->bufMapSize      = info->bufSize*1024*1024;
-
-				/* Reserve the rest for AGP textures */
-    info->agpTexStart     = info->bufStart + info->bufMapSize;
-    s = (info->agpSize*1024*1024 - info->agpTexStart);
-    l = R128MinBits((s-1) / R128_NR_TEX_REGIONS);
-    if (l < R128_LOG_TEX_GRANULARITY) l = R128_LOG_TEX_GRANULARITY;
-    info->agpTexMapSize   = (s >> l) << l;
-    info->log2AGPTexGran  = l;
-
-    if (info->CCESecure) flags = DRM_READ_ONLY;
-    else                  flags = 0;
-
-    if (drmAddMap(ctx->drmFD, info->ringStart, info->ringMapSize,
-		  DRM_AGP, flags, &info->ringHandle) < 0) {
-	fprintf(stderr,
-		   "[agp] Could not add ring mapping\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[agp] ring handle = 0x%08x\n", info->ringHandle);
-
-    if (drmMap(ctx->drmFD, info->ringHandle, info->ringMapSize,
-	       (drmAddressPtr)&info->ring) < 0) {
-	fprintf(stderr, "[agp] Could not map ring\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[agp] Ring mapped at 0x%08lx\n",
-	       (unsigned long)info->ring);
-
-    if (drmAddMap(ctx->drmFD, info->ringReadOffset, info->ringReadMapSize,
-		  DRM_AGP, flags, &info->ringReadPtrHandle) < 0) {
-	fprintf(stderr,
-		   "[agp] Could not add ring read ptr mapping\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
- 	       "[agp] ring read ptr handle = 0x%08x\n",
-	       info->ringReadPtrHandle);
-
-    if (drmMap(ctx->drmFD, info->ringReadPtrHandle, info->ringReadMapSize,
-	       (drmAddressPtr)&info->ringReadPtr) < 0) {
-	fprintf(stderr,
-		   "[agp] Could not map ring read ptr\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[agp] Ring read ptr mapped at 0x%08lx\n",
-	       (unsigned long)info->ringReadPtr);
-
-    if (drmAddMap(ctx->drmFD, info->bufStart, info->bufMapSize,
-		  DRM_AGP, 0, &info->bufHandle) < 0) {
-	fprintf(stderr,
-		   "[agp] Could not add vertex/indirect buffers mapping\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[agp] vertex/indirect buffers handle = 0x%08lx\n",
-	       info->bufHandle);
-
-    if (drmMap(ctx->drmFD, info->bufHandle, info->bufMapSize,
-	       (drmAddressPtr)&info->buf) < 0) {
-	fprintf(stderr,
-		   "[agp] Could not map vertex/indirect buffers\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[agp] Vertex/indirect buffers mapped at 0x%08lx\n",
-	       (unsigned long)info->buf);
-
-    if (drmAddMap(ctx->drmFD, info->agpTexStart, info->agpTexMapSize,
-		  DRM_AGP, 0, &info->agpTexHandle) < 0) {
-	fprintf(stderr,
-		   "[agp] Could not add AGP texture map mapping\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[agp] AGP texture map handle = 0x%08lx\n",
-	       info->agpTexHandle);
-
-    if (drmMap(ctx->drmFD, info->agpTexHandle, info->agpTexMapSize,
-	       (drmAddressPtr)&info->agpTex) < 0) {
-	fprintf(stderr,
-		   "[agp] Could not map AGP texture map\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[agp] AGP Texture map mapped at 0x%08lx\n",
-	       (unsigned long)info->agpTex);
-
-				/* Initialize Rage 128's AGP registers */
-    cntl  = INREG(R128_AGP_CNTL);
-    cntl &= ~R128_AGP_APER_SIZE_MASK;
-    switch (info->agpSize) {
-    case 256: cntl |= R128_AGP_APER_SIZE_256MB; break;
-    case 128: cntl |= R128_AGP_APER_SIZE_128MB; break;
-    case  64: cntl |= R128_AGP_APER_SIZE_64MB;  break;
-    case  32: cntl |= R128_AGP_APER_SIZE_32MB;  break;
-    case  16: cntl |= R128_AGP_APER_SIZE_16MB;  break;
-    case   8: cntl |= R128_AGP_APER_SIZE_8MB;   break;
-    case   4: cntl |= R128_AGP_APER_SIZE_4MB;   break;
-    default:
-	fprintf(stderr,
-		   "[agp] Illegal aperture size %d kB\n",
-		   info->agpSize*1024);
-	return GL_FALSE;
-    }
-    agpBase = drmAgpBase(ctx->drmFD);
-    OUTREG(R128_AGP_BASE, agpBase); 
-    OUTREG(R128_AGP_CNTL, cntl);
-
-				/* Disable Rage 128's PCIGART registers */
-    chunk = INREG(R128_BM_CHUNK_0_VAL);
-    chunk &= ~(R128_BM_PTR_FORCE_TO_PCI |
-	       R128_BM_PM4_RD_FORCE_TO_PCI |
-	       R128_BM_GLOBAL_FORCE_TO_PCI);
-    OUTREG(R128_BM_CHUNK_0_VAL, chunk);
-
-    OUTREG(R128_PCI_GART_PAGE, 1); /* Ensure AGP GART is used (for now) */
-
-    return GL_TRUE;
-}
-
-static GLboolean R128DRIPciInit(const DRIDriverContext *ctx)
-{
-    R128InfoPtr info = ctx->driverPrivate;
-    unsigned char *R128MMIO = ctx->MMIOAddress;
-    uint32_t chunk;
-    int ret;
-    int flags;
-
-    info->agpOffset = 0;
-
-    ret = drmScatterGatherAlloc(ctx->drmFD, info->agpSize*1024*1024,
-				&info->pciMemHandle);
-    if (ret < 0) {
-	fprintf(stderr, "[pci] Out of memory (%d)\n", ret);
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[pci] %d kB allocated with handle 0x%08x\n",
-	       info->agpSize*1024, info->pciMemHandle);
-
-				/* Initialize the CCE ring buffer data */
-    info->ringStart       = info->agpOffset;
-    info->ringMapSize     = info->ringSize*1024*1024 + r128_drm_page_size;
-    info->ringSizeLog2QW  = R128MinBits(info->ringSize*1024*1024/8) - 1;
-
-    info->ringReadOffset  = info->ringStart + info->ringMapSize;
-    info->ringReadMapSize = r128_drm_page_size;
-
-				/* Reserve space for vertex/indirect buffers */
-    info->bufStart        = info->ringReadOffset + info->ringReadMapSize;
-    info->bufMapSize      = info->bufSize*1024*1024;
-
-    flags = DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL;
-
-    if (drmAddMap(ctx->drmFD, info->ringStart, info->ringMapSize,
-		  DRM_SCATTER_GATHER, flags, &info->ringHandle) < 0) {
-	fprintf(stderr,
-		   "[pci] Could not add ring mapping\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[pci] ring handle = 0x%08lx\n", info->ringHandle);
-
-    if (drmMap(ctx->drmFD, info->ringHandle, info->ringMapSize,
-	       (drmAddressPtr)&info->ring) < 0) {
-	fprintf(stderr, "[pci] Could not map ring\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[pci] Ring mapped at 0x%08lx\n",
-	       (unsigned long)info->ring);
-    fprintf(stderr,
-	       "[pci] Ring contents 0x%08lx\n",
-	       *(unsigned long *)info->ring);
-
-    if (drmAddMap(ctx->drmFD, info->ringReadOffset, info->ringReadMapSize,
-		  DRM_SCATTER_GATHER, flags, &info->ringReadPtrHandle) < 0) {
-	fprintf(stderr,
-		   "[pci] Could not add ring read ptr mapping\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[pci] ring read ptr handle = 0x%08lx\n",
-	       info->ringReadPtrHandle);
-
-    if (drmMap(ctx->drmFD, info->ringReadPtrHandle, info->ringReadMapSize,
-	       (drmAddressPtr)&info->ringReadPtr) < 0) {
-	fprintf(stderr,
-		   "[pci] Could not map ring read ptr\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[pci] Ring read ptr mapped at 0x%08lx\n",
-	       (unsigned long)info->ringReadPtr);
-    fprintf(stderr,
-	       "[pci] Ring read ptr contents 0x%08lx\n",
-	       *(unsigned long *)info->ringReadPtr);
-
-    if (drmAddMap(ctx->drmFD, info->bufStart, info->bufMapSize,
-		  DRM_SCATTER_GATHER, 0, &info->bufHandle) < 0) {
-	fprintf(stderr,
-		   "[pci] Could not add vertex/indirect buffers mapping\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[pci] vertex/indirect buffers handle = 0x%08lx\n",
-	       info->bufHandle);
-
-    if (drmMap(ctx->drmFD, info->bufHandle, info->bufMapSize,
-	       (drmAddressPtr)&info->buf) < 0) {
-	fprintf(stderr,
-		   "[pci] Could not map vertex/indirect buffers\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[pci] Vertex/indirect buffers mapped at 0x%08lx\n",
-	       (unsigned long)info->buf);
-    fprintf(stderr,
-	       "[pci] Vertex/indirect buffers contents 0x%08lx\n",
-	       *(unsigned long *)info->buf);
-
-    if (!info->IsPCI) {
-	/* This is really an AGP card, force PCI GART mode */
-        chunk = INREG(R128_BM_CHUNK_0_VAL);
-        chunk |= (R128_BM_PTR_FORCE_TO_PCI |
-		  R128_BM_PM4_RD_FORCE_TO_PCI |
-		  R128_BM_GLOBAL_FORCE_TO_PCI);
-        OUTREG(R128_BM_CHUNK_0_VAL, chunk);
-        OUTREG(R128_PCI_GART_PAGE, 0); /* Ensure PCI GART is used */
-    }
-
-    return GL_TRUE;
-}
-
-/* Add a map for the MMIO registers that will be accessed by any
-   DRI-based clients. */
-static GLboolean R128DRIMapInit(const DRIDriverContext *ctx)
-{
-    R128InfoPtr info = ctx->driverPrivate;
-    int flags;
-
-    if (info->CCESecure) flags = DRM_READ_ONLY;
-    else                 flags = 0;
-
-				/* Map registers */
-    if (drmAddMap(ctx->drmFD, ctx->MMIOStart, ctx->MMIOSize,
-		  DRM_REGISTERS, flags, &info->registerHandle) < 0) {
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[drm] register handle = 0x%08x\n", info->registerHandle);
-
-    return GL_TRUE;
-}
-
-/* Initialize the kernel data structures. */
-static int R128DRIKernelInit(const DRIDriverContext *ctx)
-{
-    R128InfoPtr info = ctx->driverPrivate;
-    drm_r128_init_t drmInfo;
-
-    memset( &drmInfo, 0, sizeof(&drmInfo) );
-
-    drmInfo.func                = R128_INIT_CCE;
-    drmInfo.sarea_priv_offset   = sizeof(drm_sarea_t);
-    drmInfo.is_pci              = info->IsPCI;
-    drmInfo.cce_mode            = info->CCEMode;
-    drmInfo.cce_secure          = info->CCESecure;
-    drmInfo.ring_size           = info->ringSize*1024*1024;
-    drmInfo.usec_timeout        = info->CCEusecTimeout;
-
-    drmInfo.fb_bpp              = ctx->bpp;
-    drmInfo.depth_bpp           = ctx->bpp;
-
-    drmInfo.front_offset        = info->frontOffset;
-    drmInfo.front_pitch         = info->frontPitch;
-
-    drmInfo.back_offset         = info->backOffset;
-    drmInfo.back_pitch          = info->backPitch;
-
-    drmInfo.depth_offset        = info->depthOffset;
-    drmInfo.depth_pitch         = info->depthPitch;
-    drmInfo.span_offset         = info->spanOffset;
-
-    drmInfo.fb_offset           = info->LinearAddr;
-    drmInfo.mmio_offset         = info->registerHandle;
-    drmInfo.ring_offset         = info->ringHandle;
-    drmInfo.ring_rptr_offset    = info->ringReadPtrHandle;
-    drmInfo.buffers_offset      = info->bufHandle;
-    drmInfo.agp_textures_offset = info->agpTexHandle;
-
-    if (drmCommandWrite(ctx->drmFD, DRM_R128_INIT,
-                        &drmInfo, sizeof(drmInfo)) < 0)
-        return GL_FALSE;
-
-    return GL_TRUE;
-}
-
-/* Add a map for the vertex buffers that will be accessed by any
-   DRI-based clients. */
-static GLboolean R128DRIBufInit(const DRIDriverContext *ctx)
-{
-    R128InfoPtr info = ctx->driverPrivate;
-				/* Initialize vertex buffers */
-    if (info->IsPCI) {
-	info->bufNumBufs = drmAddBufs(ctx->drmFD,
-				      info->bufMapSize / R128_BUFFER_SIZE,
-				      R128_BUFFER_SIZE,
-				      DRM_SG_BUFFER,
-				      info->bufStart);
-    } else {
-	info->bufNumBufs = drmAddBufs(ctx->drmFD,
-				      info->bufMapSize / R128_BUFFER_SIZE,
-				      R128_BUFFER_SIZE,
-				      DRM_AGP_BUFFER,
-				      info->bufStart);
-    }
-    if (info->bufNumBufs <= 0) {
-	fprintf(stderr,
-		   "[drm] Could not create vertex/indirect buffers list\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[drm] Added %d %d byte vertex/indirect buffers\n",
-	       info->bufNumBufs, R128_BUFFER_SIZE);
-
-    if (!(info->buffers = drmMapBufs(ctx->drmFD))) {
-	fprintf(stderr,
-		   "[drm] Failed to map vertex/indirect buffers list\n");
-	return GL_FALSE;
-    }
-    fprintf(stderr,
-	       "[drm] Mapped %d vertex/indirect buffers\n",
-	       info->buffers->count);
-
-    return GL_TRUE;
-}
-
-static void R128DRIIrqInit(const DRIDriverContext *ctx)
-{
-   R128InfoPtr info = ctx->driverPrivate;
-   unsigned char *R128MMIO = ctx->MMIOAddress;
-   
-   if (!info->irq) {
-       info->irq = drmGetInterruptFromBusID(
-	   ctx->drmFD,
-	   ctx->pciBus,
-	   ctx->pciDevice,
-	   ctx->pciFunc);
-
-      if((drmCtlInstHandler(ctx->drmFD, info->irq)) != 0) {
-	 fprintf(stderr,
-		    "[drm] failure adding irq handler, "
-		    "there is a device already using that irq\n"
-		    "[drm] falling back to irq-free operation\n");
-	 info->irq = 0;
-      } else {
-          info->gen_int_cntl = INREG( R128_GEN_INT_CNTL );
-      }
-   }
-
-   if (info->irq)
-      fprintf(stderr,
-		 "[drm] dma control initialized, using IRQ %d\n",
-		 info->irq);
-}
-
-static int R128CCEStop(const DRIDriverContext *ctx)
-{
-    R128InfoPtr info = ctx->driverPrivate;
-    drm_r128_cce_stop_t stop;
-    int            ret, i;
-
-    stop.flush = 1;
-    stop.idle  = 1;
-
-    ret = drmCommandWrite( ctx->drmFD, DRM_R128_CCE_STOP,
-                           &stop, sizeof(stop) );
-
-    if ( ret == 0 ) {
-        return 0;
-    } else if ( errno != EBUSY ) {
-        return -errno;
-    }
-
-    stop.flush = 0;
-
-    i = 0;
-    do {
-        ret = drmCommandWrite( ctx->drmFD, DRM_R128_CCE_STOP,
-                               &stop, sizeof(stop) );
-    } while ( ret && errno == EBUSY && i++ < R128_IDLE_RETRY );
-
-    if ( ret == 0 ) {
-        return 0;
-    } else if ( errno != EBUSY ) {
-        return -errno;
-    }
-
-    stop.idle = 0;
-
-    if ( drmCommandWrite( ctx->drmFD, DRM_R128_CCE_STOP,
-                          &stop, sizeof(stop) )) {
-        return -errno;
-    } else {
-        return 0;
-    }
-}
-
-/* Initialize the CCE state, and start the CCE (if used by the X server) */
-static void R128DRICCEInit(const DRIDriverContext *ctx)
-{
-   R128InfoPtr info = ctx->driverPrivate;
-
-				/* Turn on bus mastering */
-    info->BusCntl &= ~R128_BUS_MASTER_DIS;
-
-				/* CCEMode is initialized in r128_driver.c */
-    switch (info->CCEMode) {
-    case R128_PM4_NONPM4:                 info->CCEFifoSize = 0;   break;
-    case R128_PM4_192PIO:                 info->CCEFifoSize = 192; break;
-    case R128_PM4_192BM:                  info->CCEFifoSize = 192; break;
-    case R128_PM4_128PIO_64INDBM:         info->CCEFifoSize = 128; break;
-    case R128_PM4_128BM_64INDBM:          info->CCEFifoSize = 128; break;
-    case R128_PM4_64PIO_128INDBM:         info->CCEFifoSize = 64;  break;
-    case R128_PM4_64BM_128INDBM:          info->CCEFifoSize = 64;  break;
-    case R128_PM4_64PIO_64VCBM_64INDBM:   info->CCEFifoSize = 64;  break;
-    case R128_PM4_64BM_64VCBM_64INDBM:    info->CCEFifoSize = 64;  break;
-    case R128_PM4_64PIO_64VCPIO_64INDPIO: info->CCEFifoSize = 64;  break;
-    }
-
-    /* Make sure the CCE is on for the X server */
-    R128CCE_START(ctx, info);
-}
-
-
-static int R128MemoryInit(const DRIDriverContext *ctx)
-{
-   R128InfoPtr info = ctx->driverPrivate;
-   int        width_bytes = ctx->shared.virtualWidth * ctx->cpp;
-   int        cpp         = ctx->cpp;
-   int        bufferSize  = ((ctx->shared.virtualHeight * width_bytes
-			      + R128_BUFFER_ALIGN)
-			     & ~R128_BUFFER_ALIGN);
-   int        depthSize   = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes
-			      + R128_BUFFER_ALIGN)
-			     & ~R128_BUFFER_ALIGN);
-   int        l;
-
-   info->frontOffset = 0;
-   info->frontPitch = ctx->shared.virtualWidth;
-
-   fprintf(stderr, 
-	   "Using %d MB AGP aperture\n", info->agpSize);
-   fprintf(stderr, 
-	   "Using %d MB for the ring buffer\n", info->ringSize);
-   fprintf(stderr, 
-	   "Using %d MB for vertex/indirect buffers\n", info->bufSize);
-   fprintf(stderr, 
-	   "Using %d MB for AGP textures\n", info->agpTexSize);
-
-   /* Front, back and depth buffers - everything else texture??
-    */
-   info->textureSize = ctx->shared.fbSize - 2 * bufferSize - depthSize;
-
-   if (info->textureSize < 0) 
-      return 0;
-
-   l = R128MinBits((info->textureSize-1) / R128_NR_TEX_REGIONS);
-   if (l < R128_LOG_TEX_GRANULARITY) l = R128_LOG_TEX_GRANULARITY;
-
-   /* Round the texture size up to the nearest whole number of
-    * texture regions.  Again, be greedy about this, don't
-    * round down.
-    */
-   info->log2TexGran = l;
-   info->textureSize = (info->textureSize >> l) << l;
-
-   /* Set a minimum usable local texture heap size.  This will fit
-    * two 256x256x32bpp textures.
-    */
-   if (info->textureSize < 512 * 1024) {
-      info->textureOffset = 0;
-      info->textureSize = 0;
-   }
-
-   /* Reserve space for textures */
-   info->textureOffset = ((ctx->shared.fbSize - info->textureSize +
-			   R128_BUFFER_ALIGN) &
-			  ~R128_BUFFER_ALIGN);
-
-   /* Reserve space for the shared depth
-    * buffer.
-    */
-   info->depthOffset = ((info->textureOffset - depthSize +
-			 R128_BUFFER_ALIGN) &
-			~R128_BUFFER_ALIGN);
-   info->depthPitch = ctx->shared.virtualWidth;
-
-   info->backOffset = ((info->depthOffset - bufferSize +
-			R128_BUFFER_ALIGN) &
-		       ~R128_BUFFER_ALIGN);
-   info->backPitch = ctx->shared.virtualWidth;
-
-
-   fprintf(stderr, 
-	   "Will use back buffer at offset 0x%x\n",
-	   info->backOffset);
-   fprintf(stderr, 
-	   "Will use depth buffer at offset 0x%x\n",
-	   info->depthOffset);
-   fprintf(stderr, 
-	   "Will use %d kb for textures at offset 0x%x\n",
-	   info->textureSize/1024, info->textureOffset);
-
-   return 1;
-} 
-
-
-/* Initialize the screen-specific data structures for the DRI and the
-   Rage 128.  This is the main entry point to the device-specific
-   initialization code.  It calls device-independent DRI functions to
-   create the DRI data structures and initialize the DRI state. */
-static GLboolean R128DRIScreenInit(DRIDriverContext *ctx)
-{
-    R128InfoPtr info = ctx->driverPrivate;
-    R128DRIPtr    pR128DRI;
-    int           err, major, minor, patch;
-    drmVersionPtr version;
-    drm_r128_sarea_t *pSAREAPriv;
-
-    switch (ctx->bpp) {
-    case 8:
-	/* These modes are not supported (yet). */
-    case 15:
-    case 24:
-	fprintf(stderr,
-		   "[dri] R128DRIScreenInit failed (depth %d not supported).  "
-		   "[dri] Disabling DRI.\n", ctx->bpp);
-	return GL_FALSE;
-
-	/* Only 16 and 32 color depths are supports currently. */
-    case 16:
-    case 32:
-	break;
-    }
-    r128_drm_page_size = getpagesize();
-    
-    info->registerSize = ctx->MMIOSize;
-    ctx->shared.SAREASize = SAREA_MAX;
-
-    /* Note that drmOpen will try to load the kernel module, if needed. */
-    ctx->drmFD = drmOpen("r128", NULL );
-    if (ctx->drmFD < 0) {
-	fprintf(stderr, "[drm] drmOpen failed\n");
-	return 0;
-    }
-    
-    /* Check the r128 DRM version */
-    version = drmGetVersion(ctx->drmFD);
-    if (version) {
-	if (version->version_major != 2 ||
-	    version->version_minor < 2) {
-	    /* incompatible drm version */
-	    fprintf(stderr,
-		"[dri] R128DRIScreenInit failed because of a version mismatch.\n"
-		"[dri] r128.o kernel module version is %d.%d.%d but version 2.2 or greater is needed.\n"
-		"[dri] Disabling the DRI.\n",
-		version->version_major,
-		version->version_minor,
-		version->version_patchlevel);
-	    drmFreeVersion(version);
-	    return GL_FALSE;
-	}
-	info->drmMinor = version->version_minor;
-	drmFreeVersion(version);
-    }
-    
-    if ((err = drmSetBusid(ctx->drmFD, ctx->pciBusID)) < 0) {
-	fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n",
-		ctx->drmFD, ctx->pciBusID, strerror(-err));
-	return 0;
-    }
-    
-   if (drmAddMap( ctx->drmFD,
-		  0,
-		  ctx->shared.SAREASize,
-		  DRM_SHM,
-		  DRM_CONTAINS_LOCK,
-		  &ctx->shared.hSAREA) < 0)
-   {
-      fprintf(stderr, "[drm] drmAddMap failed\n");
-      return 0;
-   }
-   fprintf(stderr, "[drm] added %d byte SAREA at 0x%08lx\n",
-	   ctx->shared.SAREASize, ctx->shared.hSAREA);
-
-   if (drmMap( ctx->drmFD,
-	       ctx->shared.hSAREA,
-	       ctx->shared.SAREASize,
-	       (drmAddressPtr)(&ctx->pSAREA)) < 0)
-   {
-      fprintf(stderr, "[drm] drmMap failed\n");
-      return 0;
-   }
-   memset(ctx->pSAREA, 0, ctx->shared.SAREASize);
-   fprintf(stderr, "[drm] mapped SAREA 0x%08lx to %p, size %d\n",
-	   ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize);
-   
-   /* Need to AddMap the framebuffer and mmio regions here:
-    */
-   if (drmAddMap( ctx->drmFD,
-		  (drm_handle_t)ctx->FBStart,
-		  ctx->FBSize,
-		  DRM_FRAME_BUFFER,
-		  0,
-		  &ctx->shared.hFrameBuffer) < 0)
-   {
-      fprintf(stderr, "[drm] drmAddMap framebuffer failed\n");
-      return 0;
-   }
-
-   fprintf(stderr, "[drm] framebuffer handle = 0x%08lx\n",
-	   ctx->shared.hFrameBuffer);
-
-   if (!R128MemoryInit(ctx))
-	return GL_FALSE;
-   
-				/* Initialize AGP */
-    if (!info->IsPCI && !R128DRIAgpInit(ctx)) {
-	info->IsPCI = GL_TRUE;
-	fprintf(stderr,
-		   "[agp] AGP failed to initialize -- falling back to PCI mode.\n");
-	fprintf(stderr,
-		   "[agp] Make sure you have the agpgart kernel module loaded.\n");
-    }
-
-				/* Initialize PCIGART */
-    if (info->IsPCI && !R128DRIPciInit(ctx)) {
-	return GL_FALSE;
-    }
-
-				/* DRIScreenInit doesn't add all the
-				   common mappings.  Add additional
-				   mappings here. */
-    if (!R128DRIMapInit(ctx)) {
-	return GL_FALSE;
-    }
-
-   /* Create a 'server' context so we can grab the lock for
-    * initialization ioctls.
-    */
-   if ((err = drmCreateContext(ctx->drmFD, &ctx->serverContext)) != 0) {
-      fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err);
-      return 0;
-   }
-
-   DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0); 
-
-    /* Initialize the kernel data structures */
-    if (!R128DRIKernelInit(ctx)) {
-	return GL_FALSE;
-    }
-
-    /* Initialize the vertex buffers list */
-    if (!R128DRIBufInit(ctx)) {
-	return GL_FALSE;
-    }
-
-    /* Initialize IRQ */
-    R128DRIIrqInit(ctx);
-
-    /* Initialize and start the CCE if required */
-    R128DRICCEInit(ctx);
-
-   /* Quick hack to clear the front & back buffers.  Could also use
-    * the clear ioctl to do this, but would need to setup hw state
-    * first.
-    */
-   drimemsetio((char *)ctx->FBAddress + info->frontOffset,
-	  0,
-	  info->frontPitch * ctx->cpp * ctx->shared.virtualHeight );
-
-   drimemsetio((char *)ctx->FBAddress + info->backOffset,
-	  0,
-	  info->backPitch * ctx->cpp * ctx->shared.virtualHeight );
-    
-    pSAREAPriv = (drm_r128_sarea_t *)(((char*)ctx->pSAREA) + 
-					sizeof(drm_sarea_t));
-    memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
-
-   /* This is the struct passed to radeon_dri.so for its initialization */
-   ctx->driverClientMsg = malloc(sizeof(R128DRIRec));
-   ctx->driverClientMsgSize = sizeof(R128DRIRec);
-   
-    pR128DRI                    = (R128DRIPtr)ctx->driverClientMsg;
-    pR128DRI->deviceID          = info->Chipset;
-    pR128DRI->width             = ctx->shared.virtualWidth;
-    pR128DRI->height            = ctx->shared.virtualHeight;
-    pR128DRI->depth             = ctx->bpp;
-    pR128DRI->bpp               = ctx->bpp;
-
-    pR128DRI->IsPCI             = info->IsPCI;
-    pR128DRI->AGPMode           = info->agpMode;
-
-    pR128DRI->frontOffset       = info->frontOffset;
-    pR128DRI->frontPitch        = info->frontPitch;
-    pR128DRI->backOffset        = info->backOffset;
-    pR128DRI->backPitch         = info->backPitch;
-    pR128DRI->depthOffset       = info->depthOffset;
-    pR128DRI->depthPitch        = info->depthPitch;
-    pR128DRI->spanOffset        = info->spanOffset;
-    pR128DRI->textureOffset     = info->textureOffset;
-    pR128DRI->textureSize       = info->textureSize;
-    pR128DRI->log2TexGran       = info->log2TexGran;
-
-    pR128DRI->registerHandle    = info->registerHandle;
-    pR128DRI->registerSize      = info->registerSize;
-
-    pR128DRI->agpTexHandle      = info->agpTexHandle;
-    pR128DRI->agpTexMapSize     = info->agpTexMapSize;
-    pR128DRI->log2AGPTexGran    = info->log2AGPTexGran;
-    pR128DRI->agpTexOffset      = info->agpTexStart;
-    pR128DRI->sarea_priv_offset = sizeof(drm_sarea_t);
-
-    return GL_TRUE;
-}
-
-/* The screen is being closed, so clean up any state and free any
-   resources used by the DRI. */
-void R128DRICloseScreen(const DRIDriverContext *ctx)
-{
-    R128InfoPtr info = ctx->driverPrivate;
-    drm_r128_init_t drmInfo;
-
-    /* Stop the CCE if it is still in use */
-    R128CCE_STOP(ctx, info);
-
-    if (info->irq) {
-	drmCtlUninstHandler(ctx->drmFD);
-	info->irq = 0;
-    }
-
-    /* De-allocate vertex buffers */
-    if (info->buffers) {
-	drmUnmapBufs(info->buffers);
-	info->buffers = NULL;
-    }
-
-    /* De-allocate all kernel resources */
-    memset(&drmInfo, 0, sizeof(drmInfo));
-    drmInfo.func = R128_CLEANUP_CCE;
-    drmCommandWrite(ctx->drmFD, DRM_R128_INIT,
-                    &drmInfo, sizeof(drmInfo));
-
-    /* De-allocate all AGP resources */
-    if (info->agpTex) {
-	drmUnmap(info->agpTex, info->agpTexMapSize);
-	info->agpTex = NULL;
-    }
-    if (info->buf) {
-	drmUnmap(info->buf, info->bufMapSize);
-	info->buf = NULL;
-    }
-    if (info->ringReadPtr) {
-	drmUnmap(info->ringReadPtr, info->ringReadMapSize);
-	info->ringReadPtr = NULL;
-    }
-    if (info->ring) {
-	drmUnmap(info->ring, info->ringMapSize);
-	info->ring = NULL;
-    }
-    if (info->agpMemHandle != DRM_AGP_NO_HANDLE) {
-	drmAgpUnbind(ctx->drmFD, info->agpMemHandle);
-	drmAgpFree(ctx->drmFD, info->agpMemHandle);
-	info->agpMemHandle = 0;
-	drmAgpRelease(ctx->drmFD);
-    }
-    if (info->pciMemHandle) {
-	drmScatterGatherFree(ctx->drmFD, info->pciMemHandle);
-	info->pciMemHandle = 0;
-    }
-}
-
-static GLboolean R128PreInitDRI(const DRIDriverContext *ctx)
-{
-    R128InfoPtr info = ctx->driverPrivate;
-
-    /*info->CCEMode = R128_DEFAULT_CCE_PIO_MODE;*/
-    info->CCEMode = R128_DEFAULT_CCE_BM_MODE;
-    info->CCESecure = GL_TRUE;
-
-    info->agpMode        = R128_DEFAULT_AGP_MODE;
-    info->agpSize        = R128_DEFAULT_AGP_SIZE;
-    info->ringSize       = R128_DEFAULT_RING_SIZE;
-    info->bufSize        = R128_DEFAULT_BUFFER_SIZE;
-    info->agpTexSize     = R128_DEFAULT_AGP_TEX_SIZE;
-
-    info->CCEusecTimeout = R128_DEFAULT_CCE_TIMEOUT;
-
-    return GL_TRUE;
-}
-
-/**
- * \brief Initialize the framebuffer device mode
- *
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Fills in \p info with some default values and some information from \p ctx
- * and then calls R128ScreenInit() for the screen initialization.
- * 
- * Before exiting clears the framebuffer memory accessing it directly.
- */
-static int R128InitFBDev( DRIDriverContext *ctx )
-{
-   R128InfoPtr info = calloc(1, sizeof(*info));
-
-   {
-      int  dummy = ctx->shared.virtualWidth;
-
-      switch (ctx->bpp / 8) {
-      case 1: dummy = (ctx->shared.virtualWidth + 127) & ~127; break;
-      case 2: dummy = (ctx->shared.virtualWidth +  31) &  ~31; break;
-      case 3:
-      case 4: dummy = (ctx->shared.virtualWidth +  15) &  ~15; break;
-      }
-
-      ctx->shared.virtualWidth = dummy;
-   }
-
-   ctx->driverPrivate = (void *)info;
-   
-   info->Chipset = ctx->chipset;
-
-   switch (info->Chipset) {
-   case PCI_DEVICE_ID_ATI_RAGE128_LE:
-   case PCI_DEVICE_ID_ATI_RAGE128_RE:
-   case PCI_DEVICE_ID_ATI_RAGE128_RK:
-   case PCI_DEVICE_ID_ATI_RAGE128_PD:
-   case PCI_DEVICE_ID_ATI_RAGE128_PP:
-   case PCI_DEVICE_ID_ATI_RAGE128_PR:
-       /* This is a PCI card */
-       info->IsPCI = GL_TRUE;
-       break;
-   default:
-       /* This is an AGP card */
-       info->IsPCI = GL_FALSE;
-       break;
-   }
-
-   info->frontPitch = ctx->shared.virtualWidth;
-   info->LinearAddr = ctx->FBStart & 0xfc000000;
-   
-   if (!R128PreInitDRI(ctx))
-       return 0;
-
-   if (!R128DRIScreenInit(ctx))
-      return 0;
-
-   return 1;
-}
-
-
-/**
- * \brief The screen is being closed, so clean up any state and free any
- * resources used by the DRI.
- *
- * \param ctx display handle.
- *
- * Unmaps the SAREA, closes the DRM device file descriptor and frees the driver
- * private data.
- */
-static void R128HaltFBDev( DRIDriverContext *ctx )
-{
-    drmUnmap( ctx->pSAREA, ctx->shared.SAREASize );
-    drmClose(ctx->drmFD);
-
-    if (ctx->driverPrivate) {
-       free(ctx->driverPrivate);
-       ctx->driverPrivate = 0;
-    }
-}
-
-
-/**
- * \brief Validate the fbdev mode.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Saves some registers and returns 1.
- *
- * \sa R128PostValidateMode().
- */
-static int R128ValidateMode( const DRIDriverContext *ctx )
-{
-   return 1;
-}
-
-
-/**
- * \brief Examine mode returned by fbdev.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Restores registers that fbdev has clobbered and returns 1.
- *
- * \sa R128ValidateMode().
- */
-static int R128PostValidateMode( const DRIDriverContext *ctx )
-{
-   return 1;
-}
-
-
-/**
- * \brief Shutdown the drawing engine.
- *
- * \param ctx display handle
- *
- * Turns off the command processor engine & restores the graphics card
- * to a state that fbdev understands.
- */
-static int R128EngineShutdown( const DRIDriverContext *ctx )
-{
-    return 1;
-}
-
-/**
- * \brief Restore the drawing engine.
- *
- * \param ctx display handle
- *
- * Resets the graphics card and sets initial values for several registers of
- * the card's drawing engine.
- *
- * Turns on the R128 command processor engine (i.e., the ringbuffer).
- */
-static int R128EngineRestore( const DRIDriverContext *ctx )
-{
-   return 1;
-}
-
-
-/**
- * \brief Exported driver interface for Mini GLX.
- *
- * \sa DRIDriverRec.
- */
-const struct DRIDriverRec __driDriver = {
-   R128ValidateMode,
-   R128PostValidateMode,
-   R128InitFBDev,
-   R128HaltFBDev,
-   R128EngineShutdown,
-   R128EngineRestore,  
-   0,
-};
diff --git a/src/mesa/drivers/dri/r200/server/radeon_dri.c b/src/mesa/drivers/dri/r200/server/radeon_dri.c
deleted file mode 120000
index d05847d650..0000000000
--- a/src/mesa/drivers/dri/r200/server/radeon_dri.c
+++ /dev/null
@@ -1 +0,0 @@
-../../radeon/server/radeon_dri.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r300/server/radeon_dri.c b/src/mesa/drivers/dri/r300/server/radeon_dri.c
deleted file mode 120000
index d05847d650..0000000000
--- a/src/mesa/drivers/dri/r300/server/radeon_dri.c
+++ /dev/null
@@ -1 +0,0 @@
-../../radeon/server/radeon_dri.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/server/radeon_dri.c b/src/mesa/drivers/dri/r600/server/radeon_dri.c
deleted file mode 120000
index d05847d650..0000000000
--- a/src/mesa/drivers/dri/r600/server/radeon_dri.c
+++ /dev/null
@@ -1 +0,0 @@
-../../radeon/server/radeon_dri.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/radeon/server/radeon_dri.c b/src/mesa/drivers/dri/radeon/server/radeon_dri.c
deleted file mode 100644
index 7ead588dac..0000000000
--- a/src/mesa/drivers/dri/radeon/server/radeon_dri.c
+++ /dev/null
@@ -1,1337 +0,0 @@
-/**
- * \file server/radeon_dri.c
- * \brief File to perform the device-specific initialization tasks typically
- * done in the X server.
- *
- * Here they are converted to run in the client (or perhaps a standalone
- * process), and to work with the frame buffer device rather than the X
- * server infrastructure.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <errno.h>
-#include <unistd.h>
-
-#include "driver.h"
-#include "drm.h"
-#include "memops.h"
-
-#include "radeon.h"
-#include "radeon_dri.h"
-#include "radeon_macros.h"
-#include "radeon_reg.h"
-#include "drm_sarea.h"
-
-static size_t radeon_drm_page_size;
-
-static int RadeonSetParam(const DRIDriverContext *ctx, int param, int value)
-{
-   drm_radeon_setparam_t sp;
-
-   memset(&sp, 0, sizeof(sp));
-   sp.param = param;
-   sp.value = value;
-
-   if (drmCommandWrite(ctx->drmFD, DRM_RADEON_SETPARAM, &sp, sizeof(sp))) {
-     return -1;
-   }
-
-   return 0;
-}
-
-/**
- * \brief Wait for free FIFO entries.
- *
- * \param ctx display handle.
- * \param entries number of free entries to wait.
- *
- * It polls the free entries from the chip until it reaches the requested value
- * or a timeout (3000 tries) occurs. Aborts the program if the FIFO times out.
- */
-static void RADEONWaitForFifo( const DRIDriverContext *ctx,
-			       int entries )
-{
-   unsigned char *RADEONMMIO = ctx->MMIOAddress;
-   int i;
-
-   for (i = 0; i < 3000; i++) {
-      int fifo_slots =
-	 INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
-      if (fifo_slots >= entries) return;
-   }
-
-   /* There are recoveries possible, but I haven't seen them work
-    * in practice:
-    */
-   fprintf(stderr, "FIFO timed out: %d entries, stat=0x%08x\n",
-	   INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
-	   INREG(RADEON_RBBM_STATUS));
-   exit(1);
-}
-
-/**
- * \brief Read a PLL register.
- *
- * \param ctx display handle.
- * \param addr PLL register index.
- *
- * \return value of the PLL register.
- */
-static unsigned int RADEONINPLL( const DRIDriverContext *ctx, int addr)
-{
-    unsigned char *RADEONMMIO = ctx->MMIOAddress;
-    unsigned int data;
-
-    OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f);
-    data = INREG(RADEON_CLOCK_CNTL_DATA);
-
-    return data;
-}
-
-/**
- * \brief Reset graphics card to known state.
- *
- * \param ctx display handle.
- *
- * Resets the values of several Radeon registers.
- */
-static void RADEONEngineReset( const DRIDriverContext *ctx )
-{
-   unsigned char *RADEONMMIO = ctx->MMIOAddress;
-   unsigned int clock_cntl_index;
-   unsigned int mclk_cntl;
-   unsigned int rbbm_soft_reset;
-   unsigned int host_path_cntl;
-   int i;
-
-   OUTREGP(RADEON_RB2D_DSTCACHE_CTLSTAT,
-	   RADEON_RB2D_DC_FLUSH_ALL,
-	   ~RADEON_RB2D_DC_FLUSH_ALL);
-   for (i = 0; i < 512; i++) {
-      if (!(INREG(RADEON_RB2D_DSTCACHE_CTLSTAT) & RADEON_RB2D_DC_BUSY))
-	 break;
-   }
-
-   clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX);
-
-   mclk_cntl = INPLL(ctx, RADEON_MCLK_CNTL);
-   OUTPLL(RADEON_MCLK_CNTL, (mclk_cntl |
-			     RADEON_FORCEON_MCLKA |
-			     RADEON_FORCEON_MCLKB |
-			     RADEON_FORCEON_YCLKA |
-			     RADEON_FORCEON_YCLKB |
-			     RADEON_FORCEON_MC |
-			     RADEON_FORCEON_AIC));
-
-   /* Soft resetting HDP thru RBBM_SOFT_RESET register can cause some
-    * unexpected behaviour on some machines.  Here we use
-    * RADEON_HOST_PATH_CNTL to reset it.
-    */
-   host_path_cntl = INREG(RADEON_HOST_PATH_CNTL);
-   rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET);
-
-   OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
-				   RADEON_SOFT_RESET_CP |
-				   RADEON_SOFT_RESET_HI |
-				   RADEON_SOFT_RESET_SE |
-				   RADEON_SOFT_RESET_RE |
-				   RADEON_SOFT_RESET_PP |
-				   RADEON_SOFT_RESET_E2 |
-				   RADEON_SOFT_RESET_RB));
-   INREG(RADEON_RBBM_SOFT_RESET);
-   OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & 
-				   (unsigned int) ~(RADEON_SOFT_RESET_CP |
-						    RADEON_SOFT_RESET_HI |
-						    RADEON_SOFT_RESET_SE |
-						    RADEON_SOFT_RESET_RE |
-						    RADEON_SOFT_RESET_PP |
-						    RADEON_SOFT_RESET_E2 |
-						    RADEON_SOFT_RESET_RB)));
-   INREG(RADEON_RBBM_SOFT_RESET);
-
-   OUTREG(RADEON_HOST_PATH_CNTL, host_path_cntl | RADEON_HDP_SOFT_RESET);
-   INREG(RADEON_HOST_PATH_CNTL);
-   OUTREG(RADEON_HOST_PATH_CNTL, host_path_cntl);
-
-   OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
-
-   OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
-   OUTPLL(RADEON_MCLK_CNTL, mclk_cntl);
-}
-
-/**
- * \brief Restore the drawing engine.
- *
- * \param ctx display handle
- *
- * Resets the graphics card and sets initial values for several registers of
- * the card's drawing engine.
- *
- * Turns on the radeon command processor engine (i.e., the ringbuffer).
- */
-static int RADEONEngineRestore( const DRIDriverContext *ctx )
-{
-   RADEONInfoPtr info = ctx->driverPrivate;
-   unsigned char *RADEONMMIO = ctx->MMIOAddress;
-   int pitch64, datatype, dp_gui_master_cntl, err;
-
-   fprintf(stderr, "%s\n", __FUNCTION__);
-
-   OUTREG(RADEON_RB3D_CNTL, 0);
-   RADEONEngineReset( ctx );
-
-   switch (ctx->bpp) {
-   case 16: datatype = 4; break;
-   case 32: datatype = 6; break;
-   default: return 0;
-   }
-
-   dp_gui_master_cntl =
-      ((datatype << RADEON_GMC_DST_DATATYPE_SHIFT)
-       | RADEON_GMC_CLR_CMP_CNTL_DIS);
-
-   pitch64 = ((ctx->shared.virtualWidth * (ctx->bpp / 8) + 0x3f)) >> 6;
-
-   RADEONWaitForFifo(ctx, 1);
-   OUTREG(RADEON_DEFAULT_OFFSET, ((INREG(RADEON_DEFAULT_OFFSET) & 0xC0000000)
-				  | (pitch64 << 22)));
-
-   RADEONWaitForFifo(ctx, 1);
-   OUTREG(RADEON_SURFACE_CNTL, RADEON_SURF_TRANSLATION_DIS); 
-
-   RADEONWaitForFifo(ctx, 1);
-   OUTREG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX
-					   | RADEON_DEFAULT_SC_BOTTOM_MAX));
-
-   RADEONWaitForFifo(ctx, 1);
-   OUTREG(RADEON_DP_GUI_MASTER_CNTL, (dp_gui_master_cntl
-				      | RADEON_GMC_BRUSH_SOLID_COLOR
-				      | RADEON_GMC_SRC_DATATYPE_COLOR));
-
-   RADEONWaitForFifo(ctx, 7);
-   OUTREG(RADEON_DST_LINE_START,    0);
-   OUTREG(RADEON_DST_LINE_END,      0);
-   OUTREG(RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff);
-   OUTREG(RADEON_DP_BRUSH_BKGD_CLR, 0);
-   OUTREG(RADEON_DP_SRC_FRGD_CLR,   0xffffffff);
-   OUTREG(RADEON_DP_SRC_BKGD_CLR,   0);
-   OUTREG(RADEON_DP_WRITE_MASK,     0xffffffff);
-   OUTREG(RADEON_AUX_SC_CNTL,       0);
-
-/*    RADEONWaitForIdleMMIO(ctx); */
-   usleep(100); 
-
-
-   OUTREG(RADEON_GEN_INT_CNTL, info->gen_int_cntl);
-   if (info->colorTiling)
-	   info->crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
-   OUTREG(RADEON_CRTC_OFFSET_CNTL, info->crtc_offset_cntl);
-
-   /* Initialize and start the CP if required */
-   if ((err = drmCommandNone(ctx->drmFD, DRM_RADEON_CP_START)) != 0) {
-      fprintf(stderr, "%s: CP start %d\n", __FUNCTION__, err);
-      return 0;
-   }
-
-   return 1;
-}
-
-
-/**
- * \brief Shutdown the drawing engine.
- *
- * \param ctx display handle
- *
- * Turns off the command processor engine & restores the graphics card
- * to a state that fbdev understands.
- */
-static int RADEONEngineShutdown( const DRIDriverContext *ctx )
-{
-   drm_radeon_cp_stop_t  stop;
-   int              ret, i;
-
-   stop.flush = 1;
-   stop.idle  = 1;
-
-   ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_STOP, &stop, 
-			 sizeof(drm_radeon_cp_stop_t));
-
-   if (ret == 0) {
-      return 0;
-   } else if (errno != EBUSY) {
-      return -errno;
-   }
-
-   stop.flush = 0;
- 
-   i = 0;
-   do {
-      ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_STOP, &stop, 
-			    sizeof(drm_radeon_cp_stop_t));
-   } while (ret && errno == EBUSY && i++ < 10);
-
-   if (ret == 0) {
-      return 0;
-   } else if (errno != EBUSY) {
-      return -errno;
-   }
-
-   stop.idle = 0;
-
-   if (drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_STOP,
-		       &stop, sizeof(drm_radeon_cp_stop_t))) {
-      return -errno;
-   } else {
-      return 0;
-   }
-}
-
-/**
- * \brief Compute base 2 logarithm.
- *
- * \param val value.
- * 
- * \return base 2 logarithm of \p val.
- */
-static int RADEONMinBits(int val)
-{
-   int  bits;
-
-   if (!val) return 1;
-   for (bits = 0; val; val >>= 1, ++bits);
-   return bits;
-}
-
-/**
- * \brief Initialize the AGP state
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return one on success, or zero on failure.
- * 
- * Acquires and enables the AGP device. Reserves memory in the AGP space for
- * the ring buffer, vertex buffers and textures. Initialize the Radeon
- * registers to point to that memory and add client mappings.
- */
-static int RADEONDRIAgpInit( const DRIDriverContext *ctx, RADEONInfoPtr info)
-{
-   unsigned char *RADEONMMIO = ctx->MMIOAddress;
-   unsigned long  mode;
-   int            ret;
-   int            s, l;
-
-   if (drmAgpAcquire(ctx->drmFD) < 0) {
-      fprintf(stderr, "[gart] AGP not available\n");
-      return 0;
-   }
-    
-   /* Modify the mode if the default mode is not appropriate for this
-    * particular combination of graphics card and AGP chipset.
-    */
-   mode   = drmAgpGetMode(ctx->drmFD);	/* Default mode */
-
-   /* Disable fast write entirely - too many lockups.
-    */
-   mode &= ~RADEON_AGP_MODE_MASK;
-   switch (ctx->agpmode) {
-   case 4:          mode |= RADEON_AGP_4X_MODE;
-   case 2:          mode |= RADEON_AGP_2X_MODE;
-   case 1: default: mode |= RADEON_AGP_1X_MODE;
-   }
-
-   if (drmAgpEnable(ctx->drmFD, mode) < 0) {
-      fprintf(stderr, "[gart] AGP not enabled\n");
-      drmAgpRelease(ctx->drmFD);
-      return 0;
-   }
-   else
-     fprintf(stderr, "[gart] AGP enabled at %dx\n", ctx->agpmode);
-
-   /* Workaround for some hardware bugs */
-   if (info->ChipFamily < CHIP_FAMILY_R200)
-      OUTREG(RADEON_AGP_CNTL, INREG(RADEON_AGP_CNTL) | 0x000e0000);
-
-   info->gartOffset = 0;
-
-   if ((ret = drmAgpAlloc(ctx->drmFD, info->gartSize*1024*1024, 0, NULL,
-			  &info->gartMemHandle)) < 0) {
-      fprintf(stderr, "[gart] Out of memory (%d)\n", ret);
-      drmAgpRelease(ctx->drmFD);
-      return 0;
-   }
-   fprintf(stderr,
-	   "[gart] %d kB allocated with handle 0x%08x\n",
-	   info->gartSize*1024, (unsigned)info->gartMemHandle);
-    
-   if (drmAgpBind(ctx->drmFD,
-		  info->gartMemHandle, info->gartOffset) < 0) {
-      fprintf(stderr, "[gart] Could not bind\n");
-      drmAgpFree(ctx->drmFD, info->gartMemHandle);
-      drmAgpRelease(ctx->drmFD);
-      return 0;
-   }
-
-   /* Initialize the CP ring buffer data */
-   info->ringStart       = info->gartOffset;
-   info->ringMapSize     = info->ringSize*1024*1024 + radeon_drm_page_size;
-
-   info->ringReadOffset  = info->ringStart + info->ringMapSize;
-   info->ringReadMapSize = radeon_drm_page_size;
-
-   /* Reserve space for vertex/indirect buffers */
-   info->bufStart        = info->ringReadOffset + info->ringReadMapSize;
-   info->bufMapSize      = info->bufSize*1024*1024;
-
-   /* Reserve the rest for AGP textures */
-   info->gartTexStart     = info->bufStart + info->bufMapSize;
-   s = (info->gartSize*1024*1024 - info->gartTexStart);
-   l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS);
-   if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY;
-   info->gartTexMapSize   = (s >> l) << l;
-   info->log2GARTTexGran  = l;
-
-   if (drmAddMap(ctx->drmFD, info->ringStart, info->ringMapSize,
-		 DRM_AGP, DRM_READ_ONLY, &info->ringHandle) < 0) {
-      fprintf(stderr, "[gart] Could not add ring mapping\n");
-      return 0;
-   }
-   fprintf(stderr, "[gart] ring handle = 0x%08x\n", info->ringHandle);
-    
-
-   if (drmAddMap(ctx->drmFD, info->ringReadOffset, info->ringReadMapSize,
-		 DRM_AGP, DRM_READ_ONLY, &info->ringReadPtrHandle) < 0) {
-      fprintf(stderr,
-	      "[gart] Could not add ring read ptr mapping\n");
-      return 0;
-   }
-    
-   fprintf(stderr,
- 	   "[gart] ring read ptr handle = 0x%08lx\n",
-	   info->ringReadPtrHandle);
-    
-   if (drmAddMap(ctx->drmFD, info->bufStart, info->bufMapSize,
-		 DRM_AGP, 0, &info->bufHandle) < 0) {
-      fprintf(stderr,
-	      "[gart] Could not add vertex/indirect buffers mapping\n");
-      return 0;
-   }
-   fprintf(stderr,
- 	   "[gart] vertex/indirect buffers handle = 0x%08x\n",
-	   info->bufHandle);
-
-   if (drmAddMap(ctx->drmFD, info->gartTexStart, info->gartTexMapSize,
-		 DRM_AGP, 0, &info->gartTexHandle) < 0) {
-      fprintf(stderr,
-	      "[gart] Could not add AGP texture map mapping\n");
-      return 0;
-   }
-   fprintf(stderr,
- 	   "[gart] AGP texture map handle = 0x%08lx\n",
-	   info->gartTexHandle);
-
-   /* Initialize Radeon's AGP registers */
-   /* Ring buffer is at AGP offset 0 */
-   OUTREG(RADEON_AGP_BASE, info->ringHandle);
-
-   return 1;
-}
-
-/* Initialize the PCI GART state.  Request memory for use in PCI space,
- * and initialize the Radeon registers to point to that memory.
- */
-static int RADEONDRIPciInit(const DRIDriverContext *ctx, RADEONInfoPtr info)
-{
-    int  ret;
-    int  flags = DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL;
-    int            s, l;
-
-    ret = drmScatterGatherAlloc(ctx->drmFD, info->gartSize*1024*1024,
-				&info->gartMemHandle);
-    if (ret < 0) {
-	fprintf(stderr, "[pci] Out of memory (%d)\n", ret);
-	return 0;
-    }
-    fprintf(stderr,
-	       "[pci] %d kB allocated with handle 0x%08lx\n",
-	       info->gartSize*1024, info->gartMemHandle);
-
-   info->gartOffset = 0;
-   
-   /* Initialize the CP ring buffer data */
-   info->ringStart       = info->gartOffset;
-   info->ringMapSize     = info->ringSize*1024*1024 + radeon_drm_page_size;
-
-   info->ringReadOffset  = info->ringStart + info->ringMapSize;
-   info->ringReadMapSize = radeon_drm_page_size;
-
-   /* Reserve space for vertex/indirect buffers */
-   info->bufStart        = info->ringReadOffset + info->ringReadMapSize;
-   info->bufMapSize      = info->bufSize*1024*1024;
-
-   /* Reserve the rest for AGP textures */
-   info->gartTexStart     = info->bufStart + info->bufMapSize;
-   s = (info->gartSize*1024*1024 - info->gartTexStart);
-   l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS);
-   if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY;
-   info->gartTexMapSize   = (s >> l) << l;
-   info->log2GARTTexGran  = l;
-
-    if (drmAddMap(ctx->drmFD, info->ringStart, info->ringMapSize,
-		  DRM_SCATTER_GATHER, flags, &info->ringHandle) < 0) {
-	fprintf(stderr,
-		   "[pci] Could not add ring mapping\n");
-	return 0;
-    }
-    fprintf(stderr,
-	       "[pci] ring handle = 0x%08x\n", info->ringHandle);
-
-    if (drmAddMap(ctx->drmFD, info->ringReadOffset, info->ringReadMapSize,
-		  DRM_SCATTER_GATHER, flags, &info->ringReadPtrHandle) < 0) {
-	fprintf(stderr,
-		   "[pci] Could not add ring read ptr mapping\n");
-	return 0;
-    }
-    fprintf(stderr,
- 	       "[pci] ring read ptr handle = 0x%08lx\n",
-	       info->ringReadPtrHandle);
-
-    if (drmAddMap(ctx->drmFD, info->bufStart, info->bufMapSize,
-		  DRM_SCATTER_GATHER, 0, &info->bufHandle) < 0) {
-	fprintf(stderr,
-		   "[pci] Could not add vertex/indirect buffers mapping\n");
-	return 0;
-    }
-    fprintf(stderr,
- 	       "[pci] vertex/indirect buffers handle = 0x%08lx\n",
-	       info->bufHandle);
-
-    if (drmAddMap(ctx->drmFD, info->gartTexStart, info->gartTexMapSize,
-		  DRM_SCATTER_GATHER, 0, &info->gartTexHandle) < 0) {
-	fprintf(stderr,
-		   "[pci] Could not add GART texture map mapping\n");
-	return 0;
-    }
-    fprintf(stderr,
- 	       "[pci] GART texture map handle = 0x%08x\n",
-	       info->gartTexHandle);
-
-    return 1;
-}
-
-
-/**
- * \brief Initialize the kernel data structures and enable the CP engine.
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return non-zero on success, or zero on failure.
- *
- * This function is a wrapper around the DRM_RADEON_CP_INIT command, passing
- * all the parameters in a drm_radeon_init_t structure.
- */
-static int RADEONDRIKernelInit( const DRIDriverContext *ctx,
-			       RADEONInfoPtr info)
-{
-   int cpp = ctx->bpp / 8;
-   drm_radeon_init_t  drmInfo;
-   int ret;
-
-   memset(&drmInfo, 0, sizeof(drm_radeon_init_t));
-
-   if ( (info->ChipFamily == CHIP_FAMILY_R200) ||
-	(info->ChipFamily == CHIP_FAMILY_RV250) ||
-	(info->ChipFamily == CHIP_FAMILY_M9) ||
-	(info->ChipFamily == CHIP_FAMILY_RV280) )
-      drmInfo.func             = RADEON_INIT_R200_CP;
-   else
-      drmInfo.func             = RADEON_INIT_CP;
-
-   /* This is the struct passed to the kernel module for its initialization */
-   drmInfo.sarea_priv_offset   = sizeof(drm_sarea_t);
-   drmInfo.is_pci              = ctx->isPCI;
-   drmInfo.cp_mode             = RADEON_DEFAULT_CP_BM_MODE;
-   drmInfo.gart_size            = info->gartSize*1024*1024;
-   drmInfo.ring_size           = info->ringSize*1024*1024;
-   drmInfo.usec_timeout        = 1000;
-   drmInfo.fb_bpp              = ctx->bpp;
-   drmInfo.depth_bpp           = ctx->bpp;
-   drmInfo.front_offset        = info->frontOffset;
-   drmInfo.front_pitch         = info->frontPitch * cpp;
-   drmInfo.back_offset         = info->backOffset;
-   drmInfo.back_pitch          = info->backPitch * cpp;
-   drmInfo.depth_offset        = info->depthOffset;
-   drmInfo.depth_pitch         = info->depthPitch * cpp;
-   drmInfo.fb_offset           = info->LinearAddr;
-   drmInfo.mmio_offset         = info->registerHandle;
-   drmInfo.ring_offset         = info->ringHandle;
-   drmInfo.ring_rptr_offset    = info->ringReadPtrHandle;
-   drmInfo.buffers_offset      = info->bufHandle;
-   drmInfo.gart_textures_offset = info->gartTexHandle;
-
-   ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_INIT, &drmInfo, 
-			 sizeof(drm_radeon_init_t));
-
-   return ret >= 0;
-}
-
-
-/**
- * \brief Initialize the AGP heap.
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * This function is a wrapper around the DRM_RADEON_INIT_HEAP command, passing
- * all the parameters in a drm_radeon_mem_init_heap structure.
- */
-static void RADEONDRIAgpHeapInit(const DRIDriverContext *ctx,
-				 RADEONInfoPtr info)
-{
-   drm_radeon_mem_init_heap_t drmHeap;
-
-   /* Start up the simple memory manager for gart space */
-   drmHeap.region = RADEON_MEM_REGION_GART;
-   drmHeap.start  = 0;
-   drmHeap.size   = info->gartTexMapSize;
-    
-   if (drmCommandWrite(ctx->drmFD, DRM_RADEON_INIT_HEAP,
-		       &drmHeap, sizeof(drmHeap))) {
-      fprintf(stderr,
-	      "[drm] Failed to initialized gart heap manager\n");
-   } else {
-      fprintf(stderr,
-	      "[drm] Initialized kernel gart heap manager, %d\n",
-	      info->gartTexMapSize);
-   }
-}
-
-/**
- * \brief Add a map for the vertex buffers that will be accessed by any
- * DRI-based clients.
- * 
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return one on success, or zero on failure.
- *
- * Calls drmAddBufs() with the previously allocated vertex buffers.
- */
-static int RADEONDRIBufInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
-{
-   /* Initialize vertex buffers */
-   info->bufNumBufs = drmAddBufs(ctx->drmFD,
-				 info->bufMapSize / RADEON_BUFFER_SIZE,
-				 RADEON_BUFFER_SIZE,
-				 ctx->isPCI ? DRM_SG_BUFFER : DRM_AGP_BUFFER,
-				 info->bufStart);
-
-   if (info->bufNumBufs <= 0) {
-      fprintf(stderr,
-	      "[drm] Could not create vertex/indirect buffers list\n");
-      return 0;
-   }
-   fprintf(stderr,
-	   "[drm] Added %d %d byte vertex/indirect buffers\n",
-	   info->bufNumBufs, RADEON_BUFFER_SIZE);
-   
-   return 1;
-}
-
-/**
- * \brief Install an IRQ handler.
- * 
- * \param ctx display handle.
- * \param info driver private data.
- *
- * Attempts to install an IRQ handler via drmCtlInstHandler(), falling back to
- * IRQ-free operation on failure.
- */
-static void RADEONDRIIrqInit(const DRIDriverContext *ctx,
-			     RADEONInfoPtr info)
-{
-   if (!info->irq) {
-      info->irq = drmGetInterruptFromBusID(ctx->drmFD,
-					   ctx->pciBus,
-					   ctx->pciDevice,
-					   ctx->pciFunc);
-
-      if ((drmCtlInstHandler(ctx->drmFD, info->irq)) != 0) {
-	 fprintf(stderr,
-		 "[drm] failure adding irq handler, "
-		 "there is a device already using that irq\n"
-		 "[drm] falling back to irq-free operation\n");
-	 info->irq = 0;
-      }
-   }
-
-   if (info->irq)
-      fprintf(stderr,
-	      "[drm] dma control initialized, using IRQ %d\n",
-	      info->irq);
-}
-
-static int RADEONCheckDRMVersion( const DRIDriverContext *ctx,
-				  RADEONInfoPtr info )
-{
-   drmVersionPtr  version;
-
-   version = drmGetVersion(ctx->drmFD);
-   if (version) {
-      int req_minor, req_patch;
-
-      /* Need 1.8.x for proper cleanup-on-client-exit behaviour.
-       */
-      req_minor = 8;
-      req_patch = 0;	
-
-      if (version->version_major != 1 ||
-	  version->version_minor < req_minor ||
-	  (version->version_minor == req_minor && 
-	   version->version_patchlevel < req_patch)) {
-	 /* Incompatible drm version */
-	 fprintf(stderr,
-		 "[dri] RADEONDRIScreenInit failed because of a version "
-		 "mismatch.\n"
-		 "[dri] radeon.o kernel module version is %d.%d.%d "
-		 "but version 1.%d.%d or newer is needed.\n"
-		 "[dri] Disabling DRI.\n",
-		 version->version_major,
-		 version->version_minor,
-		 version->version_patchlevel,
-		 req_minor,
-		 req_patch);
-	 drmFreeVersion(version);
-	 return 0;
-      }
-
-      info->drmMinor = version->version_minor;
-      drmFreeVersion(version);
-   }
-
-   return 1;
-}
-
-static int RADEONMemoryInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
-{
-   int        width_bytes = ctx->shared.virtualWidth * ctx->cpp;
-   int        cpp         = ctx->cpp;
-   int        bufferSize  = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes			     + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
-   int        depthSize   = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes
-			     + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
-   int        l;
-
-   info->frontOffset = 0;
-   info->frontPitch = ctx->shared.virtualWidth;
-
-   fprintf(stderr, 
-	   "Using %d MB AGP aperture\n", info->gartSize);
-   fprintf(stderr, 
-	   "Using %d MB for the ring buffer\n", info->ringSize);
-   fprintf(stderr, 
-	   "Using %d MB for vertex/indirect buffers\n", info->bufSize);
-   fprintf(stderr, 
-	   "Using %d MB for AGP textures\n", info->gartTexSize);
-
-   /* Front, back and depth buffers - everything else texture??
-    */
-   info->textureSize = ctx->shared.fbSize - 2 * bufferSize - depthSize;
-
-   if (ctx->colorTiling==1)
-   {
-	info->textureSize = ctx->shared.fbSize - ((ctx->shared.fbSize - info->textureSize + width_bytes * 16 - 1) / (width_bytes * 16)) * (width_bytes*16);
-   }
-
-   if (info->textureSize < 0) 
-      return 0;
-
-   l = RADEONMinBits((info->textureSize-1) / RADEON_NR_TEX_REGIONS);
-   if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY;
-
-   /* Round the texture size up to the nearest whole number of
-    * texture regions.  Again, be greedy about this, don't
-    * round down.
-    */
-   info->log2TexGran = l;
-   info->textureSize = (info->textureSize >> l) << l;
-
-   /* Set a minimum usable local texture heap size.  This will fit
-    * two 256x256x32bpp textures.
-    */
-   if (info->textureSize < 512 * 1024) {
-      info->textureOffset = 0;
-      info->textureSize = 0;
-   }
-
-   /* Reserve space for textures */
-   if (ctx->colorTiling==1)
-   {
-      info->textureOffset = ((ctx->shared.fbSize - info->textureSize) / 
-			(width_bytes * 16)) * (width_bytes*16);
-   }
-   else
-   {
-      info->textureOffset = ((ctx->shared.fbSize - info->textureSize +
-   	 		   RADEON_BUFFER_ALIGN) &
-			  ~RADEON_BUFFER_ALIGN);
-   }
-   /* Reserve space for the shared depth
-    * buffer.
-    */
-   info->depthOffset = ((info->textureOffset - depthSize +
-			 RADEON_BUFFER_ALIGN) &
-			~RADEON_BUFFER_ALIGN);
-   info->depthPitch = ctx->shared.virtualWidth;
-
-   info->backOffset = ((info->depthOffset - bufferSize +
-			RADEON_BUFFER_ALIGN) &
-		       ~RADEON_BUFFER_ALIGN);
-   info->backPitch = ctx->shared.virtualWidth;
-
-
-   fprintf(stderr, 
-	   "Will use back buffer at offset 0x%x\n",
-	   info->backOffset);
-   fprintf(stderr, 
-	   "Will use depth buffer at offset 0x%x\n",
-	   info->depthOffset);
-   fprintf(stderr, 
-	   "Will use %d kb for textures at offset 0x%x\n",
-	   info->textureSize/1024, info->textureOffset);
-
-   info->frontPitchOffset = (((info->frontPitch * cpp / 64) << 22) |
-			     (info->frontOffset >> 10));
-
-   info->backPitchOffset = (((info->backPitch * cpp / 64) << 22) |
-			    (info->backOffset >> 10));
-
-   info->depthPitchOffset = (((info->depthPitch * cpp / 64) << 22) |
-			     (info->depthOffset >> 10));
-
-   return 1;
-}
-
-static int RADEONColorTilingInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
-{
-   int        width_bytes = ctx->shared.virtualWidth * ctx->cpp;
-   int        bufferSize  = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes			     + RADEON_BUFFER_ALIGN)
-			     & ~RADEON_BUFFER_ALIGN);
-   /* Setup color tiling */
-   if (info->drmMinor<14)
-      info->colorTiling=0;
-
-   if (info->colorTiling)
-   {
-
-      int colorTilingFlag;
-      drm_radeon_surface_alloc_t front,back;
-
-      RadeonSetParam(ctx, RADEON_SETPARAM_SWITCH_TILING, info->colorTiling ? 1 : 0);
-      
-      /* Setup the surfaces */
-      if (info->ChipFamily < CHIP_FAMILY_R200)
-         colorTilingFlag=RADEON_SURF_TILE_COLOR_MACRO;
-      else
-         colorTilingFlag=R200_SURF_TILE_COLOR_MACRO;
-
-      front.address = info->frontOffset;
-      front.size = bufferSize;
-      front.flags = (width_bytes) | colorTilingFlag;
-      drmCommandWrite(ctx->drmFD, DRM_RADEON_SURF_ALLOC, &front,sizeof(front)); 
- 
-      back.address = info->backOffset;
-      back.size = bufferSize;
-      back.flags = (width_bytes) | colorTilingFlag;
-      drmCommandWrite(ctx->drmFD, DRM_RADEON_SURF_ALLOC, &back,sizeof(back)); 
-
-   }
-   return 1;
-} 
-
-
-
-/**
- * Called at the start of each server generation.
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return non-zero on success, or zero on failure.
- *
- * Performs static frame buffer allocation. Opens the DRM device and add maps
- * to the SAREA, framebuffer and MMIO regions. Fills in \p info with more
- * information. Creates a \e server context to grab the lock for the
- * initialization ioctls and calls the other initilization functions in this
- * file. Starts the CP engine via the DRM_RADEON_CP_START command.
- *
- * Setups a RADEONDRIRec structure to be passed to radeon_dri.so for its
- * initialization.
- */
-static int RADEONScreenInit( DRIDriverContext *ctx, RADEONInfoPtr info )
-{
-   RADEONDRIPtr   pRADEONDRI;
-   int err;
-
-   usleep(100);
-   /*assert(!ctx->IsClient);*/
-
-   {
-      int  width_bytes = (ctx->shared.virtualWidth * ctx->cpp);
-      int  maxy        = ctx->shared.fbSize / width_bytes;
-
-
-      if (maxy <= ctx->shared.virtualHeight * 3) {
-	 fprintf(stderr, 
-		 "Static buffer allocation failed -- "
-		 "need at least %d kB video memory (have %d kB)\n",
-		 (ctx->shared.virtualWidth * ctx->shared.virtualHeight *
-		  ctx->cpp * 3 + 1023) / 1024,
-		 ctx->shared.fbSize / 1024);
-	 return 0;
-      } 
-   }
-
-
-   if (info->ChipFamily >= CHIP_FAMILY_R300) {
-      fprintf(stderr, 
-	      "Direct rendering not yet supported on "
-	      "Radeon 9700 and newer cards\n");
-      return 0;
-   }
-   
-   radeon_drm_page_size = getpagesize();   
-
-   info->registerSize = ctx->MMIOSize;
-   ctx->shared.SAREASize = SAREA_MAX;
-
-   /* Note that drmOpen will try to load the kernel module, if needed. */
-   ctx->drmFD = drmOpen("radeon", NULL );
-   if (ctx->drmFD < 0) {
-      fprintf(stderr, "[drm] drmOpen failed\n");
-      return 0;
-   }
-
-   if ((err = drmSetBusid(ctx->drmFD, ctx->pciBusID)) < 0) {
-      fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n",
-	      ctx->drmFD, ctx->pciBusID, strerror(-err));
-      return 0;
-   }
-
-   if (drmAddMap( ctx->drmFD,
-		  0,
-		  ctx->shared.SAREASize,
-		  DRM_SHM,
-		  DRM_CONTAINS_LOCK,
-		  &ctx->shared.hSAREA) < 0)
-   {
-      fprintf(stderr, "[drm] drmAddMap failed\n");
-      return 0;
-   }
-   fprintf(stderr, "[drm] added %d byte SAREA at 0x%08lx\n",
-	   ctx->shared.SAREASize, ctx->shared.hSAREA);
-
-   if (drmMap( ctx->drmFD,
-	       ctx->shared.hSAREA,
-	       ctx->shared.SAREASize,
-	       (drmAddressPtr)(&ctx->pSAREA)) < 0)
-   {
-      fprintf(stderr, "[drm] drmMap failed\n");
-      return 0;
-   }
-   memset(ctx->pSAREA, 0, ctx->shared.SAREASize);
-   fprintf(stderr, "[drm] mapped SAREA 0x%08lx to %p, size %d\n",
-	   ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize);
-   
-   /* Need to AddMap the framebuffer and mmio regions here:
-    */
-   if (drmAddMap( ctx->drmFD,
-		  (drm_handle_t)ctx->FBStart,
-		  ctx->FBSize,
-		  DRM_FRAME_BUFFER,
-#ifndef _EMBEDDED
-		  0,
-#else
-		  DRM_READ_ONLY,
-#endif
-		  &ctx->shared.hFrameBuffer) < 0)
-   {
-      fprintf(stderr, "[drm] drmAddMap framebuffer failed\n");
-      return 0;
-   }
-
-   fprintf(stderr, "[drm] framebuffer handle = 0x%08lx\n",
-	   ctx->shared.hFrameBuffer);
-
-
-
-   if (drmAddMap(ctx->drmFD, 
-		 ctx->MMIOStart,
-		 ctx->MMIOSize,
-		 DRM_REGISTERS, 
-		 DRM_READ_ONLY, 
-		 &info->registerHandle) < 0) {
-      fprintf(stderr, "[drm] drmAddMap mmio failed\n");	
-      return 0;
-   }
-   fprintf(stderr,
-	   "[drm] register handle = 0x%08lx\n", info->registerHandle);
-
-   /* Check the radeon DRM version */
-   if (!RADEONCheckDRMVersion(ctx, info)) {
-      return 0;
-   }
-
-   if (ctx->isPCI) {
-      /* Initialize PCI */
-      if (!RADEONDRIPciInit(ctx, info))
-         return 0;
-   }
-   else {
-      /* Initialize AGP */
-      if (!RADEONDRIAgpInit(ctx, info))
-         return 0;
-   }
-
-   /* Memory manager setup */
-   if (!RADEONMemoryInit(ctx, info)) {
-      return 0;
-   }
-
-   /* Create a 'server' context so we can grab the lock for
-    * initialization ioctls.
-    */
-   if ((err = drmCreateContext(ctx->drmFD, &ctx->serverContext)) != 0) {
-      fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err);
-      return 0;
-   }
-
-   DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0); 
-
-   /* Initialize the kernel data structures */
-   if (!RADEONDRIKernelInit(ctx, info)) {
-      fprintf(stderr, "RADEONDRIKernelInit failed\n");
-      DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext);
-      return 0;
-   }
-
-   /* Initialize the vertex buffers list */
-   if (!RADEONDRIBufInit(ctx, info)) {
-      fprintf(stderr, "RADEONDRIBufInit failed\n");
-      DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext);
-      return 0;
-   }
-
-   RADEONColorTilingInit(ctx, info);
-
-   /* Initialize IRQ */
-   RADEONDRIIrqInit(ctx, info);
-
-   /* Initialize kernel gart memory manager */
-   RADEONDRIAgpHeapInit(ctx, info);
-
-   fprintf(stderr,"color tiling %sabled\n", info->colorTiling?"en":"dis");
-   fprintf(stderr,"page flipping %sabled\n", info->page_flip_enable?"en":"dis");
-   /* Initialize the SAREA private data structure */
-   {
-      drm_radeon_sarea_t *pSAREAPriv;
-      pSAREAPriv = (drm_radeon_sarea_t *)(((char*)ctx->pSAREA) + 
-					sizeof(drm_sarea_t));
-      memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
-      pSAREAPriv->pfState = info->page_flip_enable;
-   }
-
-
-   /* Quick hack to clear the front & back buffers.  Could also use
-    * the clear ioctl to do this, but would need to setup hw state
-    * first.
-    */
-   drimemsetio((char *)ctx->FBAddress + info->frontOffset,
-	  0,
-	  info->frontPitch * ctx->cpp * ctx->shared.virtualHeight );
-
-   drimemsetio((char *)ctx->FBAddress + info->backOffset,
-	  0,
-	  info->backPitch * ctx->cpp * ctx->shared.virtualHeight );
-
-   /* This is the struct passed to radeon_dri.so for its initialization */
-   ctx->driverClientMsg = malloc(sizeof(RADEONDRIRec));
-   ctx->driverClientMsgSize = sizeof(RADEONDRIRec);
-   pRADEONDRI                    = (RADEONDRIPtr)ctx->driverClientMsg;
-   pRADEONDRI->deviceID          = info->Chipset;
-   pRADEONDRI->width             = ctx->shared.virtualWidth;
-   pRADEONDRI->height            = ctx->shared.virtualHeight;
-   pRADEONDRI->depth             = ctx->bpp; /* XXX: depth */
-   pRADEONDRI->bpp               = ctx->bpp;
-   pRADEONDRI->IsPCI             = ctx->isPCI;
-   pRADEONDRI->AGPMode           = ctx->agpmode;
-   pRADEONDRI->frontOffset       = info->frontOffset;
-   pRADEONDRI->frontPitch        = info->frontPitch;
-   pRADEONDRI->backOffset        = info->backOffset;
-   pRADEONDRI->backPitch         = info->backPitch;
-   pRADEONDRI->depthOffset       = info->depthOffset;
-   pRADEONDRI->depthPitch        = info->depthPitch;
-   pRADEONDRI->textureOffset     = info->textureOffset;
-   pRADEONDRI->textureSize       = info->textureSize;
-   pRADEONDRI->log2TexGran       = info->log2TexGran;
-   pRADEONDRI->registerHandle    = info->registerHandle;
-   pRADEONDRI->registerSize      = info->registerSize; 
-   pRADEONDRI->statusHandle      = info->ringReadPtrHandle;
-   pRADEONDRI->statusSize        = info->ringReadMapSize;
-   pRADEONDRI->gartTexHandle      = info->gartTexHandle;
-   pRADEONDRI->gartTexMapSize     = info->gartTexMapSize;
-   pRADEONDRI->log2GARTTexGran    = info->log2GARTTexGran;
-   pRADEONDRI->gartTexOffset      = info->gartTexStart;
-   pRADEONDRI->sarea_priv_offset = sizeof(drm_sarea_t);
-
-   /* Don't release the lock now - let the VT switch handler do it. */
-
-   return 1;
-}
-
-
-/**
- * \brief Get Radeon chip family from chipset number.
- * 
- * \param info driver private data.
- *
- * \return non-zero on success, or zero on failure.
- *
- * Called by radeonInitFBDev() to set RADEONInfoRec::ChipFamily
- * according to the value of RADEONInfoRec::Chipset.  Fails if the
- * chipset is unrecognized or not appropriate for this driver (i.e., not
- * an r100 style radeon)
- */
-static int get_chipfamily_from_chipset( RADEONInfoPtr info )
-{
-    switch (info->Chipset) {
-    case PCI_CHIP_RADEON_LY:
-    case PCI_CHIP_RADEON_LZ:
-	info->ChipFamily = CHIP_FAMILY_M6;
-	break;
-
-    case PCI_CHIP_RADEON_QY:
-    case PCI_CHIP_RADEON_QZ:
-	info->ChipFamily = CHIP_FAMILY_VE;
-	break;
-
-    case PCI_CHIP_R200_QL:
-    case PCI_CHIP_R200_QN:
-    case PCI_CHIP_R200_QO:
-    case PCI_CHIP_R200_Ql:
-    case PCI_CHIP_R200_BB:
-	info->ChipFamily = CHIP_FAMILY_R200;
-	break;
-
-    case PCI_CHIP_RV200_QW: /* RV200 desktop */
-    case PCI_CHIP_RV200_QX:
-	info->ChipFamily = CHIP_FAMILY_RV200;
-	break;
-
-    case PCI_CHIP_RADEON_LW:
-    case PCI_CHIP_RADEON_LX:
-	info->ChipFamily = CHIP_FAMILY_M7;
-	break;
-
-    case PCI_CHIP_RV250_Id:
-    case PCI_CHIP_RV250_Ie:
-    case PCI_CHIP_RV250_If:
-    case PCI_CHIP_RV250_Ig:
-	info->ChipFamily = CHIP_FAMILY_RV250;
-	break;
-
-    case PCI_CHIP_RV250_Ld:
-    case PCI_CHIP_RV250_Le:
-    case PCI_CHIP_RV250_Lf:
-    case PCI_CHIP_RV250_Lg:
-	info->ChipFamily = CHIP_FAMILY_M9;
-	break;
-
-    case PCI_CHIP_RV280_Y_:
-    case PCI_CHIP_RV280_Ya:
-    case PCI_CHIP_RV280_Yb:
-    case PCI_CHIP_RV280_Yc:
-	info->ChipFamily = CHIP_FAMILY_RV280;
-        break;
-
-    case PCI_CHIP_R300_ND:
-    case PCI_CHIP_R300_NE:
-    case PCI_CHIP_R300_NF:
-    case PCI_CHIP_R300_NG:
-	info->ChipFamily = CHIP_FAMILY_R300;
-        break;
-
-    default:
-	/* Original Radeon/7200 */
-	info->ChipFamily = CHIP_FAMILY_RADEON;
-    }
-
-    return 1;
-}
-
-
-/**
- * \brief Validate the fbdev mode.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Saves some registers and returns 1.
- *
- * \sa radeonValidateMode().
- */
-static int radeonValidateMode( const DRIDriverContext *ctx )
-{
-   unsigned char *RADEONMMIO = ctx->MMIOAddress;
-   RADEONInfoPtr info = ctx->driverPrivate;
-
-   info->gen_int_cntl = INREG(RADEON_GEN_INT_CNTL);
-   info->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL);
-
-   if (info->colorTiling)
-	   info->crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
-   return 1;
-}
-
-
-/**
- * \brief Examine mode returned by fbdev.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Restores registers that fbdev has clobbered and returns 1.
- *
- * \sa radeonValidateMode().
- */
-static int radeonPostValidateMode( const DRIDriverContext *ctx )
-{
-   unsigned char *RADEONMMIO = ctx->MMIOAddress;
-   RADEONInfoPtr info = ctx->driverPrivate;
-
-   RADEONColorTilingInit( ctx, info);
-   OUTREG(RADEON_GEN_INT_CNTL, info->gen_int_cntl);
-   if (info->colorTiling)
-	   info->crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
-   OUTREG(RADEON_CRTC_OFFSET_CNTL, info->crtc_offset_cntl);
-   
-   return 1;
-}
-
-
-/**
- * \brief Initialize the framebuffer device mode
- *
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Fills in \p info with some default values and some information from \p ctx
- * and then calls RADEONScreenInit() for the screen initialization.
- * 
- * Before exiting clears the framebuffer memory accessing it directly.
- */
-static int radeonInitFBDev( DRIDriverContext *ctx )
-{
-   RADEONInfoPtr info = calloc(1, sizeof(*info));
-
-   {
-      int  dummy = ctx->shared.virtualWidth;
-
-      if (ctx->colorTiling==1)
-      {
-         switch (ctx->bpp / 8) {
-         case 1: dummy = (ctx->shared.virtualWidth + 255) & ~255; break;
-         case 2: dummy = (ctx->shared.virtualWidth + 127) & ~127; break;
-         case 3:
-         case 4: dummy = (ctx->shared.virtualWidth +  63) &  ~63; break;
-         }
-      } else {
-	 switch (ctx->bpp / 8) {
-         case 1: dummy = (ctx->shared.virtualWidth + 127) & ~127; break;
-         case 2: dummy = (ctx->shared.virtualWidth +  31) &  ~31; break;
-         case 3:
-         case 4: dummy = (ctx->shared.virtualWidth +  15) &  ~15; break;
-         }
-      }
-
-      ctx->shared.virtualWidth = dummy;
-      ctx->shared.Width = dummy;
-   }
-
-   fprintf(stderr,"shared virtual width is %d\n", ctx->shared.virtualWidth);
-   ctx->driverPrivate = (void *)info;
-   
-   info->gartFastWrite  = RADEON_DEFAULT_AGP_FAST_WRITE;
-   info->gartSize       = RADEON_DEFAULT_AGP_SIZE;
-   info->gartTexSize    = RADEON_DEFAULT_AGP_TEX_SIZE;
-   info->bufSize       = RADEON_DEFAULT_BUFFER_SIZE;
-   info->ringSize      = RADEON_DEFAULT_RING_SIZE;
-   info->page_flip_enable = RADEON_DEFAULT_PAGE_FLIP;
-   info->colorTiling = ctx->colorTiling;
-  
-   info->Chipset = ctx->chipset;
-
-   if (!get_chipfamily_from_chipset( info )) {
-      fprintf(stderr, "Unknown or non-radeon chipset -- cannot continue\n");
-      fprintf(stderr, "==> Verify PCI BusID is correct in miniglx.conf\n");
-      return 0;
-   }
-
-   info->frontPitch = ctx->shared.virtualWidth;
-   info->LinearAddr = ctx->FBStart & 0xfc000000;
-    
-
-   if (!RADEONScreenInit( ctx, info ))
-      return 0;
-
-
-   return 1;
-}
-
-
-/**
- * \brief The screen is being closed, so clean up any state and free any
- * resources used by the DRI.
- *
- * \param ctx display handle.
- *
- * Unmaps the SAREA, closes the DRM device file descriptor and frees the driver
- * private data.
- */
-static void radeonHaltFBDev( DRIDriverContext *ctx )
-{
-    drmUnmap( ctx->pSAREA, ctx->shared.SAREASize );
-    drmClose(ctx->drmFD);
-
-    if (ctx->driverPrivate) {
-       free(ctx->driverPrivate);
-       ctx->driverPrivate = 0;
-    }
-}
-
-
-extern void radeonNotifyFocus( int );
-
-/**
- * \brief Exported driver interface for Mini GLX.
- *
- * \sa DRIDriverRec.
- */
-const struct DRIDriverRec __driDriver = {
-   radeonValidateMode,
-   radeonPostValidateMode,
-   radeonInitFBDev,
-   radeonHaltFBDev,
-   RADEONEngineShutdown,
-   RADEONEngineRestore,  
-#ifndef _EMBEDDED
-   0,
-#else
-   radeonNotifyFocus, 
-#endif
-};
diff --git a/src/mesa/drivers/dri/tdfx/server/tdfx_dri.c b/src/mesa/drivers/dri/tdfx/server/tdfx_dri.c
deleted file mode 100644
index 63fe875f59..0000000000
--- a/src/mesa/drivers/dri/tdfx/server/tdfx_dri.c
+++ /dev/null
@@ -1,471 +0,0 @@
-/*
- * Mesa 3-D graphics library
- * Version:  5.1
- *
- * Copyright (C) 1999-2003  Brian Paul   All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/* Authors:
- *    Keith Whitwell
- *    Daniel Borca
- */
-
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <errno.h>
-#include <unistd.h>
- 
-#include "driver.h"
-#include "drm.h"
-#include "imports.h"
-
-#include "dri_util.h"
-
-#include "tdfx_context.h"
-#include "tdfx_dri.h"
-#include "xf86drm.h"
-
-
-#define TILE_WIDTH 128
-#define TILE_HEIGHT 32
-
-#define CMDFIFO_PAGES 64
-
-
-static int
-calcBufferStride (int xres, int tiled, int cpp)
-{
-  int strideInTiles;
-
-  if (tiled) {
-    /* Calculate tile width stuff */
-    strideInTiles = (xres+TILE_WIDTH-1)/TILE_WIDTH;
-
-    return strideInTiles*cpp*TILE_WIDTH;
-  } else {
-    return xres*cpp;
-  }
-} /* calcBufferStride */
-
-
-static int
-calcBufferHeightInTiles (int yres)
-{
-  int heightInTiles;            /* Height of buffer in tiles */
-
-  /* Calculate tile height stuff */
-  heightInTiles = yres >> 5;
-
-  if (yres & (TILE_HEIGHT - 1))
-    heightInTiles++;
-
-  return heightInTiles;
-
-} /* calcBufferHeightInTiles */
-
-
-static int
-calcBufferSize (int xres, int yres, int tiled, int cpp)
-{
-  int stride, height, bufSize;
-
-  if (tiled) {
-    stride = calcBufferStride(xres, tiled, cpp);
-    height = TILE_HEIGHT * calcBufferHeightInTiles(yres);
-  } else {
-    stride = xres*cpp;
-    height = yres;
-  }
-
-  bufSize = stride * height;
-
-  return bufSize;
-} /* calcBufferSize */
-
-
-static void allocateMemory (const DRIDriverContext *ctx, TDFXDRIPtr pTDFX)
-{
-  int memRemaining, fifoSize, screenSizeInTiles;
-  int fbSize;
-  char *str;
-  int pixmapCacheLinesMin;
-  int cursorOffset, cursorSize;
-
-  pTDFX->stride = calcBufferStride(pTDFX->width, !0, pTDFX->cpp);
-
-  /* enough to do DVD */
-  pixmapCacheLinesMin = ((720*480*pTDFX->cpp) + 
-					pTDFX->stride - 1)/pTDFX->stride;
-
-  if (pTDFX->deviceID > PCI_CHIP_VOODOO3) {
-  	if ((pixmapCacheLinesMin + pTDFX->height) > 4095)
-		pixmapCacheLinesMin = 4095 - pTDFX->height;
-  } else {
-  	if ((pixmapCacheLinesMin + pTDFX->height) > 2047)
-		pixmapCacheLinesMin = 2047 - pTDFX->height;
-  }
-
-  if (pTDFX->cpp!=3) {
-    screenSizeInTiles=calcBufferSize(pTDFX->width, pTDFX->height,
-				     !0, pTDFX->cpp);
-  }
-  else {
-    /* cpp==3 needs to bump up to 4 */
-    screenSizeInTiles=calcBufferSize(pTDFX->width, pTDFX->height,
-				     !0, 4);
-  }
-
-  /*
-   * Layout is:
-   *    cursor, fifo, fb, tex, bb, db
-   */
-
-  fbSize = (pTDFX->height + pixmapCacheLinesMin) * pTDFX->stride;
-
-  memRemaining=(pTDFX->mem - 1) &~ 0xFFF;
-  /* Note that a page is 4096 bytes, and a  */
-  /* tile is 32 x 128 = 4096 bytes.  So,    */
-  /* page and tile boundaries are the same  */
-  /* Place the depth offset first, forcing  */
-  /* it to be on an *odd* page boundary.    */
-  pTDFX->depthOffset = (memRemaining - screenSizeInTiles) &~ 0xFFF;
-  if ((pTDFX->depthOffset & (0x1 << 12)) == 0) {
-      pTDFX->depthOffset -= (0x1 << 12);
-  }
-  /* Now, place the back buffer, forcing it */
-  /* to be on an *even* page boundary.      */
-  pTDFX->backOffset = (pTDFX->depthOffset - screenSizeInTiles) &~ 0xFFF;
-  if (pTDFX->backOffset & (0x1 << 12)) {
-      pTDFX->backOffset -= (0x1 << 12);
-  }
-  /* Give the cmd fifo at least             */
-  /* CMDFIFO_PAGES pages, but no more than  */
-  /* 64. NOTE: Don't go higher than 64, as  */
-  /* there is suspect code in Glide3 !      */
-  fifoSize = ((64 <= CMDFIFO_PAGES) ? 64 : CMDFIFO_PAGES) << 12;
-
-  /* We give 4096 bytes to the cursor  */
-  cursorSize = 0/*4096*/;
-  cursorOffset = 0;
-
-  pTDFX->fifoOffset = cursorOffset + cursorSize;
-  pTDFX->fifoSize = fifoSize;
-  /* Now, place the front buffer, forcing   */
-  /* it to be on a page boundary too, just  */
-  /* for giggles.                           */
-  pTDFX->fbOffset = pTDFX->fifoOffset + pTDFX->fifoSize;
-  pTDFX->textureOffset = pTDFX->fbOffset + fbSize;
-  if (pTDFX->depthOffset <= pTDFX->textureOffset ||
-	pTDFX->backOffset <= pTDFX->textureOffset) {
-    /*
-     * pTDFX->textureSize < 0 means that the DRI is disabled.  pTDFX->backOffset
-     * is used to calculate the maximum amount of memory available for
-     * 2D offscreen use.  With DRI disabled, set this to the top of memory.
-     */
-
-    pTDFX->textureSize = -1;
-    pTDFX->backOffset = pTDFX->mem;
-    pTDFX->depthOffset = -1;
-    fprintf(stderr, 
-        "Not enough video memory available for textures and depth buffer\n"
-	"\tand/or back buffer.  Disabling DRI.  To use DRI try lower\n"
-	"\tresolution modes and/or a smaller virtual screen size\n");
-  } else {
-    pTDFX->textureSize = pTDFX->backOffset - pTDFX->textureOffset;
-  }
-}
-
-
-static int createScreen (DRIDriverContext *ctx, TDFXDRIPtr pTDFX)
-{
-   int err;
-   
-   {
-      int  width_bytes = (ctx->shared.virtualWidth * ctx->cpp);
-      int  maxy        = ctx->shared.fbSize / width_bytes;
-
-
-      if (maxy <= ctx->shared.virtualHeight * 3) {
-	 fprintf(stderr, 
-		 "Static buffer allocation failed -- "
-		 "need at least %d kB video memory (have %d kB)\n",
-		 (ctx->shared.virtualWidth * ctx->shared.virtualHeight *
-		  ctx->cpp * 3 + 1023) / 1024,
-		 ctx->shared.fbSize / 1024);
-	 return 0;
-      } 
-   }
-
-   ctx->shared.SAREASize = SAREA_MAX;
-   pTDFX->regsSize = ctx->MMIOSize;
-
-   /* Note that drmOpen will try to load the kernel module, if needed. */
-   ctx->drmFD = drmOpen("tdfx", NULL );
-   if (ctx->drmFD < 0) {
-      fprintf(stderr, "[drm] drmOpen failed\n");
-      return 0;
-   }
-
-   if ((err = drmSetBusid(ctx->drmFD, ctx->pciBusID)) < 0) {
-      fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n",
-	      ctx->drmFD, ctx->pciBusID, strerror(-err));
-      return 0;
-   }
-
-   if (drmAddMap( ctx->drmFD,
-		  0,
-		  ctx->shared.SAREASize,
-		  DRM_SHM,
-		  DRM_CONTAINS_LOCK,
-		  &ctx->shared.hSAREA) < 0)
-   {
-      fprintf(stderr, "[drm] drmAddMap failed\n");
-      return 0;
-   }
-   fprintf(stderr, "[drm] added %d byte SAREA at 0x%08lx\n",
-	   ctx->shared.SAREASize, ctx->shared.hSAREA);
-
-   if (drmMap( ctx->drmFD,
-	       ctx->shared.hSAREA,
-	       ctx->shared.SAREASize,
-	       (drmAddressPtr)(&ctx->pSAREA)) < 0)
-   {
-      fprintf(stderr, "[drm] drmMap failed\n");
-      return 0;
-   }
-   memset(ctx->pSAREA, 0, ctx->shared.SAREASize);
-   fprintf(stderr, "[drm] mapped SAREA 0x%08lx to %p, size %d\n",
-	   ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize);
-   
-   /* Need to AddMap the framebuffer and mmio regions here:
-    */
-   if (drmAddMap( ctx->drmFD,
-		  (drm_handle_t)ctx->FBStart,
-		  ctx->FBSize,
-		  DRM_FRAME_BUFFER,
-#ifndef _EMBEDDED
-		  0,
-#else
-		  DRM_READ_ONLY,
-#endif
-		  &ctx->shared.hFrameBuffer) < 0)
-   {
-      fprintf(stderr, "[drm] drmAddMap framebuffer failed\n");
-      return 0;
-   }
-
-   fprintf(stderr, "[drm] framebuffer handle = 0x%08lx\n",
-	   ctx->shared.hFrameBuffer);
-
-
-   if (drmAddMap(ctx->drmFD, 
-		 ctx->MMIOStart,
-		 ctx->MMIOSize,
-		 DRM_REGISTERS, 
-		 DRM_READ_ONLY, 
-		 &pTDFX->regs) < 0) {
-      fprintf(stderr, "[drm] drmAddMap mmio failed\n");	
-      return 0;
-   }
-   fprintf(stderr,
-	   "[drm] register handle = 0x%08lx\n", pTDFX->regs);
-
-
-   /* Create a 'server' context so we can grab the lock for
-    * initialization ioctls.
-    */
-   if ((err = drmCreateContext(ctx->drmFD, &ctx->serverContext)) != 0) {
-      fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err);
-      return 0;
-   }
-
-   DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0); 
-
-   /* Initialize the kernel data structures */
-
-   /* Initialize kernel gart memory manager */
-   allocateMemory(ctx, pTDFX);
-
-   /* Initialize the SAREA private data structure */
-
-
-   /* Quick hack to clear the front & back buffers.  Could also use
-    * the clear ioctl to do this, but would need to setup hw state
-    * first.
-    */
-
-
-   /* This is the struct passed to tdfx_dri.so for its initialization */
-   ctx->driverClientMsg = malloc(sizeof(TDFXDRIRec));
-   ctx->driverClientMsgSize = sizeof(TDFXDRIRec);
-   memcpy(ctx->driverClientMsg, pTDFX, ctx->driverClientMsgSize);
-   pTDFX = (TDFXDRIPtr)ctx->driverClientMsg;
-
-   /* Don't release the lock now - let the VT switch handler do it. */
-
-   return 1;
-}
-
-
-/**
- * \brief Validate the fbdev mode.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Saves some registers and returns 1.
- *
- * \sa tdfxValidateMode().
- */
-static int tdfxValidateMode( const DRIDriverContext *ctx )
-{
-   return 1;
-}
-
-
-/**
- * \brief Examine mode returned by fbdev.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Restores registers that fbdev has clobbered and returns 1.
- *
- * \sa tdfxValidateMode().
- */
-static int tdfxPostValidateMode( const DRIDriverContext *ctx )
-{
-   return 1;
-}
-
-
-/**
- * \brief Initialize the framebuffer device mode
- *
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Before exiting clears the framebuffer memory accessing it directly.
- */
-static int tdfxInitFBDev( DRIDriverContext *ctx )
-{
-   TDFXDRIPtr pTDFX = calloc(1, sizeof(TDFXDRIRec));
-
-   {
-      int  dummy = ctx->shared.virtualWidth;
-
-      switch (ctx->bpp / 8) {
-      case 1: dummy = (ctx->shared.virtualWidth + 127) & ~127; break;
-      case 2: dummy = (ctx->shared.virtualWidth +  31) &  ~31; break;
-      case 3:
-      case 4: dummy = (ctx->shared.virtualWidth +  15) &  ~15; break;
-      }
-
-      ctx->shared.virtualWidth = dummy;
-   }
-
-   ctx->driverPrivate = (void *)pTDFX;
-
-   pTDFX->deviceID = ctx->chipset;
-   pTDFX->width    = ctx->shared.virtualWidth;
-   pTDFX->height   = ctx->shared.virtualHeight;
-   pTDFX->cpp      = ctx->cpp;
-   pTDFX->mem      = ctx->FBSize; /* ->shared.fbSize? mem probe? */
-   pTDFX->sarea_priv_offset = sizeof(drm_sarea_t);
-
-   if (!createScreen(ctx, pTDFX))
-      return 0;
-
-   return 1;
-}
-
-
-/**
- * \brief The screen is being closed, so clean up any state and free any
- * resources used by the DRI.
- *
- * \param ctx display handle.
- *
- * Unmaps the SAREA, closes the DRM device file descriptor and frees the driver
- * private data.
- */
-static void tdfxHaltFBDev( DRIDriverContext *ctx )
-{
-    drmUnmap( ctx->pSAREA, ctx->shared.SAREASize );
-    drmClose(ctx->drmFD);
-
-    if (ctx->driverPrivate) {
-       free(ctx->driverPrivate);
-       ctx->driverPrivate = 0;
-    }
-}
-
-
-/**
- * \brief Shutdown the drawing engine.
- *
- * \param ctx display handle
- *
- * Turns off the 3D engine & restores the graphics card
- * to a state that fbdev understands.
- */
-static int tdfxEngineShutdown( const DRIDriverContext *ctx )
-{
-   fprintf(stderr, "%s: not implemented\n", __FUNCTION__);
-   return 1;
-}
-
-
-/**
- * \brief Restore the drawing engine.
- *
- * \param ctx display handle
- *
- * Resets the graphics card and sets initial values for several registers of
- * the card's drawing engine.
- *
- * Turns on 3dfx
- */
-static int tdfxEngineRestore( const DRIDriverContext *ctx )
-{
-   fprintf(stderr, "%s: not implemented\n", __FUNCTION__);
-   return 1;
-}
-
-
-/**
- * \brief Exported driver interface for Mini GLX.
- *
- * \sa DRIDriverRec.
- */
-struct DRIDriverRec __driDriver = {
-   tdfxValidateMode,
-   tdfxPostValidateMode,
-   tdfxInitFBDev,
-   tdfxHaltFBDev,
-   tdfxEngineShutdown,
-   tdfxEngineRestore,
-   0
-};
diff --git a/src/mesa/drivers/dri/unichrome/server/via_dri.c b/src/mesa/drivers/dri/unichrome/server/via_dri.c
deleted file mode 100644
index 74034485e2..0000000000
--- a/src/mesa/drivers/dri/unichrome/server/via_dri.c
+++ /dev/null
@@ -1,1251 +0,0 @@
-/*
- * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
- * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sub license,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <errno.h>
-#include <unistd.h>
- 
-#include "driver.h"
-#include "drm.h"
-#include "imports.h"
-
-#include "dri_util.h"
-
-#include "via_context.h"
-#include "via_dri.h"
-#include "via_driver.h"
-#include "xf86drm.h"
-
-static void VIAEnableMMIO(DRIDriverContext * ctx);
-static void VIADisableMMIO(DRIDriverContext * ctx);
-static void VIADisableExtendedFIFO(DRIDriverContext *ctx);
-static void VIAEnableExtendedFIFO(DRIDriverContext *ctx);
-static void VIAInitialize2DEngine(DRIDriverContext *ctx);
-static void VIAInitialize3DEngine(DRIDriverContext *ctx);
-
-static int VIADRIScreenInit(DRIDriverContext * ctx);
-static void VIADRICloseScreen(DRIDriverContext * ctx);
-static int VIADRIFinishScreenInit(DRIDriverContext * ctx);
-
-/* _SOLO : missing macros normally defined by X code */
-#define xf86DrvMsg(a, b, ...) fprintf(stderr, __VA_ARGS__)
-#define MMIO_IN8(base, addr) ((*(((volatile uint8_t*)base)+(addr)))+0)
-#define MMIO_OUT8(base, addr, val) ((*(((volatile uint8_t*)base)+(addr)))=((uint8_t)val))
-#define MMIO_OUT16(base, addr, val) ((*(volatile uint16_t*)(((uint8_t*)base)+(addr)))=((uint16_t)val))
-
-#define VIDEO	0 
-#define AGP		1
-#define AGP_PAGE_SIZE 4096
-#define AGP_PAGES 8192
-#define AGP_SIZE (AGP_PAGE_SIZE * AGP_PAGES)
-#define AGP_CMDBUF_PAGES 512
-#define AGP_CMDBUF_SIZE (AGP_PAGE_SIZE * AGP_CMDBUF_PAGES)
-
-static char VIAKernelDriverName[] = "via";
-static char VIAClientDriverName[] = "unichrome";
-
-static int VIADRIAgpInit(const DRIDriverContext *ctx, VIAPtr pVia);
-static int VIADRIPciInit(DRIDriverContext * ctx, VIAPtr pVia);
-static int VIADRIFBInit(DRIDriverContext * ctx, VIAPtr pVia);
-static int VIADRIKernelInit(DRIDriverContext * ctx, VIAPtr pVia);
-static int VIADRIMapInit(DRIDriverContext * ctx, VIAPtr pVia);
-
-static void VIADRIIrqInit( DRIDriverContext *ctx )
-{
-    VIAPtr pVia = VIAPTR(ctx);
-    VIADRIPtr pVIADRI = pVia->devPrivate;
-
-    pVIADRI->irqEnabled = drmGetInterruptFromBusID(pVia->drmFD,
-					   ctx->pciBus,
-					   ctx->pciDevice,
-					   ctx->pciFunc);
-
-    if ((drmCtlInstHandler(pVia->drmFD, pVIADRI->irqEnabled))) {
-	xf86DrvMsg(pScreen->myNum, X_WARNING,
-		   "[drm] Failure adding irq handler. "
-		   "Falling back to irq-free operation.\n");
-	pVIADRI->irqEnabled = 0;
-    }
-
-    if (pVIADRI->irqEnabled)
-	xf86DrvMsg(pScreen->myNum, X_INFO,
-		   "[drm] Irq handler installed, using IRQ %d.\n",
-		   pVIADRI->irqEnabled);
-}
-
-static void VIADRIIrqExit( DRIDriverContext *ctx ) {
-    VIAPtr pVia = VIAPTR(ctx);
-    VIADRIPtr pVIADRI = pVia->devPrivate;
-
-    if (pVIADRI->irqEnabled) {
-	if (drmCtlUninstHandler(pVia->drmFD)) {
-	    xf86DrvMsg(pScreen-myNum, X_INFO,"[drm] Irq handler uninstalled.\n");
-	} else {
-	    xf86DrvMsg(pScreen->myNum, X_ERROR,
-		       "[drm] Could not uninstall irq handler.\n");
-	}
-    }
-}
-	    
-static void VIADRIRingBufferCleanup(DRIDriverContext *ctx)
-{
-    VIAPtr pVia = VIAPTR(ctx);
-    VIADRIPtr pVIADRI = pVia->devPrivate;
-    drm_via_dma_init_t ringBufInit;
-
-    if (pVIADRI->ringBufActive) {
-	xf86DrvMsg(pScreen->myNum, X_INFO, 
-		   "[drm] Cleaning up DMA ring-buffer.\n");
-	ringBufInit.func = VIA_CLEANUP_DMA;
-	if (drmCommandWrite(pVia->drmFD, DRM_VIA_DMA_INIT, &ringBufInit,
-			    sizeof(ringBufInit))) {
-	    xf86DrvMsg(pScreen->myNum, X_WARNING, 
-		       "[drm] Failed to clean up DMA ring-buffer: %d\n", errno);
-	}
-	pVIADRI->ringBufActive = 0;
-    }
-}
-
-static int VIADRIRingBufferInit(DRIDriverContext *ctx)
-{
-    VIAPtr pVia = VIAPTR(ctx);
-    VIADRIPtr pVIADRI = pVia->devPrivate;
-    drm_via_dma_init_t ringBufInit;
-    drmVersionPtr drmVer;
-
-    pVIADRI->ringBufActive = 0;
-
-    if (NULL == (drmVer = drmGetVersion(pVia->drmFD))) {
-	return GL_FALSE;
-    }
-
-    if (((drmVer->version_major <= 1) && (drmVer->version_minor <= 3))) {
-	return GL_FALSE;
-    } 
-
-    /*
-     * Info frome code-snippet on DRI-DEVEL list; Erdi Chen.
-     */
-
-    switch (pVia->ChipId) {
-    case PCI_CHIP_VT3259:
-    	ringBufInit.reg_pause_addr = 0x40c;
-	break;
-    default:
-    	ringBufInit.reg_pause_addr = 0x418;
-	break;
-    }
-   
-    ringBufInit.offset = pVia->agpSize;
-    ringBufInit.size = AGP_CMDBUF_SIZE;
-    ringBufInit.func = VIA_INIT_DMA;
-    if (drmCommandWrite(pVia->drmFD, DRM_VIA_DMA_INIT, &ringBufInit,
-			sizeof(ringBufInit))) {
-	xf86DrvMsg(pScreen->myNum, X_ERROR, 
-		   "[drm] Failed to initialize DMA ring-buffer: %d\n", errno);
-	return GL_FALSE;
-    }
-    xf86DrvMsg(pScreen->myNum, X_INFO, 
-	       "[drm] Initialized AGP ring-buffer, size 0x%lx at AGP offset 0x%lx.\n",
-	       ringBufInit.size, ringBufInit.offset);
-   
-    pVIADRI->ringBufActive = 1;
-    return GL_TRUE;
-}	    
-
-static int VIADRIAgpInit(const DRIDriverContext *ctx, VIAPtr pVia)
-{
-    unsigned long  agp_phys;
-    drmAddress agpaddr;
-    VIADRIPtr pVIADRI;
-    pVIADRI = pVia->devPrivate;
-    pVia->agpSize = 0;
-
-    if (drmAgpAcquire(pVia->drmFD) < 0) {
-        xf86DrvMsg(pScreen->myNum, X_ERROR, "[drm] drmAgpAcquire failed %d\n", errno);
-        return GL_FALSE;
-    }
-
-    if (drmAgpEnable(pVia->drmFD, drmAgpGetMode(pVia->drmFD)&~0x0) < 0) {
-         xf86DrvMsg(pScreen->myNum, X_ERROR, "[drm] drmAgpEnable failed\n");
-        return GL_FALSE;
-    }
-    
-    xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] drmAgpEnabled succeeded\n");
-
-    if (drmAgpAlloc(pVia->drmFD, AGP_SIZE, 0, &agp_phys, &pVia->agpHandle) < 0) {
-        xf86DrvMsg(pScreen->myNum, X_ERROR,
-                 "[drm] drmAgpAlloc failed\n");
-        drmAgpRelease(pVia->drmFD);
-        return GL_FALSE;
-    }
-   
-    if (drmAgpBind(pVia->drmFD, pVia->agpHandle, 0) < 0) {
-        xf86DrvMsg(pScreen->myNum, X_ERROR,
-                 "[drm] drmAgpBind failed\n");
-        drmAgpFree(pVia->drmFD, pVia->agpHandle);
-        drmAgpRelease(pVia->drmFD);
-
-        return GL_FALSE;
-    }
-
-    /*
-     * Place the ring-buffer last in the AGP region, and restrict the
-     * public map not to include the buffer for security reasons.
-     */
-
-    pVia->agpSize = AGP_SIZE - AGP_CMDBUF_SIZE;
-    pVia->agpAddr = drmAgpBase(pVia->drmFD);
-    xf86DrvMsg(pScreen->myNum, X_INFO,
-                 "[drm] agpAddr = 0x%08lx\n",pVia->agpAddr);
-		 
-    pVIADRI->agp.size = pVia->agpSize;
-    if (drmAddMap(pVia->drmFD, (drm_handle_t)0,
-                 pVIADRI->agp.size, DRM_AGP, 0, 
-                 &pVIADRI->agp.handle) < 0) {
-	xf86DrvMsg(pScreen->myNum, X_ERROR,
-	    "[drm] Failed to map public agp area\n");
-        pVIADRI->agp.size = 0;
-        return GL_FALSE;
-    }  
-    /* Map AGP from kernel to Xserver - Not really needed */
-    drmMap(pVia->drmFD, pVIADRI->agp.handle,pVIADRI->agp.size, &agpaddr);
-
-    xf86DrvMsg(pScreen->myNum, X_INFO, 
-                "[drm] agpAddr = 0x%08lx\n", pVia->agpAddr);
-    xf86DrvMsg(pScreen->myNum, X_INFO, 
-                "[drm] agpSize = 0x%08lx\n", pVia->agpSize);
-    xf86DrvMsg(pScreen->myNum, X_INFO, 
-                "[drm] agp physical addr = 0x%08lx\n", agp_phys);
-
-    {
-	drm_via_agp_t agp;
-	agp.offset = 0;
-	agp.size = AGP_SIZE-AGP_CMDBUF_SIZE;
-	if (drmCommandWrite(pVia->drmFD, DRM_VIA_AGP_INIT, &agp,
-			    sizeof(drm_via_agp_t)) < 0) {
-	    drmUnmap(&agpaddr,pVia->agpSize);
-	    drmRmMap(pVia->drmFD,pVIADRI->agp.handle);
-	    drmAgpUnbind(pVia->drmFD, pVia->agpHandle);
-	    drmAgpFree(pVia->drmFD, pVia->agpHandle);
-	    drmAgpRelease(pVia->drmFD);
-	    return GL_FALSE;
-	}
-    }
-
-    return GL_TRUE;
-}
-
-static int VIADRIFBInit(DRIDriverContext * ctx, VIAPtr pVia)
-{   
-    int FBSize = pVia->FBFreeEnd-pVia->FBFreeStart;
-    int FBOffset = pVia->FBFreeStart; 
-    VIADRIPtr pVIADRI = pVia->devPrivate;
-    pVIADRI->fbOffset = FBOffset;
-    pVIADRI->fbSize = pVia->videoRambytes;
-
-    {
-	drm_via_fb_t fb;
-	fb.offset = FBOffset;
-	fb.size = FBSize;
-	
-	if (drmCommandWrite(pVia->drmFD, DRM_VIA_FB_INIT, &fb,
-			    sizeof(drm_via_fb_t)) < 0) {
-	    xf86DrvMsg(pScreen->myNum, X_ERROR,
-		       "[drm] failed to init frame buffer area\n");
-	    return GL_FALSE;
-	} else {
-	    xf86DrvMsg(pScreen->myNum, X_INFO,
-		       "[drm] FBFreeStart= 0x%08x FBFreeEnd= 0x%08x "
-		       "FBSize= 0x%08x\n",
-		       pVia->FBFreeStart, pVia->FBFreeEnd, FBSize);
-	    return GL_TRUE;	
-	}   
-    }
-}
-
-static int VIADRIPciInit(DRIDriverContext * ctx, VIAPtr pVia)
-{
-    return GL_TRUE;	
-}
-
-static int VIADRIScreenInit(DRIDriverContext * ctx)
-{
-    VIAPtr pVia = VIAPTR(ctx);
-    VIADRIPtr pVIADRI;
-    int err;
-
-#if 0
-    ctx->shared.SAREASize = ((sizeof(drm_sarea_t) + 0xfff) & 0x1000);
-#else
-    if (sizeof(drm_sarea_t)+sizeof(drm_via_sarea_t) > SAREA_MAX) {
-	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
-			"Data does not fit in SAREA\n");
-	return GL_FALSE;
-    }
-    ctx->shared.SAREASize = SAREA_MAX;
-#endif
-
-    ctx->drmFD = drmOpen(VIAKernelDriverName, NULL);
-    if (ctx->drmFD < 0) {
-        fprintf(stderr, "[drm] drmOpen failed\n");
-        return 0;
-    }
-    pVia->drmFD = ctx->drmFD;
-
-    err = drmSetBusid(ctx->drmFD, ctx->pciBusID);
-    if (err < 0) {
-        fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n",
-                ctx->drmFD, ctx->pciBusID, strerror(-err));
-        return 0;
-    }
-
-    err = drmAddMap(ctx->drmFD, 0, ctx->shared.SAREASize, DRM_SHM,
-                  DRM_CONTAINS_LOCK, &ctx->shared.hSAREA);
-    if (err < 0) {
-        fprintf(stderr, "[drm] drmAddMap failed\n");
-        return 0;
-    }
-    fprintf(stderr, "[drm] added %d byte SAREA at 0x%08lx\n",
-            ctx->shared.SAREASize, ctx->shared.hSAREA);
-
-    if (drmMap(ctx->drmFD,
-               ctx->shared.hSAREA,
-               ctx->shared.SAREASize,
-               (drmAddressPtr)(&ctx->pSAREA)) < 0)
-    {
-        fprintf(stderr, "[drm] drmMap failed\n");
-        return 0;
-    }
-    memset(ctx->pSAREA, 0, ctx->shared.SAREASize);
-    fprintf(stderr, "[drm] mapped SAREA 0x%08lx to %p, size %d\n",
-            ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize);
-
-    /* Need to AddMap the framebuffer and mmio regions here:
-     */
-    if (drmAddMap(ctx->drmFD,
-                  (drm_handle_t)ctx->FBStart,
-                  ctx->FBSize,
-                  DRM_FRAME_BUFFER,
-#ifndef _EMBEDDED
-                   0,
-#else
-                   DRM_READ_ONLY,
-#endif
-                   &ctx->shared.hFrameBuffer) < 0)
-    {
-        fprintf(stderr, "[drm] drmAddMap framebuffer failed\n");
-        return 0;
-    }
-
-    fprintf(stderr, "[drm] framebuffer handle = 0x%08lx\n",
-            ctx->shared.hFrameBuffer);
-
-    pVIADRI = (VIADRIPtr) CALLOC(sizeof(VIADRIRec));
-    if (!pVIADRI) {
-        drmClose(ctx->drmFD);
-        return GL_FALSE;
-    }
-    pVia->devPrivate = pVIADRI;
-    ctx->driverClientMsg = pVIADRI;
-    ctx->driverClientMsgSize = sizeof(*pVIADRI);
-
-    /* DRIScreenInit doesn't add all the common mappings.  Add additional mappings here. */
-    if (!VIADRIMapInit(ctx, pVia)) {
-	VIADRICloseScreen(ctx);
-	return GL_FALSE;
-    }
-
-    pVIADRI->regs.size = VIA_MMIO_REGSIZE;
-    pVIADRI->regs.handle = pVia->registerHandle;
-    xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] mmio Registers = 0x%08lx\n",
-	pVIADRI->regs.handle);
-
-    if (drmMap(pVia->drmFD,
-               pVIADRI->regs.handle,
-               pVIADRI->regs.size,
-               (drmAddress *)&pVia->MapBase) != 0)
-    {
-        VIADRICloseScreen(ctx);
-        return GL_FALSE;
-    }
-
-    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] mmio mapped.\n" );
-
-    VIAEnableMMIO(ctx);
-
-    /* Get video memory clock. */
-    VGAOUT8(0x3D4, 0x3D);
-    pVia->MemClk = (VGAIN8(0x3D5) & 0xF0) >> 4;
-    xf86DrvMsg(0, X_INFO, "[dri] MemClk (0x%x)\n", pVia->MemClk);
-
-    /* 3D rendering has noise if not enabled. */
-    VIAEnableExtendedFIFO(ctx);
-
-    VIAInitialize2DEngine(ctx);
-
-    /* Must disable MMIO or 3D won't work. */
-    VIADisableMMIO(ctx);
-
-    VIAInitialize3DEngine(ctx);
-
-    pVia->IsPCI = !VIADRIAgpInit(ctx, pVia);
-
-    if (pVia->IsPCI) {
-        VIADRIPciInit(ctx, pVia);
-	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] use pci.\n" );
-    }
-    else
-        xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] use agp.\n" );
-
-    if (!(VIADRIFBInit(ctx, pVia))) {
-	VIADRICloseScreen(ctx);
-        xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "[dri] frame buffer initialize fail .\n" );
-        return GL_FALSE;
-    }
-    
-    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] frame buffer initialized.\n" );
- 
-    return VIADRIFinishScreenInit(ctx);
-}
-
-static void
-VIADRICloseScreen(DRIDriverContext * ctx)
-{
-    VIAPtr pVia = VIAPTR(ctx);
-    VIADRIPtr pVIADRI=(VIADRIPtr)pVia->devPrivate;
-
-    VIADRIRingBufferCleanup(ctx);
-
-    if (pVia->MapBase) {
-	xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] Unmapping MMIO registers\n");
-        drmUnmap(pVia->MapBase, pVIADRI->regs.size);
-    }
-
-    if (pVia->agpSize) {
-	xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] Freeing agp memory\n");
-        drmAgpFree(pVia->drmFD, pVia->agpHandle);
-	xf86DrvMsg(pScreen->myNum, X_INFO, "[drm] Releasing agp module\n");
-    	drmAgpRelease(pVia->drmFD);
-    }
-
-#if 0
-    if (pVia->DRIIrqEnable) 
-#endif
-        VIADRIIrqExit(ctx);
-}
-
-static int
-VIADRIFinishScreenInit(DRIDriverContext * ctx)
-{
-    VIAPtr pVia = VIAPTR(ctx);
-    VIADRIPtr pVIADRI;
-    int err;
-
-    err = drmCreateContext(ctx->drmFD, &ctx->serverContext);
-    if (err != 0) {
-        fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err);
-        return GL_FALSE;
-    }
-
-    DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0);
-
-
-    if (!VIADRIKernelInit(ctx, pVia)) {
-	VIADRICloseScreen(ctx);
-	return GL_FALSE;
-    }
-    xf86DrvMsg(pScreen->myNum, X_INFO, "[dri] kernel data initialized.\n");
-
-    /* set SAREA value */
-    {
-	drm_via_sarea_t *saPriv;
-
-	saPriv=(drm_via_sarea_t*)(((char*)ctx->pSAREA) +
-                               sizeof(drm_sarea_t));
-	assert(saPriv);
-	memset(saPriv, 0, sizeof(*saPriv));
-	saPriv->ctxOwner = -1;
-    }
-    pVIADRI=(VIADRIPtr)pVia->devPrivate;
-    pVIADRI->deviceID=pVia->Chipset;  
-    pVIADRI->width=ctx->shared.virtualWidth;
-    pVIADRI->height=ctx->shared.virtualHeight;
-    pVIADRI->mem=ctx->shared.fbSize;
-    pVIADRI->bytesPerPixel= (ctx->bpp+7) / 8; 
-    pVIADRI->sarea_priv_offset = sizeof(drm_sarea_t);
-    /* TODO */
-    pVIADRI->scrnX=pVIADRI->width;
-    pVIADRI->scrnY=pVIADRI->height;
-
-    /* Initialize IRQ */
-#if 0
-    if (pVia->DRIIrqEnable) 
-#endif
-	VIADRIIrqInit(ctx);
-    
-    pVIADRI->ringBufActive = 0;
-    VIADRIRingBufferInit(ctx);
-
-    return GL_TRUE;
-}
-
-/* Initialize the kernel data structures. */
-static int VIADRIKernelInit(DRIDriverContext * ctx, VIAPtr pVia)
-{
-    drm_via_init_t drmInfo;
-    memset(&drmInfo, 0, sizeof(drm_via_init_t));
-    drmInfo.sarea_priv_offset   = sizeof(drm_sarea_t);
-    drmInfo.func = VIA_INIT_MAP;
-    drmInfo.fb_offset           = pVia->FrameBufferBase;
-    drmInfo.mmio_offset         = pVia->registerHandle;
-    if (pVia->IsPCI)
-	drmInfo.agpAddr = (uint32_t)NULL;
-    else
-	drmInfo.agpAddr = (uint32_t)pVia->agpAddr;
-
-    if ((drmCommandWrite(pVia->drmFD, DRM_VIA_MAP_INIT,&drmInfo,
-			     sizeof(drm_via_init_t))) < 0)
-	    return GL_FALSE;
-
-    return GL_TRUE;
-}
-/* Add a map for the MMIO registers */
-static int VIADRIMapInit(DRIDriverContext * ctx, VIAPtr pVia)
-{
-    int flags = 0;
-
-    if (drmAddMap(pVia->drmFD, pVia->MmioBase, VIA_MMIO_REGSIZE,
-		  DRM_REGISTERS, flags, &pVia->registerHandle) < 0) {
-	return GL_FALSE;
-    }
-
-    xf86DrvMsg(pScreen->myNum, X_INFO,
-	"[drm] register handle = 0x%08lx\n", pVia->registerHandle);
-
-    return GL_TRUE;
-}
-
-static int viaValidateMode(const DRIDriverContext *ctx)
-{
-    VIAPtr pVia = VIAPTR(ctx);
-
-    return 1;
-}
-
-static int viaPostValidateMode(const DRIDriverContext *ctx)
-{
-    VIAPtr pVia = VIAPTR(ctx);
-
-    return 1;
-}
-
-static void VIAEnableMMIO(DRIDriverContext * ctx)
-{
-    /*vgaHWPtr hwp = VGAHWPTR(ctx);*/
-    VIAPtr pVia = VIAPTR(ctx);
-    unsigned char val;
-
-#if 0
-    if (xf86IsPrimaryPci(pVia->PciInfo)) {
-        /* If we are primary card, we still use std vga port. If we use
-         * MMIO, system will hang in vgaHWSave when our card used in
-         * PLE and KLE (integrated Trident MVP4)
-         */
-        vgaHWSetStdFuncs(hwp);
-    }
-    else {
-        vgaHWSetMmioFuncs(hwp, pVia->MapBase, 0x8000);
-    }
-#endif
-
-    val = VGAIN8(0x3c3);
-    VGAOUT8(0x3c3, val | 0x01);
-    val = VGAIN8(0x3cc);
-    VGAOUT8(0x3c2, val | 0x01);
-
-    /* Unlock Extended IO Space */
-    VGAOUT8(0x3c4, 0x10);
-    VGAOUT8(0x3c5, 0x01);
-
-    /* Enable MMIO */
-    if(!pVia->IsSecondary) {
-	VGAOUT8(0x3c4, 0x1a);
-	val = VGAIN8(0x3c5);
-#ifdef DEBUG
-	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "primary val = %x\n", val);
-#endif
-	VGAOUT8(0x3c5, val | 0x68);
-    }
-    else {
-	VGAOUT8(0x3c4, 0x1a);
-	val = VGAIN8(0x3c5);
-#ifdef DEBUG
-	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "secondary val = %x\n", val);
-#endif
-	VGAOUT8(0x3c5, val | 0x38);
-    }
-
-    /* Unlock CRTC registers */
-    VGAOUT8(0x3d4, 0x47);
-    VGAOUT8(0x3d5, 0x00);
-
-    return;
-}
-
-static void VIADisableMMIO(DRIDriverContext * ctx)
-{
-    VIAPtr pVia = VIAPTR(ctx);
-    unsigned char val;
-
-    VGAOUT8(0x3c4, 0x1a);
-    val = VGAIN8(0x3c5);
-    VGAOUT8(0x3c5, val & 0x97);
-
-    return;
-}
-
-static void VIADisableExtendedFIFO(DRIDriverContext *ctx)
-{
-    VIAPtr  pVia = VIAPTR(ctx);
-    uint32_t  dwGE230, dwGE298;
-
-    /* Cause of exit XWindow will dump back register value, others chipset no
-     * need to set extended fifo value */
-    if (pVia->Chipset == VIA_CLE266 && pVia->ChipRev < 15 &&
-        (ctx->shared.virtualWidth > 1024 || pVia->HasSecondary)) {
-        /* Turn off Extend FIFO */
-        /* 0x298[29] */
-        dwGE298 = VIAGETREG(0x298);
-        VIASETREG(0x298, dwGE298 | 0x20000000);
-        /* 0x230[21] */
-        dwGE230 = VIAGETREG(0x230);
-        VIASETREG(0x230, dwGE230 & ~0x00200000);
-        /* 0x298[29] */
-        dwGE298 = VIAGETREG(0x298);
-        VIASETREG(0x298, dwGE298 & ~0x20000000);
-    }
-}
-
-static void VIAEnableExtendedFIFO(DRIDriverContext *ctx)
-{
-    VIAPtr  pVia = VIAPTR(ctx);
-    uint8_t   bRegTemp;
-    uint32_t  dwGE230, dwGE298;
-
-    switch (pVia->Chipset) {
-    case VIA_CLE266:
-        if (pVia->ChipRev > 14) {  /* For 3123Cx */
-            if (pVia->HasSecondary) {  /* SAMM or DuoView case */
-                if (ctx->shared.virtualWidth >= 1024)
-    	        {
-    	            /* 3c5.16[0:5] */
-        	        VGAOUT8(0x3C4, 0x16);
-            	    bRegTemp = VGAIN8(0x3C5);
-    	            bRegTemp &= ~0x3F;
-        	        bRegTemp |= 0x1C;
-            	    VGAOUT8(0x3C5, bRegTemp);
-        	        /* 3c5.17[0:6] */
-            	    VGAOUT8(0x3C4, 0x17);
-                	bRegTemp = VGAIN8(0x3C5);
-    	            bRegTemp &= ~0x7F;
-        	        bRegTemp |= 0x3F;
-            	    VGAOUT8(0x3C5, bRegTemp);
-            	    pVia->EnableExtendedFIFO = GL_TRUE;
-    	        }
-            }
-            else   /* Single view or Simultaneoue case */
-            {
-                if (ctx->shared.virtualWidth > 1024)
-    	        {
-    	            /* 3c5.16[0:5] */
-        	        VGAOUT8(0x3C4, 0x16);
-            	    bRegTemp = VGAIN8(0x3C5);
-    	            bRegTemp &= ~0x3F;
-        	        bRegTemp |= 0x17;
-            	    VGAOUT8(0x3C5, bRegTemp);
-        	        /* 3c5.17[0:6] */
-            	    VGAOUT8(0x3C4, 0x17);
-                	bRegTemp = VGAIN8(0x3C5);
-    	            bRegTemp &= ~0x7F;
-        	        bRegTemp |= 0x2F;
-            	    VGAOUT8(0x3C5, bRegTemp);
-            	    pVia->EnableExtendedFIFO = GL_TRUE;
-    	        }
-            }
-            /* 3c5.18[0:5] */
-            VGAOUT8(0x3C4, 0x18);
-            bRegTemp = VGAIN8(0x3C5);
-            bRegTemp &= ~0x3F;
-            bRegTemp |= 0x17;
-            bRegTemp |= 0x40;  /* force the preq always higher than treq */
-            VGAOUT8(0x3C5, bRegTemp);
-        }
-        else {      /* for 3123Ax */
-            if (ctx->shared.virtualWidth > 1024 || pVia->HasSecondary) {
-                /* Turn on Extend FIFO */
-                /* 0x298[29] */
-                dwGE298 = VIAGETREG(0x298);
-                VIASETREG(0x298, dwGE298 | 0x20000000);
-                /* 0x230[21] */
-                dwGE230 = VIAGETREG(0x230);
-                VIASETREG(0x230, dwGE230 | 0x00200000);
-                /* 0x298[29] */
-                dwGE298 = VIAGETREG(0x298);
-                VIASETREG(0x298, dwGE298 & ~0x20000000);
-
-                /* 3c5.16[0:5] */
-                VGAOUT8(0x3C4, 0x16);
-                bRegTemp = VGAIN8(0x3C5);
-                bRegTemp &= ~0x3F;
-                bRegTemp |= 0x17;
-                /* bRegTemp |= 0x10; */
-                VGAOUT8(0x3C5, bRegTemp);
-                /* 3c5.17[0:6] */
-                VGAOUT8(0x3C4, 0x17);
-                bRegTemp = VGAIN8(0x3C5);
-                bRegTemp &= ~0x7F;
-                bRegTemp |= 0x2F;
-                /*bRegTemp |= 0x1F;*/
-                VGAOUT8(0x3C5, bRegTemp);
-                /* 3c5.18[0:5] */
-                VGAOUT8(0x3C4, 0x18);
-                bRegTemp = VGAIN8(0x3C5);
-                bRegTemp &= ~0x3F;
-                bRegTemp |= 0x17;
-                bRegTemp |= 0x40;  /* force the preq always higher than treq */
-                VGAOUT8(0x3C5, bRegTemp);
-          	    pVia->EnableExtendedFIFO = GL_TRUE;
-            }
-        }
-        break;
-    case VIA_KM400:
-        if (pVia->HasSecondary) {  /* SAMM or DuoView case */
-            if ((ctx->shared.virtualWidth >= 1600) &&
-                (pVia->MemClk <= VIA_MEM_DDR200)) {
-        	    /* enable CRT extendded FIFO */
-            	VGAOUT8(0x3C4, 0x17);
-                VGAOUT8(0x3C5, 0x1C);
-    	        /* revise second display queue depth and read threshold */
-        	    VGAOUT8(0x3C4, 0x16);
-            	bRegTemp = VGAIN8(0x3C5);
-    	        bRegTemp &= ~0x3F;
-    	        bRegTemp = (bRegTemp) | (0x09);
-                VGAOUT8(0x3C5, bRegTemp);
-            }
-            else {
-                /* enable CRT extendded FIFO */
-                VGAOUT8(0x3C4, 0x17);
-                VGAOUT8(0x3C5,0x3F);
-                /* revise second display queue depth and read threshold */
-                VGAOUT8(0x3C4, 0x16);
-                bRegTemp = VGAIN8(0x3C5);
-                bRegTemp &= ~0x3F;
-                bRegTemp = (bRegTemp) | (0x1C);
-                VGAOUT8(0x3C5, bRegTemp);
-            }
-            /* 3c5.18[0:5] */
-            VGAOUT8(0x3C4, 0x18);
-            bRegTemp = VGAIN8(0x3C5);
-            bRegTemp &= ~0x3F;
-            bRegTemp |= 0x17;
-            bRegTemp |= 0x40;  /* force the preq always higher than treq */
-            VGAOUT8(0x3C5, bRegTemp);
-       	    pVia->EnableExtendedFIFO = GL_TRUE;
-        }
-        else {
-            if ( (ctx->shared.virtualWidth > 1024) && (ctx->shared.virtualWidth <= 1280) )
-            {
-                /* enable CRT extendded FIFO */
-                VGAOUT8(0x3C4, 0x17);
-                VGAOUT8(0x3C5, 0x3F);
-                /* revise second display queue depth and read threshold */
-                VGAOUT8(0x3C4, 0x16);
-                bRegTemp = VGAIN8(0x3C5);
-                bRegTemp &= ~0x3F;
-                bRegTemp = (bRegTemp) | (0x17);
-                VGAOUT8(0x3C5, bRegTemp);
-           	    pVia->EnableExtendedFIFO = GL_TRUE;
-            }
-            else if ((ctx->shared.virtualWidth > 1280))
-            {
-                /* enable CRT extendded FIFO */
-                VGAOUT8(0x3C4, 0x17);
-                VGAOUT8(0x3C5, 0x3F);
-                /* revise second display queue depth and read threshold */
-                VGAOUT8(0x3C4, 0x16);
-                bRegTemp = VGAIN8(0x3C5);
-                bRegTemp &= ~0x3F;
-                bRegTemp = (bRegTemp) | (0x1C);
-                VGAOUT8(0x3C5, bRegTemp);
-           	    pVia->EnableExtendedFIFO = GL_TRUE;
-            }
-            else
-            {
-                /* enable CRT extendded FIFO */
-                VGAOUT8(0x3C4, 0x17);
-                VGAOUT8(0x3C5, 0x3F);
-                /* revise second display queue depth and read threshold */
-                VGAOUT8(0x3C4, 0x16);
-                bRegTemp = VGAIN8(0x3C5);
-                bRegTemp &= ~0x3F;
-                bRegTemp = (bRegTemp) | (0x10);
-                VGAOUT8(0x3C5, bRegTemp);
-            }
-            /* 3c5.18[0:5] */
-            VGAOUT8(0x3C4, 0x18);
-            bRegTemp = VGAIN8(0x3C5);
-            bRegTemp &= ~0x3F;
-            bRegTemp |= 0x17;
-            bRegTemp |= 0x40;  /* force the preq always higher than treq */
-            VGAOUT8(0x3C5, bRegTemp);
-        }
-        break;
-    case VIA_K8M800:
-        /*=* R1 Display FIFO depth (384 /8 -1 -> 0xbf) SR17[7:0] (8bits) *=*/
-        VGAOUT8(0x3c4, 0x17);
-        VGAOUT8(0x3c5, 0xbf);
-
-        /*=* R2 Display fetch datum threshold value (328/4 -> 0x52)
-             SR16[5:0], SR16[7] (7bits) *=*/
-        VGAOUT8(0x3c4, 0x16);
-        bRegTemp = VGAIN8(0x3c5) & ~0xBF;
-        bRegTemp |= (0x52 & 0x3F);
-        bRegTemp |= ((0x52 & 0x40) << 1);
-        VGAOUT8(0x3c5, bRegTemp);
-
-        /*=* R3 Switch to the highest agent threshold value (74 -> 0x4a)
-             SR18[5:0], SR18[7] (7bits) *=*/
-        VGAOUT8(0x3c4, 0x18);
-        bRegTemp = VGAIN8(0x3c5) & ~0xBF;
-        bRegTemp |= (0x4a & 0x3F);
-        bRegTemp |= ((0x4a & 0x40) << 1);
-        VGAOUT8(0x3c5, bRegTemp);
-#if 0
-        /*=* R4 Fetch Number for a scan line (unit: 8 bytes)
-             SR1C[7:0], SR1D[1:0] (10bits) *=*/
-        wRegTemp = (pBIOSInfo->offsetWidthByQWord >> 1) + 4;
-        VGAOUT8(0x3c4, 0x1c);
-        VGAOUT8(0x3c5, (uint8_t)(wRegTemp & 0xFF));
-        VGAOUT8(0x3c4, 0x1d);
-        bRegTemp = VGAIN8(0x3c5) & ~0x03;
-        VGAOUT8(0x3c5, bRegTemp | ((wRegTemp & 0x300) >> 8));
-#endif
-        if (ctx->shared.virtualWidth >= 1400 && ctx->bpp == 32)
-        {
-            /*=* Max. length for a request SR22[4:0] (64/4 -> 0x10) *=*/
-            VGAOUT8(0x3c4, 0x22);
-            bRegTemp = VGAIN8(0x3c5) & ~0x1F;
-            VGAOUT8(0x3c5, bRegTemp | 0x10);
-        }
-        else
-        {
-            /*=* Max. length for a request SR22[4:0]
-                 (128/4 -> over flow 0x0) *=*/
-            VGAOUT8(0x3c4, 0x22);
-            bRegTemp = VGAIN8(0x3c5) & ~0x1F;
-            VGAOUT8(0x3c5, bRegTemp);
-        }
-        break;
-    case VIA_PM800:
-        /*=* R1 Display FIFO depth (96-1 -> 0x5f) SR17[7:0] (8bits) *=*/
-        VGAOUT8(0x3c4, 0x17);
-        VGAOUT8(0x3c5, 0x5f);
-
-        /*=* R2 Display fetch datum threshold value (32 -> 0x20)
-             SR16[5:0], SR16[7] (7bits) *=*/
-        VGAOUT8(0x3c4, 0x16);
-        bRegTemp = VGAIN8(0x3c5) & ~0xBF;
-        bRegTemp |= (0x20 & 0x3F);
-        bRegTemp |= ((0x20 & 0x40) << 1);
-        VGAOUT8(0x3c5, bRegTemp);
-
-        /*=* R3 Switch to the highest agent threshold value (16 -> 0x10)
-             SR18[5:0], SR18[7] (7bits) *=*/
-        VGAOUT8(0x3c4, 0x18);
-        bRegTemp = VGAIN8(0x3c5) & ~0xBF;
-        bRegTemp |= (0x10 & 0x3F);
-        bRegTemp |= ((0x10 & 0x40) << 1);
-        VGAOUT8(0x3c5, bRegTemp);
-#if 0
-        /*=* R4 Fetch Number for a scan line (unit: 8 bytes)
-             SR1C[7:0], SR1D[1:0] (10bits) *=*/
-        wRegTemp = (pBIOSInfo->offsetWidthByQWord >> 1) + 4;
-        VGAOUT8(0x3c4, 0x1c);
-        VGAOUT8(0x3c5, (uint8_t)(wRegTemp & 0xFF));
-        VGAOUT8(0x3c4, 0x1d);
-        bRegTemp = VGAIN8(0x3c5) & ~0x03;
-        VGAOUT8(0x3c5, bRegTemp | ((wRegTemp & 0x300) >> 8));
-#endif
-        if (ctx->shared.virtualWidth >= 1400 && ctx->bpp == 32)
-        {
-            /*=* Max. length for a request SR22[4:0] (64/4 -> 0x10) *=*/
-            VGAOUT8(0x3c4, 0x22);
-            bRegTemp = VGAIN8(0x3c5) & ~0x1F;
-            VGAOUT8(0x3c5, bRegTemp | 0x10);
-        }
-        else
-        {
-            /*=* Max. length for a request SR22[4:0] (0x1F) *=*/
-            VGAOUT8(0x3c4, 0x22);
-            bRegTemp = VGAIN8(0x3c5) & ~0x1F;
-            VGAOUT8(0x3c5, bRegTemp | 0x1F);
-        }
-        break;
-    default:
-        break;
-    }
-}
-
-static void VIAInitialize2DEngine(DRIDriverContext *ctx)
-{
-    VIAPtr  pVia = VIAPTR(ctx);
-    uint32_t  dwVQStartAddr, dwVQEndAddr;
-    uint32_t  dwVQLen, dwVQStartL, dwVQEndL, dwVQStartEndH;
-    uint32_t  dwGEMode;
-
-    /* init 2D engine regs to reset 2D engine */
-    VIASETREG(0x04, 0x0);
-    VIASETREG(0x08, 0x0);
-    VIASETREG(0x0c, 0x0);
-    VIASETREG(0x10, 0x0);
-    VIASETREG(0x14, 0x0);
-    VIASETREG(0x18, 0x0);
-    VIASETREG(0x1c, 0x0);
-    VIASETREG(0x20, 0x0);
-    VIASETREG(0x24, 0x0);
-    VIASETREG(0x28, 0x0);
-    VIASETREG(0x2c, 0x0);
-    VIASETREG(0x30, 0x0);
-    VIASETREG(0x34, 0x0);
-    VIASETREG(0x38, 0x0);
-    VIASETREG(0x3c, 0x0);
-    VIASETREG(0x40, 0x0);
-
-    VIADisableMMIO(ctx);
-
-    /* Init AGP and VQ regs */
-    VIASETREG(0x43c, 0x00100000);
-    VIASETREG(0x440, 0x00000000);
-    VIASETREG(0x440, 0x00333004);
-    VIASETREG(0x440, 0x60000000);
-    VIASETREG(0x440, 0x61000000);
-    VIASETREG(0x440, 0x62000000);
-    VIASETREG(0x440, 0x63000000);
-    VIASETREG(0x440, 0x64000000);
-    VIASETREG(0x440, 0x7D000000);
-
-    VIASETREG(0x43c, 0xfe020000);
-    VIASETREG(0x440, 0x00000000);
-
-    if (pVia->VQStart != 0) {
-        /* Enable VQ */
-        dwVQStartAddr = pVia->VQStart;
-        dwVQEndAddr = pVia->VQEnd;
-        dwVQStartL = 0x50000000 | (dwVQStartAddr & 0xFFFFFF);
-        dwVQEndL = 0x51000000 | (dwVQEndAddr & 0xFFFFFF);
-        dwVQStartEndH = 0x52000000 | ((dwVQStartAddr & 0xFF000000) >> 24) |
-                        ((dwVQEndAddr & 0xFF000000) >> 16);
-        dwVQLen = 0x53000000 | (VIA_VQ_SIZE >> 3);
-
-        VIASETREG(0x43c, 0x00fe0000);
-        VIASETREG(0x440, 0x080003fe);
-        VIASETREG(0x440, 0x0a00027c);
-        VIASETREG(0x440, 0x0b000260);
-        VIASETREG(0x440, 0x0c000274);
-        VIASETREG(0x440, 0x0d000264);
-        VIASETREG(0x440, 0x0e000000);
-        VIASETREG(0x440, 0x0f000020);
-        VIASETREG(0x440, 0x1000027e);
-        VIASETREG(0x440, 0x110002fe);
-        VIASETREG(0x440, 0x200f0060);
-
-        VIASETREG(0x440, 0x00000006);
-        VIASETREG(0x440, 0x40008c0f);
-        VIASETREG(0x440, 0x44000000);
-        VIASETREG(0x440, 0x45080c04);
-        VIASETREG(0x440, 0x46800408);
-
-        VIASETREG(0x440, dwVQStartEndH);
-        VIASETREG(0x440, dwVQStartL);
-        VIASETREG(0x440, dwVQEndL);
-        VIASETREG(0x440, dwVQLen);
-    }
-    else {
-        /* Diable VQ */
-        VIASETREG(0x43c, 0x00fe0000);
-        VIASETREG(0x440, 0x00000004);
-        VIASETREG(0x440, 0x40008c0f);
-        VIASETREG(0x440, 0x44000000);
-        VIASETREG(0x440, 0x45080c04);
-        VIASETREG(0x440, 0x46800408);
-    }
-
-    dwGEMode = 0;
-
-    switch (ctx->bpp) {
-    case 16:
-        dwGEMode |= VIA_GEM_16bpp;
-        break;
-    case 32:
-        dwGEMode |= VIA_GEM_32bpp;
-        break;
-    default:
-        dwGEMode |= VIA_GEM_8bpp;
-        break;
-    }
-
-#if 0
-    switch (ctx->shared.virtualWidth) {
-    case 800:
-        dwGEMode |= VIA_GEM_800;
-        break;
-    case 1024:
-        dwGEMode |= VIA_GEM_1024;
-        break;
-    case 1280:
-        dwGEMode |= VIA_GEM_1280;
-        break;
-    case 1600:
-        dwGEMode |= VIA_GEM_1600;
-        break;
-    case 2048:
-        dwGEMode |= VIA_GEM_2048;
-        break;
-    default:
-        dwGEMode |= VIA_GEM_640;
-        break;
-    }
-#endif
-    
-    VIAEnableMMIO(ctx);
-
-    /* Set BPP and Pitch */
-    VIASETREG(VIA_REG_GEMODE, dwGEMode);
-
-    /* Set Src and Dst base address and pitch, pitch is qword */
-    VIASETREG(VIA_REG_SRCBASE, 0x0);
-    VIASETREG(VIA_REG_DSTBASE, 0x0);
-    VIASETREG(VIA_REG_PITCH, VIA_PITCH_ENABLE |
-              ((ctx->shared.virtualWidth * ctx->bpp >> 3) >> 3) |
-              (((ctx->shared.virtualWidth * ctx->bpp >> 3) >> 3) << 16));
-}
-
-static int b3DRegsInitialized = 0;
-
-static void VIAInitialize3DEngine(DRIDriverContext *ctx)
-{
-    VIAPtr  pVia = VIAPTR(ctx);
-    int i;
-
-    if (!b3DRegsInitialized)
-    {
-
-        VIASETREG(0x43C, 0x00010000);
-
-        for (i = 0; i <= 0x7D; i++)
-        {
-            VIASETREG(0x440, (uint32_t) i << 24);
-        }
-
-        VIASETREG(0x43C, 0x00020000);
-
-        for (i = 0; i <= 0x94; i++)
-        {
-            VIASETREG(0x440, (uint32_t) i << 24);
-        }
-
-        VIASETREG(0x440, 0x82400000);
-
-        VIASETREG(0x43C, 0x01020000);
-
-
-        for (i = 0; i <= 0x94; i++)
-        {
-            VIASETREG(0x440, (uint32_t) i << 24);
-        }
-
-        VIASETREG(0x440, 0x82400000);
-        VIASETREG(0x43C, 0xfe020000);
-
-        for (i = 0; i <= 0x03; i++)
-        {
-            VIASETREG(0x440, (uint32_t) i << 24);
-        }
-
-        VIASETREG(0x43C, 0x00030000);
-
-        for (i = 0; i <= 0xff; i++)
-        {
-            VIASETREG(0x440, 0);
-        }
-        VIASETREG(0x43C, 0x00100000);
-        VIASETREG(0x440, 0x00333004);
-        VIASETREG(0x440, 0x10000002);
-        VIASETREG(0x440, 0x60000000);
-        VIASETREG(0x440, 0x61000000);
-        VIASETREG(0x440, 0x62000000);
-        VIASETREG(0x440, 0x63000000);
-        VIASETREG(0x440, 0x64000000);
-
-        VIASETREG(0x43C, 0x00fe0000);
-
-        if (pVia->ChipRev >= 3 )
-            VIASETREG(0x440,0x40008c0f);
-        else
-            VIASETREG(0x440,0x4000800f);
-
-        VIASETREG(0x440,0x44000000);
-        VIASETREG(0x440,0x45080C04);
-        VIASETREG(0x440,0x46800408);
-        VIASETREG(0x440,0x50000000);
-        VIASETREG(0x440,0x51000000);
-        VIASETREG(0x440,0x52000000);
-        VIASETREG(0x440,0x53000000);
-
-        b3DRegsInitialized = 1;
-        xf86DrvMsg(pScrn->scrnIndex, X_INFO,
-                   "3D Engine has been initialized.\n");
-    }
-
-    VIASETREG(0x43C,0x00fe0000);
-    VIASETREG(0x440,0x08000001);
-    VIASETREG(0x440,0x0A000183);
-    VIASETREG(0x440,0x0B00019F);
-    VIASETREG(0x440,0x0C00018B);
-    VIASETREG(0x440,0x0D00019B);
-    VIASETREG(0x440,0x0E000000);
-    VIASETREG(0x440,0x0F000000);
-    VIASETREG(0x440,0x10000000);
-    VIASETREG(0x440,0x11000000);
-    VIASETREG(0x440,0x20000000);
-}
-
-static int
-WaitIdleCLE266(VIAPtr pVia)
-{
-    int loop = 0;
-
-    /*mem_barrier();*/
-
-    while (!(VIAGETREG(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && (loop++ < MAXLOOP))
-        ;
-
-    while ((VIAGETREG(VIA_REG_STATUS) &
-          (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY)) &&
-          (loop++ < MAXLOOP))
-        ;
-
-    return loop >= MAXLOOP;
-}
-
-static int viaInitFBDev(DRIDriverContext *ctx)
-{
-    VIAPtr pVia = CALLOC(sizeof(*pVia));
-
-    ctx->driverPrivate = (void *)pVia;
-
-    switch (ctx->chipset) {
-    case PCI_CHIP_CLE3122:
-    case PCI_CHIP_CLE3022:
-        pVia->Chipset = VIA_CLE266;
-        break;
-    case PCI_CHIP_VT7205:
-    case PCI_CHIP_VT3205:
-        pVia->Chipset = VIA_KM400;
-        break;
-    case PCI_CHIP_VT3204:
-    case PCI_CHIP_VT3344:
-        pVia->Chipset = VIA_K8M800;
-        break;
-    case PCI_CHIP_VT3259:
-        pVia->Chipset = VIA_PM800;
-        break;
-    default:
-        xf86DrvMsg(0, X_ERROR, "VIA: Unknown device ID (0x%x)\n", ctx->chipset);
-    }
-
-    /* _SOLO TODO XXX need to read ChipRev too */
-    pVia->ChipRev = 0;
-
-    pVia->videoRambytes = ctx->shared.fbSize;
-    pVia->MmioBase = ctx->MMIOStart;
-    pVia->FrameBufferBase = ctx->FBStart & 0xfc000000;
-
-    pVia->FBFreeStart = ctx->shared.virtualWidth * ctx->cpp *
-        ctx->shared.virtualHeight;
-
-#if 1
-    /* Alloc a second framebuffer for the second head */
-    pVia->FBFreeStart += ctx->shared.virtualWidth * ctx->cpp *
-	ctx->shared.virtualHeight;
-#endif
-
-    pVia->VQStart = pVia->FBFreeStart;
-    pVia->VQEnd = pVia->FBFreeStart + VIA_VQ_SIZE - 1;
-
-    pVia->FBFreeStart += VIA_VQ_SIZE;
-
-    pVia->FBFreeEnd = pVia->videoRambytes;
-
-    if (!VIADRIScreenInit(ctx))
-        return 0;
-
-    return 1;
-}
-
-static void viaHaltFBDev(DRIDriverContext *ctx)
-{
-    drmUnmap( ctx->pSAREA, ctx->shared.SAREASize );
-    drmClose(ctx->drmFD);
-
-    if (ctx->driverPrivate) {
-        free(ctx->driverPrivate);
-        ctx->driverPrivate = 0;
-    }
-}
-
-static int viaEngineShutdown(const DRIDriverContext *ctx)
-{
-    return 1;
-}
-
-static int viaEngineRestore(const DRIDriverContext *ctx)
-{
-    return 1;
-}
-
-const struct DRIDriverRec __driDriver =
-{
-    viaValidateMode,
-    viaPostValidateMode,
-    viaInitFBDev,
-    viaHaltFBDev,
-    viaEngineShutdown,
-    viaEngineRestore,  
-    0,
-};
-
-- 
cgit v1.2.3


From bc632d04370566c1156cbd0345fe303834f0b910 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 8 Mar 2010 12:12:31 -0800
Subject: i965: Fix up the handling of point sprite coordinate replacement.

The code was walking over the regs of pairs of attributes and checking
whether the attribute with a given reg index had point sprite enabled.
So the point sprite setup code was rarely even getting executed.
Instead, we need to determine which channels of a reg need point
sprite coordinate replacement.  In addition, it was multiplying the
attribute by 1/w, when it's supposed to cover (0, 1) in each direction
regardless of w, and it wasn't filling in the Z and W components of
the texcoord as specified.

Fixes piglit point-sprite and the spriteblast demo.  Bug #24431, #22245.
---
 src/mesa/drivers/dri/i965/brw_sf.c      |  21 ++---
 src/mesa/drivers/dri/i965/brw_sf.h      |   6 +-
 src/mesa/drivers/dri/i965/brw_sf_emit.c | 135 ++++++++++++++++++++------------
 3 files changed, 96 insertions(+), 66 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_sf.c b/src/mesa/drivers/dri/i965/brw_sf.c
index 8e6839b812..57d1c29ade 100644
--- a/src/mesa/drivers/dri/i965/brw_sf.c
+++ b/src/mesa/drivers/dri/i965/brw_sf.c
@@ -46,7 +46,6 @@
 static void compile_sf_prog( struct brw_context *brw,
 			     struct brw_sf_prog_key *key )
 {
-   GLcontext *ctx = &brw->intel.ctx;
    struct brw_sf_compile c;
    const GLuint *program;
    GLuint program_size;
@@ -69,20 +68,14 @@ static void compile_sf_prog( struct brw_context *brw,
 
    /* Construct map from attribute number to position in the vertex.
     */
-   for (i = idx = 0; i < VERT_RESULT_MAX; i++) 
+   for (i = idx = 0; i < VERT_RESULT_MAX; i++) {
       if (c.key.attrs & BITFIELD64_BIT(i)) {
 	 c.attr_to_idx[i] = idx;
 	 c.idx_to_attr[idx] = i;
-	 if (i >= VERT_RESULT_TEX0 && i <= VERT_RESULT_TEX7) {
-            c.point_attrs[i].CoordReplace = 
-               ctx->Point.CoordReplace[i - VERT_RESULT_TEX0];
-	 }
-         else {
-            c.point_attrs[i].CoordReplace = GL_FALSE;
-         }
 	 idx++;
       }
-   
+   }
+
    /* Which primitive?  Or all three? 
     */
    switch (key->primitive) {
@@ -162,6 +155,14 @@ static void upload_sf_prog(struct brw_context *brw)
    }
 
    key.do_point_sprite = ctx->Point.PointSprite;
+   if (key.do_point_sprite) {
+      int i;
+
+      for (i = 0; i < 8; i++) {
+	 if (ctx->Point.CoordReplace[i])
+	    key.point_sprite_coord_replace |= (1 << i);
+      }
+   }
    key.sprite_origin_lower_left = (ctx->Point.SpriteOrigin == GL_LOWER_LEFT);
    /* _NEW_LIGHT */
    key.do_flat_shading = (ctx->Light.ShadeModel == GL_FLAT);
diff --git a/src/mesa/drivers/dri/i965/brw_sf.h b/src/mesa/drivers/dri/i965/brw_sf.h
index 0ba731fac9..a0680a56f2 100644
--- a/src/mesa/drivers/dri/i965/brw_sf.h
+++ b/src/mesa/drivers/dri/i965/brw_sf.h
@@ -46,6 +46,7 @@
 
 struct brw_sf_prog_key {
    GLbitfield64 attrs;
+   uint8_t point_sprite_coord_replace;
    GLuint primitive:2;
    GLuint do_twoside_color:1;
    GLuint do_flat_shading:1;
@@ -56,10 +57,6 @@ struct brw_sf_prog_key {
    GLuint pad:24;
 };
 
-struct brw_sf_point_tex {
-   GLboolean CoordReplace;	
-};
-
 struct brw_sf_compile {
    struct brw_compile func;
    struct brw_sf_prog_key key;
@@ -100,7 +97,6 @@ struct brw_sf_compile {
 
    GLubyte attr_to_idx[VERT_RESULT_MAX];   
    GLubyte idx_to_attr[VERT_RESULT_MAX];   
-   struct brw_sf_point_tex point_attrs[VERT_RESULT_MAX];
 };
 
  
diff --git a/src/mesa/drivers/dri/i965/brw_sf_emit.c b/src/mesa/drivers/dri/i965/brw_sf_emit.c
index bb08055e3b..56f7c986e7 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_emit.c
@@ -354,6 +354,33 @@ static GLboolean calculate_masks( struct brw_sf_compile *c,
    return is_last_attr;
 }
 
+/* Calculates the predicate control for which channels of a reg
+ * (containing 2 attrs) to do point sprite coordinate replacement on.
+ */
+static uint16_t
+calculate_point_sprite_mask(struct brw_sf_compile *c, GLuint reg)
+{
+   int attr1, attr2;
+   uint16_t pc = 0;
+
+   attr1 = c->idx_to_attr[reg * 2];
+   if (attr1 >= VERT_RESULT_TEX0 && attr1 <= VERT_RESULT_TEX7) {
+      if (c->key.point_sprite_coord_replace & (1 << (attr1 - VERT_RESULT_TEX0)))
+	 pc |= 0x0f;
+   }
+
+   if (reg * 2 + 1 < c->nr_setup_attrs) {
+       attr2 = c->idx_to_attr[reg * 2 + 1];
+       if (attr2 >= VERT_RESULT_TEX0 && attr2 <= VERT_RESULT_TEX7) {
+	  if (c->key.point_sprite_coord_replace & (1 << (attr2 -
+							 VERT_RESULT_TEX0)))
+	     pc |= 0xf0;
+       }
+   }
+
+   return pc;
+}
+
 
 
 void brw_emit_tri_setup( struct brw_sf_compile *c, GLboolean allocate)
@@ -529,22 +556,27 @@ void brw_emit_point_sprite_setup( struct brw_sf_compile *c, GLboolean allocate)
    copy_z_inv_w(c);
    for (i = 0; i < c->nr_setup_regs; i++)
    {
-      struct brw_sf_point_tex *tex = &c->point_attrs[c->idx_to_attr[2*i]];
       struct brw_reg a0 = offset(c->vert[0], i);
-      GLushort pc, pc_persp, pc_linear;
+      GLushort pc, pc_persp, pc_linear, pc_coord_replace;
       GLboolean last = calculate_masks(c, i, &pc, &pc_persp, &pc_linear);
-            
-      if (pc_persp)
-      {				
-	  if (!tex->CoordReplace) {
-	      brw_set_predicate_control_flag_value(p, pc_persp);
-	      brw_MUL(p, a0, a0, c->inv_w[0]);
-	  }
+
+      pc_coord_replace = calculate_point_sprite_mask(c, i);
+      pc_persp &= ~pc_coord_replace;
+
+      if (pc_persp) {
+	 brw_set_predicate_control_flag_value(p, pc_persp);
+	 brw_MUL(p, a0, a0, c->inv_w[0]);
       }
 
-      if (tex->CoordReplace) {
-	  /* Caculate 1.0/PointWidth */
-	  brw_math(&c->func,
+      /* Point sprite coordinate replacement: A texcoord with this
+       * enabled gets replaced with the value (x, y, 0, 1) where x and
+       * y vary from 0 to 1 across the horizontal and vertical of the
+       * point.
+       */
+      if (pc_coord_replace) {
+	 brw_set_predicate_control_flag_value(p, pc_coord_replace);
+	 /* Caculate 1.0/PointWidth */
+	 brw_math(&c->func,
 		  c->tmp,
 		  BRW_MATH_FUNCTION_INV,
 		  BRW_MATH_SATURATE_NONE,
@@ -553,50 +585,51 @@ void brw_emit_point_sprite_setup( struct brw_sf_compile *c, GLboolean allocate)
 		  BRW_MATH_DATA_SCALAR,
 		  BRW_MATH_PRECISION_FULL);
 
-	  if (c->key.sprite_origin_lower_left) {
-	   	brw_MUL(p, c->m1Cx, c->tmp, c->inv_w[0]);
-		brw_MOV(p, vec1(suboffset(c->m1Cx, 1)), brw_imm_f(0.0));
-	  	brw_MUL(p, c->m2Cy, c->tmp, negate(c->inv_w[0]));
-		brw_MOV(p, vec1(suboffset(c->m2Cy, 0)), brw_imm_f(0.0));
-	  } else {
-	   	brw_MUL(p, c->m1Cx, c->tmp, c->inv_w[0]);
-		brw_MOV(p, vec1(suboffset(c->m1Cx, 1)), brw_imm_f(0.0));
-	  	brw_MUL(p, c->m2Cy, c->tmp, c->inv_w[0]);
-		brw_MOV(p, vec1(suboffset(c->m2Cy, 0)), brw_imm_f(0.0));
-	  }
-      } else {
-	  brw_MOV(p, c->m1Cx, brw_imm_ud(0));
-	  brw_MOV(p, c->m2Cy, brw_imm_ud(0));
-      }
+	 brw_set_access_mode(p, BRW_ALIGN_16);
 
-      {
-	 brw_set_predicate_control_flag_value(p, pc); 
-	 if (tex->CoordReplace) {
-	     if (c->key.sprite_origin_lower_left) {
-		 brw_MUL(p, c->m3C0, c->inv_w[0], brw_imm_f(1.0));
-		 brw_MOV(p, vec1(suboffset(c->m3C0, 0)), brw_imm_f(0.0));
-	     }
-	     else
-		 brw_MOV(p, c->m3C0, brw_imm_f(0.0));
+	 /* dA/dx, dA/dy */
+	 brw_MOV(p, c->m1Cx, brw_imm_f(0.0));
+	 brw_MOV(p, c->m2Cy, brw_imm_f(0.0));
+	 brw_MOV(p, brw_writemask(c->m1Cx, WRITEMASK_X), c->tmp);
+	 if (c->key.sprite_origin_lower_left) {
+	    brw_MOV(p, brw_writemask(c->m2Cy, WRITEMASK_Y), negate(c->tmp));
 	 } else {
-	 	brw_MOV(p, c->m3C0, a0); /* constant value */
+	    brw_MOV(p, brw_writemask(c->m2Cy, WRITEMASK_Y), c->tmp);
 	 }
 
-	 /* Copy m0..m3 to URB. 
-	  */
-	 brw_urb_WRITE(p, 
-		       brw_null_reg(),
-		       0,
-		       brw_vec8_grf(0, 0),
-		       0, 	/* allocate */
-		       1,	/* used */
-		       4, 	/* msg len */
-		       0,	/* response len */
-		       last, 	/* eot */
-		       last, 	/* writes complete */
-		       i*4,	/* urb destination offset */
-		       BRW_URB_SWIZZLE_TRANSPOSE);
+	 /* attribute constant offset */
+	 brw_MOV(p, c->m3C0, brw_imm_f(0.0));
+	 if (c->key.sprite_origin_lower_left) {
+	    brw_MOV(p, brw_writemask(c->m3C0, WRITEMASK_YW), brw_imm_f(1.0));
+	 } else {
+	    brw_MOV(p, brw_writemask(c->m3C0, WRITEMASK_W), brw_imm_f(1.0));
+	 }
+
+	 brw_set_access_mode(p, BRW_ALIGN_1);
       }
+
+      if (pc & ~pc_coord_replace) {
+	 brw_set_predicate_control_flag_value(p, pc & ~pc_coord_replace);
+	 brw_MOV(p, c->m1Cx, brw_imm_ud(0));
+	 brw_MOV(p, c->m2Cy, brw_imm_ud(0));
+	 brw_MOV(p, c->m3C0, a0); /* constant value */
+      }
+
+
+      brw_set_predicate_control_flag_value(p, pc);
+      /* Copy m0..m3 to URB. */
+      brw_urb_WRITE(p,
+		    brw_null_reg(),
+		    0,
+		    brw_vec8_grf(0, 0),
+		    0, 	/* allocate */
+		    1,	/* used */
+		    4, 	/* msg len */
+		    0,	/* response len */
+		    last, 	/* eot */
+		    last, 	/* writes complete */
+		    i*4,	/* urb destination offset */
+		    BRW_URB_SWIZZLE_TRANSPOSE);
    }
 }
 
-- 
cgit v1.2.3


From 7f6d2754d586545ab6c970acffdd897294879039 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 8 Mar 2010 16:08:33 -0800
Subject: i965: Fix up VP constbuf leak on program delete.

---
 src/mesa/drivers/dri/i965/brw_program.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index c78f7b38ae..1fd957b3ad 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -95,9 +95,17 @@ static void brwDeleteProgram( GLcontext *ctx,
 			      struct gl_program *prog )
 {
    if (prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
-      struct gl_fragment_program *fprog = (struct gl_fragment_program *) prog;
-      struct brw_fragment_program *brw_fprog = brw_fragment_program(fprog);
-      dri_bo_unreference(brw_fprog->const_buffer);
+      struct gl_fragment_program *fp = (struct gl_fragment_program *) prog;
+      struct brw_fragment_program *brw_fp = brw_fragment_program(fp);
+
+      dri_bo_unreference(brw_fp->const_buffer);
+   }
+
+   if (prog->Target == GL_VERTEX_PROGRAM_ARB) {
+      struct gl_vertex_program *vp = (struct gl_vertex_program *) prog;
+      struct brw_vertex_program *brw_vp = brw_vertex_program(vp);
+
+      dri_bo_unreference(brw_vp->const_buffer);
    }
 
    _mesa_delete_program( ctx, prog );
-- 
cgit v1.2.3


From f6f547d87ea68f44c50a0b0231b7360ca94b2975 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 9 Mar 2010 09:56:42 -0800
Subject: i965: Fix nested loops in the VS.

We were patching up all the break and continues between the start of
our loop and the end of our loop, even if they were breaks/continues
for an inner loop.  Avoiding patching already patched breaks/continues
fixes piglit glsl-vs-loop-nested.
---
 src/mesa/drivers/dri/i965/brw_vs_emit.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index a7c4b58972..a48804a660 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -1717,11 +1717,13 @@ void brw_vs_emit(struct brw_vs_compile *c )
             /* patch all the BREAK/CONT instructions from last BEGINLOOP */
             while (inst0 > loop_inst[loop_depth]) {
                inst0--;
-               if (inst0->header.opcode == BRW_OPCODE_BREAK) {
+               if (inst0->header.opcode == BRW_OPCODE_BREAK &&
+		   inst0->bits3.if_else.jump_count == 0) {
                   inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
                   inst0->bits3.if_else.pop_count = 0;
                }
-               else if (inst0->header.opcode == BRW_OPCODE_CONTINUE) {
+               else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
+			inst0->bits3.if_else.jump_count == 0) {
                   inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
                   inst0->bits3.if_else.pop_count = 0;
                }
-- 
cgit v1.2.3


From 280abdacf900d591ef909cf697f0c5679389c3f6 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 9 Mar 2010 11:31:28 -0800
Subject: i965: Print the offsets for WHILE and BREAK in disasm.

---
 src/mesa/drivers/dri/i965/brw_disasm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index a8f6b993ac..54699cf8d3 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -74,9 +74,9 @@ struct {
     [BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 1, .ndst = 0 },
     [BRW_OPCODE_IF] = { .name = "if", .nsrc = 2, .ndst = 0 },
     [BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 1, .ndst = 01 },
-    [BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 1, .ndst = 0 },
+    [BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 2, .ndst = 0 },
     [BRW_OPCODE_ELSE] = { .name = "else", .nsrc = 2, .ndst = 0 },
-    [BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 1, .ndst = 0 },
+    [BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 2, .ndst = 0 },
     [BRW_OPCODE_CONTINUE] = { .name = "cont", .nsrc = 1, .ndst = 0 },
     [BRW_OPCODE_HALT] = { .name = "halt", .nsrc = 1, .ndst = 0 },
     [BRW_OPCODE_MSAVE] = { .name = "msave", .nsrc = 1, .ndst = 1 },
-- 
cgit v1.2.3


From 6b194dab6b4d9f12cdd54c699b23c0d3420a49c2 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 9 Mar 2010 11:56:14 -0800
Subject: i965: Unalias all GLSL source regs from the destination regs used.

We were doing it ad-hoc before, as instructions with potential
aliasing problems were identified.  But thanks to swizzling basically
anything can have aliasing, so just do it generally at source reg
setup time.  This is somewhat inefficient, because sometimes an
operation doesn't need unaliasing protection if the swizzling is safe,
but the unaliasing before didn't cover those cases either.

Fixes piglit glsl-fs-loop.
---
 src/mesa/drivers/dri/i965/brw_wm_glsl.c | 138 ++++++--------------------------
 1 file changed, 25 insertions(+), 113 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
index 562608e2ec..13306accda 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
@@ -614,112 +614,6 @@ static void invoke_subroutine( struct brw_wm_compile *c,
     }
 }
 
-/* Workaround for using brw_wm_emit.c's emit functions, which expect
- * destination regs to be uniquely written.  Moves arguments out to
- * temporaries as necessary for instructions which use their destination as
- * a temporary.
- */
-static void
-unalias3(struct brw_wm_compile *c,
-	 void (*func)(struct brw_compile *c,
-		      const struct brw_reg *dst,
-		      GLuint mask,
-		      const struct brw_reg *arg0,
-		      const struct brw_reg *arg1,
-		      const struct brw_reg *arg2),
-	 const struct brw_reg *dst,
-	 GLuint mask,
-	 const struct brw_reg *arg0,
-	 const struct brw_reg *arg1,
-	 const struct brw_reg *arg2)
-{
-    struct brw_compile *p = &c->func;
-    struct brw_reg tmp_arg0[4], tmp_arg1[4], tmp_arg2[4];
-    int i, j;
-    int mark = mark_tmps(c);
-
-    for (j = 0; j < 4; j++) {
-	tmp_arg0[j] = arg0[j];
-	tmp_arg1[j] = arg1[j];
-	tmp_arg2[j] = arg2[j];
-    }
-
-    for (i = 0; i < 4; i++) {
-	if (mask & (1<<i)) {
-	    for (j = 0; j < 4; j++) {
-		if (arg0[j].file == dst[i].file &&
-		    dst[i].nr == arg0[j].nr) {
-		    tmp_arg0[j] = alloc_tmp(c);
-		    brw_MOV(p, tmp_arg0[j], arg0[j]);
-		}
-		if (arg1[j].file == dst[i].file &&
-		    dst[i].nr == arg1[j].nr) {
-		    tmp_arg1[j] = alloc_tmp(c);
-		    brw_MOV(p, tmp_arg1[j], arg1[j]);
-		}
-		if (arg2[j].file == dst[i].file &&
-		    dst[i].nr == arg2[j].nr) {
-		    tmp_arg2[j] = alloc_tmp(c);
-		    brw_MOV(p, tmp_arg2[j], arg2[j]);
-		}
-	    }
-	}
-    }
-
-    func(p, dst, mask, tmp_arg0, tmp_arg1, tmp_arg2);
-
-    release_tmps(c, mark);
-}
-
-/* Workaround for using brw_wm_emit.c's emit functions, which expect
- * destination regs to be uniquely written.  Moves arguments out to
- * temporaries as necessary for instructions which use their destination as
- * a temporary.
- */
-static void
-unalias2(struct brw_wm_compile *c,
-	 void (*func)(struct brw_compile *c,
-		      const struct brw_reg *dst,
-		      GLuint mask,
-		      const struct brw_reg *arg0,
-		      const struct brw_reg *arg1),
-	 const struct brw_reg *dst,
-	 GLuint mask,
-	 const struct brw_reg *arg0,
-	 const struct brw_reg *arg1)
-{
-    struct brw_compile *p = &c->func;
-    struct brw_reg tmp_arg0[4], tmp_arg1[4];
-    int i, j;
-    int mark = mark_tmps(c);
-
-    for (j = 0; j < 4; j++) {
-	tmp_arg0[j] = arg0[j];
-	tmp_arg1[j] = arg1[j];
-    }
-
-    for (i = 0; i < 4; i++) {
-	if (mask & (1<<i)) {
-	    for (j = 0; j < 4; j++) {
-		if (arg0[j].file == dst[i].file &&
-		    dst[i].nr == arg0[j].nr) {
-		    tmp_arg0[j] = alloc_tmp(c);
-		    brw_MOV(p, tmp_arg0[j], arg0[j]);
-		}
-		if (arg1[j].file == dst[i].file &&
-		    dst[i].nr == arg1[j].nr) {
-		    tmp_arg1[j] = alloc_tmp(c);
-		    brw_MOV(p, tmp_arg1[j], arg1[j]);
-		}
-	    }
-	}
-    }
-
-    func(p, dst, mask, tmp_arg0, tmp_arg1);
-
-    release_tmps(c, mark);
-}
-
 static void emit_arl(struct brw_wm_compile *c,
                      const struct prog_instruction *inst)
 {
@@ -1813,14 +1707,29 @@ static void
 get_argument_regs(struct brw_wm_compile *c,
 		  const struct prog_instruction *inst,
 		  int index,
+		  struct brw_reg *dst,
 		  struct brw_reg *regs,
 		  int mask)
 {
-    int i;
+    struct brw_compile *p = &c->func;
+    int i, j;
 
     for (i = 0; i < 4; i++) {
-	if (mask & (1 << i))
+	if (mask & (1 << i)) {
 	    regs[i] = get_src_reg(c, inst, index, i);
+
+	    /* Unalias destination registers from our sources. */
+	    if (regs[i].file == BRW_GENERAL_REGISTER_FILE) {
+	       for (j = 0; j < 4; j++) {
+		   if (memcmp(&regs[i], &dst[j], sizeof(regs[0])) == 0) {
+		       struct brw_reg tmp = alloc_tmp(c);
+		       brw_MOV(p, tmp, regs[i]);
+		       regs[i] = tmp;
+		       break;
+		   }
+	       }
+	    }
+	}
     }
 }
 
@@ -1845,6 +1754,7 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
 	int dst_flags;
 	struct brw_reg args[3][4], dst[4];
 	int j;
+	int mark = mark_tmps( c );
 
         c->cur_inst = i;
 
@@ -1866,7 +1776,7 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
 	   }
 	}
 	for (j = 0; j < brw_wm_nr_args(inst->Opcode); j++)
-	    get_argument_regs(c, inst, j, args[j], WRITEMASK_XYZW);
+	    get_argument_regs(c, inst, j, dst, args[j], WRITEMASK_XYZW);
 
 	dst_flags = inst->DstReg.WriteMask;
 	if (inst->SaturateMode == SATURATE_ZERO_ONE)
@@ -1920,8 +1830,7 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
 		emit_alu1(p, brw_RNDD, dst, dst_flags, args[0]);
 		break;
 	    case OPCODE_LRP:
-		unalias3(c, emit_lrp,
-			 dst, dst_flags, args[0], args[1], args[2]);
+		emit_lrp(p, dst, dst_flags, args[0], args[1], args[2]);
 		break;
 	    case OPCODE_TRUNC:
 		emit_alu1(p, brw_RNDZ, dst, dst_flags, args[0]);
@@ -1961,10 +1870,10 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
 		emit_math1(c, BRW_MATH_FUNCTION_LOG, dst, dst_flags, args[0]);
 		break;
 	    case OPCODE_MIN:	
-		unalias2(c, emit_min, dst, dst_flags, args[0], args[1]);
+		emit_min(p, dst, dst_flags, args[0], args[1]);
 		break;
 	    case OPCODE_MAX:	
-		unalias2(c, emit_max, dst, dst_flags, args[0], args[1]);
+		emit_max(p, dst, dst_flags, args[0], args[1]);
 		break;
 	    case OPCODE_DDX:
 	    case OPCODE_DDY:
@@ -2119,6 +2028,9 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
 			inst->Opcode);
 	}
 
+	/* Release temporaries containing any unaliased source regs. */
+	release_tmps( c, mark );
+
 	if (inst->CondUpdate)
 	    brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
 	else
-- 
cgit v1.2.3


From a81836ee2fe5092d695b717addf8cec91f569777 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 9 Mar 2010 14:22:51 -0800
Subject: i965: Fix ENDLOOP to only patch up this loop's BREAK and CONT.

Corresponds to d225a25e21a24508aea3b877c78beb35502e942d and fixes
piglit glsl-fs-loop-nested.  Bug #25173.
---
 src/mesa/drivers/dri/i965/brw_wm_glsl.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
index 13306accda..ea3c2405af 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
@@ -2012,11 +2012,13 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
                   /* patch all the BREAK/CONT instructions from last BGNLOOP */
                   while (inst0 > loop_inst[loop_depth]) {
                      inst0--;
-                     if (inst0->header.opcode == BRW_OPCODE_BREAK) {
+                     if (inst0->header.opcode == BRW_OPCODE_BREAK &&
+			 inst0->bits3.if_else.jump_count == 0) {
 			inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
 			inst0->bits3.if_else.pop_count = 0;
                      }
-                     else if (inst0->header.opcode == BRW_OPCODE_CONTINUE) {
+                     else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
+			      inst0->bits3.if_else.jump_count == 0) {
                         inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
                         inst0->bits3.if_else.pop_count = 0;
                      }
-- 
cgit v1.2.3


From c8ef7a09664d29dac682b953eb66efaebbdd6fd7 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 10 Mar 2010 09:31:49 -0800
Subject: i965: Print the offset for IFF in disasm

---
 src/mesa/drivers/dri/i965/brw_disasm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index 54699cf8d3..4d25152efc 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -73,7 +73,7 @@ struct {
     [BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 },
     [BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 1, .ndst = 0 },
     [BRW_OPCODE_IF] = { .name = "if", .nsrc = 2, .ndst = 0 },
-    [BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 1, .ndst = 01 },
+    [BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 2, .ndst = 1 },
     [BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 2, .ndst = 0 },
     [BRW_OPCODE_ELSE] = { .name = "else", .nsrc = 2, .ndst = 0 },
     [BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 2, .ndst = 0 },
-- 
cgit v1.2.3


From f6d210c284751ac50a8d6358de7e75a1ff1e4ac7 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 10 Mar 2010 10:38:20 -0800
Subject: i965: Fix the response len of masked sampler messages for 8-wide
 dispatch.

The bad response length would hang the GPU with a masked sample in a
shader using control flow.  For 8-wide, the response length is always
4, and masked slots are just not written to.  brw_wm_glsl.c already
allocates registers in the right locations.

Fixes piglit glsl-fs-bug25902 (fd.o bug #25902).
---
 src/mesa/drivers/dri/i965/brw_eu_emit.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index f69d529613..40c1b71998 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -1290,7 +1290,11 @@ void brw_SAMPLE(struct brw_compile *p,
 		GLuint simd_mode)
 {
    GLboolean need_stall = 0;
-   
+   GLboolean dispatch_16 = GL_FALSE;
+
+   if (p->current->header.execution_size == BRW_EXECUTE_16)
+      dispatch_16 = GL_TRUE;
+
    if (writemask == 0) {
       /*printf("%s: zero writemask??\n", __FUNCTION__); */
       return;
@@ -1343,7 +1347,13 @@ void brw_SAMPLE(struct brw_compile *p,
 
   	 src0 = retype(brw_null_reg(), BRW_REGISTER_TYPE_UW); 
 	 dest = offset(dest, dst_offset);
-	 response_length = len * 2;
+
+	 /* For 16-wide dispatch, masked channels are skipped in the
+	  * response.  For 8-wide, masked channels still take up slots,
+	  * and are just not written to.
+	  */
+	 if (dispatch_16)
+	    response_length = len * 2;
       }
    }
 
-- 
cgit v1.2.3


From f77c1cd7df805f097958a5b83d235f8a8ad693b1 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 10 Mar 2010 10:51:13 -0800
Subject: i965: Print the opcode name for unrecognized opcodes in the GLSL
 path.

---
 src/mesa/drivers/dri/i965/brw_wm_glsl.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
index ea3c2405af..14caf24e4b 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
@@ -2026,8 +2026,9 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
                }
                break;
 	    default:
-		printf("unsupported IR in fragment shader %d\n",
-			inst->Opcode);
+		printf("unsupported opcode %d (%s) in fragment shader\n",
+		       inst->Opcode, inst->Opcode < MAX_OPCODE ?
+		       _mesa_opcode_string(inst->Opcode) : "unknown");
 	}
 
 	/* Release temporaries containing any unaliased source regs. */
-- 
cgit v1.2.3


From 48dca99feb394febc3af44e14f23fb12a9cc9204 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 10 Mar 2010 11:00:40 -0800
Subject: i965: Add support for the CMP opcode in the GLSL path.

This would be triggered by use of sqrt() along with control flow.
Fixes piglit-fs-sqrt-branch and a bug in Yo Frankie!.
---
 src/mesa/drivers/dri/i965/brw_wm.h      |  6 ++++++
 src/mesa/drivers/dri/i965/brw_wm_emit.c | 12 ++++++------
 src/mesa/drivers/dri/i965/brw_wm_glsl.c |  3 +++
 3 files changed, 15 insertions(+), 6 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h
index 88d84ee82f..47b764d24d 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.h
+++ b/src/mesa/drivers/dri/i965/brw_wm.h
@@ -328,6 +328,12 @@ void emit_cinterp(struct brw_compile *p,
 		  const struct brw_reg *dst,
 		  GLuint mask,
 		  const struct brw_reg *arg0);
+void emit_cmp(struct brw_compile *p,
+	      const struct brw_reg *dst,
+	      GLuint mask,
+	      const struct brw_reg *arg0,
+	      const struct brw_reg *arg1,
+	      const struct brw_reg *arg2);
 void emit_ddxy(struct brw_compile *p,
 	       const struct brw_reg *dst,
 	       GLuint mask,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index 9315bca315..c7d87b9d94 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -566,12 +566,12 @@ static void emit_sne( struct brw_compile *p,
    emit_sop(p, dst, mask, BRW_CONDITIONAL_NEQ, arg0, arg1);
 }
 
-static void emit_cmp( struct brw_compile *p, 
-		      const struct brw_reg *dst,
-		      GLuint mask,
-		      const struct brw_reg *arg0,
-		      const struct brw_reg *arg1,
-		      const struct brw_reg *arg2 )
+void emit_cmp(struct brw_compile *p,
+	      const struct brw_reg *dst,
+	      GLuint mask,
+	      const struct brw_reg *arg0,
+	      const struct brw_reg *arg1,
+	      const struct brw_reg *arg2)
 {
    GLuint i;
 
diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
index 14caf24e4b..af249452b9 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
@@ -1869,6 +1869,9 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
 	    case OPCODE_LG2:
 		emit_math1(c, BRW_MATH_FUNCTION_LOG, dst, dst_flags, args[0]);
 		break;
+	    case OPCODE_CMP:
+		emit_cmp(p, dst, dst_flags, args[0], args[1], args[2]);
+		break;
 	    case OPCODE_MIN:	
 		emit_min(p, dst, dst_flags, args[0], args[1]);
 		break;
-- 
cgit v1.2.3


From dc8c0359448cdae7b367552ba58783c04b199778 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 10 Mar 2010 13:51:24 -0800
Subject: i965: Set up the execution size before relying on it.

Fixes hangs with texturing in the non-GLSL path since
f6d210c284751ac50a8d6358de7e75a1ff1e4ac7
---
 src/mesa/drivers/dri/i965/brw_eu_emit.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 40c1b71998..82f2fdab2f 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -1290,10 +1290,6 @@ void brw_SAMPLE(struct brw_compile *p,
 		GLuint simd_mode)
 {
    GLboolean need_stall = 0;
-   GLboolean dispatch_16 = GL_FALSE;
-
-   if (p->current->header.execution_size == BRW_EXECUTE_16)
-      dispatch_16 = GL_TRUE;
 
    if (writemask == 0) {
       /*printf("%s: zero writemask??\n", __FUNCTION__); */
@@ -1331,8 +1327,14 @@ void brw_SAMPLE(struct brw_compile *p,
          /* printf("need stall %x %x\n", newmask , writemask); */
       }
       else {
+	 GLboolean dispatch_16 = GL_FALSE;
+
 	 struct brw_reg m1 = brw_message_reg(msg_reg_nr);
-	 
+
+	 guess_execution_size(p->current, dest);
+	 if (p->current->header.execution_size == BRW_EXECUTE_16)
+	    dispatch_16 = GL_TRUE;
+
 	 newmask = ~newmask & WRITEMASK_XYZW;
 
 	 brw_push_insn_state(p);
-- 
cgit v1.2.3


From 56ff30a9f97a1a7094432333906544d6138d6bf2 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 10 Mar 2010 14:46:27 -0800
Subject: i965: Use the PLN instruction when possible in interpolation.

Saves an instruction in PINTERP, LINTERP, and PIXEL_W from
brw_wm_glsl.c For non-GLSL it isn't used yet because the deltas have
to be laid out differently.
---
 src/mesa/drivers/dri/i965/brw_context.c |  1 +
 src/mesa/drivers/dri/i965/brw_context.h |  1 +
 src/mesa/drivers/dri/i965/brw_defines.h |  1 +
 src/mesa/drivers/dri/i965/brw_disasm.c  |  1 +
 src/mesa/drivers/dri/i965/brw_eu.h      |  1 +
 src/mesa/drivers/dri/i965/brw_eu_emit.c |  2 +-
 src/mesa/drivers/dri/i965/brw_wm_emit.c | 44 ++++++++++++++++++++++++++++-----
 src/mesa/drivers/dri/i965/brw_wm_glsl.c | 38 ++++++++++++++++++++++++++++
 8 files changed, 82 insertions(+), 7 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index a512896f31..241193c357 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -156,6 +156,7 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis,
       brw->has_surface_tile_offset = GL_TRUE;
       brw->has_compr4 = GL_TRUE;
       brw->has_aa_line_parameters = GL_TRUE;
+      brw->has_pln = GL_TRUE;
   } else {
       brw->CMD_VF_STATISTICS = CMD_VF_STATISTICS_965;
       brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_965;
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index d6fc37e4d8..2855c93ea6 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -446,6 +446,7 @@ struct brw_context
    GLboolean has_compr4;
    GLboolean has_negative_rhw_bug;
    GLboolean has_aa_line_parameters;
+   GLboolean has_pln;
 ;
    struct {
       struct brw_state_flags dirty;
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index bb1b5f5ef0..984e56d00c 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -550,6 +550,7 @@
 #define BRW_OPCODE_DP2        87
 #define BRW_OPCODE_DPA2       88
 #define BRW_OPCODE_LINE       89
+#define BRW_OPCODE_PLN        90
 #define BRW_OPCODE_NOP        126
 
 #define BRW_PREDICATE_NONE             0
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index 4d25152efc..ad61770212 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -50,6 +50,7 @@ struct {
     [BRW_OPCODE_MAC] = { .name = "mac", .nsrc = 2, .ndst = 1 },
     [BRW_OPCODE_MACH] = { .name = "mach", .nsrc = 2, .ndst = 1 },
     [BRW_OPCODE_LINE] = { .name = "line", .nsrc = 2, .ndst = 1 },
+    [BRW_OPCODE_PLN] = { .name = "pln", .nsrc = 2, .ndst = 1 },
     [BRW_OPCODE_SAD2] = { .name = "sad2", .nsrc = 2, .ndst = 1 },
     [BRW_OPCODE_SADA2] = { .name = "sada2", .nsrc = 2, .ndst = 1 },
     [BRW_OPCODE_DP4] = { .name = "dp4", .nsrc = 2, .ndst = 1 },
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 39eb88d7c2..8e9117b644 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -795,6 +795,7 @@ ALU2(DPH)
 ALU2(DP3)
 ALU2(DP2)
 ALU2(LINE)
+ALU2(PLN)
 
 #undef ALU1
 #undef ALU2
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 82f2fdab2f..d2395dec28 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -573,7 +573,7 @@ ALU2(DPH)
 ALU2(DP3)
 ALU2(DP2)
 ALU2(LINE)
-
+ALU2(PLN)
 
 
 
diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index c7d87b9d94..412e09b76a 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -34,6 +34,23 @@
 #include "brw_context.h"
 #include "brw_wm.h"
 
+static GLboolean can_do_pln(struct intel_context *intel,
+			    const struct brw_reg *deltas)
+{
+   struct brw_context *brw = brw_context(&intel->ctx);
+
+   if (!brw->has_pln)
+      return GL_FALSE;
+
+   if (deltas[1].nr != deltas[0].nr + 1)
+      return GL_FALSE;
+
+   if (intel->gen < 6 && ((deltas[0].nr & 1) != 0))
+      return GL_FALSE;
+
+   return GL_TRUE;
+}
+
 /* Not quite sure how correct this is - need to understand horiz
  * vs. vertical strides a little better.
  */
@@ -186,6 +203,7 @@ void emit_pixel_w(struct brw_wm_compile *c,
 		  const struct brw_reg *deltas)
 {
    struct brw_compile *p = &c->func;
+   struct intel_context *intel = &p->brw->intel;
 
    /* Don't need this if all you are doing is interpolating color, for
     * instance.
@@ -196,8 +214,12 @@ void emit_pixel_w(struct brw_wm_compile *c,
       /* Calc 1/w - just linterp wpos[3] optimized by putting the
        * result straight into a message reg.
        */
-      brw_LINE(p, brw_null_reg(), interp3, deltas[0]);
-      brw_MAC(p, brw_message_reg(2), suboffset(interp3, 1), deltas[1]);
+      if (can_do_pln(intel, deltas)) {
+	 brw_PLN(p, brw_message_reg(2), interp3, deltas[0]);
+      } else {
+	 brw_LINE(p, brw_null_reg(), interp3, deltas[0]);
+	 brw_MAC(p, brw_message_reg(2), suboffset(interp3, 1), deltas[1]);
+      }
 
       /* Calc w */
       if (c->dispatch_width == 16) {
@@ -224,6 +246,7 @@ void emit_linterp(struct brw_compile *p,
 		  const struct brw_reg *arg0,
 		  const struct brw_reg *deltas)
 {
+   struct intel_context *intel = &p->brw->intel;
    struct brw_reg interp[4];
    GLuint nr = arg0[0].nr;
    GLuint i;
@@ -235,8 +258,12 @@ void emit_linterp(struct brw_compile *p,
 
    for (i = 0; i < 4; i++) {
       if (mask & (1<<i)) {
-	 brw_LINE(p, brw_null_reg(), interp[i], deltas[0]);
-	 brw_MAC(p, dst[i], suboffset(interp[i],1), deltas[1]);
+	 if (can_do_pln(intel, deltas)) {
+	    brw_PLN(p, dst[i], interp[i], deltas[0]);
+	 } else {
+	    brw_LINE(p, brw_null_reg(), interp[i], deltas[0]);
+	    brw_MAC(p, dst[i], suboffset(interp[i],1), deltas[1]);
+	 }
       }
    }
 }
@@ -249,6 +276,7 @@ void emit_pinterp(struct brw_compile *p,
 		  const struct brw_reg *deltas,
 		  const struct brw_reg *w)
 {
+   struct intel_context *intel = &p->brw->intel;
    struct brw_reg interp[4];
    GLuint nr = arg0[0].nr;
    GLuint i;
@@ -260,8 +288,12 @@ void emit_pinterp(struct brw_compile *p,
 
    for (i = 0; i < 4; i++) {
       if (mask & (1<<i)) {
-	 brw_LINE(p, brw_null_reg(), interp[i], deltas[0]);
-	 brw_MAC(p, dst[i], suboffset(interp[i],1), deltas[1]);
+	 if (can_do_pln(intel, deltas)) {
+	    brw_PLN(p, dst[i], interp[i], deltas[0]);
+	 } else {
+	    brw_LINE(p, brw_null_reg(), interp[i], deltas[0]);
+	    brw_MAC(p, dst[i], suboffset(interp[i],1), deltas[1]);
+	 }
       }
    }
    for (i = 0; i < 4; i++) {
diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
index af249452b9..0b66cc6c9f 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
@@ -289,6 +289,7 @@ reclaim_temps(struct brw_wm_compile *c)
  */
 static void prealloc_reg(struct brw_wm_compile *c)
 {
+    struct intel_context *intel = &c->func.brw->intel;
     int i, j;
     struct brw_reg reg;
     int urb_read_length = 0;
@@ -413,6 +414,43 @@ static void prealloc_reg(struct brw_wm_compile *c)
 	}
     }
 
+    for (i = 0; i < c->nr_fp_insns; i++) {
+	const struct prog_instruction *inst = &c->prog_instructions[i];
+
+	switch (inst->Opcode) {
+	case WM_DELTAXY:
+	    /* Allocate WM_DELTAXY destination on G45/GM45 to an
+	     * even-numbered GRF if possible so that we can use the PLN
+	     * instruction.
+	     */
+	    if (inst->DstReg.WriteMask == WRITEMASK_XY &&
+		!c->wm_regs[inst->DstReg.File][inst->DstReg.Index][0].inited &&
+		!c->wm_regs[inst->DstReg.File][inst->DstReg.Index][1].inited &&
+		(IS_G4X(intel->intelScreen->deviceID) || intel->gen == 5)) {
+		int grf;
+
+		for (grf = c->first_free_grf & ~1;
+		     grf < BRW_WM_MAX_GRF;
+		     grf += 2)
+		{
+		    if (!c->used_grf[grf] && !c->used_grf[grf + 1]) {
+			c->used_grf[grf] = GL_TRUE;
+			c->used_grf[grf + 1] = GL_TRUE;
+			c->first_free_grf = grf + 2;  /* a guess */
+
+			set_reg(c, inst->DstReg.File, inst->DstReg.Index, 0,
+				brw_vec8_grf(grf, 0));
+			set_reg(c, inst->DstReg.File, inst->DstReg.Index, 1,
+				brw_vec8_grf(grf + 1, 0));
+			break;
+		    }
+		}
+	    }
+	default:
+	    break;
+	}
+    }
+
     /* An instruction may reference up to three constants.
      * They'll be found in these registers.
      * XXX alloc these on demand!
-- 
cgit v1.2.3


From ba541b0769768ffa09562938d3b49690669948b8 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 10 Mar 2010 15:32:05 -0800
Subject: i965: Use the SEL instruction to implement MIN and MAX.

Saves an instruction over doing conditional moves.
---
 src/mesa/drivers/dri/i965/brw_wm_emit.c | 14 +++-----------
 1 file changed, 3 insertions(+), 11 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index 412e09b76a..b169576017 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -633,14 +633,10 @@ void emit_max(struct brw_compile *p,
 
    for (i = 0; i < 4; i++) {
       if (mask & (1<<i)) {	
-	 brw_set_saturate(p, (mask & SATURATE) ? 1 : 0);
-	 brw_MOV(p, dst[i], arg0[i]);
-	 brw_set_saturate(p, 0);
-
-	 brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, arg0[i], arg1[i]);
+	 brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_GE, arg0[i], arg1[i]);
 
 	 brw_set_saturate(p, (mask & SATURATE) ? 1 : 0);
-	 brw_MOV(p, dst[i], arg1[i]);
+	 brw_SEL(p, dst[i], arg0[i], arg1[i]);
 	 brw_set_saturate(p, 0);
 	 brw_set_predicate_control_flag_value(p, 0xff);
       }
@@ -657,14 +653,10 @@ void emit_min(struct brw_compile *p,
 
    for (i = 0; i < 4; i++) {
       if (mask & (1<<i)) {	
-	 brw_set_saturate(p, (mask & SATURATE) ? 1 : 0);
-	 brw_MOV(p, dst[i], arg1[i]);
-	 brw_set_saturate(p, 0);
-
 	 brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, arg0[i], arg1[i]);
 
 	 brw_set_saturate(p, (mask & SATURATE) ? 1 : 0);
-	 brw_MOV(p, dst[i], arg0[i]);
+	 brw_SEL(p, dst[i], arg0[i], arg1[i]);
 	 brw_set_saturate(p, 0);
 	 brw_set_predicate_control_flag_value(p, 0xff);
       }
-- 
cgit v1.2.3


From 52cea5090ceb56105464d60b989c2c36ec9c4b16 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 10 Mar 2010 15:44:32 -0800
Subject: i965: When doing a swizzled kill pixel, don't do redundant channel
 compares.

This was obvious when looking at the compiled output of ETQW's
shaders.
---
 src/mesa/drivers/dri/i965/brw_wm_emit.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index b169576017..3a4057bb6b 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -1110,11 +1110,19 @@ static void emit_kil( struct brw_wm_compile *c,
 {
    struct brw_compile *p = &c->func;
    struct brw_reg r0uw = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
-   GLuint i;
-   
-   /* XXX - usually won't need 4 compares!
-    */
+   GLuint i, j;
+
    for (i = 0; i < 4; i++) {
+      /* Check if we've already done the comparison for this reg
+       * -- common when someone does KIL TEMP.wwww.
+       */
+      for (j = 0; j < i; j++) {
+	 if (memcmp(&arg0[j], &arg0[i], sizeof(arg0[0])) == 0)
+	    break;
+      }
+      if (j != i)
+	 continue;
+
       brw_push_insn_state(p);
       brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_GE, arg0[i], brw_imm_f(0));   
       brw_set_predicate_control_flag_value(p, 0xff);
-- 
cgit v1.2.3


From 512d8ca2f34bcaa96e18daace4ae9f95e679471e Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 10 Mar 2010 17:16:39 -0800
Subject: i965: Fix up VS DP4 sequences to avoid dependency control.

This is recommended by the B-Spec.  I wasn't able to measure any
difference in ETQW.
---
 src/mesa/drivers/dri/i965/Makefile       |   1 +
 src/mesa/drivers/dri/i965/brw_eu.h       |   5 ++
 src/mesa/drivers/dri/i965/brw_optimize.c | 115 +++++++++++++++++++++++++++++++
 src/mesa/drivers/dri/i965/brw_vs_emit.c  |   2 +
 4 files changed, 123 insertions(+)
 create mode 100644 src/mesa/drivers/dri/i965/brw_optimize.c

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index a242580273..842d4b7aa1 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -54,6 +54,7 @@ DRIVER_SOURCES = \
 	brw_gs_emit.c \
 	brw_gs_state.c \
 	brw_misc_state.c \
+	brw_optimize.c \
 	brw_program.c \
 	brw_queryobj.c \
 	brw_sf.c \
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 8e9117b644..4f55158e8f 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -966,4 +966,9 @@ void brw_math_invert( struct brw_compile *p,
 
 void brw_set_src1( struct brw_instruction *insn,
                           struct brw_reg reg );
+
+
+/* brw_optimize.c */
+void brw_optimize(struct brw_compile *p);
+
 #endif
diff --git a/src/mesa/drivers/dri/i965/brw_optimize.c b/src/mesa/drivers/dri/i965/brw_optimize.c
new file mode 100644
index 0000000000..57df9ea115
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_optimize.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Eric Anholt <eric@anholt.net>
+ *
+ */
+
+#include "main/macros.h"
+#include "shader/program.h"
+#include "shader/prog_parameter.h"
+#include "shader/prog_print.h"
+#include "brw_context.h"
+#include "brw_defines.h"
+#include "brw_eu.h"
+
+static GLboolean
+is_single_channel_dp4(struct brw_instruction *insn)
+{
+   if (insn->header.opcode != BRW_OPCODE_DP4 ||
+       insn->header.execution_size != BRW_EXECUTE_8 ||
+       insn->header.access_mode != BRW_ALIGN_16 ||
+       insn->bits1.da1.dest_reg_file != BRW_GENERAL_REGISTER_FILE)
+      return GL_FALSE;
+
+   if (!is_power_of_two(insn->bits1.da16.dest_writemask))
+      return GL_FALSE;
+
+   return GL_TRUE;
+}
+
+/**
+ * Sets the dependency control fields on DP4 instructions.
+ *
+ * The hardware only tracks dependencies on a register basis, so when
+ * you do:
+ *
+ * DP4 dst.x src1 src2
+ * DP4 dst.y src1 src3
+ * DP4 dst.z src1 src4
+ * DP4 dst.w src1 src5
+ *
+ * It will wait to do the DP4 dst.y until the dst.x is resolved, etc.
+ * We can examine our instruction stream and set the dependency
+ * control fields to tell the hardware when to do it.
+ *
+ * We may want to extend this to other instructions that are used to
+ * fill in a channel at a time of the destination register.
+ */
+static void
+brw_set_dp4_dependency_control(struct brw_compile *p)
+{
+   int i;
+
+   for (i = 1; i < p->nr_insn; i++) {
+      struct brw_instruction *insn = &p->store[i];
+      struct brw_instruction *prev = &p->store[i - 1];
+
+      if (!is_single_channel_dp4(prev))
+	 continue;
+
+      if (!is_single_channel_dp4(insn)) {
+	 i++;
+	 continue;
+      }
+
+      /* Only avoid hw dep control if the write masks are different
+       * channels of one reg.
+       */
+      if (insn->bits1.da16.dest_writemask == prev->bits1.da16.dest_writemask)
+	 continue;
+      if (insn->bits1.da16.dest_reg_nr != prev->bits1.da16.dest_reg_nr)
+	 continue;
+
+      /* Check if the second instruction depends on the previous one
+       * for a src.
+       */
+      if (insn->bits1.da1.src0_reg_file == BRW_GENERAL_REGISTER_FILE &&
+	  (insn->bits2.da1.src0_address_mode != BRW_ADDRESS_DIRECT ||
+	   insn->bits2.da1.src0_reg_nr == insn->bits1.da16.dest_reg_nr))
+	  continue;
+      if (insn->bits1.da1.src1_reg_file == BRW_GENERAL_REGISTER_FILE &&
+	  (insn->bits3.da1.src1_address_mode != BRW_ADDRESS_DIRECT ||
+	   insn->bits3.da1.src1_reg_nr == insn->bits1.da16.dest_reg_nr))
+	  continue;
+
+      prev->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
+      insn->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
+   }
+}
+
+void
+brw_optimize(struct brw_compile *p)
+{
+   brw_set_dp4_dependency_control(p);
+}
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index a48804a660..14c3b936b7 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -1825,6 +1825,8 @@ void brw_vs_emit(struct brw_vs_compile *c )
 
    post_vs_emit(c, end_inst, last_inst);
 
+   brw_optimize(p);
+
    if (INTEL_DEBUG & DEBUG_VS) {
       int i;
 
-- 
cgit v1.2.3


From 8ef3b1834a896927bdd4f2aea552cdb732849da9 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 10 Mar 2010 17:35:02 -0800
Subject: i965: Do VS SGT, SLT, and friends using CMP, SEL instead of CMP, MOV,
 MOV.

---
 src/mesa/drivers/dri/i965/brw_vs_emit.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index 14c3b936b7..d16e916832 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -384,9 +384,8 @@ static void emit_sop( struct brw_vs_compile *c,
 {
    struct brw_compile *p = &c->func;
 
-   brw_MOV(p, dst, brw_imm_f(0.0f));
-   brw_CMP(p, brw_null_reg(), cond, arg0, arg1);
-   brw_MOV(p, dst, brw_imm_f(1.0f));
+   brw_CMP(p, brw_null_reg(), cond, arg1, arg0);
+   brw_SEL(p, dst, brw_null_reg(), brw_imm_f(1.0f));
    brw_set_predicate_control_flag_value(p, 0xff);
 }
 
-- 
cgit v1.2.3


From 46450c1f3f93bf4dc96696fc7e0f0eb808d9c08a Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 10 Mar 2010 17:38:33 -0800
Subject: i965: Do FS SLT, SGT, and friends using CMP, SEL instead of CMP, MOV,
 MOV.

---
 src/mesa/drivers/dri/i965/brw_wm_emit.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index 3a4057bb6b..438fcc7178 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -534,11 +534,8 @@ void emit_sop(struct brw_compile *p,
    for (i = 0; i < 4; i++) {
       if (mask & (1<<i)) {	
 	 brw_push_insn_state(p);
-	 brw_CMP(p, brw_null_reg(), cond, arg0[i], arg1[i]);
-	 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
-	 brw_MOV(p, dst[i], brw_imm_f(0));
-	 brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
-	 brw_MOV(p, dst[i], brw_imm_f(1.0));
+	 brw_CMP(p, brw_null_reg(), cond, arg1[i], arg0[i]);
+	 brw_SEL(p, dst[i], brw_null_reg(), brw_imm_f(1.0));
 	 brw_pop_insn_state(p);
       }
    }
-- 
cgit v1.2.3


From f4f2737e8767d3808d876c3f7e65ca9f48faf624 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 10 Mar 2010 18:48:23 -0800
Subject: i965: Clarify that DELTAXY always occurs for both X and Y.

---
 src/mesa/drivers/dri/i965/brw_wm_emit.c | 27 +++++++++++++--------------
 1 file changed, 13 insertions(+), 14 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index 438fcc7178..2d1d011e55 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -125,23 +125,22 @@ void emit_delta_xy(struct brw_compile *p,
 {
    struct brw_reg r1 = brw_vec1_grf(1, 0);
 
+   if (mask == 0)
+      return;
+
+   assert(mask == WRITEMASK_XY);
+
    /* Calc delta X,Y by subtracting origin in r1 from the pixel
     * centers.
     */
-   if (mask & WRITEMASK_X) {
-      brw_ADD(p,
-	      dst[0],
-	      retype(arg0[0], BRW_REGISTER_TYPE_UW),
-	      negate(r1));
-   }
-
-   if (mask & WRITEMASK_Y) {
-      brw_ADD(p,
-	      dst[1],
-	      retype(arg0[1], BRW_REGISTER_TYPE_UW),
-	      negate(suboffset(r1,1)));
-
-   }
+   brw_ADD(p,
+	   dst[0],
+	   retype(arg0[0], BRW_REGISTER_TYPE_UW),
+	   negate(r1));
+   brw_ADD(p,
+	   dst[1],
+	   retype(arg0[1], BRW_REGISTER_TYPE_UW),
+	   negate(suboffset(r1,1)));
 }
 
 void emit_wpos_xy(struct brw_wm_compile *c,
-- 
cgit v1.2.3


From f1d6baee0b02aaac34f9476eee92469281336b26 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 12 Mar 2010 15:10:22 -0800
Subject: i965: Clarify the roles of emit_pixel_xy(), emit_delta_xy(),
 emit_wpos_xy().

---
 src/mesa/drivers/dri/i965/brw_wm_emit.c | 26 +++++++++++++++++++-------
 1 file changed, 19 insertions(+), 7 deletions(-)

(limited to 'src/mesa/drivers/dri/i965')

diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index 2d1d011e55..05e464d4b6 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -62,7 +62,13 @@ static INLINE struct brw_reg sechalf( struct brw_reg reg )
 }
 
 
-/* Payload R0:
+/**
+ * Computes the screen-space x,y position of the pixels.
+ *
+ * This will be used by emit_delta_xy() or emit_wpos_xy() for
+ * interpolation of attributes..
+ *
+ * Payload R0:
  *
  * R0.0 -- pixel mask, one bit for each of 4 pixels in 4 tiles,
  *         corresponding to each of the 16 execution channels.
@@ -77,7 +83,6 @@ static INLINE struct brw_reg sechalf( struct brw_reg reg )
  * R1.7 -- ?
  * R1.8 -- ?
  */
-
 void emit_pixel_xy(struct brw_wm_compile *c,
 		   const struct brw_reg *dst,
 		   GLuint mask)
@@ -117,7 +122,14 @@ void emit_pixel_xy(struct brw_wm_compile *c,
    brw_pop_insn_state(p);
 }
 
-
+/**
+ * Computes the screen-space x,y distance of the pixels from the start
+ * vertex.
+ *
+ * This will be used in linterp or pinterp with the start vertex value
+ * and the Cx, Cy, and C0 coefficients passed in from the setup engine
+ * to produce interpolated attribute values.
+ */
 void emit_delta_xy(struct brw_compile *p,
 		   const struct brw_reg *dst,
 		   GLuint mask,
@@ -131,7 +143,7 @@ void emit_delta_xy(struct brw_compile *p,
    assert(mask == WRITEMASK_XY);
 
    /* Calc delta X,Y by subtracting origin in r1 from the pixel
-    * centers.
+    * centers produced by emit_pixel_xy().
     */
    brw_ADD(p,
 	   dst[0],
@@ -143,6 +155,9 @@ void emit_delta_xy(struct brw_compile *p,
 	   negate(suboffset(r1,1)));
 }
 
+/**
+ * Computes the pixel offset from the window origin for gl_FragCoord().
+ */
 void emit_wpos_xy(struct brw_wm_compile *c,
 		  const struct brw_reg *dst,
 		  GLuint mask,
@@ -150,9 +165,6 @@ void emit_wpos_xy(struct brw_wm_compile *c,
 {
    struct brw_compile *p = &c->func;
 
-   /* Calculate the pixel offset from window bottom left into destination
-    * X and Y channels.
-    */
    if (mask & WRITEMASK_X) {
       if (c->fp->program.PixelCenterInteger) {
 	 /* X' = X */
-- 
cgit v1.2.3