From 18c3b754f974751550dc9505d50535365beac8f3 Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Fri, 17 Sep 2010 15:08:09 +0800 Subject: i965: sandybridge pipe control workaround before write cache flush Must issue a pipe control with any non-zero post sync op before write cache flush = 1 pipe control. --- src/mesa/drivers/dri/intel/intel_batchbuffer.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/intel/intel_batchbuffer.c') diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c index ff741fc39a..9b39823917 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c @@ -264,10 +264,18 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch) struct intel_context *intel = batch->intel; if (intel->gen >= 6) { - BEGIN_BATCH(4); + BEGIN_BATCH(8); + + /* XXX workaround: issue any post sync != 0 before write cache flush = 1 */ + OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE); + OUT_BATCH(0); /* write address */ + OUT_BATCH(0); /* write data */ + OUT_BATCH(_3DSTATE_PIPE_CONTROL); OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH | PIPE_CONTROL_WRITE_FLUSH | + PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_NO_WRITE); OUT_BATCH(0); /* write address */ OUT_BATCH(0); /* write data */ -- cgit v1.2.3