From 8e0f40d28777f1ae599a95312788fe29a0515a0d Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 3 Nov 2009 17:18:36 -0800 Subject: intel: Use PIPE_CONTROL on gen4 hardware for doing pipeline flushing. This should do all the things that MI_FLUSH did, but it can be pipelined so that further rendering isn't blocked on the flush completion unless necessary. --- src/mesa/drivers/dri/intel/intel_context.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/mesa/drivers/dri/intel/intel_context.h') diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index 2fc224e51a..84fbfc564c 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -117,8 +117,6 @@ struct intel_context struct intel_region * depth_region, GLuint num_regions); - GLuint (*flush_cmd) (void); - void (*reduced_primitive_state) (struct intel_context * intel, GLenum rprim); -- cgit v1.2.3