From a736d3f4399a99b54d6af140f2227253f2ee262b Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Thu, 12 Nov 2009 15:36:02 -0800 Subject: intel: Remove unused enable_imaging parameter to intelInitExtensions --- src/mesa/drivers/dri/intel/intel_extensions.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri/intel/intel_extensions.c') diff --git a/src/mesa/drivers/dri/intel/intel_extensions.c b/src/mesa/drivers/dri/intel/intel_extensions.c index b6754c9fcb..d8a3981b53 100644 --- a/src/mesa/drivers/dri/intel/intel_extensions.c +++ b/src/mesa/drivers/dri/intel/intel_extensions.c @@ -194,15 +194,13 @@ static const struct dri_extension fragment_shader_extensions[] = { * extensions for a context. */ void -intelInitExtensions(GLcontext *ctx, GLboolean enable_imaging) +intelInitExtensions(GLcontext *ctx) { struct intel_context *intel = ctx?intel_context(ctx):NULL; /* Disable imaging extension until convolution is working in teximage paths. */ - enable_imaging = GL_FALSE; - - driInitExtensions(ctx, card_extensions, enable_imaging); + driInitExtensions(ctx, card_extensions, GL_FALSE); if (intel == NULL || intel->ttm) driInitExtensions(ctx, ttm_extensions, GL_FALSE); -- cgit v1.2.3 From b6b753f72728b734fc9886f4ec513ae09e6b269d Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Thu, 12 Nov 2009 15:39:59 -0800 Subject: intel: Don't check for context pointer to be NULL during extension init Thanks to Chia-I Wu's changes to the extension function infrastructure, we no longer have to tell the loader which extensions the driver might enable. This means that intelInitExtensions will never be called with a NULL context pointer. Remove all the NULL checks. Signed-off-by: Ian Romanick Reviewed-by: Eric Anholt --- src/mesa/drivers/dri/intel/intel_extensions.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) (limited to 'src/mesa/drivers/dri/intel/intel_extensions.c') diff --git a/src/mesa/drivers/dri/intel/intel_extensions.c b/src/mesa/drivers/dri/intel/intel_extensions.c index d8a3981b53..1682e115cc 100644 --- a/src/mesa/drivers/dri/intel/intel_extensions.c +++ b/src/mesa/drivers/dri/intel/intel_extensions.c @@ -196,27 +196,26 @@ static const struct dri_extension fragment_shader_extensions[] = { void intelInitExtensions(GLcontext *ctx) { - struct intel_context *intel = ctx?intel_context(ctx):NULL; + struct intel_context *intel = intel_context(ctx); /* Disable imaging extension until convolution is working in teximage paths. */ driInitExtensions(ctx, card_extensions, GL_FALSE); - if (intel == NULL || intel->ttm) + if (intel->ttm) driInitExtensions(ctx, ttm_extensions, GL_FALSE); - if (intel == NULL || IS_965(intel->intelScreen->deviceID)) + if (IS_965(intel->intelScreen->deviceID)) driInitExtensions(ctx, brw_extensions, GL_FALSE); - if (intel == NULL || IS_915(intel->intelScreen->deviceID) + if (IS_915(intel->intelScreen->deviceID) || IS_945(intel->intelScreen->deviceID)) { driInitExtensions(ctx, i915_extensions, GL_FALSE); - if (intel == NULL || driQueryOptionb(&intel->optionCache, "fragment_shader")) + if (driQueryOptionb(&intel->optionCache, "fragment_shader")) driInitExtensions(ctx, fragment_shader_extensions, GL_FALSE); - if (intel == NULL || driQueryOptionb(&intel->optionCache, - "stub_occlusion_query")) + if (driQueryOptionb(&intel->optionCache, "stub_occlusion_query")) driInitExtensions(ctx, arb_oq_extensions, GL_FALSE); } } -- cgit v1.2.3 From 827ba44f6ee83ab21c6a2b09323f6f1df4a7d4c8 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 18 Nov 2009 18:15:25 +0100 Subject: intel: Remove non-GEM support. This really isn't supported at this point. GEM's been in the kernel for a year, and the fake bufmgr never really worked. --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 8 ---- src/mesa/drivers/dri/intel/intel_batchbuffer.c | 4 +- src/mesa/drivers/dri/intel/intel_context.c | 38 ++++------------- src/mesa/drivers/dri/intel/intel_context.h | 6 --- src/mesa/drivers/dri/intel/intel_extensions.c | 14 ++----- src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 16 +++----- src/mesa/drivers/dri/intel/intel_regions.c | 57 +++++--------------------- src/mesa/drivers/dri/intel/intel_screen.c | 38 ++++------------- src/mesa/drivers/dri/intel/intel_screen.h | 1 - src/mesa/drivers/dri/intel/intel_span.c | 13 ++---- 10 files changed, 43 insertions(+), 152 deletions(-) (limited to 'src/mesa/drivers/dri/intel/intel_extensions.c') diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 271a88dae0..7c796dae93 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -243,14 +243,6 @@ static void wrap_buffers( struct brw_context *brw, dri_bo_unreference(brw->vb.upload.bo); brw->vb.upload.bo = dri_bo_alloc(brw->intel.bufmgr, "temporary VBO", size, 1); - - /* Set the internal VBO\ to no-backing-store. We only use them as a - * temporary within a brw_try_draw_prims while the lock is held. - */ - /* DON'T DO THIS AS IF WE HAVE TO RE-ORG MEMORY WE NEED SOMEWHERE WITH - FAKE TO PUSH THIS STUFF */ -// if (!brw->intel.ttm) -// dri_bo_fake_disable_backing_store(brw->vb.upload.bo, NULL, NULL); } static void get_space( struct brw_context *brw, diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c index 12c5a30d6b..2eae9b66d8 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c @@ -80,7 +80,7 @@ intel_batchbuffer_reset(struct intel_batchbuffer *batch) batch->buf = NULL; } - if (!batch->buffer && intel->ttm == GL_TRUE) + if (!batch->buffer) batch->buffer = malloc (intel->maxBatchSize); batch->buf = dri_bo_alloc(intel->bufmgr, "batchbuffer", @@ -212,7 +212,7 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file, batch->reserved_space = 0; /* Emit a flush if the bufmgr doesn't do it for us. */ - if (intel->always_flush_cache || !intel->ttm) { + if (intel->always_flush_cache) { intel_batchbuffer_emit_mi_flush(batch); used = batch->ptr - batch->map; } diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index 7b7c0a0b5a..1434ae530b 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -176,9 +176,7 @@ intelGetString(GLcontext * ctx, GLenum name) break; } - (void) driGetRendererString(buffer, chipset, - (intel->ttm) ? DRIVER_DATE_GEM : DRIVER_DATE, - 0); + (void) driGetRendererString(buffer, chipset, DRIVER_DATE_GEM, 0); return (GLubyte *) buffer; default: @@ -601,6 +599,7 @@ intelInitContext(struct intel_context *intel, __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; intelScreenPrivate *intelScreen = (intelScreenPrivate *) sPriv->private; int fthrottle_mode; + int bo_reuse_mode; if (!_mesa_initialize_context(&intel->ctx, mesaVis, shareCtx, functions, (void *) intel)) { @@ -635,18 +634,14 @@ intelInitContext(struct intel_context *intel, intel->maxBatchSize = BATCH_SZ; intel->bufmgr = intelScreen->bufmgr; - intel->ttm = intelScreen->ttm; - if (intel->ttm) { - int bo_reuse_mode; - bo_reuse_mode = driQueryOptioni(&intel->optionCache, "bo_reuse"); - switch (bo_reuse_mode) { - case DRI_CONF_BO_REUSE_DISABLED: - break; - case DRI_CONF_BO_REUSE_ALL: - intel_bufmgr_gem_enable_reuse(intel->bufmgr); - break; - } + bo_reuse_mode = driQueryOptioni(&intel->optionCache, "bo_reuse"); + switch (bo_reuse_mode) { + case DRI_CONF_BO_REUSE_DISABLED: + break; + case DRI_CONF_BO_REUSE_ALL: + intel_bufmgr_gem_enable_reuse(intel->bufmgr); + break; } /* This doesn't yet catch all non-conformant rendering, but it's a @@ -1052,21 +1047,6 @@ intelContendedLock(struct intel_context *intel, GLuint flags) sarea->ctxOwner = me; } - /* If the last consumer of the texture memory wasn't us, notify the fake - * bufmgr and record the new owner. We should have the memory shared - * between contexts of a single fake bufmgr, but this will at least make - * things correct for now. - */ - if (!intel->ttm && sarea->texAge != intel->hHWContext) { - sarea->texAge = intel->hHWContext; - intel_bufmgr_fake_contended_lock_take(intel->bufmgr); - if (INTEL_DEBUG & DEBUG_BATCH) - intel_decode_context_reset(); - if (INTEL_DEBUG & DEBUG_BUFMGR) - fprintf(stderr, "Lost Textures: sarea->texAge %x hw context %x\n", - sarea->ctxOwner, intel->hHWContext); - } - /* Drawable changed? */ if (dPriv && intel->lastStamp != dPriv->lastStamp) { diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index f16f502c1d..481202c971 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -181,12 +181,6 @@ struct intel_context struct intel_region *back_region; struct intel_region *depth_region; - /** - * This value indicates that the kernel memory manager is being used - * instead of the fake client-side memory manager. - */ - GLboolean ttm; - struct intel_batchbuffer *batch; drm_intel_bo *first_post_swapbuffers_batch; GLboolean no_batch_wrap; diff --git a/src/mesa/drivers/dri/intel/intel_extensions.c b/src/mesa/drivers/dri/intel/intel_extensions.c index 1682e115cc..f5fe543b5d 100644 --- a/src/mesa/drivers/dri/intel/intel_extensions.c +++ b/src/mesa/drivers/dri/intel/intel_extensions.c @@ -79,6 +79,7 @@ static const struct dri_extension card_extensions[] = { { "GL_ARB_half_float_pixel", NULL }, { "GL_ARB_map_buffer_range", GL_ARB_map_buffer_range_functions }, { "GL_ARB_multitexture", NULL }, + { "GL_ARB_pixel_buffer_object", NULL }, { "GL_ARB_point_parameters", GL_ARB_point_parameters_functions }, { "GL_ARB_point_sprite", NULL }, { "GL_ARB_shader_objects", GL_ARB_shader_objects_functions }, @@ -104,6 +105,8 @@ static const struct dri_extension card_extensions[] = { { "GL_EXT_blend_logic_op", NULL }, { "GL_EXT_blend_subtract", NULL }, { "GL_EXT_cull_vertex", GL_EXT_cull_vertex_functions }, + { "GL_EXT_framebuffer_blit", GL_EXT_framebuffer_blit_functions }, + { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, { "GL_EXT_fog_coord", GL_EXT_fog_coord_functions }, { "GL_EXT_gpu_program_parameters", GL_EXT_gpu_program_parameters_functions }, { "GL_EXT_packed_depth_stencil", NULL }, @@ -176,14 +179,6 @@ static const struct dri_extension arb_oq_extensions[] = { { NULL, NULL } }; - -static const struct dri_extension ttm_extensions[] = { - { "GL_ARB_pixel_buffer_object", NULL }, - { "GL_EXT_framebuffer_blit", GL_EXT_framebuffer_blit_functions }, - { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, - { NULL, NULL } -}; - static const struct dri_extension fragment_shader_extensions[] = { { "GL_ARB_fragment_shader", NULL }, { NULL, NULL } @@ -202,9 +197,6 @@ intelInitExtensions(GLcontext *ctx) */ driInitExtensions(ctx, card_extensions, GL_FALSE); - if (intel->ttm) - driInitExtensions(ctx, ttm_extensions, GL_FALSE); - if (IS_965(intel->intelScreen->deviceID)) driInitExtensions(ctx, brw_extensions, GL_FALSE); diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index abb3024bfb..6a565f80cf 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -224,16 +224,12 @@ int intel_miptree_pitch_align (struct intel_context *intel, if (!mt->compressed) { int pitch_align; - if (intel->ttm) { - /* XXX: Align pitch to multiple of 64 bytes for now to allow - * render-to-texture to work in all cases. This should probably be - * replaced at some point by some scheme to only do this when really - * necessary. - */ - pitch_align = 64; - } else { - pitch_align = 4; - } + /* XXX: Align pitch to multiple of 64 bytes for now to allow + * render-to-texture to work in all cases. This should probably be + * replaced at some point by some scheme to only do this when really + * necessary. + */ + pitch_align = 64; if (tiling == I915_TILING_X) pitch_align = 512; diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c index 80975163d4..d6b9dc4446 100644 --- a/src/mesa/drivers/dri/intel/intel_regions.c +++ b/src/mesa/drivers/dri/intel/intel_regions.c @@ -542,55 +542,18 @@ intel_recreate_static(struct intel_context *intel, region->buffer = NULL; } - if (intel->ttm) { - assert(region_desc->bo_handle != -1); - region->buffer = intel_bo_gem_create_from_name(intel->bufmgr, - name, - region_desc->bo_handle); - - ret = dri_bo_get_tiling(region->buffer, ®ion->tiling, - ®ion->bit_6_swizzle); - if (ret != 0) { - fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n", - region_desc->bo_handle, name, strerror(-ret)); - intel_region_release(®ion); - return NULL; - } - } else { - if (region->classic_map != NULL) { - drmUnmap(region->classic_map, - region->pitch * region->cpp * region->height); - region->classic_map = NULL; - } - ret = drmMap(intel->driFd, region_desc->handle, - region->pitch * region->cpp * region->height, - ®ion->classic_map); - if (ret != 0) { - fprintf(stderr, "Failed to drmMap %s buffer\n", name); - free(region); - return NULL; - } - - region->buffer = intel_bo_fake_alloc_static(intel->bufmgr, + assert(region_desc->bo_handle != -1); + region->buffer = intel_bo_gem_create_from_name(intel->bufmgr, name, - region_desc->offset, - region->pitch * region->cpp * - region->height, - region->classic_map); - - /* The sarea just gives us a boolean for whether it's tiled or not, - * instead of which tiling mode it is. Guess. - */ - if (region_desc->tiled) { - if (intel->gen >= 4 && region_desc == &intelScreen->depth) - region->tiling = I915_TILING_Y; - else - region->tiling = I915_TILING_X; - } else { - region->tiling = I915_TILING_NONE; - } + region_desc->bo_handle); - region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE; + ret = dri_bo_get_tiling(region->buffer, ®ion->tiling, + ®ion->bit_6_swizzle); + if (ret != 0) { + fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n", + region_desc->bo_handle, name, strerror(-ret)); + intel_region_release(®ion); + return NULL; } assert(region->buffer != NULL); diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index 789135b49f..2c5a884a9b 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -605,7 +605,6 @@ intelFillInModes(__DRIscreenPrivate *psp, static GLboolean intel_init_bufmgr(intelScreenPrivate *intelScreen) { - GLboolean gem_disable = getenv("INTEL_NO_GEM") != NULL; int gem_kernel = 0; GLboolean gem_supported; struct drm_i915_getparam gp; @@ -622,43 +621,24 @@ intel_init_bufmgr(intelScreenPrivate *intelScreen) /* If we've got a new enough DDX that's initializing GEM and giving us * object handles for the shared buffers, use that. */ - intelScreen->ttm = GL_FALSE; if (intelScreen->driScrnPriv->dri2.enabled) gem_supported = GL_TRUE; else if (intelScreen->driScrnPriv->ddx_version.minor >= 9 && gem_kernel && intelScreen->front.bo_handle != -1) gem_supported = GL_TRUE; - else - gem_supported = GL_FALSE; - - if (!gem_disable && gem_supported) { - intelScreen->bufmgr = intel_bufmgr_gem_init(spriv->fd, BATCH_SZ); - if (intelScreen->bufmgr != NULL) - intelScreen->ttm = GL_TRUE; + else { + fprintf(stderr, "[%s:%u] Error initializing GEM.\n", + __func__, __LINE__); + return GL_FALSE; } + + intelScreen->bufmgr = intel_bufmgr_gem_init(spriv->fd, BATCH_SZ); /* Otherwise, use the classic buffer manager. */ if (intelScreen->bufmgr == NULL) { - if (gem_disable) { - _mesa_warning(NULL, "GEM disabled. Using classic."); - } else { - _mesa_warning(NULL, - "Failed to initialize GEM. Falling back to classic."); - } - - if (intelScreen->tex.size == 0) { - fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n", - __func__, __LINE__); - return GL_FALSE; - } - - intelScreen->bufmgr = - intel_bufmgr_fake_init(spriv->fd, - intelScreen->tex.offset, - intelScreen->tex.map, - intelScreen->tex.size, - (unsigned int * volatile) - &intelScreen->sarea->last_dispatch); + fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n", + __func__, __LINE__); + return GL_FALSE; } if (intel_get_param(spriv, I915_PARAM_NUM_FENCES_AVAIL, &num_fences)) diff --git a/src/mesa/drivers/dri/intel/intel_screen.h b/src/mesa/drivers/dri/intel/intel_screen.h index a9b9e109a6..14ca0903b6 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.h +++ b/src/mesa/drivers/dri/intel/intel_screen.h @@ -77,7 +77,6 @@ typedef struct GLboolean no_hw; GLboolean no_vbo; - int ttm; dri_bufmgr *bufmgr; GLboolean kernel_exec_fencing; diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index 3607c7dded..2c89a66a95 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -613,15 +613,7 @@ intel_set_span_functions(struct intel_context *intel, struct gl_renderbuffer *rb) { struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb; - uint32_t tiling; - - /* If in GEM mode, we need to do the tile address swizzling ourselves, - * instead of the fence registers handling it. - */ - if (intel->ttm) - tiling = irb->region->tiling; - else - tiling = I915_TILING_NONE; + uint32_t tiling = irb->region->tiling; if (intel->intelScreen->kernel_exec_fencing) { switch (irb->texformat) { @@ -673,6 +665,9 @@ intel_set_span_functions(struct intel_context *intel, return; } + /* If in GEM mode, we need to do the tile address swizzling ourselves, + * instead of the fence registers handling it. + */ switch (irb->texformat) { case MESA_FORMAT_RGB565: switch (tiling) { -- cgit v1.2.3 From d8da270a2be18849eee8a168d1c1528e96677b41 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 24 Nov 2009 11:59:23 -0800 Subject: intel: Remove GL_NV_point_sprite from extension list i830 does not (and cannot!) support the any of the non-default GL_POINT_SPRITE_R_MODE_NV settings. i915 and i965 could, but currently do not. In both cases it would require mucking about with the fragment shader. --- src/mesa/drivers/dri/intel/intel_extensions.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mesa/drivers/dri/intel/intel_extensions.c') diff --git a/src/mesa/drivers/dri/intel/intel_extensions.c b/src/mesa/drivers/dri/intel/intel_extensions.c index 2e61c556d8..877f5b5971 100644 --- a/src/mesa/drivers/dri/intel/intel_extensions.c +++ b/src/mesa/drivers/dri/intel/intel_extensions.c @@ -114,7 +114,6 @@ static const struct dri_extension card_extensions[] = { { "GL_MESA_pack_invert", NULL }, { "GL_MESA_ycbcr_texture", NULL }, { "GL_NV_blend_square", NULL }, - { "GL_NV_point_sprite", GL_NV_point_sprite_functions }, { "GL_NV_vertex_program", GL_NV_vertex_program_functions }, { "GL_NV_vertex_program1_1", NULL }, { "GL_SGIS_generate_mipmap", NULL }, -- cgit v1.2.3 From cb3810dd19760797e699c47929f655b829c4d339 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 16 Dec 2009 15:42:55 -0800 Subject: intel: Replace IS_965 checks with context structure usage. Saves another 600 bytes or so of code. --- src/mesa/drivers/dri/i965/brw_clip_line.c | 9 +++++---- src/mesa/drivers/dri/i965/brw_clip_tri.c | 3 ++- src/mesa/drivers/dri/i965/brw_context.c | 4 ++-- src/mesa/drivers/dri/i965/brw_context.h | 2 ++ src/mesa/drivers/dri/i965/brw_defines.h | 3 --- src/mesa/drivers/dri/i965/brw_misc_state.c | 4 ++-- src/mesa/drivers/dri/i965/brw_vs_emit.c | 7 ++++--- src/mesa/drivers/dri/intel/intel_extensions.c | 2 +- 8 files changed, 18 insertions(+), 16 deletions(-) (limited to 'src/mesa/drivers/dri/intel/intel_extensions.c') diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c b/src/mesa/drivers/dri/i965/brw_clip_line.c index 59727af88d..afc0b11049 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_line.c +++ b/src/mesa/drivers/dri/i965/brw_clip_line.c @@ -127,6 +127,7 @@ static void brw_clip_line_alloc_regs( struct brw_clip_compile *c ) static void clip_and_emit_line( struct brw_clip_compile *c ) { struct brw_compile *p = &c->func; + struct brw_context *brw = p->brw; struct brw_indirect vtx0 = brw_indirect(0, 0); struct brw_indirect vtx1 = brw_indirect(1, 0); struct brw_indirect newvtx0 = brw_indirect(2, 0); @@ -153,7 +154,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c ) brw_clip_init_clipmask(c); /* -ve rhw workaround */ - if (BRW_IS_965(p->brw)) { + if (brw->has_negative_rhw_bug) { brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<20)); @@ -190,7 +191,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c ) * Both can be negative on GM965/G965 due to RHW workaround * if so, this object should be rejected. */ - if (BRW_IS_965(p->brw)) { + if (brw->has_negative_rhw_bug) { brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE, c->reg.dp0, brw_imm_f(0.0)); is_neg2 = brw_IF(p, BRW_EXECUTE_1); { @@ -215,7 +216,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c ) /* If both are positive, do nothing */ /* Only on GM965/G965 */ - if (BRW_IS_965(p->brw)) { + if (brw->has_negative_rhw_bug) { brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.dp0, brw_imm_f(0.0)); is_neg2 = brw_IF(p, BRW_EXECUTE_1); } @@ -230,7 +231,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c ) brw_set_predicate_control(p, BRW_PREDICATE_NONE); } - if (BRW_IS_965(p->brw)) { + if (brw->has_negative_rhw_bug) { brw_ENDIF(p, is_neg2); } } diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c b/src/mesa/drivers/dri/i965/brw_clip_tri.c index ec15e9a697..cfbb8f2686 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_tri.c +++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c @@ -572,6 +572,7 @@ void brw_emit_tri_clip( struct brw_clip_compile *c ) { struct brw_instruction *neg_rhw; struct brw_compile *p = &c->func; + struct brw_context *brw = p->brw; brw_clip_tri_alloc_regs(c, 3 + c->key.nr_userclip + 6); brw_clip_tri_init_vertices(c); brw_clip_init_clipmask(c); @@ -579,7 +580,7 @@ void brw_emit_tri_clip( struct brw_clip_compile *c ) /* if -ve rhw workaround bit is set, do cliptest */ - if (BRW_IS_965(p->brw)) { + if (brw->has_negative_rhw_bug) { brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<20)); diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 282566f8d5..d8af2c512b 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -163,11 +163,10 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis, brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_GM45; brw->has_surface_tile_offset = GL_TRUE; brw->has_compr4 = GL_TRUE; + brw->has_aa_line_parameters = GL_TRUE; } else { brw->CMD_VF_STATISTICS = CMD_VF_STATISTICS_965; brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_965; - brw->has_surface_tile_offset = GL_FALSE; - brw->has_compr4 = GL_FALSE; } /* WM maximum threads is number of EUs times number of threads per EU. */ @@ -183,6 +182,7 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis, brw->urb.size = 256; brw->vs_max_threads = 16; brw->wm_max_threads = 8 * 4; + brw->has_negative_rhw_bug = GL_TRUE; } if (INTEL_DEBUG & DEBUG_SINGLE_THREAD) { diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 4ae48bba05..ea5503e2fe 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -440,6 +440,8 @@ struct brw_context GLboolean emit_state_always; GLboolean has_surface_tile_offset; GLboolean has_compr4; + GLboolean has_negative_rhw_bug; + GLboolean has_aa_line_parameters; ; struct { struct brw_state_flags dirty; diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 2ee331a200..ea0d7e05d4 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -832,7 +832,4 @@ #include "intel_chipset.h" -#define BRW_IS_965(brw) (!(brw)->intel.is_g4x && \ - !(brw)->intel.is_ironlake) - #endif diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index fd14eaa612..d437b1e030 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -374,8 +374,8 @@ const struct brw_tracked_state brw_polygon_stipple_offset = { static void upload_aa_line_parameters(struct brw_context *brw) { struct brw_aa_line_parameters balp; - - if (BRW_IS_965(brw)) + + if (!brw->has_aa_line_parameters) return; /* use legacy aa line coverage computation */ diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 21d2fec707..1b84dd505f 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -1114,7 +1114,8 @@ static void emit_swz( struct brw_vs_compile *c, static void emit_vertex_write( struct brw_vs_compile *c) { struct brw_compile *p = &c->func; - struct intel_context *intel = &p->brw->intel; + struct brw_context *brw = p->brw; + struct intel_context *intel = &brw->intel; struct brw_reg m0 = brw_message_reg(0); struct brw_reg pos = c->regs[PROGRAM_OUTPUT][VERT_RESULT_HPOS]; struct brw_reg ndc; @@ -1138,7 +1139,7 @@ static void emit_vertex_write( struct brw_vs_compile *c) * workaround. */ if ((c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_PSIZ)) || - c->key.nr_userclip || BRW_IS_965(p->brw)) + c->key.nr_userclip || brw->has_negative_rhw_bug) { struct brw_reg header1 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD); GLuint i; @@ -1169,7 +1170,7 @@ static void emit_vertex_write( struct brw_vs_compile *c) * Later, clipping will detect ucp[6] and ensure the primitive is * clipped against all fixed planes. */ - if (BRW_IS_965(p->brw)) { + if (brw->has_negative_rhw_bug) { brw_CMP(p, vec8(brw_null_reg()), BRW_CONDITIONAL_L, diff --git a/src/mesa/drivers/dri/intel/intel_extensions.c b/src/mesa/drivers/dri/intel/intel_extensions.c index 86dc42cc51..bb50531d98 100644 --- a/src/mesa/drivers/dri/intel/intel_extensions.c +++ b/src/mesa/drivers/dri/intel/intel_extensions.c @@ -196,7 +196,7 @@ intelInitExtensions(GLcontext *ctx) */ driInitExtensions(ctx, card_extensions, GL_FALSE); - if (IS_965(intel->intelScreen->deviceID)) + if (intel->gen >= 4) driInitExtensions(ctx, brw_extensions, GL_FALSE); if (IS_915(intel->intelScreen->deviceID) -- cgit v1.2.3 From f67748038935e609aa85450b20d550b4813c9429 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 16 Dec 2009 15:50:40 -0800 Subject: intel: Replace some gen3 IS_* checks with context structure usage. Shaves 400 bytes or so from i915_dri.so. --- src/mesa/drivers/dri/i915/i915_vtbl.c | 2 +- src/mesa/drivers/dri/i915/intel_tris.c | 4 ++-- src/mesa/drivers/dri/intel/intel_context.c | 10 +++++++--- src/mesa/drivers/dri/intel/intel_context.h | 1 + src/mesa/drivers/dri/intel/intel_extensions.c | 3 +-- src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 2 +- 6 files changed, 13 insertions(+), 9 deletions(-) (limited to 'src/mesa/drivers/dri/intel/intel_extensions.c') diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index ba6be9796e..9f7635a953 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -611,7 +611,7 @@ i915_state_draw_region(struct intel_context *intel, * the value of this bit, the pipeline needs to be MI_FLUSHed. And it * can only be set when a depth buffer is already defined. */ - if (IS_945(intel->intelScreen->deviceID) && intel->use_early_z && + if (intel->is_945 && intel->use_early_z && depth_region->tiling != I915_TILING_NONE) value |= CLASSIC_EARLY_DEPTH; diff --git a/src/mesa/drivers/dri/i915/intel_tris.c b/src/mesa/drivers/dri/i915/intel_tris.c index 8a3ab39bc2..63c5ae96dc 100644 --- a/src/mesa/drivers/dri/i915/intel_tris.c +++ b/src/mesa/drivers/dri/i915/intel_tris.c @@ -221,7 +221,7 @@ void intel_flush_prim(struct intel_context *intel) intel->prim.count = 0; offset = intel->prim.start_offset; intel->prim.start_offset = intel->prim.current_offset; - if (!IS_9XX(intel->intelScreen->deviceID)) + if (!intel->gen >= 3) intel->prim.start_offset = ALIGN(intel->prim.start_offset, 128); intel->prim.flush = NULL; @@ -251,7 +251,7 @@ void intel_flush_prim(struct intel_context *intel) intel->vertex_size * 4); #endif - if (IS_9XX(intel->intelScreen->deviceID)) { + if (intel->gen >= 3) { BEGIN_BATCH(5, LOOP_CLIPRECTS); OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(0) | I1_LOAD_S(1) | 1); diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index 6f567dc4d0..02e0cc7b33 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -613,12 +613,16 @@ intelInitContext(struct intel_context *intel, intel->sarea = intelScreen->sarea; intel->driContext = driContextPriv; - if (IS_965(intel->intelScreen->deviceID)) + if (IS_965(intel->intelScreen->deviceID)) { intel->gen = 4; - else if (IS_9XX(intel->intelScreen->deviceID)) + } else if (IS_9XX(intel->intelScreen->deviceID)) { intel->gen = 3; - else + if (IS_945(intel->intelScreen->deviceID)) { + intel->is_945 = GL_TRUE; + } + } else { intel->gen = 2; + } if (IS_IGDNG(intel->intelScreen->deviceID)) { intel->is_ironlake = GL_TRUE; diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index e46764e99c..e85886db82 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -179,6 +179,7 @@ struct intel_context GLboolean needs_ff_sync; GLboolean is_ironlake; GLboolean is_g4x; + GLboolean is_945; GLboolean has_luminance_srgb; int urb_size; diff --git a/src/mesa/drivers/dri/intel/intel_extensions.c b/src/mesa/drivers/dri/intel/intel_extensions.c index bb50531d98..5ac5ce10af 100644 --- a/src/mesa/drivers/dri/intel/intel_extensions.c +++ b/src/mesa/drivers/dri/intel/intel_extensions.c @@ -199,8 +199,7 @@ intelInitExtensions(GLcontext *ctx) if (intel->gen >= 4) driInitExtensions(ctx, brw_extensions, GL_FALSE); - if (IS_915(intel->intelScreen->deviceID) - || IS_945(intel->intelScreen->deviceID)) { + if (intel->gen == 3) { driInitExtensions(ctx, i915_extensions, GL_FALSE); if (driQueryOptionb(&intel->optionCache, "fragment_shader")) diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index 6a565f80cf..82e4150c6a 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -87,7 +87,7 @@ intel_miptree_create_internal(struct intel_context *intel, mt->pitch = 0; #ifdef I915 - if (IS_945(intel->intelScreen->deviceID)) + if (intel->is_945) ok = i945_miptree_layout(intel, mt, tiling); else ok = i915_miptree_layout(intel, mt, tiling); -- cgit v1.2.3