From 537bbe6dec780f6f85838fe7e6036579c509f8a6 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 6 May 2008 10:51:08 -0700 Subject: [intel-GEM] Add tiling support to swrast. Accessing tiled surfaces without using the fence registers requires that software deal with the address swizzling itself. --- src/mesa/drivers/dri/intel/intel_fbo.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/intel/intel_fbo.h') diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h index c90c84b48c..9e085a1992 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.h +++ b/src/mesa/drivers/dri/intel/intel_fbo.h @@ -72,6 +72,7 @@ struct intel_renderbuffer struct intel_region *region; void *pfMap; /* possibly paged flipped map pointer */ GLuint pfPitch; /* possibly paged flipped pitch */ + int tiling; GLboolean RenderToTexture; /* RTT? */ GLuint PairedDepth; /**< only used if this is a depth renderbuffer */ @@ -90,7 +91,7 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *irb, struct intel_region *region); extern struct intel_renderbuffer * -intel_create_renderbuffer(GLenum intFormat); +intel_create_renderbuffer(GLenum intFormat, int tiling); extern void intel_fbo_init(struct intel_context *intel); -- cgit v1.2.3 From 19f585a3cf65887e249d630fe43e83e7e7618dfa Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 2 Jul 2008 09:10:21 -0700 Subject: intel-gem: Fix Y-tiling span setup. The boolean that the server gives us for whether the region is tiled was getting used as the enum for what tiling mode. Instead, guess the correct tiling in screen setup. Also, fix the Y-tiling pitch setup. The pitch to the next tile in Y is 32 scanlines, not 8. --- src/mesa/drivers/dri/intel/intel_fbo.c | 13 ++++++++--- src/mesa/drivers/dri/intel/intel_fbo.h | 7 +++--- src/mesa/drivers/dri/intel/intel_screen.c | 39 ++++++++++++++++++++----------- src/mesa/drivers/dri/intel/intel_screen.h | 6 +++++ src/mesa/drivers/dri/intel/intel_span.c | 7 +++--- src/mesa/drivers/dri/intel/intel_span.h | 7 ++---- 6 files changed, 52 insertions(+), 27 deletions(-) (limited to 'src/mesa/drivers/dri/intel/intel_fbo.h') diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index bc0b579429..3a3ce68c59 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -376,7 +376,8 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *rb, * not a user-created renderbuffer. */ struct intel_renderbuffer * -intel_create_renderbuffer(GLenum intFormat, int tiling) +intel_create_renderbuffer(intelScreenPrivate *intelScreen, + GLenum intFormat, enum tiling_mode tiling) { GET_CURRENT_CONTEXT(ctx); @@ -449,8 +450,14 @@ intel_create_renderbuffer(GLenum intFormat, int tiling) irb->Base.Delete = intel_delete_renderbuffer; irb->Base.AllocStorage = intel_alloc_window_storage; irb->Base.GetPointer = intel_get_pointer; - /* This sets the Get/PutRow/Value functions */ - intel_set_span_functions(&irb->Base, tiling); + /* This sets the Get/PutRow/Value functions. In classic mode, all access + * is through the aperture and will be swizzled by the fence registers, so + * we don't need the span functions to perfom tile swizzling + */ + if (intelScreen->ttm) + intel_set_span_functions(&irb->Base, tiling); + else + intel_set_span_functions(&irb->Base, INTEL_TILE_NONE); return irb; } diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h index 9e085a1992..23af593960 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.h +++ b/src/mesa/drivers/dri/intel/intel_fbo.h @@ -28,9 +28,9 @@ #ifndef INTEL_FBO_H #define INTEL_FBO_H +#include "intel_screen.h" struct intel_context; -struct intel_region; /** * Intel framebuffer, derived from gl_framebuffer. @@ -72,7 +72,7 @@ struct intel_renderbuffer struct intel_region *region; void *pfMap; /* possibly paged flipped map pointer */ GLuint pfPitch; /* possibly paged flipped pitch */ - int tiling; + enum tiling_mode tiling; GLboolean RenderToTexture; /* RTT? */ GLuint PairedDepth; /**< only used if this is a depth renderbuffer */ @@ -91,7 +91,8 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *irb, struct intel_region *region); extern struct intel_renderbuffer * -intel_create_renderbuffer(GLenum intFormat, int tiling); +intel_create_renderbuffer(intelScreenPrivate *intelScreen, + GLenum intFormat, enum tiling_mode tiling); extern void intel_fbo_init(struct intel_context *intel); diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index 6597dbffed..9e4f48fbd7 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -528,6 +528,7 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv, GLboolean swStencil = (mesaVis->stencilBits > 0 && mesaVis->depthBits != 24); GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8); + enum tiling_mode tiling; struct intel_framebuffer *intel_fb = CALLOC_STRUCT(intel_framebuffer); @@ -537,34 +538,46 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv, _mesa_initialize_framebuffer(&intel_fb->Base, mesaVis); /* setup the hardware-based renderbuffers */ + /* We get only a boolean value from the DDX for whether tiling is + * enabled, so we have to guess when it's Y and not X (965 depth). + */ { - intel_fb->color_rb[0] = intel_create_renderbuffer(rgbFormat, - screen->ttm ? screen->front.tiled : INTEL_TILE_NONE); + tiling = screen->front.tiled ? INTEL_TILE_X : INTEL_TILE_NONE; + intel_fb->color_rb[0] = intel_create_renderbuffer(screen, + rgbFormat, tiling); _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_FRONT_LEFT, &intel_fb->color_rb[0]->Base); } if (mesaVis->doubleBufferMode) { - intel_fb->color_rb[1] = intel_create_renderbuffer(rgbFormat, - screen->ttm ? screen->back.tiled : INTEL_TILE_NONE); + tiling = screen->back.tiled ? INTEL_TILE_X : INTEL_TILE_NONE; + intel_fb->color_rb[1] = intel_create_renderbuffer(screen, + rgbFormat, tiling); + _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_BACK_LEFT, &intel_fb->color_rb[1]->Base); if (screen->third.handle) { struct gl_renderbuffer *tmp_rb = NULL; - - intel_fb->color_rb[2] = intel_create_renderbuffer(rgbFormat, - screen->ttm ? screen->third.tiled : INTEL_TILE_NONE); + tiling = screen->third.tiled ? INTEL_TILE_X : INTEL_TILE_NONE; + intel_fb->color_rb[2] = intel_create_renderbuffer(screen, + rgbFormat, + tiling); _mesa_reference_renderbuffer(&tmp_rb, &intel_fb->color_rb[2]->Base); } } +#ifdef I915 + tiling = screen->depth.tiled ? INTEL_TILE_X : INTEL_TILE_NONE; +#else + tiling = screen->depth.tiled ? INTEL_TILE_Y : INTEL_TILE_NONE; +#endif if (mesaVis->depthBits == 24) { if (mesaVis->stencilBits == 8) { /* combined depth/stencil buffer */ struct intel_renderbuffer *depthStencilRb - = intel_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT, - screen->ttm ? screen->depth.tiled : INTEL_TILE_NONE); + = intel_create_renderbuffer(screen, + GL_DEPTH24_STENCIL8_EXT, tiling); /* note: bind RB to two attachment points */ _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH, &depthStencilRb->Base); @@ -572,8 +585,8 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv, &depthStencilRb->Base); } else { struct intel_renderbuffer *depthRb - = intel_create_renderbuffer(GL_DEPTH_COMPONENT24, - screen->ttm ? screen->depth.tiled : INTEL_TILE_NONE); + = intel_create_renderbuffer(screen, + GL_DEPTH_COMPONENT24, tiling); _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH, &depthRb->Base); } @@ -581,8 +594,8 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv, else if (mesaVis->depthBits == 16) { /* just 16-bit depth buffer, no hw stencil */ struct intel_renderbuffer *depthRb - = intel_create_renderbuffer(GL_DEPTH_COMPONENT16, - screen->ttm ? screen->depth.tiled : INTEL_TILE_NONE); + = intel_create_renderbuffer(screen, + GL_DEPTH_COMPONENT16, tiling); _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH, &depthRb->Base); } diff --git a/src/mesa/drivers/dri/intel/intel_screen.h b/src/mesa/drivers/dri/intel/intel_screen.h index 9a73b13951..648bf61240 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.h +++ b/src/mesa/drivers/dri/intel/intel_screen.h @@ -33,6 +33,12 @@ #include "i915_drm.h" #include "xmlconfig.h" +enum tiling_mode { + INTEL_TILE_NONE, + INTEL_TILE_X, + INTEL_TILE_Y +}; + /* XXX: change name or eliminate to avoid conflict with "struct * intel_region"!!! */ diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index 8d7d913ca9..6138b262f4 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -168,7 +168,7 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont int x_tile_number, y_tile_number; int tile_off, tile_base; - tile_stride = (irb->pfPitch * irb->region->cpp) << 3; + tile_stride = (irb->pfPitch * irb->region->cpp) << 5; x += intel->drawX; y += intel->drawY; @@ -181,7 +181,8 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont x_tile_number = xbyte >> 7; y_tile_number = y >> 5; - tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) + (x_tile_off & 0xf); + tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) + + (x_tile_off & 0xf); tile_base = (x_tile_number << 12) + y_tile_number * tile_stride; return buf + tile_base + tile_off; @@ -670,7 +671,7 @@ intelInitSpanFuncs(GLcontext * ctx) * These are used for the software fallbacks. */ void -intel_set_span_functions(struct gl_renderbuffer *rb, int tiling) +intel_set_span_functions(struct gl_renderbuffer *rb, enum tiling_mode tiling) { if (rb->_ActualFormat == GL_RGB5) { /* 565 RGB */ diff --git a/src/mesa/drivers/dri/intel/intel_span.h b/src/mesa/drivers/dri/intel/intel_span.h index c56e5e1611..1b47c2829c 100644 --- a/src/mesa/drivers/dri/intel/intel_span.h +++ b/src/mesa/drivers/dri/intel/intel_span.h @@ -33,10 +33,7 @@ extern void intelInitSpanFuncs(GLcontext * ctx); extern void intelSpanRenderFinish(GLcontext * ctx); extern void intelSpanRenderStart(GLcontext * ctx); -extern void intel_set_span_functions(struct gl_renderbuffer *rb, int tiling); - -#define INTEL_TILE_NONE 0 -#define INTEL_TILE_X 1 -#define INTEL_TILE_Y 2 +extern void intel_set_span_functions(struct gl_renderbuffer *rb, + enum tiling_mode tiling); #endif -- cgit v1.2.3 From 2e841880cfc1006a2818d4a8bfefd21136dc39a9 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 11 Jul 2008 14:16:36 -0700 Subject: drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes. --- src/mesa/drivers/dri/i965/brw_misc_state.c | 2 +- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 37 ++++-- src/mesa/drivers/dri/intel/intel_blit.c | 24 ++-- src/mesa/drivers/dri/intel/intel_blit.h | 8 +- src/mesa/drivers/dri/intel/intel_context.c | 3 - src/mesa/drivers/dri/intel/intel_context.h | 1 - src/mesa/drivers/dri/intel/intel_fbo.c | 21 +--- src/mesa/drivers/dri/intel/intel_fbo.h | 4 +- src/mesa/drivers/dri/intel/intel_pixel_bitmap.c | 2 +- src/mesa/drivers/dri/intel/intel_pixel_copy.c | 4 +- src/mesa/drivers/dri/intel/intel_pixel_draw.c | 2 +- src/mesa/drivers/dri/intel/intel_regions.c | 129 ++++++++++++++----- src/mesa/drivers/dri/intel/intel_regions.h | 13 +- src/mesa/drivers/dri/intel/intel_screen.c | 133 ++------------------ src/mesa/drivers/dri/intel/intel_screen.h | 6 - src/mesa/drivers/dri/intel/intel_span.c | 154 ++++++++++++----------- src/mesa/drivers/dri/intel/intel_span.h | 3 - src/mesa/drivers/dri/intel/intel_tex_copy.c | 2 +- 18 files changed, 250 insertions(+), 298 deletions(-) (limited to 'src/mesa/drivers/dri/intel/intel_fbo.h') diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 9d925682c2..bd28235281 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -232,7 +232,7 @@ static void emit_depthbuffer(struct brw_context *brw) OUT_BATCH(((region->pitch * region->cpp) - 1) | (format << 18) | (BRW_TILEWALK_YMAJOR << 26) | - (region->tiled << 27) | + ((region->tiling != I915_TILING_NONE) << 27) | (BRW_SURFACE_2D << 29)); OUT_RELOC(region->buffer, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index a7da5e643c..761a5df33f 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -154,9 +154,28 @@ struct brw_wm_surface_key { GLint first_level, last_level; GLint width, height, depth; GLint pitch, cpp; - GLboolean tiled; + uint32_t tiling; }; +static void +brw_set_surface_tiling(struct brw_surface_state *surf, uint32_t tiling) +{ + switch (tiling) { + case I915_TILING_NONE: + surf->ss3.tiled_surface = 0; + surf->ss3.tile_walk = 0; + break; + case I915_TILING_X: + surf->ss3.tiled_surface = 1; + surf->ss3.tile_walk = BRW_TILEWALK_XMAJOR; + break; + case I915_TILING_Y: + surf->ss3.tiled_surface = 1; + surf->ss3.tile_walk = BRW_TILEWALK_YMAJOR; + break; + } +} + static dri_bo * brw_create_texture_surface( struct brw_context *brw, struct brw_wm_surface_key *key ) @@ -179,9 +198,7 @@ brw_create_texture_surface( struct brw_context *brw, surf.ss2.mip_count = key->last_level - key->first_level; surf.ss2.width = key->width - 1; surf.ss2.height = key->height - 1; - - surf.ss3.tile_walk = BRW_TILEWALK_XMAJOR; - surf.ss3.tiled_surface = key->tiled; + brw_set_surface_tiling(&surf, key->tiling); surf.ss3.pitch = (key->pitch * key->cpp) - 1; surf.ss3.depth = key->depth - 1; @@ -234,7 +251,7 @@ brw_update_texture_surface( GLcontext *ctx, GLuint unit ) key.pitch = intelObj->mt->pitch; key.cpp = intelObj->mt->cpp; key.depth = firstImage->Depth; - key.tiled = intelObj->mt->region->tiled; + key.tiling = intelObj->mt->region->tiling; ret |= dri_bufmgr_check_aperture_space(key.bo); @@ -267,7 +284,8 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region, unsigned int surface_format; unsigned int width, height, cpp; GLubyte color_mask[4]; - GLboolean tiled, color_blend; + GLboolean color_blend; + uint32_t tiling; } key; memset(&key, 0, sizeof(key)); @@ -280,7 +298,7 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region, key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; else key.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM; - key.tiled = region->tiled; + key.tiling = region->tiling; key.width = region->pitch; /* XXX: not really! */ key.height = region->height; key.cpp = region->cpp; @@ -289,7 +307,7 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region, } else { key.surface_type = BRW_SURFACE_NULL; key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; - key.tiled = 0; + key.tiling = 0; key.width = 1; key.height = 1; key.cpp = 4; @@ -319,8 +337,7 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region, surf.ss2.width = key.width - 1; surf.ss2.height = key.height - 1; - surf.ss3.tile_walk = BRW_TILEWALK_XMAJOR; - surf.ss3.tiled_surface = key.tiled; + brw_set_surface_tiling(&surf, key.tiling); surf.ss3.pitch = (key.width * key.cpp) - 1; /* _NEW_COLOR */ diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index 84a455d1cb..2a05d29124 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -106,11 +106,11 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv, } #ifndef I915 - if (src->tiled) { + if (src->tiling != I915_TILING_NONE) { CMD |= XY_SRC_TILED; src_pitch /= 4; } - if (dst->tiled) { + if (dst->tiling != I915_TILING_NONE) { CMD |= XY_DST_TILED; dst_pitch /= 4; } @@ -178,7 +178,7 @@ intelEmitFillBlit(struct intel_context *intel, GLshort dst_pitch, dri_bo *dst_buffer, GLuint dst_offset, - GLboolean dst_tiled, + uint32_t dst_tiling, GLshort x, GLshort y, GLshort w, GLshort h, GLuint color) @@ -203,7 +203,7 @@ intelEmitFillBlit(struct intel_context *intel, return; } #ifndef I915 - if (dst_tiled) { + if (dst_tiling != I915_TILING_NONE) { CMD |= XY_DST_TILED; dst_pitch /= 4; } @@ -259,11 +259,11 @@ intelEmitCopyBlit(struct intel_context *intel, GLshort src_pitch, dri_bo *src_buffer, GLuint src_offset, - GLboolean src_tiled, + uint32_t src_tiling, GLshort dst_pitch, dri_bo *dst_buffer, GLuint dst_offset, - GLboolean dst_tiled, + uint32_t dst_tiling, GLshort src_x, GLshort src_y, GLshort dst_x, GLshort dst_y, GLshort w, GLshort h, @@ -309,11 +309,11 @@ intelEmitCopyBlit(struct intel_context *intel, } #ifndef I915 - if (dst_tiled) { + if (dst_tiling != I915_TILING_NONE) { CMD |= XY_DST_TILED; dst_pitch /= 4; } - if (src_tiled) { + if (src_tiling != I915_TILING_NONE) { CMD |= XY_SRC_TILED; src_pitch /= 4; } @@ -512,7 +512,7 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) } #ifndef I915 - if (irb_region->tiled) { + if (irb_region->tiling != I915_TILING_NONE) { CMD |= XY_DST_TILED; pitch /= 4; } @@ -563,7 +563,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel, GLshort dst_pitch, dri_bo *dst_buffer, GLuint dst_offset, - GLboolean dst_tiled, + uint32_t dst_tiling, GLshort x, GLshort y, GLshort w, GLshort h, GLenum logic_op) @@ -593,7 +593,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel, if (cpp == 4) opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; #ifndef I915 - if (dst_tiled) { + if (dst_tiling != I915_TILING_NONE) { opcode |= XY_DST_TILED; dst_pitch /= 4; } @@ -606,7 +606,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel, br13 |= BR13_8888; blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */ - if (dst_tiled) + if (dst_tiling != I915_TILING_NONE) blit_cmd |= XY_DST_TILED; BEGIN_BATCH(8 + 3, REFERENCES_CLIPRECTS); diff --git a/src/mesa/drivers/dri/intel/intel_blit.h b/src/mesa/drivers/dri/intel/intel_blit.h index fc0620caba..0881cc4fdc 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.h +++ b/src/mesa/drivers/dri/intel/intel_blit.h @@ -42,11 +42,11 @@ extern void intelEmitCopyBlit(struct intel_context *intel, GLshort src_pitch, dri_bo *src_buffer, GLuint src_offset, - GLboolean src_tiled, + uint32_t src_tiling, GLshort dst_pitch, dri_bo *dst_buffer, GLuint dst_offset, - GLboolean dst_tiled, + uint32_t dst_tiling, GLshort srcx, GLshort srcy, GLshort dstx, GLshort dsty, GLshort w, GLshort h, @@ -57,7 +57,7 @@ extern void intelEmitFillBlit(struct intel_context *intel, GLshort dst_pitch, dri_bo *dst_buffer, GLuint dst_offset, - GLboolean dst_tiled, + uint32_t dst_tiling, GLshort x, GLshort y, GLshort w, GLshort h, GLuint color); @@ -69,7 +69,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel, GLshort dst_pitch, dri_bo *dst_buffer, GLuint dst_offset, - GLboolean dst_tiled, + uint32_t dst_tiling, GLshort x, GLshort y, GLshort w, GLshort h, GLenum logic_op); diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index fa0b4c5618..7e3f370ad0 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -703,9 +703,6 @@ intelInitContext(struct intel_context *intel, intel->no_rast = 1; } - intel->tiling_swizzle_mode = driQueryOptioni(&intel->optionCache, - "swizzle_mode"); - /* Disable all hardware rendering (skip emitting batches and fences/waits * to the kernel) */ diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index 6ed9a377e4..f1116d2747 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -266,7 +266,6 @@ struct intel_context GLuint lastStamp; GLboolean no_hw; - int tiling_swizzle_mode; /** * Configuration cache diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 3a3ce68c59..7663393fba 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -294,10 +294,6 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, rb->Width = width; rb->Height = height; - /* This sets the Get/PutRow/Value functions */ - /* XXX can we choose a different tile here? */ - intel_set_span_functions(&irb->Base, INTEL_TILE_NONE); - return GL_TRUE; } } @@ -376,8 +372,7 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *rb, * not a user-created renderbuffer. */ struct intel_renderbuffer * -intel_create_renderbuffer(intelScreenPrivate *intelScreen, - GLenum intFormat, enum tiling_mode tiling) +intel_create_renderbuffer(GLenum intFormat) { GET_CURRENT_CONTEXT(ctx); @@ -444,20 +439,10 @@ intel_create_renderbuffer(intelScreenPrivate *intelScreen, irb->Base.InternalFormat = intFormat; - irb->tiling = tiling; - /* intel-specific methods */ irb->Base.Delete = intel_delete_renderbuffer; irb->Base.AllocStorage = intel_alloc_window_storage; irb->Base.GetPointer = intel_get_pointer; - /* This sets the Get/PutRow/Value functions. In classic mode, all access - * is through the aperture and will be swizzled by the fence registers, so - * we don't need the span functions to perfom tile swizzling - */ - if (intelScreen->ttm) - intel_set_span_functions(&irb->Base, tiling); - else - intel_set_span_functions(&irb->Base, INTEL_TILE_NONE); return irb; } @@ -568,7 +553,6 @@ intel_update_wrapper(GLcontext *ctx, struct intel_renderbuffer *irb, irb->Base.Delete = intel_delete_renderbuffer; irb->Base.AllocStorage = intel_nop_alloc_storage; - intel_set_span_functions(&irb->Base, irb->tiling); irb->RenderToTexture = GL_TRUE; @@ -596,9 +580,6 @@ intel_wrap_texture(GLcontext * ctx, struct gl_texture_image *texImage) _mesa_init_renderbuffer(&irb->Base, name); irb->Base.ClassID = INTEL_RB_CLASS; - /* XXX can we fix this? */ - irb->tiling = INTEL_TILE_NONE; - if (!intel_update_wrapper(ctx, irb, texImage)) { _mesa_free(irb); return NULL; diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h index 23af593960..5fe0fd8abf 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.h +++ b/src/mesa/drivers/dri/intel/intel_fbo.h @@ -72,7 +72,6 @@ struct intel_renderbuffer struct intel_region *region; void *pfMap; /* possibly paged flipped map pointer */ GLuint pfPitch; /* possibly paged flipped pitch */ - enum tiling_mode tiling; GLboolean RenderToTexture; /* RTT? */ GLuint PairedDepth; /**< only used if this is a depth renderbuffer */ @@ -91,8 +90,7 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *irb, struct intel_region *region); extern struct intel_renderbuffer * -intel_create_renderbuffer(intelScreenPrivate *intelScreen, - GLenum intFormat, enum tiling_mode tiling); +intel_create_renderbuffer(GLenum intFormat); extern void intel_fbo_init(struct intel_context *intel); diff --git a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c index ce6c6d204f..7e0d20e681 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c @@ -293,7 +293,7 @@ do_blit_bitmap( GLcontext *ctx, dst->pitch, dst->buffer, 0, - dst->tiled, + dst->tiling, rect.x1 + px, rect.y2 - (py + h), w, h, diff --git a/src/mesa/drivers/dri/intel/intel_pixel_copy.c b/src/mesa/drivers/dri/intel/intel_pixel_copy.c index eb4f10e9d5..3093ccf7c6 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_copy.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_copy.c @@ -337,8 +337,8 @@ do_blit_copypixels(GLcontext * ctx, continue; intelEmitCopyBlit(intel, dst->cpp, - src->pitch, src->buffer, 0, src->tiled, - dst->pitch, dst->buffer, 0, dst->tiled, + src->pitch, src->buffer, 0, src->tiling, + dst->pitch, dst->buffer, 0, dst->tiling, clip_x + delta_x, clip_y + delta_y, /* srcx, srcy */ clip_x, clip_y, /* dstx, dsty */ clip_w, clip_h, diff --git a/src/mesa/drivers/dri/intel/intel_pixel_draw.c b/src/mesa/drivers/dri/intel/intel_pixel_draw.c index 2b3445cb28..5675084da5 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_draw.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_draw.c @@ -314,7 +314,7 @@ do_blit_drawpixels(GLcontext * ctx, intelEmitCopyBlit(intel, dest->cpp, rowLength, src_buffer, src_offset, GL_FALSE, - dest->pitch, dest->buffer, 0, dest->tiled, + dest->pitch, dest->buffer, 0, dest->tiling, rect.x1 - dest_rect.x1, rect.y2 - dest_rect.y2, rect.x1, diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c index 5d23c72504..91b835d1aa 100644 --- a/src/mesa/drivers/dri/intel/intel_regions.c +++ b/src/mesa/drivers/dri/intel/intel_regions.c @@ -39,6 +39,9 @@ * last moment. */ +#include +#include + #include "intel_context.h" #include "intel_regions.h" #include "intel_blit.h" @@ -46,6 +49,7 @@ #include "dri_bufmgr.h" #include "intel_bufmgr.h" #include "intel_batchbuffer.h" +#include "intel_chipset.h" #define FILE_DEBUG_FLAG DEBUG_REGION @@ -76,10 +80,34 @@ intel_region_unmap(struct intel_context *intel, struct intel_region *region) } } +static int +intel_set_region_tiling_gem(struct intel_context *intel, + struct intel_region *region, + uint32_t bo_handle) +{ + struct drm_i915_gem_get_tiling get_tiling; + int ret; + + memset(&get_tiling, 0, sizeof(get_tiling)); + + get_tiling.handle = bo_handle; + ret = ioctl(intel->driFd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling); + if (ret != 0) { + fprintf(stderr, "Failed to get tiling state for region: %s\n", + strerror(errno)); + return ret; + } + + region->tiling = get_tiling.tiling_mode; + region->bit_6_swizzle = get_tiling.swizzle_mode; + + return 0; +} + static struct intel_region * intel_region_alloc_internal(struct intel_context *intel, GLuint cpp, GLuint pitch, GLuint height, - GLuint tiled, dri_bo *buffer) + dri_bo *buffer) { struct intel_region *region; @@ -93,9 +121,12 @@ intel_region_alloc_internal(struct intel_context *intel, region->pitch = pitch; region->height = height; /* needed? */ region->refcount = 1; - region->tiled = tiled; region->buffer = buffer; + /* Default to no tiling */ + region->tiling = I915_TILING_NONE; + region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE; + return region; } @@ -108,20 +139,26 @@ intel_region_alloc(struct intel_context *intel, buffer = dri_bo_alloc(intel->bufmgr, "region", pitch * cpp * height, 64); - return intel_region_alloc_internal(intel, cpp, pitch, height, 0, buffer); + return intel_region_alloc_internal(intel, cpp, pitch, height, buffer); } struct intel_region * intel_region_alloc_for_handle(struct intel_context *intel, GLuint cpp, GLuint pitch, GLuint height, - GLuint tiled, GLuint handle) + GLuint handle) { + struct intel_region *region; dri_bo *buffer; - buffer = intel_bo_gem_create_from_name(intel->bufmgr, "region", handle); + buffer = intel_bo_gem_create_from_name(intel->bufmgr, "dri2 region", handle); + + region = intel_region_alloc_internal(intel, cpp, pitch, height, buffer); + if (region == NULL) + return region; + + intel_set_region_tiling_gem(intel, region, handle); - return intel_region_alloc_internal(intel, - cpp, pitch, height, tiled, buffer); + return region; } void @@ -135,26 +172,34 @@ intel_region_reference(struct intel_region **dst, struct intel_region *src) } void -intel_region_release(struct intel_region **region) +intel_region_release(struct intel_region **region_handle) { - if (!*region) + struct intel_region *region = *region_handle; + + if (region == NULL) return; - DBG("%s %d\n", __FUNCTION__, (*region)->refcount - 1); + DBG("%s %d\n", __FUNCTION__, region->refcount - 1); - ASSERT((*region)->refcount > 0); - (*region)->refcount--; + ASSERT(region->refcount > 0); + region->refcount--; - if ((*region)->refcount == 0) { - assert((*region)->map_refcount == 0); + if (region->refcount == 0) { + assert(region->map_refcount == 0); - if ((*region)->pbo) - (*region)->pbo->region = NULL; - (*region)->pbo = NULL; - dri_bo_unreference((*region)->buffer); - free(*region); + if (region->pbo) + region->pbo->region = NULL; + region->pbo = NULL; + dri_bo_unreference(region->buffer); + + if (region->classic_map != NULL) { + drmUnmap(region->classic_map, + region->pitch * region->cpp * region->height); + } + + free(region); } - *region = NULL; + *region_handle = NULL; } /* @@ -269,8 +314,8 @@ intel_region_copy(struct intel_context *intel, intelEmitCopyBlit(intel, dst->cpp, - src->pitch, src->buffer, src_offset, src->tiled, - dst->pitch, dst->buffer, dst_offset, dst->tiled, + src->pitch, src->buffer, src_offset, src->tiling, + dst->pitch, dst->buffer, dst_offset, dst->tiling, srcx, srcy, dstx, dsty, width, height, GL_COPY); } @@ -300,7 +345,7 @@ intel_region_fill(struct intel_context *intel, intelEmitFillBlit(intel, dst->cpp, - dst->pitch, dst->buffer, dst_offset, dst->tiled, + dst->pitch, dst->buffer, dst_offset, dst->tiling, dstx, dsty, width, height, color); } @@ -382,8 +427,8 @@ intel_region_cow(struct intel_context *intel, struct intel_region *region) intelEmitCopyBlit(intel, region->cpp, - region->pitch, region->buffer, 0, region->tiled, - region->pitch, pbo->buffer, 0, region->tiled, + region->pitch, region->buffer, 0, region->tiling, + region->pitch, pbo->buffer, 0, region->tiling, 0, 0, 0, 0, region->pitch, region->height, GL_COPY); @@ -414,6 +459,7 @@ intel_recreate_static(struct intel_context *intel, GLuint mem_type) { intelScreenPrivate *intelScreen = intel->intelScreen; + int ret; if (region == NULL) { region = calloc(sizeof(*region), 1); @@ -426,20 +472,45 @@ intel_recreate_static(struct intel_context *intel, region->cpp = intel->ctx.Visual.rgbBits / 8; region->pitch = intelScreen->pitch; region->height = intelScreen->height; /* needed? */ - region->tiled = region_desc->tiled; if (intel->ttm) { assert(region_desc->bo_handle != -1); region->buffer = intel_bo_gem_create_from_name(intel->bufmgr, name, region_desc->bo_handle); + + intel_set_region_tiling_gem(intel, region, region_desc->bo_handle); } else { + ret = drmMap(intel->driFd, region_desc->handle, + region->pitch * region->cpp * region->height, + ®ion->classic_map); + if (ret != 0) { + fprintf(stderr, "Failed to drmMap %s buffer\n", name); + free(region); + return NULL; + } + region->buffer = intel_bo_fake_alloc_static(intel->bufmgr, name, region_desc->offset, - intelScreen->pitch * - intelScreen->height, - region_desc->map); + region->pitch * region->cpp * + region->height, + region->classic_map); + + /* The sarea just gives us a boolean for whether it's tiled or not, + * instead of which tiling mode it is. Guess. + */ + if (region_desc->tiled) { + if (IS_965(intel->intelScreen->deviceID) && + region_desc == &intelScreen->depth) + region->tiling = I915_TILING_Y; + else + region->tiling = I915_TILING_X; + } else { + region->tiling = I915_TILING_NONE; + } + + region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE; } assert(region->buffer != NULL); diff --git a/src/mesa/drivers/dri/intel/intel_regions.h b/src/mesa/drivers/dri/intel/intel_regions.h index 229f79aeba..e5f19fbb45 100644 --- a/src/mesa/drivers/dri/intel/intel_regions.h +++ b/src/mesa/drivers/dri/intel/intel_regions.h @@ -28,6 +28,12 @@ #ifndef INTEL_REGIONS_H #define INTEL_REGIONS_H +/** @file intel_regions.h + * + * Structure definitions and prototypes for intel_region handling, which is + * the basic structure for rectangular collections of pixels stored in a dri_bo. + */ + #include "mtypes.h" #include "dri_bufmgr.h" @@ -53,8 +59,9 @@ struct intel_region GLuint map_refcount; /**< Reference count for mapping */ GLuint draw_offset; /**< Offset of drawing address within the region */ - GLboolean tiled; /**< True if the region is X or Y-tiled. Used on 965. */ - + uint32_t tiling; /**< Which tiling mode the region is in */ + uint32_t bit_6_swizzle; /**< GEM flag for address swizzling requirement */ + drmAddress classic_map; /**< drmMap of the region when not in GEM mode */ struct intel_buffer_object *pbo; /* zero-copy uploads */ }; @@ -69,7 +76,7 @@ struct intel_region *intel_region_alloc(struct intel_context *intel, struct intel_region * intel_region_alloc_for_handle(struct intel_context *intel, GLuint cpp, GLuint pitch, GLuint height, - GLuint tiled, unsigned int handle); + unsigned int handle); void intel_region_reference(struct intel_region **dst, struct intel_region *src); diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index 9e4f48fbd7..36dce171c6 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -69,20 +69,13 @@ PUBLIC const char __driConfigOptions[] = DRI_CONF_SECTION_QUALITY DRI_CONF_FORCE_S3TC_ENABLE(false) DRI_CONF_ALLOW_LARGE_TEXTURES(2) - DRI_CONF_OPT_BEGIN_V(swizzle_mode, enum, 0, "0:2") - DRI_CONF_DESC_BEGIN(en, "Tiling swizzle mode for software fallbacks") - DRI_CONF_ENUM(0, "No swizzling") - DRI_CONF_ENUM(1, "addr[6] = addr[6] ^ addr[9]") - DRI_CONF_ENUM(2, "addr[6] = addr[6] ^ addr[9] ^ addr[10]") - DRI_CONF_DESC_END - DRI_CONF_OPT_END DRI_CONF_SECTION_END DRI_CONF_SECTION_DEBUG DRI_CONF_NO_RAST(false) DRI_CONF_SECTION_END DRI_CONF_END; -const GLuint __driNConfigOptions = 7; +const GLuint __driNConfigOptions = 6; #ifdef USE_NEW_INTERFACE static PFNGLXCREATECONTEXTMODES create_context_modes = NULL; @@ -97,51 +90,6 @@ intelMapScreenRegions(__DRIscreenPrivate * sPriv) { intelScreenPrivate *intelScreen = (intelScreenPrivate *) sPriv->private; - if (intelScreen->front.handle) { - if (drmMap(sPriv->fd, - intelScreen->front.handle, - intelScreen->front.size, - (drmAddress *) & intelScreen->front.map) != 0) { - _mesa_problem(NULL, "drmMap(frontbuffer) failed!"); - return GL_FALSE; - } - } - else { - _mesa_warning(NULL, "no front buffer handle in intelMapScreenRegions!"); - } - - if (0) - _mesa_printf("Back 0x%08x ", intelScreen->back.handle); - if (drmMap(sPriv->fd, - intelScreen->back.handle, - intelScreen->back.size, - (drmAddress *) & intelScreen->back.map) != 0) { - intelUnmapScreenRegions(intelScreen); - return GL_FALSE; - } - - if (intelScreen->third.handle) { - if (0) - _mesa_printf("Third 0x%08x ", intelScreen->third.handle); - if (drmMap(sPriv->fd, - intelScreen->third.handle, - intelScreen->third.size, - (drmAddress *) & intelScreen->third.map) != 0) { - intelUnmapScreenRegions(intelScreen); - return GL_FALSE; - } - } - - if (0) - _mesa_printf("Depth 0x%08x ", intelScreen->depth.handle); - if (drmMap(sPriv->fd, - intelScreen->depth.handle, - intelScreen->depth.size, - (drmAddress *) & intelScreen->depth.map) != 0) { - intelUnmapScreenRegions(intelScreen); - return GL_FALSE; - } - if (0) _mesa_printf("TEX 0x%08x ", intelScreen->tex.handle); if (intelScreen->tex.size != 0) { @@ -154,50 +102,15 @@ intelMapScreenRegions(__DRIscreenPrivate * sPriv) } } - if (0) - printf("Mappings: front: %p back: %p third: %p depth: %p tex: %p\n", - intelScreen->front.map, - intelScreen->back.map, intelScreen->third.map, - intelScreen->depth.map, intelScreen->tex.map); return GL_TRUE; } void intelUnmapScreenRegions(intelScreenPrivate * intelScreen) { -#define REALLY_UNMAP 1 - if (intelScreen->front.map) { -#if REALLY_UNMAP - if (drmUnmap(intelScreen->front.map, intelScreen->front.size) != 0) - printf("drmUnmap front failed!\n"); -#endif - intelScreen->front.map = NULL; - } - if (intelScreen->back.map) { -#if REALLY_UNMAP - if (drmUnmap(intelScreen->back.map, intelScreen->back.size) != 0) - printf("drmUnmap back failed!\n"); -#endif - intelScreen->back.map = NULL; - } - if (intelScreen->third.map) { -#if REALLY_UNMAP - if (drmUnmap(intelScreen->third.map, intelScreen->third.size) != 0) - printf("drmUnmap third failed!\n"); -#endif - intelScreen->third.map = NULL; - } - if (intelScreen->depth.map) { -#if REALLY_UNMAP - drmUnmap(intelScreen->depth.map, intelScreen->depth.size); - intelScreen->depth.map = NULL; -#endif - } if (intelScreen->tex.map) { -#if REALLY_UNMAP drmUnmap(intelScreen->tex.map, intelScreen->tex.size); intelScreen->tex.map = NULL; -#endif } } @@ -341,8 +254,6 @@ intelHandleDrawableConfig(__DRIdrawablePrivate *dPriv, * attached. */ } -#define BUFFER_FLAG_TILED 0x0100 - /** * DRI2 entrypoint */ @@ -355,7 +266,6 @@ intelHandleBufferAttach(__DRIdrawablePrivate *dPriv, struct intel_renderbuffer *rb; struct intel_region *region; struct intel_context *intel = pcp->driverPrivate; - GLuint tiled; switch (ba->buffer.attachment) { case DRI_DRAWABLE_BUFFER_FRONT_LEFT: @@ -389,10 +299,9 @@ intelHandleBufferAttach(__DRIdrawablePrivate *dPriv, return; #endif - tiled = (ba->buffer.flags & BUFFER_FLAG_TILED) > 0; region = intel_region_alloc_for_handle(intel, ba->buffer.cpp, ba->buffer.pitch / ba->buffer.cpp, - dPriv->h, tiled, + dPriv->h, ba->buffer.handle); intel_renderbuffer_set_region(rb, region); @@ -528,7 +437,6 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv, GLboolean swStencil = (mesaVis->stencilBits > 0 && mesaVis->depthBits != 24); GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8); - enum tiling_mode tiling; struct intel_framebuffer *intel_fb = CALLOC_STRUCT(intel_framebuffer); @@ -538,46 +446,29 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv, _mesa_initialize_framebuffer(&intel_fb->Base, mesaVis); /* setup the hardware-based renderbuffers */ - /* We get only a boolean value from the DDX for whether tiling is - * enabled, so we have to guess when it's Y and not X (965 depth). - */ - { - tiling = screen->front.tiled ? INTEL_TILE_X : INTEL_TILE_NONE; - intel_fb->color_rb[0] = intel_create_renderbuffer(screen, - rgbFormat, tiling); - _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_FRONT_LEFT, - &intel_fb->color_rb[0]->Base); - } + intel_fb->color_rb[0] = intel_create_renderbuffer(rgbFormat); + _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_FRONT_LEFT, + &intel_fb->color_rb[0]->Base); if (mesaVis->doubleBufferMode) { - tiling = screen->back.tiled ? INTEL_TILE_X : INTEL_TILE_NONE; - intel_fb->color_rb[1] = intel_create_renderbuffer(screen, - rgbFormat, tiling); + intel_fb->color_rb[1] = intel_create_renderbuffer(rgbFormat); _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_BACK_LEFT, &intel_fb->color_rb[1]->Base); if (screen->third.handle) { struct gl_renderbuffer *tmp_rb = NULL; - tiling = screen->third.tiled ? INTEL_TILE_X : INTEL_TILE_NONE; - intel_fb->color_rb[2] = intel_create_renderbuffer(screen, - rgbFormat, - tiling); + + intel_fb->color_rb[2] = intel_create_renderbuffer(rgbFormat); _mesa_reference_renderbuffer(&tmp_rb, &intel_fb->color_rb[2]->Base); } } -#ifdef I915 - tiling = screen->depth.tiled ? INTEL_TILE_X : INTEL_TILE_NONE; -#else - tiling = screen->depth.tiled ? INTEL_TILE_Y : INTEL_TILE_NONE; -#endif if (mesaVis->depthBits == 24) { if (mesaVis->stencilBits == 8) { /* combined depth/stencil buffer */ struct intel_renderbuffer *depthStencilRb - = intel_create_renderbuffer(screen, - GL_DEPTH24_STENCIL8_EXT, tiling); + = intel_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT); /* note: bind RB to two attachment points */ _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH, &depthStencilRb->Base); @@ -585,8 +476,7 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv, &depthStencilRb->Base); } else { struct intel_renderbuffer *depthRb - = intel_create_renderbuffer(screen, - GL_DEPTH_COMPONENT24, tiling); + = intel_create_renderbuffer(GL_DEPTH_COMPONENT24); _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH, &depthRb->Base); } @@ -594,8 +484,7 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv, else if (mesaVis->depthBits == 16) { /* just 16-bit depth buffer, no hw stencil */ struct intel_renderbuffer *depthRb - = intel_create_renderbuffer(screen, - GL_DEPTH_COMPONENT16, tiling); + = intel_create_renderbuffer(GL_DEPTH_COMPONENT16); _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH, &depthRb->Base); } diff --git a/src/mesa/drivers/dri/intel/intel_screen.h b/src/mesa/drivers/dri/intel/intel_screen.h index 648bf61240..9a73b13951 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.h +++ b/src/mesa/drivers/dri/intel/intel_screen.h @@ -33,12 +33,6 @@ #include "i915_drm.h" #include "xmlconfig.h" -enum tiling_mode { - INTEL_TILE_NONE, - INTEL_TILE_X, - INTEL_TILE_Y -}; - /* XXX: change name or eliminate to avoid conflict with "struct * intel_region"!!! */ diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index b1392f794e..3065d15e32 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -39,6 +39,10 @@ #include "swrast/swrast.h" +static void +intel_set_span_functions(struct intel_context *intel, + struct gl_renderbuffer *rb); + /* * Deal with tiled surfaces */ @@ -111,39 +115,26 @@ static GLubyte *x_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont tile_off = (y_tile_off << 9) + x_tile_off; - /* bit swizzling tricks your parents never told you about: - * - * The specs say that the X tiling layout is just 8 512-byte rows - * packed into a page. It turns out that there's some additional - * swizzling of bit 6 to reduce cache aliasing issues. Experimental - * results below: - * - * line bit GM965 945G/Q965 - * 9 10 11 - * 0 0 0 0 0 0 - * 1 0 1 0 1 1 - * 2 1 0 0 1 1 - * 3 1 1 0 0 0 - * 4 0 0 1 1 0 - * 5 0 1 1 0 1 - * 6 1 0 1 0 1 - * 7 1 1 1 1 0 - * - * So we see that the GM965 is bit 6 ^ 9 ^ 10 ^ 11, while other - * parts were just 6 ^ 9 ^ 10. However, some systems, including a - * GM965 we've seen, don't perform the swizzling at all. Information - * on how to detect it through register reads is expected soon. - */ - switch (intel->tiling_swizzle_mode) { - case 0: + switch (irb->region->bit_6_swizzle) { + case I915_BIT_6_SWIZZLE_NONE: break; - case 1: + case I915_BIT_6_SWIZZLE_9: + tile_off ^= ((tile_off >> 3) & 64); + break; + case I915_BIT_6_SWIZZLE_9_10: tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64); break; - case 2: + case I915_BIT_6_SWIZZLE_9_11: + tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64); + break; + case I915_BIT_6_SWIZZLE_9_10_11: tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^ ((tile_off >> 5) & 64); break; + default: + fprintf(stderr, "Unknown tile swizzling mode %d\n", + irb->region->bit_6_swizzle); + exit(1); } tile_base = (x_tile_number << 12) + y_tile_number * tile_stride; @@ -184,15 +175,28 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) + (x_tile_off & 0xf); - switch (intel->tiling_swizzle_mode) { - case 0: + switch (irb->region->bit_6_swizzle) { + case I915_BIT_6_SWIZZLE_NONE: + break; + case I915_BIT_6_SWIZZLE_9: + tile_off ^= ((tile_off >> 3) & 64); + break; + case I915_BIT_6_SWIZZLE_9_10: + tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64); break; - case 1: - tile_off ^= (tile_off >> 3) & 64; + case I915_BIT_6_SWIZZLE_9_11: + tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64); break; - case 2: + case I915_BIT_6_SWIZZLE_9_10_11: + tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^ + ((tile_off >> 5) & 64); break; + default: + fprintf(stderr, "Unknown tile swizzling mode %d\n", + irb->region->bit_6_swizzle); + exit(1); } + tile_base = (x_tile_number << 12) + y_tile_number * tile_stride; return buf + tile_base + tile_off; @@ -491,16 +495,14 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map) for (j = 0; j < ctx->DrawBuffer->_NumColorDrawBuffers; j++) { struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[j]; irb = intel_renderbuffer(rb); - if (irb) { - /* this is a user-created intel_renderbuffer */ - if (irb->region) { - if (map) - intel_region_map(intel, irb->region); - else - intel_region_unmap(intel, irb->region); - irb->pfMap = irb->region->map; - irb->pfPitch = irb->region->pitch; - } + if (irb && irb->region) { + intel_set_span_functions(intel, rb); + if (map) + intel_region_map(intel, irb->region); + else + intel_region_unmap(intel, irb->region); + irb->pfMap = irb->region->map; + irb->pfPitch = irb->region->pitch; } } @@ -526,6 +528,7 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map) /* color read buffers */ irb = intel_renderbuffer(ctx->ReadBuffer->_ColorReadBuffer); if (irb && irb->region) { + intel_set_span_functions(intel, ctx->ReadBuffer->_ColorReadBuffer); if (map) intel_region_map(intel, irb->region); else @@ -568,6 +571,8 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map) irb = intel_renderbuffer(ctx->DrawBuffer->_DepthBuffer->Wrapped); if (irb && irb->region) { if (map) { + intel_set_span_functions(intel, + ctx->DrawBuffer->_DepthBuffer->Wrapped); intel_region_map(intel, irb->region); irb->pfMap = irb->region->map; irb->pfPitch = irb->region->pitch; @@ -585,6 +590,8 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map) irb = intel_renderbuffer(ctx->DrawBuffer->_StencilBuffer->Wrapped); if (irb && irb->region) { if (map) { + intel_set_span_functions(intel, + ctx->DrawBuffer->_StencilBuffer->Wrapped); intel_region_map(intel, irb->region); irb->pfMap = irb->region->map; irb->pfPitch = irb->region->pitch; @@ -615,15 +622,6 @@ intelSpanRenderStart(GLcontext * ctx) intelFlush(&intel->ctx); LOCK_HARDWARE(intel); -#if 0 - /* Just map the framebuffer and all textures. Bufmgr code will - * take care of waiting on the necessary fences: - */ - intel_region_map(intel, intel->front_region); - intel_region_map(intel, intel->back_region); - intel_region_map(intel, intel->depth_region); -#endif - for (i = 0; i < ctx->Const.MaxTextureCoordUnits; i++) { if (ctx->Texture.Unit[i]._ReallyEnabled) { struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current; @@ -646,14 +644,6 @@ intelSpanRenderFinish(GLcontext * ctx) _swrast_flush(ctx); - /* Now unmap the framebuffer: - */ -#if 0 - intel_region_unmap(intel, intel->front_region); - intel_region_unmap(intel, intel->back_region); - intel_region_unmap(intel, intel->depth_region); -#endif - for (i = 0; i < ctx->Const.MaxTextureCoordUnits; i++) { if (ctx->Texture.Unit[i]._ReallyEnabled) { struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current; @@ -680,20 +670,32 @@ intelInitSpanFuncs(GLcontext * ctx) * Plug in appropriate span read/write functions for the given renderbuffer. * These are used for the software fallbacks. */ -void -intel_set_span_functions(struct gl_renderbuffer *rb, enum tiling_mode tiling) +static void +intel_set_span_functions(struct intel_context *intel, + struct gl_renderbuffer *rb) { + struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb; + uint32_t tiling; + + /* If in GEM mode, we need to do the tile address swizzling ourselves, + * instead of the fence registers handling it. + */ + if (intel->ttm) + tiling = irb->region->tiling; + else + tiling = I915_TILING_NONE; + if (rb->_ActualFormat == GL_RGB5) { /* 565 RGB */ switch (tiling) { - case INTEL_TILE_NONE: + case I915_TILING_NONE: default: intelInitPointers_RGB565(rb); break; - case INTEL_TILE_X: + case I915_TILING_X: intel_XTile_InitPointers_RGB565(rb); break; - case INTEL_TILE_Y: + case I915_TILING_Y: intel_YTile_InitPointers_RGB565(rb); break; } @@ -701,28 +703,28 @@ intel_set_span_functions(struct gl_renderbuffer *rb, enum tiling_mode tiling) else if (rb->_ActualFormat == GL_RGBA8) { /* 8888 RGBA */ switch (tiling) { - case INTEL_TILE_NONE: + case I915_TILING_NONE: default: intelInitPointers_ARGB8888(rb); break; - case INTEL_TILE_X: + case I915_TILING_X: intel_XTile_InitPointers_ARGB8888(rb); break; - case INTEL_TILE_Y: + case I915_TILING_Y: intel_YTile_InitPointers_ARGB8888(rb); break; } } else if (rb->_ActualFormat == GL_DEPTH_COMPONENT16) { switch (tiling) { - case INTEL_TILE_NONE: + case I915_TILING_NONE: default: intelInitDepthPointers_z16(rb); break; - case INTEL_TILE_X: + case I915_TILING_X: intel_XTile_InitDepthPointers_z16(rb); break; - case INTEL_TILE_Y: + case I915_TILING_Y: intel_YTile_InitDepthPointers_z16(rb); break; } @@ -730,28 +732,28 @@ intel_set_span_functions(struct gl_renderbuffer *rb, enum tiling_mode tiling) else if (rb->_ActualFormat == GL_DEPTH_COMPONENT24 || /* XXX FBO remove */ rb->_ActualFormat == GL_DEPTH24_STENCIL8_EXT) { switch (tiling) { - case INTEL_TILE_NONE: + case I915_TILING_NONE: default: intelInitDepthPointers_z24_s8(rb); break; - case INTEL_TILE_X: + case I915_TILING_X: intel_XTile_InitDepthPointers_z24_s8(rb); break; - case INTEL_TILE_Y: + case I915_TILING_Y: intel_YTile_InitDepthPointers_z24_s8(rb); break; } } else if (rb->_ActualFormat == GL_STENCIL_INDEX8_EXT) { switch (tiling) { - case INTEL_TILE_NONE: + case I915_TILING_NONE: default: intelInitStencilPointers_z24_s8(rb); break; - case INTEL_TILE_X: + case I915_TILING_X: intel_XTile_InitStencilPointers_z24_s8(rb); break; - case INTEL_TILE_Y: + case I915_TILING_Y: intel_YTile_InitStencilPointers_z24_s8(rb); break; } diff --git a/src/mesa/drivers/dri/intel/intel_span.h b/src/mesa/drivers/dri/intel/intel_span.h index 1b47c2829c..d2d4d6ecd4 100644 --- a/src/mesa/drivers/dri/intel/intel_span.h +++ b/src/mesa/drivers/dri/intel/intel_span.h @@ -33,7 +33,4 @@ extern void intelInitSpanFuncs(GLcontext * ctx); extern void intelSpanRenderFinish(GLcontext * ctx); extern void intelSpanRenderStart(GLcontext * ctx); -extern void intel_set_span_functions(struct gl_renderbuffer *rb, - enum tiling_mode tiling); - #endif diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c index 8a8eec83aa..cf8eb4ed3c 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_copy.c +++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c @@ -148,7 +148,7 @@ do_copy_texsubimage(struct intel_context *intel, intelImage->mt->pitch, intelImage->mt->region->buffer, image_offset, - intelImage->mt->region->tiled, + intelImage->mt->region->tiling, x, y + height, dstx, dsty, width, height, GL_COPY); /* ? */ } -- cgit v1.2.3 From d2d5abfaeb46fc7b4d4267a6c9e92420fc9b5334 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 22 Jul 2008 15:20:07 -0700 Subject: intel-gem: Use pread/pwrite for span access. This will avoid clflushing entire buffers for small acesses, such as those commonly used by regression tests. --- src/mesa/drivers/dri/common/spantmp2.h | 64 ++++---- src/mesa/drivers/dri/intel/intel_fbo.c | 1 - src/mesa/drivers/dri/intel/intel_fbo.h | 1 - src/mesa/drivers/dri/intel/intel_span.c | 272 +++++++++++++------------------- 4 files changed, 141 insertions(+), 197 deletions(-) (limited to 'src/mesa/drivers/dri/intel/intel_fbo.h') diff --git a/src/mesa/drivers/dri/common/spantmp2.h b/src/mesa/drivers/dri/common/spantmp2.h index 5e51112a20..a1e56eb148 100644 --- a/src/mesa/drivers/dri/common/spantmp2.h +++ b/src/mesa/drivers/dri/common/spantmp2.h @@ -48,40 +48,34 @@ #define HW_WRITE_CLIPLOOP() HW_CLIPLOOP() #endif -/* Whether GET_PTR(x, y) + cpp != GET_PTR(x+1, y) */ -#ifndef GET_PTR_NONLINEAR -#define GET_PTR_NONLINEAR 0 -#endif - #if (SPANTMP_PIXEL_FMT == GL_RGB) && (SPANTMP_PIXEL_TYPE == GL_UNSIGNED_SHORT_5_6_5) /** ** GL_RGB, GL_UNSIGNED_SHORT_5_6_5 **/ +#ifndef GET_VALUE #ifndef GET_PTR #define GET_PTR(_x, _y) (buf + (_x) * 2 + (_y) * pitch) #endif +#define GET_VALUE(_x, _y) *(volatile GLushort *)(GET_PTR(_x, _y)) +#define PUT_VALUE(_x, _y, _v) *(volatile GLushort *)(GET_PTR(_x, _y)) = (_v) +#endif /* GET_VALUE */ + #define INIT_MONO_PIXEL(p, color) \ p = PACK_COLOR_565( color[0], color[1], color[2] ) #define WRITE_RGBA( _x, _y, r, g, b, a ) \ - do { \ - GLshort * _p = (GLshort *) GET_PTR(_x, _y); \ - _p[0] = ((((int)r & 0xf8) << 8) | (((int)g & 0xfc) << 3) | \ - (((int)b & 0xf8) >> 3)); \ - } while(0) + PUT_VALUE(_x, _y, ((((int)r & 0xf8) << 8) | \ + (((int)g & 0xfc) << 3) | \ + (((int)b & 0xf8) >> 3))) \ -#define WRITE_PIXEL( _x, _y, p ) \ - do { \ - GLushort * _p = (GLushort *) GET_PTR(_x, _y); \ - _p[0] = p; \ - } while(0) +#define WRITE_PIXEL( _x, _y, p ) PUT_VALUE(_x, _y, p) #define READ_RGBA( rgba, _x, _y ) \ do { \ - GLushort p = *(volatile GLshort *) GET_PTR(_x, _y); \ + GLushort p = GET_VALUE(_x, _y); \ rgba[0] = ((p >> 8) & 0xf8) * 255 / 0xf8; \ rgba[1] = ((p >> 3) & 0xfc) * 255 / 0xfc; \ rgba[2] = ((p << 3) & 0xf8) * 255 / 0xf8; \ @@ -94,29 +88,30 @@ ** GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV **/ +#ifndef GET_VALUE #ifndef GET_PTR #define GET_PTR(_x, _y) ( buf + (_x) * 4 + (_y) * pitch) #endif +#define GET_VALUE(_x, _y) *(volatile GLuint *)(GET_PTR(_x, _y)) +#define PUT_VALUE(_x, _y, _v) *(volatile GLuint *)(GET_PTR(_x, _y)) = (_v) +#endif /* GET_VALUE */ + # define INIT_MONO_PIXEL(p, color) \ p = PACK_COLOR_8888(color[3], color[0], color[1], color[2]) # define WRITE_RGBA(_x, _y, r, g, b, a) \ - do { \ - GLuint * _p = (GLuint *) GET_PTR(_x, _y); \ - _p[0] = ((r << 16) | (g << 8) | (b << 0) | (a << 24)); \ - } while(0) + PUT_VALUE(_x, _y, ((r << 16) | \ + (g << 8) | \ + (b << 0) | \ + (a << 24))) -#define WRITE_PIXEL(_x, _y, p) \ - do { \ - GLuint * _p = (GLuint *) GET_PTR(_x, _y); \ - _p[0] = p; \ - } while(0) +#define WRITE_PIXEL(_x, _y, p) PUT_VALUE(_x, _y, p) # if defined( USE_X86_ASM ) # define READ_RGBA(rgba, _x, _y) \ do { \ - GLuint p = *(volatile GLuint *) GET_PTR(_x, _y); \ + GLuint p = GET_VALUE(_x, _y); \ __asm__ __volatile__( "bswap %0; rorl $8, %0" \ : "=r" (p) : "0" (p) ); \ ((GLuint *)rgba)[0] = p; \ @@ -127,14 +122,14 @@ */ # define READ_RGBA( rgba, _x, _y ) \ do { \ - GLuint p = *(volatile GLuint *) GET_PTR(_x, _y); \ + GLuint p = GET_VALUE(_x, _y); \ GLuint t = p; \ *((uint32_t *) rgba) = (t >> 24) | (p << 8); \ } while (0) # else # define READ_RGBA( rgba, _x, _y ) \ do { \ - GLuint p = *(volatile GLuint *) GET_PTR(_x, _y); \ + GLuint p = GET_VALUE(_x, _y); \ rgba[0] = (p >> 16) & 0xff; \ rgba[1] = (p >> 8) & 0xff; \ rgba[2] = (p >> 0) & 0xff; \ @@ -393,7 +388,7 @@ static void TAG(ReadRGBASpan)( GLcontext *ctx, } -#if !GET_PTR_NONLINEAR && \ +#if defined(GET_PTR) && \ defined(USE_MMX_ASM) && \ (((SPANTMP_PIXEL_FMT == GL_BGRA) && \ (SPANTMP_PIXEL_TYPE == GL_UNSIGNED_INT_8_8_8_8_REV)) || \ @@ -445,7 +440,7 @@ static void TAG2(ReadRGBASpan,_MMX)( GLcontext *ctx, #endif -#if !GET_PTR_NONLINEAR && \ +#if defined(GET_PTR) && \ defined(USE_SSE_ASM) && \ (SPANTMP_PIXEL_FMT == GL_BGRA) && \ (SPANTMP_PIXEL_TYPE == GL_UNSIGNED_INT_8_8_8_8_REV) @@ -480,7 +475,7 @@ static void TAG2(ReadRGBASpan,_SSE2)( GLcontext *ctx, } #endif -#if !GET_PTR_NONLINEAR && \ +#if defined(GET_PTR) && \ defined(USE_SSE_ASM) && \ (SPANTMP_PIXEL_FMT == GL_BGRA) && \ (SPANTMP_PIXEL_TYPE == GL_UNSIGNED_INT_8_8_8_8_REV) @@ -574,7 +569,7 @@ static void TAG(InitPointers)(struct gl_renderbuffer *rb) rb->PutMonoValues = TAG(WriteMonoRGBAPixels); rb->GetValues = TAG(ReadRGBAPixels); -#if !GET_PTR_NONLINEAR +#if defined(GET_PTR) #if defined(USE_SSE_ASM) && \ (SPANTMP_PIXEL_FMT == GL_BGRA) && \ (SPANTMP_PIXEL_TYPE == GL_UNSIGNED_INT_8_8_8_8_REV) @@ -604,7 +599,7 @@ static void TAG(InitPointers)(struct gl_renderbuffer *rb) } else #endif -#endif /* GET_PTR_NONLINEAR */ +#endif /* GET_PTR */ { if (DBG) fprintf( stderr, "Using %s version of GetRow\n", "C" ); rb->GetRow = TAG(ReadRGBASpan); @@ -619,7 +614,8 @@ static void TAG(InitPointers)(struct gl_renderbuffer *rb) #undef READ_RGBA #undef TAG #undef TAG2 +#undef GET_VALUE +#undef PUT_VALUE #undef GET_PTR -#undef GET_PTR_NONLINEAR #undef SPANTMP_PIXEL_FMT #undef SPANTMP_PIXEL_TYPE diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 7663393fba..d539097a66 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -363,7 +363,6 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *rb, intel_region_reference(&rb->region, region); intel_region_release(&old); - rb->pfMap = region->map; rb->pfPitch = region->pitch; } diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h index 5fe0fd8abf..f55d3747f2 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.h +++ b/src/mesa/drivers/dri/intel/intel_fbo.h @@ -70,7 +70,6 @@ struct intel_renderbuffer { struct gl_renderbuffer Base; struct intel_region *region; - void *pfMap; /* possibly paged flipped map pointer */ GLuint pfPitch; /* possibly paged flipped pitch */ GLboolean RenderToTexture; /* RTT? */ diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index c9d413ec43..44e2eff680 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -43,57 +43,72 @@ static void intel_set_span_functions(struct intel_context *intel, struct gl_renderbuffer *rb); -/* - * Deal with tiled surfaces - */ +static uint32_t +pread_32(struct intel_renderbuffer *irb, uint32_t offset) +{ + uint32_t val; -#if 0 -/* These are pre-965 tile swizzling functions -- power of two widths */ -static uintptr_t x_tile_swizzle_pow2 (uintptr_t addr, int n) + dri_bo_get_subdata(irb->region->buffer, offset, 4, &val); + + return val; +} + +static uint16_t +pread_16(struct intel_renderbuffer *irb, uint32_t offset) { - uintptr_t a = addr; - uintptr_t base_mask = (((~0) << (n + 4)) | 0xff); - uintptr_t x_mask = ((~0) << 12) & ~base_mask; - - a = ((a & base_mask) | - ((a >> (n-8)) & 0x7) | - ((a << 3) & x_mask)); - _mesa_printf ("x_swizzle %08x (base %x yrow %x tile#x %x xsword %x byte %x) %08x\n", - addr, - addr >> (n + 4), - (addr >> (n + 1)) & 0x7, - (addr >> 9) & ((1 << (n-8)) - 1), - (addr >> 5) & 0xf, - (addr & 0x1f), - a); - return a; + uint16_t val; + + dri_bo_get_subdata(irb->region->buffer, offset, 2, &val); + + return val; } -static uintptr_t y_tile_swizzle_pow2 (uintptr_t addr, int n) +static uint8_t +pread_8(struct intel_renderbuffer *irb, uint32_t offset) { - uintptr_t a = (uintptr_t) addr; - uintptr_t base_mask = (((~0) << (n + 6)) | 0xf); - uintptr_t x_mask = ((~0) << 9) & ~base_mask; - - a = ((a & base_mask) | - ((a >> (n-3)) & 0x1f) | - ((a << 5) & x_mask)); - _mesa_printf ("y_swizzle %08x (base %x yrow %x tile#x %x xoword %x byte %x) %08x\n", - addr, - addr >> (n + 6), - (addr >> (n + 1)) & 0x01f, - (addr >> 7) & ((1 << (n-6)) - 1), - (addr >> 4) & 0x7, - (addr & 0xf), - a); - return a; + uint8_t val; + + dri_bo_get_subdata(irb->region->buffer, offset, 1, &val); + + return val; +} + +static void +pwrite_32(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val) +{ + dri_bo_subdata(irb->region->buffer, offset, 4, &val); +} + +static void +pwrite_16(struct intel_renderbuffer *irb, uint32_t offset, uint16_t val) +{ + dri_bo_subdata(irb->region->buffer, offset, 2, &val); +} + +static void +pwrite_8(struct intel_renderbuffer *irb, uint32_t offset, uint8_t val) +{ + dri_bo_subdata(irb->region->buffer, offset, 1, &val); +} + +static uint32_t no_tile_swizzle(struct intel_renderbuffer *irb, + struct intel_context *intel, + int x, int y) +{ + x += intel->drawX; + y += intel->drawY; + + return (y * irb->region->pitch + x) * irb->region->cpp; } -#endif -static GLubyte *x_tile_swizzle(struct intel_renderbuffer *irb, struct intel_context *intel, +/* + * Deal with tiled surfaces + */ + +static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb, + struct intel_context *intel, int x, int y) { - GLubyte *buf = (GLubyte *) irb->pfMap; int tile_stride; int xbyte; int x_tile_off, y_tile_off; @@ -146,13 +161,13 @@ static GLubyte *x_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont irb->pfPitch, tile_stride); #endif - return buf + tile_base + tile_off; + return tile_base + tile_off; } -static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_context *intel, +static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb, + struct intel_context *intel, int x, int y) { - GLubyte *buf = (GLubyte *) irb->pfMap; int tile_stride; int xbyte; int x_tile_off, y_tile_off; @@ -199,7 +214,7 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont tile_base = (x_tile_number << 12) + y_tile_number * tile_stride; - return buf + tile_base + tile_off; + return tile_base + tile_off; } /* @@ -214,11 +229,8 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont struct intel_renderbuffer *irb = intel_renderbuffer(rb); \ const GLint yScale = irb->RenderToTexture ? 1 : -1; \ const GLint yBias = irb->RenderToTexture ? 0 : irb->Base.Height - 1; \ - GLubyte *buf = (GLubyte *) irb->pfMap \ - + (intel->drawY * irb->pfPitch + intel->drawX) * irb->region->cpp;\ GLuint p; \ - assert(irb->pfMap);\ - (void) p; (void) buf; + (void) p; /* XXX FBO: this is identical to the macro in spantmp2.h except we get * the cliprect info from the context, not the driDrawable. @@ -251,7 +263,8 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont #define TAG(x) intel##x##_RGB565 #define TAG2(x,y) intel##x##_RGB565##y -#define GET_PTR(X,Y) (buf + ((Y) * irb->pfPitch + (X)) * 2) +#define GET_VALUE(X, Y) pread_16(irb, no_tile_swizzle(irb, intel, X, Y)) +#define PUT_VALUE(X, Y, V) pwrite_16(irb, no_tile_swizzle(irb, intel, X, Y), V) #include "spantmp2.h" /* 32 bit, ARGB8888 color spanline and pixel functions @@ -261,7 +274,8 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont #define TAG(x) intel##x##_ARGB8888 #define TAG2(x,y) intel##x##_ARGB8888##y -#define GET_PTR(X,Y) (buf + ((Y) * irb->pfPitch + (X)) * 4) +#define GET_VALUE(X, Y) pread_32(irb, no_tile_swizzle(irb, intel, X, Y)) +#define PUT_VALUE(X, Y, V) pwrite_32(irb, no_tile_swizzle(irb, intel, X, Y), V) #include "spantmp2.h" /* 16 bit RGB565 color tile spanline and pixel functions @@ -272,8 +286,8 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont #define TAG(x) intel_XTile_##x##_RGB565 #define TAG2(x,y) intel_XTile_##x##_RGB565##y -#define GET_PTR(X,Y) x_tile_swizzle(irb, intel, X, Y) -#define GET_PTR_NONLINEAR 1 +#define GET_VALUE(X, Y) pread_16(irb, x_tile_swizzle(irb, intel, X, Y)) +#define PUT_VALUE(X, Y, V) pwrite_16(irb, x_tile_swizzle(irb, intel, X, Y), V) #include "spantmp2.h" #define SPANTMP_PIXEL_FMT GL_RGB @@ -281,8 +295,8 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont #define TAG(x) intel_YTile_##x##_RGB565 #define TAG2(x,y) intel_YTile_##x##_RGB565##y -#define GET_PTR(X,Y) y_tile_swizzle(irb, intel, X, Y) -#define GET_PTR_NONLINEAR 1 +#define GET_VALUE(X, Y) pread_16(irb, y_tile_swizzle(irb, intel, X, Y)) +#define PUT_VALUE(X, Y, V) pwrite_16(irb, y_tile_swizzle(irb, intel, X, Y), V) #include "spantmp2.h" /* 32 bit ARGB888 color tile spanline and pixel functions @@ -293,8 +307,8 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont #define TAG(x) intel_XTile_##x##_ARGB8888 #define TAG2(x,y) intel_XTile_##x##_ARGB8888##y -#define GET_PTR(X,Y) x_tile_swizzle(irb, intel, X, Y) -#define GET_PTR_NONLINEAR 1 +#define GET_VALUE(X, Y) pread_32(irb, x_tile_swizzle(irb, intel, X, Y)) +#define PUT_VALUE(X, Y, V) pwrite_32(irb, x_tile_swizzle(irb, intel, X, Y), V) #include "spantmp2.h" #define SPANTMP_PIXEL_FMT GL_BGRA @@ -302,18 +316,15 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont #define TAG(x) intel_YTile_##x##_ARGB8888 #define TAG2(x,y) intel_YTile_##x##_ARGB8888##y -#define GET_PTR(X,Y) y_tile_swizzle(irb, intel, X, Y) -#define GET_PTR_NONLINEAR 1 +#define GET_VALUE(X, Y) pread_32(irb, y_tile_swizzle(irb, intel, X, Y)) +#define PUT_VALUE(X, Y, V) pwrite_32(irb, y_tile_swizzle(irb, intel, X, Y), V) #include "spantmp2.h" #define LOCAL_DEPTH_VARS \ struct intel_context *intel = intel_context(ctx); \ struct intel_renderbuffer *irb = intel_renderbuffer(rb); \ - const GLuint pitch = irb->pfPitch/***XXX region->pitch*/; /* in pixels */ \ const GLint yScale = irb->RenderToTexture ? 1 : -1; \ - const GLint yBias = irb->RenderToTexture ? 0 : irb->Base.Height - 1; \ - char *buf = (char *) irb->pfMap/*XXX use region->map*/ + \ - (intel->drawY * pitch + intel->drawX) * irb->region->cpp; (void) buf; + const GLint yBias = irb->RenderToTexture ? 0 : irb->Base.Height - 1; #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS @@ -321,13 +332,10 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont /** ** 16-bit depthbuffer functions. **/ -#define WRITE_DEPTH( _x, _y, d ) \ - ((GLushort *)buf)[(_x) + (_y) * pitch] = d; - -#define READ_DEPTH( d, _x, _y ) \ - d = ((GLushort *)buf)[(_x) + (_y) * pitch]; - - +#define WRITE_DEPTH(_x, _y, d) \ + pwrite_16(irb, no_tile_swizzle(irb, intel, _x, _y), d) +#define READ_DEPTH(d, _x, _y) \ + d = pread_16(irb, no_tile_swizzle(irb, intel, _x, _y)) #define TAG(x) intel##x##_z16 #include "depthtmp.h" @@ -335,26 +343,20 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont /** ** 16-bit x tile depthbuffer functions. **/ -#define WRITE_DEPTH( _x, _y, d ) \ - (*((GLushort *)x_tile_swizzle (irb, intel, _x, _y)) = d) - -#define READ_DEPTH( d, _x, _y ) \ - d = *((GLushort *)x_tile_swizzle (irb, intel, _x, _y)) - - +#define WRITE_DEPTH(_x, _y, d) \ + pwrite_16(irb, x_tile_swizzle(irb, intel, _x, _y), d) +#define READ_DEPTH(d, _x, _y) \ + d = pread_16(irb, x_tile_swizzle(irb, intel, _x, _y)) #define TAG(x) intel_XTile_##x##_z16 #include "depthtmp.h" /** ** 16-bit y tile depthbuffer functions. **/ -#define WRITE_DEPTH( _x, _y, d ) \ - (*((GLushort *)y_tile_swizzle (irb, intel, _x, _y)) = d) - -#define READ_DEPTH( d, _x, _y ) \ - (d = *((GLushort *)y_tile_swizzle (irb, intel, _x, _y))) - - +#define WRITE_DEPTH(_x, _y, d) \ + pwrite_16(irb, y_tile_swizzle(irb, intel, _x, _y), d) +#define READ_DEPTH(d, _x, _y) \ + d = pread_16(irb, y_tile_swizzle(irb, intel, _x, _y)) #define TAG(x) intel_YTile_##x##_z16 #include "depthtmp.h" @@ -366,14 +368,13 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont ** and stencil values. **/ /* Change ZZZS -> SZZZ */ -#define WRITE_DEPTH( _x, _y, d ) { \ - GLuint tmp = ((d) >> 8) | ((d) << 24); \ - ((GLuint *)buf)[(_x) + (_y) * pitch] = tmp; \ -} +#define WRITE_DEPTH(_x, _y, d) \ + pwrite_32(irb, no_tile_swizzle(irb, intel, _x, _y), \ + ((d) >> 8) | ((d) << 24)) /* Change SZZZ -> ZZZS */ #define READ_DEPTH( d, _x, _y ) { \ - GLuint tmp = ((GLuint *)buf)[(_x) + (_y) * pitch]; \ + GLuint tmp = pread_32(irb, no_tile_swizzle(irb, intel, _x, _y)); \ d = (tmp << 8) | (tmp >> 24); \ } @@ -388,14 +389,13 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont ** and stencil values. **/ /* Change ZZZS -> SZZZ */ -#define WRITE_DEPTH( _x, _y, d ) { \ - GLuint tmp = ((d) >> 8) | ((d) << 24); \ - *((GLuint *)x_tile_swizzle (irb, intel, _x, _y)) = tmp; \ -} +#define WRITE_DEPTH(_x, _y, d) \ + pwrite_32(irb, x_tile_swizzle(irb, intel, _x, _y), \ + ((d) >> 8) | ((d) << 24)) \ /* Change SZZZ -> ZZZS */ #define READ_DEPTH( d, _x, _y ) { \ - GLuint tmp = *((GLuint *)x_tile_swizzle (irb, intel, _x, _y)); \ + GLuint tmp = pread_32(irb, x_tile_swizzle(irb, intel, _x, _y)); \ d = (tmp << 8) | (tmp >> 24); \ } @@ -409,14 +409,13 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont ** and stencil values. **/ /* Change ZZZS -> SZZZ */ -#define WRITE_DEPTH( _x, _y, d ) { \ - GLuint tmp = ((d) >> 8) | ((d) << 24); \ - *((GLuint *)y_tile_swizzle (irb, intel, _x, _y)) = tmp; \ -} +#define WRITE_DEPTH(_x, _y, d) \ + pwrite_32(irb, y_tile_swizzle(irb, intel, _x, _y), \ + ((d) >> 8) | ((d) << 24)) /* Change SZZZ -> ZZZS */ #define READ_DEPTH( d, _x, _y ) { \ - GLuint tmp = *((GLuint *)y_tile_swizzle (irb, intel, _x, _y)); \ + GLuint tmp = pread_32(irb, y_tile_swizzle(irb, intel, _x, _y)); \ d = (tmp << 8) | (tmp >> 24); \ } @@ -427,15 +426,11 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont /** ** 8-bit stencil function (XXX FBO: This is obsolete) **/ -#define WRITE_STENCIL( _x, _y, d ) { \ - GLuint tmp = ((GLuint *)buf)[(_x) + (_y) * pitch]; \ - tmp &= 0xffffff; \ - tmp |= ((d) << 24); \ - ((GLuint *) buf)[(_x) + (_y) * pitch] = tmp; \ -} +#define WRITE_STENCIL(_x, _y, d) \ + pwrite_8(irb, no_tile_swizzle(irb, intel, _x, _y) + 3, d) -#define READ_STENCIL( d, _x, _y ) \ - d = ((GLuint *)buf)[(_x) + (_y) * pitch] >> 24; +#define READ_STENCIL(d, _x, _y) \ + d = pread_8(irb, no_tile_swizzle(irb, intel, _x, _y) + 3); #define TAG(x) intel##x##_z24_s8 #include "stenciltmp.h" @@ -443,16 +438,11 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont /** ** 8-bit x-tile stencil function (XXX FBO: This is obsolete) **/ -#define WRITE_STENCIL( _x, _y, d ) { \ - GLuint *a = (GLuint *) x_tile_swizzle (irb, intel, _x, _y); \ - GLuint tmp = *a; \ - tmp &= 0xffffff; \ - tmp |= ((d) << 24); \ - *a = tmp; \ -} +#define WRITE_STENCIL(_x, _y, d) \ + pwrite_8(irb, x_tile_swizzle(irb, intel, _x, _y) + 3, d) -#define READ_STENCIL( d, _x, _y ) \ - (d = *((GLuint*) x_tile_swizzle (irb, intel, _x, _y)) >> 24) +#define READ_STENCIL(d, _x, _y) \ + d = pread_8(irb, x_tile_swizzle(irb, intel, _x, _y) + 3); #define TAG(x) intel_XTile_##x##_z24_s8 #include "stenciltmp.h" @@ -460,16 +450,11 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont /** ** 8-bit y-tile stencil function (XXX FBO: This is obsolete) **/ -#define WRITE_STENCIL( _x, _y, d ) { \ - GLuint *a = (GLuint *) y_tile_swizzle (irb, intel, _x, _y); \ - GLuint tmp = *a; \ - tmp &= 0xffffff; \ - tmp |= ((d) << 24); \ - *a = tmp; \ -} +#define WRITE_STENCIL(_x, _y, d) \ + pwrite_8(irb, y_tile_swizzle(irb, intel, _x, _y) + 3, d) -#define READ_STENCIL( d, _x, _y ) \ - (d = *((GLuint*) y_tile_swizzle (irb, intel, _x, _y)) >> 24) +#define READ_STENCIL(d, _x, _y) \ + d = pread_8(irb, y_tile_swizzle(irb, intel, _x, _y) + 3) #define TAG(x) intel_YTile_##x##_z24_s8 #include "stenciltmp.h" @@ -482,9 +467,6 @@ intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb) if (irb == NULL || irb->region == NULL) return; - intel_region_map(intel, irb->region); - - irb->pfMap = irb->region->map; irb->pfPitch = irb->region->pitch; intel_set_span_functions(intel, rb); @@ -499,9 +481,6 @@ intel_renderbuffer_unmap(struct intel_context *intel, if (irb == NULL || irb->region == NULL) return; - intel_region_unmap(intel, irb->region); - - irb->pfMap = NULL; irb->pfPitch = 0; rb->GetRow = NULL; @@ -559,35 +538,6 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map) else intel_renderbuffer_unmap(intel, ctx->ReadBuffer->_ColorReadBuffer); - /* Account for front/back color page flipping. - * The span routines use the pfMap and pfPitch fields which will - * swap the front/back region map/pitch if we're page flipped. - * Do this after mapping, above, so the map field is valid. - */ -#if 0 - if (map && ctx->DrawBuffer->Name == 0) { - struct intel_renderbuffer *irbFront - = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_FRONT_LEFT); - struct intel_renderbuffer *irbBack - = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_BACK_LEFT); - if (irbBack) { - /* double buffered */ - if (intel->sarea->pf_current_page == 0) { - irbFront->pfMap = irbFront->region->map; - irbFront->pfPitch = irbFront->region->pitch; - irbBack->pfMap = irbBack->region->map; - irbBack->pfPitch = irbBack->region->pitch; - } - else { - irbFront->pfMap = irbBack->region->map; - irbFront->pfPitch = irbBack->region->pitch; - irbBack->pfMap = irbFront->region->map; - irbBack->pfPitch = irbFront->region->pitch; - } - } - } -#endif - /* depth buffer (Note wrapper!) */ if (ctx->DrawBuffer->_DepthBuffer) { if (map) -- cgit v1.2.3 From 2e3714380027252ba17a11f23eae851d3f77ab02 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 23 Jul 2008 09:17:07 -0700 Subject: intel: Add a little span cache to spead up readpixels by cutting syscalls. --- src/mesa/drivers/dri/intel/intel_fbo.c | 3 +++ src/mesa/drivers/dri/intel/intel_fbo.h | 3 +++ src/mesa/drivers/dri/intel/intel_span.c | 48 ++++++++++++++++++++++++--------- 3 files changed, 42 insertions(+), 12 deletions(-) (limited to 'src/mesa/drivers/dri/intel/intel_fbo.h') diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index d539097a66..254f3efae0 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -153,6 +153,9 @@ intel_delete_renderbuffer(struct gl_renderbuffer *rb) intel_unpair_depth_stencil(ctx, irb); } + if (irb->span_cache != NULL) + _mesa_free(irb->span_cache); + if (intel && irb->region) { intel_region_release(&irb->region); } diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h index f55d3747f2..9d15582d78 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.h +++ b/src/mesa/drivers/dri/intel/intel_fbo.h @@ -79,6 +79,9 @@ struct intel_renderbuffer GLuint pf_pending; /**< sequence number of pending flip */ GLuint vbl_pending; /**< vblank sequence number of pending flip */ + + uint8_t *span_cache; + unsigned long span_cache_offset; }; extern struct intel_renderbuffer *intel_renderbuffer(struct gl_renderbuffer diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index 44e2eff680..06f7c9b4b7 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -43,51 +43,74 @@ static void intel_set_span_functions(struct intel_context *intel, struct gl_renderbuffer *rb); +#define SPAN_CACHE_SIZE 4096 + +static void +get_span_cache(struct intel_renderbuffer *irb, uint32_t offset) +{ + if (irb->span_cache == NULL) { + irb->span_cache = _mesa_malloc(SPAN_CACHE_SIZE); + irb->span_cache_offset = -1; + } + + if ((offset & ~(SPAN_CACHE_SIZE - 1)) != irb->span_cache_offset) { + irb->span_cache_offset = offset & ~(SPAN_CACHE_SIZE - 1); + dri_bo_get_subdata(irb->region->buffer, irb->span_cache_offset, + SPAN_CACHE_SIZE, irb->span_cache); + } +} + +static void +clear_span_cache(struct intel_renderbuffer *irb) +{ + irb->span_cache_offset = -1; +} + static uint32_t pread_32(struct intel_renderbuffer *irb, uint32_t offset) { - uint32_t val; + get_span_cache(irb, offset); - dri_bo_get_subdata(irb->region->buffer, offset, 4, &val); - - return val; + return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))); } static uint16_t pread_16(struct intel_renderbuffer *irb, uint32_t offset) { - uint16_t val; - - dri_bo_get_subdata(irb->region->buffer, offset, 2, &val); + get_span_cache(irb, offset); - return val; + return *(uint16_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))); } static uint8_t pread_8(struct intel_renderbuffer *irb, uint32_t offset) { - uint8_t val; + get_span_cache(irb, offset); - dri_bo_get_subdata(irb->region->buffer, offset, 1, &val); - - return val; + return *(uint8_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))); } static void pwrite_32(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val) { + clear_span_cache(irb); + dri_bo_subdata(irb->region->buffer, offset, 4, &val); } static void pwrite_16(struct intel_renderbuffer *irb, uint32_t offset, uint16_t val) { + clear_span_cache(irb); + dri_bo_subdata(irb->region->buffer, offset, 2, &val); } static void pwrite_8(struct intel_renderbuffer *irb, uint32_t offset, uint8_t val) { + clear_span_cache(irb); + dri_bo_subdata(irb->region->buffer, offset, 1, &val); } @@ -481,6 +504,7 @@ intel_renderbuffer_unmap(struct intel_context *intel, if (irb == NULL || irb->region == NULL) return; + clear_span_cache(irb); irb->pfPitch = 0; rb->GetRow = NULL; -- cgit v1.2.3