From 17ef1f6074d6107c167f1956a5c60993904c0b72 Mon Sep 17 00:00:00 2001 From: Chia-I Wu Date: Thu, 8 Oct 2009 10:33:57 +0800 Subject: mesa: Enable remap table in core. This enables the remap table in core. driInitExtensions is adapted to use the remap table. All uses of extension_helper.h are replaced by remap_helper.h. The chicken-egg problem of the DRI drivers is also solved. It is now also possible to pass NULL extensions to driInitExtensions. It will cause driInitExtensions to map all known functions. This functionality is used by software drivers and EGL_i915. Signed-off-by: Chia-I Wu --- src/mesa/drivers/dri/intel/intel_screen.c | 24 ------------------------ 1 file changed, 24 deletions(-) (limited to 'src/mesa/drivers/dri/intel/intel_screen.c') diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index 24f7fbc992..41342ddcae 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -696,18 +696,6 @@ static const __DRIconfig **intelInitScreen(__DRIscreenPrivate *psp) return NULL; } - /* Calling driInitExtensions here, with a NULL context pointer, - * does not actually enable the extensions. It just makes sure - * that all the dispatch offsets for all the extensions that - * *might* be enables are known. This is needed because the - * dispatch offsets need to be known when _mesa_context_create is - * called, but we can't enable the extensions until we have a - * context pointer. - * - * Hello chicken. Hello egg. How are you two today? - */ - intelInitExtensions(NULL, GL_TRUE); - if (!intelInitDriver(psp)) return NULL; @@ -760,18 +748,6 @@ __DRIconfig **intelInitScreen2(__DRIscreenPrivate *psp) int color; __DRIconfig **configs = NULL; - /* Calling driInitExtensions here, with a NULL context pointer, - * does not actually enable the extensions. It just makes sure - * that all the dispatch offsets for all the extensions that - * *might* be enables are known. This is needed because the - * dispatch offsets need to be known when _mesa_context_create is - * called, but we can't enable the extensions until we have a - * context pointer. - * - * Hello chicken. Hello egg. How are you two today? - */ - intelInitExtensions(NULL, GL_TRUE); - /* Allocate the private area */ intelScreen = (intelScreenPrivate *) CALLOC(sizeof(intelScreenPrivate)); if (!intelScreen) { -- cgit v1.2.3 From 4a253431abf43a0638afb43605b44a8742b72a60 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Thu, 29 Oct 2009 19:12:50 -0600 Subject: intel: update intel_create_renderbuffer(format), add XRGB support Pass a gl_format to intel_create_renderbuffer() instead of GLenum. Add cases for MESA_FORMAT_XRGB8888 textures and renderbuffers. However, we don't yet create any renderbuffers or textures with that format. It seems the default alpha value is zero instead of one. Need to investigate that first. --- src/mesa/drivers/dri/i915/i830_texstate.c | 2 ++ src/mesa/drivers/dri/i915/i830_vtbl.c | 1 + src/mesa/drivers/dri/i915/i915_texstate.c | 2 ++ src/mesa/drivers/dri/i915/i915_vtbl.c | 1 + src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 7 ++++ src/mesa/drivers/dri/intel/intel_blit.c | 1 + src/mesa/drivers/dri/intel/intel_fbo.c | 44 +++++++++--------------- src/mesa/drivers/dri/intel/intel_fbo.h | 2 +- src/mesa/drivers/dri/intel/intel_pixel_draw.c | 2 +- src/mesa/drivers/dri/intel/intel_screen.c | 14 ++++---- src/mesa/drivers/dri/intel/intel_span.c | 15 ++++++++ src/mesa/drivers/dri/intel/intel_tex_format.c | 2 ++ 12 files changed, 57 insertions(+), 36 deletions(-) (limited to 'src/mesa/drivers/dri/intel/intel_screen.c') diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c index 28263fbe3c..f4bbb53b86 100644 --- a/src/mesa/drivers/dri/i915/i830_texstate.c +++ b/src/mesa/drivers/dri/i915/i830_texstate.c @@ -59,6 +59,8 @@ translate_texture_format(GLuint mesa_format, GLuint internal_format) return MAPSURF_32BIT | MT_32BIT_XRGB8888; else return MAPSURF_32BIT | MT_32BIT_ARGB8888; + case MESA_FORMAT_XRGB8888: + return MAPSURF_32BIT | MT_32BIT_XRGB8888; case MESA_FORMAT_YCBCR_REV: return (MAPSURF_422 | MT_422_YCRCB_NORMAL); case MESA_FORMAT_YCBCR: diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c index 22f8bc7f19..4133696129 100644 --- a/src/mesa/drivers/dri/i915/i830_vtbl.c +++ b/src/mesa/drivers/dri/i915/i830_vtbl.c @@ -647,6 +647,7 @@ i830_state_draw_region(struct intel_context *intel, if (irb != NULL) { switch (irb->texformat) { case MESA_FORMAT_ARGB8888: + case MESA_FORMAT_XRGB8888: value |= DV_PF_8888; break; case MESA_FORMAT_RGB565: diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index bea47f5af8..d6689af53f 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -60,6 +60,8 @@ translate_texture_format(gl_format mesa_format, GLuint internal_format, return MAPSURF_32BIT | MT_32BIT_XRGB8888; else return MAPSURF_32BIT | MT_32BIT_ARGB8888; + case MESA_FORMAT_XRGB8888: + return MAPSURF_32BIT | MT_32BIT_XRGB8888; case MESA_FORMAT_YCBCR_REV: return (MAPSURF_422 | MT_422_YCRCB_NORMAL); case MESA_FORMAT_YCBCR: diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index d84df1a142..3c1b2dd0b0 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -589,6 +589,7 @@ i915_state_draw_region(struct intel_context *intel, if (irb != NULL) { switch (irb->texformat) { case MESA_FORMAT_ARGB8888: + case MESA_FORMAT_XRGB8888: value |= DV_PF_8888; break; case MESA_FORMAT_RGB565: diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 3b2c6a25be..0bf735c0f2 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -96,7 +96,11 @@ static GLuint translate_tex_format( gl_format mesa_format, else return BRW_SURFACEFORMAT_B8G8R8A8_UNORM; + case MESA_FORMAT_XRGB8888: + return BRW_SURFACEFORMAT_B8G8R8X8_UNORM; + case MESA_FORMAT_RGBA8888_REV: + _mesa_problem(NULL, "unexpected format in i965:translate_tex_format()"); if (internal_format == GL_RGB) return BRW_SURFACEFORMAT_R8G8B8X8_UNORM; else @@ -531,6 +535,9 @@ brw_update_renderbuffer_surface(struct brw_context *brw, case MESA_FORMAT_ARGB8888: key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; break; + case MESA_FORMAT_XRGB8888: + key.surface_format = BRW_SURFACEFORMAT_B8G8R8X8_UNORM; + break; case MESA_FORMAT_RGB565: key.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM; break; diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index 55d97a0f76..817223da41 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -498,6 +498,7 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) switch (irb->texformat) { case MESA_FORMAT_ARGB8888: + case MESA_FORMAT_XRGB8888: clearVal = intel->ClearColor8888; break; case MESA_FORMAT_RGB565: diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index d006389f5a..9c780d40cc 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -292,7 +292,7 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *rb, * not a user-created renderbuffer. */ struct intel_renderbuffer * -intel_create_renderbuffer(GLenum intFormat) +intel_create_renderbuffer(gl_format format) { GET_CURRENT_CONTEXT(ctx); @@ -308,48 +308,30 @@ intel_create_renderbuffer(GLenum intFormat) _mesa_init_renderbuffer(&irb->Base, name); irb->Base.ClassID = INTEL_RB_CLASS; - switch (intFormat) { - case GL_RGB5: - irb->Base.Format = MESA_FORMAT_RGB565; + switch (format) { + case MESA_FORMAT_RGB565: irb->Base._BaseFormat = GL_RGB; irb->Base.DataType = GL_UNSIGNED_BYTE; - irb->texformat = MESA_FORMAT_RGB565; break; - case GL_RGB8: - irb->Base.Format = MESA_FORMAT_ARGB8888; /* XXX: NEED XRGB8888 */ + case MESA_FORMAT_XRGB8888: irb->Base._BaseFormat = GL_RGB; irb->Base.DataType = GL_UNSIGNED_BYTE; - irb->texformat = MESA_FORMAT_ARGB8888; /* XXX: NEED XRGB8888 */ break; - case GL_RGBA8: - irb->Base.Format = MESA_FORMAT_ARGB8888; + case MESA_FORMAT_ARGB8888: irb->Base._BaseFormat = GL_RGBA; irb->Base.DataType = GL_UNSIGNED_BYTE; - irb->texformat = MESA_FORMAT_ARGB8888; - break; - case GL_STENCIL_INDEX8_EXT: - irb->Base.Format = MESA_FORMAT_S8_Z24; - irb->Base._BaseFormat = GL_STENCIL_INDEX; - irb->Base.DataType = GL_UNSIGNED_BYTE; - irb->texformat = MESA_FORMAT_S8_Z24; break; - case GL_DEPTH_COMPONENT16: - irb->Base.Format = MESA_FORMAT_Z16; + case MESA_FORMAT_Z16: irb->Base._BaseFormat = GL_DEPTH_COMPONENT; irb->Base.DataType = GL_UNSIGNED_SHORT; - irb->texformat = MESA_FORMAT_Z16; break; - case GL_DEPTH_COMPONENT24: - irb->Base.Format = MESA_FORMAT_S8_Z24; + case MESA_FORMAT_X8_Z24: irb->Base._BaseFormat = GL_DEPTH_COMPONENT; irb->Base.DataType = GL_UNSIGNED_INT; - irb->texformat = MESA_FORMAT_S8_Z24; break; - case GL_DEPTH24_STENCIL8_EXT: - irb->Base.Format = MESA_FORMAT_S8_Z24; + case MESA_FORMAT_S8_Z24: irb->Base._BaseFormat = GL_DEPTH_STENCIL; irb->Base.DataType = GL_UNSIGNED_INT_24_8_EXT; - irb->texformat = MESA_FORMAT_S8_Z24; break; default: _mesa_problem(NULL, @@ -358,7 +340,10 @@ intel_create_renderbuffer(GLenum intFormat) return NULL; } - irb->Base.InternalFormat = intFormat; + assert(irb->Base._BaseFormat == _mesa_get_format_base_format(format)); + irb->Base.Format = format; + irb->Base.InternalFormat = irb->Base._BaseFormat; + irb->texformat = format; /* intel-specific methods */ irb->Base.Delete = intel_delete_renderbuffer; @@ -442,6 +427,10 @@ intel_update_wrapper(GLcontext *ctx, struct intel_renderbuffer *irb, irb->Base.DataType = GL_UNSIGNED_BYTE; DBG("Render to RGBA8 texture OK\n"); } + else if (texImage->TexFormat == MESA_FORMAT_XRGB8888) { + irb->Base.DataType = GL_UNSIGNED_BYTE; + DBG("Render to XGBA8 texture OK\n"); + } else if (texImage->TexFormat == MESA_FORMAT_RGB565) { irb->Base.DataType = GL_UNSIGNED_BYTE; DBG("Render to RGB5 texture OK\n"); @@ -644,6 +633,7 @@ intel_validate_framebuffer(GLcontext *ctx, struct gl_framebuffer *fb) switch (irb->texformat) { case MESA_FORMAT_ARGB8888: + case MESA_FORMAT_XRGB8888: case MESA_FORMAT_RGB565: case MESA_FORMAT_ARGB1555: case MESA_FORMAT_ARGB4444: diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h index e0584e3494..50a8a95985 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.h +++ b/src/mesa/drivers/dri/intel/intel_fbo.h @@ -115,7 +115,7 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *irb, extern struct intel_renderbuffer * -intel_create_renderbuffer(GLenum intFormat); +intel_create_renderbuffer(gl_format format); extern void diff --git a/src/mesa/drivers/dri/intel/intel_pixel_draw.c b/src/mesa/drivers/dri/intel/intel_pixel_draw.c index 5ffa847fd4..9b382e3622 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_draw.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_draw.c @@ -169,7 +169,7 @@ intel_stencil_drawpixels(GLcontext * ctx, * buffer. */ depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH); - irb = intel_create_renderbuffer(GL_RGBA8); + irb = intel_create_renderbuffer(MESA_FORMAT_ARGB8888); rb = &irb->Base; irb->Base.Width = depth_irb->Base.Width; irb->Base.Height = depth_irb->Base.Height; diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index 41342ddcae..62c322b4ed 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -349,7 +349,7 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv, else { GLboolean swStencil = (mesaVis->stencilBits > 0 && mesaVis->depthBits != 24); - GLenum rgbFormat; + gl_format rgbFormat; struct intel_framebuffer *intel_fb = CALLOC_STRUCT(intel_framebuffer); @@ -359,11 +359,11 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv, _mesa_initialize_framebuffer(&intel_fb->Base, mesaVis); if (mesaVis->redBits == 5) - rgbFormat = GL_RGB5; + rgbFormat = MESA_FORMAT_RGB565; else if (mesaVis->alphaBits == 0) - rgbFormat = GL_RGB8; + rgbFormat = MESA_FORMAT_ARGB8888; /* XXX change to XRGB someday */ else - rgbFormat = GL_RGBA8; + rgbFormat = MESA_FORMAT_ARGB8888; /* setup the hardware-based renderbuffers */ intel_fb->color_rb[0] = intel_create_renderbuffer(rgbFormat); @@ -382,7 +382,7 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv, if (mesaVis->stencilBits == 8) { /* combined depth/stencil buffer */ struct intel_renderbuffer *depthStencilRb - = intel_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT); + = intel_create_renderbuffer(MESA_FORMAT_S8_Z24); /* note: bind RB to two attachment points */ _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH, &depthStencilRb->Base); @@ -390,7 +390,7 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv, &depthStencilRb->Base); } else { struct intel_renderbuffer *depthRb - = intel_create_renderbuffer(GL_DEPTH_COMPONENT24); + = intel_create_renderbuffer(MESA_FORMAT_X8_Z24); _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH, &depthRb->Base); } @@ -398,7 +398,7 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv, else if (mesaVis->depthBits == 16) { /* just 16-bit depth buffer, no hw stencil */ struct intel_renderbuffer *depthRb - = intel_create_renderbuffer(GL_DEPTH_COMPONENT16); + = intel_create_renderbuffer(MESA_FORMAT_Z16); _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH, &depthRb->Base); } diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index a36c077fbd..b0484a9959 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -651,8 +651,23 @@ intel_set_span_functions(struct intel_context *intel, break; } break; + case MESA_FORMAT_XRGB8888: + switch (tiling) { + case I915_TILING_NONE: + default: + intelInitPointers_xRGB8888(rb); + break; + case I915_TILING_X: + intel_XTile_InitPointers_xRGB8888(rb); + break; + case I915_TILING_Y: + intel_YTile_InitPointers_xRGB8888(rb); + break; + } + break; case MESA_FORMAT_ARGB8888: if (0 /*rb->AlphaBits == 0*/) { /* XXX: Need xRGB8888 Mesa format */ + /* XXX remove this code someday when we enable XRGB surfaces */ /* 8888 RGBx */ switch (tiling) { case I915_TILING_NONE: diff --git a/src/mesa/drivers/dri/intel/intel_tex_format.c b/src/mesa/drivers/dri/intel/intel_tex_format.c index eca0f6d572..f37a545c7f 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_format.c +++ b/src/mesa/drivers/dri/intel/intel_tex_format.c @@ -50,6 +50,7 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, if (format == GL_RGB && type == GL_UNSIGNED_SHORT_5_6_5) { return MESA_FORMAT_RGB565; } + /* XXX use MESA_FORMAT_XRGB8888 someday */ return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_RGB565; case GL_RGBA8: @@ -69,6 +70,7 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, case GL_RGB10: case GL_RGB12: case GL_RGB16: + /* XXX use MESA_FORMAT_XRGB8888 someday */ return MESA_FORMAT_ARGB8888; case GL_RGB5: -- cgit v1.2.3 From 409469fb70682cd819ab405e0f92a4659381cfbe Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Fri, 30 Oct 2009 09:12:11 -0600 Subject: intel: fix up some XRGB breakage We weren't choosing the right XRGB span functions for reading the framebuffer. XRGB formats still aren't turned on yet though. --- src/mesa/drivers/dri/intel/intel_fbo.c | 5 ++++- src/mesa/drivers/dri/intel/intel_screen.c | 2 +- src/mesa/drivers/dri/intel/intel_span.c | 2 +- 3 files changed, 6 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/intel/intel_screen.c') diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 9c780d40cc..d8ac4d3663 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -314,6 +314,10 @@ intel_create_renderbuffer(gl_format format) irb->Base.DataType = GL_UNSIGNED_BYTE; break; case MESA_FORMAT_XRGB8888: + /* XXX this is a hack since XRGB surfaces don't seem to work + * properly yet. Reading the alpha channel returns 0 instead of 1. + */ + format = MESA_FORMAT_ARGB8888; irb->Base._BaseFormat = GL_RGB; irb->Base.DataType = GL_UNSIGNED_BYTE; break; @@ -340,7 +344,6 @@ intel_create_renderbuffer(gl_format format) return NULL; } - assert(irb->Base._BaseFormat == _mesa_get_format_base_format(format)); irb->Base.Format = format; irb->Base.InternalFormat = irb->Base._BaseFormat; irb->texformat = format; diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index 62c322b4ed..789135b49f 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -361,7 +361,7 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv, if (mesaVis->redBits == 5) rgbFormat = MESA_FORMAT_RGB565; else if (mesaVis->alphaBits == 0) - rgbFormat = MESA_FORMAT_ARGB8888; /* XXX change to XRGB someday */ + rgbFormat = MESA_FORMAT_XRGB8888; else rgbFormat = MESA_FORMAT_ARGB8888; diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index b0484a9959..927e4fd982 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -666,7 +666,7 @@ intel_set_span_functions(struct intel_context *intel, } break; case MESA_FORMAT_ARGB8888: - if (0 /*rb->AlphaBits == 0*/) { /* XXX: Need xRGB8888 Mesa format */ + if (rb->_BaseFormat == GL_RGB) { /* XXX remove this code someday when we enable XRGB surfaces */ /* 8888 RGBx */ switch (tiling) { -- cgit v1.2.3 From 827ba44f6ee83ab21c6a2b09323f6f1df4a7d4c8 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 18 Nov 2009 18:15:25 +0100 Subject: intel: Remove non-GEM support. This really isn't supported at this point. GEM's been in the kernel for a year, and the fake bufmgr never really worked. --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 8 ---- src/mesa/drivers/dri/intel/intel_batchbuffer.c | 4 +- src/mesa/drivers/dri/intel/intel_context.c | 38 ++++------------- src/mesa/drivers/dri/intel/intel_context.h | 6 --- src/mesa/drivers/dri/intel/intel_extensions.c | 14 ++----- src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 16 +++----- src/mesa/drivers/dri/intel/intel_regions.c | 57 +++++--------------------- src/mesa/drivers/dri/intel/intel_screen.c | 38 ++++------------- src/mesa/drivers/dri/intel/intel_screen.h | 1 - src/mesa/drivers/dri/intel/intel_span.c | 13 ++---- 10 files changed, 43 insertions(+), 152 deletions(-) (limited to 'src/mesa/drivers/dri/intel/intel_screen.c') diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 271a88dae0..7c796dae93 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -243,14 +243,6 @@ static void wrap_buffers( struct brw_context *brw, dri_bo_unreference(brw->vb.upload.bo); brw->vb.upload.bo = dri_bo_alloc(brw->intel.bufmgr, "temporary VBO", size, 1); - - /* Set the internal VBO\ to no-backing-store. We only use them as a - * temporary within a brw_try_draw_prims while the lock is held. - */ - /* DON'T DO THIS AS IF WE HAVE TO RE-ORG MEMORY WE NEED SOMEWHERE WITH - FAKE TO PUSH THIS STUFF */ -// if (!brw->intel.ttm) -// dri_bo_fake_disable_backing_store(brw->vb.upload.bo, NULL, NULL); } static void get_space( struct brw_context *brw, diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c index 12c5a30d6b..2eae9b66d8 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c @@ -80,7 +80,7 @@ intel_batchbuffer_reset(struct intel_batchbuffer *batch) batch->buf = NULL; } - if (!batch->buffer && intel->ttm == GL_TRUE) + if (!batch->buffer) batch->buffer = malloc (intel->maxBatchSize); batch->buf = dri_bo_alloc(intel->bufmgr, "batchbuffer", @@ -212,7 +212,7 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file, batch->reserved_space = 0; /* Emit a flush if the bufmgr doesn't do it for us. */ - if (intel->always_flush_cache || !intel->ttm) { + if (intel->always_flush_cache) { intel_batchbuffer_emit_mi_flush(batch); used = batch->ptr - batch->map; } diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index 7b7c0a0b5a..1434ae530b 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -176,9 +176,7 @@ intelGetString(GLcontext * ctx, GLenum name) break; } - (void) driGetRendererString(buffer, chipset, - (intel->ttm) ? DRIVER_DATE_GEM : DRIVER_DATE, - 0); + (void) driGetRendererString(buffer, chipset, DRIVER_DATE_GEM, 0); return (GLubyte *) buffer; default: @@ -601,6 +599,7 @@ intelInitContext(struct intel_context *intel, __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; intelScreenPrivate *intelScreen = (intelScreenPrivate *) sPriv->private; int fthrottle_mode; + int bo_reuse_mode; if (!_mesa_initialize_context(&intel->ctx, mesaVis, shareCtx, functions, (void *) intel)) { @@ -635,18 +634,14 @@ intelInitContext(struct intel_context *intel, intel->maxBatchSize = BATCH_SZ; intel->bufmgr = intelScreen->bufmgr; - intel->ttm = intelScreen->ttm; - if (intel->ttm) { - int bo_reuse_mode; - bo_reuse_mode = driQueryOptioni(&intel->optionCache, "bo_reuse"); - switch (bo_reuse_mode) { - case DRI_CONF_BO_REUSE_DISABLED: - break; - case DRI_CONF_BO_REUSE_ALL: - intel_bufmgr_gem_enable_reuse(intel->bufmgr); - break; - } + bo_reuse_mode = driQueryOptioni(&intel->optionCache, "bo_reuse"); + switch (bo_reuse_mode) { + case DRI_CONF_BO_REUSE_DISABLED: + break; + case DRI_CONF_BO_REUSE_ALL: + intel_bufmgr_gem_enable_reuse(intel->bufmgr); + break; } /* This doesn't yet catch all non-conformant rendering, but it's a @@ -1052,21 +1047,6 @@ intelContendedLock(struct intel_context *intel, GLuint flags) sarea->ctxOwner = me; } - /* If the last consumer of the texture memory wasn't us, notify the fake - * bufmgr and record the new owner. We should have the memory shared - * between contexts of a single fake bufmgr, but this will at least make - * things correct for now. - */ - if (!intel->ttm && sarea->texAge != intel->hHWContext) { - sarea->texAge = intel->hHWContext; - intel_bufmgr_fake_contended_lock_take(intel->bufmgr); - if (INTEL_DEBUG & DEBUG_BATCH) - intel_decode_context_reset(); - if (INTEL_DEBUG & DEBUG_BUFMGR) - fprintf(stderr, "Lost Textures: sarea->texAge %x hw context %x\n", - sarea->ctxOwner, intel->hHWContext); - } - /* Drawable changed? */ if (dPriv && intel->lastStamp != dPriv->lastStamp) { diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index f16f502c1d..481202c971 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -181,12 +181,6 @@ struct intel_context struct intel_region *back_region; struct intel_region *depth_region; - /** - * This value indicates that the kernel memory manager is being used - * instead of the fake client-side memory manager. - */ - GLboolean ttm; - struct intel_batchbuffer *batch; drm_intel_bo *first_post_swapbuffers_batch; GLboolean no_batch_wrap; diff --git a/src/mesa/drivers/dri/intel/intel_extensions.c b/src/mesa/drivers/dri/intel/intel_extensions.c index 1682e115cc..f5fe543b5d 100644 --- a/src/mesa/drivers/dri/intel/intel_extensions.c +++ b/src/mesa/drivers/dri/intel/intel_extensions.c @@ -79,6 +79,7 @@ static const struct dri_extension card_extensions[] = { { "GL_ARB_half_float_pixel", NULL }, { "GL_ARB_map_buffer_range", GL_ARB_map_buffer_range_functions }, { "GL_ARB_multitexture", NULL }, + { "GL_ARB_pixel_buffer_object", NULL }, { "GL_ARB_point_parameters", GL_ARB_point_parameters_functions }, { "GL_ARB_point_sprite", NULL }, { "GL_ARB_shader_objects", GL_ARB_shader_objects_functions }, @@ -104,6 +105,8 @@ static const struct dri_extension card_extensions[] = { { "GL_EXT_blend_logic_op", NULL }, { "GL_EXT_blend_subtract", NULL }, { "GL_EXT_cull_vertex", GL_EXT_cull_vertex_functions }, + { "GL_EXT_framebuffer_blit", GL_EXT_framebuffer_blit_functions }, + { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, { "GL_EXT_fog_coord", GL_EXT_fog_coord_functions }, { "GL_EXT_gpu_program_parameters", GL_EXT_gpu_program_parameters_functions }, { "GL_EXT_packed_depth_stencil", NULL }, @@ -176,14 +179,6 @@ static const struct dri_extension arb_oq_extensions[] = { { NULL, NULL } }; - -static const struct dri_extension ttm_extensions[] = { - { "GL_ARB_pixel_buffer_object", NULL }, - { "GL_EXT_framebuffer_blit", GL_EXT_framebuffer_blit_functions }, - { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, - { NULL, NULL } -}; - static const struct dri_extension fragment_shader_extensions[] = { { "GL_ARB_fragment_shader", NULL }, { NULL, NULL } @@ -202,9 +197,6 @@ intelInitExtensions(GLcontext *ctx) */ driInitExtensions(ctx, card_extensions, GL_FALSE); - if (intel->ttm) - driInitExtensions(ctx, ttm_extensions, GL_FALSE); - if (IS_965(intel->intelScreen->deviceID)) driInitExtensions(ctx, brw_extensions, GL_FALSE); diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index abb3024bfb..6a565f80cf 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -224,16 +224,12 @@ int intel_miptree_pitch_align (struct intel_context *intel, if (!mt->compressed) { int pitch_align; - if (intel->ttm) { - /* XXX: Align pitch to multiple of 64 bytes for now to allow - * render-to-texture to work in all cases. This should probably be - * replaced at some point by some scheme to only do this when really - * necessary. - */ - pitch_align = 64; - } else { - pitch_align = 4; - } + /* XXX: Align pitch to multiple of 64 bytes for now to allow + * render-to-texture to work in all cases. This should probably be + * replaced at some point by some scheme to only do this when really + * necessary. + */ + pitch_align = 64; if (tiling == I915_TILING_X) pitch_align = 512; diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c index 80975163d4..d6b9dc4446 100644 --- a/src/mesa/drivers/dri/intel/intel_regions.c +++ b/src/mesa/drivers/dri/intel/intel_regions.c @@ -542,55 +542,18 @@ intel_recreate_static(struct intel_context *intel, region->buffer = NULL; } - if (intel->ttm) { - assert(region_desc->bo_handle != -1); - region->buffer = intel_bo_gem_create_from_name(intel->bufmgr, - name, - region_desc->bo_handle); - - ret = dri_bo_get_tiling(region->buffer, ®ion->tiling, - ®ion->bit_6_swizzle); - if (ret != 0) { - fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n", - region_desc->bo_handle, name, strerror(-ret)); - intel_region_release(®ion); - return NULL; - } - } else { - if (region->classic_map != NULL) { - drmUnmap(region->classic_map, - region->pitch * region->cpp * region->height); - region->classic_map = NULL; - } - ret = drmMap(intel->driFd, region_desc->handle, - region->pitch * region->cpp * region->height, - ®ion->classic_map); - if (ret != 0) { - fprintf(stderr, "Failed to drmMap %s buffer\n", name); - free(region); - return NULL; - } - - region->buffer = intel_bo_fake_alloc_static(intel->bufmgr, + assert(region_desc->bo_handle != -1); + region->buffer = intel_bo_gem_create_from_name(intel->bufmgr, name, - region_desc->offset, - region->pitch * region->cpp * - region->height, - region->classic_map); - - /* The sarea just gives us a boolean for whether it's tiled or not, - * instead of which tiling mode it is. Guess. - */ - if (region_desc->tiled) { - if (intel->gen >= 4 && region_desc == &intelScreen->depth) - region->tiling = I915_TILING_Y; - else - region->tiling = I915_TILING_X; - } else { - region->tiling = I915_TILING_NONE; - } + region_desc->bo_handle); - region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE; + ret = dri_bo_get_tiling(region->buffer, ®ion->tiling, + ®ion->bit_6_swizzle); + if (ret != 0) { + fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n", + region_desc->bo_handle, name, strerror(-ret)); + intel_region_release(®ion); + return NULL; } assert(region->buffer != NULL); diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index 789135b49f..2c5a884a9b 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -605,7 +605,6 @@ intelFillInModes(__DRIscreenPrivate *psp, static GLboolean intel_init_bufmgr(intelScreenPrivate *intelScreen) { - GLboolean gem_disable = getenv("INTEL_NO_GEM") != NULL; int gem_kernel = 0; GLboolean gem_supported; struct drm_i915_getparam gp; @@ -622,43 +621,24 @@ intel_init_bufmgr(intelScreenPrivate *intelScreen) /* If we've got a new enough DDX that's initializing GEM and giving us * object handles for the shared buffers, use that. */ - intelScreen->ttm = GL_FALSE; if (intelScreen->driScrnPriv->dri2.enabled) gem_supported = GL_TRUE; else if (intelScreen->driScrnPriv->ddx_version.minor >= 9 && gem_kernel && intelScreen->front.bo_handle != -1) gem_supported = GL_TRUE; - else - gem_supported = GL_FALSE; - - if (!gem_disable && gem_supported) { - intelScreen->bufmgr = intel_bufmgr_gem_init(spriv->fd, BATCH_SZ); - if (intelScreen->bufmgr != NULL) - intelScreen->ttm = GL_TRUE; + else { + fprintf(stderr, "[%s:%u] Error initializing GEM.\n", + __func__, __LINE__); + return GL_FALSE; } + + intelScreen->bufmgr = intel_bufmgr_gem_init(spriv->fd, BATCH_SZ); /* Otherwise, use the classic buffer manager. */ if (intelScreen->bufmgr == NULL) { - if (gem_disable) { - _mesa_warning(NULL, "GEM disabled. Using classic."); - } else { - _mesa_warning(NULL, - "Failed to initialize GEM. Falling back to classic."); - } - - if (intelScreen->tex.size == 0) { - fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n", - __func__, __LINE__); - return GL_FALSE; - } - - intelScreen->bufmgr = - intel_bufmgr_fake_init(spriv->fd, - intelScreen->tex.offset, - intelScreen->tex.map, - intelScreen->tex.size, - (unsigned int * volatile) - &intelScreen->sarea->last_dispatch); + fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n", + __func__, __LINE__); + return GL_FALSE; } if (intel_get_param(spriv, I915_PARAM_NUM_FENCES_AVAIL, &num_fences)) diff --git a/src/mesa/drivers/dri/intel/intel_screen.h b/src/mesa/drivers/dri/intel/intel_screen.h index a9b9e109a6..14ca0903b6 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.h +++ b/src/mesa/drivers/dri/intel/intel_screen.h @@ -77,7 +77,6 @@ typedef struct GLboolean no_hw; GLboolean no_vbo; - int ttm; dri_bufmgr *bufmgr; GLboolean kernel_exec_fencing; diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index 3607c7dded..2c89a66a95 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -613,15 +613,7 @@ intel_set_span_functions(struct intel_context *intel, struct gl_renderbuffer *rb) { struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb; - uint32_t tiling; - - /* If in GEM mode, we need to do the tile address swizzling ourselves, - * instead of the fence registers handling it. - */ - if (intel->ttm) - tiling = irb->region->tiling; - else - tiling = I915_TILING_NONE; + uint32_t tiling = irb->region->tiling; if (intel->intelScreen->kernel_exec_fencing) { switch (irb->texformat) { @@ -673,6 +665,9 @@ intel_set_span_functions(struct intel_context *intel, return; } + /* If in GEM mode, we need to do the tile address swizzling ourselves, + * instead of the fence registers handling it. + */ switch (irb->texformat) { case MESA_FORMAT_RGB565: switch (tiling) { -- cgit v1.2.3