From e74f54793e45dd2e36474f6fc527456647f32efd Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 1 Jul 2008 15:09:24 -0700 Subject: intel-gem: Move bit 6 x tiling swizzle to a driconf option, and add new mode. It turns out that it's not just deviceID dependent, and there's some additional undefined factor that determines the bit 6 swizzling. It's now controllable with swizzle_mode=[012] until we get a response on how to automatically detect. --- src/mesa/drivers/dri/intel/intel_screen.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/intel/intel_screen.c') diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index 8fd503ee8b..6597dbffed 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -69,13 +69,20 @@ PUBLIC const char __driConfigOptions[] = DRI_CONF_SECTION_QUALITY DRI_CONF_FORCE_S3TC_ENABLE(false) DRI_CONF_ALLOW_LARGE_TEXTURES(2) + DRI_CONF_OPT_BEGIN_V(swizzle_mode, enum, 0, "0:2") + DRI_CONF_DESC_BEGIN(en, "Tiling swizzle mode for software fallbacks") + DRI_CONF_ENUM(0, "No swizzling") + DRI_CONF_ENUM(1, "addr[6] = addr[6] ^ addr[9]") + DRI_CONF_ENUM(2, "addr[6] = addr[6] ^ addr[9] ^ addr[10]") + DRI_CONF_DESC_END + DRI_CONF_OPT_END DRI_CONF_SECTION_END DRI_CONF_SECTION_DEBUG DRI_CONF_NO_RAST(false) DRI_CONF_SECTION_END DRI_CONF_END; -const GLuint __driNConfigOptions = 6; +const GLuint __driNConfigOptions = 7; #ifdef USE_NEW_INTERFACE static PFNGLXCREATECONTEXTMODES create_context_modes = NULL; -- cgit v1.2.3