From 827ba44f6ee83ab21c6a2b09323f6f1df4a7d4c8 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 18 Nov 2009 18:15:25 +0100 Subject: intel: Remove non-GEM support. This really isn't supported at this point. GEM's been in the kernel for a year, and the fake bufmgr never really worked. --- src/mesa/drivers/dri/intel/intel_span.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) (limited to 'src/mesa/drivers/dri/intel/intel_span.c') diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index 3607c7dded..2c89a66a95 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -613,15 +613,7 @@ intel_set_span_functions(struct intel_context *intel, struct gl_renderbuffer *rb) { struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb; - uint32_t tiling; - - /* If in GEM mode, we need to do the tile address swizzling ourselves, - * instead of the fence registers handling it. - */ - if (intel->ttm) - tiling = irb->region->tiling; - else - tiling = I915_TILING_NONE; + uint32_t tiling = irb->region->tiling; if (intel->intelScreen->kernel_exec_fencing) { switch (irb->texformat) { @@ -673,6 +665,9 @@ intel_set_span_functions(struct intel_context *intel, return; } + /* If in GEM mode, we need to do the tile address swizzling ourselves, + * instead of the fence registers handling it. + */ switch (irb->texformat) { case MESA_FORMAT_RGB565: switch (tiling) { -- cgit v1.2.3