From a183efc132c8db1bb42525ac177ffff96f69a59b Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Mon, 17 Dec 2007 22:43:48 -0800 Subject: [Intel] Centralize mipmap pitch computations. mipmap pitches must account for the device alignment requirements, which used to be fairly simple; just align to a 4-byte boundary. However, to allow textures to be drawn to under TTM, they now need to be aligned to a 64-byte boundary. Placing all of the alignment constraints in a single function allows this new constraint to be applied uniformly. There was some pitch constraining code in intel_miptree_create, but that was modifying the pitch long after the miptree had been layed out, so it only served to wreck the mipmap and cause rendering errors. --- src/mesa/drivers/dri/intel/intel_tex_layout.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/intel/intel_tex_layout.h') diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.h b/src/mesa/drivers/dri/intel/intel_tex_layout.h index 99d41c3629..193699d3f7 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_layout.h +++ b/src/mesa/drivers/dri/intel/intel_tex_layout.h @@ -38,5 +38,5 @@ static GLuint minify( GLuint d ) return MAX2(1, d>>1); } -extern void i945_miptree_layout_2d( struct intel_mipmap_tree *mt ); +extern void i945_miptree_layout_2d( struct intel_context *intel, struct intel_mipmap_tree *mt ); extern GLuint intel_compressed_alignment(GLenum); -- cgit v1.2.3