From bcc2a3d7e3c5f81bb5a45b8d628a133f3b5499a5 Mon Sep 17 00:00:00 2001 From: "Xiang, Haihao" Date: Tue, 1 Jul 2008 11:38:07 +0800 Subject: dri: Take the base image size into account when computing first level of the mipmap. fix #16210 --- src/mesa/drivers/dri/intel/intel_tex_validate.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mesa/drivers/dri/intel') diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c b/src/mesa/drivers/dri/intel/intel_tex_validate.c index d260a721d9..992c75c519 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_validate.c +++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c @@ -43,6 +43,7 @@ intel_calculate_first_last_level(struct intel_texture_object *intelObj) #ifdef I915 firstLevel = tObj->BaseLevel + (GLint) (tObj->MinLod + 0.5); firstLevel = MAX2(firstLevel, tObj->BaseLevel); + firstLevel = MIN2(firstLevel, tObj->BaseLevel + baseImage->MaxLog2); lastLevel = tObj->BaseLevel + (GLint) (tObj->MaxLod + 0.5); lastLevel = MAX2(lastLevel, tObj->BaseLevel); lastLevel = MIN2(lastLevel, tObj->BaseLevel + baseImage->MaxLog2); -- cgit v1.2.3 From 92c075eeb7c330ea420400d1c2bae57356b19f03 Mon Sep 17 00:00:00 2001 From: "Xiang, Haihao" Date: Tue, 8 Jul 2008 14:14:04 +0800 Subject: i965: official name for GM45 chipset --- src/mesa/drivers/dri/i965/brw_clip_line.c | 2 +- src/mesa/drivers/dri/i965/brw_clip_state.c | 2 +- src/mesa/drivers/dri/i965/brw_clip_tri.c | 2 +- src/mesa/drivers/dri/i965/brw_defines.h | 13 +++++++------ src/mesa/drivers/dri/i965/brw_eu_emit.c | 16 ++++++++-------- src/mesa/drivers/dri/i965/brw_misc_state.c | 8 ++++---- src/mesa/drivers/dri/i965/brw_structs.h | 4 ++-- src/mesa/drivers/dri/i965/brw_vs_emit.c | 2 +- src/mesa/drivers/dri/intel/intel_chipset.h | 10 +++++----- src/mesa/drivers/dri/intel/intel_context.c | 4 +++- 10 files changed, 33 insertions(+), 30 deletions(-) (limited to 'src/mesa/drivers/dri/intel') diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c b/src/mesa/drivers/dri/i965/brw_clip_line.c index 7d51cddfc3..0930e6a573 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_line.c +++ b/src/mesa/drivers/dri/i965/brw_clip_line.c @@ -148,7 +148,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c ) brw_clip_init_clipmask(c); /* -ve rhw workaround */ - if (!BRW_IS_IGD(p->brw)) { + if (!(BRW_IS_GM45(p->brw) || BRW_IS_G4X(p->brw))) { brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<20)); diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c index 7cb21f894e..2d0b24c5ca 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_state.c +++ b/src/mesa/drivers/dri/i965/brw_clip_state.c @@ -102,7 +102,7 @@ clip_unit_create_from_key(struct brw_context *brw, clip.clip5.api_mode = BRW_CLIP_API_OGL; clip.clip5.clip_mode = key->clip_mode; - if (BRW_IS_IGD(brw)) + if (BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) clip.clip5.negative_w_clip_test = 1; clip.clip6.clipper_viewport_state_ptr = 0; diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c b/src/mesa/drivers/dri/i965/brw_clip_tri.c index f1fc6e1e9d..7c703179fe 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_tri.c +++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c @@ -536,7 +536,7 @@ void brw_emit_tri_clip( struct brw_clip_compile *c ) /* if -ve rhw workaround bit is set, do cliptest */ - if (!BRW_IS_IGD(p->brw)) { + if (!(BRW_IS_GM45(p->brw) || BRW_IS_G4X(p->brw))) { brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<20)); diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 3aada8cab1..92c058ade8 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -804,7 +804,7 @@ #define CMD_STATE_BASE_ADDRESS 0x6101 #define CMD_STATE_INSN_POINTER 0x6102 #define CMD_PIPELINE_SELECT_965 0x6104 -#define CMD_PIPELINE_SELECT_IGD 0x6904 +#define CMD_PIPELINE_SELECT_GM45 0x6904 #define CMD_PIPELINED_STATE_POINTERS 0x7800 #define CMD_BINDING_TABLE_PTRS 0x7801 @@ -836,7 +836,7 @@ #define CMD_INDEX_BUFFER 0x780a #define CMD_VF_STATISTICS_965 0x780b -#define CMD_VF_STATISTICS_IGD 0x680b +#define CMD_VF_STATISTICS_GM45 0x680b #define CMD_DRAW_RECT 0x7900 #define CMD_BLEND_CONSTANT_COLOR 0x7901 @@ -862,9 +862,10 @@ #include "intel_chipset.h" -#define BRW_IS_IGD(brw) (IS_IGD((brw)->intel.intelScreen->deviceID)) -#define CMD_PIPELINE_SELECT(brw) ((BRW_IS_IGD(brw)) ? CMD_PIPELINE_SELECT_IGD : CMD_PIPELINE_SELECT_965) -#define CMD_VF_STATISTICS(brw) ((BRW_IS_IGD(brw)) ? CMD_VF_STATISTICS_IGD : CMD_VF_STATISTICS_965) -#define URB_SIZES(brw) ((BRW_IS_IGD(brw)) ? 384 : 256) /* 512 bit unit */ +#define BRW_IS_GM45(brw) (IS_GM45_GM((brw)->intel.intelScreen->deviceID)) +#define BRW_IS_G4X(brw) (IS_G4X((brw)->intel.intelScreen->deviceID)) +#define CMD_PIPELINE_SELECT(brw) ((BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) ? CMD_PIPELINE_SELECT_GM45 : CMD_PIPELINE_SELECT_965) +#define CMD_VF_STATISTICS(brw) ((BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) ? CMD_VF_STATISTICS_GM45 : CMD_VF_STATISTICS_965) +#define URB_SIZES(brw) ((BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) ? 384 : 256) /* 512 bit unit */ #endif diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index fefd30bc7f..6b97f8b170 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -329,14 +329,14 @@ static void brw_set_sampler_message(struct brw_context *brw, { brw_set_src1(insn, brw_imm_d(0)); - if (BRW_IS_IGD(brw)) { - insn->bits3.sampler_igd.binding_table_index = binding_table_index; - insn->bits3.sampler_igd.sampler = sampler; - insn->bits3.sampler_igd.msg_type = msg_type; - insn->bits3.sampler_igd.response_length = response_length; - insn->bits3.sampler_igd.msg_length = msg_length; - insn->bits3.sampler_igd.end_of_thread = eot; - insn->bits3.sampler_igd.msg_target = BRW_MESSAGE_TARGET_SAMPLER; + if (BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) { + insn->bits3.sampler_gm45_g4x.binding_table_index = binding_table_index; + insn->bits3.sampler_gm45_g4x.sampler = sampler; + insn->bits3.sampler_gm45_g4x.msg_type = msg_type; + insn->bits3.sampler_gm45_g4x.response_length = response_length; + insn->bits3.sampler_gm45_g4x.msg_length = msg_length; + insn->bits3.sampler_gm45_g4x.end_of_thread = eot; + insn->bits3.sampler_gm45_g4x.msg_target = BRW_MESSAGE_TARGET_SAMPLER; } else { insn->bits3.sampler.binding_table_index = binding_table_index; insn->bits3.sampler.sampler = sampler; diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 26ec797b5f..62df2590f3 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -192,7 +192,7 @@ static void emit_depthbuffer(struct brw_context *brw) { struct intel_context *intel = &brw->intel; struct intel_region *region = brw->state.depth_region; - unsigned int len = BRW_IS_IGD(brw) ? sizeof(struct brw_depthbuffer_igd) / 4 : sizeof(struct brw_depthbuffer) / 4; + unsigned int len = (BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) ? sizeof(struct brw_depthbuffer_gm45_g4x) / 4 : sizeof(struct brw_depthbuffer) / 4; if (region == NULL) { BEGIN_BATCH(len, IGNORE_CLIPRECTS); @@ -203,7 +203,7 @@ static void emit_depthbuffer(struct brw_context *brw) OUT_BATCH(0); OUT_BATCH(0); - if (BRW_IS_IGD(brw)) + if (BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) OUT_BATCH(0); ADVANCE_BATCH(); @@ -239,7 +239,7 @@ static void emit_depthbuffer(struct brw_context *brw) ((region->height - 1) << 19)); OUT_BATCH(0); - if (BRW_IS_IGD(brw)) + if (BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) OUT_BATCH(0); ADVANCE_BATCH(); @@ -324,7 +324,7 @@ static void upload_aa_line_parameters(struct brw_context *brw) { struct brw_aa_line_parameters balp; - if (!BRW_IS_IGD(brw)) + if (!(BRW_IS_GM45(brw) || BRW_IS_G4X(brw))) return; /* use legacy aa line coverage computation */ diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h index 1326280e00..ec865c925a 100644 --- a/src/mesa/drivers/dri/i965/brw_structs.h +++ b/src/mesa/drivers/dri/i965/brw_structs.h @@ -175,7 +175,7 @@ struct brw_depthbuffer } dword4; }; -struct brw_depthbuffer_igd +struct brw_depthbuffer_gm45_g4x { union header_union header; @@ -1405,7 +1405,7 @@ struct brw_instruction GLuint msg_target:4; GLuint pad1:3; GLuint end_of_thread:1; - } sampler_igd; + } sampler_gm45_g4x; struct brw_urb_immediate urb; diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 3cac97c71f..7767d1369c 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -867,7 +867,7 @@ static void emit_vertex_write( struct brw_vs_compile *c) * Later, clipping will detect ucp[6] and ensure the primitive is * clipped against all fixed planes. */ - if (!BRW_IS_IGD(p->brw) && !c->key.know_w_is_one) { + if (!(BRW_IS_GM45(p->brw) || BRW_IS_G4X(p->brw)) && !c->key.know_w_is_one) { brw_CMP(p, vec8(brw_null_reg()), BRW_CONDITIONAL_L, diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index 4a5166263a..15b9ef4312 100644 --- a/src/mesa/drivers/dri/intel/intel_chipset.h +++ b/src/mesa/drivers/dri/intel/intel_chipset.h @@ -53,7 +53,7 @@ #define PCI_CHIP_I965_GM 0x2A02 #define PCI_CHIP_I965_GME 0x2A12 -#define PCI_CHIP_IGD_GM 0x2A42 +#define PCI_CHIP_GM45_GM 0x2A42 #define PCI_CHIP_IGD_E_G 0x2E02 #define PCI_CHIP_Q45_G 0x2E12 @@ -65,13 +65,12 @@ devid == PCI_CHIP_I945_GME || \ devid == PCI_CHIP_I965_GM || \ devid == PCI_CHIP_I965_GME || \ - devid == PCI_CHIP_IGD_GM) + devid == PCI_CHIP_GM45_GM) -#define IS_IGD_GM(devid) (devid == PCI_CHIP_IGD_GM) +#define IS_GM45_GM(devid) (devid == PCI_CHIP_GM45_GM) #define IS_G4X(devid) (devid == PCI_CHIP_IGD_E_G || \ devid == PCI_CHIP_Q45_G || \ devid == PCI_CHIP_G45_G) -#define IS_IGD(devid) (IS_IGD_GM(devid) || IS_G4X(devid)) #define IS_915(devid) (devid == PCI_CHIP_I915_G || \ devid == PCI_CHIP_E7221_G || \ @@ -90,7 +89,8 @@ devid == PCI_CHIP_I965_GM || \ devid == PCI_CHIP_I965_GME || \ devid == PCI_CHIP_I946_GZ || \ - IS_IGD(devid)) + IS_GM45_GM(devid) || \ + IS_G4X(devid)) #define IS_9XX(devid) (IS_915(devid) || \ IS_945(devid) || \ diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index 671b3f68a3..f8ea6461c9 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -166,7 +166,9 @@ intelGetString(GLcontext * ctx, GLenum name) case PCI_CHIP_I965_GME: chipset = "Intel(R) 965GME/GLE"; break; - case PCI_CHIP_IGD_GM: + case PCI_CHIP_GM45_GM: + chipset = "Mobile Intel® GM45 Express Chipset"; + break; case PCI_CHIP_IGD_E_G: chipset = "Intel(R) Integrated Graphics Device"; break; -- cgit v1.2.3 From b52398571b7f5c537c2f5e1c87f1b8bdf3d8ea9b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 11 Jul 2008 07:28:55 +1000 Subject: intel: fix batch flushing problem with cliprects handling. pointed out and debugged by stringfellow on #dri-devel --- src/mesa/drivers/dri/intel/intel_batchbuffer.h | 4 +++- src/mesa/drivers/dri/intel/intel_blit.c | 5 ++++- 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/intel') diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h b/src/mesa/drivers/dri/intel/intel_batchbuffer.h index 2d636df2ce..0da602010e 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.h +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.h @@ -118,8 +118,10 @@ intel_batchbuffer_require_space(struct intel_batchbuffer *batch, if (batch->cliprect_mode == IGNORE_CLIPRECTS) { batch->cliprect_mode = cliprect_mode; } else { - if (batch->cliprect_mode != cliprect_mode) + if (batch->cliprect_mode != cliprect_mode) { intel_batchbuffer_flush(batch); + batch->cliprect_mode = cliprect_mode; + } } } } diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index d9dbbb2482..25ac609f13 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -123,7 +123,8 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv, dst_pitch /= 4; } #endif - + /* do space/cliprects check before going any further */ + intel_batchbuffer_require_space(intel->batch, 8 * 4, REFERENCES_CLIPRECTS); again: ret = dri_bufmgr_check_aperture_space(dst->buffer); ret |= dri_bufmgr_check_aperture_space(src->buffer); @@ -278,6 +279,8 @@ intelEmitCopyBlit(struct intel_context *intel, int ret; BATCH_LOCALS; + /* do space/cliprects check before going any further */ + intel_batchbuffer_require_space(intel->batch, 8 * 4, NO_LOOP_CLIPRECTS); again: ret = dri_bufmgr_check_aperture_space(dst_buffer); ret |= dri_bufmgr_check_aperture_space(src_buffer); -- cgit v1.2.3 From 29cb89d0c2cb17e2fa38563fc93794a6ebd75cf9 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Wed, 16 Jul 2008 10:37:49 -0700 Subject: intel: Clean-up ARB_texture_env_crossbar Enable support for ARB_texture_env_crossbar in the master extension list instead of in every single device-specific list. --- src/mesa/drivers/dri/i915/i830_context.c | 8 -------- src/mesa/drivers/dri/i915/i915_context.c | 1 - src/mesa/drivers/dri/intel/intel_context.c | 7 +++---- 3 files changed, 3 insertions(+), 13 deletions(-) (limited to 'src/mesa/drivers/dri/intel') diff --git a/src/mesa/drivers/dri/i915/i830_context.c b/src/mesa/drivers/dri/i915/i830_context.c index acb7178a5c..16c8a8d24f 100644 --- a/src/mesa/drivers/dri/i915/i830_context.c +++ b/src/mesa/drivers/dri/i915/i830_context.c @@ -42,12 +42,6 @@ * Mesa's Driver Functions ***************************************/ -static const struct dri_extension i830_extensions[] = { - {"GL_ARB_texture_env_crossbar", NULL}, - {NULL, NULL} -}; - - static void i830InitDriverFunctions(struct dd_function_table *functions) { @@ -105,8 +99,6 @@ i830CreateContext(const __GLcontextModes * mesaVis, intel->verts = TNL_CONTEXT(ctx)->clipspace.vertex_buf; - driInitExtensions(ctx, i830_extensions, GL_FALSE); - i830InitState(i830); i830InitMetaFuncs(i830); diff --git a/src/mesa/drivers/dri/i915/i915_context.c b/src/mesa/drivers/dri/i915/i915_context.c index 532b402db7..bd9f1d5f5d 100644 --- a/src/mesa/drivers/dri/i915/i915_context.c +++ b/src/mesa/drivers/dri/i915/i915_context.c @@ -54,7 +54,6 @@ static const struct dri_extension i915_extensions[] = { {"GL_ARB_depth_texture", NULL}, {"GL_ARB_fragment_program", NULL}, {"GL_ARB_shadow", NULL}, - {"GL_ARB_texture_env_crossbar", NULL}, {"GL_ARB_texture_non_power_of_two", NULL}, {"GL_EXT_shadow_funcs", NULL}, /* ARB extn won't work if not enabled */ diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index f8ea6461c9..f9f0c7444e 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -194,9 +194,8 @@ intelGetString(GLcontext * ctx, GLenum name) /** * Extension strings exported by the intel driver. * - * \note - * It appears that ARB_texture_env_crossbar has "disappeared" compared to the - * old i830-specific driver. + * Extensions supported by all chips supported by i830_dri, i915_dri, or + * i965_dri. */ static const struct dri_extension card_extensions[] = { {"GL_ARB_multisample", GL_ARB_multisample_functions}, @@ -208,6 +207,7 @@ static const struct dri_extension card_extensions[] = { {"GL_ARB_texture_cube_map", NULL}, {"GL_ARB_texture_env_add", NULL}, {"GL_ARB_texture_env_combine", NULL}, + {"GL_ARB_texture_env_crossbar", NULL}, {"GL_ARB_texture_env_dot3", NULL}, {"GL_ARB_texture_mirrored_repeat", NULL}, {"GL_ARB_texture_non_power_of_two", NULL }, @@ -264,7 +264,6 @@ static const struct dri_extension brw_extensions[] = { { "GL_EXT_shadow_funcs", NULL }, /* ARB extn won't work if not enabled */ { "GL_SGIX_depth_texture", NULL }, - { "GL_ARB_texture_env_crossbar", NULL }, { "GL_EXT_texture_sRGB", NULL}, { NULL, NULL } }; -- cgit v1.2.3 From b4b7326717d3253656f9702fc04f06f8d210a6aa Mon Sep 17 00:00:00 2001 From: "Xiang, Haihao" Date: Fri, 18 Jul 2008 17:40:11 +0800 Subject: intel: fix texture border issue. (bug #16697) --- src/mesa/drivers/dri/i965/brw_fallback.c | 5 ++++- src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 5 ++++- src/mesa/drivers/dri/intel/intel_tex_image.c | 5 ++++- src/mesa/drivers/dri/intel/intel_tex_validate.c | 5 ++++- 4 files changed, 16 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri/intel') diff --git a/src/mesa/drivers/dri/i965/brw_fallback.c b/src/mesa/drivers/dri/i965/brw_fallback.c index b5cf821a93..8a8fb50cb9 100644 --- a/src/mesa/drivers/dri/i965/brw_fallback.c +++ b/src/mesa/drivers/dri/i965/brw_fallback.c @@ -73,7 +73,10 @@ static GLboolean do_check_fallback(struct brw_context *brw) if (texUnit->_ReallyEnabled) { struct intel_texture_object *intelObj = intel_texture_object(texUnit->_Current); struct gl_texture_image *texImage = intelObj->base.Image[0][intelObj->firstLevel]; - if (texImage->Border) { + if (texImage->Border || + ((texImage->_BaseFormat == GL_DEPTH_COMPONENT) && + ((texImage->TexObject->WrapS == GL_CLAMP_TO_BORDER) || + (texImage->TexObject->WrapT == GL_CLAMP_TO_BORDER)))) { DBG("FALLBACK: texture border\n"); return GL_TRUE; } diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index 9205627813..1b645c7262 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -265,7 +265,10 @@ intel_miptree_match_image(struct intel_mipmap_tree *mt, { /* Images with borders are never pulled into mipmap trees. */ - if (image->Border) + if (image->Border || + ((image->_BaseFormat == GL_DEPTH_COMPONENT) && + ((image->TexObject->WrapS == GL_CLAMP_TO_BORDER) || + (image->TexObject->WrapT == GL_CLAMP_TO_BORDER)))) return GL_FALSE; if (image->InternalFormat != mt->internal_format || diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c index 95ddbd5920..f261034c18 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_image.c +++ b/src/mesa/drivers/dri/intel/intel_tex_image.c @@ -75,7 +75,10 @@ guess_and_alloc_mipmap_tree(struct intel_context *intel, DBG("%s\n", __FUNCTION__); - if (intelImage->base.Border) + if (intelImage->base.Border || + ((intelImage->base._BaseFormat == GL_DEPTH_COMPONENT) && + ((intelObj->base.WrapS == GL_CLAMP_TO_BORDER) || + (intelObj->base.WrapT == GL_CLAMP_TO_BORDER)))) return; if (intelImage->level > intelObj->base.BaseLevel && diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c b/src/mesa/drivers/dri/intel/intel_tex_validate.c index 992c75c519..f56c236e61 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_validate.c +++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c @@ -144,7 +144,10 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit) /* Fallback case: */ - if (firstImage->base.Border) { + if (firstImage->base.Border || + ((firstImage->base._BaseFormat == GL_DEPTH_COMPONENT) && + ((tObj->WrapS == GL_CLAMP_TO_BORDER) || + (tObj->WrapT == GL_CLAMP_TO_BORDER)))) { if (intelObj->mt) { intel_miptree_release(intel, &intelObj->mt); } -- cgit v1.2.3 From 97988ccc46c0248177cd71937021ca8cc2a7452b Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Tue, 22 Jul 2008 09:39:23 -0700 Subject: intel: fix buffer swaps and enable page flipping on 965 Some buffer swap intel render buffer fields (pf_num_pages & vbl_pending) are also used for page flipping, so enable the code that sets & updates them on 965. This allows buffer swaps and page flips to work on 965 and prevents hangs in LOCK_HARDWARE in the buffer swap case due to an uninitialized vbl_pending field. Fixes FDO #16118. --- src/mesa/drivers/dri/intel/intel_buffers.c | 54 +++++++++--------------------- 1 file changed, 15 insertions(+), 39 deletions(-) (limited to 'src/mesa/drivers/dri/intel') diff --git a/src/mesa/drivers/dri/intel/intel_buffers.c b/src/mesa/drivers/dri/intel/intel_buffers.c index 2a25f079e9..348c490af0 100644 --- a/src/mesa/drivers/dri/intel/intel_buffers.c +++ b/src/mesa/drivers/dri/intel/intel_buffers.c @@ -197,7 +197,6 @@ intelSetBackClipRects(struct intel_context *intel) } } -#ifdef I915 static void intelUpdatePageFlipping(struct intel_context *intel, GLint areaA, GLint areaB) @@ -267,7 +266,6 @@ intelUpdatePageFlipping(struct intel_context *intel, intel_flip_renderbuffers(intel_fb); intel_draw_buffer(&intel->ctx, intel->ctx.DrawBuffer); } -#endif /* I915 */ /** * This will be called whenever the currently bound window is moved/resized. @@ -318,9 +316,7 @@ intelWindowMoved(struct intel_context *intel) GLint areaB = driIntersectArea( drw_rect, planeB_rect ); GLuint flags = dPriv->vblFlags; -#ifdef I915 intelUpdatePageFlipping(intel, areaA, areaB); -#endif /* Update vblank info */ @@ -645,7 +641,6 @@ intel_wait_flips(struct intel_context *intel) static GLboolean intelPageFlip(const __DRIdrawablePrivate * dPriv) { -#ifdef I915 struct intel_context *intel; int ret; struct intel_framebuffer *intel_fb = dPriv->driverPrivate; @@ -698,40 +693,8 @@ intelPageFlip(const __DRIdrawablePrivate * dPriv) intel_draw_buffer(&intel->ctx, &intel_fb->Base); return GL_TRUE; -#else - return GL_FALSE; -#endif } -#if 0 -void -intelSwapBuffers(__DRIdrawablePrivate * dPriv) -{ - if (dPriv->driverPrivate) { - const struct gl_framebuffer *fb - = (struct gl_framebuffer *) dPriv->driverPrivate; - if (fb->Visual.doubleBufferMode) { - GET_CURRENT_CONTEXT(ctx); - if (ctx && ctx->DrawBuffer == fb) { - _mesa_notifySwapBuffers(ctx); /* flush pending rendering */ - } - if (intel->doPageFlip) { - intelPageFlip(dPriv); - } - else { - intelCopyBuffer(dPriv); - } - } - } - else { - _mesa_problem(NULL, - "dPriv has no gl_framebuffer pointer in intelSwapBuffers"); - } -} -#else -/* Trunk version: - */ - static GLboolean intelScheduleSwap(__DRIdrawablePrivate * dPriv, GLboolean *missed_target) { @@ -746,8 +709,10 @@ intelScheduleSwap(__DRIdrawablePrivate * dPriv, GLboolean *missed_target) if (!dPriv->vblFlags || (dPriv->vblFlags & VBLANK_FLAG_NO_IRQ) || - intelScreen->drmMinor < (intel_fb->pf_active ? 9 : 6)) + intelScreen->drmMinor < (intel_fb->pf_active ? 9 : 6)) { + printf("swap schedule failed: bad flags or drm minor\n"); return GL_FALSE; + } interval = driGetVBlankInterval(dPriv); @@ -756,6 +721,7 @@ intelScheduleSwap(__DRIdrawablePrivate * dPriv, GLboolean *missed_target) if (dPriv->vblFlags & VBLANK_FLAG_SYNC) { swap.seqtype |= DRM_VBLANK_NEXTONMISS; } else if (interval == 0) { + printf("swap schedule failed: bad interval\n"); return GL_FALSE; } @@ -803,6 +769,7 @@ intelScheduleSwap(__DRIdrawablePrivate * dPriv, GLboolean *missed_target) } ret = GL_FALSE; + printf("swap schedule failed: vblank swap failed\n"); } UNLOCK_HARDWARE(intel); @@ -832,8 +799,18 @@ intelSwapBuffers(__DRIdrawablePrivate * dPriv) _mesa_notifySwapBuffers(ctx); /* flush pending rendering comands */ if (!intelScheduleSwap(dPriv, &missed_target)) { + printf("schedule swap failed, trying to wait manually\n"); driWaitForVBlank(dPriv, &missed_target); + /* + * Update each buffer's vbl_pending so we don't get too out of + * sync + */ + intel_get_renderbuffer(&intel_fb->Base, + BUFFER_BACK_LEFT)->vbl_pending = + intel_get_renderbuffer(&intel_fb->Base, + BUFFER_FRONT_LEFT)->vbl_pending = + dPriv->vblSeq; if (!intelPageFlip(dPriv)) { intelCopyBuffer(dPriv, NULL); } @@ -854,7 +831,6 @@ intelSwapBuffers(__DRIdrawablePrivate * dPriv) fprintf(stderr, "%s: drawable has no context!\n", __FUNCTION__); } } -#endif void intelCopySubBuffer(__DRIdrawablePrivate * dPriv, int x, int y, int w, int h) -- cgit v1.2.3 From 9a4be9785f932bedf727fbf88244ac1b158b09a5 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Thu, 24 Jul 2008 09:11:37 -0700 Subject: intel: remove buffer swap debug output Accidentally pushed as part of the last commit. --- src/mesa/drivers/dri/intel/intel_buffers.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) (limited to 'src/mesa/drivers/dri/intel') diff --git a/src/mesa/drivers/dri/intel/intel_buffers.c b/src/mesa/drivers/dri/intel/intel_buffers.c index 348c490af0..75542a9775 100644 --- a/src/mesa/drivers/dri/intel/intel_buffers.c +++ b/src/mesa/drivers/dri/intel/intel_buffers.c @@ -709,10 +709,8 @@ intelScheduleSwap(__DRIdrawablePrivate * dPriv, GLboolean *missed_target) if (!dPriv->vblFlags || (dPriv->vblFlags & VBLANK_FLAG_NO_IRQ) || - intelScreen->drmMinor < (intel_fb->pf_active ? 9 : 6)) { - printf("swap schedule failed: bad flags or drm minor\n"); + intelScreen->drmMinor < (intel_fb->pf_active ? 9 : 6)) return GL_FALSE; - } interval = driGetVBlankInterval(dPriv); @@ -720,10 +718,8 @@ intelScheduleSwap(__DRIdrawablePrivate * dPriv, GLboolean *missed_target) if (dPriv->vblFlags & VBLANK_FLAG_SYNC) { swap.seqtype |= DRM_VBLANK_NEXTONMISS; - } else if (interval == 0) { - printf("swap schedule failed: bad interval\n"); + } else if (interval == 0) return GL_FALSE; - } swap.drawable = dPriv->hHWDrawable; target = swap.sequence = dPriv->vblSeq + interval; @@ -769,7 +765,6 @@ intelScheduleSwap(__DRIdrawablePrivate * dPriv, GLboolean *missed_target) } ret = GL_FALSE; - printf("swap schedule failed: vblank swap failed\n"); } UNLOCK_HARDWARE(intel); @@ -799,7 +794,6 @@ intelSwapBuffers(__DRIdrawablePrivate * dPriv) _mesa_notifySwapBuffers(ctx); /* flush pending rendering comands */ if (!intelScheduleSwap(dPriv, &missed_target)) { - printf("schedule swap failed, trying to wait manually\n"); driWaitForVBlank(dPriv, &missed_target); /* -- cgit v1.2.3 From 94979950e8991bd44899eb4067c3ae43449ce51e Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 25 Jul 2008 16:31:38 +1000 Subject: intel: disable zero-copy TFP. patch from Fedora. maybe someone can fix this later but for now lets try and release Mesa so ajax can live his life and get Xorg 7.4 out. --- src/mesa/drivers/dri/intel/intel_screen.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mesa/drivers/dri/intel') diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index 5233e58fc9..467d022f44 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -391,10 +391,12 @@ intelHandleBufferAttach(__DRIdrawablePrivate *dPriv, intel_renderbuffer_set_region(rb, region); } +#if 0 static const __DRItexOffsetExtension intelTexOffsetExtension = { { __DRI_TEX_OFFSET }, intelSetTexOffset, }; +#endif static const __DRItexBufferExtension intelTexBufferExtension = { { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, @@ -407,7 +409,9 @@ static const __DRIextension *intelScreenExtensions[] = { &driSwapControlExtension.base, &driFrameTrackingExtension.base, &driMediaStreamCounterExtension.base, +#if 0 &intelTexOffsetExtension.base, +#endif &intelTexBufferExtension.base, NULL }; -- cgit v1.2.3 From 04c98089d15d27e541561d3fb35b9c28b699833b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 25 Jul 2008 19:57:35 +1000 Subject: Revert "intel: disable zero-copy TFP." This reverts commit 94979950e8991bd44899eb4067c3ae43449ce51e. I've fixed it instead --- src/mesa/drivers/dri/intel/intel_screen.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/mesa/drivers/dri/intel') diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index 467d022f44..5233e58fc9 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -391,12 +391,10 @@ intelHandleBufferAttach(__DRIdrawablePrivate *dPriv, intel_renderbuffer_set_region(rb, region); } -#if 0 static const __DRItexOffsetExtension intelTexOffsetExtension = { { __DRI_TEX_OFFSET }, intelSetTexOffset, }; -#endif static const __DRItexBufferExtension intelTexBufferExtension = { { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, @@ -409,9 +407,7 @@ static const __DRIextension *intelScreenExtensions[] = { &driSwapControlExtension.base, &driFrameTrackingExtension.base, &driMediaStreamCounterExtension.base, -#if 0 &intelTexOffsetExtension.base, -#endif &intelTexBufferExtension.base, NULL }; -- cgit v1.2.3