From 8e444fb9e2685e3eac42beb848b08e91dc20c88a Mon Sep 17 00:00:00 2001 From: "Xiang, Haihao" Date: Tue, 29 Jan 2008 11:13:53 +0800 Subject: i965: new integrated graphics chipset support --- src/mesa/drivers/dri/intel/intel_chipset.h | 10 ++++++++-- src/mesa/drivers/dri/intel/intel_decode.c | 9 ++++++--- 2 files changed, 14 insertions(+), 5 deletions(-) (limited to 'src/mesa/drivers/dri/intel') diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index 4fc4c96376..5f094dc5fb 100644 --- a/src/mesa/drivers/dri/intel/intel_chipset.h +++ b/src/mesa/drivers/dri/intel/intel_chipset.h @@ -52,19 +52,25 @@ #define PCI_CHIP_I965_GM 0x2A02 #define PCI_CHIP_I965_GME 0x2A12 +#define PCI_CHIP_IGD_GM 0x2A42 + #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \ devid == PCI_CHIP_I915_GM || \ devid == PCI_CHIP_I945_GM || \ devid == PCI_CHIP_I945_GME || \ devid == PCI_CHIP_I965_GM || \ - devid == PCI_CHIP_I965_GME) + devid == PCI_CHIP_I965_GME || \ + devid == PCI_CHIP_IGD_GM) + +#define IS_IGD(devid) (devid == PCI_CHIP_IGD_GM) #define IS_965(devid) (devid == PCI_CHIP_I965_G || \ devid == PCI_CHIP_I965_Q || \ devid == PCI_CHIP_I965_G_1 || \ devid == PCI_CHIP_I965_GM || \ devid == PCI_CHIP_I965_GME || \ - devid == PCI_CHIP_I946_GZ) + devid == PCI_CHIP_I946_GZ || \ + IS_IGD(devid)) #define IS_9XX(devid) (devid == PCI_CHIP_I915_G || \ devid == PCI_CHIP_I915_GM || \ diff --git a/src/mesa/drivers/dri/intel/intel_decode.c b/src/mesa/drivers/dri/intel/intel_decode.c index 73f0fcd591..a1240639f4 100644 --- a/src/mesa/drivers/dri/intel/intel_decode.c +++ b/src/mesa/drivers/dri/intel/intel_decode.c @@ -112,7 +112,7 @@ decode_mi(uint32_t *data, int count, uint32_t hw_offset, int *failures) for (opcode = 0; opcode < sizeof(opcodes_mi) / sizeof(opcodes_mi[0]); opcode++) { - if ((data[0] & 0x1e000000) >> 23 == opcodes_mi[opcode].opcode) { + if ((data[0] & 0x1f800000) >> 23 == opcodes_mi[opcode].opcode) { unsigned int len = 1, i; instr_out(data, hw_offset, 0, "%s\n", opcodes_mi[opcode].name); @@ -827,6 +827,8 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, int *failures) { 0x6101, 6, 6, "STATE_BASE_ADDRESS" }, { 0x6102, 2, 2 , "STATE_SIP" }, { 0x6104, 1, 1, "3DSTATE_PIPELINE_SELECT" }, + { 0x680b, 1, 1, "3DSTATE_VF_STATISTICS" }, + { 0x6904, 1, 1, "3DSTATE_PIPELINE_SELECT" }, { 0x7800, 7, 7, "3DSTATE_PIPELINED_POINTERS" }, { 0x7801, 6, 6, "3DSTATE_BINDING_TABLE_POINTERS" }, { 0x780b, 1, 1, "3DSTATE_VF_STATISTICS" }, @@ -836,11 +838,12 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, int *failures) /* 0x7809: 3DSTATE_VERTEX_ELEMENTS */ { 0x7900, 4, 4, "3DSTATE_DRAWING_RECTANGLE" }, { 0x7901, 5, 5, "3DSTATE_CONSTANT_COLOR" }, - { 0x7905, 5, 5, "3DSTATE_DEPTH_BUFFER" }, + { 0x7905, 5, 7, "3DSTATE_DEPTH_BUFFER" }, { 0x7906, 2, 2, "3DSTATE_POLY_STIPPLE_OFFSET" }, { 0x7907, 33, 33, "3DSTATE_POLY_STIPPLE_PATTERN" }, - { 0x7909, 2, 2, "3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP" }, { 0x7908, 3, 3, "3DSTATE_LINE_STIPPLE" }, + { 0x7909, 2, 2, "3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP" }, + { 0x790a, 3, 3, "3DSTATE_AA_LINE_PARAMETERS" }, { 0x7b00, 6, 6, "3DPRIMITIVE" }, }; -- cgit v1.2.3