From 4637235183b80963536f2364e4d50fcb894886dd Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 14 Jan 2009 10:44:48 +1000 Subject: radeon/r200/r300: initial attempt to convert to common context code --- src/mesa/drivers/dri/r200/r200_tcl.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'src/mesa/drivers/dri/r200/r200_tcl.c') diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 99aecfe1e9..d14564c29b 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -154,7 +154,7 @@ static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) } else { if (rmesa->dma.flush) - rmesa->dma.flush( rmesa ); + rmesa->dma.flush( rmesa->radeon.glCtx ); r200EnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + rmesa->hw.max_state_size + ELTS_BUFSZ(nr) ); @@ -394,7 +394,7 @@ static GLboolean r200_run_tcl_render( GLcontext *ctx, /* TODO: separate this from the swtnl pipeline */ - if (rmesa->TclFallback) + if (rmesa->radeon.TclFallback) return GL_TRUE; /* fallback to software t&l */ if (R200_DEBUG & DEBUG_PRIMS) @@ -405,7 +405,7 @@ static GLboolean r200_run_tcl_render( GLcontext *ctx, /* Validate state: */ - if (rmesa->NewGLState) + if (rmesa->radeon.NewGLState) r200ValidateState( ctx ); if (!ctx->VertexProgram._Enabled) { @@ -566,7 +566,7 @@ static void transition_to_hwtnl( GLcontext *ctx ) tnl->Driver.NotifyMaterialChange = r200UpdateMaterial; if ( rmesa->dma.flush ) - rmesa->dma.flush( rmesa ); + rmesa->dma.flush( rmesa->radeon.glCtx ); rmesa->dma.flush = NULL; @@ -631,10 +631,10 @@ static char *getFallbackString(GLuint bit) void r200TclFallback( GLcontext *ctx, GLuint bit, GLboolean mode ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint oldfallback = rmesa->TclFallback; + GLuint oldfallback = rmesa->radeon.TclFallback; if (mode) { - rmesa->TclFallback |= bit; + rmesa->radeon.TclFallback |= bit; if (oldfallback == 0) { if (R200_DEBUG & DEBUG_FALLBACKS) fprintf(stderr, "R200 begin tcl fallback %s\n", @@ -643,7 +643,7 @@ void r200TclFallback( GLcontext *ctx, GLuint bit, GLboolean mode ) } } else { - rmesa->TclFallback &= ~bit; + rmesa->radeon.TclFallback &= ~bit; if (oldfallback == bit) { if (R200_DEBUG & DEBUG_FALLBACKS) fprintf(stderr, "R200 end tcl fallback %s\n", -- cgit v1.2.3 From ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 20 Jan 2009 22:51:04 +1000 Subject: r200: clear is working at least - not much else --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 226 +++++++--- src/mesa/drivers/dri/r200/r200_context.c | 112 +---- src/mesa/drivers/dri/r200/r200_context.h | 8 +- src/mesa/drivers/dri/r200/r200_ioctl.c | 20 +- src/mesa/drivers/dri/r200/r200_ioctl.h | 59 ++- src/mesa/drivers/dri/r200/r200_maos_arrays.c | 34 +- src/mesa/drivers/dri/r200/r200_pixel.c | 8 +- src/mesa/drivers/dri/r200/r200_span.c | 46 +- src/mesa/drivers/dri/r200/r200_span.h | 3 +- src/mesa/drivers/dri/r200/r200_state.c | 33 +- src/mesa/drivers/dri/r200/r200_state_init.c | 146 ++++++ src/mesa/drivers/dri/r200/r200_swtcl.c | 70 ++- src/mesa/drivers/dri/r200/r200_tcl.c | 18 +- src/mesa/drivers/dri/r200/r200_texmem.c | 4 +- src/mesa/drivers/dri/r300/r300_context.c | 2 - src/mesa/drivers/dri/r300/r300_context.h | 10 +- src/mesa/drivers/dri/r300/r300_emit.c | 143 +----- src/mesa/drivers/dri/r300/r300_emit.h | 7 - src/mesa/drivers/dri/r300/r300_render.c | 6 +- src/mesa/drivers/dri/r300/r300_swtcl.c | 14 +- src/mesa/drivers/dri/r300/radeon_context.c | 496 --------------------- src/mesa/drivers/dri/radeon/common_cmdbuf.h | 4 + src/mesa/drivers/dri/radeon/common_context.h | 17 + src/mesa/drivers/dri/radeon/common_misc.c | 634 +++++++++++++++++++++++++++ src/mesa/drivers/dri/radeon/common_misc.h | 14 + src/mesa/drivers/dri/radeon/radeon_context.c | 56 +-- src/mesa/drivers/dri/radeon/radeon_screen.c | 122 +----- src/mesa/drivers/dri/radeon/radeon_span.c | 25 +- src/mesa/drivers/dri/radeon/radeon_span.h | 4 - src/mesa/drivers/dri/radeon/radeon_state.c | 4 +- 30 files changed, 1200 insertions(+), 1145 deletions(-) (limited to 'src/mesa/drivers/dri/r200/r200_tcl.c') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index 53c6ecf6ee..f107ff5624 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -38,7 +38,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast/swrast.h" #include "main/simple_list.h" +#include "radeon_cs.h" #include "r200_context.h" +#include "common_cmdbuf.h" #include "r200_state.h" #include "r200_ioctl.h" #include "r200_tcl.h" @@ -148,6 +150,40 @@ static void r200SaveHwState( r200ContextPtr rmesa ) fprintf(stderr, "Returning to r200EmitState\n"); } +static INLINE void r200EmitAtoms(r200ContextPtr r200, GLboolean dirty) +{ + BATCH_LOCALS(&r200->radeon); + struct radeon_state_atom *atom; + int dwords; + + /* Emit actual atoms */ + foreach(atom, &r200->hw.atomlist) { + if ((atom->dirty || r200->hw.all_dirty) == dirty) { + dwords = (*atom->check) (r200->radeon.glCtx, atom); + if (dwords) { + // if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { + // r300PrintStateAtom(r300, atom); + // } + if (atom->emit) { + (*atom->emit)(r200->radeon.glCtx, atom); + } else { + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_BATCH_TABLE(atom->cmd, dwords); + END_BATCH(); + } + atom->dirty = GL_FALSE; + } else { + // if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { + // fprintf(stderr, " skip state %s\n", + // atom->name); + // } + } + } + } + + COMMIT_BATCH(); +} + void r200EmitState( r200ContextPtr rmesa ) { char *dest; @@ -163,8 +199,8 @@ void r200EmitState( r200ContextPtr rmesa ) rmesa->save_on_next_emit = GL_FALSE; } - if (!rmesa->hw.is_dirty && !rmesa->hw.all_dirty) - return; + if (rmesa->radeon.cmdbuf.cs->cdw && !rmesa->hw.is_dirty && !rmesa->hw.all_dirty) + return; mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits; @@ -172,44 +208,19 @@ void r200EmitState( r200ContextPtr rmesa ) * for enough space for the case of emitting all state, and inline the * r200AllocCmdBuf code here without all the checks. */ - r200EnsureCmdBufSpace( rmesa, rmesa->hw.max_state_size ); - - /* we need to calculate dest after EnsureCmdBufSpace - as we may flush the buffer - airlied */ - dest = rmesa->store.cmd_buf + rmesa->store.cmd_used; - if (R200_DEBUG & DEBUG_STATE) { - foreach( atom, &rmesa->hw.atomlist ) { - if ( atom->dirty || rmesa->hw.all_dirty ) { - dwords = atom->check( rmesa->radeon.glCtx, atom ); - if ( dwords ) - print_state_atom( atom ); - else - fprintf(stderr, "skip state %s\n", atom->name); - } - } - } + rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->hw.max_state_size, __FUNCTION__); - foreach( atom, &rmesa->hw.atomlist ) { - if ( rmesa->hw.all_dirty ) - atom->dirty = GL_TRUE; - if ( atom->dirty ) { - dwords = atom->check( rmesa->radeon.glCtx, atom ); - if ( dwords ) { - int size = atom->cmd_size * 4; - if (atom->emit) { - (*atom->emit)(rmesa->radeon.glCtx, atom); - } else { - memcpy( dest, atom->cmd, size); - dest += size; - rmesa->store.cmd_used += size; - } - atom->dirty = GL_FALSE; - } - } + if (!rmesa->radeon.cmdbuf.cs->cdw) { + if (RADEON_DEBUG & DEBUG_STATE) + fprintf(stderr, "Begin reemit state\n"); + + r200EmitAtoms(rmesa, GL_FALSE); } - assert( rmesa->store.cmd_used <= R200_CMD_BUF_SZ ); + if (RADEON_DEBUG & DEBUG_STATE) + fprintf(stderr, "Begin dirty state\n"); + r200EmitAtoms(rmesa, GL_TRUE); rmesa->hw.is_dirty = GL_FALSE; rmesa->hw.all_dirty = GL_FALSE; } @@ -222,6 +233,7 @@ void r200EmitVbufPrim( r200ContextPtr rmesa, GLuint vertex_nr ) { drm_radeon_cmd_header_t *cmd; + BATCH_LOCALS(&rmesa->radeon); assert(!(primitive & R200_VF_PRIM_WALK_IND)); @@ -230,7 +242,13 @@ void r200EmitVbufPrim( r200ContextPtr rmesa, if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS)) fprintf(stderr, "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__, rmesa->store.cmd_used/4, primitive, vertex_nr); - + + BEGIN_BATCH(3); + OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_VBUF_2, 0); + OUT_BATCH(primitive | R200_VF_PRIM_WALK_LIST | R200_VF_COLOR_ORDER_RGBA | + (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT)); + END_BATCH(); +#if 0 cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, VBUF_BUFSZ, __FUNCTION__ ); cmd[0].i = 0; @@ -240,6 +258,7 @@ void r200EmitVbufPrim( r200ContextPtr rmesa, R200_VF_PRIM_WALK_LIST | R200_VF_COLOR_ORDER_RGBA | (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT)); +#endif } @@ -285,8 +304,8 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, r200EmitState( rmesa ); - cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, ELTS_BUFSZ(min_nr), - __FUNCTION__ ); + // cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, ELTS_BUFSZ(min_nr), + // __FUNCTION__ ); cmd[0].i = 0; cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP; cmd[1].i = R200_CP_CMD_3D_DRAW_INDX_2; @@ -314,26 +333,124 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, void r200EmitVertexAOS( r200ContextPtr rmesa, - GLuint vertex_size, - GLuint offset ) + GLuint vertex_size, + struct radeon_bo *bo, + GLuint offset ) { - drm_radeon_cmd_header_t *cmd; + BATCH_LOCALS(&rmesa->radeon); if (R200_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL)) fprintf(stderr, "%s: vertex_size 0x%x offset 0x%x \n", __FUNCTION__, vertex_size, offset); - cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, VERT_AOS_BUFSZ, - __FUNCTION__ ); - cmd[0].header.cmd_type = RADEON_CMD_PACKET3; - cmd[1].i = R200_CP_CMD_3D_LOAD_VBPNTR | (2 << 16); - cmd[2].i = 1; - cmd[3].i = vertex_size | (vertex_size << 8); - cmd[4].i = offset; + BEGIN_BATCH(5); + OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, 2); + OUT_BATCH(1); + OUT_BATCH(vertex_size | (vertex_size << 8)); + OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0); + END_BATCH(); } - +void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset) +{ + BATCH_LOCALS(&rmesa->radeon); + uint32_t voffset; + int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2; + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__, nr, + offset); + + BEGIN_BATCH(sz+2); + OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, sz - 1); + OUT_BATCH(nr); + + + if (!rmesa->radeon.radeonScreen->kernel_mm) { + for (i = 0; i + 1 < nr; i += 2) { + OUT_BATCH((rmesa->tcl.aos[i].components << 0) | + (rmesa->tcl.aos[i].stride << 8) | + (rmesa->tcl.aos[i + 1].components << 16) | + (rmesa->tcl.aos[i + 1].stride << 24)); + + voffset = rmesa->tcl.aos[i + 0].offset + + offset * 4 * rmesa->tcl.aos[i + 0].stride; + OUT_BATCH_RELOC(voffset, + rmesa->tcl.aos[i].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + voffset = rmesa->tcl.aos[i + 1].offset + + offset * 4 * rmesa->tcl.aos[i + 1].stride; + OUT_BATCH_RELOC(voffset, + rmesa->tcl.aos[i+1].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + + if (nr & 1) { + OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) | + (rmesa->tcl.aos[nr - 1].stride << 8)); + voffset = rmesa->tcl.aos[nr - 1].offset + + offset * 4 * rmesa->tcl.aos[nr - 1].stride; + OUT_BATCH_RELOC(voffset, + rmesa->tcl.aos[nr - 1].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + } else { + for (i = 0; i + 1 < nr; i += 2) { + OUT_BATCH((rmesa->tcl.aos[i].components << 0) | + (rmesa->tcl.aos[i].stride << 8) | + (rmesa->tcl.aos[i + 1].components << 16) | + (rmesa->tcl.aos[i + 1].stride << 24)); + + voffset = rmesa->tcl.aos[i + 0].offset + + offset * 4 * rmesa->tcl.aos[i + 0].stride; + OUT_BATCH(voffset); + voffset = rmesa->tcl.aos[i + 1].offset + + offset * 4 * rmesa->tcl.aos[i + 1].stride; + OUT_BATCH(voffset); + } + + if (nr & 1) { + OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) | + (rmesa->tcl.aos[nr - 1].stride << 8)); + voffset = rmesa->tcl.aos[nr - 1].offset + + offset * 4 * rmesa->tcl.aos[nr - 1].stride; + OUT_BATCH(voffset); + } + for (i = 0; i + 1 < nr; i += 2) { + voffset = rmesa->tcl.aos[i + 0].offset + + offset * 4 * rmesa->tcl.aos[i + 0].stride; + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->tcl.aos[i+0].bo, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + voffset = rmesa->tcl.aos[i + 1].offset + + offset * 4 * rmesa->tcl.aos[i + 1].stride; + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->tcl.aos[i+1].bo, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + if (nr & 1) { + voffset = rmesa->tcl.aos[nr - 1].offset + + offset * 4 * rmesa->tcl.aos[nr - 1].stride; + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->tcl.aos[nr-1].bo, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + } + END_BATCH(); +} + +#if 0 void r200EmitAOS( r200ContextPtr rmesa, struct radeon_dma_region **component, GLuint nr, @@ -377,6 +494,7 @@ void r200EmitAOS( r200ContextPtr rmesa, fprintf(stderr, " %d: %x\n", i, tmp[i]); } } +#endif void r200EmitBlit( r200ContextPtr rmesa, GLuint color_fmt, @@ -404,8 +522,8 @@ void r200EmitBlit( r200ContextPtr rmesa, assert( w < (1<<16) ); assert( h < (1<<16) ); - cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 8 * sizeof(int), - __FUNCTION__ ); + // cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 8 * sizeof(int), + // __FUNCTION__ ); cmd[0].header.cmd_type = RADEON_CMD_PACKET3; @@ -434,8 +552,8 @@ void r200EmitWait( r200ContextPtr rmesa, GLuint flags ) assert( !(flags & ~(RADEON_WAIT_2D|RADEON_WAIT_3D)) ); - cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 1 * sizeof(int), - __FUNCTION__ ); + // cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 1 * sizeof(int), + // __FUNCTION__ ); cmd[0].i = 0; cmd[0].wait.cmd_type = RADEON_CMD_WAIT; cmd[0].wait.flags = flags; diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 730831db04..acbfdb2db6 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -297,9 +297,9 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private); struct dd_function_table functions; r200ContextPtr rmesa; - GLcontext *ctx, *shareCtx; + GLcontext *ctx; int i; - int tcl_mode, fthrottle_mode; + int tcl_mode; assert(glVisual); assert(driContextPriv); @@ -344,31 +344,12 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, r200InitTextureFuncs(&functions); r200InitShaderFuncs(&functions); - /* Allocate and initialize the Mesa context */ - if (sharedContextPrivate) - shareCtx = ((r200ContextPtr) sharedContextPrivate)->radeon.glCtx; - else - shareCtx = NULL; - rmesa->radeon.glCtx = _mesa_create_context(glVisual, shareCtx, - &functions, (void *) rmesa); - if (!rmesa->radeon.glCtx) { - FREE(rmesa); - return GL_FALSE; + if (!radeonInitContext(&rmesa->radeon, &functions, + glVisual, driContextPriv, + sharedContextPrivate)) { + FREE(rmesa); + return GL_FALSE; } - driContextPriv->driverPrivate = rmesa; - - /* Init r200 context data */ - rmesa->radeon.dri.context = driContextPriv; - rmesa->radeon.dri.screen = sPriv; - rmesa->radeon.dri.drawable = NULL; /* Set by XMesaMakeCurrent */ - rmesa->radeon.dri.hwContext = driContextPriv->hHWContext; - rmesa->radeon.dri.hwLock = &sPriv->pSAREA->lock; - rmesa->radeon.dri.fd = sPriv->fd; - rmesa->radeon.dri.drmMinor = sPriv->drm_version.minor; - - rmesa->radeon.radeonScreen = screen; - rmesa->radeon.sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA + - screen->sarea_priv_offset); rmesa->dma.buf0_address = rmesa->radeon.radeonScreen->buffers->list[0].address; @@ -531,27 +512,9 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, r200InitState( rmesa ); r200InitSwtcl( ctx ); - fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode"); - rmesa->radeon.iw.irq_seq = -1; - rmesa->radeon.irqsEmitted = 0; - rmesa->radeon.do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS && - rmesa->radeon.radeonScreen->irq); - - rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); - - if (!rmesa->radeon.do_irqs) - fprintf(stderr, - "IRQ's not enabled, falling back to %s: %d %d\n", - rmesa->radeon.do_usleeps ? "usleeps" : "busy waits", - fthrottle_mode, - rmesa->radeon.radeonScreen->irq); - rmesa->prefer_gart_client_texturing = (getenv("R200_GART_CLIENT_TEXTURES") != 0); - (*sPriv->systemTime->getUST)( & rmesa->radeon.swap_ust ); - - #if DO_DEBUG R200_DEBUG = driParseDebugString( getenv( "R200_DEBUG" ), debug_control ); @@ -609,8 +572,8 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) r200ReleaseArrays( rmesa->radeon.glCtx, ~0 ); if (rmesa->dma.current.buf) { - r200ReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ ); - r200FlushCmdBuf( rmesa, __FUNCTION__ ); + // r200ReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ ); + rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); } if (rmesa->radeon.state.scissor.pClipRects) { @@ -618,6 +581,7 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) rmesa->radeon.state.scissor.pClipRects = NULL; } + if ( release_texture_heaps ) { /* This share group is about to go away, free our private * texture object data. @@ -632,67 +596,13 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) assert( is_empty_list( & rmesa->radeon.swapped ) ); } - /* free the Mesa context */ - rmesa->radeon.glCtx->DriverCtx = NULL; - _mesa_destroy_context( rmesa->radeon.glCtx ); - - /* free the option cache */ - driDestroyOptionCache (&rmesa->radeon.optionCache); + radeonCleanupContext(&rmesa->radeon); FREE( rmesa ); } } -/* Force the context `c' to be the current context and associate with it - * buffer `b'. - */ -GLboolean -r200MakeCurrent( __DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv ) -{ - if ( driContextPriv ) { - r200ContextPtr newCtx = - (r200ContextPtr) driContextPriv->driverPrivate; - - if (R200_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *)newCtx->radeon.glCtx); - - newCtx->radeon.dri.readable = driReadPriv; - - if ( newCtx->radeon.dri.drawable != driDrawPriv || - newCtx->radeon.lastStamp != driDrawPriv->lastStamp ) { - if (driDrawPriv->swap_interval == (unsigned)-1) { - driDrawPriv->vblFlags = (newCtx->radeon.radeonScreen->irq != 0) - ? driGetDefaultVBlankFlags(&newCtx->radeon.optionCache) - : VBLANK_FLAG_NO_IRQ; - - driDrawableInitVBlank( driDrawPriv ); - } - - newCtx->radeon.dri.drawable = driDrawPriv; - - radeonSetCliprects(&newCtx->radeon); - r200UpdateViewportOffset( newCtx->radeon.glCtx ); - } - - _mesa_make_current( newCtx->radeon.glCtx, - (GLframebuffer *) driDrawPriv->driverPrivate, - (GLframebuffer *) driReadPriv->driverPrivate ); - - _mesa_update_state( newCtx->radeon.glCtx ); - r200ValidateState( newCtx->radeon.glCtx ); - - } else { - if (R200_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx is null\n", __FUNCTION__); - _mesa_make_current( NULL, NULL, NULL ); - } - if (R200_DEBUG & DEBUG_DRI) - fprintf(stderr, "End %s\n", __FUNCTION__); - return GL_TRUE; -} /* Force the context `c' to be unbound from its buffer. */ diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index c1a68aa694..5ecf797999 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -538,7 +538,8 @@ struct r200_tcl_info { GLuint hw_primitive; /* hw can handle 12 components max */ - struct radeon_dma_region *aos_components[12]; + struct radeon_aos aos[12]; + // struct radeon_dma_region *aos_components[12]; GLuint nr_aos_components; GLuint *Elts; @@ -600,6 +601,8 @@ struct r200_swtcl_info { */ GLboolean needproj; + struct radeon_bo *bo; + void (*flush) (r200ContextPtr); struct radeon_dma_region indexed_verts; }; @@ -619,7 +622,6 @@ struct r200_swtcl_info { #define R200_MAX_VERTEX_SIZE ((3*6)+11) - struct r200_context { struct radeon_context radeon; @@ -641,7 +643,7 @@ struct r200_context { /* Clientdata textures; */ - GLuint prefer_gart_client_texturing; + GLuint prefer_gart_client_texturing; GLboolean save_on_next_emit; diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index fe3a471c8a..1bb97c5002 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -42,6 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast/swrast.h" #include "r200_context.h" +#include "common_cmdbuf.h" #include "r200_state.h" #include "r200_ioctl.h" #include "r200_tcl.h" @@ -77,11 +78,12 @@ static void r200BackUpAndEmitLostStateLocked( r200ContextPtr rmesa ) saved_store = rmesa->store; rmesa->dma.nr_released_bufs = 0; rmesa->store = rmesa->backup_store; - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); rmesa->dma.nr_released_bufs = nr_released_bufs; rmesa->store = saved_store; } +#if 0 int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ) { int ret, i; @@ -163,7 +165,6 @@ int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ) return ret; } - /* Note: does not emit any commands to avoid recursion on * r200AllocCmdBuf. */ @@ -173,7 +174,7 @@ void r200FlushCmdBuf( r200ContextPtr rmesa, const char *caller ) LOCK_HARDWARE( &rmesa->radeon ); - ret = r200FlushCmdBufLocked( rmesa, caller ); + ret = rcommonFlushCmdBufLocked( rmesa, caller ); UNLOCK_HARDWARE( &rmesa->radeon ); @@ -182,13 +183,14 @@ void r200FlushCmdBuf( r200ContextPtr rmesa, const char *caller ) exit(ret); } } +#endif /* ============================================================= * Hardware vertex buffer handling */ - +#if 0 void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) { struct radeon_dma_buffer *dmabuf; @@ -209,7 +211,7 @@ void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) r200ReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ ); if (rmesa->dma.nr_released_bufs > 4) - r200FlushCmdBuf( rmesa, __FUNCTION__ ); + rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); dma.context = rmesa->radeon.dri.hwContext; dma.send_count = 0; @@ -230,7 +232,7 @@ void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) break; if (rmesa->dma.nr_released_bufs) { - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); } if (rmesa->radeon.do_usleeps) { @@ -325,7 +327,7 @@ void r200AllocDmaRegion( r200ContextPtr rmesa, assert( rmesa->dma.current.ptr <= rmesa->dma.current.end ); } - +#endif /* ================================================================ * Buffer clear @@ -437,7 +439,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) } /* Send current state to the hardware */ - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); for ( i = 0 ; i < dPriv->numClipRects ; ) { GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, dPriv->numClipRects ); @@ -525,7 +527,7 @@ void r200Flush( GLcontext *ctx ) r200EmitState( rmesa ); if (rmesa->store.cmd_used) - r200FlushCmdBuf( rmesa, __FUNCTION__ ); + rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); } /* Make sure all commands have been sent to the hardware and have diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index 1f92705685..f36a6fd90f 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -45,8 +45,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. extern void r200EmitState( r200ContextPtr rmesa ); extern void r200EmitVertexAOS( r200ContextPtr rmesa, - GLuint vertex_size, - GLuint offset ); + GLuint vertex_size, + struct radeon_bo *bo, + GLuint offset ); extern void r200EmitVbufPrim( r200ContextPtr rmesa, GLuint primitive, @@ -58,10 +59,7 @@ extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, GLuint primitive, GLuint min_nr ); -extern void r200EmitAOS( r200ContextPtr rmesa, - struct radeon_dma_region **regions, - GLuint n, - GLuint offset ); +extern void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset); extern void r200EmitBlit( r200ContextPtr rmesa, GLuint color_fmt, @@ -75,8 +73,8 @@ extern void r200EmitBlit( r200ContextPtr rmesa, extern void r200EmitWait( r200ContextPtr rmesa, GLuint flags ); -extern void r200FlushCmdBuf( r200ContextPtr rmesa, const char * ); -extern int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ); +//extern void r200FlushCmdBuf( r200ContextPtr rmesa, const char * ); +//extern int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ); extern void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ); @@ -178,10 +176,11 @@ do { \ * and hang on to the lock until the critical section is finished and we flush * the buffer again and unlock. */ +#if 0 static INLINE void r200EnsureCmdBufSpace( r200ContextPtr rmesa, int bytes ) { if (rmesa->store.cmd_used + bytes > R200_CMD_BUF_SZ) - r200FlushCmdBuf( rmesa, __FUNCTION__ ); + rcommonFlushCmdBuf( rmesa, __FUNCTION__ ); assert( bytes <= R200_CMD_BUF_SZ ); } @@ -200,5 +199,47 @@ static INLINE char *r200AllocCmdBuf( r200ContextPtr rmesa, assert( rmesa->store.cmd_used <= R200_CMD_BUF_SZ ); return head; } +#endif + +static inline uint32_t cmdpacket3_clip(int cmd_type) +{ + drm_radeon_cmd_header_t cmd; + + cmd.i = 0; + cmd.header.cmd_type = RADEON_CMD_PACKET3_CLIP; + + return (uint32_t)cmd.i; + +} +#define OUT_BATCH_PACKET3_CLIP(packet, num_extra) do { \ + if (!b_l_rmesa->radeonScreen->kernel_mm) { \ + OUT_BATCH(cmdpacket3_clip(0)); \ + OUT_BATCH(packet); \ + } else { \ + OUT_BATCH(CP_PACKET2); \ + OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ + } \ + } while(0) + +static inline uint32_t cmdpacket3(int cmd_type) +{ + drm_radeon_cmd_header_t cmd; + + cmd.i = 0; + cmd.header.cmd_type = RADEON_CMD_PACKET3; + + return (uint32_t)cmd.i; + +} +#define OUT_BATCH_PACKET3(packet, num_extra) do { \ + if (!b_l_rmesa->radeonScreen->kernel_mm) { \ + OUT_BATCH(cmdpacket3(0)); \ + OUT_BATCH(packet); \ + } else { \ + OUT_BATCH(CP_PACKET2); \ + OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ + } \ + } while(0) + #endif /* __R200_IOCTL_H__ */ diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c index 838dfe79f9..7fe1590c8d 100644 --- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c +++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c @@ -123,14 +123,14 @@ static void emit_ubyte_rgba( GLcontext *ctx, assert (!rvb->buf); if (stride == 0) { - r200AllocDmaRegion( rmesa, rvb, 4, 4 ); + // r200AllocDmaRegion( rmesa, rvb, 4, 4 ); count = 1; rvb->aos_start = GET_START(rvb); rvb->aos_stride = 0; rvb->aos_size = 1; } else { - r200AllocDmaRegion( rmesa, rvb, 4 * count, 4 ); /* alignment? */ + // r200AllocDmaRegion( rmesa, rvb, 4 * count, 4 ); /* alignment? */ rvb->aos_start = GET_START(rvb); rvb->aos_stride = 1; rvb->aos_size = 1; @@ -193,14 +193,14 @@ static void emit_vecfog( GLcontext *ctx, assert (!rvb->buf); if (stride == 0) { - r200AllocDmaRegion( rmesa, rvb, 4, 4 ); + // r200AllocDmaRegion( rmesa, rvb, 4, 4 ); count = 1; rvb->aos_start = GET_START(rvb); rvb->aos_stride = 0; rvb->aos_size = 1; } else { - r200AllocDmaRegion( rmesa, rvb, count * 4, 4 ); /* alignment? */ + // r200AllocDmaRegion( rmesa, rvb, count * 4, 4 ); /* alignment? */ rvb->aos_start = GET_START(rvb); rvb->aos_stride = 1; rvb->aos_size = 1; @@ -334,14 +334,14 @@ static void emit_vector( GLcontext *ctx, assert (!rvb->buf); if (stride == 0) { - r200AllocDmaRegion( rmesa, rvb, size * 4, 4 ); + // r200AllocDmaRegion( rmesa, rvb, size * 4, 4 ); count = 1; rvb->aos_start = GET_START(rvb); rvb->aos_stride = 0; rvb->aos_size = size; } else { - r200AllocDmaRegion( rmesa, rvb, size * count * 4, 4 ); /* alignment? */ + // r200AllocDmaRegion( rmesa, rvb, size * count * 4, 4 ); /* alignment? */ rvb->aos_start = GET_START(rvb); rvb->aos_stride = size; rvb->aos_size = size; @@ -379,7 +379,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) { r200ContextPtr rmesa = R200_CONTEXT( ctx ); struct vertex_buffer *VB = &TNL_CONTEXT( ctx )->vb; - struct radeon_dma_region **component = rmesa->tcl.aos_components; + // struct radeon_dma_region **component = rmesa->tcl.aos_components; GLuint nr = 0; GLuint vfmt0 = 0, vfmt1 = 0; GLuint count = VB->Count; @@ -418,12 +418,12 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) assert(attrib == VERT_ATTRIB_FOG); if (!rmesa->tcl.vertex_data[i].buf) { if (ctx->VertexProgram._Enabled) - emit_vector( ctx, - &(rmesa->tcl.vertex_data[i]), - (char *)VB->AttribPtr[attrib]->data, - 1, - VB->AttribPtr[attrib]->stride, - count); + rcommon_emit_vector( ctx, + &(rmesa->tcl.vertex_data[i]), + (char *)VB->AttribPtr[attrib]->data, + 1, + VB->AttribPtr[attrib]->stride, + count); else emit_vecfog( ctx, &(rmesa->tcl.vertex_data[i]), @@ -483,7 +483,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) } after_emit: assert(nr < 12); - component[nr++] = &rmesa->tcl.vertex_data[i]; + // component[nr++] = &rmesa->tcl.vertex_data[i]; } } @@ -505,8 +505,8 @@ void r200ReleaseArrays( GLcontext *ctx, GLuint newinputs ) /* only do it for changed inputs ? */ int i; for (i = 0; i < 15; i++) { - if (newinputs & (1 << i)) - r200ReleaseDmaRegion( rmesa, - &rmesa->tcl.vertex_data[i], __FUNCTION__ ); + // if (newinputs & (1 << i)) + // r200ReleaseDmaRegion( rmesa, + // &rmesa->tcl.vertex_data[i], __FUNCTION__ ); } } diff --git a/src/mesa/drivers/dri/r200/r200_pixel.c b/src/mesa/drivers/dri/r200/r200_pixel.c index a8aa1a2773..930d797f45 100644 --- a/src/mesa/drivers/dri/r200/r200_pixel.c +++ b/src/mesa/drivers/dri/r200/r200_pixel.c @@ -200,7 +200,7 @@ r200TryReadPixels( GLcontext *ctx, LOCK_HARDWARE( &rmesa->radeon ); if (rmesa->store.cmd_used) - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); if (!clip_pixelrect(ctx, ctx->ReadBuffer, &x, &y, &width, &height, &size)) { @@ -257,7 +257,7 @@ r200TryReadPixels( GLcontext *ctx, bw, bh ); } - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); } UNLOCK_HARDWARE( &rmesa->radeon ); @@ -321,7 +321,7 @@ static void do_draw_pix( GLcontext *ctx, LOCK_HARDWARE( &rmesa->radeon ); if (rmesa->store.cmd_used) - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); y -= height; /* cope with pixel zoom */ @@ -363,7 +363,7 @@ static void do_draw_pix( GLcontext *ctx, bw, bh ); } - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); radeonWaitForIdleLocked( &rmesa->radeon ); /* required by GL */ UNLOCK_HARDWARE( &rmesa->radeon ); } diff --git a/src/mesa/drivers/dri/r200/r200_span.c b/src/mesa/drivers/dri/r200/r200_span.c index b4da9ef6a3..df0172f64e 100644 --- a/src/mesa/drivers/dri/r200/r200_span.c +++ b/src/mesa/drivers/dri/r200/r200_span.c @@ -38,6 +38,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast/swrast.h" #include "r200_context.h" +#include "radeon_buffer.h" #include "r200_ioctl.h" #include "r200_state.h" #include "r200_span.h" @@ -86,8 +87,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define SPANTMP_PIXEL_FMT GL_RGB #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5 -#define TAG(x) r200##x##_RGB565 -#define TAG2(x,y) r200##x##_RGB565##y +#define TAG(x) radeon##x##_RGB565 +#define TAG2(x,y) radeon##x##_RGB565##y #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 2) #include "spantmp2.h" @@ -96,8 +97,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define SPANTMP_PIXEL_FMT GL_BGRA #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV -#define TAG(x) r200##x##_ARGB8888 -#define TAG2(x,y) r200##x##_ARGB8888##y +#define TAG(x) radeon##x##_ARGB8888 +#define TAG2(x,y) radeon##x##_ARGB8888##y #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 4) #include "spantmp2.h" @@ -180,7 +181,7 @@ r200_mba_z16( driRenderbuffer *drb, GLint x, GLint y ) #define READ_DEPTH( d, _x, _y ) \ d = *(GLushort *)(buf + r200_mba_z16( drb, _x + xo, _y + yo )); -#define TAG(x) r200##x##_z16 +#define TAG(x) radeon##x##_z16 #include "depthtmp.h" @@ -201,7 +202,7 @@ do { \ d = *(GLuint *)(buf + r200_mba_z32( drb, _x + xo, \ _y + yo )) & 0x00ffffff; -#define TAG(x) r200##x##_z24_s8 +#define TAG(x) radeon##x##_z24_s8 #include "depthtmp.h" @@ -228,7 +229,7 @@ do { \ d = tmp >> 24; \ } while (0) -#define TAG(x) r200##x##_z24_s8 +#define TAG(x) radeon##x##_z24_s8 #include "stenciltmp.h" @@ -284,24 +285,17 @@ void r200InitSpanFuncs( GLcontext *ctx ) /** * Plug in the Get/Put routines for the given driRenderbuffer. */ -void -radeonSetSpanFunctions(driRenderbuffer *drb, const GLvisual *vis) +void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb) { - if (drb->Base.InternalFormat == GL_RGBA) { - if (vis->redBits == 5 && vis->greenBits == 6 && vis->blueBits == 5) { - r200InitPointers_RGB565(&drb->Base); - } - else { - r200InitPointers_ARGB8888(&drb->Base); - } - } - else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) { - r200InitDepthPointers_z16(&drb->Base); - } - else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) { - r200InitDepthPointers_z24_s8(&drb->Base); - } - else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) { - r200InitStencilPointers_z24_s8(&drb->Base); - } + if (rrb->base.InternalFormat == GL_RGB5) { + radeonInitPointers_RGB565(&rrb->base); + } else if (rrb->base.InternalFormat == GL_RGBA8) { + radeonInitPointers_ARGB8888(&rrb->base); + } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT16) { + radeonInitDepthPointers_z16(&rrb->base); + } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT24) { + radeonInitDepthPointers_z24_s8(&rrb->base); + } else if (rrb->base.InternalFormat == GL_STENCIL_INDEX8_EXT) { + radeonInitStencilPointers_z24_s8(&rrb->base); + } } diff --git a/src/mesa/drivers/dri/r200/r200_span.h b/src/mesa/drivers/dri/r200/r200_span.h index bae5644309..b2f3d5e43c 100644 --- a/src/mesa/drivers/dri/r200/r200_span.h +++ b/src/mesa/drivers/dri/r200/r200_span.h @@ -39,7 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. extern void r200InitSpanFuncs( GLcontext *ctx ); -extern void -radeonSetSpanFunctions(driRenderbuffer *rb, const GLvisual *vis); +extern void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb); #endif diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index 997c1711f9..f2e62d1bf7 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -47,6 +47,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/t_pipeline.h" #include "swrast_setup/swrast_setup.h" +#include "radeon_buffer.h" #include "r200_context.h" #include "r200_ioctl.h" #include "r200_state.h" @@ -1624,8 +1625,8 @@ void r200UpdateWindow( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; - GLfloat xoffset = (GLfloat)dPriv->x; - GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h; + GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; + GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; const GLfloat *v = ctx->Viewport._WindowMap.m; float_ui32_type sx = { v[MAT_SX] }; @@ -2316,34 +2317,34 @@ r200UpdateDrawBuffer(GLcontext *ctx) { r200ContextPtr rmesa = R200_CONTEXT(ctx); struct gl_framebuffer *fb = ctx->DrawBuffer; - driRenderbuffer *drb; + struct radeon_renderbuffer *rrb; if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { - /* draw to front */ - drb = (driRenderbuffer *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - } - else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { - /* draw to back */ - drb = (driRenderbuffer *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - } - else { - /* drawing to multiple buffers, or none */ - return; + /* draw to front */ + rrb = (void *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + } else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { + /* draw to back */ + rrb = (void *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + } else { + /* drawing to multiple buffers, or none */ + return; } - assert(drb); - assert(drb->flippedPitch); + assert(rrb); + assert(rrb->pitch); R200_STATECHANGE( rmesa, ctx ); +#if 0 /* Note: we used the (possibly) page-flipped values */ rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] - = ((drb->flippedOffset + rmesa->radeon.radeonScreen->fbLocation) + = ((rrb->flippedOffset + rmesa->radeon.radeonScreen->fbLocation) & R200_COLOROFFSET_MASK); rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = drb->flippedPitch; if (rmesa->radeon.sarea->tiling_enabled) { rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE; } +#endif } diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index f68f5ae08f..f46b01b56a 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -52,6 +52,115 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "xmlpool.h" +/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in + * 1.3 cmdbuffers allow all previous state to be updated as well as + * the tcl scalar and vector areas. + */ +static struct { + int start; + int len; + const char *name; +} packet[RADEON_MAX_STATE_PACKETS] = { + {RADEON_PP_MISC, 7, "RADEON_PP_MISC"}, + {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"}, + {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"}, + {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"}, + {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"}, + {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"}, + {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"}, + {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"}, + {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"}, + {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"}, + {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"}, + {RADEON_RE_MISC, 1, "RADEON_RE_MISC"}, + {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"}, + {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"}, + {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"}, + {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"}, + {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"}, + {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"}, + {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"}, + {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"}, + {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17, + "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"}, + {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"}, + {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"}, + {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"}, + {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"}, + {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"}, + {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"}, + {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"}, + {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"}, + {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"}, + {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"}, + {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"}, + {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"}, + {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"}, + {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"}, + {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"}, + {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"}, + {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"}, + {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"}, + {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"}, + {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"}, + {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"}, + {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"}, + {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"}, + {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"}, + {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"}, + {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"}, + {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"}, + {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"}, + {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, + "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"}, + {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"}, + {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"}, + {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"}, + {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"}, + {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"}, + {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"}, + {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"}, + {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"}, + {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"}, + {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"}, + {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, + "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"}, + {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */ + {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */ + {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"}, + {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"}, + {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"}, + {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"}, + {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"}, + {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"}, + {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"}, + {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"}, + {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"}, + {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"}, + {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"}, + {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"}, + {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"}, + {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"}, + {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"}, + {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, + {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, + {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, + {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, + {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, + {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, + {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, + {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */ + {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"}, + {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, + {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, + {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, + {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, + {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, + {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, + {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, + {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"}, +}; + /* ============================================================= * State initialization */ @@ -179,6 +288,39 @@ VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96 ) +#if 0 +static int ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r200ContextPtr r200 = R200_CONTEXT(ctx); + BATCH_LOCALS(&r200->radeon); + struct radeon_renderbuffer *rrb; + uint32_t cbpitch; + GLframebuffer *fb = r200->radeon.dri.drawable->driverPrivate; + + rrb = r200->radeon.state.color.rrb; + if (r200->radeon.radeonScreen->driScreen->dri2.enabled) { + rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + } + if (!rrb || !rrb->bo) { + fprintf(stderr, "no rrb\n"); + return; + } + + cbpitch = (rrb->pitch / rrb->cpp); + if (rrb->cpp == 4) + ; + else + ; + +} +#endif + +static int tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + +} + + /* Initialize the context's hardware state. */ void r200InitState( r200ContextPtr rmesa ) @@ -267,6 +409,8 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( ctx, always, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 ); else ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 ); + + // rmesa->hw.ctx.emit = ctx_emit; ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 ); ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); @@ -964,4 +1108,6 @@ void r200InitState( r200ContextPtr rmesa ) r200LightingSpaceChange( ctx ); rmesa->hw.all_dirty = GL_TRUE; + + rcommonInitCmdBuf(&rmesa->radeon, rmesa->hw.max_state_size); } diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index 1130c3544d..0be772d015 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -48,6 +48,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/t_context.h" #include "tnl/t_pipeline.h" +#include "radeon_bo.h" #include "r200_context.h" #include "r200_ioctl.h" #include "r200_state.h" @@ -284,33 +285,24 @@ static void flush_last_swtcl_prim(GLcontext *ctx) rmesa->dma.flush = NULL; - if (rmesa->dma.current.buf) { - struct radeon_dma_region *current = &rmesa->dma.current; - GLuint current_offset = (rmesa->radeon.radeonScreen->gart_buffer_offset + - current->buf->buf->idx * RADEON_BUFFER_SIZE + - current->start); + radeon_bo_unmap(rmesa->swtcl.bo); + rcommonEnsureCmdBufSpace(rmesa, + rmesa->hw.max_state_size + (12*sizeof(int)), + __FUNCTION__); - assert (!(rmesa->swtcl.hw_primitive & R200_VF_PRIM_WALK_IND)); - assert (current->start + - rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == - current->ptr); + r200EmitState(rmesa); + r200EmitVertexAOS( rmesa, + rmesa->swtcl.vertex_size, + rmesa->swtcl.bo, 0); - if (rmesa->dma.current.start != rmesa->dma.current.ptr) { - r200EnsureCmdBufSpace( rmesa, VERT_AOS_BUFSZ + - rmesa->hw.max_state_size + VBUF_BUFSZ ); - r200EmitVertexAOS( rmesa, - rmesa->swtcl.vertex_size, - current_offset); + + r200EmitVbufPrim( rmesa, + rmesa->swtcl.hw_primitive, + rmesa->swtcl.numverts); - r200EmitVbufPrim( rmesa, - rmesa->swtcl.hw_primitive, - rmesa->swtcl.numverts); - } - - rmesa->swtcl.numverts = 0; - current->start = current->ptr; - } + // COMMIT_BATCH(); + rmesa->swtcl.numverts = 0; } @@ -321,28 +313,16 @@ r200AllocDmaLowVerts( r200ContextPtr rmesa, int nverts, int vsize ) { GLuint bytes = vsize * nverts; - if ( rmesa->dma.current.ptr + bytes > rmesa->dma.current.end ) - r200RefillCurrentDmaRegion( rmesa ); - - if (!rmesa->dma.flush) { - rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->dma.flush = flush_last_swtcl_prim; - } - - ASSERT( vsize == rmesa->swtcl.vertex_size * 4 ); - ASSERT( rmesa->dma.flush == flush_last_swtcl_prim ); - ASSERT( rmesa->dma.current.start + - rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == - rmesa->dma.current.ptr ); - - - { - GLubyte *head = (GLubyte *) (rmesa->dma.current.address + rmesa->dma.current.ptr); - rmesa->dma.current.ptr += bytes; - rmesa->swtcl.numverts += nverts; - return head; + rmesa->swtcl.bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, + 0, bytes, 4, RADEON_GEM_DOMAIN_GTT, 0); + radeon_bo_map(rmesa->swtcl.bo, 1); + if (rmesa->swtcl.flush == NULL) { + rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; + rmesa->swtcl.flush = flush_last_swtcl_prim; } + return rmesa->swtcl.bo->ptr; + } @@ -974,6 +954,6 @@ void r200DestroySwtcl( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - if (rmesa->swtcl.indexed_verts.buf) - r200ReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, __FUNCTION__ ); + // if (rmesa->swtcl.indexed_verts.buf) + // r200ReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, __FUNCTION__ ); } diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index d14564c29b..4a31578c89 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -156,11 +156,10 @@ static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) if (rmesa->dma.flush) rmesa->dma.flush( rmesa->radeon.glCtx ); - r200EnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + + rcommonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + rmesa->hw.max_state_size + ELTS_BUFSZ(nr) ); r200EmitAOS( rmesa, - rmesa->tcl.aos_components, rmesa->tcl.nr_aos_components, 0 ); return r200AllocEltsOpenEnded( rmesa, rmesa->tcl.hw_primitive, nr ); @@ -188,13 +187,12 @@ static void r200EmitPrim( GLcontext *ctx, r200ContextPtr rmesa = R200_CONTEXT( ctx ); r200TclPrimitive( ctx, prim, hwprim ); - r200EnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + - rmesa->hw.max_state_size + VBUF_BUFSZ ); + rcommonEnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + + rmesa->hw.max_state_size + VBUF_BUFSZ ); r200EmitAOS( rmesa, - rmesa->tcl.aos_components, - rmesa->tcl.nr_aos_components, - start ); + rmesa->tcl.nr_aos_components, + start ); /* Why couldn't this packet have taken an offset param? */ @@ -570,9 +568,9 @@ static void transition_to_hwtnl( GLcontext *ctx ) rmesa->dma.flush = NULL; - if (rmesa->swtcl.indexed_verts.buf) - r200ReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, - __FUNCTION__ ); + // if (rmesa->swtcl.indexed_verts.buf) + // r200ReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, + // __FUNCTION__ ); R200_STATECHANGE( rmesa, vap ); rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] |= R200_VAP_TCL_ENABLE; diff --git a/src/mesa/drivers/dri/r200/r200_texmem.c b/src/mesa/drivers/dri/r200/r200_texmem.c index e8b6876dd3..5a0922de21 100644 --- a/src/mesa/drivers/dri/r200/r200_texmem.c +++ b/src/mesa/drivers/dri/r200/r200_texmem.c @@ -226,7 +226,7 @@ static void r200UploadRectSubImage( r200ContextPtr rmesa, tex = (char *)texImage->Data + done * src_pitch; memset(®ion, 0, sizeof(region)); - r200AllocDmaRegion( rmesa, ®ion, lines * dstPitch, 1024 ); + // r200AllocDmaRegion( rmesa, ®ion, lines * dstPitch, 1024 ); /* Copy texdata to dma: */ @@ -262,7 +262,7 @@ static void r200UploadRectSubImage( r200ContextPtr rmesa, r200EmitWait( rmesa, RADEON_WAIT_2D ); - r200ReleaseDmaRegion( rmesa, ®ion, __FUNCTION__ ); + // r200ReleaseDmaRegion( rmesa, ®ion, __FUNCTION__ ); done += lines; } } diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 3647022622..798f1f58c9 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -496,8 +496,6 @@ void r300DestroyContext(__DRIcontextPrivate * driContextPriv) * state, so don't destroy it earlier */ - /* free the option cache */ - driDestroyOptionCache(&r300->radeon.optionCache); FREE(r300); } diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 8449d00d37..477756774d 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -700,19 +700,11 @@ struct r500_fragment_program { #define REG_COLOR0 1 #define REG_TEX0 2 -struct r300_aos { - struct radeon_bo *bo; /** Buffer object where vertex data is stored */ - int offset; /** Offset into buffer object, in bytes */ - int components; /** Number of components per vertex */ - int stride; /** Stride in dwords (may be 0 for repeating) */ - int count; /** Number of vertices */ -}; - struct r300_state { struct r300_texture_state texture; int sw_tcl_inputs[VERT_ATTRIB_MAX]; struct r300_vertex_shader_state vertex_shader; - struct r300_aos aos[R300_MAX_AOS_ARRAYS]; + struct radeon_aos aos[R300_MAX_AOS_ARRAYS]; int aos_count; struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */ diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index bf33c18979..e2d90a843e 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -63,141 +63,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define DEBUG_ALL DEBUG_VERTS -#if defined(USE_X86_ASM) -#define COPY_DWORDS( dst, src, nr ) \ -do { \ - int __tmp; \ - __asm__ __volatile__( "rep ; movsl" \ - : "=%c" (__tmp), "=D" (dst), "=S" (__tmp) \ - : "0" (nr), \ - "D" ((long)dst), \ - "S" ((long)src) ); \ -} while (0) -#else -#define COPY_DWORDS( dst, src, nr ) \ -do { \ - int j; \ - for ( j = 0 ; j < nr ; j++ ) \ - dst[j] = ((int *)src)[j]; \ - dst += nr; \ -} while (0) -#endif - -static void r300EmitVec4(uint32_t *out, GLvoid * data, int stride, int count) -{ - int i; - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d out %p data %p\n", - __FUNCTION__, count, stride, (void *)out, (void *)data); - - if (stride == 4) - COPY_DWORDS(out, data, count); - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out++; - data += stride; - } -} - -static void r300EmitVec8(uint32_t *out, GLvoid * data, int stride, int count) -{ - int i; - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d out %p data %p\n", - __FUNCTION__, count, stride, (void *)out, (void *)data); - - if (stride == 8) - COPY_DWORDS(out, data, count * 2); - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out[1] = *(int *)(data + 4); - out += 2; - data += stride; - } -} - -static void r300EmitVec12(uint32_t *out, GLvoid * data, int stride, int count) -{ - int i; - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d out %p data %p\n", - __FUNCTION__, count, stride, (void *)out, (void *)data); - - if (stride == 12) { - COPY_DWORDS(out, data, count * 3); - } - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out[1] = *(int *)(data + 4); - out[2] = *(int *)(data + 8); - out += 3; - data += stride; - } -} - -static void r300EmitVec16(uint32_t *out, GLvoid * data, int stride, int count) -{ - int i; - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d out %p data %p\n", - __FUNCTION__, count, stride, (void *)out, (void *)data); - - if (stride == 16) - COPY_DWORDS(out, data, count * 4); - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out[1] = *(int *)(data + 4); - out[2] = *(int *)(data + 8); - out[3] = *(int *)(data + 12); - out += 4; - data += stride; - } -} - -static void r300EmitVec(GLcontext * ctx, struct r300_aos *aos, - GLvoid * data, int size, int stride, int count) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - uint32_t *out; - uint32_t bo_size; - - memset(aos, 0, sizeof(struct r300_aos)); - if (stride == 0) { - bo_size = size * 4; - count = 1; - aos->stride = 0; - } else { - bo_size = size * count * 4; - aos->stride = size; - } - aos->bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, - 0, bo_size, 32, RADEON_GEM_DOMAIN_GTT, 0); - aos->offset = 0; - aos->components = size; - aos->count = count; - - radeon_bo_map(aos->bo, 1); - out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); - switch (size) { - case 1: r300EmitVec4(out, data, stride, count); break; - case 2: r300EmitVec8(out, data, stride, count); break; - case 3: r300EmitVec12(out, data, stride, count); break; - case 4: r300EmitVec16(out, data, stride, count); break; - default: - assert(0); - break; - } - radeon_bo_unmap(aos->bo); -} - #define DW_SIZE(x) ((inputs[tab[(x)]] << R300_DST_VEC_LOC_SHIFT) | \ (attribptr[tab[(x)]]->size - 1) << R300_DATA_TYPE_0_SHIFT) @@ -429,10 +294,10 @@ int r300EmitArrays(GLcontext * ctx) for (ci = 0; ci < vb->AttribPtr[tab[i]]->size; ci++) { swizzle[i][ci] = ci; } - r300EmitVec(ctx, &rmesa->state.aos[i], - vb->AttribPtr[tab[i]]->data, - vb->AttribPtr[tab[i]]->size, - vb->AttribPtr[tab[i]]->stride, count); + rcommon_emit_vector(ctx, &rmesa->state.aos[i], + vb->AttribPtr[tab[i]]->data, + vb->AttribPtr[tab[i]]->size, + vb->AttribPtr[tab[i]]->stride, count); } /* Setup INPUT_ROUTE. */ diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h index 1e7a639c00..d6df2e9edf 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.h +++ b/src/mesa/drivers/dri/r300/r300_emit.h @@ -44,13 +44,6 @@ #include "r300_cmdbuf.h" #include "radeon_reg.h" -/* TODO: move these defines (and the ones from DRM) into r300_reg.h and sync up - * with DRM */ -#define CP_PACKET2 (2 << 30) -#define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) -#define CP_PACKET3( pkt, n ) \ - (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) - static INLINE uint32_t cmdpacket0(struct radeon_screen *rscrn, int reg, int count) { diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index c81393e747..ef3671eadb 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -180,11 +180,11 @@ static void r300EmitElts(GLcontext * ctx, void *elts, unsigned long n_elts) rmesa->state.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, 0, n_elts * 4, 4, RADEON_GEM_DOMAIN_GTT, 0); - rmesa->state.elt_dma_offset = 0; - radeon_bo_map(rmesa->state.elt_dma_bo, 1); + rmesa->state.elt_dma_offset = 0; + radeon_bo_map(rmesa->state.elt_dma_bo, 1); out = rmesa->state.elt_dma_bo->ptr + rmesa->state.elt_dma_offset; memcpy(out, elts, n_elts * 4); - radeon_bo_unmap(rmesa->state.elt_dma_bo); + radeon_bo_unmap(rmesa->state.elt_dma_bo); } static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 03fc2107db..eb86bd3bdd 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -271,13 +271,13 @@ r300AllocDmaLowVerts( r300ContextPtr rmesa, int nverts, int vsize ) GLuint bytes = vsize * nverts; rmesa->swtcl.bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, - 0, bytes, 4, RADEON_GEM_DOMAIN_GTT, 0); - radeon_bo_map(rmesa->swtcl.bo, 1); - if (rmesa->swtcl.flush == NULL) { - rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->swtcl.flush = flush_last_swtcl_prim; - } - return rmesa->swtcl.bo->ptr; + 0, bytes, 4, RADEON_GEM_DOMAIN_GTT, 0); + radeon_bo_map(rmesa->swtcl.bo, 1); + if (rmesa->swtcl.flush == NULL) { + rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; + rmesa->swtcl.flush = flush_last_swtcl_prim; + } + return rmesa->swtcl.bo->ptr; } static GLuint reduced_prim[] = { diff --git a/src/mesa/drivers/dri/r300/radeon_context.c b/src/mesa/drivers/dri/r300/radeon_context.c index 6884967663..13a7682416 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.c +++ b/src/mesa/drivers/dri/r300/radeon_context.c @@ -60,502 +60,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "xmlpool.h" /* for symbolic values of enum-type options */ #include "drirenderbuffer.h" -#define DRIVER_DATE "20060815" - - -/* Return various strings for glGetString(). - */ -static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name) -{ - radeonContextPtr radeon = RADEON_CONTEXT(ctx); - static char buffer[128]; - - switch (name) { - case GL_VENDOR: - if (IS_R300_CLASS(radeon->radeonScreen)) - return (GLubyte *) "DRI R300 Project"; - else - return (GLubyte *) "Tungsten Graphics, Inc."; - - case GL_RENDERER: - { - unsigned offset; - GLuint agp_mode = (radeon->radeonScreen->card_type==RADEON_CARD_PCI) ? 0 : - radeon->radeonScreen->AGPMode; - const char* chipname; - - - - if (IS_R300_CLASS(radeon->radeonScreen)) - chipname = "R300"; - else - chipname = "R200"; - - offset = driGetRendererString(buffer, chipname, DRIVER_DATE, - agp_mode); - - if (IS_R300_CLASS(radeon->radeonScreen)) { - sprintf(&buffer[offset], " %sTCL", - (radeon->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) - ? "" : "NO-"); - } else { - sprintf(&buffer[offset], " %sTCL", - !(radeon->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE) - ? "" : "NO-"); - } - - if (radeon->radeonScreen->driScreen->dri2.enabled) - strcat(buffer, " DRI2"); - - return (GLubyte *) buffer; - } - - default: - return NULL; - } -} - -/* Initialize the driver's misc functions. - */ -static void radeonInitDriverFuncs(struct dd_function_table *functions) -{ - functions->GetString = radeonGetString; -} - - -/** - * Create and initialize all common fields of the context, - * including the Mesa context itself. - */ -GLboolean radeonInitContext(radeonContextPtr radeon, - struct dd_function_table* functions, - const __GLcontextModes * glVisual, - __DRIcontextPrivate * driContextPriv, - void *sharedContextPrivate) -{ - __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; - radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); - GLcontext* ctx; - GLcontext* shareCtx; - int fthrottle_mode; - - /* Fill in additional standard functions. */ - radeonInitDriverFuncs(functions); - - radeon->radeonScreen = screen; - /* Allocate and initialize the Mesa context */ - if (sharedContextPrivate) - shareCtx = ((radeonContextPtr)sharedContextPrivate)->glCtx; - else - shareCtx = NULL; - radeon->glCtx = _mesa_create_context(glVisual, shareCtx, - functions, (void *)radeon); - if (!radeon->glCtx) - return GL_FALSE; - - ctx = radeon->glCtx; - driContextPriv->driverPrivate = radeon; - - /* DRI fields */ - radeon->dri.context = driContextPriv; - radeon->dri.screen = sPriv; - radeon->dri.drawable = NULL; - radeon->dri.readable = NULL; - radeon->dri.hwContext = driContextPriv->hHWContext; - radeon->dri.hwLock = &sPriv->pSAREA->lock; - radeon->dri.fd = sPriv->fd; - radeon->dri.drmMinor = sPriv->drm_version.minor; - - radeon->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + - screen->sarea_priv_offset); - - /* Setup IRQs */ - fthrottle_mode = driQueryOptioni(&radeon->optionCache, "fthrottle_mode"); - radeon->iw.irq_seq = -1; - radeon->irqsEmitted = 0; - radeon->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS && - radeon->radeonScreen->irq); - - radeon->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); - - if (!radeon->do_irqs) - fprintf(stderr, - "IRQ's not enabled, falling back to %s: %d %d\n", - radeon->do_usleeps ? "usleeps" : "busy waits", - fthrottle_mode, radeon->radeonScreen->irq); - - (*sPriv->systemTime->getUST) (&radeon->swap_ust); - - return GL_TRUE; -} - - -/** - * Cleanup common context fields. - * Called by r200DestroyContext/r300DestroyContext - */ -void radeonCleanupContext(radeonContextPtr radeon) -{ - FILE *track; - struct radeon_renderbuffer *rb; - GLframebuffer *fb; - - fb = (void*)radeon->dri.drawable->driverPrivate; - rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - fb = (void*)radeon->dri.readable->driverPrivate; - rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - - /* _mesa_destroy_context() might result in calls to functions that - * depend on the DriverCtx, so don't set it to NULL before. - * - * radeon->glCtx->DriverCtx = NULL; - */ - - /* free the Mesa context */ - _mesa_destroy_context(radeon->glCtx); - - if (radeon->state.scissor.pClipRects) { - FREE(radeon->state.scissor.pClipRects); - radeon->state.scissor.pClipRects = 0; - } - track = fopen("/tmp/tracklog", "w"); - if (track) { - radeon_tracker_print(&radeon->radeonScreen->bom->tracker, track); - fclose(track); - } -} - -static void -radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon, - GLframebuffer *draw) -{ - /* if radeon->fake */ - struct radeon_renderbuffer *rb; - - if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { - - if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->frontOffset, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - 0); - } - rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp; - } - if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { - if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->backOffset, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - 0); - } - rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->backPitch * rb->cpp; - } - if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { - if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->depthOffset, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - 0); - } - rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; - } -} - -static void -radeon_make_renderbuffer_current(radeonContextPtr radeon, - GLframebuffer *draw) -{ - int size = 4096*4096*4; - /* if radeon->fake */ - struct radeon_renderbuffer *rb; - - if (radeon->radeonScreen->kernel_mm) { - radeon_make_kernel_renderbuffer_current(radeon, draw); - return; - } - - - if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { - if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->frontOffset + - radeon->radeonScreen->fbLocation, - size, - 4096, - RADEON_GEM_DOMAIN_VRAM, - 0); - } - rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp; - } - if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { - if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->backOffset + - radeon->radeonScreen->fbLocation, - size, - 4096, - RADEON_GEM_DOMAIN_VRAM, - 0); - } - rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->backPitch * rb->cpp; - } - if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { - if (!rb->bo) { - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - radeon->radeonScreen->depthOffset + - radeon->radeonScreen->fbLocation, - size, - 4096, - RADEON_GEM_DOMAIN_VRAM, - 0); - } - rb->cpp = radeon->radeonScreen->cpp; - rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; - } -} - - -void -radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) -{ - unsigned int attachments[10]; - __DRIbuffer *buffers; - __DRIscreen *screen; - struct radeon_renderbuffer *rb; - int i, count; - GLframebuffer *draw; - radeonContextPtr radeon; - - draw = drawable->driverPrivate; - screen = context->driScreenPriv; - radeon = (radeonContextPtr) context->driverPrivate; - i = 0; - if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { - attachments[i++] = __DRI_BUFFER_FRONT_LEFT; - } - if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { - attachments[i++] = __DRI_BUFFER_BACK_LEFT; - } - if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { - attachments[i++] = __DRI_BUFFER_DEPTH; - } - - buffers = (*screen->dri2.loader->getBuffers)(drawable, - &drawable->w, - &drawable->h, - attachments, i, - &count, - drawable->loaderPrivate); - if (buffers == NULL) - return; - - /* set one cliprect to cover the whole drawable */ - drawable->x = 0; - drawable->y = 0; - drawable->backX = 0; - drawable->backY = 0; - drawable->numClipRects = 1; - drawable->pClipRects[0].x1 = 0; - drawable->pClipRects[0].y1 = 0; - drawable->pClipRects[0].x2 = drawable->w; - drawable->pClipRects[0].y2 = drawable->h; - drawable->numBackClipRects = 1; - drawable->pBackClipRects[0].x1 = 0; - drawable->pBackClipRects[0].y1 = 0; - drawable->pBackClipRects[0].x2 = drawable->w; - drawable->pBackClipRects[0].y2 = drawable->h; - for (i = 0; i < count; i++) { - switch (buffers[i].attachment) { - case __DRI_BUFFER_FRONT_LEFT: - rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - if (rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb->cpp = buffers[i].cpp; - rb->pitch = buffers[i].pitch; - rb->width = drawable->w; - rb->height = drawable->h; - rb->has_surface = 0; - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - buffers[i].name, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - buffers[i].flags); - if (rb->bo == NULL) { - fprintf(stderr, "failled to attach front %d\n", - buffers[i].name); - } - break; - case __DRI_BUFFER_BACK_LEFT: - rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - if (rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb->cpp = buffers[i].cpp; - rb->pitch = buffers[i].pitch; - rb->width = drawable->w; - rb->height = drawable->h; - rb->has_surface = 0; - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - buffers[i].name, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - buffers[i].flags); - break; - case __DRI_BUFFER_DEPTH: - rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer; - if (rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb->cpp = buffers[i].cpp; - rb->pitch = buffers[i].pitch; - rb->width = drawable->w; - rb->height = drawable->h; - rb->has_surface = 0; - rb->bo = radeon_bo_open(radeon->radeonScreen->bom, - buffers[i].name, - 0, - 0, - RADEON_GEM_DOMAIN_VRAM, - buffers[i].flags); - break; - case __DRI_BUFFER_STENCIL: - break; - case __DRI_BUFFER_ACCUM: - default: - fprintf(stderr, - "unhandled buffer attach event, attacment type %d\n", - buffers[i].attachment); - return; - } - } - radeon = (radeonContextPtr) context->driverPrivate; - driUpdateFramebufferSize(radeon->glCtx, drawable); -} - - -/* Force the context `c' to be the current context and associate with it - * buffer `b'. - */ -GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, - __DRIdrawablePrivate * driDrawPriv, - __DRIdrawablePrivate * driReadPriv) -{ - radeonContextPtr radeon; - GLframebuffer *dfb, *rfb; - - if (!driContextPriv) { - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx is null\n", __FUNCTION__); - _mesa_make_current(NULL, NULL, NULL); - return GL_TRUE; - } - radeon = (radeonContextPtr) driContextPriv->driverPrivate; - dfb = driDrawPriv->driverPrivate; - rfb = driReadPriv->driverPrivate; - - if (driContextPriv->driScreenPriv->dri2.enabled) { - radeon_update_renderbuffers(driContextPriv, driDrawPriv); - if (driDrawPriv != driReadPriv) - radeon_update_renderbuffers(driContextPriv, driReadPriv); - radeon->state.color.rrb = - (void *)dfb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - radeon->state.depth.rrb = - (void *)dfb->Attachment[BUFFER_DEPTH].Renderbuffer; - } - - - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx %p\n", __FUNCTION__, radeon->glCtx); - - driUpdateFramebufferSize(radeon->glCtx, driDrawPriv); - if (driReadPriv != driDrawPriv) - driUpdateFramebufferSize(radeon->glCtx, driReadPriv); - - if (!driContextPriv->driScreenPriv->dri2.enabled) { - radeon_make_renderbuffer_current(radeon, dfb); - } - - _mesa_make_current(radeon->glCtx, dfb, rfb); - - if (radeon->dri.drawable != driDrawPriv) { - if (driDrawPriv->swap_interval == (unsigned)-1) { - driDrawPriv->vblFlags = - (radeon->radeonScreen->irq != 0) - ? driGetDefaultVBlankFlags(&radeon-> - optionCache) - : VBLANK_FLAG_NO_IRQ; - - driDrawableInitVBlank(driDrawPriv); - } - } - - radeon->dri.readable = driReadPriv; - - if (radeon->dri.drawable != driDrawPriv || - radeon->lastStamp != driDrawPriv->lastStamp) { - radeon->dri.drawable = driDrawPriv; - - radeonSetCliprects(radeon); - r300UpdateViewportOffset(radeon->glCtx); - } - - _mesa_update_state(radeon->glCtx); - - if (!driContextPriv->driScreenPriv->dri2.enabled) { - radeonUpdatePageFlipping(radeon); - } - - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "End %s\n", __FUNCTION__); - return GL_TRUE; -} - /* Force the context `c' to be unbound from its buffer. */ GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv) diff --git a/src/mesa/drivers/dri/radeon/common_cmdbuf.h b/src/mesa/drivers/dri/radeon/common_cmdbuf.h index fbcbf72b2b..d6fa50a029 100644 --- a/src/mesa/drivers/dri/radeon/common_cmdbuf.h +++ b/src/mesa/drivers/dri/radeon/common_cmdbuf.h @@ -14,6 +14,10 @@ void rcommonBeginBatch(radeonContextPtr rmesa, const char *function, int line); +#define CP_PACKET2 (2 << 30) +#define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) +#define CP_PACKET3( pkt, n ) \ + (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) /** * Every function writing to the command buffer needs to declare this diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index d6e15bc3b8..22fb908fb4 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -46,6 +46,16 @@ typedef struct radeon_context *radeonContextPtr; #define R200_FALLBACK_DISABLE 0x10 #define R200_FALLBACK_BORDER_MODE 0x20 +#define RADEON_TCL_FALLBACK_RASTER 0x1 /* rasterization */ +#define RADEON_TCL_FALLBACK_UNFILLED 0x2 /* unfilled tris */ +#define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE 0x4 /* twoside tris */ +#define RADEON_TCL_FALLBACK_MATERIAL 0x8 /* material in vb */ +#define RADEON_TCL_FALLBACK_TEXGEN_0 0x10 /* texgen, unit 0 */ +#define RADEON_TCL_FALLBACK_TEXGEN_1 0x20 /* texgen, unit 1 */ +#define RADEON_TCL_FALLBACK_TEXGEN_2 0x40 /* texgen, unit 2 */ +#define RADEON_TCL_FALLBACK_TCL_DISABLE 0x80 /* user disable */ +#define RADEON_TCL_FALLBACK_FOGCOORDSPEC 0x100 /* fogcoord, sep. spec light */ + /* The blit width for texture uploads */ #define BLIT_WIDTH_BYTES 1024 @@ -157,6 +167,13 @@ struct radeon_dma_region { int aos_size; }; +struct radeon_aos { + struct radeon_bo *bo; /** Buffer object where vertex data is stored */ + int offset; /** Offset into buffer object, in bytes */ + int components; /** Number of components per vertex */ + int stride; /** Stride in dwords (may be 0 for repeating) */ + int count; /** Number of vertices */ +}; struct radeon_dma { /* Active dma region. Allocations for vertices and retained diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index a234352658..383334a005 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -50,6 +50,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drirenderbuffer.h" #include "vblank.h" +#include "xmlpool.h" /* for symbolic values of enum-type options */ #include "radeon_bo.h" #include "radeon_cs.h" @@ -66,6 +67,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "common_lock.h" #include "common_cmdbuf.h" +#define DRIVER_DATE "20090101" + #ifndef RADEON_DEBUG int RADEON_DEBUG = (0); #endif @@ -703,3 +706,634 @@ void rcommonBeginBatch(radeonContextPtr rmesa, int n, } radeon_cs_begin(rmesa->cmdbuf.cs, n, file, function, line); } + + + +/* Return various strings for glGetString(). + */ +static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + static char buffer[128]; + + switch (name) { + case GL_VENDOR: + if (IS_R300_CLASS(radeon->radeonScreen)) + return (GLubyte *) "DRI R300 Project"; + else + return (GLubyte *) "Tungsten Graphics, Inc."; + + case GL_RENDERER: + { + unsigned offset; + GLuint agp_mode = (radeon->radeonScreen->card_type==RADEON_CARD_PCI) ? 0 : + radeon->radeonScreen->AGPMode; + const char* chipname; + + + + if (IS_R300_CLASS(radeon->radeonScreen)) + chipname = "R300"; + else + chipname = "R200"; + + offset = driGetRendererString(buffer, chipname, DRIVER_DATE, + agp_mode); + + if (IS_R300_CLASS(radeon->radeonScreen)) { + sprintf(&buffer[offset], " %sTCL", + (radeon->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) + ? "" : "NO-"); + } else { + sprintf(&buffer[offset], " %sTCL", + !(radeon->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE) + ? "" : "NO-"); + } + + if (radeon->radeonScreen->driScreen->dri2.enabled) + strcat(buffer, " DRI2"); + + return (GLubyte *) buffer; + } + + default: + return NULL; + } +} + +/* Initialize the driver's misc functions. + */ +static void radeonInitDriverFuncs(struct dd_function_table *functions) +{ + functions->GetString = radeonGetString; +} + +/** + * Create and initialize all common fields of the context, + * including the Mesa context itself. + */ +GLboolean radeonInitContext(radeonContextPtr radeon, + struct dd_function_table* functions, + const __GLcontextModes * glVisual, + __DRIcontextPrivate * driContextPriv, + void *sharedContextPrivate) +{ + __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); + GLcontext* ctx; + GLcontext* shareCtx; + int fthrottle_mode; + + /* Fill in additional standard functions. */ + radeonInitDriverFuncs(functions); + + radeon->radeonScreen = screen; + /* Allocate and initialize the Mesa context */ + if (sharedContextPrivate) + shareCtx = ((radeonContextPtr)sharedContextPrivate)->glCtx; + else + shareCtx = NULL; + radeon->glCtx = _mesa_create_context(glVisual, shareCtx, + functions, (void *)radeon); + if (!radeon->glCtx) + return GL_FALSE; + + ctx = radeon->glCtx; + driContextPriv->driverPrivate = radeon; + + /* DRI fields */ + radeon->dri.context = driContextPriv; + radeon->dri.screen = sPriv; + radeon->dri.drawable = NULL; + radeon->dri.readable = NULL; + radeon->dri.hwContext = driContextPriv->hHWContext; + radeon->dri.hwLock = &sPriv->pSAREA->lock; + radeon->dri.fd = sPriv->fd; + radeon->dri.drmMinor = sPriv->drm_version.minor; + + radeon->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + + screen->sarea_priv_offset); + + /* Setup IRQs */ + fthrottle_mode = driQueryOptioni(&radeon->optionCache, "fthrottle_mode"); + radeon->iw.irq_seq = -1; + radeon->irqsEmitted = 0; + radeon->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS && + radeon->radeonScreen->irq); + + radeon->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); + + if (!radeon->do_irqs) + fprintf(stderr, + "IRQ's not enabled, falling back to %s: %d %d\n", + radeon->do_usleeps ? "usleeps" : "busy waits", + fthrottle_mode, radeon->radeonScreen->irq); + + (*sPriv->systemTime->getUST) (&radeon->swap_ust); + + return GL_TRUE; +} + +/** + * Cleanup common context fields. + * Called by r200DestroyContext/r300DestroyContext + */ +void radeonCleanupContext(radeonContextPtr radeon) +{ + FILE *track; + struct radeon_renderbuffer *rb; + GLframebuffer *fb; + + fb = (void*)radeon->dri.drawable->driverPrivate; + rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + fb = (void*)radeon->dri.readable->driverPrivate; + rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + + /* _mesa_destroy_context() might result in calls to functions that + * depend on the DriverCtx, so don't set it to NULL before. + * + * radeon->glCtx->DriverCtx = NULL; + */ + + /* free the Mesa context */ + _mesa_destroy_context(radeon->glCtx); + + /* free the option cache */ + driDestroyOptionCache(&radeon->optionCache); + + if (radeon->state.scissor.pClipRects) { + FREE(radeon->state.scissor.pClipRects); + radeon->state.scissor.pClipRects = 0; + } + track = fopen("/tmp/tracklog", "w"); + if (track) { + radeon_tracker_print(&radeon->radeonScreen->bom->tracker, track); + fclose(track); + } +} + +void +radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon, + GLframebuffer *draw) +{ + /* if radeon->fake */ + struct radeon_renderbuffer *rb; + + if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { + + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->frontOffset, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp; + } + if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->backOffset, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->backPitch * rb->cpp; + } + if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->depthOffset, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; + } +} + +static void +radeon_make_renderbuffer_current(radeonContextPtr radeon, + GLframebuffer *draw) +{ + int size = 4096*4096*4; + /* if radeon->fake */ + struct radeon_renderbuffer *rb; + + if (radeon->radeonScreen->kernel_mm) { + radeon_make_kernel_renderbuffer_current(radeon, draw); + return; + } + + + if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->frontOffset + + radeon->radeonScreen->fbLocation, + size, + 4096, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp; + } + if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->backOffset + + radeon->radeonScreen->fbLocation, + size, + 4096, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->backPitch * rb->cpp; + } + if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { + if (!rb->bo) { + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + radeon->radeonScreen->depthOffset + + radeon->radeonScreen->fbLocation, + size, + 4096, + RADEON_GEM_DOMAIN_VRAM, + 0); + } + rb->cpp = radeon->radeonScreen->cpp; + rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp; + } +} + + +void +radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) +{ + unsigned int attachments[10]; + __DRIbuffer *buffers; + __DRIscreen *screen; + struct radeon_renderbuffer *rb; + int i, count; + GLframebuffer *draw; + radeonContextPtr radeon; + + draw = drawable->driverPrivate; + screen = context->driScreenPriv; + radeon = (radeonContextPtr) context->driverPrivate; + i = 0; + if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) { + attachments[i++] = __DRI_BUFFER_FRONT_LEFT; + } + if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) { + attachments[i++] = __DRI_BUFFER_BACK_LEFT; + } + if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) { + attachments[i++] = __DRI_BUFFER_DEPTH; + } + + buffers = (*screen->dri2.loader->getBuffers)(drawable, + &drawable->w, + &drawable->h, + attachments, i, + &count, + drawable->loaderPrivate); + if (buffers == NULL) + return; + + /* set one cliprect to cover the whole drawable */ + drawable->x = 0; + drawable->y = 0; + drawable->backX = 0; + drawable->backY = 0; + drawable->numClipRects = 1; + drawable->pClipRects[0].x1 = 0; + drawable->pClipRects[0].y1 = 0; + drawable->pClipRects[0].x2 = drawable->w; + drawable->pClipRects[0].y2 = drawable->h; + drawable->numBackClipRects = 1; + drawable->pBackClipRects[0].x1 = 0; + drawable->pBackClipRects[0].y1 = 0; + drawable->pBackClipRects[0].x2 = drawable->w; + drawable->pBackClipRects[0].y2 = drawable->h; + for (i = 0; i < count; i++) { + switch (buffers[i].attachment) { + case __DRI_BUFFER_FRONT_LEFT: + rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + if (rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb->cpp = buffers[i].cpp; + rb->pitch = buffers[i].pitch; + rb->width = drawable->w; + rb->height = drawable->h; + rb->has_surface = 0; + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + buffers[i].name, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + buffers[i].flags); + if (rb->bo == NULL) { + fprintf(stderr, "failled to attach front %d\n", + buffers[i].name); + } + break; + case __DRI_BUFFER_BACK_LEFT: + rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb->cpp = buffers[i].cpp; + rb->pitch = buffers[i].pitch; + rb->width = drawable->w; + rb->height = drawable->h; + rb->has_surface = 0; + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + buffers[i].name, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + buffers[i].flags); + break; + case __DRI_BUFFER_DEPTH: + rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb->cpp = buffers[i].cpp; + rb->pitch = buffers[i].pitch; + rb->width = drawable->w; + rb->height = drawable->h; + rb->has_surface = 0; + rb->bo = radeon_bo_open(radeon->radeonScreen->bom, + buffers[i].name, + 0, + 0, + RADEON_GEM_DOMAIN_VRAM, + buffers[i].flags); + break; + case __DRI_BUFFER_STENCIL: + break; + case __DRI_BUFFER_ACCUM: + default: + fprintf(stderr, + "unhandled buffer attach event, attacment type %d\n", + buffers[i].attachment); + return; + } + } + radeon = (radeonContextPtr) context->driverPrivate; + driUpdateFramebufferSize(radeon->glCtx, drawable); +} + +/* Force the context `c' to be the current context and associate with it + * buffer `b'. + */ +GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, + __DRIdrawablePrivate * driDrawPriv, + __DRIdrawablePrivate * driReadPriv) +{ + radeonContextPtr radeon; + GLframebuffer *dfb, *rfb; + + if (!driContextPriv) { + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "%s ctx is null\n", __FUNCTION__); + _mesa_make_current(NULL, NULL, NULL); + return GL_TRUE; + } + radeon = (radeonContextPtr) driContextPriv->driverPrivate; + dfb = driDrawPriv->driverPrivate; + rfb = driReadPriv->driverPrivate; + + if (driContextPriv->driScreenPriv->dri2.enabled) { + radeon_update_renderbuffers(driContextPriv, driDrawPriv); + if (driDrawPriv != driReadPriv) + radeon_update_renderbuffers(driContextPriv, driReadPriv); + radeon->state.color.rrb = + (void *)dfb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + radeon->state.depth.rrb = + (void *)dfb->Attachment[BUFFER_DEPTH].Renderbuffer; + } + + + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "%s ctx %p\n", __FUNCTION__, radeon->glCtx); + + driUpdateFramebufferSize(radeon->glCtx, driDrawPriv); + if (driReadPriv != driDrawPriv) + driUpdateFramebufferSize(radeon->glCtx, driReadPriv); + + if (!driContextPriv->driScreenPriv->dri2.enabled) { + radeon_make_renderbuffer_current(radeon, dfb); + } + + _mesa_make_current(radeon->glCtx, dfb, rfb); + + if (radeon->dri.drawable != driDrawPriv) { + if (driDrawPriv->swap_interval == (unsigned)-1) { + driDrawPriv->vblFlags = + (radeon->radeonScreen->irq != 0) + ? driGetDefaultVBlankFlags(&radeon-> + optionCache) + : VBLANK_FLAG_NO_IRQ; + + driDrawableInitVBlank(driDrawPriv); + } + } + + radeon->dri.readable = driReadPriv; + + if (radeon->dri.drawable != driDrawPriv || + radeon->lastStamp != driDrawPriv->lastStamp) { + radeon->dri.drawable = driDrawPriv; + + radeonSetCliprects(radeon); + radeon->vtbl.update_viewport_offset(radeon->glCtx); + } + + _mesa_update_state(radeon->glCtx); + + if (!driContextPriv->driScreenPriv->dri2.enabled) { + radeonUpdatePageFlipping(radeon); + } + + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "End %s\n", __FUNCTION__); + return GL_TRUE; +} + + +#if defined(USE_X86_ASM) +#define COPY_DWORDS( dst, src, nr ) \ +do { \ + int __tmp; \ + __asm__ __volatile__( "rep ; movsl" \ + : "=%c" (__tmp), "=D" (dst), "=S" (__tmp) \ + : "0" (nr), \ + "D" ((long)dst), \ + "S" ((long)src) ); \ +} while (0) +#else +#define COPY_DWORDS( dst, src, nr ) \ +do { \ + int j; \ + for ( j = 0 ; j < nr ; j++ ) \ + dst[j] = ((int *)src)[j]; \ + dst += nr; \ +} while (0) +#endif + +static void radeonEmitVec4(uint32_t *out, GLvoid * data, int stride, int count) +{ + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); + + if (stride == 4) + COPY_DWORDS(out, data, count); + else + for (i = 0; i < count; i++) { + out[0] = *(int *)data; + out++; + data += stride; + } +} + +static void radeonEmitVec8(uint32_t *out, GLvoid * data, int stride, int count) +{ + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); + + if (stride == 8) + COPY_DWORDS(out, data, count * 2); + else + for (i = 0; i < count; i++) { + out[0] = *(int *)data; + out[1] = *(int *)(data + 4); + out += 2; + data += stride; + } +} + +static void radeonEmitVec12(uint32_t *out, GLvoid * data, int stride, int count) +{ + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); + + if (stride == 12) { + COPY_DWORDS(out, data, count * 3); + } + else + for (i = 0; i < count; i++) { + out[0] = *(int *)data; + out[1] = *(int *)(data + 4); + out[2] = *(int *)(data + 8); + out += 3; + data += stride; + } +} + +static void radeonEmitVec16(uint32_t *out, GLvoid * data, int stride, int count) +{ + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); + + if (stride == 16) + COPY_DWORDS(out, data, count * 4); + else + for (i = 0; i < count; i++) { + out[0] = *(int *)data; + out[1] = *(int *)(data + 4); + out[2] = *(int *)(data + 8); + out[3] = *(int *)(data + 12); + out += 4; + data += stride; + } +} + +void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, + GLvoid * data, int size, int stride, int count) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + uint32_t *out; + uint32_t bo_size; + + memset(aos, 0, sizeof(struct radeon_aos)); + if (stride == 0) { + bo_size = size * 4; + count = 1; + aos->stride = 0; + } else { + bo_size = size * count * 4; + aos->stride = size; + } + aos->bo = radeon_bo_open(rmesa->radeonScreen->bom, + 0, bo_size, 32, RADEON_GEM_DOMAIN_GTT, 0); + aos->offset = 0; + aos->components = size; + aos->count = count; + + radeon_bo_map(aos->bo, 1); + out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); + switch (size) { + case 1: radeonEmitVec4(out, data, stride, count); break; + case 2: radeonEmitVec8(out, data, stride, count); break; + case 3: radeonEmitVec12(out, data, stride, count); break; + case 4: radeonEmitVec16(out, data, stride, count); break; + default: + assert(0); + break; + } + radeon_bo_unmap(aos->bo); +} diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h index d7161c4b96..32cbae7ad3 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.h +++ b/src/mesa/drivers/dri/radeon/common_misc.h @@ -18,4 +18,18 @@ void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, void radeonUpdatePageFlipping(radeonContextPtr rmesa); +GLboolean radeonInitContext(radeonContextPtr radeon, + struct dd_function_table* functions, + const __GLcontextModes * glVisual, + __DRIcontextPrivate * driContextPriv, + void *sharedContextPrivate); + +void radeonCleanupContext(radeonContextPtr radeon); +void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable); +GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, + __DRIdrawablePrivate * driDrawPriv, + __DRIdrawablePrivate * driReadPriv); + +void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, + GLvoid * data, int size, int stride, int count); #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index c7adf4975b..b87275c56b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -527,6 +527,7 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) radeonFlushCmdBuf( rmesa, __FUNCTION__ ); } + radeonCleanupContext(&rmesa->radeon); _mesa_vector4f_free( &rmesa->tcl.ObjClean ); if (rmesa->radeon.state.scissor.pClipRects) { @@ -548,65 +549,12 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) assert( is_empty_list( & rmesa->radeon.swapped ) ); } - /* free the Mesa context */ - rmesa->radeon.glCtx->DriverCtx = NULL; - _mesa_destroy_context( rmesa->radeon.glCtx ); - - /* free the option cache */ - driDestroyOptionCache (&rmesa->radeon.optionCache); + radeonCleanupContext(&rmesa->radeon); FREE( rmesa ); } } -/* Make context `c' the current context and bind it to the given - * drawing and reading surfaces. - */ -GLboolean -radeonMakeCurrent( __DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv ) -{ - if ( driContextPriv ) { - radeonContextPtr newCtx = - (radeonContextPtr) driContextPriv->driverPrivate; - - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) newCtx->glCtx); - - newCtx->dri.readable = driReadPriv; - - if ( (newCtx->dri.drawable != driDrawPriv) || - newCtx->lastStamp != driDrawPriv->lastStamp ) { - if (driDrawPriv->swap_interval == (unsigned)-1) { - driDrawPriv->vblFlags = (newCtx->radeonScreen->irq != 0) - ? driGetDefaultVBlankFlags(&newCtx->optionCache) - : VBLANK_FLAG_NO_IRQ; - - driDrawableInitVBlank( driDrawPriv ); - } - - newCtx->dri.drawable = driDrawPriv; - - radeonSetCliprects(newCtx); - radeonUpdateViewportOffset( newCtx->glCtx ); - } - - _mesa_make_current( newCtx->glCtx, - (GLframebuffer *) driDrawPriv->driverPrivate, - (GLframebuffer *) driReadPriv->driverPrivate ); - - _mesa_update_state( newCtx->glCtx ); - } else { - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx is null\n", __FUNCTION__); - _mesa_make_current( NULL, NULL, NULL ); - } - - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "End %s\n", __FUNCTION__); - return GL_TRUE; -} /* Force the context `c' to be unbound from its buffer. */ diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 0b6791f54c..320bf9244b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -76,6 +76,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_bo_legacy.h" #include "radeon_bo_gem.h" +#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ +DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ + DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ + DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ +DRI_CONF_OPT_END + #if !RADEON_COMMON /* R100 */ PUBLIC const char __driConfigOptions[] = DRI_CONF_BEGIN @@ -85,6 +91,7 @@ DRI_CONF_BEGIN DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) DRI_CONF_HYPERZ(false) + DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) DRI_CONF_SECTION_END DRI_CONF_SECTION_QUALITY DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) @@ -100,7 +107,7 @@ DRI_CONF_BEGIN DRI_CONF_NO_RAST(false) DRI_CONF_SECTION_END DRI_CONF_END; -static const GLuint __driNConfigOptions = 14; +static const GLuint __driNConfigOptions = 15; #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) @@ -112,6 +119,7 @@ DRI_CONF_BEGIN DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) DRI_CONF_HYPERZ(false) + DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) DRI_CONF_SECTION_END DRI_CONF_SECTION_QUALITY DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) @@ -131,7 +139,7 @@ DRI_CONF_BEGIN DRI_CONF_NV_VERTEX_PROGRAM(false) DRI_CONF_SECTION_END DRI_CONF_END; -static const GLuint __driNConfigOptions = 16; +static const GLuint __driNConfigOptions = 17; extern const struct dri_extension blend_extensions[]; extern const struct dri_extension ARB_vp_extension[]; @@ -154,11 +162,7 @@ DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ DRI_CONF_OPT_END -#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ -DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ - DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ - DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ -DRI_CONF_OPT_END + #define DRI_CONF_DISABLE_S3TC(def) \ DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ @@ -1152,7 +1156,6 @@ radeonInitDriver( __DRIscreenPrivate *sPriv ) return GL_TRUE; } -#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) static GLboolean radeon_alloc_window_storage(GLcontext *ctx, struct gl_renderbuffer *rb, GLenum intFormat, GLuint w, GLuint h) @@ -1308,107 +1311,6 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, return (driDrawPriv->driverPrivate != NULL); } -#else - -/** - * Create the Mesa framebuffer and renderbuffers for a given window/drawable. - * - * \todo This function (and its interface) will need to be updated to support - * pbuffers. - */ -static GLboolean -radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, - __DRIdrawablePrivate *driDrawPriv, - const __GLcontextModes *mesaVis, - GLboolean isPixmap ) -{ - radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; - - if (isPixmap) { - return GL_FALSE; /* not implemented */ - } - else { - const GLboolean swDepth = GL_FALSE; - const GLboolean swAlpha = GL_FALSE; - const GLboolean swAccum = mesaVis->accumRedBits > 0; - const GLboolean swStencil = mesaVis->stencilBits > 0 && - mesaVis->depthBits != 24; - struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis); - - /* front color renderbuffer */ - { - driRenderbuffer *frontRb - = driNewRenderbuffer(GL_RGBA, - driScrnPriv->pFB + screen->frontOffset, - screen->cpp, - screen->frontOffset, screen->frontPitch, - driDrawPriv); - radeonSetSpanFunctions(frontRb, mesaVis); - _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base); - } - - /* back color renderbuffer */ - if (mesaVis->doubleBufferMode) { - driRenderbuffer *backRb - = driNewRenderbuffer(GL_RGBA, - driScrnPriv->pFB + screen->backOffset, - screen->cpp, - screen->backOffset, screen->backPitch, - driDrawPriv); - radeonSetSpanFunctions(backRb, mesaVis); - _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base); - } - - /* depth renderbuffer */ - if (mesaVis->depthBits == 16) { - driRenderbuffer *depthRb - = driNewRenderbuffer(GL_DEPTH_COMPONENT16, - driScrnPriv->pFB + screen->depthOffset, - screen->cpp, - screen->depthOffset, screen->depthPitch, - driDrawPriv); - radeonSetSpanFunctions(depthRb, mesaVis); - _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); - // depthRb->has_surface = screen->depthHasSurface; - } - else if (mesaVis->depthBits == 24) { - driRenderbuffer *depthRb - = driNewRenderbuffer(GL_DEPTH_COMPONENT24, - driScrnPriv->pFB + screen->depthOffset, - screen->cpp, - screen->depthOffset, screen->depthPitch, - driDrawPriv); - radeonSetSpanFunctions(depthRb, mesaVis); - _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); - // depthRb->has_surface = screen->depthHasSurface; - } - - /* stencil renderbuffer */ - if (mesaVis->stencilBits > 0 && !swStencil) { - driRenderbuffer *stencilRb - = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT, - driScrnPriv->pFB + screen->depthOffset, - screen->cpp, - screen->depthOffset, screen->depthPitch, - driDrawPriv); - radeonSetSpanFunctions(stencilRb, mesaVis); - _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base); - //stencilRb->has_surface = screen->depthHasSurface; - } - - _mesa_add_soft_renderbuffers(fb, - GL_FALSE, /* color */ - swDepth, - swStencil, - swAccum, - swAlpha, - GL_FALSE /* aux */); - driDrawPriv->driverPrivate = (void *) fb; - - return (driDrawPriv->driverPrivate != NULL); - } -} -#endif static void radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) @@ -1621,7 +1523,7 @@ const struct __DriverAPIRec driDriverAPI = { .CreateBuffer = radeonCreateBuffer, .DestroyBuffer = radeonDestroyBuffer, .SwapBuffers = radeonSwapBuffers, - .MakeCurrent = r200MakeCurrent, + .MakeCurrent = radeonMakeCurrent, .UnbindContext = r200UnbindContext, .GetSwapInfo = getSwapInfo, .GetDrawableMSC = driDrawableGetMSC32, diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 423f3ca7e3..a850baea29 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -308,20 +308,17 @@ void radeonInitSpanFuncs(GLcontext * ctx) /** * Plug in the Get/Put routines for the given driRenderbuffer. */ -void radeonSetSpanFunctions(driRenderbuffer * drb, const GLvisual * vis) +void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb) { - if (drb->Base.InternalFormat == GL_RGBA) { - if (vis->redBits == 5 && vis->greenBits == 6 - && vis->blueBits == 5) { - radeonInitPointers_RGB565(&drb->Base); - } else { - radeonInitPointers_ARGB8888(&drb->Base); - } - } else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) { - radeonInitDepthPointers_z16(&drb->Base); - } else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) { - radeonInitDepthPointers_z24_s8(&drb->Base); - } else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) { - radeonInitStencilPointers_z24_s8(&drb->Base); + if (rrb->base.InternalFormat == GL_RGB5) { + radeonInitPointers_RGB565(&rrb->base); + } else if (rrb->base.InternalFormat == GL_RGBA8) { + radeonInitPointers_ARGB8888(&rrb->base); + } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT16) { + radeonInitDepthPointers_z16(&rrb->base); + } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT24) { + radeonInitDepthPointers_z24_s8(&rrb->base); + } else if (rrb->base.InternalFormat == GL_STENCIL_INDEX8_EXT) { + radeonInitStencilPointers_z24_s8(&rrb->base); } } diff --git a/src/mesa/drivers/dri/radeon/radeon_span.h b/src/mesa/drivers/dri/radeon/radeon_span.h index 1650a9bea9..93d7630310 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.h +++ b/src/mesa/drivers/dri/radeon/radeon_span.h @@ -48,9 +48,5 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. extern void radeonInitSpanFuncs(GLcontext * ctx); -#if COMPILE_R300 extern void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb); -#else -extern void radeonSetSpanFunctions(driRenderbuffer * rb, const GLvisual * vis); -#endif #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 67f861a48e..0c9fb14857 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -1404,8 +1404,8 @@ void radeonUpdateWindow( GLcontext *ctx ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; - GLfloat xoffset = (GLfloat)dPriv->x; - GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h; + GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; + GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; const GLfloat *v = ctx->Viewport._WindowMap.m; float_ui32_type sx = { v[MAT_SX] }; -- cgit v1.2.3 From d9c4a01bad3a7d4a965fc09d8605afc6ca48f6f9 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 21 Jan 2009 01:40:33 +1000 Subject: r200: make tri render on my r200. --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 28 ++++-------- src/mesa/drivers/dri/r200/r200_ioctl.c | 6 ++- src/mesa/drivers/dri/r200/r200_ioctl.h | 27 ++++------- src/mesa/drivers/dri/r200/r200_maos_arrays.c | 18 ++++---- src/mesa/drivers/dri/r200/r200_state_init.c | 62 +++++++++++++++++++++----- src/mesa/drivers/dri/r200/r200_tcl.c | 2 + src/mesa/drivers/dri/r300/r300_ioctl.c | 4 +- src/mesa/drivers/dri/r300/r300_state.c | 2 +- src/mesa/drivers/dri/radeon/common_lock.c | 13 ------ src/mesa/drivers/dri/radeon/common_misc.c | 13 ++++++ src/mesa/drivers/dri/radeon/common_misc.h | 1 + src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 47 +++++++++++-------- 12 files changed, 129 insertions(+), 94 deletions(-) (limited to 'src/mesa/drivers/dri/r200/r200_tcl.c') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index f107ff5624..6d421f5d5e 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -47,17 +47,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r200_sanity.h" #include "radeon_reg.h" -static void print_state_atom( struct radeon_state_atom *state ) -{ - int i; - - fprintf(stderr, "emit %s/%d\n", state->name, state->cmd_size); - - if (0 & R200_DEBUG & DEBUG_VERBOSE) - for (i = 0 ; i < state->cmd_size ; i++) - fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]); - -} +#define DEBUG_CMDBUF 0 /* The state atoms will be emitted in the order they appear in the atom list, * so this step is important. @@ -141,7 +131,7 @@ static void r200SaveHwState( r200ContextPtr rmesa ) rmesa->backup_store.cmd_used += size; } if (R200_DEBUG & DEBUG_STATE) - print_state_atom( atom ); + radeon_print_state_atom( atom ); } } @@ -161,9 +151,9 @@ static INLINE void r200EmitAtoms(r200ContextPtr r200, GLboolean dirty) if ((atom->dirty || r200->hw.all_dirty) == dirty) { dwords = (*atom->check) (r200->radeon.glCtx, atom); if (dwords) { - // if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { - // r300PrintStateAtom(r300, atom); - // } + if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { + radeon_print_state_atom(atom); + } if (atom->emit) { (*atom->emit)(r200->radeon.glCtx, atom); } else { @@ -173,10 +163,10 @@ static INLINE void r200EmitAtoms(r200ContextPtr r200, GLboolean dirty) } atom->dirty = GL_FALSE; } else { - // if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { - // fprintf(stderr, " skip state %s\n", - // atom->name); - // } + if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { + fprintf(stderr, " skip state %s\n", + atom->name); + } } } } diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index 1bb97c5002..1fbbbfbb56 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -41,7 +41,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/context.h" #include "swrast/swrast.h" +#include "radeon_cs.h" #include "r200_context.h" + #include "common_cmdbuf.h" #include "r200_state.h" #include "r200_ioctl.h" @@ -525,8 +527,8 @@ void r200Flush( GLcontext *ctx ) rmesa->dma.flush( ctx ); r200EmitState( rmesa ); - - if (rmesa->store.cmd_used) + + if (rmesa->radeon.cmdbuf.cs->cdw) rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); } diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index f36a6fd90f..1ae0dd114b 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -201,40 +201,31 @@ static INLINE char *r200AllocCmdBuf( r200ContextPtr rmesa, } #endif -static inline uint32_t cmdpacket3_clip(int cmd_type) +static inline uint32_t cmdpacket3(int cmd_type) { drm_radeon_cmd_header_t cmd; cmd.i = 0; - cmd.header.cmd_type = RADEON_CMD_PACKET3_CLIP; + cmd.header.cmd_type = cmd_type; return (uint32_t)cmd.i; } -#define OUT_BATCH_PACKET3_CLIP(packet, num_extra) do { \ + +#define OUT_BATCH_PACKET3(packet, num_extra) do { \ if (!b_l_rmesa->radeonScreen->kernel_mm) { \ - OUT_BATCH(cmdpacket3_clip(0)); \ - OUT_BATCH(packet); \ + OUT_BATCH(cmdpacket3(RADEON_CMD_PACKET3)); \ + OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ } else { \ OUT_BATCH(CP_PACKET2); \ OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ } \ } while(0) -static inline uint32_t cmdpacket3(int cmd_type) -{ - drm_radeon_cmd_header_t cmd; - - cmd.i = 0; - cmd.header.cmd_type = RADEON_CMD_PACKET3; - - return (uint32_t)cmd.i; - -} -#define OUT_BATCH_PACKET3(packet, num_extra) do { \ +#define OUT_BATCH_PACKET3_CLIP(packet, num_extra) do { \ if (!b_l_rmesa->radeonScreen->kernel_mm) { \ - OUT_BATCH(cmdpacket3(0)); \ - OUT_BATCH(packet); \ + OUT_BATCH(cmdpacket3(RADEON_CMD_PACKET3_CLIP)); \ + OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ } else { \ OUT_BATCH(CP_PACKET2); \ OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c index c3c2b973b5..7f7ae2ba79 100644 --- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c +++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c @@ -223,6 +223,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) GLuint count = VB->Count; GLuint i, emitsize; + fprintf(stderr,"emit arrays\n"); for ( i = 0; i < 15; i++ ) { GLubyte attrib = vimap_rev[i]; if (attrib != 255) { @@ -257,14 +258,14 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) if (!rmesa->tcl.vertex_data[i].buf) { if (ctx->VertexProgram._Enabled) rcommon_emit_vector( ctx, - &(rmesa->tcl.aos[i]), + &(rmesa->tcl.aos[nr]), (char *)VB->AttribPtr[attrib]->data, 1, VB->AttribPtr[attrib]->stride, count); else r200_emit_vecfog( ctx, - &(rmesa->tcl.aos[i]), + &(rmesa->tcl.aos[nr]), (char *)VB->AttribPtr[attrib]->data, VB->AttribPtr[attrib]->stride, count); @@ -313,7 +314,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) } if (!rmesa->tcl.vertex_data[i].buf) { rcommon_emit_vector( ctx, - &(rmesa->tcl.aos[i]), + &(rmesa->tcl.aos[nr]), (char *)VB->AttribPtr[attrib]->data, emitsize, VB->AttribPtr[attrib]->stride, @@ -321,6 +322,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) } after_emit: assert(nr < 12); + nr++; // component[nr++] = &rmesa->tcl.vertex_data[i]; } } @@ -339,12 +341,10 @@ after_emit: void r200ReleaseArrays( GLcontext *ctx, GLuint newinputs ) { r200ContextPtr rmesa = R200_CONTEXT( ctx ); - - /* only do it for changed inputs ? */ int i; - for (i = 0; i < 15; i++) { - // if (newinputs & (1 << i)) - // r200ReleaseDmaRegion( rmesa, - // &rmesa->tcl.vertex_data[i], __FUNCTION__ ); + for (i = 0; i < rmesa->tcl.nr_aos_components; i++) { + if (rmesa->tcl.aos[i].bo) { + rmesa->tcl.aos[i].bo = radeon_bo_unref(rmesa->tcl.aos[i].bo); + } } } diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index f46b01b56a..3b56fec78a 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -43,6 +43,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/t_pipeline.h" #include "swrast_setup/swrast_setup.h" +#include "radeon_buffer.h" +#include "radeon_cs.h" +#include "common_context.h" +#include "common_cmdbuf.h" #include "r200_context.h" #include "r200_ioctl.h" #include "r200_state.h" @@ -288,32 +292,66 @@ VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96 ) -#if 0 -static int ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) +static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) { r200ContextPtr r200 = R200_CONTEXT(ctx); BATCH_LOCALS(&r200->radeon); struct radeon_renderbuffer *rrb; uint32_t cbpitch; + uint32_t zbpitch; + uint32_t dwords = atom->cmd_size; GLframebuffer *fb = r200->radeon.dri.drawable->driverPrivate; - + + /* output the first 7 bytes of context */ + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_BATCH_TABLE(atom->cmd, 5); + + rrb = r200->radeon.state.depth.rrb; + if (!rrb) { + OUT_BATCH(atom->cmd[CTX_RB3D_DEPTHOFFSET]); + OUT_BATCH(atom->cmd[CTX_RB3D_DEPTHPITCH]); + } else { + zbpitch = (rrb->pitch / rrb->cpp); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); + OUT_BATCH(zbpitch); + } + + OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); + OUT_BATCH(atom->cmd[CTX_CMD_1]); + OUT_BATCH(atom->cmd[CTX_PP_CNTL]); + OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); + rrb = r200->radeon.state.color.rrb; if (r200->radeon.radeonScreen->driScreen->dri2.enabled) { rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; } if (!rrb || !rrb->bo) { - fprintf(stderr, "no rrb\n"); - return; + OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]); + } else { + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); } - cbpitch = (rrb->pitch / rrb->cpp); - if (rrb->cpp == 4) - ; - else - ; + OUT_BATCH(atom->cmd[CTX_CMD_2]); + + if (!rrb || !rrb->bo) { + OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]); + } else { + cbpitch = (rrb->pitch / rrb->cpp); + if (rrb->cpp == 4) + ; + else + ; + if (r200->radeon.sarea->tiling_enabled) + cbpitch |= R200_COLOR_TILE_ENABLE; + OUT_BATCH(cbpitch); + } + + if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) + OUT_BATCH_TABLE((atom->cmd + 14), 4); + + END_BATCH(); } -#endif static int tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) { @@ -410,7 +448,7 @@ void r200InitState( r200ContextPtr rmesa ) else ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 ); - // rmesa->hw.ctx.emit = ctx_emit; + rmesa->hw.ctx.emit = ctx_emit; ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 ); ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 4a31578c89..226bf1620c 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -142,6 +142,7 @@ static GLboolean discrete_prim[0x10] = { static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) { + fprintf(stderr,"alloc elts\n"); if (rmesa->dma.flush == r200FlushElts && rmesa->store.cmd_used + nr*2 < R200_CMD_BUF_SZ) { @@ -187,6 +188,7 @@ static void r200EmitPrim( GLcontext *ctx, r200ContextPtr rmesa = R200_CONTEXT( ctx ); r200TclPrimitive( ctx, prim, hwprim ); + fprintf(stderr,"Emit prim %d\n", rmesa->tcl.nr_aos_components); rcommonEnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + rmesa->hw.max_state_size + VBUF_BUFSZ ); diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index 02c4b1cb40..eb50037911 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -68,7 +68,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. static void r300ClearBuffer(r300ContextPtr r300, int flags, struct radeon_renderbuffer *rrb, - struct radeon_renderbuffer *rrbd) + struct radeon_renderbuffer *rrbd) { BATCH_LOCALS(&r300->radeon); GLcontext *ctx = r300->radeon.glCtx; @@ -592,7 +592,7 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) rcommonEnsureCmdBufSpace(&r300->radeon, 421 * 3, __FUNCTION__); if (flags || bits) r300EmitClearState(ctx); - rrbd = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; + rrbd = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; if (flags & BUFFER_BIT_FRONT_LEFT) { rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index d98b83c506..b1048f3b0c 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -2362,7 +2362,7 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff; rrb = r300->radeon.state.depth.rrb; - if (rrb && rrb->bo && (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)) { + if (rrb && rrb->bo && (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)) { /* XXX: Turn off when clearing buffers ? */ r300->hw.zb.cmd[R300_ZB_PITCH] |= R300_DEPTHMACROTILE_ENABLE; diff --git a/src/mesa/drivers/dri/radeon/common_lock.c b/src/mesa/drivers/dri/radeon/common_lock.c index 09517450a9..91600ac4cd 100644 --- a/src/mesa/drivers/dri/radeon/common_lock.c +++ b/src/mesa/drivers/dri/radeon/common_lock.c @@ -55,7 +55,6 @@ char *prevLockFile = NULL; int prevLockLine = 0; #endif -#ifdef RADEON_COMMON_FOR_R300 /* Turn on/off page flipping according to the flags in the sarea: */ void radeonUpdatePageFlipping(radeonContextPtr rmesa) @@ -81,18 +80,6 @@ void radeonUpdatePageFlipping(radeonContextPtr rmesa) rmesa->state.depth.rrb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; } -#else -/* Turn on/off page flipping according to the flags in the sarea: - */ -void radeonUpdatePageFlipping(radeonContextPtr rmesa) -{ - rmesa->doPageFlip = rmesa->sarea->pfState; - if (rmesa->glCtx->WinSysDrawBuffer) { - driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer, - rmesa->sarea->pfCurrentPage); - } -} -#endif /* Update the hardware state. This is called if another context has * grabbed the hardware lock, which includes the X server. This diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 51cbe59024..d7c16c4957 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -1337,3 +1337,16 @@ void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, } radeon_bo_unmap(aos->bo); } + + +void radeon_print_state_atom( struct radeon_state_atom *state ) +{ + int i; + + fprintf(stderr, "emit %s/%d\n", state->name, state->cmd_size); + + if (RADEON_DEBUG & DEBUG_VERBOSE) + for (i = 0 ; i < state->cmd_size ; i++) + fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]); + +} diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h index 32cbae7ad3..e4f200d6a5 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.h +++ b/src/mesa/drivers/dri/radeon/common_misc.h @@ -32,4 +32,5 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, GLvoid * data, int size, int stride, int count); +void radeon_print_state_atom( struct radeon_state_atom *state ); #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index 0c897815a7..af9ee4df47 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -206,8 +206,8 @@ static int cs_end(struct radeon_cs *cs, } cs->section = 0; if (cs->section_ndw != cs->section_cdw) { - fprintf(stderr, "CS section size missmatch start at (%s,%s,%d)\n", - cs->section_file, cs->section_func, cs->section_line); + fprintf(stderr, "CS section size missmatch start at (%s,%s,%d) %d vs %d\n", + cs->section_file, cs->section_func, cs->section_line, cs->section_ndw, cs->section_cdw); fprintf(stderr, "CS section end at (%s,%s,%d)\n", file, func, line); return -EPIPE; @@ -221,10 +221,6 @@ static int cs_process_relocs(struct radeon_cs *cs) struct cs_reloc_legacy *relocs; int i, j, r; - if (!IS_R300_CLASS(csm->ctx->radeonScreen)) { - /* FIXME: r300 only right now */ - return -EINVAL; - } csm = (struct cs_manager_legacy*)cs->csm; relocs = (struct cs_reloc_legacy *)cs->relocs; for (i = 0; i < cs->crelocs; i++) { @@ -238,6 +234,8 @@ static int cs_process_relocs(struct radeon_cs *cs) relocs[i].base.bo, soffset, eoffset); return r; } + fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", + relocs[i].base.bo, soffset, eoffset); cs->packets[relocs[i].indices[j]] += soffset; if (cs->packets[relocs[i].indices[j]] >= eoffset) { radeon_bo_debug(relocs[i].base.bo, 12); @@ -269,6 +267,14 @@ static int cs_set_age(struct radeon_cs *cs) return 0; } +static void dump_cmdbuf(struct radeon_cs *cs) +{ + int i; + for (i = 0; i < cs->cdw; i++){ + fprintf(stderr,"%x: %08x\n", i, cs->packets[i]); + } + +} static int cs_emit(struct radeon_cs *cs) { struct cs_manager_legacy *csm = (struct cs_manager_legacy*)cs->csm; @@ -279,19 +285,22 @@ static int cs_emit(struct radeon_cs *cs) csm->ctx->vtbl.emit_cs_header(cs, csm->ctx); + /* append buffer age */ - age.scratch.cmd_type = R300_CMD_SCRATCH; - /* Scratch register 2 corresponds to what radeonGetAge polls */ - csm->pending_age = 0; - csm->pending_count = 1; - ull = (uint64_t) (intptr_t) &csm->pending_age; - age.scratch.reg = 2; - age.scratch.n_bufs = 1; - age.scratch.flags = 0; - radeon_cs_write_dword(cs, age.u); - radeon_cs_write_dword(cs, ull & 0xffffffff); - radeon_cs_write_dword(cs, ull >> 32); - radeon_cs_write_dword(cs, 0); + if (IS_R300_CLASS(csm->ctx->radeonScreen)) { + age.scratch.cmd_type = R300_CMD_SCRATCH; + /* Scratch register 2 corresponds to what radeonGetAge polls */ + csm->pending_age = 0; + csm->pending_count = 1; + ull = (uint64_t) (intptr_t) &csm->pending_age; + age.scratch.reg = 2; + age.scratch.n_bufs = 1; + age.scratch.flags = 0; + radeon_cs_write_dword(cs, age.u); + radeon_cs_write_dword(cs, ull & 0xffffffff); + radeon_cs_write_dword(cs, ull >> 32); + radeon_cs_write_dword(cs, 0); + } r = cs_process_relocs(cs); if (r) { @@ -308,6 +317,8 @@ static int cs_emit(struct radeon_cs *cs) cmd.boxes = (drm_clip_rect_t *) csm->ctx->pClipRects; } + dump_cmdbuf(cs); + r = drmCommandWrite(cs->csm->fd, DRM_RADEON_CMDBUF, &cmd, sizeof(cmd)); if (r) { return r; -- cgit v1.2.3 From 0788e424713a2b71cceee60bcd21c79a2896b3bd Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 22 Jan 2009 02:38:00 +1000 Subject: r200: remove indexed verts --- src/mesa/drivers/dri/r200/r200_context.h | 2 -- src/mesa/drivers/dri/r200/r200_swtcl.c | 2 -- src/mesa/drivers/dri/r200/r200_swtcl.h | 4 ---- src/mesa/drivers/dri/r200/r200_tcl.c | 4 ---- 4 files changed, 12 deletions(-) (limited to 'src/mesa/drivers/dri/r200/r200_tcl.c') diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 5ecf797999..2725dc495f 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -544,7 +544,6 @@ struct r200_tcl_info { GLuint *Elts; - struct radeon_dma_region indexed_verts; struct radeon_dma_region vertex_data[15]; }; @@ -603,7 +602,6 @@ struct r200_swtcl_info { struct radeon_bo *bo; void (*flush) (r200ContextPtr); - struct radeon_dma_region indexed_verts; }; diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index 0be772d015..7275886f84 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -954,6 +954,4 @@ void r200DestroySwtcl( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - // if (rmesa->swtcl.indexed_verts.buf) - // r200ReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, __FUNCTION__ ); } diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.h b/src/mesa/drivers/dri/r200/r200_swtcl.h index 0c25d8bc83..91c7c0ff8f 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.h +++ b/src/mesa/drivers/dri/r200/r200_swtcl.h @@ -52,10 +52,6 @@ extern void r200BuildVertices( GLcontext *ctx, GLuint start, GLuint count, extern void r200PrintSetupFlags(char *msg, GLuint flags ); -extern void r200_emit_indexed_verts( GLcontext *ctx, - GLuint start, - GLuint count ); - extern void r200_translate_vertex( GLcontext *ctx, const radeonVertex *src, SWvertex *dst ); diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 226bf1620c..0f15fd457e 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -570,10 +570,6 @@ static void transition_to_hwtnl( GLcontext *ctx ) rmesa->dma.flush = NULL; - // if (rmesa->swtcl.indexed_verts.buf) - // r200ReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, - // __FUNCTION__ ); - R200_STATECHANGE( rmesa, vap ); rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] |= R200_VAP_TCL_ENABLE; rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] &= ~R200_VAP_FORCE_W_TO_ONE; -- cgit v1.2.3 From 7d01cb37d94b8966fa089106b902325dbef33a58 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 23 Jan 2009 00:17:38 +1000 Subject: r200: emit elts into a separate ELT bo --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 209 ++++++++------------------ src/mesa/drivers/dri/r200/r200_context.h | 7 +- src/mesa/drivers/dri/r200/r200_ioctl.c | 249 +------------------------------ src/mesa/drivers/dri/r200/r200_ioctl.h | 3 +- src/mesa/drivers/dri/r200/r200_pixel.c | 10 +- src/mesa/drivers/dri/r200/r200_tcl.c | 19 ++- 6 files changed, 89 insertions(+), 408 deletions(-) (limited to 'src/mesa/drivers/dri/r200/r200_tcl.c') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index 6d421f5d5e..5768f39e5c 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -238,40 +238,61 @@ void r200EmitVbufPrim( r200ContextPtr rmesa, OUT_BATCH(primitive | R200_VF_PRIM_WALK_LIST | R200_VF_COLOR_ORDER_RGBA | (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT)); END_BATCH(); -#if 0 - cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, VBUF_BUFSZ, - __FUNCTION__ ); - cmd[0].i = 0; - cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP; - cmd[1].i = R200_CP_CMD_3D_DRAW_VBUF_2; - cmd[2].i = (primitive | - R200_VF_PRIM_WALK_LIST | - R200_VF_COLOR_ORDER_RGBA | - (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT)); -#endif } +static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type) +{ + BATCH_LOCALS(&rmesa->radeon); + + if (vertex_count > 0) { + BEGIN_BATCH(8); + OUT_BATCH_PACKET3(R200_CP_CMD_3D_DRAW_INDX_2, 0); + OUT_BATCH(R200_VF_PRIM_WALK_IND | + ((vertex_count + 0) << 16) | + type); + + if (!rmesa->radeon.radeonScreen->kernel_mm) { + OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2); + OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810); + OUT_BATCH_RELOC(rmesa->tcl.elt_dma_offset, + rmesa->tcl.elt_dma_bo, + rmesa->tcl.elt_dma_offset, + RADEON_GEM_DOMAIN_GTT, 0, 0); + OUT_BATCH(vertex_count/2); + } else { + OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2); + OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810); + OUT_BATCH(rmesa->tcl.elt_dma_offset); + OUT_BATCH(vertex_count/2); + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->tcl.elt_dma_bo, + RADEON_GEM_DOMAIN_GTT, 0, 0); + } + END_BATCH(); + } +} -void r200FlushElts( GLcontext *ctx ) +void r200FlushElts( r200ContextPtr rmesa ) { - r200ContextPtr rmesa = R200_CONTEXT(ctx); - int *cmd = (int *)(rmesa->store.cmd_buf + rmesa->store.elts_start); int dwords; - int nr = (rmesa->store.cmd_used - (rmesa->store.elts_start + 12)) / 2; + int nr, elt_used = rmesa->tcl.elt_used; if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS)) - fprintf(stderr, "%s\n", __FUNCTION__); + fprintf(stderr, "%s %x %d\n", __FUNCTION__, rmesa->tcl.hw_primitive, elt_used); - assert( rmesa->dma.flush == r200FlushElts ); - rmesa->dma.flush = NULL; + assert( rmesa->tcl.flush == r200FlushElts ); + rmesa->tcl.flush = NULL; - /* Cope with odd number of elts: - */ - rmesa->store.cmd_used = (rmesa->store.cmd_used + 2) & ~2; - dwords = (rmesa->store.cmd_used - rmesa->store.elts_start) / 4; + elt_used = (elt_used + 2) & ~2; - cmd[1] |= (dwords - 3) << 16; - cmd[2] |= nr << R200_VF_VERTEX_NUMBER_SHIFT; + nr = elt_used / 2; + + radeon_bo_unmap(rmesa->tcl.elt_dma_bo); + + r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive); + + radeon_bo_unref(rmesa->tcl.elt_dma_bo); + rmesa->tcl.elt_dma_bo = NULL; if (R200_DEBUG & DEBUG_SYNC) { fprintf(stderr, "%s: Syncing\n", __FUNCTION__); @@ -284,7 +305,6 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, GLuint primitive, GLuint min_nr ) { - drm_radeon_cmd_header_t *cmd; GLushort *retval; if (R200_DEBUG & DEBUG_IOCTL) @@ -293,29 +313,24 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, assert((primitive & R200_VF_PRIM_WALK_IND)); r200EmitState( rmesa ); - - // cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, ELTS_BUFSZ(min_nr), - // __FUNCTION__ ); - cmd[0].i = 0; - cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP; - cmd[1].i = R200_CP_CMD_3D_DRAW_INDX_2; - cmd[2].i = (primitive | - R200_VF_PRIM_WALK_IND | - R200_VF_COLOR_ORDER_RGBA); + rmesa->tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, + 0, R200_ELT_BUF_SZ, 4, + RADEON_GEM_DOMAIN_GTT, 0); + rmesa->tcl.elt_dma_offset = 0; + rmesa->tcl.elt_used = min_nr * 2; + + radeon_bo_map(rmesa->tcl.elt_dma_bo, 1); + retval = rmesa->tcl.elt_dma_bo->ptr + rmesa->tcl.elt_dma_offset; - retval = (GLushort *)(cmd+3); if (R200_DEBUG & DEBUG_PRIMS) - fprintf(stderr, "%s: header 0x%x prim %x \n", - __FUNCTION__, - cmd[1].i, primitive); + fprintf(stderr, "%s: header prim %x \n", + __FUNCTION__, primitive); - assert(!rmesa->dma.flush); + assert(!rmesa->tcl.flush); rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->dma.flush = r200FlushElts; - - rmesa->store.elts_start = ((char *)cmd) - rmesa->store.cmd_buf; + rmesa->tcl.flush = r200FlushElts; return retval; } @@ -439,112 +454,14 @@ void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset) } END_BATCH(); } - -#if 0 -void r200EmitAOS( r200ContextPtr rmesa, - struct radeon_dma_region **component, - GLuint nr, - GLuint offset ) -{ - drm_radeon_cmd_header_t *cmd; - int sz = AOS_BUFSZ(nr); - int i; - int *tmp; - if (R200_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s nr arrays: %d\n", __FUNCTION__, nr); - - cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, sz, __FUNCTION__ ); - cmd[0].i = 0; - cmd[0].header.cmd_type = RADEON_CMD_PACKET3; - cmd[1].i = R200_CP_CMD_3D_LOAD_VBPNTR | (((sz / sizeof(int)) - 3) << 16); - cmd[2].i = nr; - tmp = &cmd[0].i; - cmd += 3; - - for (i = 0 ; i < nr ; i++) { - if (i & 1) { - cmd[0].i |= ((component[i]->aos_stride << 24) | - (component[i]->aos_size << 16)); - cmd[2].i = (component[i]->aos_start + - offset * component[i]->aos_stride * 4); - cmd += 3; - } - else { - cmd[0].i = ((component[i]->aos_stride << 8) | - (component[i]->aos_size << 0)); - cmd[1].i = (component[i]->aos_start + - offset * component[i]->aos_stride * 4); - } - } - - if (R200_DEBUG & DEBUG_VERTS) { - fprintf(stderr, "%s:\n", __FUNCTION__); - for (i = 0 ; i < sz ; i++) - fprintf(stderr, " %d: %x\n", i, tmp[i]); - } -} -#endif - -void r200EmitBlit( r200ContextPtr rmesa, - GLuint color_fmt, - GLuint src_pitch, - GLuint src_offset, - GLuint dst_pitch, - GLuint dst_offset, - GLint srcx, GLint srcy, - GLint dstx, GLint dsty, - GLuint w, GLuint h ) +void r200FireAOS(r200ContextPtr rmesa, int vertex_count, int type) { - drm_radeon_cmd_header_t *cmd; + BATCH_LOCALS(&rmesa->radeon); - if (R200_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s src %x/%x %d,%d dst: %x/%x %d,%d sz: %dx%d\n", - __FUNCTION__, - src_pitch, src_offset, srcx, srcy, - dst_pitch, dst_offset, dstx, dsty, - w, h); - - assert( (src_pitch & 63) == 0 ); - assert( (dst_pitch & 63) == 0 ); - assert( (src_offset & 1023) == 0 ); - assert( (dst_offset & 1023) == 0 ); - assert( w < (1<<16) ); - assert( h < (1<<16) ); - - // cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 8 * sizeof(int), - // __FUNCTION__ ); - - - cmd[0].header.cmd_type = RADEON_CMD_PACKET3; - cmd[1].i = R200_CP_CMD_BITBLT_MULTI | (5 << 16); - cmd[2].i = (RADEON_GMC_SRC_PITCH_OFFSET_CNTL | - RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_NONE | - (color_fmt << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_S | - RADEON_DP_SRC_SOURCE_MEMORY | - RADEON_GMC_CLR_CMP_CNTL_DIS | - RADEON_GMC_WR_MSK_DIS ); - - cmd[3].i = ((src_pitch/64)<<22) | (src_offset >> 10); - cmd[4].i = ((dst_pitch/64)<<22) | (dst_offset >> 10); - cmd[5].i = (srcx << 16) | srcy; - cmd[6].i = (dstx << 16) | dsty; /* dst */ - cmd[7].i = (w << 16) | h; + BEGIN_BATCH(3); + OUT_BATCH_PACKET3(R200_CP_CMD_3D_DRAW_VBUF_2, 0); + OUT_BATCH(R200_VF_PRIM_WALK_LIST | (vertex_count << 16) | type); + END_BATCH(); } - -void r200EmitWait( r200ContextPtr rmesa, GLuint flags ) -{ - drm_radeon_cmd_header_t *cmd; - - assert( !(flags & ~(RADEON_WAIT_2D|RADEON_WAIT_3D)) ); - - // cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 1 * sizeof(int), - // __FUNCTION__ ); - cmd[0].i = 0; - cmd[0].wait.cmd_type = RADEON_CMD_WAIT; - cmd[0].wait.flags = flags; -} diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 2725dc495f..607997fafc 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -531,7 +531,7 @@ struct r200_state { #define R200_CMD_BUF_SZ (16*1024) - +#define R200_ELT_BUF_SZ (16*1024) /* r200_tcl.c */ struct r200_tcl_info { @@ -544,6 +544,11 @@ struct r200_tcl_info { GLuint *Elts; + struct radeon_bo *elt_dma_bo; + int elt_dma_offset; /** Offset into this buffer object, in bytes */ + int elt_used; + + void (*flush) (r200ContextPtr); struct radeon_dma_region vertex_data[15]; }; diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index 1fbbbfbb56..65786be96c 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -85,252 +85,6 @@ static void r200BackUpAndEmitLostStateLocked( r200ContextPtr rmesa ) rmesa->store = saved_store; } -#if 0 -int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ) -{ - int ret, i; - drm_radeon_cmd_buffer_t cmd; - - if (rmesa->radeon.lost_context) - r200BackUpAndEmitLostStateLocked( rmesa ); - - if (R200_DEBUG & DEBUG_IOCTL) { - fprintf(stderr, "%s from %s\n", __FUNCTION__, caller); - - if (0 & R200_DEBUG & DEBUG_VERBOSE) - for (i = 0 ; i < rmesa->store.cmd_used ; i += 4 ) - fprintf(stderr, "%d: %x\n", i/4, - *(int *)(&rmesa->store.cmd_buf[i])); - } - - if (R200_DEBUG & DEBUG_DMA) - fprintf(stderr, "%s: Releasing %d buffers\n", __FUNCTION__, - rmesa->dma.nr_released_bufs); - - - if (R200_DEBUG & DEBUG_SANITY) { - if (rmesa->radeon.state.scissor.enabled) - ret = r200SanityCmdBuffer( rmesa, - rmesa->radeon.state.scissor.numClipRects, - rmesa->radeon.state.scissor.pClipRects); - else - ret = r200SanityCmdBuffer( rmesa, - rmesa->radeon.numClipRects, - rmesa->radeon.pClipRects); - if (ret) { - fprintf(stderr, "drmSanityCommandWrite: %d\n", ret); - goto out; - } - } - - - if (R200_DEBUG & DEBUG_MEMORY) { - if (! driValidateTextureHeaps( rmesa->radeon.texture_heaps, rmesa->radeon.nr_heaps, - & rmesa->radeon.swapped ) ) { - fprintf( stderr, "%s: texture memory is inconsistent - expect " - "mangled textures\n", __FUNCTION__ ); - } - } - - - cmd.bufsz = rmesa->store.cmd_used; - cmd.buf = rmesa->store.cmd_buf; - - if (rmesa->radeon.state.scissor.enabled) { - cmd.nbox = rmesa->radeon.state.scissor.numClipRects; - cmd.boxes = (drm_clip_rect_t *)rmesa->radeon.state.scissor.pClipRects; - } else { - cmd.nbox = rmesa->radeon.numClipRects; - cmd.boxes = (drm_clip_rect_t *)rmesa->radeon.pClipRects; - } - - ret = drmCommandWrite( rmesa->radeon.dri.fd, - DRM_RADEON_CMDBUF, - &cmd, sizeof(cmd) ); - - if (ret) - fprintf(stderr, "drmCommandWrite: %d\n", ret); - - if (R200_DEBUG & DEBUG_SYNC) { - fprintf(stderr, "\nSyncing in %s\n\n", __FUNCTION__); - radeonWaitForIdleLocked( &rmesa->radeon ); - } - - - out: - rmesa->store.primnr = 0; - rmesa->store.statenr = 0; - rmesa->store.cmd_used = 0; - rmesa->dma.nr_released_bufs = 0; - rmesa->save_on_next_emit = 1; - - return ret; -} - -/* Note: does not emit any commands to avoid recursion on - * r200AllocCmdBuf. - */ -void r200FlushCmdBuf( r200ContextPtr rmesa, const char *caller ) -{ - int ret; - - LOCK_HARDWARE( &rmesa->radeon ); - - ret = rcommonFlushCmdBufLocked( rmesa, caller ); - - UNLOCK_HARDWARE( &rmesa->radeon ); - - if (ret) { - fprintf(stderr, "drmRadeonCmdBuffer: %d (exiting)\n", ret); - exit(ret); - } -} -#endif - - -/* ============================================================= - * Hardware vertex buffer handling - */ - -#if 0 -void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) -{ - struct radeon_dma_buffer *dmabuf; - int fd = rmesa->radeon.dri.fd; - int index = 0; - int size = 0; - drmDMAReq dma; - int ret; - - if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_DMA)) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (rmesa->dma.flush) { - rmesa->dma.flush( rmesa->radeon.glCtx ); - } - - if (rmesa->dma.current.buf) - r200ReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ ); - - if (rmesa->dma.nr_released_bufs > 4) - rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); - - dma.context = rmesa->radeon.dri.hwContext; - dma.send_count = 0; - dma.send_list = NULL; - dma.send_sizes = NULL; - dma.flags = 0; - dma.request_count = 1; - dma.request_size = RADEON_BUFFER_SIZE; - dma.request_list = &index; - dma.request_sizes = &size; - dma.granted_count = 0; - - LOCK_HARDWARE(&rmesa->radeon); /* no need to validate */ - - while (1) { - ret = drmDMA( fd, &dma ); - if (ret == 0) - break; - - if (rmesa->dma.nr_released_bufs) { - rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); - } - - if (rmesa->radeon.do_usleeps) { - UNLOCK_HARDWARE( &rmesa->radeon ); - DO_USLEEP( 1 ); - LOCK_HARDWARE( &rmesa->radeon ); - } - } - - UNLOCK_HARDWARE(&rmesa->radeon); - - if (R200_DEBUG & DEBUG_DMA) - fprintf(stderr, "Allocated buffer %d\n", index); - - dmabuf = CALLOC_STRUCT( radeon_dma_buffer ); - dmabuf->buf = &rmesa->radeon.radeonScreen->buffers->list[index]; - dmabuf->refcount = 1; - - rmesa->dma.current.buf = dmabuf; - rmesa->dma.current.address = dmabuf->buf->address; - rmesa->dma.current.end = dmabuf->buf->total; - rmesa->dma.current.start = 0; - rmesa->dma.current.ptr = 0; -} - -void r200ReleaseDmaRegion( r200ContextPtr rmesa, - struct radeon_dma_region *region, - const char *caller ) -{ - if (R200_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s from %s\n", __FUNCTION__, caller); - - if (!region->buf) - return; - - if (rmesa->dma.flush) - rmesa->dma.flush( rmesa->radeon.glCtx ); - - if (--region->buf->refcount == 0) { - drm_radeon_cmd_header_t *cmd; - - if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_DMA)) - fprintf(stderr, "%s -- DISCARD BUF %d\n", __FUNCTION__, - region->buf->buf->idx); - - cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, sizeof(*cmd), - __FUNCTION__ ); - cmd->dma.cmd_type = RADEON_CMD_DMA_DISCARD; - cmd->dma.buf_idx = region->buf->buf->idx; - FREE(region->buf); - rmesa->dma.nr_released_bufs++; - } - - region->buf = NULL; - region->start = 0; -} - -/* Allocates a region from rmesa->dma.current. If there isn't enough - * space in current, grab a new buffer (and discard what was left of current) - */ -void r200AllocDmaRegion( r200ContextPtr rmesa, - struct radeon_dma_region *region, - int bytes, - int alignment ) -{ - if (R200_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s %d\n", __FUNCTION__, bytes); - - if (rmesa->dma.flush) - rmesa->dma.flush( rmesa->radeon.glCtx ); - - if (region->buf) - r200ReleaseDmaRegion( rmesa, region, __FUNCTION__ ); - - alignment--; - rmesa->dma.current.start = rmesa->dma.current.ptr = - (rmesa->dma.current.ptr + alignment) & ~alignment; - - if ( rmesa->dma.current.ptr + bytes > rmesa->dma.current.end ) - r200RefillCurrentDmaRegion( rmesa ); - - region->start = rmesa->dma.current.start; - region->ptr = rmesa->dma.current.start; - region->end = rmesa->dma.current.start + bytes; - region->address = rmesa->dma.current.address; - region->buf = rmesa->dma.current.buf; - region->buf->refcount++; - - rmesa->dma.current.ptr += bytes; /* bug - if alignment > 7 */ - rmesa->dma.current.start = - rmesa->dma.current.ptr = (rmesa->dma.current.ptr + 0x7) & ~0x7; - - assert( rmesa->dma.current.ptr <= rmesa->dma.current.end ); -} -#endif - /* ================================================================ * Buffer clear */ @@ -526,6 +280,9 @@ void r200Flush( GLcontext *ctx ) if (rmesa->dma.flush) rmesa->dma.flush( ctx ); + if (rmesa->tcl.flush) + rmesa->tcl.flush( rmesa ); + r200EmitState( rmesa ); if (rmesa->radeon.cmdbuf.cs->cdw) diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index 1ae0dd114b..e3f0b66514 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -53,7 +53,8 @@ extern void r200EmitVbufPrim( r200ContextPtr rmesa, GLuint primitive, GLuint vertex_nr ); -extern void r200FlushElts(GLcontext *ctx); +extern void r200FlushElts(r200ContextPtr rmesa); + extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, GLuint primitive, diff --git a/src/mesa/drivers/dri/r200/r200_pixel.c b/src/mesa/drivers/dri/r200/r200_pixel.c index 930d797f45..eefa2a1e11 100644 --- a/src/mesa/drivers/dri/r200/r200_pixel.c +++ b/src/mesa/drivers/dri/r200/r200_pixel.c @@ -156,6 +156,8 @@ r200TryReadPixels( GLcontext *ctx, GLuint cpp = rmesa->radeon.radeonScreen->cpp; GLint size = width * height * cpp; + return GL_FALSE; +#if 0 if (R200_DEBUG & DEBUG_PIXEL) fprintf(stderr, "%s\n", __FUNCTION__); @@ -165,7 +167,6 @@ r200TryReadPixels( GLcontext *ctx, pitch * height * rmesa->radeon.radeonScreen->cpp ) ) { if (R200_DEBUG & DEBUG_PIXEL) fprintf(stderr, "%s: dest not GART\n", __FUNCTION__); - return GL_FALSE; } /* Need GL_PACK_INVERT_MESA to cope with upsidedown results from @@ -262,7 +263,7 @@ r200TryReadPixels( GLcontext *ctx, UNLOCK_HARDWARE( &rmesa->radeon ); r200Finish( ctx ); /* required by GL */ - +#endif return GL_TRUE; } @@ -305,7 +306,7 @@ static void do_draw_pix( GLcontext *ctx, if (R200_DEBUG & DEBUG_PIXEL) fprintf(stderr, "%s\n", __FUNCTION__); - +#if 0 switch ( rmesa->radeon.radeonScreen->cpp ) { case 2: blit_format = R200_CP_COLOR_FORMAT_RGB565; @@ -366,6 +367,7 @@ static void do_draw_pix( GLcontext *ctx, rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); radeonWaitForIdleLocked( &rmesa->radeon ); /* required by GL */ UNLOCK_HARDWARE( &rmesa->radeon ); +#endif } @@ -431,7 +433,7 @@ r200TryDrawPixels( GLcontext *ctx, return GL_FALSE; } - if ( r200IsGartMemory(rmesa, pixels, size) ) + if (0)// r200IsGartMemory(rmesa, pixels, size) ) { do_draw_pix( ctx, x, y, width, height, pitch, pixels, planemask ); return GL_TRUE; diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 0f15fd457e..891a942e38 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -142,23 +142,22 @@ static GLboolean discrete_prim[0x10] = { static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) { - fprintf(stderr,"alloc elts\n"); - if (rmesa->dma.flush == r200FlushElts && - rmesa->store.cmd_used + nr*2 < R200_CMD_BUF_SZ) { + fprintf(stderr,"alloc elts %d %d\n", nr, rmesa->tcl.elt_used); + if (rmesa->tcl.flush == r200FlushElts && + rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) { - GLushort *dest = (GLushort *)(rmesa->store.cmd_buf + - rmesa->store.cmd_used); + GLushort *dest = (GLushort *)(rmesa->tcl.elt_dma_bo->ptr + + rmesa->tcl.elt_used); - rmesa->store.cmd_used += nr*2; + rmesa->tcl.elt_used += nr*2; return dest; } else { - if (rmesa->dma.flush) - rmesa->dma.flush( rmesa->radeon.glCtx ); + if (rmesa->tcl.flush) + rmesa->tcl.flush( rmesa ); - rcommonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + - rmesa->hw.max_state_size + ELTS_BUFSZ(nr) ); + rcommonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components)); r200EmitAOS( rmesa, rmesa->tcl.nr_aos_components, 0 ); -- cgit v1.2.3 From 4ca76586c23200b66cb4f85afb21ea02853779ea Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 23 Jan 2009 00:23:10 +1000 Subject: r200: disable some debug --- src/mesa/drivers/dri/r200/r200_maos_arrays.c | 2 +- src/mesa/drivers/dri/r200/r200_tcl.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/r200/r200_tcl.c') diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c index 7f7ae2ba79..bcdc4336ab 100644 --- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c +++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c @@ -223,7 +223,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) GLuint count = VB->Count; GLuint i, emitsize; - fprintf(stderr,"emit arrays\n"); + // fprintf(stderr,"emit arrays\n"); for ( i = 0; i < 15; i++ ) { GLubyte attrib = vimap_rev[i]; if (attrib != 255) { diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 891a942e38..10c0dacd30 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -142,7 +142,7 @@ static GLboolean discrete_prim[0x10] = { static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) { - fprintf(stderr,"alloc elts %d %d\n", nr, rmesa->tcl.elt_used); + // fprintf(stderr,"alloc elts %d %d\n", nr, rmesa->tcl.elt_used); if (rmesa->tcl.flush == r200FlushElts && rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) { @@ -187,7 +187,7 @@ static void r200EmitPrim( GLcontext *ctx, r200ContextPtr rmesa = R200_CONTEXT( ctx ); r200TclPrimitive( ctx, prim, hwprim ); - fprintf(stderr,"Emit prim %d\n", rmesa->tcl.nr_aos_components); + // fprintf(stderr,"Emit prim %d\n", rmesa->tcl.nr_aos_components); rcommonEnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + rmesa->hw.max_state_size + VBUF_BUFSZ ); -- cgit v1.2.3 From f69e2f42d53337702ce52173a58a49e53bfdee56 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 22 Jan 2009 22:49:16 +1000 Subject: r200: fix up swtcl/tcl flushes --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 3 ++- src/mesa/drivers/dri/r200/r200_context.h | 4 ++-- src/mesa/drivers/dri/r200/r200_ioctl.c | 6 +++--- src/mesa/drivers/dri/r200/r200_ioctl.h | 9 ++++----- src/mesa/drivers/dri/r200/r200_swtcl.c | 6 +----- src/mesa/drivers/dri/r200/r200_tcl.c | 8 ++++---- 6 files changed, 16 insertions(+), 20 deletions(-) (limited to 'src/mesa/drivers/dri/r200/r200_tcl.c') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index 5768f39e5c..fb8dddad3f 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -272,8 +272,9 @@ static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type) } } -void r200FlushElts( r200ContextPtr rmesa ) +void r200FlushElts(GLcontext *ctx) { + r200ContextPtr rmesa = R200_CONTEXT(ctx); int dwords; int nr, elt_used = rmesa->tcl.elt_used; diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 607997fafc..62847be522 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -548,7 +548,7 @@ struct r200_tcl_info { int elt_dma_offset; /** Offset into this buffer object, in bytes */ int elt_used; - void (*flush) (r200ContextPtr); + void (*flush) (GLcontext *ctx); struct radeon_dma_region vertex_data[15]; }; @@ -606,7 +606,7 @@ struct r200_swtcl_info { GLboolean needproj; struct radeon_bo *bo; - void (*flush) (r200ContextPtr); + void (*flush) (GLcontext *ctx); }; diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index 65786be96c..744a2d8a4f 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -277,11 +277,11 @@ void r200Flush( GLcontext *ctx ) if (R200_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); - if (rmesa->dma.flush) - rmesa->dma.flush( ctx ); + if (rmesa->swtcl.flush) + rmesa->swtcl.flush( ctx ); if (rmesa->tcl.flush) - rmesa->tcl.flush( rmesa ); + rmesa->tcl.flush( ctx ); r200EmitState( rmesa ); diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index e3f0b66514..ccc15c5b49 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -53,8 +53,7 @@ extern void r200EmitVbufPrim( r200ContextPtr rmesa, GLuint primitive, GLuint vertex_nr ); -extern void r200FlushElts(r200ContextPtr rmesa); - +extern void r200FlushElts(GLcontext *ctx); extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, GLuint primitive, @@ -113,8 +112,8 @@ void r200SetUpAtomList( r200ContextPtr rmesa ); */ #define R200_NEWPRIM( rmesa ) \ do { \ - if ( rmesa->dma.flush ) \ - rmesa->dma.flush( rmesa->radeon.glCtx ); \ + if ( rmesa->swtcl.flush ) \ + rmesa->swtcl.flush( rmesa->radeon.glCtx ); \ } while (0) /* Can accomodate several state changes and primitive changes without @@ -154,7 +153,7 @@ static INLINE int R200_DB_STATECHANGE( */ #define R200_FIREVERTICES( rmesa ) \ do { \ - if ( rmesa->store.cmd_used || rmesa->dma.flush ) { \ + if ( rmesa->swtcl.flush || rmesa->tcl.flush ) { \ r200Flush( rmesa->radeon.glCtx ); \ } \ } while (0) diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index 7275886f84..663e4ae0bc 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -210,10 +210,6 @@ static void r200RenderStart( GLcontext *ctx ) r200ContextPtr rmesa = R200_CONTEXT( ctx ); r200SetVertexFormat( ctx ); - - if (rmesa->dma.flush != 0 && - rmesa->dma.flush != flush_last_swtcl_prim) - rmesa->dma.flush( ctx ); } @@ -283,7 +279,7 @@ static void flush_last_swtcl_prim(GLcontext *ctx) if (R200_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); - rmesa->dma.flush = NULL; + rmesa->swtcl.flush = NULL; radeon_bo_unmap(rmesa->swtcl.bo); rcommonEnsureCmdBufSpace(rmesa, diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 10c0dacd30..9562c8b315 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -155,7 +155,7 @@ static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) } else { if (rmesa->tcl.flush) - rmesa->tcl.flush( rmesa ); + rmesa->tcl.flush( rmesa->radeon.glCtx ); rcommonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components)); @@ -564,10 +564,10 @@ static void transition_to_hwtnl( GLcontext *ctx ) tnl->Driver.NotifyMaterialChange = r200UpdateMaterial; - if ( rmesa->dma.flush ) - rmesa->dma.flush( rmesa->radeon.glCtx ); + if ( rmesa->swtcl.flush ) + rmesa->swtcl.flush( rmesa->radeon.glCtx ); - rmesa->dma.flush = NULL; + rmesa->swtcl.flush = NULL; R200_STATECHANGE( rmesa, vap ); rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] |= R200_VAP_TCL_ENABLE; -- cgit v1.2.3 From c9bb5cd20e5468168d54fe461c853926072fa813 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 29 Jan 2009 20:33:07 +1000 Subject: r200: bring back single dma flush --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 8 ++++---- src/mesa/drivers/dri/r200/r200_context.c | 4 ++-- src/mesa/drivers/dri/r200/r200_context.h | 3 --- src/mesa/drivers/dri/r200/r200_ioctl.c | 13 +++++-------- src/mesa/drivers/dri/r200/r200_ioctl.h | 6 +++--- src/mesa/drivers/dri/r200/r200_swtcl.c | 6 +++--- src/mesa/drivers/dri/r200/r200_tcl.c | 15 ++++++++------- 7 files changed, 25 insertions(+), 30 deletions(-) (limited to 'src/mesa/drivers/dri/r200/r200_tcl.c') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index fb8dddad3f..eba5d6e019 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -281,8 +281,8 @@ void r200FlushElts(GLcontext *ctx) if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS)) fprintf(stderr, "%s %x %d\n", __FUNCTION__, rmesa->tcl.hw_primitive, elt_used); - assert( rmesa->tcl.flush == r200FlushElts ); - rmesa->tcl.flush = NULL; + assert( rmesa->radeon.dma.flush == r200FlushElts ); + rmesa->radeon.dma.flush = NULL; elt_used = (elt_used + 2) & ~2; @@ -329,9 +329,9 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, fprintf(stderr, "%s: header prim %x \n", __FUNCTION__, primitive); - assert(!rmesa->tcl.flush); + assert(!rmesa->radeon.dma.flush); rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->tcl.flush = r200FlushElts; + rmesa->radeon.dma.flush = r200FlushElts; return retval; } diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 53c64eb5a3..c2b269880c 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -584,8 +584,8 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) r200DestroySwtcl( rmesa->radeon.glCtx ); r200ReleaseArrays( rmesa->radeon.glCtx, ~0 ); - if (rmesa->dma.current) { - radeonReleaseDmaRegion(rmesa); + if (rmesa->radeon.dma.current) { + radeonReleaseDmaRegion(&rmesa->radeon); rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); } diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 80981135ac..2df0ca1272 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -544,7 +544,6 @@ struct r200_tcl_info { int elt_dma_offset; /** Offset into this buffer object, in bytes */ int elt_used; - void (*flush) (GLcontext *ctx); struct radeon_dma_region vertex_data[15]; }; @@ -602,7 +601,6 @@ struct r200_swtcl_info { GLboolean needproj; struct radeon_bo *bo; - void (*flush) (GLcontext *ctx); }; @@ -633,7 +631,6 @@ struct r200_context { /* Vertex buffers */ struct radeon_ioctl ioctl; - struct radeon_dma dma; struct radeon_store store; /* A full state emit as of the first state emit in the main store, in case * the context is lost. diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index cb2f50d5d8..0b7f664457 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -76,12 +76,12 @@ static void r200BackUpAndEmitLostStateLocked( r200ContextPtr rmesa ) rmesa->radeon.lost_context = GL_FALSE; - nr_released_bufs = rmesa->dma.nr_released_bufs; + nr_released_bufs = rmesa->radeon.dma.nr_released_bufs; saved_store = rmesa->store; - rmesa->dma.nr_released_bufs = 0; + rmesa->radeon.dma.nr_released_bufs = 0; rmesa->store = rmesa->backup_store; rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); - rmesa->dma.nr_released_bufs = nr_released_bufs; + rmesa->radeon.dma.nr_released_bufs = nr_released_bufs; rmesa->store = saved_store; } @@ -302,11 +302,8 @@ void r200Flush( GLcontext *ctx ) if (R200_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); - if (rmesa->swtcl.flush) - rmesa->swtcl.flush( ctx ); - - if (rmesa->tcl.flush) - rmesa->tcl.flush( ctx ); + if (rmesa->radeon.dma.flush) + rmesa->radeon.dma.flush( ctx ); r200EmitState( rmesa ); diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index ccc15c5b49..0410fdf3c3 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -112,8 +112,8 @@ void r200SetUpAtomList( r200ContextPtr rmesa ); */ #define R200_NEWPRIM( rmesa ) \ do { \ - if ( rmesa->swtcl.flush ) \ - rmesa->swtcl.flush( rmesa->radeon.glCtx ); \ + if ( rmesa->radeon.dma.flush ) \ + rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \ } while (0) /* Can accomodate several state changes and primitive changes without @@ -153,7 +153,7 @@ static INLINE int R200_DB_STATECHANGE( */ #define R200_FIREVERTICES( rmesa ) \ do { \ - if ( rmesa->swtcl.flush || rmesa->tcl.flush ) { \ + if ( rmesa->radeon.dma.flush ) { \ r200Flush( rmesa->radeon.glCtx ); \ } \ } while (0) diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index 3142f8b6c9..2a22bd297a 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -279,7 +279,7 @@ static void flush_last_swtcl_prim(GLcontext *ctx) if (R200_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); - rmesa->swtcl.flush = NULL; + rmesa->radeon.dma.flush = NULL; radeon_bo_unmap(rmesa->swtcl.bo); rcommonEnsureCmdBufSpace(rmesa, @@ -313,9 +313,9 @@ r200AllocDmaLowVerts( r200ContextPtr rmesa, int nverts, int vsize ) rmesa->swtcl.bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, 0, bytes, 4, RADEON_GEM_DOMAIN_GTT, 0); radeon_bo_map(rmesa->swtcl.bo, 1); - if (rmesa->swtcl.flush == NULL) { + if (rmesa->radeon.dma.flush == NULL) { rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->swtcl.flush = flush_last_swtcl_prim; + rmesa->radeon.dma.flush = flush_last_swtcl_prim; } return rmesa->swtcl.bo->ptr; diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 9562c8b315..5bb25bc53a 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -143,7 +143,7 @@ static GLboolean discrete_prim[0x10] = { static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) { // fprintf(stderr,"alloc elts %d %d\n", nr, rmesa->tcl.elt_used); - if (rmesa->tcl.flush == r200FlushElts && + if (rmesa->radeon.dma.flush == r200FlushElts && rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) { GLushort *dest = (GLushort *)(rmesa->tcl.elt_dma_bo->ptr + @@ -154,8 +154,8 @@ static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) return dest; } else { - if (rmesa->tcl.flush) - rmesa->tcl.flush( rmesa->radeon.glCtx ); + if (rmesa->radeon.dma.flush) + rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); rcommonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components)); @@ -188,7 +188,8 @@ static void r200EmitPrim( GLcontext *ctx, r200TclPrimitive( ctx, prim, hwprim ); // fprintf(stderr,"Emit prim %d\n", rmesa->tcl.nr_aos_components); - rcommonEnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + + rcommonEnsureCmdBufSpace( &rmesa->radeon, + AOS_BUFSZ(rmesa->tcl.nr_aos_components) + rmesa->hw.max_state_size + VBUF_BUFSZ ); r200EmitAOS( rmesa, @@ -564,10 +565,10 @@ static void transition_to_hwtnl( GLcontext *ctx ) tnl->Driver.NotifyMaterialChange = r200UpdateMaterial; - if ( rmesa->swtcl.flush ) - rmesa->swtcl.flush( rmesa->radeon.glCtx ); + if ( rmesa->radeon.dma.flush ) + rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); - rmesa->swtcl.flush = NULL; + rmesa->radeon.dma.flush = NULL; R200_STATECHANGE( rmesa, vap ); rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] |= R200_VAP_TCL_ENABLE; -- cgit v1.2.3 From e45213d89bf26c68c9f4c9074eaec9ab3311de7d Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 31 Jan 2009 01:59:57 +1000 Subject: r200/r300: add aperture space checks --- src/mesa/drivers/dri/r200/r200_ioctl.h | 2 + src/mesa/drivers/dri/r200/r200_state.c | 71 ++++++++++++++++- src/mesa/drivers/dri/r200/r200_state.h | 2 +- src/mesa/drivers/dri/r200/r200_tcl.c | 3 +- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 8 +- src/mesa/drivers/dri/r300/r300_render.c | 3 + src/mesa/drivers/dri/r300/r300_state.c | 1 - src/mesa/drivers/dri/r300/r300_swtcl.c | 2 + src/mesa/drivers/dri/r300/r300_tex.h | 2 +- src/mesa/drivers/dri/r300/r300_texstate.c | 53 ++++++++++++- src/mesa/drivers/dri/radeon/common_misc.c | 49 ++++++++++-- src/mesa/drivers/dri/radeon/common_misc.h | 33 ++++++++ src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 65 +++++++++------- src/mesa/drivers/dri/radeon/radeon_bo_legacy.h | 1 + src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 104 ++++++++++++++++++++++++- 15 files changed, 345 insertions(+), 54 deletions(-) (limited to 'src/mesa/drivers/dri/r200/r200_tcl.c') diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index 0410fdf3c3..3e39a9124d 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -43,6 +43,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drm.h" #include "radeon_drm.h" +#include "common_cmdbuf.h" + extern void r200EmitState( r200ContextPtr rmesa ); extern void r200EmitVertexAOS( r200ContextPtr rmesa, GLuint vertex_size, diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index f2e62d1bf7..f3d809d62c 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -48,6 +48,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast_setup/swrast_setup.h" #include "radeon_buffer.h" +#include "radeon_cs.h" +#include "radeon_mipmap_tree.h" #include "r200_context.h" #include "r200_ioctl.h" #include "r200_state.h" @@ -2347,9 +2349,66 @@ r200UpdateDrawBuffer(GLcontext *ctx) #endif } +static GLboolean r200ValidateBuffers(GLcontext *ctx) +{ + r200ContextPtr rmesa = R200_CONTEXT(ctx); + struct radeon_cs_space_check bos[8]; + struct radeon_renderbuffer *rrb; + int num_bo = 0; + int i; + int flushed = 0, ret; +again: + num_bo = 0; + + rrb = radeon_get_colorbuffer(&rmesa->radeon); + /* color buffer */ + if (rrb && rrb->bo) { + bos[num_bo].bo = rrb->bo; + bos[num_bo].read_domains = 0; + bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM; + bos[num_bo].new_accounted = 0; + num_bo++; + } + + /* depth buffer */ + rrb = radeon_get_depthbuffer(&rmesa->radeon); + /* color buffer */ + if (rrb && rrb->bo) { + bos[num_bo].bo = rrb->bo; + bos[num_bo].read_domains = 0; + bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM; + bos[num_bo].new_accounted = 0; + num_bo++; + } + + for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) { + radeonTexObj *t; + + if (!ctx->Texture.Unit[i]._ReallyEnabled) + continue; + + t = radeon_tex_obj(ctx->Texture.Unit[i]._Current); + bos[num_bo].bo = t->mt->bo; + bos[num_bo].read_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM; + bos[num_bo].write_domain = 0; + bos[num_bo].new_accounted = 0; + num_bo++; + } + + ret = radeon_cs_space_check(rmesa->radeon.cmdbuf.cs, bos, num_bo); + if (ret == RADEON_CS_SPACE_OP_TO_BIG) + return GL_FALSE; + if (ret == RADEON_CS_SPACE_FLUSH) { + r200Flush(ctx); + if (flushed) + return GL_FALSE; + flushed = 1; + goto again; + } + return GL_TRUE; +} - -void r200ValidateState( GLcontext *ctx ) +GLboolean r200ValidateState( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); GLuint new_state = rmesa->radeon.NewGLState; @@ -2364,6 +2423,10 @@ void r200ValidateState( GLcontext *ctx ) r200UpdateLocalViewer( ctx ); } + /* we need to do a space check here */ + if (!r200ValidateBuffers(ctx)) + return GL_FALSE; + /* FIXME: don't really need most of these when vertex progs are enabled */ /* Need an event driven matrix update? @@ -2408,6 +2471,7 @@ void r200ValidateState( GLcontext *ctx ) } rmesa->radeon.NewGLState = 0; + return GL_TRUE; } @@ -2452,7 +2516,8 @@ static void r200WrapRunPipeline( GLcontext *ctx ) /* Validate state: */ if (rmesa->radeon.NewGLState) - r200ValidateState( ctx ); + if (!r200ValidateState( ctx )) + FALLBACK(rmesa, RADEON_FALLBACK_TEXTURE, GL_TRUE); has_material = !ctx->VertexProgram._Enabled && ctx->Light.Enabled && check_material( ctx ); diff --git a/src/mesa/drivers/dri/r200/r200_state.h b/src/mesa/drivers/dri/r200/r200_state.h index 741bf88e9c..1dddbfdbfe 100644 --- a/src/mesa/drivers/dri/r200/r200_state.h +++ b/src/mesa/drivers/dri/r200/r200_state.h @@ -47,7 +47,7 @@ extern void r200UpdateViewportOffset( GLcontext *ctx ); extern void r200UpdateWindow( GLcontext *ctx ); extern void r200UpdateDrawBuffer(GLcontext *ctx); -extern void r200ValidateState( GLcontext *ctx ); +extern GLboolean r200ValidateState( GLcontext *ctx ); extern void r200PrintDirty( r200ContextPtr rmesa, const char *msg ); diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 5bb25bc53a..3c19e330f5 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -406,7 +406,8 @@ static GLboolean r200_run_tcl_render( GLcontext *ctx, /* Validate state: */ if (rmesa->radeon.NewGLState) - r200ValidateState( ctx ); + if (!r200ValidateState( ctx )) + return GL_TRUE; /* fallback to sw t&l */ if (!ctx->VertexProgram._Enabled) { /* NOTE: inputs != tnl->render_inputs - these are the untransformed diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 04bb76bb30..9098931602 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -296,12 +296,8 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) BATCH_LOCALS(&r300->radeon); struct radeon_renderbuffer *rrb; uint32_t cbpitch; - GLframebuffer *fb = r300->radeon.dri.drawable->driverPrivate; - rrb = r300->radeon.state.color.rrb; - if (r300->radeon.radeonScreen->driScreen->dri2.enabled) { - rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - } + rrb = radeon_get_colorbuffer(&r300->radeon); if (!rrb || !rrb->bo) { fprintf(stderr, "no rrb\n"); return; @@ -331,7 +327,7 @@ static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom) struct radeon_renderbuffer *rrb; uint32_t zbpitch; - rrb = r300->radeon.state.depth.rrb; + rrb = radeon_get_depthbuffer(&r300->radeon); if (!rrb) return; diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 57249c46ef..3b00de2b56 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -501,6 +501,9 @@ static GLboolean r300RunTCLRender(GLcontext * ctx, return GL_TRUE; } + if (!r300ValidateTextures(ctx)) + return GL_TRUE; + r300UpdateShaders(rmesa); vp = (struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx); diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 5fbd5b93ff..e5939afeeb 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -2632,7 +2632,6 @@ void r300UpdateShaderStates(r300ContextPtr rmesa) GLcontext *ctx; ctx = rmesa->radeon.glCtx; - r300ValidateTextures(ctx); r300SetEarlyZState(ctx); GLuint fgdepthsrc = R300_FG_DEPTH_SRC_SCAN; diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 6ae5868a52..ef65fbb127 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -579,6 +579,8 @@ static void r300RenderStart(GLcontext *ctx) r300ChooseRenderState(ctx); r300SetVertexFormat(ctx); + r300ValidateTextures(ctx); + r300UpdateShaders(rmesa); r300UpdateShaderStates(rmesa); diff --git a/src/mesa/drivers/dri/r300/r300_tex.h b/src/mesa/drivers/dri/r300/r300_tex.h index 358b927828..a293ccf02c 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.h +++ b/src/mesa/drivers/dri/r300/r300_tex.h @@ -41,7 +41,7 @@ extern void r300SetTexOffset(__DRIcontext *pDRICtx, GLint texname, unsigned long long offset, GLint depth, GLuint pitch); -extern void r300ValidateTextures(GLcontext * ctx); +extern GLboolean r300ValidateTextures(GLcontext * ctx); extern void r300InitTextureFuncs(struct dd_function_table *functions); diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 68c7ca3d29..7ffc15fe39 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -49,6 +49,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_ioctl.h" #include "radeon_ioctl.h" #include "radeon_mipmap_tree.h" +#include "radeon_cs.h" #include "r300_tex.h" #include "r300_reg.h" #include "radeon_buffer.h" @@ -265,13 +266,43 @@ static GLboolean r300_validate_texture(GLcontext * ctx, struct gl_texture_object /** - * Ensure all enabled and complete textures are uploaded. + * Ensure all enabled and complete textures are uploaded along with any buffers being used. */ -void r300ValidateTextures(GLcontext * ctx) +GLboolean r300ValidateBuffers(GLcontext * ctx) { + r300ContextPtr rmesa = R300_CONTEXT(ctx); + struct radeon_cs_space_check bos[16]; + struct radeon_renderbuffer *rrb; + int num_bo = 0; int i; + int flushed = 0, ret; +again: + num_bo = 0; + + rrb = radeon_get_colorbuffer(&rmesa->radeon); + /* color buffer */ + if (rrb && rrb->bo) { + bos[num_bo].bo = rrb->bo; + bos[num_bo].read_domains = 0; + bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM; + bos[num_bo].new_accounted = 0; + num_bo++; + } + /* depth buffer */ + rrb = radeon_get_depthbuffer(&rmesa->radeon); + /* color buffer */ + if (rrb && rrb->bo) { + bos[num_bo].bo = rrb->bo; + bos[num_bo].read_domains = 0; + bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM; + bos[num_bo].new_accounted = 0; + num_bo++; + } + for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) { + radeonTexObj *t; + if (!ctx->Texture.Unit[i]._ReallyEnabled) continue; @@ -280,7 +311,25 @@ void r300ValidateTextures(GLcontext * ctx) "failed to validate texture for unit %d.\n", i); } + t = radeon_tex_obj(ctx->Texture.Unit[i]._Current); + bos[num_bo].bo = t->mt->bo; + bos[num_bo].read_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM; + bos[num_bo].write_domain = 0; + bos[num_bo].new_accounted = 0; + num_bo++; } + + ret = radeon_cs_space_check(rmesa->radeon.cmdbuf.cs, bos, num_bo); + if (ret == RADEON_CS_SPACE_OP_TO_BIG) + return GL_FALSE; + if (ret == RADEON_CS_SPACE_FLUSH) { + r300Flush(ctx); + if (flushed) + return GL_FALSE; + flushed = 1; + goto again; + } + return GL_TRUE; } void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 19294487f6..1adcefb19a 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -685,6 +685,14 @@ void rcommonInitCmdBuf(radeonContextPtr rmesa, int max_state_size) assert(rmesa->cmdbuf.cs != NULL); rmesa->cmdbuf.size = size; + if (!rmesa->radeonScreen->kernel_mm) { + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]); + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, rmesa->radeonScreen->gartTextures.size); + } else { + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]); + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, rmesa->radeonScreen->gartTextures.size); + } + } /** * Destroy the command buffer @@ -907,7 +915,7 @@ void radeonCleanupContext(radeonContextPtr radeon) } } -void +static void radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon, GLframebuffer *draw) { @@ -1314,7 +1322,6 @@ void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, { radeonContextPtr rmesa = RADEON_CONTEXT(ctx); uint32_t *out; - uint32_t bo_size; if (stride == 0) { radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * 4, 32); @@ -1328,7 +1335,6 @@ void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, aos->components = size; aos->count = count; -// radeon_bo_map(aos->bo, 1); out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); switch (size) { case 1: radeonEmitVec4(out, data, stride, count); break; @@ -1339,7 +1345,6 @@ void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, assert(0); break; } -// radeon_bo_unmap(aos->bo); } @@ -2320,6 +2325,9 @@ void radeonSpanRenderFinish(GLcontext * ctx) void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size) { + struct radeon_cs_space_check bos[1]; + int flushed, ret; + size = MAX2(size, MAX_DMA_BUF_SZ * 16); if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) @@ -2330,8 +2338,6 @@ void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size) rmesa->dma.flush(rmesa->glCtx); } - - if (rmesa->dma.nr_released_bufs > 4) { rcommonFlushCmdBuf(rmesa, __FUNCTION__); rmesa->dma.nr_released_bufs = 0; @@ -2341,13 +2347,42 @@ void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size) radeon_bo_unref(rmesa->dma.current); rmesa->dma.current = 0; } - + +again_alloc: rmesa->dma.current = radeon_bo_open(rmesa->radeonScreen->bom, 0, size, 4, RADEON_GEM_DOMAIN_GTT, 0); + if (!rmesa->dma.current) { + rcommonFlushCmdBuf(rmesa, __FUNCTION__); + rmesa->dma.nr_released_bufs = 0; + goto again_alloc; + } + rmesa->dma.current_used = 0; rmesa->dma.current_vertexptr = 0; + + bos[0].bo = rmesa->dma.current; + bos[0].read_domains = RADEON_GEM_DOMAIN_GTT; + bos[0].write_domain =0 ; + bos[0].new_accounted = 0; + +again: + ret = radeon_cs_space_check(rmesa->cmdbuf.cs, bos, 1); + if (ret == RADEON_CS_SPACE_OP_TO_BIG) { + fprintf(stderr,"Got OPEARTION TO BIG ILLEGAL - this cannot happen"); + assert(0); + } else if (ret == RADEON_CS_SPACE_FLUSH) { + rcommonFlushCmdBuf(rmesa, __FUNCTION__); + if (flushed) { + fprintf(stderr,"flushed but still no space\n"); + assert(0); + } + flushed = 1; + goto again; + } + + radeon_bo_map(rmesa->dma.current, 1); } diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h index d17d1607db..44e464eb13 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.h +++ b/src/mesa/drivers/dri/radeon/common_misc.h @@ -2,6 +2,7 @@ #define COMMON_MISC_H #include "common_context.h" +#include "radeon_buffer.h" void radeonRecalcScissorRects(radeonContextPtr radeon); void radeonSetCliprects(radeonContextPtr radeon); void radeonUpdateScissor( GLcontext *ctx ); @@ -122,4 +123,36 @@ void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size); void radeonAllocDmaRegion(radeonContextPtr rmesa, struct radeon_bo **pbo, int *poffset, int bytes, int alignment); +void radeonReleaseDmaRegion(radeonContextPtr rmesa); + +void rcommon_flush_last_swtcl_prim(GLcontext *ctx); + +void *rcommonAllocDmaLowVerts(radeonContextPtr rmesa, int nverts, int vsize); + + +static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPtr rmesa) +{ + struct radeon_renderbuffer *rrb; + rrb = rmesa->state.depth.rrb; + if (!rrb) + return NULL; + + return rrb; +} + +static inline struct radeon_renderbuffer *radeon_get_colorbuffer(radeonContextPtr rmesa) +{ + struct radeon_renderbuffer *rrb; + GLframebuffer *fb = rmesa->dri.drawable->driverPrivate; + + rrb = rmesa->state.color.rrb; + if (rmesa->radeonScreen->driScreen->dri2.enabled) { + rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + } + if (!rrb) + return NULL; + return rrb; +} + + #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index bd126c026c..f782d96900 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -413,10 +413,8 @@ static struct radeon_bo *bo_open(struct radeon_bo_manager *bom, r = bo_dma_alloc(&(bo_legacy->base)); if (r) { if (legacy_wait_any_pending(boml) == -1) { - fprintf(stderr, "Ran out of GART memory (for %d)!\n", size); - fprintf(stderr, "Please consider adjusting GARTSize option.\n"); bo_free(bo_legacy); - exit(-1); + return NULL; } goto retry; return NULL; @@ -639,6 +637,24 @@ void radeon_bo_manager_legacy_dtor(struct radeon_bo_manager *bom) free(boml); } +static struct bo_legacy *radeon_legacy_bo_alloc_static(struct bo_manager_legacy *bom, + int size, uint32_t offset) +{ + struct bo_legacy *bo; + + bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0); + if (bo == NULL) + return NULL; + bo->static_bo = 1; + bo->offset = offset + bom->fb_location; + bo->base.handle = bo->offset; + bo->ptr = bom->screen->driScreen->pFB + offset; + if (bo->base.handle > bom->nhandle) { + bom->nhandle = bo->base.handle + 1; + } + return bo; +} + struct radeon_bo_manager *radeon_bo_manager_legacy_ctor(struct radeon_screen *scrn) { struct bo_manager_legacy *bom; @@ -682,41 +698,30 @@ struct radeon_bo_manager *radeon_bo_manager_legacy_ctor(struct radeon_screen *sc /* biggest framebuffer size */ size = 4096*4096*4; + /* allocate front */ - bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0); - if (bo == NULL) { + bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->frontOffset); + if (!bo) { radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom); return NULL; } if (scrn->sarea->tiling_enabled) { bo->base.flags = RADEON_BO_FLAGS_MACRO_TILE; } - bo->static_bo = 1; - bo->offset = bom->screen->frontOffset + bom->fb_location; - bo->base.handle = bo->offset; - bo->ptr = scrn->driScreen->pFB + bom->screen->frontOffset; - if (bo->base.handle > bom->nhandle) { - bom->nhandle = bo->base.handle + 1; - } + /* allocate back */ - bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0); - if (bo == NULL) { + bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->backOffset); + if (!bo) { radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom); return NULL; } if (scrn->sarea->tiling_enabled) { bo->base.flags = RADEON_BO_FLAGS_MACRO_TILE; } - bo->static_bo = 1; - bo->offset = bom->screen->backOffset + bom->fb_location; - bo->base.handle = bo->offset; - bo->ptr = scrn->driScreen->pFB + bom->screen->backOffset; - if (bo->base.handle > bom->nhandle) { - bom->nhandle = bo->base.handle + 1; - } + /* allocate depth */ - bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0); - if (bo == NULL) { + bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->depthOffset); + if (!bo) { radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom); return NULL; } @@ -725,13 +730,6 @@ struct radeon_bo_manager *radeon_bo_manager_legacy_ctor(struct radeon_screen *sc bo->base.flags |= RADEON_BO_FLAGS_MACRO_TILE; bo->base.flags |= RADEON_BO_FLAGS_MICRO_TILE; } - bo->static_bo = 1; - bo->offset = bom->screen->depthOffset + bom->fb_location; - bo->base.handle = bo->offset; - bo->ptr = scrn->driScreen->pFB + bom->screen->depthOffset; - if (bo->base.handle > bom->nhandle) { - bom->nhandle = bo->base.handle + 1; - } return (struct radeon_bo_manager*)bom; } @@ -750,3 +748,10 @@ unsigned radeon_bo_legacy_relocs_size(struct radeon_bo *bo) } return bo->size; } + +int radeon_legacy_bo_is_static(struct radeon_bo *bo) +{ + struct bo_legacy *bo_legacy = (struct bo_legacy*)bo; + return bo_legacy->static_bo; +} + diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h index 208171e372..575979cbec 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h @@ -44,4 +44,5 @@ void radeon_bo_manager_legacy_dtor(struct radeon_bo_manager *bom); void radeon_bo_legacy_texture_age(struct radeon_bo_manager *bom); unsigned radeon_bo_legacy_relocs_size(struct radeon_bo *bo); +int radeon_legacy_bo_is_static(struct radeon_bo *bo); #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index 8997187d62..171818db37 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -315,7 +315,7 @@ static int cs_emit(struct radeon_cs *cs) cmd.boxes = (drm_clip_rect_t *) csm->ctx->pClipRects; } - dump_cmdbuf(cs); + // dump_cmdbuf(cs); r = drmCommandWrite(cs->csm->fd, DRM_RADEON_CMDBUF, &cmd, sizeof(cmd)); if (r) { @@ -330,6 +330,10 @@ static int cs_emit(struct radeon_cs *cs) } } cs_set_age(cs); + + cs->csm->read_used = 0; + cs->csm->vram_write_used = 0; + cs->csm->gart_write_used = 0; return 0; } @@ -374,6 +378,101 @@ static void cs_print(struct radeon_cs *cs, FILE *file) { } +static int cs_check_space(struct radeon_cs *cs, struct radeon_cs_space_check *bos, int num_bo) +{ + struct radeon_cs_manager *csm = cs->csm; + int this_op_read = 0, this_op_gart_write = 0, this_op_vram_write = 0; + uint32_t read_domains, write_domain; + int i; + struct radeon_bo *bo; + + /* check the totals for this operation */ + + if (num_bo == 0) + return 0; + + /* prepare */ + for (i = 0; i < num_bo; i++) { + bo = bos[i].bo; + + bos[i].new_accounted = 0; + read_domains = bos[i].read_domains; + write_domain = bos[i].write_domain; + + /* pinned bos don't count */ + if (radeon_legacy_bo_is_static(bo)) + continue; + + /* already accounted this bo */ + if (write_domain && (write_domain == bo->space_accounted)) + continue; + + if (read_domains && ((read_domains << 16) == bo->space_accounted)) + continue; + + if (bo->space_accounted == 0) { + if (write_domain == RADEON_GEM_DOMAIN_VRAM) + this_op_vram_write += bo->size; + else if (write_domain == RADEON_GEM_DOMAIN_GTT) + this_op_gart_write += bo->size; + else + this_op_read += bo->size; + bos[i].new_accounted = (read_domains << 16) | write_domain; + } else { + uint16_t old_read, old_write; + + old_read = bo->space_accounted >> 16; + old_write = bo->space_accounted & 0xffff; + + if (write_domain && (old_read & write_domain)) { + bos[i].new_accounted = write_domain; + /* moving from read to a write domain */ + if (write_domain == RADEON_GEM_DOMAIN_VRAM) { + this_op_read -= bo->size; + this_op_vram_write += bo->size; + } else if (write_domain == RADEON_GEM_DOMAIN_VRAM) { + this_op_read -= bo->size; + this_op_gart_write += bo->size; + } + } else if (read_domains & old_write) { + bos[i].new_accounted = bo->space_accounted & 0xffff; + } else { + /* rewrite the domains */ + if (write_domain != old_write) + fprintf(stderr,"WRITE DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, write_domain, old_write); + if (read_domains != old_read) + fprintf(stderr,"READ DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, read_domains, old_read); + return RADEON_CS_SPACE_FLUSH; + } + } + } + + if (this_op_read < 0) + this_op_read = 0; + + /* check sizes - operation first */ + if ((this_op_read + this_op_gart_write > csm->gart_limit) || + (this_op_vram_write > csm->vram_limit)) { + return RADEON_CS_SPACE_OP_TO_BIG; + } + + if (((csm->vram_write_used + this_op_vram_write) > csm->vram_limit) || + ((csm->read_used + csm->gart_write_used + this_op_gart_write + this_op_read) > csm->gart_limit)) { + return RADEON_CS_SPACE_FLUSH; + } + + csm->gart_write_used += this_op_gart_write; + csm->vram_write_used += this_op_vram_write; + csm->read_used += this_op_read; + /* commit */ + for (i = 0; i < num_bo; i++) { + bo = bos[i].bo; + bo->space_accounted = bos[i].new_accounted; + } + + return RADEON_CS_SPACE_OK; +} + static struct radeon_cs_funcs radeon_cs_legacy_funcs = { cs_create, cs_write_dword, @@ -384,7 +483,8 @@ static struct radeon_cs_funcs radeon_cs_legacy_funcs = { cs_destroy, cs_erase, cs_need_flush, - cs_print + cs_print, + cs_check_space }; struct radeon_cs_manager *radeon_cs_manager_legacy_ctor(struct radeon_context *ctx) -- cgit v1.2.3 From f68a61d88398fe8eb3eb41b929dcb4483354a81e Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 31 Jan 2009 02:00:12 +1000 Subject: r200/r300: swtcl fixups to use old dma buffers on top of BOs --- src/mesa/drivers/dri/r200/r200_context.c | 3 +- src/mesa/drivers/dri/r200/r200_context.h | 30 ----- src/mesa/drivers/dri/r200/r200_maos_arrays.c | 19 ++- src/mesa/drivers/dri/r200/r200_swtcl.c | 113 ++++++------------ src/mesa/drivers/dri/r200/r200_swtcl.h | 2 +- src/mesa/drivers/dri/r200/r200_tcl.c | 4 +- src/mesa/drivers/dri/r300/r300_context.c | 1 + src/mesa/drivers/dri/r300/r300_context.h | 34 +----- src/mesa/drivers/dri/r300/r300_swtcl.c | 157 ++++++++----------------- src/mesa/drivers/dri/r300/r300_swtcl.h | 1 + src/mesa/drivers/dri/radeon/common_context.h | 38 +++--- src/mesa/drivers/dri/radeon/common_misc.c | 68 +++++------ src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 3 + src/mesa/drivers/dri/radeon/radeon_screen.c | 1 + 14 files changed, 163 insertions(+), 311 deletions(-) (limited to 'src/mesa/drivers/dri/r200/r200_tcl.c') diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index c2b269880c..c2b5afc385 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -297,6 +297,7 @@ static void r200_init_vtbl(radeonContextPtr radeon) radeon->vtbl.update_draw_buffer = r200UpdateDrawBuffer; radeon->vtbl.emit_cs_header = r200_vtbl_emit_cs_header; radeon->vtbl.emit_state = r200_vtbl_emit_state; + radeon->vtbl.swtcl_flush = r200_swtcl_flush; } @@ -389,7 +390,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, rmesa->radeon.texture_depth = ( screen->cpp == 4 ) ? DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; - rmesa->swtcl.RenderIndex = ~0; + rmesa->radeon.swtcl.RenderIndex = ~0; rmesa->hw.all_dirty = 1; /* Set the maximum texture size small enough that we can guarentee that diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 2df0ca1272..4b7ce5d1ef 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -551,40 +551,12 @@ struct r200_tcl_info { /* r200_swtcl.c */ struct r200_swtcl_info { - GLuint RenderIndex; - - /** - * Size of a hardware vertex. This is calculated when \c ::vertex_attrs is - * installed in the Mesa state vector. - */ - GLuint vertex_size; - - /** - * Attributes instructing the Mesa TCL pipeline where / how to put vertex - * data in the hardware buffer. - */ - struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; - - /** - * Number of elements of \c ::vertex_attrs that are actually used. - */ - GLuint vertex_attr_count; - /** - * Cached pointer to the buffer where Mesa will store vertex data. - */ - GLubyte *verts; - /* Fallback rasterization functions - */ radeon_point_func draw_point; radeon_line_func draw_line; radeon_tri_func draw_tri; - GLuint hw_primitive; - GLenum render_primitive; - GLuint numverts; - /** * Offset of the 4UB color data within a hardware (swtcl) vertex. */ @@ -599,8 +571,6 @@ struct r200_swtcl_info { * Should Mesa project vertex data or will the hardware do it? */ GLboolean needproj; - - struct radeon_bo *bo; }; diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c index 278e00442c..1bf7ef33f8 100644 --- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c +++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c @@ -75,37 +75,29 @@ static void r200_emit_vecfog(GLcontext *ctx, struct radeon_aos *aos, { radeonContextPtr rmesa = RADEON_CONTEXT(ctx); uint32_t *out; - uint32_t bo_size; int i; int size = 1; - memset(aos, 0, sizeof(struct radeon_aos)); if (stride == 0) { - bo_size = size * 4; + radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * 4, 32); count = 1; aos->stride = 0; } else { - bo_size = size * count * 4; + radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * 4, 32); aos->stride = size; } - aos->bo = radeon_bo_open(rmesa->radeonScreen->bom, - 0, bo_size, 32, RADEON_GEM_DOMAIN_GTT, 0); - aos->offset = 0; + aos->components = size; aos->count = count; - radeon_bo_map(aos->bo, 1); out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); for (i = 0; i < count; i++) { out[0] = r200ComputeFogBlendFactor( ctx, *(GLfloat *)data ); out++; data += stride; } - radeon_bo_unmap(aos->bo); } - - /* Emit any changed arrays to new GART memory, re-emit a packet to * update the arrays. */ @@ -230,6 +222,7 @@ after_emit: rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = vfmt1; } + radeon_bo_unmap(rmesa->radeon.dma.current); rmesa->tcl.nr_aos_components = nr; } @@ -240,7 +233,9 @@ void r200ReleaseArrays( GLcontext *ctx, GLuint newinputs ) int i; for (i = 0; i < rmesa->tcl.nr_aos_components; i++) { if (rmesa->tcl.aos[i].bo) { - rmesa->tcl.aos[i].bo = radeon_bo_unref(rmesa->tcl.aos[i].bo); + radeon_bo_unref(rmesa->tcl.aos[i].bo); + rmesa->tcl.aos[i].bo = NULL; } } + radeonReleaseDmaRegion(&rmesa->radeon); } diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index ef725a0efb..a39072d1d2 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -56,27 +56,24 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r200_tcl.h" -static void flush_last_swtcl_prim( GLcontext *ctx ); - - /*********************************************************************** * Initialization ***********************************************************************/ #define EMIT_ATTR( ATTR, STYLE, F0 ) \ do { \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = (ATTR); \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = (STYLE); \ - rmesa->swtcl.vertex_attr_count++; \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \ + rmesa->radeon.swtcl.vertex_attr_count++; \ fmt_0 |= F0; \ } while (0) #define EMIT_PAD( N ) \ do { \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = 0; \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = EMIT_PAD; \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].offset = (N); \ - rmesa->swtcl.vertex_attr_count++; \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N); \ + rmesa->radeon.swtcl.vertex_attr_count++; \ } while (0) static void r200SetVertexFormat( GLcontext *ctx ) @@ -101,7 +98,7 @@ static void r200SetVertexFormat( GLcontext *ctx ) } assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL ); - rmesa->swtcl.vertex_attr_count = 0; + rmesa->radeon.swtcl.vertex_attr_count = 0; /* EMIT_ATTR's must be in order as they tell t_vertex.c how to * build up a hardware vertex. @@ -194,12 +191,12 @@ static void r200SetVertexFormat( GLcontext *ctx ) rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = fmt_0; rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = fmt_1; - rmesa->swtcl.vertex_size = + rmesa->radeon.swtcl.vertex_size = _tnl_install_attrs( ctx, - rmesa->swtcl.vertex_attrs, - rmesa->swtcl.vertex_attr_count, + rmesa->radeon.swtcl.vertex_attrs, + rmesa->radeon.swtcl.vertex_attr_count, NULL, 0 ); - rmesa->swtcl.vertex_size /= 4; + rmesa->radeon.swtcl.vertex_size /= 4; RENDERINPUTS_COPY( rmesa->radeon.tnl_index_bitset, index_bitset ); } } @@ -270,63 +267,27 @@ void r200ChooseVertexState( GLcontext *ctx ) } } - -/* Flush vertices in the current dma region. - */ -static void flush_last_swtcl_prim(GLcontext *ctx) +void r200_swtcl_flush(GLcontext *ctx, uint32_t current_offset) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - if (R200_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s\n", __FUNCTION__); - - rmesa->radeon.dma.flush = NULL; - - radeon_bo_unmap(rmesa->swtcl.bo); - rcommonEnsureCmdBufSpace(rmesa, + rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->hw.max_state_size + (12*sizeof(int)), __FUNCTION__); r200EmitState(rmesa); r200EmitVertexAOS( rmesa, - rmesa->swtcl.vertex_size, - rmesa->swtcl.bo, 0); + rmesa->radeon.swtcl.vertex_size, + rmesa->radeon.dma.current, + current_offset); r200EmitVbufPrim( rmesa, - rmesa->swtcl.hw_primitive, - rmesa->swtcl.numverts); + rmesa->radeon.swtcl.hw_primitive, + rmesa->radeon.swtcl.numverts); - radeon_bo_unref(rmesa->swtcl.bo); - // COMMIT_BATCH(); - rmesa->swtcl.numverts = 0; } - -/* Alloc space in the current dma region. - */ -static INLINE void * -r200AllocDmaLowVerts( r200ContextPtr rmesa, int nverts, int vsize ) -{ - GLuint bytes = vsize * nverts; - - if (rmesa->swtcl.flush) - rmesa->swtcl.flush(rmesa->radeon.glCtx); - - rmesa->swtcl.bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, - 0, bytes, 4, RADEON_GEM_DOMAIN_GTT, 0); - radeon_bo_map(rmesa->swtcl.bo, 1); - if (rmesa->radeon.dma.flush == NULL) { - rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->radeon.dma.flush = flush_last_swtcl_prim; - } - rmesa->swtcl.numverts = nverts; - return rmesa->swtcl.bo->ptr; - - -} - - /**************************************************************************/ @@ -374,11 +335,11 @@ static void r200ResetLineStipple( GLcontext *ctx ); #undef LOCAL_VARS #undef ALLOC_VERTS #define CTX_ARG r200ContextPtr rmesa -#define GET_VERTEX_DWORDS() rmesa->swtcl.vertex_size -#define ALLOC_VERTS( n, size ) r200AllocDmaLowVerts( rmesa, n, size * 4 ) +#define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size +#define ALLOC_VERTS( n, size ) rcommonAllocDmaLowVerts( &rmesa->radeon, n, size * 4 ) #define LOCAL_VARS \ r200ContextPtr rmesa = R200_CONTEXT(ctx); \ - const char *r200verts = (char *)rmesa->swtcl.verts; + const char *r200verts = (char *)rmesa->radeon.swtcl.verts; #define VERT(x) (radeonVertex *)(r200verts + ((x) * vertsize * sizeof(int))) #define VERTEX radeonVertex #define DO_DEBUG_VERTS (1 && (R200_DEBUG & DEBUG_VERTS)) @@ -438,7 +399,7 @@ static struct { #define VERT_Y(_v) _v->v.y #define VERT_Z(_v) _v->v.z #define AREA_IS_CCW( a ) (a < 0) -#define GET_VERTEX(e) (rmesa->swtcl.verts + (e*rmesa->swtcl.vertex_size*sizeof(int))) +#define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + (e*rmesa->radeon.swtcl.vertex_size*sizeof(int))) #define VERT_SET_RGBA( v, c ) \ do { \ @@ -495,7 +456,7 @@ do { \ ***********************************************************************/ #define RASTERIZE(x) r200RasterPrimitive( ctx, reduced_hw_prim(ctx, x) ) -#define RENDER_PRIMITIVE rmesa->swtcl.render_primitive +#define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive #undef TAG #define TAG(x) x #include "tnl_dd/t_dd_unfilled.h" @@ -551,8 +512,8 @@ static void init_rast_tab( void ) #undef LOCAL_VARS #define LOCAL_VARS \ r200ContextPtr rmesa = R200_CONTEXT(ctx); \ - const GLuint vertsize = rmesa->swtcl.vertex_size; \ - const char *r200verts = (char *)rmesa->swtcl.verts; \ + const GLuint vertsize = rmesa->radeon.swtcl.vertex_size; \ + const char *r200verts = (char *)rmesa->radeon.swtcl.verts; \ const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \ const GLboolean stipple = ctx->Line.StippleFlag; \ (void) elt; (void) stipple; @@ -587,7 +548,7 @@ void r200ChooseRenderState( GLcontext *ctx ) if (flags & DD_TRI_LIGHT_TWOSIDE) index |= R200_TWOSIDE_BIT; if (flags & DD_TRI_UNFILLED) index |= R200_UNFILLED_BIT; - if (index != rmesa->swtcl.RenderIndex) { + if (index != rmesa->radeon.swtcl.RenderIndex) { tnl->Driver.Render.Points = rast_tab[index].points; tnl->Driver.Render.Line = rast_tab[index].line; tnl->Driver.Render.ClippedLine = rast_tab[index].line; @@ -604,7 +565,7 @@ void r200ChooseRenderState( GLcontext *ctx ) tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon; } - rmesa->swtcl.RenderIndex = index; + rmesa->radeon.swtcl.RenderIndex = index; } } @@ -618,7 +579,7 @@ static void r200RasterPrimitive( GLcontext *ctx, GLuint hwprim ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - if (rmesa->swtcl.hw_primitive != hwprim) { + if (rmesa->radeon.swtcl.hw_primitive != hwprim) { /* need to disable perspective-correct texturing for point sprites */ if ((hwprim & 0xf) == R200_VF_PRIM_POINT_SPRITES && ctx->Point.PointSprite) { if (rmesa->hw.set.cmd[SET_RE_CNTL] & R200_PERSPECTIVE_ENABLE) { @@ -631,14 +592,14 @@ static void r200RasterPrimitive( GLcontext *ctx, GLuint hwprim ) rmesa->hw.set.cmd[SET_RE_CNTL] |= R200_PERSPECTIVE_ENABLE; } R200_NEWPRIM( rmesa ); - rmesa->swtcl.hw_primitive = hwprim; + rmesa->radeon.swtcl.hw_primitive = hwprim; } } static void r200RenderPrimitive( GLcontext *ctx, GLenum prim ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - rmesa->swtcl.render_primitive = prim; + rmesa->radeon.swtcl.render_primitive = prim; if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED)) r200RasterPrimitive( ctx, reduced_hw_prim(ctx, prim) ); } @@ -691,7 +652,7 @@ void r200Fallback( GLcontext *ctx, GLuint bit, GLboolean mode ) R200_FIREVERTICES( rmesa ); TCL_FALLBACK( ctx, R200_TCL_FALLBACK_RASTER, GL_TRUE ); _swsetup_Wakeup( ctx ); - rmesa->swtcl.RenderIndex = ~0; + rmesa->radeon.swtcl.RenderIndex = ~0; if (R200_DEBUG & DEBUG_FALLBACKS) { fprintf(stderr, "R200 begin rasterization fallback: 0x%x %s\n", bit, getFallbackString(bit)); @@ -776,7 +737,7 @@ r200PointsBitmap( GLcontext *ctx, GLint px, GLint py, vte |= R200_VTX_W0_FMT; vap &= ~R200_VAP_FORCE_W_TO_ONE; - rmesa->swtcl.vertex_size = 5; + rmesa->radeon.swtcl.vertex_size = 5; if ( (rmesa->hw.vtx.cmd[VTX_VTXFMT_0] != fmt_0) || (rmesa->hw.vtx.cmd[VTX_VTXFMT_1] != fmt_1) ) { @@ -944,10 +905,10 @@ void r200InitSwtcl( GLcontext *ctx ) _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12, 36 * sizeof(GLfloat) ); - rmesa->swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf; - rmesa->swtcl.RenderIndex = ~0; - rmesa->swtcl.render_primitive = GL_TRIANGLES; - rmesa->swtcl.hw_primitive = 0; + rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf; + rmesa->radeon.swtcl.RenderIndex = ~0; + rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES; + rmesa->radeon.swtcl.hw_primitive = 0; } diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.h b/src/mesa/drivers/dri/r200/r200_swtcl.h index 91c7c0ff8f..a4051a4b76 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.h +++ b/src/mesa/drivers/dri/r200/r200_swtcl.h @@ -66,5 +66,5 @@ extern void r200PointsBitmap( GLcontext *ctx, GLint px, GLint py, const struct gl_pixelstore_attrib *unpack, const GLubyte *bitmap ); - +void r200_swtcl_flush(GLcontext *ctx, uint32_t current_offset); #endif diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 3c19e330f5..494a8f3d7b 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -157,7 +157,7 @@ static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) if (rmesa->radeon.dma.flush) rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); - rcommonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components)); + rcommonEnsureCmdBufSpace(&rmesa->radeon, AOS_BUFSZ(rmesa->tcl.nr_aos_components), __FUNCTION__); r200EmitAOS( rmesa, rmesa->tcl.nr_aos_components, 0 ); @@ -190,7 +190,7 @@ static void r200EmitPrim( GLcontext *ctx, // fprintf(stderr,"Emit prim %d\n", rmesa->tcl.nr_aos_components); rcommonEnsureCmdBufSpace( &rmesa->radeon, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + - rmesa->hw.max_state_size + VBUF_BUFSZ ); + rmesa->hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ ); r200EmitAOS( rmesa, rmesa->tcl.nr_aos_components, diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index f57952d878..7e707a38b3 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -260,6 +260,7 @@ static void r300_init_vtbl(radeonContextPtr radeon) radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header; radeon->vtbl.emit_state = r300_vtbl_emit_state; radeon->vtbl.flush_vertices = r300_vtbl_flush_vertices; + radeon->vtbl.swtcl_flush = r300_swtcl_flush; } diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 155529a8a6..9e97a136e3 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -658,37 +658,7 @@ struct r300_state { /* r300_swtcl.c */ struct r300_swtcl_info { - GLuint RenderIndex; - - /** - * Size of a hardware vertex. This is calculated when \c ::vertex_attrs is - * installed in the Mesa state vector. - */ - GLuint vertex_size; - - /** - * Attributes instructing the Mesa TCL pipeline where / how to put vertex - * data in the hardware buffer. - */ - struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; - - /** - * Number of elements of \c ::vertex_attrs that are actually used. - */ - GLuint vertex_attr_count; - - /** - * Cached pointer to the buffer where Mesa will store vertex data. - */ - GLubyte *verts; - - /* Fallback rasterization functions - */ - GLuint hw_primitive; - GLenum render_primitive; - GLuint numverts; - - /** + /* * Offset of the 4UB color data within a hardware (swtcl) vertex. */ GLuint coloroffset; @@ -697,8 +667,6 @@ struct r300_swtcl_info { * Offset of the 3UB specular color data within a hardware (swtcl) vertex. */ GLuint specoffset; - - struct radeon_bo *bo; }; diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index ef65fbb127..73e3c51b9a 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -57,24 +57,21 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_ioctl.h" #include "r300_emit.h" -static void flush_last_swtcl_prim( GLcontext *ctx); - - void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset); void r300EmitVbufPrim(r300ContextPtr rmesa, GLuint primitive, GLuint vertex_nr); #define EMIT_ATTR( ATTR, STYLE ) \ do { \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = (ATTR); \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = (STYLE); \ - rmesa->swtcl.vertex_attr_count++; \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \ + rmesa->radeon.swtcl.vertex_attr_count++; \ } while (0) #define EMIT_PAD( N ) \ do { \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = 0; \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = EMIT_PAD; \ - rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].offset = (N); \ - rmesa->swtcl.vertex_attr_count++; \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \ + rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N); \ + rmesa->radeon.swtcl.vertex_attr_count++; \ } while (0) static void r300SetVertexFormat( GLcontext *ctx ) @@ -112,7 +109,7 @@ static void r300SetVertexFormat( GLcontext *ctx ) } assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL ); - rmesa->swtcl.vertex_attr_count = 0; + rmesa->radeon.swtcl.vertex_attr_count = 0; /* EMIT_ATTR's must be in order as they tell t_vertex.c how to * build up a hardware vertex. @@ -222,95 +219,20 @@ static void r300SetVertexFormat( GLcontext *ctx ) rmesa->hw.vof.cmd[R300_VOF_CNTL_0] = r300VAPOutputCntl0(ctx, OutputsWritten); rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = vap_fmt_1; - rmesa->swtcl.vertex_size = + rmesa->radeon.swtcl.vertex_size = _tnl_install_attrs( ctx, - rmesa->swtcl.vertex_attrs, - rmesa->swtcl.vertex_attr_count, + rmesa->radeon.swtcl.vertex_attrs, + rmesa->radeon.swtcl.vertex_attr_count, NULL, 0 ); - rmesa->swtcl.vertex_size /= 4; + rmesa->radeon.swtcl.vertex_size /= 4; RENDERINPUTS_COPY( rmesa->tnl_index_bitset, index_bitset ); R300_STATECHANGE(rmesa, vte); rmesa->hw.vte.cmd[1] = vte; - rmesa->hw.vte.cmd[2] = rmesa->swtcl.vertex_size; -} - - -/* Flush vertices in the current dma region. - */ -static void flush_last_swtcl_prim( GLcontext *ctx ) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct radeon_dma *dma = &rmesa->radeon.dma; - - - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s\n", __FUNCTION__); - dma->flush = NULL; - - if (dma->current) { - GLuint current_offset = dma->current_used; - - assert (dma->current_used + - rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == - dma->current_vertexptr); - - radeon_bo_unmap(dma->current); - if (dma->current_used != dma->current_vertexptr) { - dma->current_used = dma->current_vertexptr; - - rcommonEnsureCmdBufSpace(rmesa, - rmesa->hw.max_state_size + (12*sizeof(int)), - __FUNCTION__); - r300EmitState(rmesa); - r300EmitVertexAOS(rmesa, - rmesa->swtcl.vertex_size, - dma->current, - current_offset); - - r300EmitVbufPrim(rmesa, - rmesa->swtcl.hw_primitive, - rmesa->swtcl.numverts); - r300EmitCacheFlush(rmesa); - COMMIT_BATCH(); - } - radeonReleaseDmaRegion(&rmesa->radeon); - rmesa->swtcl.numverts = 0; - } -} - -/* Alloc space in the current dma region. - */ -static void * -r300AllocDmaLowVerts( r300ContextPtr rmesa, int nverts, int vsize ) -{ - GLuint bytes = vsize * nverts; - void *head; - - if (!rmesa->radeon.dma.current || rmesa->radeon.dma.current_vertexptr + bytes > rmesa->radeon.dma.current->size) { - radeonRefillCurrentDmaRegion( &rmesa->radeon, bytes); - } - - if (!rmesa->radeon.dma.flush) { - rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->radeon.dma.flush = flush_last_swtcl_prim; - } - - ASSERT( vsize == rmesa->swtcl.vertex_size * 4 ); - ASSERT( rmesa->radeon.dma.flush == flush_last_swtcl_prim ); - ASSERT( rmesa->radeon.dma.current_used + - rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == - rmesa->radeon.dma.current_vertexptr ); - -// fprintf(stderr,"current %p %x\n", rmesa->radeon.dma.current->ptr, -// rmesa->radeon.dma.current_vertexptr); - head = (rmesa->radeon.dma.current->ptr + rmesa->radeon.dma.current_vertexptr); - rmesa->radeon.dma.current_vertexptr += bytes; - rmesa->swtcl.numverts += nverts; - return head; + rmesa->hw.vte.cmd[2] = rmesa->radeon.swtcl.vertex_size; } static GLuint reduced_prim[] = { @@ -350,11 +272,11 @@ static void r300RenderPrimitive( GLcontext *ctx, GLenum prim ); #undef LOCAL_VARS #undef ALLOC_VERTS #define CTX_ARG r300ContextPtr rmesa -#define GET_VERTEX_DWORDS() rmesa->swtcl.vertex_size -#define ALLOC_VERTS( n, size ) r300AllocDmaLowVerts( rmesa, n, size * 4 ) +#define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size +#define ALLOC_VERTS( n, size ) rcommonAllocDmaLowVerts( &rmesa->radeon, n, size * 4 ) #define LOCAL_VARS \ r300ContextPtr rmesa = R300_CONTEXT(ctx); \ - const char *r300verts = (char *)rmesa->swtcl.verts; + const char *r300verts = (char *)rmesa->radeon.swtcl.verts; #define VERT(x) (r300Vertex *)(r300verts + ((x) * vertsize * sizeof(int))) #define VERTEX r300Vertex #define DO_DEBUG_VERTS (1 && (RADEON_DEBUG & DEBUG_VERTS)) @@ -413,7 +335,7 @@ static struct { #define VERT_Y(_v) _v->v.y #define VERT_Z(_v) _v->v.z #define AREA_IS_CCW( a ) (a < 0) -#define GET_VERTEX(e) (rmesa->swtcl.verts + (e*rmesa->swtcl.vertex_size*sizeof(int))) +#define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + (e*rmesa->radeon.swtcl.vertex_size*sizeof(int))) /* Only used to pull back colors into vertices (ie, we know color is * floating point). @@ -459,7 +381,7 @@ do { \ ***********************************************************************/ #define RASTERIZE(x) r300RasterPrimitive( ctx, reduced_prim[x] ) -#define RENDER_PRIMITIVE rmesa->swtcl.render_primitive +#define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive #undef TAG #define TAG(x) x #include "tnl_dd/t_dd_unfilled.h" @@ -516,8 +438,8 @@ static void init_rast_tab( void ) #undef LOCAL_VARS #define LOCAL_VARS \ r300ContextPtr rmesa = R300_CONTEXT(ctx); \ - const GLuint vertsize = rmesa->swtcl.vertex_size; \ - const char *r300verts = (char *)rmesa->swtcl.verts; \ + const GLuint vertsize = rmesa->radeon.swtcl.vertex_size; \ + const char *r300verts = (char *)rmesa->radeon.swtcl.verts; \ const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \ const GLboolean stipple = ctx->Line.StippleFlag; \ (void) elt; (void) stipple; @@ -549,7 +471,7 @@ static void r300ChooseRenderState( GLcontext *ctx ) if (flags & DD_TRI_LIGHT_TWOSIDE) index |= R300_TWOSIDE_BIT; if (flags & DD_TRI_UNFILLED) index |= R300_UNFILLED_BIT; - if (index != rmesa->swtcl.RenderIndex) { + if (index != rmesa->radeon.swtcl.RenderIndex) { tnl->Driver.Render.Points = rast_tab[index].points; tnl->Driver.Render.Line = rast_tab[index].line; tnl->Driver.Render.ClippedLine = rast_tab[index].line; @@ -566,7 +488,7 @@ static void r300ChooseRenderState( GLcontext *ctx ) tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon; } - rmesa->swtcl.RenderIndex = index; + rmesa->radeon.swtcl.RenderIndex = index; } } @@ -598,9 +520,9 @@ static void r300RasterPrimitive( GLcontext *ctx, GLuint hwprim ) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - if (rmesa->swtcl.hw_primitive != hwprim) { + if (rmesa->radeon.swtcl.hw_primitive != hwprim) { R300_NEWPRIM( rmesa ); - rmesa->swtcl.hw_primitive = hwprim; + rmesa->radeon.swtcl.hw_primitive = hwprim; } } @@ -608,7 +530,7 @@ static void r300RenderPrimitive(GLcontext *ctx, GLenum prim) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - rmesa->swtcl.render_primitive = prim; + rmesa->radeon.swtcl.render_primitive = prim; if ((prim == GL_TRIANGLES) && (ctx->_TriangleCaps & DD_TRI_UNFILLED)) return; @@ -647,10 +569,10 @@ void r300InitSwtcl(GLcontext *ctx) _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12, 48 * sizeof(GLfloat) ); - rmesa->swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf; - rmesa->swtcl.RenderIndex = ~0; - rmesa->swtcl.render_primitive = GL_TRIANGLES; - rmesa->swtcl.hw_primitive = 0; + rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf; + rmesa->radeon.swtcl.RenderIndex = ~0; + rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES; + rmesa->radeon.swtcl.hw_primitive = 0; _tnl_invalidate_vertex_state( ctx, ~0 ); _tnl_invalidate_vertices( ctx, ~0 ); @@ -698,3 +620,24 @@ void r300EmitVbufPrim(r300ContextPtr rmesa, GLuint primitive, GLuint vertex_nr) OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type); END_BATCH(); } + +void r300_swtcl_flush(GLcontext *ctx, uint32_t current_offset) +{ + r300ContextPtr rmesa = R300_CONTEXT(ctx); + + rcommonEnsureCmdBufSpace(&rmesa->radeon, + rmesa->hw.max_state_size + (12*sizeof(int)), + __FUNCTION__); + r300EmitState(rmesa); + r300EmitVertexAOS(rmesa, + rmesa->radeon.swtcl.vertex_size, + rmesa->radeon.dma.current, + current_offset); + + r300EmitVbufPrim(rmesa, + rmesa->radeon.swtcl.hw_primitive, + rmesa->radeon.swtcl.numverts); + r300EmitCacheFlush(rmesa); + COMMIT_BATCH(); + +} diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.h b/src/mesa/drivers/dri/r300/r300_swtcl.h index 55df53c1ad..23b4ce3469 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.h +++ b/src/mesa/drivers/dri/r300/r300_swtcl.h @@ -42,4 +42,5 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. extern void r300InitSwtcl( GLcontext *ctx ); extern void r300DestroySwtcl( GLcontext *ctx ); +extern void r300_swtcl_flush(GLcontext *ctx, uint32_t current_offset); #endif diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index 1ed33e2aec..90abca0bc1 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -11,6 +11,7 @@ #include "radeon_screen.h" #include "radeon_drm.h" #include "dri_util.h" +#include "tnl/t_vertex.h" /* This union is used to avoid warnings/miscompilation with float to uint32_t casts due to strict-aliasing */ @@ -250,13 +251,19 @@ struct radeon_dma { /* radeon_swtcl.c */ struct radeon_swtcl_info { - struct radeon_bo *bo; - /* Fallback rasterization functions - */ - GLuint hw_primitive; - GLenum render_primitive; - GLuint numverts; + GLuint RenderIndex; + GLuint vertex_size; + GLubyte *verts; + + /* Fallback rasterization functions + */ + GLuint hw_primitive; + GLenum render_primitive; + GLuint numverts; + + struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; + GLuint vertex_attr_count; }; @@ -416,7 +423,7 @@ struct radeon_context { /* Derived state - for r300 only */ struct radeon_state state; - struct radeon_swtcl swtcl; + struct radeon_swtcl_info swtcl; /* Configuration cache */ driOptionCache optionCache; @@ -424,14 +431,15 @@ struct radeon_context { struct radeon_cmdbuf cmdbuf; struct { - void (*get_lock)(radeonContextPtr radeon); - void (*update_viewport_offset)(GLcontext *ctx); - void (*flush)(GLcontext *ctx); - void (*set_all_dirty)(GLcontext *ctx); - void (*update_draw_buffer)(GLcontext *ctx); - void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa); - void (*emit_state)(radeonContextPtr rmesa); - void (*flush_vertices)(radeonContextPtr rmesa); + void (*get_lock)(radeonContextPtr radeon); + void (*update_viewport_offset)(GLcontext *ctx); + void (*flush)(GLcontext *ctx); + void (*set_all_dirty)(GLcontext *ctx); + void (*update_draw_buffer)(GLcontext *ctx); + void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa); + void (*emit_state)(radeonContextPtr rmesa); + void (*flush_vertices)(radeonContextPtr rmesa); + void (*swtcl_flush)(GLcontext *ctx, uint32_t offset); } vtbl; }; diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 1adcefb19a..9044967ac0 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -2420,46 +2420,46 @@ void radeonAllocDmaRegion(radeonContextPtr rmesa, void radeonReleaseDmaRegion(radeonContextPtr rmesa) { - rmesa->dma.nr_released_bufs++; - radeon_bo_unref(rmesa->dma.current); + if (rmesa->dma.current) { + rmesa->dma.nr_released_bufs++; + radeon_bo_unref(rmesa->dma.current); + } rmesa->dma.current = NULL; } -void rcommonEmitVertexAOS(radeonContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset) + +/* Flush vertices in the current dma region. + */ +void rcommon_flush_last_swtcl_prim( GLcontext *ctx ) { - BATCH_LOCALS(rmesa); + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + struct radeon_dma *dma = &rmesa->dma; + - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s: vertex_size %d, offset 0x%x \n", - __FUNCTION__, vertex_size, offset); + if (RADEON_DEBUG & DEBUG_IOCTL) + fprintf(stderr, "%s\n", __FUNCTION__); + dma->flush = NULL; - BEGIN_BATCH(5); - OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, 2); - OUT_BATCH(1); - OUT_BATCH(vertex_size | (vertex_size << 8)); - OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0); - END_BATCH(); -} + if (dma->current) { + GLuint current_offset = dma->current_used; -void rcommonEmitVbufPrim(radeonContextPtr rmesa, GLuint primitive, GLuint vertex_nr) -{ - BATCH_LOCALS(rmesa); - int type, num_verts; + assert (dma->current_used + + rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == + dma->current_vertexptr); - type = r300PrimitiveType(rmesa, primitive); - num_verts = r300NumVerts(rmesa, vertex_nr, primitive); + radeon_bo_unmap(dma->current); + if (dma->current_used != dma->current_vertexptr) { + dma->current_used = dma->current_vertexptr; - BEGIN_BATCH(3); - OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0); - OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type); - END_BATCH(); + rmesa->vtbl.swtcl_flush(ctx, current_offset); + } + radeonReleaseDmaRegion(rmesa); + rmesa->swtcl.numverts = 0; + } } - - - /* Alloc space in the current dma region. */ -static void * +void * rcommonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize ) { GLuint bytes = vsize * nverts; @@ -2471,19 +2471,19 @@ rcommonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize ) if (!rmesa->dma.flush) { rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->dma.flush = flush_last_swtcl_prim; + rmesa->dma.flush = rcommon_flush_last_swtcl_prim; } ASSERT( vsize == rmesa->swtcl.vertex_size * 4 ); - ASSERT( rmesa->radeon.dma.flush == flush_last_swtcl_prim ); - ASSERT( rmesa->radeon.dma.current_used + + ASSERT( rmesa->dma.flush == rcommon_flush_last_swtcl_prim ); + ASSERT( rmesa->dma.current_used + rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == - rmesa->radeon.dma.current_vertexptr ); + rmesa->dma.current_vertexptr ); // fprintf(stderr,"current %p %x\n", rmesa->radeon.dma.current->ptr, // rmesa->radeon.dma.current_vertexptr); - head = (rmesa->radeon.dma.current->ptr + rmesa->radeon.dma.current_vertexptr); - rmesa->radeon.dma.current_vertexptr += bytes; + head = (rmesa->dma.current->ptr + rmesa->dma.current_vertexptr); + rmesa->dma.current_vertexptr += bytes; rmesa->swtcl.numverts += nverts; return head; } diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index 171818db37..5c6d93f573 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -44,6 +44,8 @@ struct cs_manager_legacy { /* hack for scratch stuff */ uint32_t pending_age; uint32_t pending_count; + + }; struct cs_reloc_legacy { @@ -507,3 +509,4 @@ void radeon_cs_manager_legacy_dtor(struct radeon_cs_manager *csm) { free(csm); } + diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 320bf9244b..4ff4267348 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1015,6 +1015,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) free(screen); return NULL; } + return screen; } -- cgit v1.2.3 From abdf1f65d2bafbad8020f1444a01eb18ae9f7159 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 9 Feb 2009 03:50:07 +1000 Subject: r200: cleanup some bits that aren't used --- src/mesa/drivers/dri/r200/r200_context.h | 2 -- src/mesa/drivers/dri/r200/r200_ioctl.h | 26 -------------------------- src/mesa/drivers/dri/r200/r200_maos_arrays.c | 6 ++---- src/mesa/drivers/dri/r200/r200_tcl.c | 1 - 4 files changed, 2 insertions(+), 33 deletions(-) (limited to 'src/mesa/drivers/dri/r200/r200_tcl.c') diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 4b7ce5d1ef..862751bd40 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -535,7 +535,6 @@ struct r200_tcl_info { /* hw can handle 12 components max */ struct radeon_aos aos[12]; - // struct radeon_dma_region *aos_components[12]; GLuint nr_aos_components; GLuint *Elts; @@ -544,7 +543,6 @@ struct r200_tcl_info { int elt_dma_offset; /** Offset into this buffer object, in bytes */ int elt_used; - struct radeon_dma_region vertex_data[15]; }; diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index 30b089658d..6b9e4be30a 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -63,32 +63,6 @@ extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, extern void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset); -extern void r200EmitBlit( r200ContextPtr rmesa, - GLuint color_fmt, - GLuint src_pitch, - GLuint src_offset, - GLuint dst_pitch, - GLuint dst_offset, - GLint srcx, GLint srcy, - GLint dstx, GLint dsty, - GLuint w, GLuint h ); - -extern void r200EmitWait( r200ContextPtr rmesa, GLuint flags ); - -//extern void r200FlushCmdBuf( r200ContextPtr rmesa, const char * ); -//extern int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ); - -extern void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ); - -extern void r200AllocDmaRegion( r200ContextPtr rmesa, - struct radeon_dma_region *region, - int bytes, - int alignment ); - -extern void r200ReleaseDmaRegion( r200ContextPtr rmesa, - struct radeon_dma_region *region, - const char *caller ); - extern void r200Flush( GLcontext *ctx ); extern void r200Finish( GLcontext *ctx ); extern void r200InitIoctlFuncs( struct dd_function_table *functions ); diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c index 716f9037dd..5dbc202330 100644 --- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c +++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c @@ -105,7 +105,6 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) { r200ContextPtr rmesa = R200_CONTEXT( ctx ); struct vertex_buffer *VB = &TNL_CONTEXT( ctx )->vb; - // struct radeon_dma_region **component = rmesa->tcl.aos_components; GLuint nr = 0; GLuint vfmt0 = 0, vfmt1 = 0; GLuint count = VB->Count; @@ -143,7 +142,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) case 3: /* special handling to fix up fog. Will get us into trouble with vbos...*/ assert(attrib == VERT_ATTRIB_FOG); - if (!rmesa->tcl.vertex_data[i].buf) { + if (!rmesa->tcl.aos[i].bo) { if (ctx->VertexProgram._Enabled) rcommon_emit_vector( ctx, &(rmesa->tcl.aos[nr]), @@ -200,7 +199,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) default: assert(0); } - if (!rmesa->tcl.vertex_data[i].buf) { + if (!rmesa->tcl.aos[nr].bo) { rcommon_emit_vector( ctx, &(rmesa->tcl.aos[nr]), (char *)VB->AttribPtr[attrib]->data, @@ -211,7 +210,6 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) after_emit: assert(nr < 12); nr++; - // component[nr++] = &rmesa->tcl.vertex_data[i]; } } diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 494a8f3d7b..4c4df14ef8 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -142,7 +142,6 @@ static GLboolean discrete_prim[0x10] = { static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) { - // fprintf(stderr,"alloc elts %d %d\n", nr, rmesa->tcl.elt_used); if (rmesa->radeon.dma.flush == r200FlushElts && rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) { -- cgit v1.2.3 From 1090d206de011a67d236d8c4ae32d2d42b2f6337 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 12 Feb 2009 21:16:39 +1000 Subject: radeon/r200/r300: another big merge upheavel. This merges lots of the hw state atom emission and firevertices code. it also removes a lot of the extra radeon crap from r300 and merge scissor --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 195 +++++------------------ src/mesa/drivers/dri/r200/r200_context.c | 32 +--- src/mesa/drivers/dri/r200/r200_context.h | 14 +- src/mesa/drivers/dri/r200/r200_ioctl.c | 61 +------ src/mesa/drivers/dri/r200/r200_ioctl.h | 14 +- src/mesa/drivers/dri/r200/r200_state.c | 29 +--- src/mesa/drivers/dri/r200/r200_state_init.c | 15 +- src/mesa/drivers/dri/r200/r200_swtcl.c | 10 +- src/mesa/drivers/dri/r200/r200_tcl.c | 6 +- src/mesa/drivers/dri/r200/r200_tex.c | 2 +- src/mesa/drivers/dri/r300/Makefile | 4 - src/mesa/drivers/dri/r300/r300_cmdbuf.c | 119 ++------------ src/mesa/drivers/dri/r300/r300_context.c | 32 ++-- src/mesa/drivers/dri/r300/r300_context.h | 9 +- src/mesa/drivers/dri/r300/r300_emit.c | 1 - src/mesa/drivers/dri/r300/r300_emit.h | 32 ++-- src/mesa/drivers/dri/r300/r300_ioctl.c | 7 +- src/mesa/drivers/dri/r300/r300_render.c | 2 - src/mesa/drivers/dri/r300/r300_state.c | 16 +- src/mesa/drivers/dri/r300/r300_state.h | 15 +- src/mesa/drivers/dri/r300/r300_swtcl.c | 2 +- src/mesa/drivers/dri/r300/r300_tex.c | 2 +- src/mesa/drivers/dri/r300/r300_texmem.c | 58 ------- src/mesa/drivers/dri/r300/r300_texstate.c | 1 - src/mesa/drivers/dri/r300/radeon_context.c | 75 --------- src/mesa/drivers/dri/r300/radeon_context.h | 43 ----- src/mesa/drivers/dri/r300/radeon_ioctl.c | 69 -------- src/mesa/drivers/dri/r300/radeon_ioctl.h | 57 ------- src/mesa/drivers/dri/r300/radeon_state.c | 109 ------------- src/mesa/drivers/dri/r300/radeon_state.h | 39 ----- src/mesa/drivers/dri/radeon/common_cmdbuf.h | 14 +- src/mesa/drivers/dri/radeon/common_context.h | 27 ++-- src/mesa/drivers/dri/radeon/common_misc.c | 155 ++++++++++++++++-- src/mesa/drivers/dri/radeon/common_misc.h | 5 + src/mesa/drivers/dri/radeon/radeon_context.c | 46 ++---- src/mesa/drivers/dri/radeon/radeon_context.h | 24 +-- src/mesa/drivers/dri/radeon/radeon_ioctl.c | 202 +++--------------------- src/mesa/drivers/dri/radeon/radeon_ioctl.h | 14 +- src/mesa/drivers/dri/radeon/radeon_screen.c | 2 +- src/mesa/drivers/dri/radeon/radeon_state.c | 26 +-- src/mesa/drivers/dri/radeon/radeon_state_init.c | 12 +- src/mesa/drivers/dri/radeon/radeon_swtcl.c | 12 +- src/mesa/drivers/dri/radeon/radeon_tcl.c | 8 +- src/mesa/drivers/dri/radeon/radeon_tex.c | 2 +- 44 files changed, 353 insertions(+), 1266 deletions(-) delete mode 100644 src/mesa/drivers/dri/r300/r300_texmem.c delete mode 100644 src/mesa/drivers/dri/r300/radeon_context.c delete mode 100644 src/mesa/drivers/dri/r300/radeon_ioctl.c delete mode 100644 src/mesa/drivers/dri/r300/radeon_ioctl.h delete mode 100644 src/mesa/drivers/dri/r300/radeon_state.c delete mode 100644 src/mesa/drivers/dri/r300/radeon_state.h (limited to 'src/mesa/drivers/dri/r200/r200_tcl.c') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index eba5d6e019..aa64232a93 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -47,8 +47,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r200_sanity.h" #include "radeon_reg.h" -#define DEBUG_CMDBUF 0 - /* The state atoms will be emitted in the order they appear in the atom list, * so this step is important. */ @@ -58,161 +56,54 @@ void r200SetUpAtomList( r200ContextPtr rmesa ) mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits; - make_empty_list(&rmesa->hw.atomlist); - rmesa->hw.atomlist.name = "atom-list"; - - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.ctx ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.set ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.lin ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.msk ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vpt ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vtx ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vap ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vte ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.msc ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.cst ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.zbs ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tcl ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.msl ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tcg ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.grd ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.fog ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tam ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tf ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.atf ); + make_empty_list(&rmesa->radeon.hw.atomlist); + rmesa->radeon.hw.atomlist.name = "atom-list"; + + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.ctx ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.set ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.lin ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.msk ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpt ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vtx ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vap ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vte ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.msc ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.cst ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.zbs ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcl ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.msl ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcg ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.grd ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.fog ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tam ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tf ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.atf ); for (i = 0; i < mtu; ++i) - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.tex[i] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.tex[i] ); for (i = 0; i < mtu; ++i) - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.cube[i] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.cube[i] ); for (i = 0; i < 6; ++i) - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.pix[i] ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.afs[0] ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.afs[1] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.pix[i] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.afs[0] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.afs[1] ); for (i = 0; i < 8; ++i) - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.lit[i] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.lit[i] ); for (i = 0; i < 3 + mtu; ++i) - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.mat[i] ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.eye ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.glt ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.mat[i] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.eye ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.glt ); for (i = 0; i < 2; ++i) - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.mtl[i] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.mtl[i] ); for (i = 0; i < 6; ++i) - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.ucp[i] ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.spr ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.ptp ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.prf ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.pvs ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vpp[0] ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vpp[1] ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vpi[0] ); - insert_at_tail( &rmesa->hw.atomlist, &rmesa->hw.vpi[1] ); -} - -static void r200SaveHwState( r200ContextPtr rmesa ) -{ - struct radeon_state_atom *atom; - char * dest = rmesa->backup_store.cmd_buf; - uint32_t dwords; - if (R200_DEBUG & DEBUG_STATE) - fprintf(stderr, "%s\n", __FUNCTION__); - - rmesa->backup_store.cmd_used = 0; - - foreach( atom, &rmesa->hw.atomlist ) { - dwords = atom->check( rmesa->radeon.glCtx, atom ); - if ( dwords ) { - int size = atom->cmd_size * 4; - - if (atom->emit) { - (*atom->emit)(rmesa->radeon.glCtx, atom); - } else { - memcpy( dest, atom->cmd, size); - dest += size; - rmesa->backup_store.cmd_used += size; - } - if (R200_DEBUG & DEBUG_STATE) - radeon_print_state_atom( atom ); - } - } - - assert( rmesa->backup_store.cmd_used <= R200_CMD_BUF_SZ ); - if (R200_DEBUG & DEBUG_STATE) - fprintf(stderr, "Returning to r200EmitState\n"); -} - -static INLINE void r200EmitAtoms(r200ContextPtr r200, GLboolean dirty) -{ - BATCH_LOCALS(&r200->radeon); - struct radeon_state_atom *atom; - int dwords; - - /* Emit actual atoms */ - foreach(atom, &r200->hw.atomlist) { - if ((atom->dirty || r200->hw.all_dirty) == dirty) { - dwords = (*atom->check) (r200->radeon.glCtx, atom); - if (dwords) { - if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { - radeon_print_state_atom(atom); - } - if (atom->emit) { - (*atom->emit)(r200->radeon.glCtx, atom); - } else { - BEGIN_BATCH_NO_AUTOSTATE(dwords); - OUT_BATCH_TABLE(atom->cmd, dwords); - END_BATCH(); - } - atom->dirty = GL_FALSE; - } else { - if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { - fprintf(stderr, " skip state %s\n", - atom->name); - } - } - } - } - - COMMIT_BATCH(); -} - -void r200EmitState( r200ContextPtr rmesa ) -{ - char *dest; - int mtu; - struct radeon_state_atom *atom; - uint32_t dwords; - - if (R200_DEBUG & (DEBUG_STATE|DEBUG_PRIMS)) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (rmesa->save_on_next_emit) { - r200SaveHwState(rmesa); - rmesa->save_on_next_emit = GL_FALSE; - } - - if (rmesa->radeon.cmdbuf.cs->cdw && !rmesa->hw.is_dirty && !rmesa->hw.all_dirty) - return; - - mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits; - - /* To avoid going across the entire set of states multiple times, just check - * for enough space for the case of emitting all state, and inline the - * r200AllocCmdBuf code here without all the checks. - */ - rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->hw.max_state_size, __FUNCTION__); - - if (!rmesa->radeon.cmdbuf.cs->cdw) { - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Begin reemit state\n"); - - r200EmitAtoms(rmesa, GL_FALSE); - } - - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Begin dirty state\n"); - - r200EmitAtoms(rmesa, GL_TRUE); - rmesa->hw.is_dirty = GL_FALSE; - rmesa->hw.all_dirty = GL_FALSE; + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.ucp[i] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.spr ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.ptp ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.prf ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.pvs ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpp[0] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpp[1] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpi[0] ); + insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpi[1] ); } /* Fire a section of the retained (indexed_verts) buffer as a regular @@ -227,7 +118,7 @@ void r200EmitVbufPrim( r200ContextPtr rmesa, assert(!(primitive & R200_VF_PRIM_WALK_IND)); - r200EmitState( rmesa ); + radeonEmitState(&rmesa->radeon); if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS)) fprintf(stderr, "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__, @@ -313,7 +204,7 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, assert((primitive & R200_VF_PRIM_WALK_IND)); - r200EmitState( rmesa ); + radeonEmitState(&rmesa->radeon); rmesa->tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, 0, R200_ELT_BUF_SZ, 4, diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 00274fbd43..1f5a9f2427 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -61,6 +61,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r200_maos.h" #include "r200_vertprog.h" +#include "radeon_span.h" + #define need_GL_ARB_multisample #define need_GL_ARB_texture_compression #define need_GL_ARB_vertex_buffer_object @@ -259,43 +261,17 @@ static void r200_get_lock(radeonContextPtr radeon) } } - -static void r200_vtbl_flush(GLcontext *ctx) -{ - R200_FIREVERTICES(R200_CONTEXT(ctx)); -} - -static void r200_vtbl_flush_vertices(radeonContextPtr rmesa) -{ - R200_FIREVERTICES(((r200ContextPtr)rmesa)); -} - -static void r200_vtbl_set_all_dirty(GLcontext *ctx) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - rmesa->hw.all_dirty = GL_TRUE; -} - static void r200_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) { } -static void r200_vtbl_emit_state(radeonContextPtr rmesa) -{ - r200EmitState((r200ContextPtr)rmesa); -} - static void r200_init_vtbl(radeonContextPtr radeon) { radeon->vtbl.get_lock = r200_get_lock; radeon->vtbl.update_viewport_offset = r200UpdateViewportOffset; - radeon->vtbl.flush = r200_vtbl_flush; - radeon->vtbl.flush_vertices = r200_vtbl_flush_vertices; - radeon->vtbl.set_all_dirty = r200_vtbl_set_all_dirty; radeon->vtbl.update_draw_buffer = r200UpdateDrawBuffer; radeon->vtbl.emit_cs_header = r200_vtbl_emit_cs_header; - radeon->vtbl.emit_state = r200_vtbl_emit_state; radeon->vtbl.swtcl_flush = r200_swtcl_flush; } @@ -390,7 +366,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; rmesa->radeon.swtcl.RenderIndex = ~0; - rmesa->hw.all_dirty = 1; + rmesa->radeon.hw.all_dirty = 1; /* Set the maximum texture size small enough that we can guarentee that * all texture units can bind a maximal texture and have all of them in @@ -565,7 +541,7 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) /* check if we're deleting the currently bound context */ if (rmesa == current) { - R200_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); _mesa_make_current(NULL, NULL, NULL); } diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 862751bd40..96f47ea92b 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -469,9 +469,6 @@ struct r200_texture_state { struct r200_hw_state { - /* Head of the linked list of state atoms. */ - struct radeon_state_atom atomlist; - /* Hardware state, stored as cmdbuf commands: * -- Need to doublebuffer for * - reviving state after loss of context @@ -512,9 +509,6 @@ struct r200_hw_state { struct radeon_state_atom atf; struct radeon_state_atom spr; struct radeon_state_atom ptp; - - int max_state_size; /* Number of bytes necessary for a full state emit. */ - GLboolean is_dirty, all_dirty; }; struct r200_state { @@ -600,16 +594,10 @@ struct r200_context { */ struct radeon_ioctl ioctl; struct radeon_store store; - /* A full state emit as of the first state emit in the main store, in case - * the context is lost. - */ - struct radeon_store backup_store; /* Clientdata textures; */ - GLuint prefer_gart_client_texturing; - - GLboolean save_on_next_emit; + GLuint prefer_gart_client_texturing; /* TCL stuff */ diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index 0b7f664457..8f64c8c6d9 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -57,34 +57,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define R200_TIMEOUT 512 #define R200_IDLE_RETRY 16 - -/* At this point we were in FlushCmdBufLocked but we had lost our context, so - * we need to unwire our current cmdbuf, hook the one with the saved state in - * it, flush it, and then put the current one back. This is so commands at the - * start of a cmdbuf can rely on the state being kept from the previous one. - */ -static void r200BackUpAndEmitLostStateLocked( r200ContextPtr rmesa ) -{ - GLuint nr_released_bufs; - struct radeon_store saved_store; - - if (rmesa->backup_store.cmd_used == 0) - return; - - if (R200_DEBUG & DEBUG_STATE) - fprintf(stderr, "Emitting backup state on lost context\n"); - - rmesa->radeon.lost_context = GL_FALSE; - - nr_released_bufs = rmesa->radeon.dma.nr_released_bufs; - saved_store = rmesa->store; - rmesa->radeon.dma.nr_released_bufs = 0; - rmesa->store = rmesa->backup_store; - rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); - rmesa->radeon.dma.nr_released_bufs = nr_released_bufs; - rmesa->store = saved_store; -} - static void r200UserClear(GLcontext *ctx, GLuint flags) { if (flags & (RADEON_FRONT | RADEON_BACK)) { @@ -291,36 +263,9 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) else r200KernelClear(ctx, flags); - rmesa->hw.all_dirty = GL_TRUE; -} - - -void r200Flush( GLcontext *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT( ctx ); - - if (R200_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (rmesa->radeon.dma.flush) - rmesa->radeon.dma.flush( ctx ); - - r200EmitState( rmesa ); - - if (rmesa->radeon.cmdbuf.cs->cdw) - rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); + rmesa->radeon.hw.all_dirty = GL_TRUE; } -/* Make sure all commands have been sent to the hardware and have - * completed processing. - */ -void r200Finish( GLcontext *ctx ) -{ - r200Flush( ctx ); - radeon_common_finish(ctx); -} - - /* This version of AllocateMemoryMESA allocates only GART memory, and * only does so after the point at which the driver has been * initialized. @@ -458,7 +403,7 @@ GLuint r200GartOffsetFromVirtual( r200ContextPtr rmesa, const GLvoid *pointer ) void r200InitIoctlFuncs( struct dd_function_table *functions ) { functions->Clear = r200Clear; - functions->Finish = r200Finish; - functions->Flush = r200Flush; + functions->Finish = radeonFinish; + functions->Flush = radeonFlush; } diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index 316acef459..6b114971c3 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -47,7 +47,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "common_cmdbuf.h" -extern void r200EmitState( r200ContextPtr rmesa ); extern void r200EmitVertexAOS( r200ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, @@ -101,7 +100,7 @@ do { \ do { \ R200_NEWPRIM( rmesa ); \ rmesa->hw.ATOM.dirty = GL_TRUE; \ - rmesa->hw.is_dirty = GL_TRUE; \ + rmesa->radeon.hw.is_dirty = GL_TRUE; \ } while (0) #define R200_DB_STATE( ATOM ) \ @@ -116,7 +115,7 @@ static INLINE int R200_DB_STATECHANGE( GLuint *tmp; R200_NEWPRIM( rmesa ); atom->dirty = GL_TRUE; - rmesa->hw.is_dirty = GL_TRUE; + rmesa->radeon.hw.is_dirty = GL_TRUE; tmp = atom->cmd; atom->cmd = atom->lastcmd; atom->lastcmd = tmp; @@ -127,15 +126,6 @@ static INLINE int R200_DB_STATECHANGE( } -/* Fire the buffered vertices no matter what. - */ -#define R200_FIREVERTICES( rmesa ) \ -do { \ - if ( rmesa->radeon.cmdbuf.cs->cdw || rmesa->radeon.dma.flush ) { \ - r200Flush( rmesa->radeon.glCtx ); \ - } \ -} while (0) - /* Command lengths. Note that any time you ensure ELTS_BUFSZ or VBUF_BUFSZ * are available, you will also be adding an rmesa->state.max_state_size because * r200EmitState is called from within r200EmitVbufPrim and r200FlushElts. diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index f3d809d62c..5c41018cdb 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -524,25 +524,6 @@ static void r200Fogfv( GLcontext *ctx, GLenum pname, const GLfloat *param ) } } - -/* ============================================================= - * Scissoring - */ - - -static void r200Scissor( GLcontext *ctx, - GLint x, GLint y, GLsizei w, GLsizei h ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - if ( ctx->Scissor.Enabled ) { - R200_FIREVERTICES( rmesa ); /* don't pipeline cliprect changes */ - radeonUpdateScissor( ctx ); - } - -} - - /* ============================================================= * Culling */ @@ -787,7 +768,7 @@ static void r200PolygonStipple( GLcontext *ctx, const GLubyte *mask ) /* TODO: push this into cmd mechanism */ - R200_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); LOCK_HARDWARE( &rmesa->radeon ); /* FIXME: Use window x,y offsets into stipple RAM. @@ -1638,7 +1619,7 @@ void r200UpdateWindow( GLcontext *ctx ) float_ui32_type sz = { v[MAT_SZ] * rmesa->radeon.state.depth.scale }; float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale }; - R200_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); R200_STATECHANGE( rmesa, vpt ); rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = sx.ui32; @@ -1783,7 +1764,7 @@ static void r200DrawBuffer( GLcontext *ctx, GLenum mode ) fprintf(stderr, "%s %s\n", __FUNCTION__, _mesa_lookup_enum_by_nr( mode )); - R200_FIREVERTICES(rmesa); /* don't pipeline cliprect changes */ + radeon_firevertices(&rmesa->radeon); /* don't pipeline cliprect changes */ if (ctx->DrawBuffer->_NumColorDrawBuffers != 1) { /* 0 (GL_NONE) buffers or multiple color drawing buffers */ @@ -2057,7 +2038,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state ) } case GL_SCISSOR_TEST: - R200_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); rmesa->radeon.state.scissor.enabled = state; radeonUpdateScissor( ctx ); break; @@ -2575,7 +2556,7 @@ void r200InitStateFuncs( struct dd_function_table *functions ) functions->PointParameterfv = r200PointParameter; functions->PointSize = r200PointSize; functions->RenderMode = r200RenderMode; - functions->Scissor = r200Scissor; + functions->Scissor = radeonScissor; functions->ShadeModel = r200ShadeModel; functions->StencilFuncSeparate = r200StencilFuncSeparate; functions->StencilMaskSeparate = r200StencilMaskSeparate; diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 1e904ea432..d11baacae9 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -46,8 +46,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_buffer.h" #include "radeon_mipmap_tree.h" #include "radeon_cs.h" -#include "common_context.h" -#include "common_cmdbuf.h" +#include "common_misc.h" #include "r200_context.h" #include "r200_ioctl.h" #include "r200_state.h" @@ -177,8 +176,8 @@ void r200PrintDirty( r200ContextPtr rmesa, const char *msg ) fprintf(stderr, msg); fprintf(stderr, ": "); - foreach(l, &rmesa->hw.atomlist) { - if (l->dirty || rmesa->hw.all_dirty) + foreach(l, &rmesa->radeon.hw.atomlist) { + if (l->dirty || rmesa->radeon.hw.all_dirty) fprintf(stderr, "%s, ", l->name); } @@ -649,7 +648,7 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->state.pixel.readPitch = rmesa->radeon.state.color.drawPitch; #endif - rmesa->hw.max_state_size = 0; + rmesa->radeon.hw.max_state_size = 0; #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \ do { \ @@ -660,7 +659,7 @@ void r200InitState( r200ContextPtr rmesa ) rmesa->hw.ATOM.idx = IDX; \ rmesa->hw.ATOM.check = check_##CHK; \ rmesa->hw.ATOM.dirty = GL_FALSE; \ - rmesa->hw.max_state_size += SZ * sizeof(int); \ + rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \ } while (0) @@ -1405,7 +1404,7 @@ void r200InitState( r200ContextPtr rmesa ) r200LightingSpaceChange( ctx ); - rmesa->hw.all_dirty = GL_TRUE; + rmesa->radeon.hw.all_dirty = GL_TRUE; - rcommonInitCmdBuf(&rmesa->radeon, rmesa->hw.max_state_size); + rcommonInitCmdBuf(&rmesa->radeon); } diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index a39072d1d2..df786561e1 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -204,8 +204,6 @@ static void r200SetVertexFormat( GLcontext *ctx ) static void r200RenderStart( GLcontext *ctx ) { - r200ContextPtr rmesa = R200_CONTEXT( ctx ); - r200SetVertexFormat( ctx ); } @@ -271,11 +269,11 @@ void r200_swtcl_flush(GLcontext *ctx, uint32_t current_offset) { r200ContextPtr rmesa = R200_CONTEXT(ctx); rcommonEnsureCmdBufSpace(&rmesa->radeon, - rmesa->hw.max_state_size + (12*sizeof(int)), + rmesa->radeon.hw.max_state_size + (12*sizeof(int)), __FUNCTION__); - r200EmitState(rmesa); + radeonEmitState(&rmesa->radeon); r200EmitVertexAOS( rmesa, rmesa->radeon.swtcl.vertex_size, rmesa->radeon.dma.current, @@ -649,7 +647,7 @@ void r200Fallback( GLcontext *ctx, GLuint bit, GLboolean mode ) if (mode) { rmesa->radeon.Fallback |= bit; if (oldfallback == 0) { - R200_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); TCL_FALLBACK( ctx, R200_TCL_FALLBACK_RASTER, GL_TRUE ); _swsetup_Wakeup( ctx ); rmesa->radeon.swtcl.RenderIndex = ~0; @@ -914,6 +912,4 @@ void r200InitSwtcl( GLcontext *ctx ) void r200DestroySwtcl( GLcontext *ctx ) { - r200ContextPtr rmesa = R200_CONTEXT(ctx); - } diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 4c4df14ef8..8e0fb14e70 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -123,7 +123,7 @@ static GLboolean discrete_prim[0x10] = { #define RESET_STIPPLE() do { \ R200_STATECHANGE( rmesa, lin ); \ - r200EmitState( rmesa ); \ + radeonEmitState(&rmesa->radeon); \ } while (0) #define AUTO_STIPPLE( mode ) do { \ @@ -134,7 +134,7 @@ static GLboolean discrete_prim[0x10] = { else \ rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \ ~R200_LINE_PATTERN_AUTO_RESET; \ - r200EmitState( rmesa ); \ + radeonEmitState(&rmesa->radeon); \ } while (0) @@ -189,7 +189,7 @@ static void r200EmitPrim( GLcontext *ctx, // fprintf(stderr,"Emit prim %d\n", rmesa->tcl.nr_aos_components); rcommonEnsureCmdBufSpace( &rmesa->radeon, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + - rmesa->hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ ); + rmesa->radeon.hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ ); r200EmitAOS( rmesa, rmesa->tcl.nr_aos_components, diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c index cf0a32bf89..c0d1723c77 100644 --- a/src/mesa/drivers/dri/r200/r200_tex.c +++ b/src/mesa/drivers/dri/r200/r200_tex.c @@ -420,7 +420,7 @@ static void r200DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) if (rmesa) { int i; - R200_FIREVERTICES(rmesa); + radeon_firevertices(&rmesa->radeon); for ( i = 0 ; i < rmesa->radeon.glCtx->Const.MaxTextureUnits ; i++ ) { if ( t == rmesa->state.texture.unit[i].texobj ) { rmesa->state.texture.unit[i].texobj = NULL; diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index 4042005d03..abdd1da490 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -26,11 +26,7 @@ DRIVER_SOURCES = \ radeon_screen.c \ common_lock.c \ common_misc.c \ - radeon_context.c \ - radeon_ioctl.c \ radeon_span.c \ - radeon_state.c \ - r300_context.c \ r300_ioctl.c \ r300_cmdbuf.c \ r300_state.c \ diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 303efe3ada..d6acb39d9f 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -45,7 +45,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_drm.h" #include "radeon_buffer.h" -#include "radeon_ioctl.h" #include "r300_context.h" #include "r300_ioctl.h" #include "radeon_reg.h" @@ -61,111 +60,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200 # define RADEON_ONE_REG_WR (1 << 15) -// Set this to 1 for extremely verbose debugging of command buffers -#define DEBUG_CMDBUF 0 - /** # of dwords reserved for additional instructions that may need to be written * during flushing. */ #define SPACE_FOR_FLUSHING 4 -static void r300PrintStateAtom(r300ContextPtr r300, - struct radeon_state_atom *state) -{ - int i; - int dwords = (*state->check) (r300->radeon.glCtx, state); - - fprintf(stderr, " emit %s %d/%d\n", state->name, dwords, state->cmd_size); - - if (RADEON_DEBUG & DEBUG_VERBOSE) { - for (i = 0; i < dwords; i++) { - fprintf(stderr, " %s[%d]: %08x\n", - state->name, i, state->cmd[i]); - } - } -} - -/** - * Emit all atoms with a dirty field equal to dirty. - * - * The caller must have ensured that there is enough space in the command - * buffer. - */ -static INLINE void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty) -{ - BATCH_LOCALS(&r300->radeon); - struct radeon_state_atom *atom; - int dwords; - - cp_wait(r300, R300_WAIT_3D | R300_WAIT_3D_CLEAN); - BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH(cmdpacket0(r300->radeon.radeonScreen, R300_TX_INVALTAGS, 1)); - OUT_BATCH(R300_TX_FLUSH); - END_BATCH(); - end_3d(r300); - - /* Emit actual atoms */ - foreach(atom, &r300->hw.atomlist) { - if ((atom->dirty || r300->hw.all_dirty) == dirty) { - dwords = (*atom->check) (r300->radeon.glCtx, atom); - if (dwords) { - if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { - r300PrintStateAtom(r300, atom); - } - if (atom->emit) { - (*atom->emit)(r300->radeon.glCtx, atom); - } else { - BEGIN_BATCH_NO_AUTOSTATE(dwords); - OUT_BATCH_TABLE(atom->cmd, dwords); - END_BATCH(); - } - atom->dirty = GL_FALSE; - } else { - if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { - fprintf(stderr, " skip state %s\n", - atom->name); - } - } - } - } - - COMMIT_BATCH(); -} - -/** - * Copy dirty hardware state atoms into the command buffer. - * - * We also copy out clean state if we're at the start of a buffer. That makes - * it easy to recover from lost contexts. - */ -void r300EmitState(r300ContextPtr r300) -{ - if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_PRIMS)) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (r300->radeon.cmdbuf.cs->cdw && !r300->hw.is_dirty && !r300->hw.all_dirty) - return; - - /* To avoid going across the entire set of states multiple times, just check - * for enough space for the case of emitting all state. - */ - rcommonEnsureCmdBufSpace(&r300->radeon, r300->hw.max_state_size, __FUNCTION__); - - if (!r300->radeon.cmdbuf.cs->cdw) { - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Begin reemit state\n"); - - r300EmitAtoms(r300, GL_FALSE); - } - - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Begin dirty state\n"); - - r300EmitAtoms(r300, GL_TRUE); - r300->hw.is_dirty = GL_FALSE; - r300->hw.all_dirty = GL_FALSE; -} - static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt) { if (r300->radeon.radeonScreen->kernel_mm) { @@ -405,8 +304,8 @@ int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom) r300->hw.ATOM.idx = (IDX); \ r300->hw.ATOM.check = check_##CHK; \ r300->hw.ATOM.dirty = GL_FALSE; \ - r300->hw.max_state_size += (SZ); \ - insert_at_tail(&r300->hw.atomlist, &r300->hw.ATOM); \ + r300->radeon.hw.max_state_size += (SZ); \ + insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \ } while (0) /** * Allocate memory for the command buffer and initialize the state atom @@ -425,7 +324,7 @@ void r300InitCmdBuf(r300ContextPtr r300) if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) is_r500 = 1; - r300->hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */ + r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */ mtu = r300->radeon.glCtx->Const.MaxTextureUnits; if (RADEON_DEBUG & DEBUG_TEXTURE) { @@ -433,8 +332,8 @@ void r300InitCmdBuf(r300ContextPtr r300) } /* Setup the atom linked list */ - make_empty_list(&r300->hw.atomlist); - r300->hw.atomlist.name = "atom-list"; + make_empty_list(&r300->radeon.hw.atomlist); + r300->radeon.hw.atomlist.name = "atom-list"; /* Initialize state atoms */ ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0); @@ -708,10 +607,10 @@ void r300InitCmdBuf(r300ContextPtr r300) r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0); - r300->hw.is_dirty = GL_TRUE; - r300->hw.all_dirty = GL_TRUE; + r300->radeon.hw.is_dirty = GL_TRUE; + r300->radeon.hw.all_dirty = GL_TRUE; - rcommonInitCmdBuf(&r300->radeon, r300->hw.max_state_size); + rcommonInitCmdBuf(&r300->radeon); } /** @@ -721,7 +620,7 @@ void r300DestroyCmdBuf(r300ContextPtr r300) { struct radeon_state_atom *atom; - foreach(atom, &r300->hw.atomlist) { + foreach(atom, &r300->radeon.hw.atomlist) { FREE(atom->cmd); } diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 3e47888e45..e4dc37debc 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -55,7 +55,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drivers/common/driverfuncs.h" -#include "radeon_ioctl.h" #include "radeon_span.h" #include "r300_context.h" #include "r300_cmdbuf.h" @@ -198,22 +197,6 @@ static void r300_get_lock(radeonContextPtr rmesa) } } -static void r300_vtbl_flush(GLcontext *ctx) -{ - r300Flush(ctx); -} - -static void r300_vtbl_set_all_dirty(GLcontext *ctx) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - rmesa->hw.all_dirty = GL_TRUE; -} - -static void r300_vtbl_emit_state(radeonContextPtr rmesa) -{ - r300EmitState((r300ContextPtr)rmesa); -} - static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) { /* please flush pipe do all pending work */ @@ -243,22 +226,25 @@ static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmes R300_WAIT_3D | R300_WAIT_3D_CLEAN)); } -static void r300_vtbl_flush_vertices(radeonContextPtr rmesa) +static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon) { - R300_FIREVERTICES(((r300ContextPtr)rmesa)); + BATCH_LOCALS(radeon); + cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN); + BEGIN_BATCH_NO_AUTOSTATE(2); + OUT_BATCH(cmdpacket0(radeon->radeonScreen, R300_TX_INVALTAGS, 1)); + OUT_BATCH(R300_TX_FLUSH); + END_BATCH(); + end_3d(radeon); } static void r300_init_vtbl(radeonContextPtr radeon) { radeon->vtbl.get_lock = r300_get_lock; radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset; - radeon->vtbl.flush = r300_vtbl_flush; - radeon->vtbl.set_all_dirty = r300_vtbl_set_all_dirty; radeon->vtbl.update_draw_buffer = r300UpdateDrawBuffer; radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header; - radeon->vtbl.emit_state = r300_vtbl_emit_state; - radeon->vtbl.flush_vertices = r300_vtbl_flush_vertices; radeon->vtbl.swtcl_flush = r300_swtcl_flush; + radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms; } diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 9e97a136e3..75393bcd14 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -42,6 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_drm.h" #include "dri_util.h" #include "texmem.h" +#include "common_context.h" #include "radeon_context.h" #include "radeon_bo.h" @@ -53,7 +54,7 @@ struct r300_context; typedef struct r300_context r300ContextRec; typedef struct r300_context *r300ContextPtr; -#include "radeon_lock.h" + #include "main/mm.h" /* From http://gcc. gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html . @@ -304,12 +305,6 @@ struct r300_texture_state { * Cache for hardware register state. */ struct r300_hw_state { - struct radeon_state_atom atomlist; - - GLboolean is_dirty; - GLboolean all_dirty; - int max_state_size; /* in dwords */ - struct radeon_state_atom vpt; /* viewport (1D98) */ struct radeon_state_atom vap_cntl; struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */ diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index 4a18397aa8..20afae6a09 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -46,7 +46,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/t_context.h" #include "r300_context.h" -#include "radeon_ioctl.h" #include "r300_state.h" #include "r300_emit.h" #include "r300_ioctl.h" diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h index 290bd614c5..6c02646605 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.h +++ b/src/mesa/drivers/dri/r300/r300_emit.h @@ -146,36 +146,36 @@ static INLINE uint32_t cmdpacify(struct radeon_screen *rscrn) /** * Must be sent to switch to 2d commands */ -void static INLINE end_3d(r300ContextPtr rmesa) +void static INLINE end_3d(radeonContextPtr radeon) { - BATCH_LOCALS(&rmesa->radeon); + BATCH_LOCALS(radeon); - if (!rmesa->radeon.radeonScreen->kernel_mm) { - BEGIN_BATCH_NO_AUTOSTATE(1); - OUT_BATCH(cmdpacify(rmesa->radeon.radeonScreen)); - END_BATCH(); - } + if (!radeon->radeonScreen->kernel_mm) { + BEGIN_BATCH_NO_AUTOSTATE(1); + OUT_BATCH(cmdpacify(radeon->radeonScreen)); + END_BATCH(); + } } void static INLINE cp_delay(r300ContextPtr rmesa, unsigned short count) { BATCH_LOCALS(&rmesa->radeon); - if (!rmesa->radeon.radeonScreen->kernel_mm) { - BEGIN_BATCH_NO_AUTOSTATE(1); - OUT_BATCH(cmdcpdelay(rmesa->radeon.radeonScreen, count)); - END_BATCH(); - } + if (!rmesa->radeon.radeonScreen->kernel_mm) { + BEGIN_BATCH_NO_AUTOSTATE(1); + OUT_BATCH(cmdcpdelay(rmesa->radeon.radeonScreen, count)); + END_BATCH(); + } } -void static INLINE cp_wait(r300ContextPtr rmesa, unsigned char flags) +void static INLINE cp_wait(radeonContextPtr radeon, unsigned char flags) { - BATCH_LOCALS(&rmesa->radeon); + BATCH_LOCALS(radeon); uint32_t wait_until; - if (!rmesa->radeon.radeonScreen->kernel_mm) { + if (!radeon->radeonScreen->kernel_mm) { BEGIN_BATCH_NO_AUTOSTATE(1); - OUT_BATCH(cmdwait(rmesa->radeon.radeonScreen, flags)); + OUT_BATCH(cmdwait(radeon->radeonScreen, flags)); END_BATCH(); } else { switch(flags) { diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index f07252fbe2..ee33415095 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -48,7 +48,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_buffer.h" #include "r300_context.h" -#include "radeon_ioctl.h" #include "r300_ioctl.h" #include "r300_cmdbuf.h" #include "r300_state.h" @@ -94,8 +93,8 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, } /* TODO in bufmgr */ - cp_wait(r300, R300_WAIT_3D | R300_WAIT_3D_CLEAN); - end_3d(rmesa); + cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN); + end_3d(&rmesa->radeon); if (flags & CLEARBUFFER_COLOR) { assert(rrb != 0); @@ -195,7 +194,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, } r300EmitCacheFlush(rmesa); - cp_wait(rmesa, R300_WAIT_3D | R300_WAIT_3D_CLEAN); + cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN); R300_STATECHANGE(r300, cb); R300_STATECHANGE(r300, cmk); diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 23d068c339..393bf754ff 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -66,8 +66,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/t_vp_build.h" #include "radeon_reg.h" #include "radeon_macros.h" -#include "radeon_ioctl.h" -#include "radeon_state.h" #include "r300_context.h" #include "r300_ioctl.h" #include "r300_state.h" diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index bdb67a1afd..1e7d9af11d 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -53,8 +53,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "vbo/vbo.h" #include "tnl/tnl.h" -#include "radeon_ioctl.h" -#include "radeon_state.h" #include "radeon_buffer.h" #include "r300_context.h" #include "r300_ioctl.h" @@ -1087,7 +1085,7 @@ static void r300UpdateWindow(GLcontext * ctx) GLfloat sz = v[MAT_SZ] * rmesa->radeon.state.depth.scale; GLfloat tz = v[MAT_TZ] * rmesa->radeon.state.depth.scale; - R300_FIREVERTICES(rmesa); + radeon_firevertices(&rmesa->radeon); R300_STATECHANGE(rmesa, vpt); rmesa->hw.vpt.cmd[R300_VPT_XSCALE] = r300PackFloat32(sx); @@ -2112,6 +2110,7 @@ static void r300SetupVertexProgram(r300ContextPtr rmesa) */ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) { + r300ContextPtr rmesa = R300_CONTEXT(ctx); if (RADEON_DEBUG & DEBUG_STATE) fprintf(stderr, "%s( %s = %s )\n", __FUNCTION__, _mesa_lookup_enum_by_nr(cap), @@ -2157,8 +2156,12 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) case GL_POLYGON_OFFSET_FILL: r300SetPolygonOffsetState(ctx, state); break; + case GL_SCISSOR_TEST: + radeon_firevertices(&rmesa->radeon); + rmesa->radeon.state.scissor.enabled = state; + radeonUpdateScissor( ctx ); + break; default: - radeonEnable(ctx, cap, state); break; } } @@ -2405,7 +2408,7 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.vps.cmd[R300_VPS_ZERO_3] = 0; } - r300->hw.all_dirty = GL_TRUE; + r300->radeon.hw.all_dirty = GL_TRUE; } void r300UpdateShaders(r300ContextPtr rmesa) @@ -2747,7 +2750,7 @@ static void r300DrawBuffer( GLcontext *ctx, GLenum mode ) fprintf(stderr, "%s %s\n", __FUNCTION__, _mesa_lookup_enum_by_nr( mode )); - R300_FIREVERTICES(rmesa); /* don't pipeline cliprect changes */ + radeon_firevertices(&rmesa->radeon); /* don't pipeline cliprect changes */ radeonSetCliprects( &rmesa->radeon ); radeonUpdatePageFlipping(&rmesa->radeon); @@ -2803,6 +2806,7 @@ void r300InitStateFuncs(struct dd_function_table *functions) functions->RenderMode = r300RenderMode; functions->ClipPlane = r300ClipPlane; + functions->Scissor = radeonScissor; functions->DrawBuffer = r300DrawBuffer; functions->ReadBuffer = r300ReadBuffer; diff --git a/src/mesa/drivers/dri/r300/r300_state.h b/src/mesa/drivers/dri/r300/r300_state.h index 4d0a25fb0e..247a20ee51 100644 --- a/src/mesa/drivers/dri/r300/r300_state.h +++ b/src/mesa/drivers/dri/r300/r300_state.h @@ -39,26 +39,17 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define R300_NEWPRIM( rmesa ) \ do { \ + if ( rmesa->radeon.dma.flush ) \ + rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \ } while (0) #define R300_STATECHANGE(r300, atom) \ do { \ R300_NEWPRIM(r300); \ r300->hw.atom.dirty = GL_TRUE; \ - r300->hw.is_dirty = GL_TRUE; \ + r300->radeon.hw.is_dirty = GL_TRUE; \ } while(0) -#define R300_PRINT_STATE(r300, atom) \ - r300PrintStateAtom(r300, &r300->hw.atom) - -/* Fire the buffered vertices no matter what. - TODO: This has not been implemented yet - */ -#define R300_FIREVERTICES( r300 ) \ - do { \ - r300Flush( (r300)->radeon.glCtx ); \ - } while (0) - // r300_state.c extern int future_hw_tcl_on; void _tnl_UpdateFixedFunctionProgram (GLcontext * ctx); diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 98208cd77e..34e752178a 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -626,7 +626,7 @@ void r300_swtcl_flush(GLcontext *ctx, uint32_t current_offset) r300ContextPtr rmesa = R300_CONTEXT(ctx); rcommonEnsureCmdBufSpace(&rmesa->radeon, - rmesa->hw.max_state_size + (12*sizeof(int)), + rmesa->radeon.hw.max_state_size + (12*sizeof(int)), __FUNCTION__); r300EmitState(rmesa); r300EmitVertexAOS(rmesa, diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c index 989aa462ae..e316e2d822 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.c +++ b/src/mesa/drivers/dri/r300/r300_tex.c @@ -263,7 +263,7 @@ static void r300DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) if (rmesa) { int i; - R300_FIREVERTICES(rmesa); + radeon_firevertices(&rmesa->radeon); for(i = 0; i < R300_MAX_TEXTURE_UNITS; ++i) if (rmesa->hw.textures[i] == t) diff --git a/src/mesa/drivers/dri/r300/r300_texmem.c b/src/mesa/drivers/dri/r300/r300_texmem.c deleted file mode 100644 index 53eeca1386..0000000000 --- a/src/mesa/drivers/dri/r300/r300_texmem.c +++ /dev/null @@ -1,58 +0,0 @@ -/************************************************************************** - -Copyright (C) Tungsten Graphics 2002. All Rights Reserved. -The Weather Channel, Inc. funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 -license. This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation on the rights to use, copy, modify, merge, publish, -distribute, sub license, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR THEIR -SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR -IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. - -**************************************************************************/ - -/** - * \file - * - * \author Gareth Hughes - * - * \author Kevin E. Martin - */ - -#include - -#include "main/glheader.h" -#include "main/imports.h" -#include "main/context.h" -#include "main/colormac.h" -#include "main/macros.h" -#include "main/simple_list.h" -#include "radeon_reg.h" /* gets definition for usleep */ -#include "r300_context.h" -#include "r300_state.h" -#include "r300_cmdbuf.h" -#include "r300_emit.h" -#include "r300_mipmap_tree.h" -#include "radeon_ioctl.h" -#include "r300_tex.h" -#include "r300_ioctl.h" -#include /* for usleep() */ - - diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 6e2b1309c5..50ecc570bd 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -47,7 +47,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_context.h" #include "r300_state.h" #include "r300_ioctl.h" -#include "radeon_ioctl.h" #include "radeon_mipmap_tree.h" #include "radeon_cs.h" #include "r300_tex.h" diff --git a/src/mesa/drivers/dri/r300/radeon_context.c b/src/mesa/drivers/dri/r300/radeon_context.c deleted file mode 100644 index 13a7682416..0000000000 --- a/src/mesa/drivers/dri/r300/radeon_context.c +++ /dev/null @@ -1,75 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/** - * \file radeon_context.c - * Common context initialization. - * - * \author Keith Whitwell - */ - -#include - -#include "main/glheader.h" -#include "main/imports.h" -#include "main/context.h" -#include "main/state.h" -#include "main/matrix.h" -#include "main/framebuffer.h" - -#include "drivers/common/driverfuncs.h" -#include "swrast/swrast.h" - -#include "radeon_buffer.h" -#include "radeon_screen.h" -#include "radeon_ioctl.h" -#include "radeon_macros.h" -#include "radeon_reg.h" - -#include "radeon_state.h" -#include "r300_state.h" - -#include "utils.h" -#include "vblank.h" -#include "xmlpool.h" /* for symbolic values of enum-type options */ -#include "drirenderbuffer.h" - -/* Force the context `c' to be unbound from its buffer. - */ -GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv) -{ - radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; - - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx %p\n", __FUNCTION__, - radeon->glCtx); - - return GL_TRUE; -} - diff --git a/src/mesa/drivers/dri/r300/radeon_context.h b/src/mesa/drivers/dri/r300/radeon_context.h index 736bf7c649..005edf8448 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.h +++ b/src/mesa/drivers/dri/r300/radeon_context.h @@ -67,20 +67,6 @@ extern void radeonFallback(GLcontext * ctx, GLuint bit, GLboolean mode); /* TCL fallbacks */ extern void radeonTclFallback(GLcontext * ctx, GLuint bit, GLboolean mode); -#define RADEON_TCL_FALLBACK_RASTER 0x0001 /* rasterization */ -#define RADEON_TCL_FALLBACK_UNFILLED 0x0002 /* unfilled tris */ -#define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE 0x0004 /* twoside tris */ -#define RADEON_TCL_FALLBACK_MATERIAL 0x0008 /* material in vb */ -#define RADEON_TCL_FALLBACK_TEXGEN_0 0x0010 /* texgen, unit 0 */ -#define RADEON_TCL_FALLBACK_TEXGEN_1 0x0020 /* texgen, unit 1 */ -#define RADEON_TCL_FALLBACK_TEXGEN_2 0x0040 /* texgen, unit 2 */ -#define RADEON_TCL_FALLBACK_TEXGEN_3 0x0080 /* texgen, unit 3 */ -#define RADEON_TCL_FALLBACK_TEXGEN_4 0x0100 /* texgen, unit 4 */ -#define RADEON_TCL_FALLBACK_TEXGEN_5 0x0200 /* texgen, unit 5 */ -#define RADEON_TCL_FALLBACK_TCL_DISABLE 0x0400 /* user disable */ -#define RADEON_TCL_FALLBACK_BITMAP 0x0800 /* draw bitmap with points */ -#define RADEON_TCL_FALLBACK_VERTEX_PROGRAM 0x1000 /* vertex program active */ - #if R200_MERGED #define TCL_FALLBACK( ctx, bit, mode ) radeonTclFallback( ctx, bit, mode ) #else @@ -88,33 +74,4 @@ extern void radeonTclFallback(GLcontext * ctx, GLuint bit, GLboolean mode); #endif -extern void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, - int x, int y, int w, int h); -extern GLboolean radeonInitContext(radeonContextPtr radeon, - struct dd_function_table *functions, - const __GLcontextModes * glVisual, - __DRIcontextPrivate * driContextPriv, - void *sharedContextPrivate); -extern void radeonCleanupContext(radeonContextPtr radeon); -extern GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, - __DRIdrawablePrivate * driDrawPriv, - __DRIdrawablePrivate * driReadPriv); -extern GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv); -void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable); - -/* ================================================================ - * Debugging: - */ -#define DO_DEBUG 1 - -#if DO_DEBUG -extern int RADEON_DEBUG; -#else -#define RADEON_DEBUG 0 -#endif - -#define DEBUG_SYNC 0x1000 -#define DEBUG_PIXEL 0x2000 -#define DEBUG_MEMORY 0x4000 - #endif /* __RADEON_CONTEXT_H__ */ diff --git a/src/mesa/drivers/dri/r300/radeon_ioctl.c b/src/mesa/drivers/dri/r300/radeon_ioctl.c deleted file mode 100644 index 120d6c03ab..0000000000 --- a/src/mesa/drivers/dri/r300/radeon_ioctl.c +++ /dev/null @@ -1,69 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell - */ - -#include -#include - -#include "main/glheader.h" -#include "main/imports.h" -#include "main/macros.h" -#include "main/context.h" -#include "swrast/swrast.h" -#include "r300_context.h" -#include "radeon_ioctl.h" -#include "radeon_buffer.h" -#include "r300_ioctl.h" -#include "r300_state.h" -#include "radeon_reg.h" - -#include "drirenderbuffer.h" -#include "vblank.h" - -void radeonFlush(GLcontext * ctx) -{ - radeonContextPtr radeon = RADEON_CONTEXT(ctx); - - if (IS_R300_CLASS(radeon->radeonScreen)) - r300Flush(ctx); -} - - -/* Make sure all commands have been sent to the hardware and have - * completed processing. - */ -void radeonFinish(GLcontext * ctx) -{ - radeonFlush(ctx); - radeon_common_finish(ctx); -} diff --git a/src/mesa/drivers/dri/r300/radeon_ioctl.h b/src/mesa/drivers/dri/r300/radeon_ioctl.h deleted file mode 100644 index 3add775b82..0000000000 --- a/src/mesa/drivers/dri/r300/radeon_ioctl.h +++ /dev/null @@ -1,57 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell - */ - -#ifndef __RADEON_IOCTL_H__ -#define __RADEON_IOCTL_H__ - -#include "main/simple_list.h" -#include "radeon_dri.h" -#include "radeon_lock.h" - -#include "xf86drm.h" -#include "drm.h" -#if 0 -#include "r200context.h" -#endif -#include "radeon_drm.h" - -extern void radeonCopyBuffer(__DRIdrawablePrivate * drawable, - const drm_clip_rect_t * rect); -extern void radeonPageFlip(__DRIdrawablePrivate * drawable); -extern void radeonFlush(GLcontext * ctx); -extern void radeonFinish(GLcontext * ctx); -extern void radeonWaitForIdleLocked(radeonContextPtr radeon); -extern uint32_t radeonGetAge(radeonContextPtr radeon); - -#endif /* __RADEON_IOCTL_H__ */ diff --git a/src/mesa/drivers/dri/r300/radeon_state.c b/src/mesa/drivers/dri/r300/radeon_state.c deleted file mode 100644 index 0ee5313043..0000000000 --- a/src/mesa/drivers/dri/r300/radeon_state.c +++ /dev/null @@ -1,109 +0,0 @@ -/************************************************************************** - -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell - */ - -#include "main/glheader.h" -#include "main/imports.h" -#include "main/api_arrayelt.h" -#include "main/enums.h" -#include "main/framebuffer.h" -#include "main/colormac.h" -#include "main/light.h" - -#include "swrast/swrast.h" -#include "vbo/vbo.h" -#include "tnl/tnl.h" -#include "tnl/t_pipeline.h" -#include "swrast_setup/swrast_setup.h" - -#include "radeon_ioctl.h" -#include "radeon_state.h" -#include "r300_ioctl.h" - - -/* ============================================================= - * Scissoring - */ - -static void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h) -{ - if (ctx->Scissor.Enabled) { - /* We don't pipeline cliprect changes */ - r300Flush(ctx); - radeonUpdateScissor(ctx); - } -} - -/** - * Handle common enable bits. - * Called as a fallback by r200Enable/r300Enable. - */ -void radeonEnable(GLcontext* ctx, GLenum cap, GLboolean state) -{ - radeonContextPtr radeon = RADEON_CONTEXT(ctx); - - switch(cap) { - case GL_SCISSOR_TEST: - /* We don't pipeline cliprect & scissor changes */ - r300Flush(ctx); - - radeon->state.scissor.enabled = state; - radeonUpdateScissor(ctx); - break; - - default: - return; - } -} - - -/** - * Initialize default state. - * This function is called once at context init time from - * r200InitState/r300InitState - */ -void radeonInitState(radeonContextPtr radeon) -{ - radeon->Fallback = 0; -} - - -/** - * Initialize common state functions. - * Called by r200InitStateFuncs/r300InitStateFuncs - */ -void radeonInitStateFuncs(struct dd_function_table *functions) -{ - functions->Scissor = radeonScissor; -} diff --git a/src/mesa/drivers/dri/r300/radeon_state.h b/src/mesa/drivers/dri/r300/radeon_state.h deleted file mode 100644 index 279b108412..0000000000 --- a/src/mesa/drivers/dri/r300/radeon_state.h +++ /dev/null @@ -1,39 +0,0 @@ -/* -Copyright (C) 2004 Nicolai Haehnle. All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Nicolai Haehnle - */ - -#ifndef __RADEON_STATE_H__ -#define __RADEON_STATE_H__ - -extern void radeonEnable(GLcontext* ctx, GLenum cap, GLboolean state); - -extern void radeonInitState(radeonContextPtr radeon); -extern void radeonInitStateFuncs(struct dd_function_table* functions); - -#endif diff --git a/src/mesa/drivers/dri/radeon/common_cmdbuf.h b/src/mesa/drivers/dri/radeon/common_cmdbuf.h index 071e29ee02..5526934209 100644 --- a/src/mesa/drivers/dri/radeon/common_cmdbuf.h +++ b/src/mesa/drivers/dri/radeon/common_cmdbuf.h @@ -1,10 +1,12 @@ #ifndef COMMON_CMDBUF_H #define COMMON_CMDBUF_H +#include "radeon_cs.h" + void rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *caller); int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller); int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller); -void rcommonInitCmdBuf(radeonContextPtr rmesa, int max_state_size); +void rcommonInitCmdBuf(radeonContextPtr rmesa); void rcommonDestroyCmdBuf(radeonContextPtr rmesa); void rcommonBeginBatch(radeonContextPtr rmesa, @@ -128,4 +130,14 @@ void rcommonBeginBatch(radeonContextPtr rmesa, /** Write a 32 bit float to the ring; requires 1 dword. */ #define OUT_BATCH_FLOAT32(f) \ OUT_BATCH(radeonPackFloat32((f))); + + +/* Fire the buffered vertices no matter what. + */ +static INLINE void radeon_firevertices(radeonContextPtr radeon) +{ + if (radeon->cmdbuf.cs->cdw || radeon->dma.flush ) + radeonFlush(radeon->glCtx); +} + #endif diff --git a/src/mesa/drivers/dri/radeon/common_context.h b/src/mesa/drivers/dri/radeon/common_context.h index 618e74d458..c3a445e0d2 100644 --- a/src/mesa/drivers/dri/radeon/common_context.h +++ b/src/mesa/drivers/dri/radeon/common_context.h @@ -111,6 +111,13 @@ struct radeon_state_atom { void (*emit) (GLcontext *, struct radeon_state_atom *atom); }; +struct radeon_hw_state { + /* Head of the linked list of state atoms. */ + struct radeon_state_atom atomlist; + int max_state_size; /* Number of bytes necessary for a full state emit. */ + GLboolean is_dirty, all_dirty; +}; + /* Texture related */ typedef struct _radeon_texture_image radeon_texture_image; @@ -206,17 +213,6 @@ struct radeon_dma_buffer { drmBufPtr buf; }; -/* A retained region, eg vertices for indexed vertices. - */ -struct radeon_dma_region { - struct radeon_dma_buffer *buf; - char *address; /* == buf->address */ - int start, end, ptr; /* offsets from start of buf */ - int aos_start; - int aos_stride; - int aos_size; -}; - struct radeon_aos { struct radeon_bo *bo; /** Buffer object where vertex data is stored */ int offset; /** Offset into buffer object, in bytes */ @@ -388,6 +384,7 @@ struct radeon_context { float initialMaxAnisotropy; struct radeon_dma dma; + struct radeon_hw_state hw; /* Rasterization and vertex state: */ GLuint TclFallback; @@ -434,13 +431,11 @@ struct radeon_context { struct { void (*get_lock)(radeonContextPtr radeon); void (*update_viewport_offset)(GLcontext *ctx); - void (*flush)(GLcontext *ctx); - void (*set_all_dirty)(GLcontext *ctx); void (*update_draw_buffer)(GLcontext *ctx); void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa); - void (*emit_state)(radeonContextPtr rmesa); - void (*flush_vertices)(radeonContextPtr rmesa); void (*swtcl_flush)(GLcontext *ctx, uint32_t offset); + void (*pre_emit_atoms)(radeonContextPtr rmesa); + void (*pre_emit_state)(radeonContextPtr rmesa); } vtbl; }; @@ -502,4 +497,6 @@ extern int RADEON_DEBUG; #define RADEON_DEBUG 0 #endif +#include "common_misc.h" +#include "common_cmdbuf.h" #endif diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c index 9456f2a438..12536b1672 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.c +++ b/src/mesa/drivers/dri/radeon/common_misc.c @@ -42,6 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/colormac.h" #include "main/light.h" #include "main/framebuffer.h" +#include "main/simple_list.h" #include "swrast/swrast.h" #include "vbo/vbo.h" @@ -81,6 +82,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. int RADEON_DEBUG = (0); #endif +#define DEBUG_CMDBUF 0 + /* ============================================================= * Scissoring */ @@ -215,6 +218,21 @@ void radeonUpdateScissor( GLcontext *ctx ) } } +/* ============================================================= + * Scissoring + */ + +void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + if (ctx->Scissor.Enabled) { + /* We don't pipeline cliprect changes */ + radeon_firevertices(radeon); + radeonUpdateScissor(ctx); + } +} + + /* ================================================================ * SwapBuffers with client-side throttling */ @@ -367,7 +385,7 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx ); } - rmesa->vtbl.flush(rmesa->glCtx); + radeon_firevertices(rmesa); LOCK_HARDWARE( rmesa ); /* Throttle the frame rate -- only allow one pending swap buffers @@ -437,7 +455,7 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, } rmesa->swap_ust = ust; - rmesa->vtbl.set_all_dirty(rmesa->glCtx); + rmesa->hw.all_dirty = GL_TRUE; } } @@ -465,7 +483,7 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv ) rmesa->sarea->pfCurrentPage); } - rmesa->vtbl.flush(rmesa->glCtx); + radeon_firevertices(rmesa); LOCK_HARDWARE( rmesa ); @@ -516,16 +534,111 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv ) rmesa->vtbl.update_draw_buffer(rmesa->glCtx); } +void radeonFlush(GLcontext *ctx) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + if (RADEON_DEBUG & DEBUG_IOCTL) + fprintf(stderr, "%s\n", __FUNCTION__); + + if (radeon->dma.flush) + radeon->dma.flush( ctx ); + + radeonEmitState(radeon); + + if (radeon->cmdbuf.cs->cdw) + rcommonFlushCmdBuf(radeon, __FUNCTION__); +} + +static INLINE void radeonEmitAtoms(radeonContextPtr radeon, GLboolean dirty) +{ + BATCH_LOCALS(radeon); + struct radeon_state_atom *atom; + int dwords; + + if (radeon->vtbl.pre_emit_atoms) + radeon->vtbl.pre_emit_atoms(radeon); + + /* Emit actual atoms */ + foreach(atom, &radeon->hw.atomlist) { + if ((atom->dirty || radeon->hw.all_dirty) == dirty) { + dwords = (*atom->check) (radeon->glCtx, atom); + if (dwords) { + if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { + radeon_print_state_atom(atom); + } + if (atom->emit) { + (*atom->emit)(radeon->glCtx, atom); + } else { + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_BATCH_TABLE(atom->cmd, dwords); + END_BATCH(); + } + atom->dirty = GL_FALSE; + } else { + if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { + fprintf(stderr, " skip state %s\n", + atom->name); + } + } + } + } + + COMMIT_BATCH(); +} + +void radeonEmitState(radeonContextPtr radeon) +{ + if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS)) + fprintf(stderr, "%s\n", __FUNCTION__); + + if (radeon->vtbl.pre_emit_state) + radeon->vtbl.pre_emit_state(radeon); + + /* this code used to return here but now it emits zbs */ + if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw.all_dirty) + return; + + /* To avoid going across the entire set of states multiple times, just check + * for enough space for the case of emitting all state, and inline the + * radeonAllocCmdBuf code here without all the checks. + */ + rcommonEnsureCmdBufSpace(radeon, radeon->hw.max_state_size, __FUNCTION__); + + /* We always always emit zbs, this is due to a bug found by keithw in + the hardware and rediscovered after Erics changes by me. + if you ever touch this code make sure you emit zbs otherwise + you get tcl lockups on at least M7/7500 class of chips - airlied */ + /* special r100 case */ + // rmesa->hw.zbs.dirty=1; + + if (!radeon->cmdbuf.cs->cdw) { + if (RADEON_DEBUG & DEBUG_STATE) + fprintf(stderr, "Begin reemit state\n"); + + radeonEmitAtoms(radeon, GL_FALSE); + } + + if (RADEON_DEBUG & DEBUG_STATE) + fprintf(stderr, "Begin dirty state\n"); + + radeonEmitAtoms(radeon, GL_TRUE); + radeon->hw.is_dirty = GL_FALSE; + radeon->hw.all_dirty = GL_FALSE; + +} + /* Make sure all commands have been sent to the hardware and have * completed processing. */ -void radeon_common_finish(GLcontext * ctx) +void radeonFinish(GLcontext * ctx) { radeonContextPtr radeon = RADEON_CONTEXT(ctx); struct gl_framebuffer *fb = ctx->DrawBuffer; int i; + radeonFlush(ctx); + if (radeon->radeonScreen->kernel_mm) { for (i = 0; i < fb->_NumColorDrawBuffers; i++) { struct radeon_renderbuffer *rrb; @@ -611,7 +724,7 @@ int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller) rmesa->cmdbuf.flushing = 1; if (rmesa->cmdbuf.cs->cdw) { ret = radeon_cs_emit(rmesa->cmdbuf.cs); - rmesa->vtbl.set_all_dirty(rmesa->glCtx); + rmesa->hw.all_dirty = GL_TRUE; } radeon_cs_erase(rmesa->cmdbuf.cs); rmesa->cmdbuf.flushing = 0; @@ -650,20 +763,18 @@ void rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *ca } } -void rcommonInitCmdBuf(radeonContextPtr rmesa, int max_state_size) +void rcommonInitCmdBuf(radeonContextPtr rmesa) { GLuint size; /* Initialize command buffer */ size = 256 * driQueryOptioni(&rmesa->optionCache, "command_buffer_size"); - if (size < 2 * max_state_size) { - size = 2 * max_state_size + 65535; + if (size < 2 * rmesa->hw.max_state_size) { + size = 2 * rmesa->hw.max_state_size + 65535; } if (size > 64 * 256) size = 64 * 256; - size = 64 * 1024 / 4; - if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) { fprintf(stderr, "sizeof(drm_r300_cmd_header_t)=%zd\n", sizeof(drm_r300_cmd_header_t)); @@ -671,7 +782,7 @@ void rcommonInitCmdBuf(radeonContextPtr rmesa, int max_state_size) sizeof(drm_radeon_cmd_buffer_t)); fprintf(stderr, "Allocating %d bytes command buffer (max state is %d bytes)\n", - size * 4, max_state_size * 4); + size * 4, rmesa->hw.max_state_size * 4); } if (rmesa->radeonScreen->kernel_mm) { @@ -725,7 +836,7 @@ void rcommonBeginBatch(radeonContextPtr rmesa, int n, if (!rmesa->cmdbuf.cs->cdw && dostate) { if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "Reemit state after flush (from %s)\n", function); - rmesa->vtbl.emit_state(rmesa); + radeonEmitState(rmesa); } radeon_cs_begin(rmesa->cmdbuf.cs, n, file, function, line); } @@ -927,6 +1038,20 @@ void radeonCleanupContext(radeonContextPtr radeon) } } +/* Force the context `c' to be unbound from its buffer. + */ +GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv) +{ + radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; + + if (RADEON_DEBUG & DEBUG_DRI) + fprintf(stderr, "%s ctx %p\n", __FUNCTION__, + radeon->glCtx); + + return GL_TRUE; +} + + static void radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon, GLframebuffer *draw) @@ -1810,7 +1935,7 @@ static void radeon_teximage( radeonTexObj* t = radeon_tex_obj(texObj); radeon_texture_image* image = get_radeon_texture_image(texImage); - rmesa->vtbl.flush_vertices(rmesa); + radeon_firevertices(rmesa); t->validated = GL_FALSE; @@ -1968,7 +2093,7 @@ static void radeon_texsubimage(GLcontext* ctx, int dims, int level, radeonTexObj* t = radeon_tex_obj(texObj); radeon_texture_image* image = get_radeon_texture_image(texImage); - rmesa->vtbl.flush_vertices(rmesa); + radeon_firevertices(rmesa); t->validated = GL_FALSE; pixels = _mesa_validate_pbo_teximage(ctx, dims, @@ -2373,7 +2498,7 @@ void radeonSpanRenderStart(GLcontext * ctx) radeonContextPtr rmesa = RADEON_CONTEXT(ctx); int i; - rmesa->vtbl.flush_vertices(rmesa); + radeon_firevertices(rmesa); for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) { if (ctx->Texture.Unit[i]._ReallyEnabled) diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h index 80b34aa6bd..ebf287a031 100644 --- a/src/mesa/drivers/dri/radeon/common_misc.h +++ b/src/mesa/drivers/dri/radeon/common_misc.h @@ -6,6 +6,7 @@ void radeonRecalcScissorRects(radeonContextPtr radeon); void radeonSetCliprects(radeonContextPtr radeon); void radeonUpdateScissor( GLcontext *ctx ); +void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h); void radeonWaitForIdleLocked(radeonContextPtr radeon); extern uint32_t radeonGetAge(radeonContextPtr radeon); @@ -26,6 +27,7 @@ GLboolean radeonInitContext(radeonContextPtr radeon, void *sharedContextPrivate); void radeonCleanupContext(radeonContextPtr radeon); +GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv); void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable); GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, __DRIdrawablePrivate * driDrawPriv, @@ -132,6 +134,9 @@ void rcommon_flush_last_swtcl_prim(GLcontext *ctx); void *rcommonAllocDmaLowVerts(radeonContextPtr rmesa, int nverts, int vsize); +void radeonFlush(GLcontext *ctx); +void radeonFinish(GLcontext * ctx); +void radeonEmitState(radeonContextPtr radeon); static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPtr rmesa) { diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index 6fa01f4ded..b25f036c44 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -215,29 +215,17 @@ static void r100_get_lock(radeonContextPtr radeon) } } -static void r100_vtbl_flush(GLcontext *ctx) -{ - RADEON_FIREVERTICES(R100_CONTEXT(ctx)); -} - -static void r100_vtbl_set_all_dirty(GLcontext *ctx) -{ - r100ContextPtr rmesa = R100_CONTEXT(ctx); - rmesa->hw.all_dirty = GL_TRUE; -} - static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) { } -static void r100_vtbl_emit_state(radeonContextPtr rmesa) +static void r100_vtbl_pre_emit_state(radeonContextPtr radeon) { - radeonEmitState((r100ContextPtr)rmesa); -} - -static void r100_vtbl_flush_vertices(radeonContextPtr rmesa) -{ - RADEON_FIREVERTICES(((r100ContextPtr)rmesa)); + r100ContextPtr rmesa = (r100ContextPtr)radeon; + + /* r100 always needs to emit ZBS to avoid TCL lockups */ + rmesa->hw.zbs.dirty = 1; + radeon->hw.is_dirty = 1; } @@ -245,13 +233,10 @@ static void r100_init_vtbl(radeonContextPtr radeon) { radeon->vtbl.get_lock = r100_get_lock; radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset; - radeon->vtbl.flush = r100_vtbl_flush; - radeon->vtbl.set_all_dirty = r100_vtbl_set_all_dirty; radeon->vtbl.update_draw_buffer = radeonUpdateDrawBuffer; radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header; - radeon->vtbl.emit_state = r100_vtbl_emit_state; radeon->vtbl.swtcl_flush = r100_swtcl_flush; - radeon->vtbl.flush_vertices = r100_vtbl_flush_vertices; + radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state; } /* Create the device specific context. @@ -344,7 +329,7 @@ radeonCreateContext( const __GLcontextModes *glVisual, DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; rmesa->radeon.swtcl.RenderIndex = ~0; - rmesa->hw.all_dirty = GL_TRUE; + rmesa->radeon.hw.all_dirty = GL_TRUE; /* Set the maximum texture size small enough that we can guarentee that * all texture units can bind a maximal texture and have all of them in @@ -503,7 +488,7 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) /* check if we're deleting the currently bound context */ if (rmesa == current) { - RADEON_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); _mesa_make_current(NULL, NULL, NULL); } @@ -553,16 +538,3 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) } } - -/* Force the context `c' to be unbound from its buffer. - */ -GLboolean -radeonUnbindContext( __DRIcontextPrivate *driContextPriv ) -{ - r100ContextPtr rmesa = (r100ContextPtr) driContextPriv->driverPrivate; - - if (RADEON_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) rmesa->radeon.glCtx); - - return GL_TRUE; -} diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h index 358095a2b9..d05e47f16e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -296,10 +296,7 @@ struct radeon_texture_state { #define SHN_SHININESS 1 #define SHN_STATE_SIZE 2 -struct radeon_hw_state { - /* Head of the linked list of state atoms. */ - struct radeon_state_atom atomlist; - +struct r100_hw_state { /* Hardware state, stored as cmdbuf commands: * -- Need to doublebuffer for * - eliding noop statechange loops? (except line stipple count) @@ -324,8 +321,6 @@ struct radeon_hw_state { struct radeon_state_atom glt; struct radeon_state_atom txr[3]; /* for NPOT */ - int max_state_size; /* Number of bytes necessary for a full state emit. */ - GLboolean is_dirty, all_dirty; }; @@ -354,14 +349,6 @@ struct radeon_tcl_info { struct radeon_bo *indexed_bo; -// struct radeon_dma_region indexed_verts; - struct radeon_dma_region obj; - struct radeon_dma_region rgba; - struct radeon_dma_region spec; - struct radeon_dma_region fog; - struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS]; - struct radeon_dma_region norm; - int elt_cmd_offset; /** Offset into the cmdbuf */ int elt_cmd_start; int elt_used; @@ -391,8 +378,6 @@ struct r100_swtcl_info { GLuint specoffset; GLboolean needproj; - - struct radeon_dma_region indexed_verts; }; @@ -411,17 +396,13 @@ struct r100_context { /* Driver and hardware state management */ - struct radeon_hw_state hw; + struct r100_hw_state hw; struct r100_state state; /* Vertex buffers */ struct radeon_ioctl ioctl; struct radeon_store store; - /* A full state emit as of the first state emit in the main store, in case - * the context is lost. - */ - struct radeon_store backup_store; /* TCL stuff */ @@ -455,7 +436,6 @@ struct r100_context { GLuint c_textureBytes; GLuint c_vertexBuffers; - GLboolean save_on_next_emit; }; #define R100_CONTEXT(ctx) ((r100ContextPtr)(ctx->DriverCtx)) diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 45d750dbf4..d0cd9ce7a6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -59,60 +59,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RADEON_TIMEOUT 512 #define RADEON_IDLE_RETRY 16 -#define DEBUG_CMDBUF 1 - -static void radeonSaveHwState( r100ContextPtr rmesa ) -{ - struct radeon_state_atom *atom; - char * dest = rmesa->backup_store.cmd_buf; - - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "%s\n", __FUNCTION__); - - rmesa->backup_store.cmd_used = 0; - - foreach( atom, &rmesa->hw.atomlist ) { - if ( atom->check( rmesa->radeon.glCtx, 0 ) ) { - int size = atom->cmd_size * 4; - memcpy( dest, atom->cmd, size); - dest += size; - rmesa->backup_store.cmd_used += size; - if (RADEON_DEBUG & DEBUG_STATE) - radeon_print_state_atom( atom ); - } - } - - assert( rmesa->backup_store.cmd_used <= RADEON_CMD_BUF_SZ ); - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Returning to radeonEmitState\n"); -} - -/* At this point we were in FlushCmdBufLocked but we had lost our context, so - * we need to unwire our current cmdbuf, hook the one with the saved state in - * it, flush it, and then put the current one back. This is so commands at the - * start of a cmdbuf can rely on the state being kept from the previous one. - */ -static void radeonBackUpAndEmitLostStateLocked( r100ContextPtr rmesa ) -{ - GLuint nr_released_bufs; - struct radeon_store saved_store; - - if (rmesa->backup_store.cmd_used == 0) - return; - - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Emitting backup state on lost context\n"); - - rmesa->radeon.lost_context = GL_FALSE; - - nr_released_bufs = rmesa->radeon.dma.nr_released_bufs; - saved_store = rmesa->store; - rmesa->radeon.dma.nr_released_bufs = 0; - rmesa->store = rmesa->backup_store; - rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); - rmesa->radeon.dma.nr_released_bufs = nr_released_bufs; - rmesa->store = saved_store; -} /* ============================================================= * Kernel command buffer handling @@ -125,107 +71,33 @@ void radeonSetUpAtomList( r100ContextPtr rmesa ) { int i, mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits; - make_empty_list(&rmesa->hw.atomlist); - rmesa->hw.atomlist.name = "atom-list"; + make_empty_list(&rmesa->radeon.hw.atomlist); + rmesa->radeon.hw.atomlist.name = "atom-list"; - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.ctx); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.set); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.lin); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.msk); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.vpt); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.tcl); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.msc); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.ctx); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.set); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.lin); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.msk); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.vpt); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tcl); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.msc); for (i = 0; i < mtu; ++i) { - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.tex[i]); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.txr[i]); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.cube[i]); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tex[i]); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.txr[i]); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.cube[i]); } - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.zbs); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.mtl); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.zbs); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.mtl); for (i = 0; i < 3 + mtu; ++i) - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.mat[i]); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.mat[i]); for (i = 0; i < 8; ++i) - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.lit[i]); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.lit[i]); for (i = 0; i < 6; ++i) - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.ucp[i]); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.eye); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.grd); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.fog); - insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.glt); -} - -static INLINE void radeonEmitAtoms(r100ContextPtr r100, GLboolean dirty) -{ - BATCH_LOCALS(&r100->radeon); - struct radeon_state_atom *atom; - int dwords; - - /* Emit actual atoms */ - foreach(atom, &r100->hw.atomlist) { - if ((atom->dirty || r100->hw.all_dirty) == dirty) { - dwords = (*atom->check) (r100->radeon.glCtx, atom); - if (dwords) { - if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { - radeon_print_state_atom(atom); - } - if (atom->emit) { - (*atom->emit)(r100->radeon.glCtx, atom); - } else { - BEGIN_BATCH_NO_AUTOSTATE(dwords); - OUT_BATCH_TABLE(atom->cmd, dwords); - END_BATCH(); - } - atom->dirty = GL_FALSE; - } else { - if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { - fprintf(stderr, " skip state %s\n", - atom->name); - } - } - } - } - - COMMIT_BATCH(); -} - -void radeonEmitState( r100ContextPtr rmesa ) -{ - if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS)) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (rmesa->save_on_next_emit) { - radeonSaveHwState(rmesa); - rmesa->save_on_next_emit = GL_FALSE; - } - - /* this code used to return here but now it emits zbs */ - - /* To avoid going across the entire set of states multiple times, just check - * for enough space for the case of emitting all state, and inline the - * radeonAllocCmdBuf code here without all the checks. - */ - rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->hw.max_state_size, __FUNCTION__); - - /* We always always emit zbs, this is due to a bug found by keithw in - the hardware and rediscovered after Erics changes by me. - if you ever touch this code make sure you emit zbs otherwise - you get tcl lockups on at least M7/7500 class of chips - airlied */ - rmesa->hw.zbs.dirty=1; - - if (!rmesa->radeon.cmdbuf.cs->cdw) { - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Begin reemit state\n"); - - radeonEmitAtoms(rmesa, GL_FALSE); - } - - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Begin dirty state\n"); - - radeonEmitAtoms(rmesa, GL_TRUE); - rmesa->hw.is_dirty = GL_FALSE; - rmesa->hw.all_dirty = GL_FALSE; - + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.ucp[i]); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.eye); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.grd); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.fog); + insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.glt); } /* Fire a section of the retained (indexed_verts) buffer as a regular @@ -240,7 +112,7 @@ extern void radeonEmitVbufPrim( r100ContextPtr rmesa, assert(!(primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND)); - radeonEmitState( rmesa ); + radeonEmitState(&rmesa->radeon); #if RADEON_OLD_PACKETS BEGIN_BATCH(8); @@ -318,7 +190,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND)); - radeonEmitState( rmesa ); + radeonEmitState(&rmesa->radeon); rmesa->tcl.elt_cmd_start = rmesa->radeon.cmdbuf.cs->cdw; @@ -679,35 +551,9 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask ) } UNLOCK_HARDWARE( &rmesa->radeon ); - rmesa->hw.all_dirty = GL_TRUE; -} - -void radeonFlush( GLcontext *ctx ) -{ - r100ContextPtr rmesa = R100_CONTEXT( ctx ); - - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (rmesa->radeon.dma.flush) - rmesa->radeon.dma.flush( ctx ); - - radeonEmitState( rmesa ); - - if (rmesa->radeon.cmdbuf.cs->cdw) - rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); -} - -/* Make sure all commands have been sent to the hardware and have - * completed processing. - */ -void radeonFinish( GLcontext *ctx ) -{ - radeonFlush( ctx ); - radeon_common_finish(ctx); + rmesa->radeon.hw.all_dirty = GL_TRUE; } - void radeonInitIoctlFuncs( GLcontext *ctx ) { ctx->Driver.Clear = radeonClear; diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.h b/src/mesa/drivers/dri/radeon/radeon_ioctl.h index 4e93804646..6d616bf804 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.h +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.h @@ -40,7 +40,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_lock.h" #include "radeon_cs_legacy.h" -extern void radeonEmitState( r100ContextPtr rmesa ); extern void radeonEmitVertexAOS( r100ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, @@ -104,7 +103,7 @@ do { \ do { \ RADEON_NEWPRIM( rmesa ); \ rmesa->hw.ATOM.dirty = GL_TRUE; \ - rmesa->hw.is_dirty = GL_TRUE; \ + rmesa->radeon.hw.is_dirty = GL_TRUE; \ } while (0) #define RADEON_DB_STATE( ATOM ) \ @@ -118,7 +117,7 @@ static INLINE int RADEON_DB_STATECHANGE(r100ContextPtr rmesa, GLuint *tmp; RADEON_NEWPRIM( rmesa ); atom->dirty = GL_TRUE; - rmesa->hw.is_dirty = GL_TRUE; + rmesa->radeon.hw.is_dirty = GL_TRUE; tmp = atom->cmd; atom->cmd = atom->lastcmd; atom->lastcmd = tmp; @@ -128,15 +127,6 @@ static INLINE int RADEON_DB_STATECHANGE(r100ContextPtr rmesa, return 0; } -/* Fire the buffered vertices no matter what. - */ -#define RADEON_FIREVERTICES( rmesa ) \ -do { \ - if (rmesa->radeon.cmdbuf.cs->cdw || rmesa->radeon.dma.flush ) { \ - radeonFlush( rmesa->radeon.glCtx ); \ - } \ -} while (0) - /* Command lengths. Note that any time you ensure ELTS_BUFSZ or VBUF_BUFSZ * are available, you will also be adding an rmesa->state.max_state_size because * r200EmitState is called from within r200EmitVbufPrim and r200FlushElts. diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 497582ee23..7397218fb6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1523,7 +1523,7 @@ const struct __DriverAPIRec driDriverAPI = { .DestroyBuffer = radeonDestroyBuffer, .SwapBuffers = radeonSwapBuffers, .MakeCurrent = radeonMakeCurrent, - .UnbindContext = r200UnbindContext, + .UnbindContext = radeonUnbindContext, .GetSwapInfo = getSwapInfo, .GetDrawableMSC = driDrawableGetMSC32, .WaitForMSC = driWaitForMSC32, diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 1d683e5b3a..a9ec1d51c7 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -47,6 +47,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast_setup/swrast_setup.h" #include "radeon_context.h" +#include "common_cmdbuf.h" #include "radeon_ioctl.h" #include "radeon_state.h" #include "radeon_tcl.h" @@ -406,23 +407,6 @@ static void radeonFogfv( GLcontext *ctx, GLenum pname, const GLfloat *param ) } } - -/* ============================================================= - * Scissoring - */ -static void radeonScissor( GLcontext *ctx, - GLint x, GLint y, GLsizei w, GLsizei h ) -{ - r100ContextPtr rmesa = R100_CONTEXT(ctx); - - if ( ctx->Scissor.Enabled ) { - RADEON_FIREVERTICES( rmesa ); /* don't pipeline cliprect changes */ - radeonUpdateScissor( ctx ); - } - -} - - /* ============================================================= * Culling */ @@ -567,7 +551,7 @@ static void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask ) /* TODO: push this into cmd mechanism */ - RADEON_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); LOCK_HARDWARE( &rmesa->radeon ); /* FIXME: Use window x,y offsets into stipple RAM. @@ -1415,7 +1399,7 @@ void radeonUpdateWindow( GLcontext *ctx ) float_ui32_type sz = { v[MAT_SZ] * rmesa->radeon.state.depth.scale }; float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale }; - RADEON_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); RADEON_STATECHANGE( rmesa, vpt ); rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = sx.ui32; @@ -1561,7 +1545,7 @@ static void radeonDrawBuffer( GLcontext *ctx, GLenum mode ) fprintf(stderr, "%s %s\n", __FUNCTION__, _mesa_lookup_enum_by_nr( mode )); - RADEON_FIREVERTICES(rmesa); /* don't pipeline cliprect changes */ + radeon_firevertices(&rmesa->radeon); /* don't pipeline cliprect changes */ if (ctx->DrawBuffer->_NumColorDrawBuffers != 1) { /* 0 (GL_NONE) buffers or multiple color drawing buffers */ @@ -1843,7 +1827,7 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) } case GL_SCISSOR_TEST: - RADEON_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); rmesa->radeon.state.scissor.enabled = state; radeonUpdateScissor( ctx ); break; diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index f12d9bdb50..1cfb539e71 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -171,8 +171,8 @@ void radeonPrintDirty( r100ContextPtr rmesa, const char *msg ) fprintf(stderr, msg); fprintf(stderr, ": "); - foreach(l, &rmesa->hw.atomlist) { - if (l->dirty || rmesa->hw.all_dirty) + foreach(l, &rmesa->radeon.hw.atomlist) { + if (l->dirty || rmesa->radeon.hw.all_dirty) fprintf(stderr, "%s, ", l->name); } @@ -512,7 +512,7 @@ void radeonInitState( r100ContextPtr rmesa ) drawPitch = rmesa->radeon.radeonScreen->frontPitch; } - rmesa->hw.max_state_size = 0; + rmesa->radeon.hw.max_state_size = 0; #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \ do { \ @@ -524,7 +524,7 @@ void radeonInitState( r100ContextPtr rmesa ) rmesa->hw.ATOM.check = check_##CHK; \ rmesa->hw.ATOM.dirty = GL_TRUE; \ rmesa->hw.ATOM.idx = IDX; \ - rmesa->hw.max_state_size += SZ * sizeof(int); \ + rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \ } while (0) #define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \ @@ -932,7 +932,7 @@ void radeonInitState( r100ContextPtr rmesa ) rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE; rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE; - rmesa->hw.all_dirty = GL_TRUE; + rmesa->radeon.hw.all_dirty = GL_TRUE; - rcommonInitCmdBuf(&rmesa->radeon, rmesa->hw.max_state_size); + rcommonInitCmdBuf(&rmesa->radeon); } diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c b/src/mesa/drivers/dri/radeon/radeon_swtcl.c index 615621dd98..995ab2099e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c @@ -285,11 +285,11 @@ void r100_swtcl_flush(GLcontext *ctx, uint32_t current_offset) r100ContextPtr rmesa = R100_CONTEXT(ctx); rcommonEnsureCmdBufSpace(&rmesa->radeon, - rmesa->hw.max_state_size + (12*sizeof(int)), + rmesa->radeon.hw.max_state_size + (12*sizeof(int)), __FUNCTION__); - radeonEmitState(rmesa); + radeonEmitState(&rmesa->radeon); radeonEmitVertexAOS( rmesa, rmesa->radeon.swtcl.vertex_size, rmesa->radeon.dma.current, @@ -372,9 +372,6 @@ static GLboolean radeon_run_render( GLcontext *ctx, tnl_render_func *tab = TAG(render_tab_verts); GLuint i; - if (rmesa->swtcl.indexed_verts.buf) - RELEASE_ELT_VERTS(); - if (rmesa->radeon.swtcl.RenderIndex != 0 || !radeon_dma_validate_render( ctx, VB )) return GL_TRUE; @@ -750,7 +747,7 @@ void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode ) if (mode) { rmesa->radeon.Fallback |= bit; if (oldfallback == 0) { - RADEON_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE ); _swsetup_Wakeup( ctx ); rmesa->radeon.swtcl.RenderIndex = ~0; @@ -831,7 +828,4 @@ void radeonDestroySwtcl( GLcontext *ctx ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - // if (rmesa->swtcl.indexed_verts.buf) - // radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, - // __FUNCTION__ ); } diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.c b/src/mesa/drivers/dri/radeon/radeon_tcl.c index daa88f43c7..7281800ce2 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_tcl.c @@ -126,7 +126,7 @@ static GLboolean discrete_prim[0x10] = { #define RESET_STIPPLE() do { \ RADEON_STATECHANGE( rmesa, lin ); \ - radeonEmitState( rmesa ); \ + radeonEmitState(&rmesa->radeon); \ } while (0) #define AUTO_STIPPLE( mode ) do { \ @@ -137,7 +137,7 @@ static GLboolean discrete_prim[0x10] = { else \ rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \ ~RADEON_LINE_PATTERN_AUTO_RESET; \ - radeonEmitState( rmesa ); \ + radeonEmitState(&rmesa->radeon); \ } while (0) @@ -149,7 +149,7 @@ static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr ) if (rmesa->radeon.dma.flush) rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); - rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->hw.max_state_size + ELTS_BUFSZ(nr) + + rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->radeon.hw.max_state_size + ELTS_BUFSZ(nr) + AOS_BUFSZ(rmesa->tcl.nr_aos_components), __FUNCTION__); radeonEmitAOS( rmesa, @@ -178,7 +178,7 @@ static void radeonEmitPrim( GLcontext *ctx, rcommonEnsureCmdBufSpace( &rmesa->radeon, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + - rmesa->hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ ); + rmesa->radeon.hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ ); radeonEmitAOS( rmesa, rmesa->tcl.nr_aos_components, diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c index a916b63a27..e1b988bf4d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.c +++ b/src/mesa/drivers/dri/radeon/radeon_tex.c @@ -381,7 +381,7 @@ static void radeonDeleteTexture( GLcontext *ctx, } if ( rmesa ) { - RADEON_FIREVERTICES( rmesa ); + radeon_firevertices(&rmesa->radeon); for ( i = 0 ; i < rmesa->radeon.glCtx->Const.MaxTextureUnits ; i++ ) { if ( t == rmesa->state.texture.unit[i].texobj ) { rmesa->state.texture.unit[i].texobj = NULL; -- cgit v1.2.3 From e00ef43d796f0ae0247b1072bf0aa8cdd8e3034d Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 2 Apr 2009 14:25:07 +1000 Subject: radeon/r200/r300: collapse context destruction down to a common path. Context destruction was nearly the same over all the drivers, so collapse it down. --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 96 ++++++++++----------- src/mesa/drivers/dri/r200/r200_context.c | 58 ------------- src/mesa/drivers/dri/r200/r200_context.h | 6 -- src/mesa/drivers/dri/r200/r200_maos.h | 1 - src/mesa/drivers/dri/r200/r200_maos_arrays.c | 24 ++---- src/mesa/drivers/dri/r200/r200_state.h | 4 - src/mesa/drivers/dri/r200/r200_state_init.c | 16 ---- src/mesa/drivers/dri/r200/r200_swtcl.c | 4 - src/mesa/drivers/dri/r200/r200_swtcl.h | 1 - src/mesa/drivers/dri/r200/r200_tcl.c | 16 ++-- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 13 --- src/mesa/drivers/dri/r300/r300_cmdbuf.h | 2 - src/mesa/drivers/dri/r300/r300_context.c | 48 ----------- src/mesa/drivers/dri/r300/r300_context.h | 4 - src/mesa/drivers/dri/r300/r300_emit.c | 21 +---- src/mesa/drivers/dri/r300/r300_emit.h | 1 - src/mesa/drivers/dri/r300/r300_render.c | 98 +++++++++++----------- src/mesa/drivers/dri/radeon/Makefile | 3 +- .../drivers/dri/radeon/radeon_common_context.c | 90 +++++++++++++++----- .../drivers/dri/radeon/radeon_common_context.h | 12 ++- src/mesa/drivers/dri/radeon/radeon_context.c | 54 ++---------- src/mesa/drivers/dri/radeon/radeon_context.h | 24 ++---- src/mesa/drivers/dri/radeon/radeon_dma.c | 17 ++++ src/mesa/drivers/dri/radeon/radeon_dma.h | 1 + src/mesa/drivers/dri/radeon/radeon_ioctl.c | 76 ++++++++--------- src/mesa/drivers/dri/radeon/radeon_maos.h | 1 - src/mesa/drivers/dri/radeon/radeon_maos_arrays.c | 13 --- src/mesa/drivers/dri/radeon/radeon_maos_verts.c | 29 ++----- src/mesa/drivers/dri/radeon/radeon_screen.c | 46 +++------- src/mesa/drivers/dri/radeon/radeon_state.h | 3 - src/mesa/drivers/dri/radeon/radeon_state_init.c | 16 ---- src/mesa/drivers/dri/radeon/radeon_swtcl.c | 4 - src/mesa/drivers/dri/radeon/radeon_swtcl.h | 1 - src/mesa/drivers/dri/radeon/radeon_tcl.c | 8 +- 34 files changed, 286 insertions(+), 525 deletions(-) (limited to 'src/mesa/drivers/dri/r200/r200_tcl.c') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index 83375c88a7..3a11a448ec 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -143,18 +143,18 @@ static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type) if (!rmesa->radeon.radeonScreen->kernel_mm) { OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2); OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810); - OUT_BATCH_RELOC(rmesa->tcl.elt_dma_offset, - rmesa->tcl.elt_dma_bo, - rmesa->tcl.elt_dma_offset, + OUT_BATCH_RELOC(rmesa->radeon.tcl.elt_dma_offset, + rmesa->radeon.tcl.elt_dma_bo, + rmesa->radeon.tcl.elt_dma_offset, RADEON_GEM_DOMAIN_GTT, 0, 0); OUT_BATCH(vertex_count/2); } else { OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2); OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810); - OUT_BATCH(rmesa->tcl.elt_dma_offset); + OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset); OUT_BATCH(vertex_count/2); radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->tcl.elt_dma_bo, + rmesa->radeon.tcl.elt_dma_bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } END_BATCH(); @@ -176,12 +176,12 @@ void r200FlushElts(GLcontext *ctx) nr = elt_used / 2; - radeon_bo_unmap(rmesa->tcl.elt_dma_bo); + radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo); r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive); - radeon_bo_unref(rmesa->tcl.elt_dma_bo); - rmesa->tcl.elt_dma_bo = NULL; + radeon_bo_unref(rmesa->radeon.tcl.elt_dma_bo); + rmesa->radeon.tcl.elt_dma_bo = NULL; if (R200_DEBUG & DEBUG_SYNC) { fprintf(stderr, "%s: Syncing\n", __FUNCTION__); @@ -203,14 +203,14 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, radeonEmitState(&rmesa->radeon); - rmesa->tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, + rmesa->radeon.tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, 0, R200_ELT_BUF_SZ, 4, RADEON_GEM_DOMAIN_GTT, 0); - rmesa->tcl.elt_dma_offset = 0; + rmesa->radeon.tcl.elt_dma_offset = 0; rmesa->tcl.elt_used = min_nr * 2; - radeon_bo_map(rmesa->tcl.elt_dma_bo, 1); - retval = rmesa->tcl.elt_dma_bo->ptr + rmesa->tcl.elt_dma_offset; + radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1); + retval = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset; if (R200_DEBUG & DEBUG_PRIMS) @@ -264,79 +264,79 @@ void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset) if (!rmesa->radeon.radeonScreen->kernel_mm) { for (i = 0; i + 1 < nr; i += 2) { - OUT_BATCH((rmesa->tcl.aos[i].components << 0) | - (rmesa->tcl.aos[i].stride << 8) | - (rmesa->tcl.aos[i + 1].components << 16) | - (rmesa->tcl.aos[i + 1].stride << 24)); + OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) | + (rmesa->radeon.tcl.aos[i].stride << 8) | + (rmesa->radeon.tcl.aos[i + 1].components << 16) | + (rmesa->radeon.tcl.aos[i + 1].stride << 24)); - voffset = rmesa->tcl.aos[i + 0].offset + - offset * 4 * rmesa->tcl.aos[i + 0].stride; + voffset = rmesa->radeon.tcl.aos[i + 0].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; OUT_BATCH_RELOC(voffset, - rmesa->tcl.aos[i].bo, + rmesa->radeon.tcl.aos[i].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); - voffset = rmesa->tcl.aos[i + 1].offset + - offset * 4 * rmesa->tcl.aos[i + 1].stride; + voffset = rmesa->radeon.tcl.aos[i + 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; OUT_BATCH_RELOC(voffset, - rmesa->tcl.aos[i+1].bo, + rmesa->radeon.tcl.aos[i+1].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); } if (nr & 1) { - OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) | - (rmesa->tcl.aos[nr - 1].stride << 8)); - voffset = rmesa->tcl.aos[nr - 1].offset + - offset * 4 * rmesa->tcl.aos[nr - 1].stride; + OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | + (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); + voffset = rmesa->radeon.tcl.aos[nr - 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; OUT_BATCH_RELOC(voffset, - rmesa->tcl.aos[nr - 1].bo, + rmesa->radeon.tcl.aos[nr - 1].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); } } else { for (i = 0; i + 1 < nr; i += 2) { - OUT_BATCH((rmesa->tcl.aos[i].components << 0) | - (rmesa->tcl.aos[i].stride << 8) | - (rmesa->tcl.aos[i + 1].components << 16) | - (rmesa->tcl.aos[i + 1].stride << 24)); + OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) | + (rmesa->radeon.tcl.aos[i].stride << 8) | + (rmesa->radeon.tcl.aos[i + 1].components << 16) | + (rmesa->radeon.tcl.aos[i + 1].stride << 24)); - voffset = rmesa->tcl.aos[i + 0].offset + - offset * 4 * rmesa->tcl.aos[i + 0].stride; + voffset = rmesa->radeon.tcl.aos[i + 0].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; OUT_BATCH(voffset); - voffset = rmesa->tcl.aos[i + 1].offset + - offset * 4 * rmesa->tcl.aos[i + 1].stride; + voffset = rmesa->radeon.tcl.aos[i + 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; OUT_BATCH(voffset); } if (nr & 1) { - OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) | - (rmesa->tcl.aos[nr - 1].stride << 8)); - voffset = rmesa->tcl.aos[nr - 1].offset + - offset * 4 * rmesa->tcl.aos[nr - 1].stride; + OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | + (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); + voffset = rmesa->radeon.tcl.aos[nr - 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; OUT_BATCH(voffset); } for (i = 0; i + 1 < nr; i += 2) { - voffset = rmesa->tcl.aos[i + 0].offset + - offset * 4 * rmesa->tcl.aos[i + 0].stride; + voffset = rmesa->radeon.tcl.aos[i + 0].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->tcl.aos[i+0].bo, + rmesa->radeon.tcl.aos[i+0].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); - voffset = rmesa->tcl.aos[i + 1].offset + - offset * 4 * rmesa->tcl.aos[i + 1].stride; + voffset = rmesa->radeon.tcl.aos[i + 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->tcl.aos[i+1].bo, + rmesa->radeon.tcl.aos[i+1].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } if (nr & 1) { - voffset = rmesa->tcl.aos[nr - 1].offset + - offset * 4 * rmesa->tcl.aos[nr - 1].stride; + voffset = rmesa->radeon.tcl.aos[nr - 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->tcl.aos[nr-1].bo, + rmesa->radeon.tcl.aos[nr-1].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 564e168290..f80f0d8ac7 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -491,61 +491,3 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, } -/* Destroy the device specific context. - */ -/* Destroy the Mesa and driver specific context data. - */ -void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) -{ - GET_CURRENT_CONTEXT(ctx); - r200ContextPtr rmesa = (r200ContextPtr) driContextPriv->driverPrivate; - r200ContextPtr current = ctx ? R200_CONTEXT(ctx) : NULL; - - /* check if we're deleting the currently bound context */ - if (rmesa == current) { - radeon_firevertices(&rmesa->radeon); - _mesa_make_current(NULL, NULL, NULL); - } - - /* Free r200 context resources */ - assert(rmesa); /* should never be null */ - if ( rmesa ) { - - _swsetup_DestroyContext( rmesa->radeon.glCtx ); - _tnl_DestroyContext( rmesa->radeon.glCtx ); - _vbo_DestroyContext( rmesa->radeon.glCtx ); - _swrast_DestroyContext( rmesa->radeon.glCtx ); - - r200DestroySwtcl( rmesa->radeon.glCtx ); - r200ReleaseArrays( rmesa->radeon.glCtx, ~0 ); - - if (rmesa->radeon.dma.current) { - radeonReleaseDmaRegion( &rmesa->radeon ); - rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); - } - - if (rmesa->radeon.state.scissor.pClipRects) { - FREE(rmesa->radeon.state.scissor.pClipRects); - rmesa->radeon.state.scissor.pClipRects = NULL; - } - - radeonCleanupContext(&rmesa->radeon); - - FREE( rmesa ); - } -} - - - -/* Force the context `c' to be unbound from its buffer. - */ -GLboolean -r200UnbindContext( __DRIcontextPrivate *driContextPriv ) -{ - r200ContextPtr rmesa = (r200ContextPtr) driContextPriv->driverPrivate; - - if (R200_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *)rmesa->radeon.glCtx); - - return GL_TRUE; -} diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index fcbe725d6f..6267293817 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -526,14 +526,8 @@ struct r200_state { struct r200_tcl_info { GLuint hw_primitive; -/* hw can handle 12 components max */ - struct radeon_aos aos[12]; - GLuint nr_aos_components; - GLuint *Elts; - struct radeon_bo *elt_dma_bo; - int elt_dma_offset; /** Offset into this buffer object, in bytes */ int elt_used; }; diff --git a/src/mesa/drivers/dri/r200/r200_maos.h b/src/mesa/drivers/dri/r200/r200_maos.h index d3ed06d402..16a70475e1 100644 --- a/src/mesa/drivers/dri/r200/r200_maos.h +++ b/src/mesa/drivers/dri/r200/r200_maos.h @@ -38,6 +38,5 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r200_context.h" extern void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ); -extern void r200ReleaseArrays( GLcontext *ctx, GLuint newinputs ); #endif diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c index 5dbc202330..383a0c4b0d 100644 --- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c +++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c @@ -142,17 +142,17 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) case 3: /* special handling to fix up fog. Will get us into trouble with vbos...*/ assert(attrib == VERT_ATTRIB_FOG); - if (!rmesa->tcl.aos[i].bo) { + if (!rmesa->radeon.tcl.aos[i].bo) { if (ctx->VertexProgram._Enabled) rcommon_emit_vector( ctx, - &(rmesa->tcl.aos[nr]), + &(rmesa->radeon.tcl.aos[nr]), (char *)VB->AttribPtr[attrib]->data, 1, VB->AttribPtr[attrib]->stride, count); else r200_emit_vecfog( ctx, - &(rmesa->tcl.aos[nr]), + &(rmesa->radeon.tcl.aos[nr]), (char *)VB->AttribPtr[attrib]->data, VB->AttribPtr[attrib]->stride, count); @@ -199,9 +199,9 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) default: assert(0); } - if (!rmesa->tcl.aos[nr].bo) { + if (!rmesa->radeon.tcl.aos[nr].bo) { rcommon_emit_vector( ctx, - &(rmesa->tcl.aos[nr]), + &(rmesa->radeon.tcl.aos[nr]), (char *)VB->AttribPtr[attrib]->data, emitsize, VB->AttribPtr[attrib]->stride, @@ -220,18 +220,6 @@ after_emit: rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = vfmt1; } - rmesa->tcl.nr_aos_components = nr; + rmesa->radeon.tcl.aos_count = nr; } - -void r200ReleaseArrays( GLcontext *ctx, GLuint newinputs ) -{ - r200ContextPtr rmesa = R200_CONTEXT( ctx ); - int i; - for (i = 0; i < rmesa->tcl.nr_aos_components; i++) { - if (rmesa->tcl.aos[i].bo) { - radeon_bo_unref(rmesa->tcl.aos[i].bo); - rmesa->tcl.aos[i].bo = NULL; - } - } -} diff --git a/src/mesa/drivers/dri/r200/r200_state.h b/src/mesa/drivers/dri/r200/r200_state.h index 1dddbfdbfe..23cf8aea66 100644 --- a/src/mesa/drivers/dri/r200/r200_state.h +++ b/src/mesa/drivers/dri/r200/r200_state.h @@ -49,10 +49,6 @@ extern void r200UpdateDrawBuffer(GLcontext *ctx); extern GLboolean r200ValidateState( GLcontext *ctx ); -extern void r200PrintDirty( r200ContextPtr rmesa, - const char *msg ); - - extern void r200Fallback( GLcontext *ctx, GLuint bit, GLboolean mode ); #define FALLBACK( rmesa, bit, mode ) do { \ if ( 0 ) fprintf( stderr, "FALLBACK in %s: #%d=%d\n", \ diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index 2400abe838..75262e46bd 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -166,22 +166,6 @@ static struct { /* ============================================================= * State initialization */ - -void r200PrintDirty( r200ContextPtr rmesa, const char *msg ) -{ - struct radeon_state_atom *l; - - fprintf(stderr, msg); - fprintf(stderr, ": "); - - foreach(l, &rmesa->radeon.hw.atomlist) { - if (l->dirty || rmesa->radeon.hw.all_dirty) - fprintf(stderr, "%s, ", l->name); - } - - fprintf(stderr, "\n"); -} - static int cmdpkt( r200ContextPtr rmesa, int id ) { drm_radeon_cmd_header_t h; diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index b006409987..712da98077 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -908,7 +908,3 @@ void r200InitSwtcl( GLcontext *ctx ) rmesa->radeon.swtcl.hw_primitive = 0; } - -void r200DestroySwtcl( GLcontext *ctx ) -{ -} diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.h b/src/mesa/drivers/dri/r200/r200_swtcl.h index a4051a4b76..b0905879d7 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.h +++ b/src/mesa/drivers/dri/r200/r200_swtcl.h @@ -39,7 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r200_context.h" extern void r200InitSwtcl( GLcontext *ctx ); -extern void r200DestroySwtcl( GLcontext *ctx ); extern void r200ChooseRenderState( GLcontext *ctx ); extern void r200ChooseVertexState( GLcontext *ctx ); diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 8e0fb14e70..580370933e 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -145,7 +145,7 @@ static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) if (rmesa->radeon.dma.flush == r200FlushElts && rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) { - GLushort *dest = (GLushort *)(rmesa->tcl.elt_dma_bo->ptr + + GLushort *dest = (GLushort *)(rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->tcl.elt_used); rmesa->tcl.elt_used += nr*2; @@ -156,10 +156,10 @@ static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) if (rmesa->radeon.dma.flush) rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); - rcommonEnsureCmdBufSpace(&rmesa->radeon, AOS_BUFSZ(rmesa->tcl.nr_aos_components), __FUNCTION__); + rcommonEnsureCmdBufSpace(&rmesa->radeon, AOS_BUFSZ(rmesa->radeon.tcl.aos_count), __FUNCTION__); r200EmitAOS( rmesa, - rmesa->tcl.nr_aos_components, 0 ); + rmesa->radeon.tcl.aos_count, 0 ); return r200AllocEltsOpenEnded( rmesa, rmesa->tcl.hw_primitive, nr ); } @@ -186,13 +186,13 @@ static void r200EmitPrim( GLcontext *ctx, r200ContextPtr rmesa = R200_CONTEXT( ctx ); r200TclPrimitive( ctx, prim, hwprim ); - // fprintf(stderr,"Emit prim %d\n", rmesa->tcl.nr_aos_components); + // fprintf(stderr,"Emit prim %d\n", rmesa->radeon.tcl.aos_count); rcommonEnsureCmdBufSpace( &rmesa->radeon, - AOS_BUFSZ(rmesa->tcl.nr_aos_components) + + AOS_BUFSZ(rmesa->radeon.tcl.aos_count) + rmesa->radeon.hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ ); r200EmitAOS( rmesa, - rmesa->tcl.nr_aos_components, + rmesa->radeon.tcl.aos_count, start ); /* Why couldn't this packet have taken an offset param? @@ -481,7 +481,7 @@ static GLboolean r200_run_tcl_render( GLcontext *ctx, /* Do the actual work: */ - r200ReleaseArrays( ctx, ~0 /* stage->changed_inputs */ ); + radeonReleaseArrays( ctx, ~0 /* stage->changed_inputs */ ); r200EmitArrays( ctx, vimap_rev ); rmesa->tcl.Elts = VB->Elts; @@ -545,7 +545,7 @@ static void transition_to_swtnl( GLcontext *ctx ) tnl->Driver.NotifyMaterialChange = _mesa_validate_all_lighting_tables; - r200ReleaseArrays( ctx, ~0 ); + radeonReleaseArrays( ctx, ~0 ); /* Still using the D3D based hardware-rasterizer from the radeon; * need to put the card into D3D mode to make it work: diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index fc8a2e7431..1ecbeea489 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -649,16 +649,3 @@ void r300InitCmdBuf(r300ContextPtr r300) rcommonInitCmdBuf(&r300->radeon); } - -/** - * Destroy the command buffer and state atoms. - */ -void r300DestroyCmdBuf(r300ContextPtr r300) -{ - struct radeon_state_atom *atom; - - foreach(atom, &r300->radeon.hw.atomlist) { - FREE(atom->cmd); - } - -} diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h index b7798eb97b..3786813de3 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h @@ -39,8 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_context.h" extern void r300InitCmdBuf(r300ContextPtr r300); -extern void r300DestroyCmdBuf(r300ContextPtr r300); - void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom); int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom); diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 5e271c6010..06db7ab8ff 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -470,51 +470,3 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, return GL_TRUE; } -/* Destroy the device specific context. - */ -void r300DestroyContext(__DRIcontextPrivate * driContextPriv) -{ - GET_CURRENT_CONTEXT(ctx); - r300ContextPtr r300 = (r300ContextPtr) driContextPriv->driverPrivate; - radeonContextPtr radeon = (radeonContextPtr) r300; - radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL; - - if (RADEON_DEBUG & DEBUG_DRI) { - fprintf(stderr, "Destroying context !\n"); - } - - /* check if we're deleting the currently bound context */ - if (&r300->radeon == current) { - radeonFlush(r300->radeon.glCtx); - _mesa_make_current(NULL, NULL, NULL); - } - - /* Free r300 context resources */ - assert(r300); /* should never be null */ - - if (r300) { - _swsetup_DestroyContext(r300->radeon.glCtx); - _tnl_DestroyContext(r300->radeon.glCtx); - _vbo_DestroyContext(r300->radeon.glCtx); - _swrast_DestroyContext(r300->radeon.glCtx); - - radeon_firevertices(&r300->radeon); - - if (radeon->state.scissor.pClipRects) { - FREE(radeon->state.scissor.pClipRects); - radeon->state.scissor.pClipRects = NULL; - } - - r300DestroyCmdBuf(r300); - - radeonCleanupContext(&r300->radeon); - - - /* the memory manager might be accessed when Mesa frees the shared - * state, so don't destroy it earlier - */ - - - FREE(r300); - } -} diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 37718f5415..5ef59d258e 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -633,11 +633,7 @@ struct r300_state { struct r300_texture_state texture; int sw_tcl_inputs[VERT_ATTRIB_MAX]; struct r300_vertex_shader_state vertex_shader; - struct radeon_aos aos[R300_MAX_AOS_ARRAYS]; - int aos_count; - struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */ - int elt_dma_offset; /** Offset into this buffer object, in bytes */ DECLARE_RENDERINPUTS(render_inputs_bitset); /* actual render inputs that R300 was configured for. They are the same as tnl->render_inputs for fixed pipeline */ diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c index 4bf0e7a189..3ce0ba68c9 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.c +++ b/src/mesa/drivers/dri/r300/r300_emit.c @@ -302,7 +302,7 @@ int r300EmitArrays(GLcontext * ctx) for (ci = 0; ci < vb->AttribPtr[tab[i]]->size; ci++) { swizzle[i][ci] = ci; } - rcommon_emit_vector(ctx, &rmesa->state.aos[i], + rcommon_emit_vector(ctx, &rmesa->radeon.tcl.aos[i], vb->AttribPtr[tab[i]]->data, vb->AttribPtr[tab[i]]->size, vb->AttribPtr[tab[i]]->stride, count); @@ -343,28 +343,11 @@ int r300EmitArrays(GLcontext * ctx) rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = r300VAPOutputCntl1(ctx, OutputsWritten); - rmesa->state.aos_count = nr; + rmesa->radeon.tcl.aos_count = nr; return R300_FALLBACK_NONE; } -void r300ReleaseArrays(GLcontext * ctx) -{ - r300ContextPtr rmesa = R300_CONTEXT(ctx); - int i; - - if (rmesa->state.elt_dma_bo) { - radeon_bo_unref(rmesa->state.elt_dma_bo); - rmesa->state.elt_dma_bo = NULL; - } - for (i = 0; i < rmesa->state.aos_count; i++) { - if (rmesa->state.aos[i].bo) { - radeon_bo_unref(rmesa->state.aos[i].bo); - rmesa->state.aos[i].bo = NULL; - } - } -} - void r300EmitCacheFlush(r300ContextPtr rmesa) { BATCH_LOCALS(&rmesa->radeon); diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h index 6bc8f8e944..80c22d5e9a 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.h +++ b/src/mesa/drivers/dri/r300/r300_emit.h @@ -218,7 +218,6 @@ void static INLINE cp_wait(radeonContextPtr radeon, unsigned char flags) extern int r300EmitArrays(GLcontext * ctx); -extern void r300ReleaseArrays(GLcontext * ctx); extern int r300PrimitiveType(r300ContextPtr rmesa, int prim); extern int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim); diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 829d088033..924305dd12 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -175,12 +175,12 @@ static void r300EmitElts(GLcontext * ctx, void *elts, unsigned long n_elts) r300ContextPtr rmesa = R300_CONTEXT(ctx); void *out; - radeonAllocDmaRegion(&rmesa->radeon, &rmesa->state.elt_dma_bo, - &rmesa->state.elt_dma_offset, n_elts * 4, 4); - radeon_bo_map(rmesa->state.elt_dma_bo, 1); - out = rmesa->state.elt_dma_bo->ptr + rmesa->state.elt_dma_offset; + radeonAllocDmaRegion(&rmesa->radeon, &rmesa->radeon.tcl.elt_dma_bo, + &rmesa->radeon.tcl.elt_dma_offset, n_elts * 4, 4); + radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1); + out = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset; memcpy(out, elts, n_elts * 4); - radeon_bo_unmap(rmesa->state.elt_dma_bo); + radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo); } static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) @@ -199,19 +199,19 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) | (R300_VAP_PORT_IDX0 >> 2)); - OUT_BATCH_RELOC(rmesa->state.elt_dma_offset, - rmesa->state.elt_dma_bo, - rmesa->state.elt_dma_offset, + OUT_BATCH_RELOC(rmesa->radeon.tcl.elt_dma_offset, + rmesa->radeon.tcl.elt_dma_bo, + rmesa->radeon.tcl.elt_dma_offset, RADEON_GEM_DOMAIN_GTT, 0, 0); OUT_BATCH(vertex_count); } else { OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) | (R300_VAP_PORT_IDX0 >> 2)); - OUT_BATCH(rmesa->state.elt_dma_offset); + OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset); OUT_BATCH(vertex_count); radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->state.elt_dma_bo, + rmesa->radeon.tcl.elt_dma_bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } END_BATCH(); @@ -236,34 +236,34 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) OUT_BATCH(nr); for (i = 0; i + 1 < nr; i += 2) { - OUT_BATCH((rmesa->state.aos[i].components << 0) | - (rmesa->state.aos[i].stride << 8) | - (rmesa->state.aos[i + 1].components << 16) | - (rmesa->state.aos[i + 1].stride << 24)); + OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) | + (rmesa->radeon.tcl.aos[i].stride << 8) | + (rmesa->radeon.tcl.aos[i + 1].components << 16) | + (rmesa->radeon.tcl.aos[i + 1].stride << 24)); - voffset = rmesa->state.aos[i + 0].offset + - offset * 4 * rmesa->state.aos[i + 0].stride; + voffset = rmesa->radeon.tcl.aos[i + 0].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; OUT_BATCH_RELOC(voffset, - rmesa->state.aos[i].bo, + rmesa->radeon.tcl.aos[i].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); - voffset = rmesa->state.aos[i + 1].offset + - offset * 4 * rmesa->state.aos[i + 1].stride; + voffset = rmesa->radeon.tcl.aos[i + 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; OUT_BATCH_RELOC(voffset, - rmesa->state.aos[i+1].bo, + rmesa->radeon.tcl.aos[i+1].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); } if (nr & 1) { - OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) | - (rmesa->state.aos[nr - 1].stride << 8)); - voffset = rmesa->state.aos[nr - 1].offset + - offset * 4 * rmesa->state.aos[nr - 1].stride; + OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | + (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); + voffset = rmesa->radeon.tcl.aos[nr - 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; OUT_BATCH_RELOC(voffset, - rmesa->state.aos[nr - 1].bo, + rmesa->radeon.tcl.aos[nr - 1].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); @@ -276,45 +276,45 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) OUT_BATCH(nr); for (i = 0; i + 1 < nr; i += 2) { - OUT_BATCH((rmesa->state.aos[i].components << 0) | - (rmesa->state.aos[i].stride << 8) | - (rmesa->state.aos[i + 1].components << 16) | - (rmesa->state.aos[i + 1].stride << 24)); + OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) | + (rmesa->radeon.tcl.aos[i].stride << 8) | + (rmesa->radeon.tcl.aos[i + 1].components << 16) | + (rmesa->radeon.tcl.aos[i + 1].stride << 24)); - voffset = rmesa->state.aos[i + 0].offset + - offset * 4 * rmesa->state.aos[i + 0].stride; + voffset = rmesa->radeon.tcl.aos[i + 0].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; OUT_BATCH(voffset); - voffset = rmesa->state.aos[i + 1].offset + - offset * 4 * rmesa->state.aos[i + 1].stride; + voffset = rmesa->radeon.tcl.aos[i + 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; OUT_BATCH(voffset); } if (nr & 1) { - OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) | - (rmesa->state.aos[nr - 1].stride << 8)); - voffset = rmesa->state.aos[nr - 1].offset + - offset * 4 * rmesa->state.aos[nr - 1].stride; + OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | + (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); + voffset = rmesa->radeon.tcl.aos[nr - 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; OUT_BATCH(voffset); } for (i = 0; i + 1 < nr; i += 2) { - voffset = rmesa->state.aos[i + 0].offset + - offset * 4 * rmesa->state.aos[i + 0].stride; + voffset = rmesa->radeon.tcl.aos[i + 0].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->state.aos[i+0].bo, + rmesa->radeon.tcl.aos[i+0].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); - voffset = rmesa->state.aos[i + 1].offset + - offset * 4 * rmesa->state.aos[i + 1].stride; + voffset = rmesa->radeon.tcl.aos[i + 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->state.aos[i+1].bo, + rmesa->radeon.tcl.aos[i+1].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } if (nr & 1) { - voffset = rmesa->state.aos[nr - 1].offset + - offset * 4 * rmesa->state.aos[nr - 1].stride; + voffset = rmesa->radeon.tcl.aos[nr - 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->state.aos[nr-1].bo, + rmesa->radeon.tcl.aos[nr-1].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } @@ -370,10 +370,10 @@ static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx, * arrays. *sigh* */ r300EmitElts(ctx, vb->Elts, num_verts); - r300EmitAOS(rmesa, rmesa->state.aos_count, start); + r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start); r300FireEB(rmesa, num_verts, type); } else { - r300EmitAOS(rmesa, rmesa->state.aos_count, start); + r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start); r300FireAOS(rmesa, num_verts, type); } COMMIT_BATCH(); @@ -408,7 +408,7 @@ static GLboolean r300RunRender(GLcontext * ctx, r300EmitCacheFlush(rmesa); - r300ReleaseArrays(ctx); + radeonReleaseArrays(ctx, ~0); return GL_FALSE; } diff --git a/src/mesa/drivers/dri/radeon/Makefile b/src/mesa/drivers/dri/radeon/Makefile index f469c6f43a..ba409ba813 100644 --- a/src/mesa/drivers/dri/radeon/Makefile +++ b/src/mesa/drivers/dri/radeon/Makefile @@ -19,7 +19,8 @@ RADEON_COMMON_SOURCES = \ radeon_bo_legacy.c \ radeon_cs_legacy.c \ radeon_mipmap_tree.c \ - radeon_span.c + radeon_span.c \ + radeon_fbo.c DRIVER_SOURCES = \ radeon_context.c \ diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index 9103c8c0f6..4d61b00345 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -37,8 +37,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "utils.h" #include "vblank.h" #include "drirenderbuffer.h" +#include "main/context.h" #include "main/framebuffer.h" #include "main/state.h" +#include "main/simple_list.h" +#include "swrast/swrast.h" +#include "swrast_setup/swrast_setup.h" +#include "tnl/tnl.h" #define DRIVER_DATE "20090101" @@ -175,39 +180,81 @@ GLboolean radeonInitContext(radeonContextPtr radeon, return GL_TRUE; } + + +/** + * Destroy the command buffer and state atoms. + */ +static void radeon_destroy_atom_list(radeonContextPtr radeon) +{ + struct radeon_state_atom *atom; + + foreach(atom, &radeon->hw.atomlist) { + FREE(atom->cmd); + if (atom->lastcmd) + FREE(atom->lastcmd); + } + +} + /** * Cleanup common context fields. * Called by r200DestroyContext/r300DestroyContext */ -void radeonCleanupContext(radeonContextPtr radeon) +void radeonDestroyContext(__DRIcontextPrivate *driContextPriv ) { #ifdef RADEON_BO_TRACK FILE *track; #endif - struct radeon_framebuffer *rfb; - - radeonDestroyBuffer(radeon->dri.drawable); - radeonDestroyBuffer(radeon->dri.readable); - - /* free the Mesa context */ - _mesa_destroy_context(radeon->glCtx); - - /* _mesa_destroy_context() might result in calls to functions that - * depend on the DriverCtx, so don't set it to NULL before. - * - * radeon->glCtx->DriverCtx = NULL; - */ - + GET_CURRENT_CONTEXT(ctx); + radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; + radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL; + if (radeon == current) { + radeon_firevertices(radeon); + _mesa_make_current(NULL, NULL, NULL); + } + + assert(radeon); + if (radeon) { - /* free the option cache */ - driDestroyOptionCache(&radeon->optionCache); + if (radeon->dma.current) { + radeonReleaseDmaRegion( radeon ); + rcommonFlushCmdBuf( radeon, __FUNCTION__ ); + } - rcommonDestroyCmdBuf(radeon); + radeonReleaseArrays(ctx, ~0); - if (radeon->state.scissor.pClipRects) { - FREE(radeon->state.scissor.pClipRects); - radeon->state.scissor.pClipRects = 0; + if (radeon->vtbl.free_context) + radeon->vtbl.free_context(radeon->glCtx); + _swsetup_DestroyContext( radeon->glCtx ); + _tnl_DestroyContext( radeon->glCtx ); + _vbo_DestroyContext( radeon->glCtx ); + _swrast_DestroyContext( radeon->glCtx ); + + radeonDestroyBuffer(radeon->dri.drawable); + radeonDestroyBuffer(radeon->dri.readable); + + /* free atom list */ + /* free the Mesa context */ + _mesa_destroy_context(radeon->glCtx); + + /* _mesa_destroy_context() might result in calls to functions that + * depend on the DriverCtx, so don't set it to NULL before. + * + * radeon->glCtx->DriverCtx = NULL; + */ + /* free the option cache */ + driDestroyOptionCache(&radeon->optionCache); + + rcommonDestroyCmdBuf(radeon); + + radeon_destroy_atom_list(radeon); + + if (radeon->state.scissor.pClipRects) { + FREE(radeon->state.scissor.pClipRects); + radeon->state.scissor.pClipRects = 0; + } } #ifdef RADEON_BO_TRACK track = fopen("/tmp/tracklog", "w"); @@ -216,6 +263,7 @@ void radeonCleanupContext(radeonContextPtr radeon) fclose(track); } #endif + FREE(radeon); } /* Force the context `c' to be unbound from its buffer. diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index 0ce72c9198..c6e6be7484 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -290,6 +290,14 @@ struct radeon_swtcl_info { }; +#define RADEON_MAX_AOS_ARRAYS 16 +struct radeon_tcl_info { + struct radeon_aos aos[RADEON_MAX_AOS_ARRAYS]; + GLuint aos_count; + struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */ + int elt_dma_offset; /** Offset into this buffer object, in bytes */ +}; + struct radeon_ioctl { GLuint vertex_offset; struct radeon_bo *bo; @@ -367,7 +375,6 @@ struct radeon_dri_mirror { #define DEBUG_MEMORY 0x4000 - typedef void (*radeon_tri_func) (radeonContextPtr, radeonVertex *, radeonVertex *, radeonVertex *); @@ -436,6 +443,7 @@ struct radeon_context { struct radeon_state state; struct radeon_swtcl_info swtcl; + struct radeon_tcl_info tcl; /* Configuration cache */ driOptionCache optionCache; @@ -468,6 +476,7 @@ struct radeon_context { void (*pre_emit_atoms)(radeonContextPtr rmesa); void (*pre_emit_state)(radeonContextPtr rmesa); void (*fallback)(GLcontext *ctx, GLuint bit, GLboolean mode); + void (*free_context)(GLcontext *ctx); } vtbl; }; @@ -530,6 +539,7 @@ void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable) GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, __DRIdrawablePrivate * driDrawPriv, __DRIdrawablePrivate * driReadPriv); +extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv); /* ================================================================ * Debugging: diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index cad2c3e0c1..2600c78df3 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -188,6 +188,11 @@ static void r100_vtbl_pre_emit_state(radeonContextPtr radeon) radeon->hw.is_dirty = 1; } +static void r100_vtbl_free_context(GLcontext *ctx) +{ + r100ContextPtr rmesa = R100_CONTEXT(ctx); + _mesa_vector4f_free( &rmesa->tcl.ObjClean ); +} static void r100_init_vtbl(radeonContextPtr radeon) { @@ -202,7 +207,7 @@ static void r100_init_vtbl(radeonContextPtr radeon) /* Create the device specific context. */ GLboolean -radeonCreateContext( const __GLcontextModes *glVisual, +r100CreateContext( const __GLcontextModes *glVisual, __DRIcontextPrivate *driContextPriv, void *sharedContextPrivate) { @@ -397,50 +402,3 @@ radeonCreateContext( const __GLcontextModes *glVisual, } return GL_TRUE; } - - -/* Destroy the device specific context. - */ -/* Destroy the Mesa and driver specific context data. - */ -void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) -{ - GET_CURRENT_CONTEXT(ctx); - r100ContextPtr rmesa = (r100ContextPtr) driContextPriv->driverPrivate; - r100ContextPtr current = ctx ? R100_CONTEXT(ctx) : NULL; - - /* check if we're deleting the currently bound context */ - if (rmesa == current) { - radeon_firevertices(&rmesa->radeon); - _mesa_make_current(NULL, NULL, NULL); - } - - /* Free radeon context resources */ - assert(rmesa); /* should never be null */ - if ( rmesa ) { - - _swsetup_DestroyContext( rmesa->radeon.glCtx ); - _tnl_DestroyContext( rmesa->radeon.glCtx ); - _vbo_DestroyContext( rmesa->radeon.glCtx ); - _swrast_DestroyContext( rmesa->radeon.glCtx ); - - radeonDestroySwtcl( rmesa->radeon.glCtx ); - radeonReleaseArrays( rmesa->radeon.glCtx, ~0 ); - if (rmesa->radeon.dma.current) { - radeonReleaseDmaRegion( &rmesa->radeon ); - rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); - } - - _mesa_vector4f_free( &rmesa->tcl.ObjClean ); - - if (rmesa->radeon.state.scissor.pClipRects) { - FREE(rmesa->radeon.state.scissor.pClipRects); - rmesa->radeon.state.scissor.pClipRects = NULL; - } - - radeonCleanupContext(&rmesa->radeon); - - FREE( rmesa ); - } -} - diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h index 5235a6e374..1795d8bdb6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -332,7 +332,7 @@ struct r100_state { #define R200_ELT_BUF_SZ (8*1024) /* radeon_tcl.c */ -struct radeon_tcl_info { +struct r100_tcl_info { GLuint vertex_format; GLuint hw_primitive; @@ -341,14 +341,9 @@ struct radeon_tcl_info { */ GLvector4f ObjClean; - struct radeon_aos aos[8]; - GLuint nr_aos_components; - GLuint *Elts; - struct radeon_bo *indexed_bo; - - int elt_cmd_offset; /** Offset into the cmdbuf */ + int elt_cmd_offset; int elt_cmd_start; int elt_used; }; @@ -416,7 +411,7 @@ struct r100_context { /* radeon_tcl.c */ - struct radeon_tcl_info tcl; + struct r100_tcl_info tcl; /* radeon_swtcl.c */ @@ -443,15 +438,10 @@ struct r100_context { #define RADEON_OLD_PACKETS 1 -extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv); -extern GLboolean radeonCreateContext(const __GLcontextModes * glVisual, - __DRIcontextPrivate * driContextPriv, - void *sharedContextPrivate); -extern GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, - __DRIdrawablePrivate * driDrawPriv, - __DRIdrawablePrivate * driReadPriv); -extern GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv); - +extern GLboolean r100CreateContext( const __GLcontextModes *glVisual, + __DRIcontextPrivate *driContextPriv, + void *sharedContextPrivate); + #endif /* __RADEON_CONTEXT_H__ */ diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c index 01fc20bd79..47f789e9cd 100644 --- a/src/mesa/drivers/dri/radeon/radeon_dma.c +++ b/src/mesa/drivers/dri/radeon/radeon_dma.c @@ -328,3 +328,20 @@ restart: rmesa->swtcl.numverts += nverts; return head; } + +void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs ) +{ + radeonContextPtr radeon = RADEON_CONTEXT( ctx ); + int i; + + if (radeon->tcl.elt_dma_bo) { + radeon_bo_unref(radeon->tcl.elt_dma_bo); + radeon->tcl.elt_dma_bo = NULL; + } + for (i = 0; i < radeon->tcl.aos_count; i++) { + if (radeon->tcl.aos[i].bo) { + radeon_bo_unref(radeon->tcl.aos[i].bo); + radeon->tcl.aos[i].bo = NULL; + } + } +} diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.h b/src/mesa/drivers/dri/radeon/radeon_dma.h index cee3744fed..06e388fc1d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_dma.h +++ b/src/mesa/drivers/dri/radeon/radeon_dma.h @@ -48,4 +48,5 @@ void radeonReleaseDmaRegion(radeonContextPtr rmesa); void rcommon_flush_last_swtcl_prim(GLcontext *ctx); void *rcommonAllocDmaLowVerts(radeonContextPtr rmesa, int nverts, int vsize); +void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs ); #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index f18aa1a4da..b5fde6d3de 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -313,9 +313,9 @@ void radeonEmitAOS( r100ContextPtr rmesa, { #if RADEON_OLD_PACKETS assert( nr == 1 ); - rmesa->ioctl.bo = rmesa->tcl.aos[0].bo; + rmesa->ioctl.bo = rmesa->radeon.tcl.aos[0].bo; rmesa->ioctl.vertex_offset = - (rmesa->tcl.aos[0].offset + offset * rmesa->tcl.aos[0].stride * 4); + (rmesa->radeon.tcl.aos[0].offset + offset * rmesa->radeon.tcl.aos[0].stride * 4); #else BATCH_LOCALS(&rmesa->radeon); uint32_t voffset; @@ -332,79 +332,79 @@ void radeonEmitAOS( r100ContextPtr rmesa, if (!rmesa->radeon.radeonScreen->kernel_mm) { for (i = 0; i + 1 < nr; i += 2) { - OUT_BATCH((rmesa->tcl.aos[i].components << 0) | - (rmesa->tcl.aos[i].stride << 8) | - (rmesa->tcl.aos[i + 1].components << 16) | - (rmesa->tcl.aos[i + 1].stride << 24)); + OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) | + (rmesa->radeon.tcl.aos[i].stride << 8) | + (rmesa->radeon.tcl.aos[i + 1].components << 16) | + (rmesa->radeon.tcl.aos[i + 1].stride << 24)); - voffset = rmesa->tcl.aos[i + 0].offset + - offset * 4 * rmesa->tcl.aos[i + 0].stride; + voffset = rmesa->radeon.tcl.aos[i + 0].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; OUT_BATCH_RELOC(voffset, - rmesa->tcl.aos[i].bo, + rmesa->radeon.tcl.aos[i].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); - voffset = rmesa->tcl.aos[i + 1].offset + - offset * 4 * rmesa->tcl.aos[i + 1].stride; + voffset = rmesa->radeon.tcl.aos[i + 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; OUT_BATCH_RELOC(voffset, - rmesa->tcl.aos[i+1].bo, + rmesa->radeon.tcl.aos[i+1].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); } if (nr & 1) { - OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) | - (rmesa->tcl.aos[nr - 1].stride << 8)); - voffset = rmesa->tcl.aos[nr - 1].offset + - offset * 4 * rmesa->tcl.aos[nr - 1].stride; + OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | + (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); + voffset = rmesa->radeon.tcl.aos[nr - 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; OUT_BATCH_RELOC(voffset, - rmesa->tcl.aos[nr - 1].bo, + rmesa->radeon.tcl.aos[nr - 1].bo, voffset, RADEON_GEM_DOMAIN_GTT, 0, 0); } } else { for (i = 0; i + 1 < nr; i += 2) { - OUT_BATCH((rmesa->tcl.aos[i].components << 0) | - (rmesa->tcl.aos[i].stride << 8) | - (rmesa->tcl.aos[i + 1].components << 16) | - (rmesa->tcl.aos[i + 1].stride << 24)); + OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) | + (rmesa->radeon.tcl.aos[i].stride << 8) | + (rmesa->radeon.tcl.aos[i + 1].components << 16) | + (rmesa->radeon.tcl.aos[i + 1].stride << 24)); - voffset = rmesa->tcl.aos[i + 0].offset + - offset * 4 * rmesa->tcl.aos[i + 0].stride; + voffset = rmesa->radeon.tcl.aos[i + 0].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; OUT_BATCH(voffset); - voffset = rmesa->tcl.aos[i + 1].offset + - offset * 4 * rmesa->tcl.aos[i + 1].stride; + voffset = rmesa->radeon.tcl.aos[i + 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; OUT_BATCH(voffset); } if (nr & 1) { - OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) | - (rmesa->tcl.aos[nr - 1].stride << 8)); - voffset = rmesa->tcl.aos[nr - 1].offset + - offset * 4 * rmesa->tcl.aos[nr - 1].stride; + OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | + (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); + voffset = rmesa->radeon.tcl.aos[nr - 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; OUT_BATCH(voffset); } for (i = 0; i + 1 < nr; i += 2) { - voffset = rmesa->tcl.aos[i + 0].offset + - offset * 4 * rmesa->tcl.aos[i + 0].stride; + voffset = rmesa->radeon.tcl.aos[i + 0].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->tcl.aos[i+0].bo, + rmesa->radeon.tcl.aos[i+0].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); - voffset = rmesa->tcl.aos[i + 1].offset + - offset * 4 * rmesa->tcl.aos[i + 1].stride; + voffset = rmesa->radeon.tcl.aos[i + 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->tcl.aos[i+1].bo, + rmesa->radeon.tcl.aos[i+1].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } if (nr & 1) { - voffset = rmesa->tcl.aos[nr - 1].offset + - offset * 4 * rmesa->tcl.aos[nr - 1].stride; + voffset = rmesa->radeon.tcl.aos[nr - 1].offset + + offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->tcl.aos[nr-1].bo, + rmesa->radeon.tcl.aos[nr-1].bo, RADEON_GEM_DOMAIN_GTT, 0, 0); } diff --git a/src/mesa/drivers/dri/radeon/radeon_maos.h b/src/mesa/drivers/dri/radeon/radeon_maos.h index b8935e84a0..b88eb198d5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos.h +++ b/src/mesa/drivers/dri/radeon/radeon_maos.h @@ -38,6 +38,5 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_context.h" extern void radeonEmitArrays( GLcontext *ctx, GLuint inputs ); -extern void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs ); #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c index 7f5da16b03..7c6ea0530e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c +++ b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c @@ -324,16 +324,3 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) rmesa->tcl.vertex_format = vfmt; } - -void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs ) -{ - r100ContextPtr rmesa = R100_CONTEXT( ctx ); - int i; - - for (i = 0; i < rmesa->tcl.nr_aos_components; i++) { - if (rmesa->tcl.aos[i].bo) { - radeon_bo_unref(rmesa->tcl.aos[i].bo); - rmesa->tcl.aos[i].bo = NULL; - } - } -} diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c index d468a97200..78ec119302 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c +++ b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c @@ -374,15 +374,15 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) break; if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format && - rmesa->tcl.aos[0].bo) + rmesa->radeon.tcl.aos[0].bo) return; - if (rmesa->tcl.aos[0].bo) + if (rmesa->radeon.tcl.aos[0].bo) radeonReleaseArrays( ctx, ~0 ); radeonAllocDmaRegion( &rmesa->radeon, - &rmesa->tcl.aos[0].bo, - &rmesa->tcl.aos[0].offset, + &rmesa->radeon.tcl.aos[0].bo, + &rmesa->radeon.tcl.aos[0].offset, VB->Count * setup_tab[i].vertex_size * 4, 4); @@ -422,25 +422,12 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) setup_tab[i].emit( ctx, 0, VB->Count, - rmesa->tcl.aos[0].bo->ptr + rmesa->tcl.aos[0].offset); + rmesa->radeon.tcl.aos[0].bo->ptr + rmesa->radeon.tcl.aos[0].offset); - // rmesa->tcl.aos[0].size = setup_tab[i].vertex_size; - rmesa->tcl.aos[0].stride = setup_tab[i].vertex_size; + // rmesa->radeon.tcl.aos[0].size = setup_tab[i].vertex_size; + rmesa->radeon.tcl.aos[0].stride = setup_tab[i].vertex_size; rmesa->tcl.vertex_format = setup_tab[i].vertex_format; - rmesa->tcl.nr_aos_components = 1; + rmesa->radeon.tcl.aos_count = 1; } - -void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs ) -{ - r100ContextPtr rmesa = R100_CONTEXT( ctx ); - int i; - - for (i = 0; i < rmesa->tcl.nr_aos_components; i++) { - if (rmesa->tcl.aos[i].bo) { - radeon_bo_unref(rmesa->tcl.aos[i].bo); - rmesa->tcl.aos[i].bo = NULL; - } - } -} diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index ea400a672d..ecfdce9d01 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1332,7 +1332,6 @@ radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); } -#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) /** * Choose the appropriate CreateContext function based on the chipset. * Eventually, all drivers will go through this process. @@ -1343,25 +1342,21 @@ static GLboolean radeonCreateContext(const __GLcontextModes * glVisual, { __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); - +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) if (IS_R300_CLASS(screen)) return r300CreateContext(glVisual, driContextPriv, sharedContextPriv); - return GL_FALSE; -} - -/** - * Choose the appropriate DestroyContext function based on the chipset. - */ -static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv) -{ - radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; - - if (IS_R300_CLASS(radeon->radeonScreen)) - return r300DestroyContext(driContextPriv); -} +#endif +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + if (IS_R200_CLASS(screen)) + return r200CreateContext(glVisual, driContextPriv, sharedContextPriv); +#endif +#if !RADEON_COMMON + return r100CreateContext(glVisual, driContextPriv, sharedContextPriv); #endif + return GL_FALSE; +} /** @@ -1547,7 +1542,6 @@ getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) return 0; } -#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) const struct __DriverAPIRec driDriverAPI = { .InitScreen = radeonInitScreen, .DestroyScreen = radeonDestroyScreen, @@ -1567,24 +1561,4 @@ const struct __DriverAPIRec driDriverAPI = { /* DRI2 */ .InitScreen2 = radeonInitScreen2, }; -#else -const struct __DriverAPIRec driDriverAPI = { - .InitScreen = radeonInitScreen, - .DestroyScreen = radeonDestroyScreen, - .CreateContext = r200CreateContext, - .DestroyContext = r200DestroyContext, - .CreateBuffer = radeonCreateBuffer, - .DestroyBuffer = radeonDestroyBuffer, - .SwapBuffers = radeonSwapBuffers, - .MakeCurrent = radeonMakeCurrent, - .UnbindContext = radeonUnbindContext, - .GetSwapInfo = getSwapInfo, - .GetDrawableMSC = driDrawableGetMSC32, - .WaitForMSC = driWaitForMSC32, - .WaitForSBC = NULL, - .SwapBuffersMSC = NULL, - .CopySubBuffer = radeonCopySubBuffer, - .InitScreen2 = radeonInitScreen2, -}; -#endif diff --git a/src/mesa/drivers/dri/radeon/radeon_state.h b/src/mesa/drivers/dri/radeon/radeon_state.h index 17c2b11222..f05fa827d7 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.h +++ b/src/mesa/drivers/dri/radeon/radeon_state.h @@ -52,9 +52,6 @@ extern void radeonUploadTexMatrix( r100ContextPtr rmesa, extern void radeonValidateState( GLcontext *ctx ); -extern void radeonPrintDirty( r100ContextPtr rmesa, - const char *msg ); - extern void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode ); #define FALLBACK( rmesa, bit, mode ) do { \ diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index 3d0cd8d3f8..174a7e1862 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -161,22 +161,6 @@ static struct { /* ============================================================= * State initialization */ - -void radeonPrintDirty( r100ContextPtr rmesa, const char *msg ) -{ - struct radeon_state_atom *l; - - fprintf(stderr, msg); - fprintf(stderr, ": "); - - foreach(l, &rmesa->radeon.hw.atomlist) { - if (l->dirty || rmesa->radeon.hw.all_dirty) - fprintf(stderr, "%s, ", l->name); - } - - fprintf(stderr, "\n"); -} - static int cmdpkt( r100ContextPtr rmesa, int id ) { drm_radeon_cmd_header_t h; diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c b/src/mesa/drivers/dri/radeon/radeon_swtcl.c index 2484006f1c..e31f045991 100644 --- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c @@ -822,7 +822,3 @@ void radeonInitSwtcl( GLcontext *ctx ) rmesa->radeon.swtcl.hw_primitive = 0; } - -void radeonDestroySwtcl( GLcontext *ctx ) -{ -} diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.h b/src/mesa/drivers/dri/radeon/radeon_swtcl.h index 3ada9890b3..da89158eeb 100644 --- a/src/mesa/drivers/dri/radeon/radeon_swtcl.h +++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.h @@ -40,7 +40,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_context.h" extern void radeonInitSwtcl( GLcontext *ctx ); -extern void radeonDestroySwtcl( GLcontext *ctx ); extern void radeonChooseRenderState( GLcontext *ctx ); extern void radeonChooseVertexState( GLcontext *ctx ); diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.c b/src/mesa/drivers/dri/radeon/radeon_tcl.c index 5887ab355d..df6708f05e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_tcl.c @@ -150,10 +150,10 @@ static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr ) rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->radeon.hw.max_state_size + ELTS_BUFSZ(nr) + - AOS_BUFSZ(rmesa->tcl.nr_aos_components), __FUNCTION__); + AOS_BUFSZ(rmesa->radeon.tcl.aos_count), __FUNCTION__); radeonEmitAOS( rmesa, - rmesa->tcl.nr_aos_components, 0 ); + rmesa->radeon.tcl.aos_count, 0 ); return radeonAllocEltsOpenEnded( rmesa, rmesa->tcl.vertex_format, rmesa->tcl.hw_primitive, nr ); @@ -177,11 +177,11 @@ static void radeonEmitPrim( GLcontext *ctx, radeonTclPrimitive( ctx, prim, hwprim ); rcommonEnsureCmdBufSpace( &rmesa->radeon, - AOS_BUFSZ(rmesa->tcl.nr_aos_components) + + AOS_BUFSZ(rmesa->radeon.tcl.aos_count) + rmesa->radeon.hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ ); radeonEmitAOS( rmesa, - rmesa->tcl.nr_aos_components, + rmesa->radeon.tcl.aos_count, start ); /* Why couldn't this packet have taken an offset param? -- cgit v1.2.3