From ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 20 Jan 2009 22:51:04 +1000 Subject: r200: clear is working at least - not much else --- src/mesa/drivers/dri/r200/r200_cmdbuf.c | 226 ++++++++++++++++++++------- src/mesa/drivers/dri/r200/r200_context.c | 112 ++----------- src/mesa/drivers/dri/r200/r200_context.h | 8 +- src/mesa/drivers/dri/r200/r200_ioctl.c | 20 +-- src/mesa/drivers/dri/r200/r200_ioctl.h | 59 +++++-- src/mesa/drivers/dri/r200/r200_maos_arrays.c | 34 ++-- src/mesa/drivers/dri/r200/r200_pixel.c | 8 +- src/mesa/drivers/dri/r200/r200_span.c | 46 +++--- src/mesa/drivers/dri/r200/r200_span.h | 3 +- src/mesa/drivers/dri/r200/r200_state.c | 33 ++-- src/mesa/drivers/dri/r200/r200_state_init.c | 146 +++++++++++++++++ src/mesa/drivers/dri/r200/r200_swtcl.c | 70 +++------ src/mesa/drivers/dri/r200/r200_tcl.c | 18 +-- src/mesa/drivers/dri/r200/r200_texmem.c | 4 +- 14 files changed, 489 insertions(+), 298 deletions(-) (limited to 'src/mesa/drivers/dri/r200') diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index 53c6ecf6ee..f107ff5624 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -38,7 +38,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast/swrast.h" #include "main/simple_list.h" +#include "radeon_cs.h" #include "r200_context.h" +#include "common_cmdbuf.h" #include "r200_state.h" #include "r200_ioctl.h" #include "r200_tcl.h" @@ -148,6 +150,40 @@ static void r200SaveHwState( r200ContextPtr rmesa ) fprintf(stderr, "Returning to r200EmitState\n"); } +static INLINE void r200EmitAtoms(r200ContextPtr r200, GLboolean dirty) +{ + BATCH_LOCALS(&r200->radeon); + struct radeon_state_atom *atom; + int dwords; + + /* Emit actual atoms */ + foreach(atom, &r200->hw.atomlist) { + if ((atom->dirty || r200->hw.all_dirty) == dirty) { + dwords = (*atom->check) (r200->radeon.glCtx, atom); + if (dwords) { + // if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { + // r300PrintStateAtom(r300, atom); + // } + if (atom->emit) { + (*atom->emit)(r200->radeon.glCtx, atom); + } else { + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_BATCH_TABLE(atom->cmd, dwords); + END_BATCH(); + } + atom->dirty = GL_FALSE; + } else { + // if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { + // fprintf(stderr, " skip state %s\n", + // atom->name); + // } + } + } + } + + COMMIT_BATCH(); +} + void r200EmitState( r200ContextPtr rmesa ) { char *dest; @@ -163,8 +199,8 @@ void r200EmitState( r200ContextPtr rmesa ) rmesa->save_on_next_emit = GL_FALSE; } - if (!rmesa->hw.is_dirty && !rmesa->hw.all_dirty) - return; + if (rmesa->radeon.cmdbuf.cs->cdw && !rmesa->hw.is_dirty && !rmesa->hw.all_dirty) + return; mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits; @@ -172,44 +208,19 @@ void r200EmitState( r200ContextPtr rmesa ) * for enough space for the case of emitting all state, and inline the * r200AllocCmdBuf code here without all the checks. */ - r200EnsureCmdBufSpace( rmesa, rmesa->hw.max_state_size ); - - /* we need to calculate dest after EnsureCmdBufSpace - as we may flush the buffer - airlied */ - dest = rmesa->store.cmd_buf + rmesa->store.cmd_used; - if (R200_DEBUG & DEBUG_STATE) { - foreach( atom, &rmesa->hw.atomlist ) { - if ( atom->dirty || rmesa->hw.all_dirty ) { - dwords = atom->check( rmesa->radeon.glCtx, atom ); - if ( dwords ) - print_state_atom( atom ); - else - fprintf(stderr, "skip state %s\n", atom->name); - } - } - } + rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->hw.max_state_size, __FUNCTION__); - foreach( atom, &rmesa->hw.atomlist ) { - if ( rmesa->hw.all_dirty ) - atom->dirty = GL_TRUE; - if ( atom->dirty ) { - dwords = atom->check( rmesa->radeon.glCtx, atom ); - if ( dwords ) { - int size = atom->cmd_size * 4; - if (atom->emit) { - (*atom->emit)(rmesa->radeon.glCtx, atom); - } else { - memcpy( dest, atom->cmd, size); - dest += size; - rmesa->store.cmd_used += size; - } - atom->dirty = GL_FALSE; - } - } + if (!rmesa->radeon.cmdbuf.cs->cdw) { + if (RADEON_DEBUG & DEBUG_STATE) + fprintf(stderr, "Begin reemit state\n"); + + r200EmitAtoms(rmesa, GL_FALSE); } - assert( rmesa->store.cmd_used <= R200_CMD_BUF_SZ ); + if (RADEON_DEBUG & DEBUG_STATE) + fprintf(stderr, "Begin dirty state\n"); + r200EmitAtoms(rmesa, GL_TRUE); rmesa->hw.is_dirty = GL_FALSE; rmesa->hw.all_dirty = GL_FALSE; } @@ -222,6 +233,7 @@ void r200EmitVbufPrim( r200ContextPtr rmesa, GLuint vertex_nr ) { drm_radeon_cmd_header_t *cmd; + BATCH_LOCALS(&rmesa->radeon); assert(!(primitive & R200_VF_PRIM_WALK_IND)); @@ -230,7 +242,13 @@ void r200EmitVbufPrim( r200ContextPtr rmesa, if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS)) fprintf(stderr, "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__, rmesa->store.cmd_used/4, primitive, vertex_nr); - + + BEGIN_BATCH(3); + OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_VBUF_2, 0); + OUT_BATCH(primitive | R200_VF_PRIM_WALK_LIST | R200_VF_COLOR_ORDER_RGBA | + (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT)); + END_BATCH(); +#if 0 cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, VBUF_BUFSZ, __FUNCTION__ ); cmd[0].i = 0; @@ -240,6 +258,7 @@ void r200EmitVbufPrim( r200ContextPtr rmesa, R200_VF_PRIM_WALK_LIST | R200_VF_COLOR_ORDER_RGBA | (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT)); +#endif } @@ -285,8 +304,8 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, r200EmitState( rmesa ); - cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, ELTS_BUFSZ(min_nr), - __FUNCTION__ ); + // cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, ELTS_BUFSZ(min_nr), + // __FUNCTION__ ); cmd[0].i = 0; cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP; cmd[1].i = R200_CP_CMD_3D_DRAW_INDX_2; @@ -314,26 +333,124 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, void r200EmitVertexAOS( r200ContextPtr rmesa, - GLuint vertex_size, - GLuint offset ) + GLuint vertex_size, + struct radeon_bo *bo, + GLuint offset ) { - drm_radeon_cmd_header_t *cmd; + BATCH_LOCALS(&rmesa->radeon); if (R200_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL)) fprintf(stderr, "%s: vertex_size 0x%x offset 0x%x \n", __FUNCTION__, vertex_size, offset); - cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, VERT_AOS_BUFSZ, - __FUNCTION__ ); - cmd[0].header.cmd_type = RADEON_CMD_PACKET3; - cmd[1].i = R200_CP_CMD_3D_LOAD_VBPNTR | (2 << 16); - cmd[2].i = 1; - cmd[3].i = vertex_size | (vertex_size << 8); - cmd[4].i = offset; + BEGIN_BATCH(5); + OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, 2); + OUT_BATCH(1); + OUT_BATCH(vertex_size | (vertex_size << 8)); + OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0); + END_BATCH(); } - +void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset) +{ + BATCH_LOCALS(&rmesa->radeon); + uint32_t voffset; + int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2; + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__, nr, + offset); + + BEGIN_BATCH(sz+2); + OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, sz - 1); + OUT_BATCH(nr); + + + if (!rmesa->radeon.radeonScreen->kernel_mm) { + for (i = 0; i + 1 < nr; i += 2) { + OUT_BATCH((rmesa->tcl.aos[i].components << 0) | + (rmesa->tcl.aos[i].stride << 8) | + (rmesa->tcl.aos[i + 1].components << 16) | + (rmesa->tcl.aos[i + 1].stride << 24)); + + voffset = rmesa->tcl.aos[i + 0].offset + + offset * 4 * rmesa->tcl.aos[i + 0].stride; + OUT_BATCH_RELOC(voffset, + rmesa->tcl.aos[i].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + voffset = rmesa->tcl.aos[i + 1].offset + + offset * 4 * rmesa->tcl.aos[i + 1].stride; + OUT_BATCH_RELOC(voffset, + rmesa->tcl.aos[i+1].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + + if (nr & 1) { + OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) | + (rmesa->tcl.aos[nr - 1].stride << 8)); + voffset = rmesa->tcl.aos[nr - 1].offset + + offset * 4 * rmesa->tcl.aos[nr - 1].stride; + OUT_BATCH_RELOC(voffset, + rmesa->tcl.aos[nr - 1].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + } else { + for (i = 0; i + 1 < nr; i += 2) { + OUT_BATCH((rmesa->tcl.aos[i].components << 0) | + (rmesa->tcl.aos[i].stride << 8) | + (rmesa->tcl.aos[i + 1].components << 16) | + (rmesa->tcl.aos[i + 1].stride << 24)); + + voffset = rmesa->tcl.aos[i + 0].offset + + offset * 4 * rmesa->tcl.aos[i + 0].stride; + OUT_BATCH(voffset); + voffset = rmesa->tcl.aos[i + 1].offset + + offset * 4 * rmesa->tcl.aos[i + 1].stride; + OUT_BATCH(voffset); + } + + if (nr & 1) { + OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) | + (rmesa->tcl.aos[nr - 1].stride << 8)); + voffset = rmesa->tcl.aos[nr - 1].offset + + offset * 4 * rmesa->tcl.aos[nr - 1].stride; + OUT_BATCH(voffset); + } + for (i = 0; i + 1 < nr; i += 2) { + voffset = rmesa->tcl.aos[i + 0].offset + + offset * 4 * rmesa->tcl.aos[i + 0].stride; + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->tcl.aos[i+0].bo, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + voffset = rmesa->tcl.aos[i + 1].offset + + offset * 4 * rmesa->tcl.aos[i + 1].stride; + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->tcl.aos[i+1].bo, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + if (nr & 1) { + voffset = rmesa->tcl.aos[nr - 1].offset + + offset * 4 * rmesa->tcl.aos[nr - 1].stride; + radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, + rmesa->tcl.aos[nr-1].bo, + RADEON_GEM_DOMAIN_GTT, + 0, 0); + } + } + END_BATCH(); +} + +#if 0 void r200EmitAOS( r200ContextPtr rmesa, struct radeon_dma_region **component, GLuint nr, @@ -377,6 +494,7 @@ void r200EmitAOS( r200ContextPtr rmesa, fprintf(stderr, " %d: %x\n", i, tmp[i]); } } +#endif void r200EmitBlit( r200ContextPtr rmesa, GLuint color_fmt, @@ -404,8 +522,8 @@ void r200EmitBlit( r200ContextPtr rmesa, assert( w < (1<<16) ); assert( h < (1<<16) ); - cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 8 * sizeof(int), - __FUNCTION__ ); + // cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 8 * sizeof(int), + // __FUNCTION__ ); cmd[0].header.cmd_type = RADEON_CMD_PACKET3; @@ -434,8 +552,8 @@ void r200EmitWait( r200ContextPtr rmesa, GLuint flags ) assert( !(flags & ~(RADEON_WAIT_2D|RADEON_WAIT_3D)) ); - cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 1 * sizeof(int), - __FUNCTION__ ); + // cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 1 * sizeof(int), + // __FUNCTION__ ); cmd[0].i = 0; cmd[0].wait.cmd_type = RADEON_CMD_WAIT; cmd[0].wait.flags = flags; diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 730831db04..acbfdb2db6 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -297,9 +297,9 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private); struct dd_function_table functions; r200ContextPtr rmesa; - GLcontext *ctx, *shareCtx; + GLcontext *ctx; int i; - int tcl_mode, fthrottle_mode; + int tcl_mode; assert(glVisual); assert(driContextPriv); @@ -344,31 +344,12 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, r200InitTextureFuncs(&functions); r200InitShaderFuncs(&functions); - /* Allocate and initialize the Mesa context */ - if (sharedContextPrivate) - shareCtx = ((r200ContextPtr) sharedContextPrivate)->radeon.glCtx; - else - shareCtx = NULL; - rmesa->radeon.glCtx = _mesa_create_context(glVisual, shareCtx, - &functions, (void *) rmesa); - if (!rmesa->radeon.glCtx) { - FREE(rmesa); - return GL_FALSE; + if (!radeonInitContext(&rmesa->radeon, &functions, + glVisual, driContextPriv, + sharedContextPrivate)) { + FREE(rmesa); + return GL_FALSE; } - driContextPriv->driverPrivate = rmesa; - - /* Init r200 context data */ - rmesa->radeon.dri.context = driContextPriv; - rmesa->radeon.dri.screen = sPriv; - rmesa->radeon.dri.drawable = NULL; /* Set by XMesaMakeCurrent */ - rmesa->radeon.dri.hwContext = driContextPriv->hHWContext; - rmesa->radeon.dri.hwLock = &sPriv->pSAREA->lock; - rmesa->radeon.dri.fd = sPriv->fd; - rmesa->radeon.dri.drmMinor = sPriv->drm_version.minor; - - rmesa->radeon.radeonScreen = screen; - rmesa->radeon.sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA + - screen->sarea_priv_offset); rmesa->dma.buf0_address = rmesa->radeon.radeonScreen->buffers->list[0].address; @@ -531,27 +512,9 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, r200InitState( rmesa ); r200InitSwtcl( ctx ); - fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode"); - rmesa->radeon.iw.irq_seq = -1; - rmesa->radeon.irqsEmitted = 0; - rmesa->radeon.do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS && - rmesa->radeon.radeonScreen->irq); - - rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); - - if (!rmesa->radeon.do_irqs) - fprintf(stderr, - "IRQ's not enabled, falling back to %s: %d %d\n", - rmesa->radeon.do_usleeps ? "usleeps" : "busy waits", - fthrottle_mode, - rmesa->radeon.radeonScreen->irq); - rmesa->prefer_gart_client_texturing = (getenv("R200_GART_CLIENT_TEXTURES") != 0); - (*sPriv->systemTime->getUST)( & rmesa->radeon.swap_ust ); - - #if DO_DEBUG R200_DEBUG = driParseDebugString( getenv( "R200_DEBUG" ), debug_control ); @@ -609,8 +572,8 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) r200ReleaseArrays( rmesa->radeon.glCtx, ~0 ); if (rmesa->dma.current.buf) { - r200ReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ ); - r200FlushCmdBuf( rmesa, __FUNCTION__ ); + // r200ReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ ); + rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); } if (rmesa->radeon.state.scissor.pClipRects) { @@ -618,6 +581,7 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) rmesa->radeon.state.scissor.pClipRects = NULL; } + if ( release_texture_heaps ) { /* This share group is about to go away, free our private * texture object data. @@ -632,67 +596,13 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) assert( is_empty_list( & rmesa->radeon.swapped ) ); } - /* free the Mesa context */ - rmesa->radeon.glCtx->DriverCtx = NULL; - _mesa_destroy_context( rmesa->radeon.glCtx ); - - /* free the option cache */ - driDestroyOptionCache (&rmesa->radeon.optionCache); + radeonCleanupContext(&rmesa->radeon); FREE( rmesa ); } } -/* Force the context `c' to be the current context and associate with it - * buffer `b'. - */ -GLboolean -r200MakeCurrent( __DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv ) -{ - if ( driContextPriv ) { - r200ContextPtr newCtx = - (r200ContextPtr) driContextPriv->driverPrivate; - - if (R200_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *)newCtx->radeon.glCtx); - - newCtx->radeon.dri.readable = driReadPriv; - - if ( newCtx->radeon.dri.drawable != driDrawPriv || - newCtx->radeon.lastStamp != driDrawPriv->lastStamp ) { - if (driDrawPriv->swap_interval == (unsigned)-1) { - driDrawPriv->vblFlags = (newCtx->radeon.radeonScreen->irq != 0) - ? driGetDefaultVBlankFlags(&newCtx->radeon.optionCache) - : VBLANK_FLAG_NO_IRQ; - - driDrawableInitVBlank( driDrawPriv ); - } - - newCtx->radeon.dri.drawable = driDrawPriv; - - radeonSetCliprects(&newCtx->radeon); - r200UpdateViewportOffset( newCtx->radeon.glCtx ); - } - - _mesa_make_current( newCtx->radeon.glCtx, - (GLframebuffer *) driDrawPriv->driverPrivate, - (GLframebuffer *) driReadPriv->driverPrivate ); - - _mesa_update_state( newCtx->radeon.glCtx ); - r200ValidateState( newCtx->radeon.glCtx ); - - } else { - if (R200_DEBUG & DEBUG_DRI) - fprintf(stderr, "%s ctx is null\n", __FUNCTION__); - _mesa_make_current( NULL, NULL, NULL ); - } - if (R200_DEBUG & DEBUG_DRI) - fprintf(stderr, "End %s\n", __FUNCTION__); - return GL_TRUE; -} /* Force the context `c' to be unbound from its buffer. */ diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index c1a68aa694..5ecf797999 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -538,7 +538,8 @@ struct r200_tcl_info { GLuint hw_primitive; /* hw can handle 12 components max */ - struct radeon_dma_region *aos_components[12]; + struct radeon_aos aos[12]; + // struct radeon_dma_region *aos_components[12]; GLuint nr_aos_components; GLuint *Elts; @@ -600,6 +601,8 @@ struct r200_swtcl_info { */ GLboolean needproj; + struct radeon_bo *bo; + void (*flush) (r200ContextPtr); struct radeon_dma_region indexed_verts; }; @@ -619,7 +622,6 @@ struct r200_swtcl_info { #define R200_MAX_VERTEX_SIZE ((3*6)+11) - struct r200_context { struct radeon_context radeon; @@ -641,7 +643,7 @@ struct r200_context { /* Clientdata textures; */ - GLuint prefer_gart_client_texturing; + GLuint prefer_gart_client_texturing; GLboolean save_on_next_emit; diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index fe3a471c8a..1bb97c5002 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -42,6 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast/swrast.h" #include "r200_context.h" +#include "common_cmdbuf.h" #include "r200_state.h" #include "r200_ioctl.h" #include "r200_tcl.h" @@ -77,11 +78,12 @@ static void r200BackUpAndEmitLostStateLocked( r200ContextPtr rmesa ) saved_store = rmesa->store; rmesa->dma.nr_released_bufs = 0; rmesa->store = rmesa->backup_store; - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); rmesa->dma.nr_released_bufs = nr_released_bufs; rmesa->store = saved_store; } +#if 0 int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ) { int ret, i; @@ -163,7 +165,6 @@ int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ) return ret; } - /* Note: does not emit any commands to avoid recursion on * r200AllocCmdBuf. */ @@ -173,7 +174,7 @@ void r200FlushCmdBuf( r200ContextPtr rmesa, const char *caller ) LOCK_HARDWARE( &rmesa->radeon ); - ret = r200FlushCmdBufLocked( rmesa, caller ); + ret = rcommonFlushCmdBufLocked( rmesa, caller ); UNLOCK_HARDWARE( &rmesa->radeon ); @@ -182,13 +183,14 @@ void r200FlushCmdBuf( r200ContextPtr rmesa, const char *caller ) exit(ret); } } +#endif /* ============================================================= * Hardware vertex buffer handling */ - +#if 0 void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) { struct radeon_dma_buffer *dmabuf; @@ -209,7 +211,7 @@ void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) r200ReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ ); if (rmesa->dma.nr_released_bufs > 4) - r200FlushCmdBuf( rmesa, __FUNCTION__ ); + rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); dma.context = rmesa->radeon.dri.hwContext; dma.send_count = 0; @@ -230,7 +232,7 @@ void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ) break; if (rmesa->dma.nr_released_bufs) { - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); } if (rmesa->radeon.do_usleeps) { @@ -325,7 +327,7 @@ void r200AllocDmaRegion( r200ContextPtr rmesa, assert( rmesa->dma.current.ptr <= rmesa->dma.current.end ); } - +#endif /* ================================================================ * Buffer clear @@ -437,7 +439,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask ) } /* Send current state to the hardware */ - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); for ( i = 0 ; i < dPriv->numClipRects ; ) { GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, dPriv->numClipRects ); @@ -525,7 +527,7 @@ void r200Flush( GLcontext *ctx ) r200EmitState( rmesa ); if (rmesa->store.cmd_used) - r200FlushCmdBuf( rmesa, __FUNCTION__ ); + rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ ); } /* Make sure all commands have been sent to the hardware and have diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h index 1f92705685..f36a6fd90f 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ b/src/mesa/drivers/dri/r200/r200_ioctl.h @@ -45,8 +45,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. extern void r200EmitState( r200ContextPtr rmesa ); extern void r200EmitVertexAOS( r200ContextPtr rmesa, - GLuint vertex_size, - GLuint offset ); + GLuint vertex_size, + struct radeon_bo *bo, + GLuint offset ); extern void r200EmitVbufPrim( r200ContextPtr rmesa, GLuint primitive, @@ -58,10 +59,7 @@ extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, GLuint primitive, GLuint min_nr ); -extern void r200EmitAOS( r200ContextPtr rmesa, - struct radeon_dma_region **regions, - GLuint n, - GLuint offset ); +extern void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset); extern void r200EmitBlit( r200ContextPtr rmesa, GLuint color_fmt, @@ -75,8 +73,8 @@ extern void r200EmitBlit( r200ContextPtr rmesa, extern void r200EmitWait( r200ContextPtr rmesa, GLuint flags ); -extern void r200FlushCmdBuf( r200ContextPtr rmesa, const char * ); -extern int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ); +//extern void r200FlushCmdBuf( r200ContextPtr rmesa, const char * ); +//extern int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller ); extern void r200RefillCurrentDmaRegion( r200ContextPtr rmesa ); @@ -178,10 +176,11 @@ do { \ * and hang on to the lock until the critical section is finished and we flush * the buffer again and unlock. */ +#if 0 static INLINE void r200EnsureCmdBufSpace( r200ContextPtr rmesa, int bytes ) { if (rmesa->store.cmd_used + bytes > R200_CMD_BUF_SZ) - r200FlushCmdBuf( rmesa, __FUNCTION__ ); + rcommonFlushCmdBuf( rmesa, __FUNCTION__ ); assert( bytes <= R200_CMD_BUF_SZ ); } @@ -200,5 +199,47 @@ static INLINE char *r200AllocCmdBuf( r200ContextPtr rmesa, assert( rmesa->store.cmd_used <= R200_CMD_BUF_SZ ); return head; } +#endif + +static inline uint32_t cmdpacket3_clip(int cmd_type) +{ + drm_radeon_cmd_header_t cmd; + + cmd.i = 0; + cmd.header.cmd_type = RADEON_CMD_PACKET3_CLIP; + + return (uint32_t)cmd.i; + +} +#define OUT_BATCH_PACKET3_CLIP(packet, num_extra) do { \ + if (!b_l_rmesa->radeonScreen->kernel_mm) { \ + OUT_BATCH(cmdpacket3_clip(0)); \ + OUT_BATCH(packet); \ + } else { \ + OUT_BATCH(CP_PACKET2); \ + OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ + } \ + } while(0) + +static inline uint32_t cmdpacket3(int cmd_type) +{ + drm_radeon_cmd_header_t cmd; + + cmd.i = 0; + cmd.header.cmd_type = RADEON_CMD_PACKET3; + + return (uint32_t)cmd.i; + +} +#define OUT_BATCH_PACKET3(packet, num_extra) do { \ + if (!b_l_rmesa->radeonScreen->kernel_mm) { \ + OUT_BATCH(cmdpacket3(0)); \ + OUT_BATCH(packet); \ + } else { \ + OUT_BATCH(CP_PACKET2); \ + OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ + } \ + } while(0) + #endif /* __R200_IOCTL_H__ */ diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c index 838dfe79f9..7fe1590c8d 100644 --- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c +++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c @@ -123,14 +123,14 @@ static void emit_ubyte_rgba( GLcontext *ctx, assert (!rvb->buf); if (stride == 0) { - r200AllocDmaRegion( rmesa, rvb, 4, 4 ); + // r200AllocDmaRegion( rmesa, rvb, 4, 4 ); count = 1; rvb->aos_start = GET_START(rvb); rvb->aos_stride = 0; rvb->aos_size = 1; } else { - r200AllocDmaRegion( rmesa, rvb, 4 * count, 4 ); /* alignment? */ + // r200AllocDmaRegion( rmesa, rvb, 4 * count, 4 ); /* alignment? */ rvb->aos_start = GET_START(rvb); rvb->aos_stride = 1; rvb->aos_size = 1; @@ -193,14 +193,14 @@ static void emit_vecfog( GLcontext *ctx, assert (!rvb->buf); if (stride == 0) { - r200AllocDmaRegion( rmesa, rvb, 4, 4 ); + // r200AllocDmaRegion( rmesa, rvb, 4, 4 ); count = 1; rvb->aos_start = GET_START(rvb); rvb->aos_stride = 0; rvb->aos_size = 1; } else { - r200AllocDmaRegion( rmesa, rvb, count * 4, 4 ); /* alignment? */ + // r200AllocDmaRegion( rmesa, rvb, count * 4, 4 ); /* alignment? */ rvb->aos_start = GET_START(rvb); rvb->aos_stride = 1; rvb->aos_size = 1; @@ -334,14 +334,14 @@ static void emit_vector( GLcontext *ctx, assert (!rvb->buf); if (stride == 0) { - r200AllocDmaRegion( rmesa, rvb, size * 4, 4 ); + // r200AllocDmaRegion( rmesa, rvb, size * 4, 4 ); count = 1; rvb->aos_start = GET_START(rvb); rvb->aos_stride = 0; rvb->aos_size = size; } else { - r200AllocDmaRegion( rmesa, rvb, size * count * 4, 4 ); /* alignment? */ + // r200AllocDmaRegion( rmesa, rvb, size * count * 4, 4 ); /* alignment? */ rvb->aos_start = GET_START(rvb); rvb->aos_stride = size; rvb->aos_size = size; @@ -379,7 +379,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) { r200ContextPtr rmesa = R200_CONTEXT( ctx ); struct vertex_buffer *VB = &TNL_CONTEXT( ctx )->vb; - struct radeon_dma_region **component = rmesa->tcl.aos_components; + // struct radeon_dma_region **component = rmesa->tcl.aos_components; GLuint nr = 0; GLuint vfmt0 = 0, vfmt1 = 0; GLuint count = VB->Count; @@ -418,12 +418,12 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) assert(attrib == VERT_ATTRIB_FOG); if (!rmesa->tcl.vertex_data[i].buf) { if (ctx->VertexProgram._Enabled) - emit_vector( ctx, - &(rmesa->tcl.vertex_data[i]), - (char *)VB->AttribPtr[attrib]->data, - 1, - VB->AttribPtr[attrib]->stride, - count); + rcommon_emit_vector( ctx, + &(rmesa->tcl.vertex_data[i]), + (char *)VB->AttribPtr[attrib]->data, + 1, + VB->AttribPtr[attrib]->stride, + count); else emit_vecfog( ctx, &(rmesa->tcl.vertex_data[i]), @@ -483,7 +483,7 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev ) } after_emit: assert(nr < 12); - component[nr++] = &rmesa->tcl.vertex_data[i]; + // component[nr++] = &rmesa->tcl.vertex_data[i]; } } @@ -505,8 +505,8 @@ void r200ReleaseArrays( GLcontext *ctx, GLuint newinputs ) /* only do it for changed inputs ? */ int i; for (i = 0; i < 15; i++) { - if (newinputs & (1 << i)) - r200ReleaseDmaRegion( rmesa, - &rmesa->tcl.vertex_data[i], __FUNCTION__ ); + // if (newinputs & (1 << i)) + // r200ReleaseDmaRegion( rmesa, + // &rmesa->tcl.vertex_data[i], __FUNCTION__ ); } } diff --git a/src/mesa/drivers/dri/r200/r200_pixel.c b/src/mesa/drivers/dri/r200/r200_pixel.c index a8aa1a2773..930d797f45 100644 --- a/src/mesa/drivers/dri/r200/r200_pixel.c +++ b/src/mesa/drivers/dri/r200/r200_pixel.c @@ -200,7 +200,7 @@ r200TryReadPixels( GLcontext *ctx, LOCK_HARDWARE( &rmesa->radeon ); if (rmesa->store.cmd_used) - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); if (!clip_pixelrect(ctx, ctx->ReadBuffer, &x, &y, &width, &height, &size)) { @@ -257,7 +257,7 @@ r200TryReadPixels( GLcontext *ctx, bw, bh ); } - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); } UNLOCK_HARDWARE( &rmesa->radeon ); @@ -321,7 +321,7 @@ static void do_draw_pix( GLcontext *ctx, LOCK_HARDWARE( &rmesa->radeon ); if (rmesa->store.cmd_used) - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); y -= height; /* cope with pixel zoom */ @@ -363,7 +363,7 @@ static void do_draw_pix( GLcontext *ctx, bw, bh ); } - r200FlushCmdBufLocked( rmesa, __FUNCTION__ ); + rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ ); radeonWaitForIdleLocked( &rmesa->radeon ); /* required by GL */ UNLOCK_HARDWARE( &rmesa->radeon ); } diff --git a/src/mesa/drivers/dri/r200/r200_span.c b/src/mesa/drivers/dri/r200/r200_span.c index b4da9ef6a3..df0172f64e 100644 --- a/src/mesa/drivers/dri/r200/r200_span.c +++ b/src/mesa/drivers/dri/r200/r200_span.c @@ -38,6 +38,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast/swrast.h" #include "r200_context.h" +#include "radeon_buffer.h" #include "r200_ioctl.h" #include "r200_state.h" #include "r200_span.h" @@ -86,8 +87,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define SPANTMP_PIXEL_FMT GL_RGB #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5 -#define TAG(x) r200##x##_RGB565 -#define TAG2(x,y) r200##x##_RGB565##y +#define TAG(x) radeon##x##_RGB565 +#define TAG2(x,y) radeon##x##_RGB565##y #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 2) #include "spantmp2.h" @@ -96,8 +97,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define SPANTMP_PIXEL_FMT GL_BGRA #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV -#define TAG(x) r200##x##_ARGB8888 -#define TAG2(x,y) r200##x##_ARGB8888##y +#define TAG(x) radeon##x##_ARGB8888 +#define TAG2(x,y) radeon##x##_ARGB8888##y #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 4) #include "spantmp2.h" @@ -180,7 +181,7 @@ r200_mba_z16( driRenderbuffer *drb, GLint x, GLint y ) #define READ_DEPTH( d, _x, _y ) \ d = *(GLushort *)(buf + r200_mba_z16( drb, _x + xo, _y + yo )); -#define TAG(x) r200##x##_z16 +#define TAG(x) radeon##x##_z16 #include "depthtmp.h" @@ -201,7 +202,7 @@ do { \ d = *(GLuint *)(buf + r200_mba_z32( drb, _x + xo, \ _y + yo )) & 0x00ffffff; -#define TAG(x) r200##x##_z24_s8 +#define TAG(x) radeon##x##_z24_s8 #include "depthtmp.h" @@ -228,7 +229,7 @@ do { \ d = tmp >> 24; \ } while (0) -#define TAG(x) r200##x##_z24_s8 +#define TAG(x) radeon##x##_z24_s8 #include "stenciltmp.h" @@ -284,24 +285,17 @@ void r200InitSpanFuncs( GLcontext *ctx ) /** * Plug in the Get/Put routines for the given driRenderbuffer. */ -void -radeonSetSpanFunctions(driRenderbuffer *drb, const GLvisual *vis) +void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb) { - if (drb->Base.InternalFormat == GL_RGBA) { - if (vis->redBits == 5 && vis->greenBits == 6 && vis->blueBits == 5) { - r200InitPointers_RGB565(&drb->Base); - } - else { - r200InitPointers_ARGB8888(&drb->Base); - } - } - else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) { - r200InitDepthPointers_z16(&drb->Base); - } - else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) { - r200InitDepthPointers_z24_s8(&drb->Base); - } - else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) { - r200InitStencilPointers_z24_s8(&drb->Base); - } + if (rrb->base.InternalFormat == GL_RGB5) { + radeonInitPointers_RGB565(&rrb->base); + } else if (rrb->base.InternalFormat == GL_RGBA8) { + radeonInitPointers_ARGB8888(&rrb->base); + } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT16) { + radeonInitDepthPointers_z16(&rrb->base); + } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT24) { + radeonInitDepthPointers_z24_s8(&rrb->base); + } else if (rrb->base.InternalFormat == GL_STENCIL_INDEX8_EXT) { + radeonInitStencilPointers_z24_s8(&rrb->base); + } } diff --git a/src/mesa/drivers/dri/r200/r200_span.h b/src/mesa/drivers/dri/r200/r200_span.h index bae5644309..b2f3d5e43c 100644 --- a/src/mesa/drivers/dri/r200/r200_span.h +++ b/src/mesa/drivers/dri/r200/r200_span.h @@ -39,7 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. extern void r200InitSpanFuncs( GLcontext *ctx ); -extern void -radeonSetSpanFunctions(driRenderbuffer *rb, const GLvisual *vis); +extern void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb); #endif diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index 997c1711f9..f2e62d1bf7 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -47,6 +47,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/t_pipeline.h" #include "swrast_setup/swrast_setup.h" +#include "radeon_buffer.h" #include "r200_context.h" #include "r200_ioctl.h" #include "r200_state.h" @@ -1624,8 +1625,8 @@ void r200UpdateWindow( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; - GLfloat xoffset = (GLfloat)dPriv->x; - GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h; + GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; + GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; const GLfloat *v = ctx->Viewport._WindowMap.m; float_ui32_type sx = { v[MAT_SX] }; @@ -2316,34 +2317,34 @@ r200UpdateDrawBuffer(GLcontext *ctx) { r200ContextPtr rmesa = R200_CONTEXT(ctx); struct gl_framebuffer *fb = ctx->DrawBuffer; - driRenderbuffer *drb; + struct radeon_renderbuffer *rrb; if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { - /* draw to front */ - drb = (driRenderbuffer *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; - } - else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { - /* draw to back */ - drb = (driRenderbuffer *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; - } - else { - /* drawing to multiple buffers, or none */ - return; + /* draw to front */ + rrb = (void *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; + } else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) { + /* draw to back */ + rrb = (void *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + } else { + /* drawing to multiple buffers, or none */ + return; } - assert(drb); - assert(drb->flippedPitch); + assert(rrb); + assert(rrb->pitch); R200_STATECHANGE( rmesa, ctx ); +#if 0 /* Note: we used the (possibly) page-flipped values */ rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] - = ((drb->flippedOffset + rmesa->radeon.radeonScreen->fbLocation) + = ((rrb->flippedOffset + rmesa->radeon.radeonScreen->fbLocation) & R200_COLOROFFSET_MASK); rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = drb->flippedPitch; if (rmesa->radeon.sarea->tiling_enabled) { rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE; } +#endif } diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index f68f5ae08f..f46b01b56a 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -52,6 +52,115 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "xmlpool.h" +/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in + * 1.3 cmdbuffers allow all previous state to be updated as well as + * the tcl scalar and vector areas. + */ +static struct { + int start; + int len; + const char *name; +} packet[RADEON_MAX_STATE_PACKETS] = { + {RADEON_PP_MISC, 7, "RADEON_PP_MISC"}, + {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"}, + {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"}, + {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"}, + {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"}, + {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"}, + {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"}, + {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"}, + {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"}, + {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"}, + {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"}, + {RADEON_RE_MISC, 1, "RADEON_RE_MISC"}, + {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"}, + {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"}, + {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"}, + {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"}, + {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"}, + {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"}, + {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"}, + {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"}, + {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17, + "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"}, + {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"}, + {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"}, + {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"}, + {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"}, + {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"}, + {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"}, + {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"}, + {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"}, + {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"}, + {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"}, + {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"}, + {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"}, + {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"}, + {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"}, + {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"}, + {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"}, + {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"}, + {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"}, + {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"}, + {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"}, + {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"}, + {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"}, + {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"}, + {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"}, + {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"}, + {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"}, + {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"}, + {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"}, + {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, + "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"}, + {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"}, + {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"}, + {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"}, + {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"}, + {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"}, + {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"}, + {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"}, + {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"}, + {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"}, + {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"}, + {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, + "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"}, + {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */ + {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */ + {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"}, + {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"}, + {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"}, + {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"}, + {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"}, + {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"}, + {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"}, + {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"}, + {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"}, + {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"}, + {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"}, + {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"}, + {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"}, + {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"}, + {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"}, + {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, + {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, + {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, + {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, + {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, + {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, + {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, + {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */ + {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"}, + {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, + {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, + {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, + {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, + {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, + {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, + {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, + {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"}, +}; + /* ============================================================= * State initialization */ @@ -179,6 +288,39 @@ VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96 ) +#if 0 +static int ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r200ContextPtr r200 = R200_CONTEXT(ctx); + BATCH_LOCALS(&r200->radeon); + struct radeon_renderbuffer *rrb; + uint32_t cbpitch; + GLframebuffer *fb = r200->radeon.dri.drawable->driverPrivate; + + rrb = r200->radeon.state.color.rrb; + if (r200->radeon.radeonScreen->driScreen->dri2.enabled) { + rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + } + if (!rrb || !rrb->bo) { + fprintf(stderr, "no rrb\n"); + return; + } + + cbpitch = (rrb->pitch / rrb->cpp); + if (rrb->cpp == 4) + ; + else + ; + +} +#endif + +static int tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + +} + + /* Initialize the context's hardware state. */ void r200InitState( r200ContextPtr rmesa ) @@ -267,6 +409,8 @@ void r200InitState( r200ContextPtr rmesa ) ALLOC_STATE( ctx, always, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 ); else ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 ); + + // rmesa->hw.ctx.emit = ctx_emit; ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 ); ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); @@ -964,4 +1108,6 @@ void r200InitState( r200ContextPtr rmesa ) r200LightingSpaceChange( ctx ); rmesa->hw.all_dirty = GL_TRUE; + + rcommonInitCmdBuf(&rmesa->radeon, rmesa->hw.max_state_size); } diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index 1130c3544d..0be772d015 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -48,6 +48,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/t_context.h" #include "tnl/t_pipeline.h" +#include "radeon_bo.h" #include "r200_context.h" #include "r200_ioctl.h" #include "r200_state.h" @@ -284,33 +285,24 @@ static void flush_last_swtcl_prim(GLcontext *ctx) rmesa->dma.flush = NULL; - if (rmesa->dma.current.buf) { - struct radeon_dma_region *current = &rmesa->dma.current; - GLuint current_offset = (rmesa->radeon.radeonScreen->gart_buffer_offset + - current->buf->buf->idx * RADEON_BUFFER_SIZE + - current->start); + radeon_bo_unmap(rmesa->swtcl.bo); + rcommonEnsureCmdBufSpace(rmesa, + rmesa->hw.max_state_size + (12*sizeof(int)), + __FUNCTION__); - assert (!(rmesa->swtcl.hw_primitive & R200_VF_PRIM_WALK_IND)); - assert (current->start + - rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == - current->ptr); + r200EmitState(rmesa); + r200EmitVertexAOS( rmesa, + rmesa->swtcl.vertex_size, + rmesa->swtcl.bo, 0); - if (rmesa->dma.current.start != rmesa->dma.current.ptr) { - r200EnsureCmdBufSpace( rmesa, VERT_AOS_BUFSZ + - rmesa->hw.max_state_size + VBUF_BUFSZ ); - r200EmitVertexAOS( rmesa, - rmesa->swtcl.vertex_size, - current_offset); + + r200EmitVbufPrim( rmesa, + rmesa->swtcl.hw_primitive, + rmesa->swtcl.numverts); - r200EmitVbufPrim( rmesa, - rmesa->swtcl.hw_primitive, - rmesa->swtcl.numverts); - } - - rmesa->swtcl.numverts = 0; - current->start = current->ptr; - } + // COMMIT_BATCH(); + rmesa->swtcl.numverts = 0; } @@ -321,28 +313,16 @@ r200AllocDmaLowVerts( r200ContextPtr rmesa, int nverts, int vsize ) { GLuint bytes = vsize * nverts; - if ( rmesa->dma.current.ptr + bytes > rmesa->dma.current.end ) - r200RefillCurrentDmaRegion( rmesa ); - - if (!rmesa->dma.flush) { - rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->dma.flush = flush_last_swtcl_prim; - } - - ASSERT( vsize == rmesa->swtcl.vertex_size * 4 ); - ASSERT( rmesa->dma.flush == flush_last_swtcl_prim ); - ASSERT( rmesa->dma.current.start + - rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == - rmesa->dma.current.ptr ); - - - { - GLubyte *head = (GLubyte *) (rmesa->dma.current.address + rmesa->dma.current.ptr); - rmesa->dma.current.ptr += bytes; - rmesa->swtcl.numverts += nverts; - return head; + rmesa->swtcl.bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, + 0, bytes, 4, RADEON_GEM_DOMAIN_GTT, 0); + radeon_bo_map(rmesa->swtcl.bo, 1); + if (rmesa->swtcl.flush == NULL) { + rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; + rmesa->swtcl.flush = flush_last_swtcl_prim; } + return rmesa->swtcl.bo->ptr; + } @@ -974,6 +954,6 @@ void r200DestroySwtcl( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - if (rmesa->swtcl.indexed_verts.buf) - r200ReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, __FUNCTION__ ); + // if (rmesa->swtcl.indexed_verts.buf) + // r200ReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, __FUNCTION__ ); } diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index d14564c29b..4a31578c89 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -156,11 +156,10 @@ static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) if (rmesa->dma.flush) rmesa->dma.flush( rmesa->radeon.glCtx ); - r200EnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + + rcommonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + rmesa->hw.max_state_size + ELTS_BUFSZ(nr) ); r200EmitAOS( rmesa, - rmesa->tcl.aos_components, rmesa->tcl.nr_aos_components, 0 ); return r200AllocEltsOpenEnded( rmesa, rmesa->tcl.hw_primitive, nr ); @@ -188,13 +187,12 @@ static void r200EmitPrim( GLcontext *ctx, r200ContextPtr rmesa = R200_CONTEXT( ctx ); r200TclPrimitive( ctx, prim, hwprim ); - r200EnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + - rmesa->hw.max_state_size + VBUF_BUFSZ ); + rcommonEnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) + + rmesa->hw.max_state_size + VBUF_BUFSZ ); r200EmitAOS( rmesa, - rmesa->tcl.aos_components, - rmesa->tcl.nr_aos_components, - start ); + rmesa->tcl.nr_aos_components, + start ); /* Why couldn't this packet have taken an offset param? */ @@ -570,9 +568,9 @@ static void transition_to_hwtnl( GLcontext *ctx ) rmesa->dma.flush = NULL; - if (rmesa->swtcl.indexed_verts.buf) - r200ReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, - __FUNCTION__ ); + // if (rmesa->swtcl.indexed_verts.buf) + // r200ReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, + // __FUNCTION__ ); R200_STATECHANGE( rmesa, vap ); rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] |= R200_VAP_TCL_ENABLE; diff --git a/src/mesa/drivers/dri/r200/r200_texmem.c b/src/mesa/drivers/dri/r200/r200_texmem.c index e8b6876dd3..5a0922de21 100644 --- a/src/mesa/drivers/dri/r200/r200_texmem.c +++ b/src/mesa/drivers/dri/r200/r200_texmem.c @@ -226,7 +226,7 @@ static void r200UploadRectSubImage( r200ContextPtr rmesa, tex = (char *)texImage->Data + done * src_pitch; memset(®ion, 0, sizeof(region)); - r200AllocDmaRegion( rmesa, ®ion, lines * dstPitch, 1024 ); + // r200AllocDmaRegion( rmesa, ®ion, lines * dstPitch, 1024 ); /* Copy texdata to dma: */ @@ -262,7 +262,7 @@ static void r200UploadRectSubImage( r200ContextPtr rmesa, r200EmitWait( rmesa, RADEON_WAIT_2D ); - r200ReleaseDmaRegion( rmesa, ®ion, __FUNCTION__ ); + // r200ReleaseDmaRegion( rmesa, ®ion, __FUNCTION__ ); done += lines; } } -- cgit v1.2.3