From 5a143e91dcaf64d77694b85671c214f93e3e8512 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 17 Mar 2008 21:09:49 +1000
Subject: some basic r500 portage

---
 src/mesa/drivers/dri/r300/r300_state.c | 208 ++++++++++++++++++++++++++++++++-
 1 file changed, 206 insertions(+), 2 deletions(-)

(limited to 'src/mesa/drivers/dri/r300/r300_state.c')

diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index e11b5afc30..d2fd04a550 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -1603,6 +1603,128 @@ static void r300SetupRSUnit(GLcontext * ctx)
 		WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead);
 }
 
+static void r500SetupRSUnit(GLcontext * ctx)
+{
+	r300ContextPtr r300 = R300_CONTEXT(ctx);
+	/* I'm still unsure if these are needed */
+	GLuint interp_magic[8] = {
+		0x00,
+		R300_RS_COL_PTR(1),
+		R300_RS_COL_PTR(2),
+		R300_RS_COL_PTR(3),
+		0x00,
+		0x00,
+		0x00,
+		0x00
+	};
+	union r300_outputs_written OutputsWritten;
+	GLuint InputsRead;
+	int fp_reg, high_rr;
+	int in_texcoords, col_interp_nr;
+	int i;
+
+	if (hw_tcl_on)
+		OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten;
+	else
+		RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->state.render_inputs_bitset);
+
+	if (ctx->FragmentProgram._Current)
+		InputsRead = ctx->FragmentProgram._Current->Base.InputsRead;
+	else {
+		fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
+		return;		/* This should only ever happen once.. */
+	}
+
+	R300_STATECHANGE(r300, ri);
+	R300_STATECHANGE(r300, rc);
+	R300_STATECHANGE(r300, rr);
+
+	fp_reg = in_texcoords = col_interp_nr = high_rr = 0;
+
+	r300->hw.rr.cmd[R300_RR_ROUTE_1] = 0;
+
+	if (InputsRead & FRAG_BIT_WPOS) {
+		for (i = 0; i < ctx->Const.MaxTextureUnits; i++)
+			if (!(InputsRead & (FRAG_BIT_TEX0 << i)))
+				break;
+
+		if (i == ctx->Const.MaxTextureUnits) {
+			fprintf(stderr, "\tno free texcoord found...\n");
+			_mesa_exit(-1);
+		}
+
+		InputsRead |= (FRAG_BIT_TEX0 << i);
+		InputsRead &= ~FRAG_BIT_WPOS;
+	}
+
+	for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
+		r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = 0 | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3) | (in_texcoords << R300_RS_INTERP_SRC_SHIFT)
+		    | interp_magic[i];
+
+		r300->hw.rr.cmd[R300_RR_ROUTE_0 + fp_reg] = 0;
+		if (InputsRead & (FRAG_BIT_TEX0 << i)) {
+			//assert(r300->state.texture.tc_count != 0);
+			r300->hw.rr.cmd[R300_RR_ROUTE_0 + fp_reg] |= R300_RS_ROUTE_ENABLE | i	/* source INTERP */
+			    | (fp_reg << R300_RS_ROUTE_DEST_SHIFT);
+			high_rr = fp_reg;
+
+			/* Passing invalid data here can lock the GPU. */
+			if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) {
+				InputsRead &= ~(FRAG_BIT_TEX0 << i);
+				fp_reg++;
+			} else {
+				WARN_ONCE("fragprog wants coords for tex%d, vp doesn't provide them!\n", i);
+			}
+		}
+		/* Need to count all coords enabled at vof */
+		if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) {
+			in_texcoords++;
+		}
+	}
+
+	if (InputsRead & FRAG_BIT_COL0) {
+		if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) {
+			r300->hw.rr.cmd[R300_RR_ROUTE_0] |= 0 | R300_RS_ROUTE_0_COLOR | (fp_reg++ << R300_RS_ROUTE_0_COLOR_DEST_SHIFT);
+			InputsRead &= ~FRAG_BIT_COL0;
+			col_interp_nr++;
+		} else {
+			WARN_ONCE("fragprog wants col0, vp doesn't provide it\n");
+		}
+	}
+
+	if (InputsRead & FRAG_BIT_COL1) {
+		if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) {
+			r300->hw.rr.cmd[R300_RR_ROUTE_1] |= R300_RS_ROUTE_1_UNKNOWN11 | R300_RS_ROUTE_1_COLOR1 | (fp_reg++ << R300_RS_ROUTE_1_COLOR1_DEST_SHIFT);
+			InputsRead &= ~FRAG_BIT_COL1;
+			if (high_rr < 1)
+				high_rr = 1;
+			col_interp_nr++;
+		} else {
+			WARN_ONCE("fragprog wants col1, vp doesn't provide it\n");
+		}
+	}
+
+	/* Need at least one. This might still lock as the values are undefined... */
+	if (in_texcoords == 0 && col_interp_nr == 0) {
+		r300->hw.rr.cmd[R300_RR_ROUTE_0] |= 0 | R300_RS_ROUTE_0_COLOR | (fp_reg++ << R300_RS_ROUTE_0_COLOR_DEST_SHIFT);
+		col_interp_nr++;
+	}
+
+	r300->hw.rc.cmd[1] = 0 | ((in_texcoords << 2) << R300_IT_COUNT_SHIFT)
+	  | (col_interp_nr << R300_IC_COUNT_SHIFT)
+	  | R300_HIRES_EN;
+
+	assert(high_rr >= 0);
+	r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R300_RS_ROUTE_0, high_rr + 1);
+	r300->hw.rc.cmd[2] = 0xC0 | high_rr;
+
+	if (InputsRead)
+		WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead);
+}
+
+
+
+
 #define bump_vpu_count(ptr, new_count)   do{\
 	drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\
 	int _nc=(new_count)/4; \
@@ -2163,6 +2285,81 @@ static void r300SetupPixelShader(r300ContextPtr rmesa)
 	}
 }
 
+static void r500SetupPixelShader(r300ContextPtr rmesa)
+{
+	GLcontext *ctx = rmesa->radeon.glCtx;
+	struct r300_fragment_program *fp = (struct r300_fragment_program *)
+	    (char *)ctx->FragmentProgram._Current;
+	int i, k;
+
+	if (!fp)		/* should only happenen once, just after context is created */
+		return;
+
+	/* emit the standard zero shader */
+	R300_STATECHANGE(rmesa, r500fp);
+	i = 1;
+	rmesa->hw.r500fp.cmd[i++] = 0x7807;
+	rmesa->hw.r500fp.cmd[i++] = R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED;
+	rmesa->hw.r500fp.cmd[i++] = R500_TEX_SRC_ADDR(0) |  R500_TEX_SRC_S_SWIZ_R |
+		R500_TEX_SRC_T_SWIZ_G |
+		R500_TEX_DST_ADDR(0) |
+		R500_TEX_DST_R_SWIZ_R |
+		R500_TEX_DST_G_SWIZ_G |
+		R500_TEX_DST_B_SWIZ_B |
+		R500_TEX_DST_A_SWIZ_A;
+	rmesa->hw.r500fp.cmd[i++] = R500_DX_ADDR(0) |
+		R500_DX_S_SWIZ_R |
+		R500_DX_T_SWIZ_R |
+		R500_DX_R_SWIZ_R |
+		R500_DX_Q_SWIZ_R |
+		R500_DY_ADDR(0) |
+		R500_DY_S_SWIZ_R |
+		R500_DY_T_SWIZ_R |
+		R500_DY_R_SWIZ_R |
+		R500_DY_Q_SWIZ_R;
+	rmesa->hw.r500fp.cmd[i++] = 0x0;
+	rmesa->hw.r500fp.cmd[i++] = 0x0;
+
+	rmesa->hw.r500fp.cmd[i++] = R500_INST_TYPE_OUT |
+		R500_INST_TEX_SEM_WAIT |
+		R500_INST_LAST |
+		R500_INST_RGB_OMASK_R |
+		R500_INST_RGB_OMASK_G |
+		R500_INST_RGB_OMASK_B |
+		R500_INST_ALPHA_OMASK;
+
+	rmesa->hw.r500fp.cmd[i++] = R500_RGB_ADDR0(0) |
+		R500_RGB_ADDR1(0) |
+		R500_RGB_ADDR1_CONST |
+		R500_RGB_ADDR2(0) |
+		R500_RGB_ADDR2_CONST |
+		R500_RGB_SRCP_OP_1_MINUS_2RGB0;
+	rmesa->hw.r500fp.cmd[i++] = R500_ALPHA_ADDR0(0) |
+		R500_ALPHA_ADDR1(0) |
+		R500_ALPHA_ADDR1_CONST |
+		R500_ALPHA_ADDR2(0) |
+		R500_ALPHA_ADDR2_CONST |
+		R500_ALPHA_SRCP_OP_1_MINUS_2A0;
+	rmesa->hw.r500fp.cmd[i++] = R500_ALU_RGB_SEL_A_SRC0 |
+		R500_ALU_RGB_R_SWIZ_A_R |
+		R500_ALU_RGB_G_SWIZ_A_G |
+		R500_ALU_RGB_B_SWIZ_A_B |
+		R500_ALU_RGB_SEL_B_SRC0 |
+		R500_ALU_RGB_R_SWIZ_B_1 |
+		R500_ALU_RGB_B_SWIZ_B_1 |
+		R500_ALU_RGB_G_SWIZ_B_1;
+	rmesa->hw.r500fp.cmd[i++] = R500_ALPHA_OP_MAD |
+		R500_ALPHA_SWIZ_A_A |
+		R500_ALPHA_SWIZ_B_1;
+	rmesa->hw.r500fp.cmd[i++] = R500_ALU_RGBA_OP_MAD |
+		R500_ALU_RGBA_R_SWIZ_0 |
+		R500_ALU_RGBA_G_SWIZ_0 |
+		R500_ALU_RGBA_B_SWIZ_0 |
+		R500_ALU_RGBA_A_SWIZ_0;
+
+
+}
+
 void r300UpdateShaderStates(r300ContextPtr rmesa)
 {
 	GLcontext *ctx;
@@ -2170,12 +2367,19 @@ void r300UpdateShaderStates(r300ContextPtr rmesa)
 
 	r300UpdateTextureState(ctx);
 
-	r300SetupPixelShader(rmesa);
+	if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
+		r500SetupPixelShader(rmesa);
+	else
+		r300SetupPixelShader(rmesa);
 	r300SetupTextures(ctx);
 
 	if ((rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
 		r300SetupVertexProgram(rmesa);
-	r300SetupRSUnit(ctx);
+
+	if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
+		r500SetupRSUnit(ctx);
+	else
+		r300SetupRSUnit(ctx);
 }
 
 /**
-- 
cgit v1.2.3


From a453b3154e063c3e934cb90a546e984a758dd14f Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 20 Mar 2008 13:55:56 +1000
Subject: r500 RS unit setup

---
 src/mesa/drivers/dri/r300/r300_cmdbuf.c |  4 ----
 src/mesa/drivers/dri/r300/r300_reg.h    | 22 +++++++++++-----------
 src/mesa/drivers/dri/r300/r300_state.c  | 28 ++++++++++++++++++----------
 3 files changed, 29 insertions(+), 25 deletions(-)

(limited to 'src/mesa/drivers/dri/r300/r300_state.c')

diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index a92bb87d7d..3cfb7cf2cd 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -399,10 +399,6 @@ void r300InitCmdBuf(r300ContextPtr r300)
 	if (is_r500) {
 		ALLOC_STATE(r500fp, variable, R300_FPI_CMDSIZE, 0);
 		r300->hw.r500fp.cmd[R300_FPI_CMD_0] = cmdr500fp(0, 0);
-	}
-
-	if (is_r500) {
-
 	} else {
 		ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
 		r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(R300_PFS_CNTL_0, 3);
diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h
index d640d8b7e7..2822b1d4c3 100644
--- a/src/mesa/drivers/dri/r300/r300_reg.h
+++ b/src/mesa/drivers/dri/r300/r300_reg.h
@@ -673,12 +673,12 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define R500_RS_IP_13					0x40A8
 #define R500_RS_IP_14					0x40AC
 #define R500_RS_IP_15					0x40B0
-#define R500_RS_IP_TEX_PTR_S_SHIFT 			0
-#define R500_RS_IP_TEX_PTR_T_SHIFT 			6
-#define R500_RS_IP_TEX_PTR_R_SHIFT 			12
-#define R500_RS_IP_TEX_PTR_Q_SHIFT 			18
-#define R500_RS_IP_COL_PTR_SHIFT 			24
-#define R500_RS_IP_COL_FMT_SHIFT 			27
+#define R500_RS_IP_TEX_PTR_S_SHIFT 			0
+#define R500_RS_IP_TEX_PTR_T_SHIFT 			6
+#define R500_RS_IP_TEX_PTR_R_SHIFT 			12
+#define R500_RS_IP_TEX_PTR_Q_SHIFT 			18
+#define R500_RS_IP_COL_PTR_SHIFT 			24
+#define R500_RS_IP_COL_FMT_SHIFT 			27
 #define R500_RS_IP_COL_FMT_RGBA 			(0 << 27)
 #define R500_RS_IP_COL_FMT_RGB0 			(1 << 27)
 #define R500_RS_IP_COL_FMT_RGB1 			(2 << 27)
@@ -692,7 +692,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define R500_RS_IP_COL_FMT_1111 			(10 << 27)
 /* gap */
 #define R500_RS_IP_OFFSET_DIS 				(0 << 31)
-#define R500_RS_IP_OFFSET_EN 				(1 << 31)
+#define R500_RS_IP_OFFSET_EN 				(1 << 31)
 
 /* gap */
 
@@ -1138,10 +1138,10 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #	define R300_RS_COL_FMT_111A		        8
 #	define R300_RS_COL_FMT_1110		        9
 #	define R300_RS_COL_FMT_1111		        10
-#	define R300_RS_SEL_S(x)		                (x << 13)
-#	define R300_RS_SEL_T(x)		                (x << 16)
-#	define R300_RS_SEL_R(x)		                (x << 19)
-#	define R300_RS_SEL_Q(x)		                (x << 22)
+#	define R300_RS_SEL_S(x)		                (x << 13)
+#	define R300_RS_SEL_T(x)		                (x << 16)
+#	define R300_RS_SEL_R(x)		                (x << 19)
+#	define R300_RS_SEL_Q(x)		                (x << 22)
 #	define R300_RS_SEL_C0		                0
 #	define R300_RS_SEL_C1		                1
 #	define R300_RS_SEL_C2		                2
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index d2fd04a550..04ee59da63 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -1609,9 +1609,9 @@ static void r500SetupRSUnit(GLcontext * ctx)
 	/* I'm still unsure if these are needed */
 	GLuint interp_magic[8] = {
 		0x00,
-		R300_RS_COL_PTR(1),
-		R300_RS_COL_PTR(2),
-		R300_RS_COL_PTR(3),
+		1 << 24,
+		2 << 24,
+		3 << 24,
 		0x00,
 		0x00,
 		0x00,
@@ -1658,14 +1658,20 @@ static void r500SetupRSUnit(GLcontext * ctx)
 	}
 
 	for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
-		r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = 0 | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3) | (in_texcoords << R300_RS_INTERP_SRC_SHIFT)
-		    | interp_magic[i];
+	  
+	  //		r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = 0 | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3) | (in_texcoords << R300_RS_INTERP_SRC_SHIFT)
+	  
+		r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = (0 << R500_TEX_PTR_S_SHIFT) | 
+			(1 << R500_TEX_PTR_T_SHIFT) |
+			(2 << R500_TEX_PTR_R_SHIFT) | 
+			(3 << R500_TEX_PTR_Q_SHIFT) |
+			(in_texcoords << 0) | interp_magic[i];
 
 		r300->hw.rr.cmd[R300_RR_ROUTE_0 + fp_reg] = 0;
 		if (InputsRead & (FRAG_BIT_TEX0 << i)) {
 			//assert(r300->state.texture.tc_count != 0);
-			r300->hw.rr.cmd[R300_RR_ROUTE_0 + fp_reg] |= R300_RS_ROUTE_ENABLE | i	/* source INTERP */
-			    | (fp_reg << R300_RS_ROUTE_DEST_SHIFT);
+			r300->hw.rr.cmd[R300_RR_ROUTE_0 + fp_reg] |= R500_RS_INST_TEX_CN_WRITE | i	/* source INTERP */
+			    | (fp_reg << R500_RS_INST_TEX_ADDR_SHIFT);
 			high_rr = fp_reg;
 
 			/* Passing invalid data here can lock the GPU. */
@@ -1684,7 +1690,8 @@ static void r500SetupRSUnit(GLcontext * ctx)
 
 	if (InputsRead & FRAG_BIT_COL0) {
 		if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) {
-			r300->hw.rr.cmd[R300_RR_ROUTE_0] |= 0 | R300_RS_ROUTE_0_COLOR | (fp_reg++ << R300_RS_ROUTE_0_COLOR_DEST_SHIFT);
+			//			r300->hw.rr.cmd[R300_RR_ROUTE_0] |= 0 | R300_RS_ROUTE_0_COLOR | (fp_reg++ << R300_RS_ROUTE_0_COLOR_DEST_SHIFT);
+			r300->hw.rr.cmd[R300_RR_ROUTE_0] |= 0 | R500_RS_INST_COL_CN_WRITE | (fp_reg++ << R500_RS_INST_COL_COL_ADDR_SHIFT);
 			InputsRead &= ~FRAG_BIT_COL0;
 			col_interp_nr++;
 		} else {
@@ -1694,7 +1701,8 @@ static void r500SetupRSUnit(GLcontext * ctx)
 
 	if (InputsRead & FRAG_BIT_COL1) {
 		if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) {
-			r300->hw.rr.cmd[R300_RR_ROUTE_1] |= R300_RS_ROUTE_1_UNKNOWN11 | R300_RS_ROUTE_1_COLOR1 | (fp_reg++ << R300_RS_ROUTE_1_COLOR1_DEST_SHIFT);
+			//			r300->hw.rr.cmd[R300_RR_ROUTE_1] |= R300_RS_ROUTE_1_UNKNOWN11 | R300_RS_ROUTE_1_COLOR1 | (fp_reg++ << R300_RS_ROUTE_1_COLOR1_DEST_SHIFT);
+			r300->hw.rr.cmd[R300_RR_ROUTE_1] |= (1 << 12) | R500_RS_INST_COL_CN_WRITER300_RS_ROUTE_1_UNKNOWN11 |  (fp_reg++ << R500_RS_INST_COL_COL_ADDR_SHIFT);
 			InputsRead &= ~FRAG_BIT_COL1;
 			if (high_rr < 1)
 				high_rr = 1;
@@ -1706,7 +1714,7 @@ static void r500SetupRSUnit(GLcontext * ctx)
 
 	/* Need at least one. This might still lock as the values are undefined... */
 	if (in_texcoords == 0 && col_interp_nr == 0) {
-		r300->hw.rr.cmd[R300_RR_ROUTE_0] |= 0 | R300_RS_ROUTE_0_COLOR | (fp_reg++ << R300_RS_ROUTE_0_COLOR_DEST_SHIFT);
+		r300->hw.rr.cmd[R300_RR_ROUTE_0] |= 0 | R500_RS_INST_COL_CN_WRITE | (fp_reg++ << R500_RS_INST_COL_COL_ADDR_SHIFT);
 		col_interp_nr++;
 	}
 
-- 
cgit v1.2.3


From c0cb9bc84c1997d790d0b7efa8ed94fc601d7d19 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 20 Mar 2008 14:21:10 +1000
Subject: mesa: cleanup state emission and rs for r500

trivial clear app now renders
---
 src/mesa/drivers/dri/r300/r300_emit.h  | 13 +++++
 src/mesa/drivers/dri/r300/r300_ioctl.c | 86 ++++++++++++++++++++++++++++++++++
 src/mesa/drivers/dri/r300/r300_state.c | 10 ++--
 3 files changed, 104 insertions(+), 5 deletions(-)

(limited to 'src/mesa/drivers/dri/r300/r300_state.c')

diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h
index a4f6ab997e..50e7e4f149 100644
--- a/src/mesa/drivers/dri/r300/r300_emit.h
+++ b/src/mesa/drivers/dri/r300/r300_emit.h
@@ -178,6 +178,19 @@ static inline uint32_t cmdpacify(void)
 		cmd[0].i = cmdvpu((dest), _n/4);			\
 	} while (0);
 
+#define r500fp_start_fragment(dest, length)				\
+	do {								\
+		int _n;							\
+		_n = (length);						\
+		cmd = (drm_radeon_cmd_header_t*)			\
+			r300AllocCmdBuf(rmesa,				\
+					(_n+1),				\
+					__FUNCTION__);			\
+		cmd_reserved = _n+1;					\
+		cmd_written =1;						\
+		cmd[0].i = cmdr500fp((dest), _n/6);			\
+	} while (0);
+
 #define start_packet3(packet, count)					\
 	{								\
 		int _n;							\
diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c
index 07656b130c..14258324bd 100644
--- a/src/mesa/drivers/dri/r300/r300_ioctl.c
+++ b/src/mesa/drivers/dri/r300/r300_ioctl.c
@@ -292,6 +292,26 @@ static void r300EmitClearState(GLcontext * ctx)
 		R300_STATECHANGE(r300, rr);
 		reg_start(R300_RS_ROUTE_0, 0);
 		e32(R300_RS_ROUTE_0_COLOR);
+	} else {
+	  
+		R300_STATECHANGE(r300, ri);
+		reg_start(R500_RS_IP_0, 8);
+		for (i = 0; i < 8; ++i) {
+			e32((1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
+			    (2 << R500_RS_IP_TEX_PTR_R_SHIFT) | 
+			    (3 << R500_RS_IP_TEX_PTR_Q_SHIFT) );
+		}
+
+		R300_STATECHANGE(r300, rc);
+		/* The second constant is needed to get glxgears display anything .. */
+		reg_start(R300_RS_COUNT, 1);
+		e32((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
+		e32(0x0);
+
+		R300_STATECHANGE(r300, rr);
+		reg_start(R500_RS_INST_0, 0);
+		e32(R500_RS_INST_COL_CN_WRITE);
+
 	}
 
 	if (!is_r500) {
@@ -322,6 +342,72 @@ static void r300EmitClearState(GLcontext * ctx)
 
 		reg_start(R300_PFS_INSTR3_0, 0);
 		e32(FP_SELA(0, NO, W, FP_TMP(0), 0, 0));
+	} else {
+		R300_STATECHANGE(r300, r500fp);
+		r500fp_start_fragment(0, 12);
+
+		e32(0x7808);
+		e32(R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED);
+		e32(R500_TEX_SRC_ADDR(0) |  R500_TEX_SRC_S_SWIZ_R |
+		    R500_TEX_SRC_T_SWIZ_G |
+		    R500_TEX_DST_ADDR(0) |
+		    R500_TEX_DST_R_SWIZ_R |
+		    R500_TEX_DST_G_SWIZ_G |
+		    R500_TEX_DST_B_SWIZ_B |
+		    R500_TEX_DST_A_SWIZ_A);
+		e32(R500_DX_ADDR(0) |
+		    R500_DX_S_SWIZ_R |
+		    R500_DX_T_SWIZ_R |
+		    R500_DX_R_SWIZ_R |
+		    R500_DX_Q_SWIZ_R |
+		    R500_DY_ADDR(0) |
+		    R500_DY_S_SWIZ_R |
+		    R500_DY_T_SWIZ_R |
+		    R500_DY_R_SWIZ_R |
+		    R500_DY_Q_SWIZ_R);
+		e32(0x0);
+		e32(0x0);
+
+		e32(R500_INST_TYPE_OUT |
+		    R500_INST_TEX_SEM_WAIT |
+		    R500_INST_LAST |
+		    R500_INST_RGB_OMASK_R |
+		    R500_INST_RGB_OMASK_G |
+		    R500_INST_RGB_OMASK_B |
+		    R500_INST_ALPHA_OMASK);
+
+		e32(R500_RGB_ADDR0(0) |
+		    R500_RGB_ADDR1(0) |
+		    R500_RGB_ADDR1_CONST |
+		    R500_RGB_ADDR2(0) |
+		    R500_RGB_ADDR2_CONST |
+		    R500_RGB_SRCP_OP_1_MINUS_2RGB0);
+
+		e32(R500_ALPHA_ADDR0(0) |
+		    R500_ALPHA_ADDR1(0) |
+		    R500_ALPHA_ADDR1_CONST |
+		    R500_ALPHA_ADDR2(0) |
+		    R500_ALPHA_ADDR2_CONST |
+		    R500_ALPHA_SRCP_OP_1_MINUS_2A0);
+
+		e32(R500_ALU_RGB_SEL_A_SRC0 |
+		    R500_ALU_RGB_R_SWIZ_A_R |
+		    R500_ALU_RGB_G_SWIZ_A_G |
+		    R500_ALU_RGB_B_SWIZ_A_B |
+		    R500_ALU_RGB_SEL_B_SRC0 |
+		    R500_ALU_RGB_R_SWIZ_B_1 |
+		    R500_ALU_RGB_B_SWIZ_B_1 |
+		    R500_ALU_RGB_G_SWIZ_B_1);
+
+		e32(R500_ALPHA_OP_MAD |
+		    R500_ALPHA_SWIZ_A_A |
+		    R500_ALPHA_SWIZ_B_1);
+
+		e32(R500_ALU_RGBA_OP_MAD |
+		    R500_ALU_RGBA_R_SWIZ_0 |
+		    R500_ALU_RGBA_G_SWIZ_0 |
+		    R500_ALU_RGBA_B_SWIZ_0 |
+		    R500_ALU_RGBA_A_SWIZ_0);
 	}
 
 	if (has_tcl) {
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index 04ee59da63..f4ee307adb 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -1661,10 +1661,10 @@ static void r500SetupRSUnit(GLcontext * ctx)
 	  
 	  //		r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = 0 | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3) | (in_texcoords << R300_RS_INTERP_SRC_SHIFT)
 	  
-		r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = (0 << R500_TEX_PTR_S_SHIFT) | 
-			(1 << R500_TEX_PTR_T_SHIFT) |
-			(2 << R500_TEX_PTR_R_SHIFT) | 
-			(3 << R500_TEX_PTR_Q_SHIFT) |
+		r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = (0 << R500_RS_IP_TEX_PTR_S_SHIFT) | 
+			(1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
+			(2 << R500_RS_IP_TEX_PTR_R_SHIFT) | 
+			(3 << R500_RS_IP_TEX_PTR_Q_SHIFT) |
 			(in_texcoords << 0) | interp_magic[i];
 
 		r300->hw.rr.cmd[R300_RR_ROUTE_0 + fp_reg] = 0;
@@ -1702,7 +1702,7 @@ static void r500SetupRSUnit(GLcontext * ctx)
 	if (InputsRead & FRAG_BIT_COL1) {
 		if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) {
 			//			r300->hw.rr.cmd[R300_RR_ROUTE_1] |= R300_RS_ROUTE_1_UNKNOWN11 | R300_RS_ROUTE_1_COLOR1 | (fp_reg++ << R300_RS_ROUTE_1_COLOR1_DEST_SHIFT);
-			r300->hw.rr.cmd[R300_RR_ROUTE_1] |= (1 << 12) | R500_RS_INST_COL_CN_WRITER300_RS_ROUTE_1_UNKNOWN11 |  (fp_reg++ << R500_RS_INST_COL_COL_ADDR_SHIFT);
+			r300->hw.rr.cmd[R300_RR_ROUTE_1] |= (1 << 12) | R500_RS_INST_COL_CN_WRITE |  (fp_reg++ << R500_RS_INST_COL_COL_ADDR_SHIFT);
 			InputsRead &= ~FRAG_BIT_COL1;
 			if (high_rr < 1)
 				high_rr = 1;
-- 
cgit v1.2.3


From c07534dc719f53c0e59d59f3bd7dd25d1d32747c Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 20 Mar 2008 14:30:59 +1000
Subject: r300: this code really shouldn't be here.

For R500 just ignore it for now while I do something interesting like
run glxgears.
---
 src/mesa/drivers/dri/r300/r300_state.c | 55 ++++++++++++++++++----------------
 1 file changed, 29 insertions(+), 26 deletions(-)

(limited to 'src/mesa/drivers/dri/r300/r300_state.c')

diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index f4ee307adb..ffcc311c05 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -1436,40 +1436,43 @@ static void r300SetupTextures(GLcontext * ctx)
 	if (!fp)		/* should only happenen once, just after context is created */
 		return;
 
-	R300_STATECHANGE(r300, fpt);
 
-	for (i = 0; i < fp->tex.length; i++) {
-		int unit;
-		int opcode;
-		unsigned long val;
+        if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
+		R300_STATECHANGE(r300, fpt);
 
-		unit = fp->tex.inst[i] >> R300_FPITX_IMAGE_SHIFT;
-		unit &= 15;
-
-		val = fp->tex.inst[i];
-		val &= ~R300_FPITX_IMAGE_MASK;
-
-		opcode =
-		    (val & R300_FPITX_OPCODE_MASK) >> R300_FPITX_OPCODE_SHIFT;
-		if (opcode == R300_FPITX_OP_KIL) {
-			r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
-		} else {
-			if (tmu_mappings[unit] >= 0) {
-				val |=
-				    tmu_mappings[unit] <<
-				    R300_FPITX_IMAGE_SHIFT;
+		for (i = 0; i < fp->tex.length; i++) {
+			int unit;
+			int opcode;
+			unsigned long val;
+			
+			unit = fp->tex.inst[i] >> R300_FPITX_IMAGE_SHIFT;
+			unit &= 15;
+			
+			val = fp->tex.inst[i];
+			val &= ~R300_FPITX_IMAGE_MASK;
+			
+			opcode =
+				(val & R300_FPITX_OPCODE_MASK) >> R300_FPITX_OPCODE_SHIFT;
+			if (opcode == R300_FPITX_OP_KIL) {
 				r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
 			} else {
-				// We get here when the corresponding texture image is incomplete
-				// (e.g. incomplete mipmaps etc.)
-				r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
+				if (tmu_mappings[unit] >= 0) {
+					val |=
+						tmu_mappings[unit] <<
+						R300_FPITX_IMAGE_SHIFT;
+					r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
+				} else {
+					// We get here when the corresponding texture image is incomplete
+					// (e.g. incomplete mipmaps etc.)
+					r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val;
+				}
 			}
 		}
+		
+		r300->hw.fpt.cmd[R300_FPT_CMD_0] =
+			cmdpacket0(R300_PFS_TEXI_0, fp->tex.length);
 	}
 
-	r300->hw.fpt.cmd[R300_FPT_CMD_0] =
-	    cmdpacket0(R300_PFS_TEXI_0, fp->tex.length);
-
 	if (RADEON_DEBUG & DEBUG_STATE)
 		fprintf(stderr, "TX_ENABLE: %08x  last_hw_tmu=%d\n",
 			r300->hw.txe.cmd[R300_TXE_ENABLE], last_hw_tmu);
-- 
cgit v1.2.3


From 6864220c28c95991cf9577892156d670bd184007 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Sat, 22 Mar 2008 10:55:32 +1000
Subject: r500: fixup support for emitting fragment program to hardware.

Also fixup the constant emission

this breaks glxgears from what I can see but its another step to correctness
---
 src/mesa/drivers/dri/r300/r300_cmdbuf.c | 23 +++++++++++++++++++----
 src/mesa/drivers/dri/r300/r300_state.c  | 24 ++++++++++++++++++++++++
 2 files changed, 43 insertions(+), 4 deletions(-)

(limited to 'src/mesa/drivers/dri/r300/r300_state.c')

diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index 248de7e34a..d965a95c0f 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -242,6 +242,7 @@ void r300EmitState(r300ContextPtr r300)
 
 #define packet0_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->packet0.count)
 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
+#define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
 
 static int check_always(r300ContextPtr r300, struct r300_state_atom *atom)
 {
@@ -262,6 +263,20 @@ static int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom)
 	return cnt ? (cnt * 4) + 1 : 0;
 }
 
+static int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom)
+{
+	int cnt;
+	cnt = r500fp_count(atom->cmd);
+	return cnt ? (cnt * 6) + 1 : 0;
+}
+
+static int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom)
+{
+	int cnt;
+	cnt = r500fp_count(atom->cmd);
+	return cnt ? (cnt * 4) + 1 : 0;
+}
+
 #define ALLOC_STATE( ATOM, CHK, SZ, IDX )				\
    do {									\
       r300->hw.ATOM.cmd_size = (SZ);					\
@@ -397,9 +412,9 @@ void r300InitCmdBuf(r300ContextPtr r300)
 	r300->hw.us_out_fmt.cmd[0] = cmdpacket0(R500_US_OUT_FMT, 5);
 
 	if (is_r500) {
-		ALLOC_STATE(r500fp, variable, R300_FPI_CMDSIZE, 0);
+		ALLOC_STATE(r500fp, r500fp, R300_FPI_CMDSIZE, 0);
 		r300->hw.r500fp.cmd[R300_FPI_CMD_0] = cmdr500fp(0, 0, 0, 0);
-		ALLOC_STATE(r500fp_const, variable, R300_FPI_CMDSIZE, 0);
+		ALLOC_STATE(r500fp_const, r500fp_const, R300_FPP_CMDSIZE, 0);
 		r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] = cmdr500fp(0, 0, 1, 0);
 	} else {
 		ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
@@ -416,6 +431,8 @@ void r300InitCmdBuf(r300ContextPtr r300)
 		r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_PFS_INSTR2_0, 1);
 		ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
 		r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_PFS_INSTR3_0, 1);
+		ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
+		r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(R300_PFS_PARAM_0_X, 0);
 	}
 	ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
 	r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(FG_FOG_BLEND, 1);
@@ -425,8 +442,6 @@ void r300InitCmdBuf(r300ContextPtr r300)
 	r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(FG_ALPHA_FUNC, 2);
 	ALLOC_STATE(fg_depth_src, always, 2, 0);
 	r300->hw.fg_depth_src.cmd[0] = cmdpacket0(R300_FG_DEPTH_SRC, 1);
-	ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
-	r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(R300_PFS_PARAM_0_X, 0);
 	ALLOC_STATE(rb3d_cctl, always, 2, 0);
 	r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(R300_RB3D_CCTL, 1);
 	ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index ffcc311c05..eab39ec4b0 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -2296,6 +2296,20 @@ static void r300SetupPixelShader(r300ContextPtr rmesa)
 	}
 }
 
+#define bump_r500fp_count(ptr, new_count)   do{\
+	drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\
+	int _nc=(new_count)/6; \
+	assert(_nc < 256); \
+	if(_nc>_p->r500fp.count)_p->r500fp.count=_nc;\
+} while(0)
+
+#define bump_r500fp_const_count(ptr, new_count)   do{\
+	drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\
+	int _nc=(new_count)/4; \
+	assert(_nc < 256); \
+	if(_nc>_p->r500fp.count)_p->r500fp.count=_nc;\
+} while(0)
+
 static void r500SetupPixelShader(r300ContextPtr rmesa)
 {
 	GLcontext *ctx = rmesa->radeon.glCtx;
@@ -2368,6 +2382,16 @@ static void r500SetupPixelShader(r300ContextPtr rmesa)
 		R500_ALU_RGBA_B_SWIZ_0 |
 		R500_ALU_RGBA_A_SWIZ_0;
 
+	bump_r500fp_count(rmesa->hw.r500fp.cmd, 12);
+
+	R300_STATECHANGE(rmesa, r500fp_const);
+	for (i = 0; i < fp->const_nr; i++) {
+		rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 0] = r300PackFloat24(fp->constant[i][0]);
+		rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 1] = r300PackFloat24(fp->constant[i][1]);
+		rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 2] = r300PackFloat24(fp->constant[i][2]);
+		rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 3] = r300PackFloat24(fp->constant[i][3]);
+	}
+	bump_r500fp_const_count(rmesa->hw.r500fp_const.cmd, fp->const_nr * 4);
 
 }
 
-- 
cgit v1.2.3


From fbab11e9b08d107b04d53833286da1c1487c2708 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Sat, 22 Mar 2008 10:56:48 +1000
Subject: r500: enable gb tiling for r5xx

---
 src/mesa/drivers/dri/r300/r300_state.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/mesa/drivers/dri/r300/r300_state.c')

diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index eab39ec4b0..ac36b3b43c 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -2046,6 +2046,8 @@ static void r300ResetHwState(r300ContextPtr r300)
 		    R300_GB_TILE_PIPE_COUNT_R300;
 		break;
 	case CHIP_FAMILY_R420:
+	case CHIP_FAMILY_RV515:
+	case CHIP_FAMILY_R520:
 		r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
 		    R300_GB_TILE_PIPE_COUNT_R420;
 		break;
-- 
cgit v1.2.3


From de9c1c3627de778671c0fa1215a2c5e24d4374dc Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Sat, 22 Mar 2008 11:00:25 +1000
Subject: r500: fixup fake shader to keep gears going

---
 src/mesa/drivers/dri/r300/r300_state.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/r300/r300_state.c')

diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index ac36b3b43c..6dc76aed87 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -2325,7 +2325,7 @@ static void r500SetupPixelShader(r300ContextPtr rmesa)
 	/* emit the standard zero shader */
 	R300_STATECHANGE(rmesa, r500fp);
 	i = 1;
-	rmesa->hw.r500fp.cmd[i++] = 0x7807;
+	rmesa->hw.r500fp.cmd[i++] = 0x7808;
 	rmesa->hw.r500fp.cmd[i++] = R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED;
 	rmesa->hw.r500fp.cmd[i++] = R500_TEX_SRC_ADDR(0) |  R500_TEX_SRC_S_SWIZ_R |
 		R500_TEX_SRC_T_SWIZ_G |
-- 
cgit v1.2.3


From 28904e54d2a1bae009cbb88088b81e8d5bbd15d5 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Wed, 16 Apr 2008 20:42:15 +1000
Subject: fixup r500 bits for renaming

---
 src/mesa/drivers/dri/r300/r300_state.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

(limited to 'src/mesa/drivers/dri/r300/r300_state.c')

diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index 6dc76aed87..8f12266a5f 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -1644,7 +1644,7 @@ static void r500SetupRSUnit(GLcontext * ctx)
 
 	fp_reg = in_texcoords = col_interp_nr = high_rr = 0;
 
-	r300->hw.rr.cmd[R300_RR_ROUTE_1] = 0;
+	r300->hw.rr.cmd[R300_RR_INST_1] = 0;
 
 	if (InputsRead & FRAG_BIT_WPOS) {
 		for (i = 0; i < ctx->Const.MaxTextureUnits; i++)
@@ -1670,10 +1670,10 @@ static void r500SetupRSUnit(GLcontext * ctx)
 			(3 << R500_RS_IP_TEX_PTR_Q_SHIFT) |
 			(in_texcoords << 0) | interp_magic[i];
 
-		r300->hw.rr.cmd[R300_RR_ROUTE_0 + fp_reg] = 0;
+		r300->hw.rr.cmd[R300_RR_INST_0 + fp_reg] = 0;
 		if (InputsRead & (FRAG_BIT_TEX0 << i)) {
 			//assert(r300->state.texture.tc_count != 0);
-			r300->hw.rr.cmd[R300_RR_ROUTE_0 + fp_reg] |= R500_RS_INST_TEX_CN_WRITE | i	/* source INTERP */
+			r300->hw.rr.cmd[R300_RR_INST_0 + fp_reg] |= R500_RS_INST_TEX_CN_WRITE | i	/* source INTERP */
 			    | (fp_reg << R500_RS_INST_TEX_ADDR_SHIFT);
 			high_rr = fp_reg;
 
@@ -1694,7 +1694,7 @@ static void r500SetupRSUnit(GLcontext * ctx)
 	if (InputsRead & FRAG_BIT_COL0) {
 		if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) {
 			//			r300->hw.rr.cmd[R300_RR_ROUTE_0] |= 0 | R300_RS_ROUTE_0_COLOR | (fp_reg++ << R300_RS_ROUTE_0_COLOR_DEST_SHIFT);
-			r300->hw.rr.cmd[R300_RR_ROUTE_0] |= 0 | R500_RS_INST_COL_CN_WRITE | (fp_reg++ << R500_RS_INST_COL_COL_ADDR_SHIFT);
+			r300->hw.rr.cmd[R300_RR_INST_0] |= 0 | R500_RS_INST_COL_CN_WRITE | (fp_reg++ << R500_RS_INST_COL_ADDR_SHIFT);
 			InputsRead &= ~FRAG_BIT_COL0;
 			col_interp_nr++;
 		} else {
@@ -1705,7 +1705,7 @@ static void r500SetupRSUnit(GLcontext * ctx)
 	if (InputsRead & FRAG_BIT_COL1) {
 		if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) {
 			//			r300->hw.rr.cmd[R300_RR_ROUTE_1] |= R300_RS_ROUTE_1_UNKNOWN11 | R300_RS_ROUTE_1_COLOR1 | (fp_reg++ << R300_RS_ROUTE_1_COLOR1_DEST_SHIFT);
-			r300->hw.rr.cmd[R300_RR_ROUTE_1] |= (1 << 12) | R500_RS_INST_COL_CN_WRITE |  (fp_reg++ << R500_RS_INST_COL_COL_ADDR_SHIFT);
+			r300->hw.rr.cmd[R300_RR_INST_1] |= (1 << 12) | R500_RS_INST_COL_CN_WRITE |  (fp_reg++ << R500_RS_INST_COL_ADDR_SHIFT);
 			InputsRead &= ~FRAG_BIT_COL1;
 			if (high_rr < 1)
 				high_rr = 1;
@@ -1717,7 +1717,7 @@ static void r500SetupRSUnit(GLcontext * ctx)
 
 	/* Need at least one. This might still lock as the values are undefined... */
 	if (in_texcoords == 0 && col_interp_nr == 0) {
-		r300->hw.rr.cmd[R300_RR_ROUTE_0] |= 0 | R500_RS_INST_COL_CN_WRITE | (fp_reg++ << R500_RS_INST_COL_COL_ADDR_SHIFT);
+		r300->hw.rr.cmd[R300_RR_INST_0] |= 0 | R500_RS_INST_COL_CN_WRITE | (fp_reg++ << R500_RS_INST_COL_ADDR_SHIFT);
 		col_interp_nr++;
 	}
 
@@ -1726,7 +1726,7 @@ static void r500SetupRSUnit(GLcontext * ctx)
 	  | R300_HIRES_EN;
 
 	assert(high_rr >= 0);
-	r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R300_RS_ROUTE_0, high_rr + 1);
+	r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R300_RS_INST_0, high_rr + 1);
 	r300->hw.rc.cmd[2] = 0xC0 | high_rr;
 
 	if (InputsRead)
-- 
cgit v1.2.3


From 831fc138c1617f5cb49da589ea5126c8eda364a4 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alex@botch2.com>
Date: Thu, 1 May 2008 16:02:58 -0400
Subject: R5xx: Add R5xx pci ids

---
 src/mesa/drivers/dri/r300/r300_state.c       |   4 +
 src/mesa/drivers/dri/radeon/radeon_chipset.h | 104 +++++++++++++++++++++++
 src/mesa/drivers/dri/radeon/radeon_screen.c  | 120 ++++++++++++++++++++++++++-
 3 files changed, 227 insertions(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/r300/r300_state.c')

diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index 8f12266a5f..7419b15a55 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -2048,6 +2048,10 @@ static void r300ResetHwState(r300ContextPtr r300)
 	case CHIP_FAMILY_R420:
 	case CHIP_FAMILY_RV515:
 	case CHIP_FAMILY_R520:
+	case CHIP_FAMILY_RV530:
+	case CHIP_FAMILY_R580:
+	case CHIP_FAMILY_RV560:
+	case CHIP_FAMILY_RV570:
 		r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
 		    R300_GB_TILE_PIPE_COUNT_R420;
 		break;
diff --git a/src/mesa/drivers/dri/radeon/radeon_chipset.h b/src/mesa/drivers/dri/radeon/radeon_chipset.h
index dc1b8a9c8e..2821ecc0c0 100644
--- a/src/mesa/drivers/dri/radeon/radeon_chipset.h
+++ b/src/mesa/drivers/dri/radeon/radeon_chipset.h
@@ -147,12 +147,111 @@
 #define PCI_CHIP_RV410_5E4D		0x5E4D
 #define PCI_CHIP_RV410_5E4F		0x5E4F
 
+#define PCI_CHIP_R520_7100              0x7100
+#define PCI_CHIP_R520_7101              0x7101
+#define PCI_CHIP_R520_7102              0x7102
+#define PCI_CHIP_R520_7103              0x7103
+#define PCI_CHIP_R520_7104              0x7104
+#define PCI_CHIP_R520_7105              0x7105
+#define PCI_CHIP_R520_7106              0x7106
+#define PCI_CHIP_R520_7108              0x7108
+#define PCI_CHIP_R520_7109              0x7109
+#define PCI_CHIP_R520_710A              0x710A
+#define PCI_CHIP_R520_710B              0x710B
+#define PCI_CHIP_R520_710C              0x710C
+#define PCI_CHIP_R520_710E              0x710E
+#define PCI_CHIP_R520_710F              0x710F
+#define PCI_CHIP_RV515_7140             0x7140
+#define PCI_CHIP_RV515_7141             0x7141
+#define PCI_CHIP_RV515_7142             0x7142
+#define PCI_CHIP_RV515_7143             0x7143
+#define PCI_CHIP_RV515_7144             0x7144
+#define PCI_CHIP_RV515_7145             0x7145
+#define PCI_CHIP_RV515_7146             0x7146
+#define PCI_CHIP_RV515_7147             0x7147
+#define PCI_CHIP_RV515_7149             0x7149
+#define PCI_CHIP_RV515_714A             0x714A
+#define PCI_CHIP_RV515_714B             0x714B
+#define PCI_CHIP_RV515_714C             0x714C
+#define PCI_CHIP_RV515_714D             0x714D
+#define PCI_CHIP_RV515_714E             0x714E
+#define PCI_CHIP_RV515_714F             0x714F
+#define PCI_CHIP_RV515_7151             0x7151
+#define PCI_CHIP_RV515_7152             0x7152
+#define PCI_CHIP_RV515_7153             0x7153
+#define PCI_CHIP_RV515_715E             0x715E
+#define PCI_CHIP_RV515_715F             0x715F
+#define PCI_CHIP_RV515_7180             0x7180
+#define PCI_CHIP_RV515_7181             0x7181
+#define PCI_CHIP_RV515_7183             0x7183
+#define PCI_CHIP_RV515_7186             0x7186
+#define PCI_CHIP_RV515_7187             0x7187
+#define PCI_CHIP_RV515_7188             0x7188
+#define PCI_CHIP_RV515_718A             0x718A
+#define PCI_CHIP_RV515_718B             0x718B
+#define PCI_CHIP_RV515_718C             0x718C
+#define PCI_CHIP_RV515_718D             0x718D
+#define PCI_CHIP_RV515_718F             0x718F
+#define PCI_CHIP_RV515_7193             0x7193
+#define PCI_CHIP_RV515_7196             0x7196
+#define PCI_CHIP_RV515_719B             0x719B
+#define PCI_CHIP_RV515_719F             0x719F
+#define PCI_CHIP_RV530_71C0             0x71C0
+#define PCI_CHIP_RV530_71C1             0x71C1
+#define PCI_CHIP_RV530_71C2             0x71C2
+#define PCI_CHIP_RV530_71C3             0x71C3
 #define PCI_CHIP_RV530_71C4             0x71C4
+#define PCI_CHIP_RV530_71C5             0x71C5
+#define PCI_CHIP_RV530_71C6             0x71C6
+#define PCI_CHIP_RV530_71C7             0x71C7
+#define PCI_CHIP_RV530_71CD             0x71CD
+#define PCI_CHIP_RV530_71CE             0x71CE
+#define PCI_CHIP_RV530_71D2             0x71D2
+#define PCI_CHIP_RV530_71D4             0x71D4
+#define PCI_CHIP_RV530_71D5             0x71D5
+#define PCI_CHIP_RV530_71D6             0x71D6
+#define PCI_CHIP_RV530_71DA             0x71DA
+#define PCI_CHIP_RV530_71DE             0x71DE
+#define PCI_CHIP_RV515_7200             0x7200
+#define PCI_CHIP_RV515_7210             0x7210
+#define PCI_CHIP_RV515_7211             0x7211
+#define PCI_CHIP_R580_7240              0x7240
+#define PCI_CHIP_R580_7243              0x7243
+#define PCI_CHIP_R580_7244              0x7244
+#define PCI_CHIP_R580_7245              0x7245
+#define PCI_CHIP_R580_7246              0x7246
+#define PCI_CHIP_R580_7247              0x7247
+#define PCI_CHIP_R580_7248              0x7248
+#define PCI_CHIP_R580_7249              0x7249
+#define PCI_CHIP_R580_724A              0x724A
+#define PCI_CHIP_R580_724B              0x724B
+#define PCI_CHIP_R580_724C              0x724C
+#define PCI_CHIP_R580_724D              0x724D
+#define PCI_CHIP_R580_724E              0x724E
+#define PCI_CHIP_R580_724F              0x724F
+#define PCI_CHIP_RV570_7280             0x7280
+#define PCI_CHIP_RV560_7281             0x7281
+#define PCI_CHIP_RV560_7283             0x7283
+#define PCI_CHIP_R580_7284              0x7284
+#define PCI_CHIP_RV560_7287             0x7287
+#define PCI_CHIP_RV570_7288             0x7288
+#define PCI_CHIP_RV570_7289             0x7289
+#define PCI_CHIP_RV570_728B             0x728B
+#define PCI_CHIP_RV570_728C             0x728C
+#define PCI_CHIP_RV560_7290             0x7290
+#define PCI_CHIP_RV560_7291             0x7291
+#define PCI_CHIP_RV560_7293             0x7293
+#define PCI_CHIP_RV560_7297             0x7297
 
 #define PCI_CHIP_RS350_7834		0x7834
 #define PCI_CHIP_RS350_7835		0x7835
 #define PCI_CHIP_RS690_791E             0x791E
 #define PCI_CHIP_RS690_791F             0x791F
+#define PCI_CHIP_RS740_796C             0x796C
+#define PCI_CHIP_RS740_796D             0x796D
+#define PCI_CHIP_RS740_796E             0x796E
+#define PCI_CHIP_RS740_796F             0x796F
+
 
 enum {
    CHIP_FAMILY_R100,
@@ -172,8 +271,13 @@ enum {
    CHIP_FAMILY_RV410,
    CHIP_FAMILY_RS400,
    CHIP_FAMILY_RS690,
+   CHIP_FAMILY_RS740,
    CHIP_FAMILY_RV515,
    CHIP_FAMILY_R520,
+   CHIP_FAMILY_RV530,
+   CHIP_FAMILY_R580,
+   CHIP_FAMILY_RV560,
+   CHIP_FAMILY_RV570,
    CHIP_FAMILY_LAST
 };
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 1a1666ccfe..6f9d912442 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -682,15 +682,133 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
       break;
 
    case PCI_CHIP_RS690_791E:
+   case PCI_CHIP_RS690_791F:
       screen->chip_family = CHIP_FAMILY_RS690;
       fprintf(stderr, "Warning, RS690 detected, 3D support is incomplete.\n");
       break;
+   case PCI_CHIP_RS740_796C:
+   case PCI_CHIP_RS740_796D:
+   case PCI_CHIP_RS740_796E:
+   case PCI_CHIP_RS740_796F:
+      screen->chip_family = CHIP_FAMILY_RS740;
+      fprintf(stderr, "Warning, RS740 detected, 3D support is incomplete.\n");
+      break;
 
-   case PCI_CHIP_RV530_71C4:
+   case PCI_CHIP_R520_7100:
+   case PCI_CHIP_R520_7101:
+   case PCI_CHIP_R520_7102:
+   case PCI_CHIP_R520_7103:
+   case PCI_CHIP_R520_7104:
+   case PCI_CHIP_R520_7105:
+   case PCI_CHIP_R520_7106:
+   case PCI_CHIP_R520_7108:
+   case PCI_CHIP_R520_7109:
+   case PCI_CHIP_R520_710A:
+   case PCI_CHIP_R520_710B:
+   case PCI_CHIP_R520_710C:
+   case PCI_CHIP_R520_710E:
+   case PCI_CHIP_R520_710F:
       screen->chip_family = CHIP_FAMILY_R520;
       fprintf(stderr, "Warning, R520 detected, 3D HAHAHAHAHA!!.\n");
       break;
 
+   case PCI_CHIP_RV515_7140:
+   case PCI_CHIP_RV515_7141:
+   case PCI_CHIP_RV515_7142:
+   case PCI_CHIP_RV515_7143:
+   case PCI_CHIP_RV515_7144:
+   case PCI_CHIP_RV515_7145:
+   case PCI_CHIP_RV515_7146:
+   case PCI_CHIP_RV515_7147:
+   case PCI_CHIP_RV515_7149:
+   case PCI_CHIP_RV515_714A:
+   case PCI_CHIP_RV515_714B:
+   case PCI_CHIP_RV515_714C:
+   case PCI_CHIP_RV515_714D:
+   case PCI_CHIP_RV515_714E:
+   case PCI_CHIP_RV515_714F:
+   case PCI_CHIP_RV515_7151:
+   case PCI_CHIP_RV515_7152:
+   case PCI_CHIP_RV515_7153:
+   case PCI_CHIP_RV515_715E:
+   case PCI_CHIP_RV515_715F:
+   case PCI_CHIP_RV515_7180:
+   case PCI_CHIP_RV515_7181:
+   case PCI_CHIP_RV515_7183:
+   case PCI_CHIP_RV515_7186:
+   case PCI_CHIP_RV515_7187:
+   case PCI_CHIP_RV515_7188:
+   case PCI_CHIP_RV515_718A:
+   case PCI_CHIP_RV515_718B:
+   case PCI_CHIP_RV515_718C:
+   case PCI_CHIP_RV515_718D:
+   case PCI_CHIP_RV515_718F:
+   case PCI_CHIP_RV515_7193:
+   case PCI_CHIP_RV515_7196:
+   case PCI_CHIP_RV515_719B:
+   case PCI_CHIP_RV515_719F:
+   case PCI_CHIP_RV515_7200:
+   case PCI_CHIP_RV515_7210:
+   case PCI_CHIP_RV515_7211:
+      screen->chip_family = CHIP_FAMILY_RV515;
+      fprintf(stderr, "Warning, RV515 detected, 3D HAHAHAHAHA!!.\n");
+      break;
+
+   case PCI_CHIP_RV530_71C0:
+   case PCI_CHIP_RV530_71C1:
+   case PCI_CHIP_RV530_71C2:
+   case PCI_CHIP_RV530_71C3:
+   case PCI_CHIP_RV530_71C4:
+   case PCI_CHIP_RV530_71C5:
+   case PCI_CHIP_RV530_71C6:
+   case PCI_CHIP_RV530_71C7:
+   case PCI_CHIP_RV530_71CD:
+   case PCI_CHIP_RV530_71CE:
+   case PCI_CHIP_RV530_71D2:
+   case PCI_CHIP_RV530_71D4:
+   case PCI_CHIP_RV530_71D5:
+   case PCI_CHIP_RV530_71D6:
+   case PCI_CHIP_RV530_71DA:
+   case PCI_CHIP_RV530_71DE:
+      screen->chip_family = CHIP_FAMILY_RV530;
+      fprintf(stderr, "Warning, RV530 detected, 3D HAHAHAHAHA!!.\n");
+      break;
+
+   case PCI_CHIP_R580_7240:
+   case PCI_CHIP_R580_7243:
+   case PCI_CHIP_R580_7244:
+   case PCI_CHIP_R580_7245:
+   case PCI_CHIP_R580_7246:
+   case PCI_CHIP_R580_7247:
+   case PCI_CHIP_R580_7248:
+   case PCI_CHIP_R580_7249:
+   case PCI_CHIP_R580_724A:
+   case PCI_CHIP_R580_724B:
+   case PCI_CHIP_R580_724C:
+   case PCI_CHIP_R580_724D:
+   case PCI_CHIP_R580_724E:
+   case PCI_CHIP_R580_724F:
+   case PCI_CHIP_R580_7284:
+      screen->chip_family = CHIP_FAMILY_R580;
+      fprintf(stderr, "Warning, R580 detected, 3D HAHAHAHAHA!!.\n");
+      break;
+
+   case PCI_CHIP_RV570_7280:
+   case PCI_CHIP_RV560_7281:
+   case PCI_CHIP_RV560_7283:
+   case PCI_CHIP_RV560_7287:
+   case PCI_CHIP_RV570_7288:
+   case PCI_CHIP_RV570_7289:
+   case PCI_CHIP_RV570_728B:
+   case PCI_CHIP_RV570_728C:
+   case PCI_CHIP_RV560_7290:
+   case PCI_CHIP_RV560_7291:
+   case PCI_CHIP_RV560_7293:
+   case PCI_CHIP_RV560_7297:
+      screen->chip_family = CHIP_FAMILY_RV560;
+      fprintf(stderr, "Warning, RV560 detected, 3D HAHAHAHAHA!!.\n");
+      break;
+
    default:
       fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
 	      dri_priv->deviceID);
-- 
cgit v1.2.3


From e3721a3b3fca5ad7d957ae95252405da0740fbf6 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alex@botch2.com>
Date: Fri, 2 May 2008 10:51:40 -0400
Subject: R5xx: various updates

- fixup VAP_CNTL setup
- remove extra instruction in r5xx passthrough shader
- add notes about pipe config
---
 src/mesa/drivers/dri/r300/r300_reg.h        |  9 +++-
 src/mesa/drivers/dri/r300/r300_state.c      | 71 ++++++++++++++++-------------
 src/mesa/drivers/dri/radeon/radeon_screen.c |  9 +++-
 3 files changed, 56 insertions(+), 33 deletions(-)

(limited to 'src/mesa/drivers/dri/r300/r300_state.c')

diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h
index 2822b1d4c3..fee21dae67 100644
--- a/src/mesa/drivers/dri/r300/r300_reg.h
+++ b/src/mesa/drivers/dri/r300/r300_reg.h
@@ -70,6 +70,13 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
  * Stolen from r200 code from Christoph Brill (It's a guess!)
  */
 #define R300_VAP_CNTL	0x2080
+#       define R300_PVS_NUM_SLOTS_SHIFT                 0
+#       define R300_PVS_NUM_CNTLRS_SHIFT                4
+#       define R300_PVS_NUM_FPUS_SHIFT                  8
+#       define R300_VF_MAX_VTX_NUM_SHIFT                18
+#       define R300_GL_CLIP_SPACE_DEF                   (0 << 22)
+#       define R300_DX_CLIP_SPACE_DEF                   (1 << 22)
+#       define R500_TCL_STATE_OPTIMIZATION              (1 << 23)
 
 /* This register is written directly and also starts data section
  * in many 3d CP_PACKET3's
@@ -375,7 +382,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define R300_VAP_CLIP_CNTL                       0x221C
 #       define R300_221C_NORMAL                  0x00000000
 #       define R300_221C_CLEAR                   0x0001C000
-#define R300_VAP_UCP_ENABLE_0 (1 << 0)
+#       define R300_VAP_UCP_ENABLE_0 (1 << 0)
 
 /* These seem to be per-pixel and per-vertex X and Y clipping planes. The first
  * plane is per-pixel and the second plane is per-vertex.
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index 7419b15a55..0740d7ea4a 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -1981,10 +1981,34 @@ static void r300ResetHwState(r300ContextPtr r300)
 	r300AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
 	r300Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
 
-	if (!has_tcl)
-		r300->hw.vap_cntl.cmd[1] = 0x0014045a;
+	/* setup the VAP */
+	/* PVS_NUM_SLOTS, PVS_NUM_CNTLRS, VF_MAX_VTX_NUM need to be adjusted
+	 * dynamically.  PVS_NUM_FPUS is fixed based on asic
+	 */
+	if (has_tcl) {
+	    r300->hw.vap_cntl.cmd[1] = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
+					(5 << R300_PVS_NUM_CNTLRS_SHIFT) |
+					(12 << R300_VF_MAX_VTX_NUM_SHIFT));
+	    if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
+		r300->hw.vap_cntl.cmd[1] |= R500_TCL_STATE_OPTIMIZATION;
+	} else
+	    r300->hw.vap_cntl.cmd[1] = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
+					(5 << R300_PVS_NUM_CNTLRS_SHIFT) |
+					(5 << R300_VF_MAX_VTX_NUM_SHIFT));
+
+	if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515)
+	    r300->hw.vap_cntl.cmd[1] |= (2 << R300_PVS_NUM_FPUS_SHIFT);
+	else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) ||
+		 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560))
+	    r300->hw.vap_cntl.cmd[1] |= (5 << R300_PVS_NUM_FPUS_SHIFT);
+	else if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420)
+	    r300->hw.vap_cntl.cmd[1] |= (6 << R300_PVS_NUM_FPUS_SHIFT);
+	else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) ||
+		 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580) ||
+		 (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570))
+	    r300->hw.vap_cntl.cmd[1] |= (8 << R300_PVS_NUM_FPUS_SHIFT);
 	else
-		r300->hw.vap_cntl.cmd[1] = 0x0030045A;	//0x0030065a /* Dangerous */
+	    r300->hw.vap_cntl.cmd[1] |= (4 << R300_PVS_NUM_FPUS_SHIFT);
 
 	r300->hw.vte.cmd[1] = R300_VPORT_X_SCALE_ENA
 	    | R300_VPORT_X_OFFSET_ENA
@@ -2035,20 +2059,27 @@ static void r300ResetHwState(r300ContextPtr r300)
 	r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_0] = 0x66666666;
 	r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_1] = 0x06666666;
 
-	/* XXX: Other families? */
+	/* num pipes needs to be read back from the GB_PIPE_SELECT register
+	 * on r4xx/r5xx/rs4xx/rs6xx
+	 * should move this to the drm
+	 */
 	r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] =
-	    R300_GB_TILE_ENABLE | R300_GB_TILE_SIZE_16;
+	    R300_GB_TILE_ENABLE | R300_GB_TILE_SIZE_16 /*| R300_GB_SUBPIXEL_1_16*/;
 	switch (r300->radeon.radeonScreen->chip_family) {
 	case CHIP_FAMILY_R300:
 	case CHIP_FAMILY_R350:
-	case CHIP_FAMILY_RV410:
 		r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
 		    R300_GB_TILE_PIPE_COUNT_R300;
 		break;
-	case CHIP_FAMILY_R420:
+	case CHIP_FAMILY_RV350:
 	case CHIP_FAMILY_RV515:
-	case CHIP_FAMILY_R520:
 	case CHIP_FAMILY_RV530:
+	case CHIP_FAMILY_RV410:
+		r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
+		    R300_GB_TILE_PIPE_COUNT_RV300;
+		break;
+	case CHIP_FAMILY_R420:
+	case CHIP_FAMILY_R520:
 	case CHIP_FAMILY_R580:
 	case CHIP_FAMILY_RV560:
 	case CHIP_FAMILY_RV570:
@@ -2329,28 +2360,6 @@ static void r500SetupPixelShader(r300ContextPtr rmesa)
 	/* emit the standard zero shader */
 	R300_STATECHANGE(rmesa, r500fp);
 	i = 1;
-	rmesa->hw.r500fp.cmd[i++] = 0x7808;
-	rmesa->hw.r500fp.cmd[i++] = R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED;
-	rmesa->hw.r500fp.cmd[i++] = R500_TEX_SRC_ADDR(0) |  R500_TEX_SRC_S_SWIZ_R |
-		R500_TEX_SRC_T_SWIZ_G |
-		R500_TEX_DST_ADDR(0) |
-		R500_TEX_DST_R_SWIZ_R |
-		R500_TEX_DST_G_SWIZ_G |
-		R500_TEX_DST_B_SWIZ_B |
-		R500_TEX_DST_A_SWIZ_A;
-	rmesa->hw.r500fp.cmd[i++] = R500_DX_ADDR(0) |
-		R500_DX_S_SWIZ_R |
-		R500_DX_T_SWIZ_R |
-		R500_DX_R_SWIZ_R |
-		R500_DX_Q_SWIZ_R |
-		R500_DY_ADDR(0) |
-		R500_DY_S_SWIZ_R |
-		R500_DY_T_SWIZ_R |
-		R500_DY_R_SWIZ_R |
-		R500_DY_Q_SWIZ_R;
-	rmesa->hw.r500fp.cmd[i++] = 0x0;
-	rmesa->hw.r500fp.cmd[i++] = 0x0;
-
 	rmesa->hw.r500fp.cmd[i++] = R500_INST_TYPE_OUT |
 		R500_INST_TEX_SEM_WAIT |
 		R500_INST_LAST |
@@ -2388,7 +2397,7 @@ static void r500SetupPixelShader(r300ContextPtr rmesa)
 		R500_ALU_RGBA_B_SWIZ_0 |
 		R500_ALU_RGBA_A_SWIZ_0;
 
-	bump_r500fp_count(rmesa->hw.r500fp.cmd, 12);
+	bump_r500fp_count(rmesa->hw.r500fp.cmd, 6);
 
 	R300_STATECHANGE(rmesa, r500fp_const);
 	for (i = 0; i < fp->const_nr; i++) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 6f9d912442..2f57d289fe 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -649,7 +649,9 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
       screen->chip_flags = RADEON_CHIPSET_TCL;
       break;
 
-   /* RV410 SE chips have half the pipes of regular RV410 */
+      /* RV410 SE chips have half the pipes of regular RV410
+       * Need to get num pipes form the GB_PIPE_SELECT register
+       */
    case PCI_CHIP_RV410_5E4C:
    case PCI_CHIP_RV410_5E4F:
       screen->chip_family = CHIP_FAMILY_RV380;
@@ -709,6 +711,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
    case PCI_CHIP_R520_710E:
    case PCI_CHIP_R520_710F:
       screen->chip_family = CHIP_FAMILY_R520;
+      //screen->chip_flags = RADEON_CHIPSET_TCL;
       fprintf(stderr, "Warning, R520 detected, 3D HAHAHAHAHA!!.\n");
       break;
 
@@ -751,6 +754,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
    case PCI_CHIP_RV515_7210:
    case PCI_CHIP_RV515_7211:
       screen->chip_family = CHIP_FAMILY_RV515;
+      //screen->chip_flags = RADEON_CHIPSET_TCL;
       fprintf(stderr, "Warning, RV515 detected, 3D HAHAHAHAHA!!.\n");
       break;
 
@@ -771,6 +775,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
    case PCI_CHIP_RV530_71DA:
    case PCI_CHIP_RV530_71DE:
       screen->chip_family = CHIP_FAMILY_RV530;
+      //screen->chip_flags = RADEON_CHIPSET_TCL;
       fprintf(stderr, "Warning, RV530 detected, 3D HAHAHAHAHA!!.\n");
       break;
 
@@ -790,6 +795,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
    case PCI_CHIP_R580_724F:
    case PCI_CHIP_R580_7284:
       screen->chip_family = CHIP_FAMILY_R580;
+      //screen->chip_flags = RADEON_CHIPSET_TCL;
       fprintf(stderr, "Warning, R580 detected, 3D HAHAHAHAHA!!.\n");
       break;
 
@@ -806,6 +812,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
    case PCI_CHIP_RV560_7293:
    case PCI_CHIP_RV560_7297:
       screen->chip_family = CHIP_FAMILY_RV560;
+      //screen->chip_flags = RADEON_CHIPSET_TCL;
       fprintf(stderr, "Warning, RV560 detected, 3D HAHAHAHAHA!!.\n");
       break;
 
-- 
cgit v1.2.3


From 2bd26f4afa4f87d3dd2a8b9715455fc3f5a05046 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alex@botch2.com>
Date: Fri, 2 May 2008 10:54:20 -0400
Subject: Update comment

---
 src/mesa/drivers/dri/r300/r300_state.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/r300/r300_state.c')

diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index 0740d7ea4a..57ff9e9a73 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -1982,7 +1982,7 @@ static void r300ResetHwState(r300ContextPtr r300)
 	r300Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
 
 	/* setup the VAP */
-	/* PVS_NUM_SLOTS, PVS_NUM_CNTLRS, VF_MAX_VTX_NUM need to be adjusted
+	/* for tcl, PVS_NUM_SLOTS, PVS_NUM_CNTLRS, VF_MAX_VTX_NUM need to be adjusted
 	 * dynamically.  PVS_NUM_FPUS is fixed based on asic
 	 */
 	if (has_tcl) {
-- 
cgit v1.2.3


From d5448ceb956d1884bf7aac4667b79a0905fa4166 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alex@botch2.com>
Date: Fri, 2 May 2008 12:48:39 -0400
Subject: R300: cleanup VAP_CLIP_CNTL

---
 src/mesa/drivers/dri/r300/r300_ioctl.c |  2 +-
 src/mesa/drivers/dri/r300/r300_reg.h   | 18 +++++++++++++++---
 src/mesa/drivers/dri/r300/r300_state.c |  2 +-
 3 files changed, 17 insertions(+), 5 deletions(-)

(limited to 'src/mesa/drivers/dri/r300/r300_state.c')

diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c
index 0fef1c61a7..03449de934 100644
--- a/src/mesa/drivers/dri/r300/r300_ioctl.c
+++ b/src/mesa/drivers/dri/r300/r300_ioctl.c
@@ -283,7 +283,7 @@ static void r300EmitClearState(GLcontext * ctx)
 	if (has_tcl) {
 	    R300_STATECHANGE(r300, vap_clip_cntl);
 	    reg_start(R300_VAP_CLIP_CNTL, 0);
-	    e32(R300_221C_CLEAR);
+	    e32(R300_PS_UCP_MODE_CLIP_AS_TRIFAN | R300_CLIP_DISABLE);
         }
 
 	R300_STATECHANGE(r300, ps);
diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h
index f65aac3ca4..7b71eeab93 100644
--- a/src/mesa/drivers/dri/r300/r300_reg.h
+++ b/src/mesa/drivers/dri/r300/r300_reg.h
@@ -398,9 +398,21 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
  * See bug #9871. http://bugs.freedesktop.org/attachment.cgi?id=10672&action=view
  */
 #define R300_VAP_CLIP_CNTL                       0x221C
-#       define R300_221C_NORMAL                  0x00000000
-#       define R300_221C_CLEAR                   0x0001C000
-#       define R300_VAP_UCP_ENABLE_0 (1 << 0)
+#       define R300_VAP_UCP_ENABLE_0             (1 << 0)
+#       define R300_VAP_UCP_ENABLE_1             (1 << 1)
+#       define R300_VAP_UCP_ENABLE_2             (1 << 2)
+#       define R300_VAP_UCP_ENABLE_3             (1 << 3)
+#       define R300_VAP_UCP_ENABLE_4             (1 << 4)
+#       define R300_VAP_UCP_ENABLE_5             (1 << 5)
+#       define R300_PS_UCP_MODE_DIST_COP         (0 << 14)
+#       define R300_PS_UCP_MODE_RADIUS_COP       (1 << 14)
+#       define R300_PS_UCP_MODE_RADIUS_COP_CLIP  (2 << 14)
+#       define R300_PS_UCP_MODE_CLIP_AS_TRIFAN   (3 << 14)
+#       define R300_CLIP_DISABLE                 (1 << 16)
+#       define R300_UCP_CULL_ONLY_ENABLE         (1 << 17)
+#       define R300_BOUNDARY_EDGE_FLAG_ENABLE    (1 << 18)
+#       define R500_COLOR2_IS_TEXTURE            (1 << 20)
+#       define R500_COLOR3_IS_TEXTURE            (1 << 21)
 
 /* These seem to be per-pixel and per-vertex X and Y clipping planes. The first
  * plane is per-pixel and the second plane is per-vertex.
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index 57ff9e9a73..27615fd568 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -2035,7 +2035,7 @@ static void r300ResetHwState(r300ContextPtr r300)
 
 	/* XXX: Other families? */
 	if (has_tcl) {
-		r300->hw.vap_clip_cntl.cmd[1] = R300_221C_NORMAL;
+		r300->hw.vap_clip_cntl.cmd[1] = R300_PS_UCP_MODE_DIST_COP;
 
 		r300->hw.vap_clip.cmd[1] = r300PackFloat32(1.0); /* X */
 		r300->hw.vap_clip.cmd[2] = r300PackFloat32(1.0); /* X */
-- 
cgit v1.2.3


From 9e7ae34da5aeb9a38c3f4280f6d9648faad48df5 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alex@botch2.com>
Date: Fri, 2 May 2008 13:56:56 -0400
Subject: R3/4/5: fix TCL on r5xx, cleanup PVS code

---
 src/mesa/drivers/dri/r300/r300_cmdbuf.c     | 30 ++++++-----
 src/mesa/drivers/dri/r300/r300_ioctl.c      |  4 +-
 src/mesa/drivers/dri/r300/r300_reg.h        | 77 ++++++++++++++++-------------
 src/mesa/drivers/dri/r300/r300_state.c      |  4 +-
 src/mesa/drivers/dri/radeon/radeon_screen.c | 10 ++--
 5 files changed, 72 insertions(+), 53 deletions(-)

(limited to 'src/mesa/drivers/dri/r300/r300_state.c')

diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index d0ce401ed6..5d6be48f76 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -333,7 +333,7 @@ void r300InitCmdBuf(r300ContextPtr r300)
 	r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
 	    cmdpacket0(R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
 	ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
-	r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(R300_VAP_INPUT_CNTL_0, 2);
+	r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(R300_VAP_VTX_STATE_CNTL, 2);
 	ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
 	r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
 
@@ -481,27 +481,35 @@ void r300InitCmdBuf(r300ContextPtr r300)
    	        int i;
 		ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
 		r300->hw.vpi.cmd[R300_VPI_CMD_0] =
-		    cmdvpu(R300_PVS_UPLOAD_PROGRAM, 0);
+		    cmdvpu(R300_PVS_CODE_START, 0);
 
-		ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
-		r300->hw.vpp.cmd[R300_VPP_CMD_0] =
-		    cmdvpu(R300_PVS_UPLOAD_PARAMETERS, 0);
+		if (is_r500) {
+		    ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
+		    r300->hw.vpp.cmd[R300_VPP_CMD_0] =
+			cmdvpu(R500_PVS_CONST_START, 0);
 
-		ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
-		r300->hw.vps.cmd[R300_VPS_CMD_0] =
-		    cmdvpu(R300_PVS_UPLOAD_POINTSIZE, 1);
+		    ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
+		    r300->hw.vps.cmd[R300_VPS_CMD_0] =
+			cmdvpu(R500_POINT_VPORT_SCALE_OFFSET, 1);
 
-		if (is_r500) {
 			for (i = 0; i < 6; i++) {
 				ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 				r300->hw.vpucp[i].cmd[R300_VPUCP_CMD_0] =
-					cmdvpu(R500_PVS_UPLOAD_CLIP_PLANE0+i, 1);
+					cmdvpu(R500_PVS_UCP_START + i, 1);
 			}
 		} else {
+		    ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
+		    r300->hw.vpp.cmd[R300_VPP_CMD_0] =
+			cmdvpu(R300_PVS_CONST_START, 0);
+
+		    ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
+		    r300->hw.vps.cmd[R300_VPS_CMD_0] =
+			cmdvpu(R300_POINT_VPORT_SCALE_OFFSET, 1);
+
 			for (i = 0; i < 6; i++) {
 				ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 				r300->hw.vpucp[i].cmd[R300_VPUCP_CMD_0] =
-					cmdvpu(R300_PVS_UPLOAD_CLIP_PLANE0+i, 1);
+					cmdvpu(R300_PVS_UCP_START + i, 1);
 			}
 		}
 	}
diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c
index 03449de934..530c3711d9 100644
--- a/src/mesa/drivers/dri/r300/r300_ioctl.c
+++ b/src/mesa/drivers/dri/r300/r300_ioctl.c
@@ -236,8 +236,8 @@ static void r300EmitClearState(GLcontext * ctx)
 
 	/* R300_VAP_INPUT_CNTL_0, R300_VAP_INPUT_CNTL_1 */
 	R300_STATECHANGE(r300, vic);
-	reg_start(R300_VAP_INPUT_CNTL_0, 1);
-	e32(R300_INPUT_CNTL_0_COLOR);
+	reg_start(R300_VAP_VTX_STATE_CNTL, 1);
+	e32((R300_SEL_USER_COLOR_0 << R300_COLOR_0_ASSEMBLY_SHIFT));
 	e32(R300_INPUT_CNTL_POS | R300_INPUT_CNTL_COLOR | R300_INPUT_CNTL_TC0);
 
 	R300_STATECHANGE(r300, vte);
diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h
index 81b5c3faf3..a6719d6553 100644
--- a/src/mesa/drivers/dri/r300/r300_reg.h
+++ b/src/mesa/drivers/dri/r300/r300_reg.h
@@ -139,17 +139,16 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #	define R300_VAP_OUTPUT_VTX_FMT_1__4_COMPONENTS 4
 
 #define R300_SE_VTE_CNTL                  0x20b0
-#	define     R300_VPORT_X_SCALE_ENA                0x00000001
-#	define     R300_VPORT_X_OFFSET_ENA               0x00000002
-#	define     R300_VPORT_Y_SCALE_ENA                0x00000004
-#	define     R300_VPORT_Y_OFFSET_ENA               0x00000008
-#	define     R300_VPORT_Z_SCALE_ENA                0x00000010
-#	define     R300_VPORT_Z_OFFSET_ENA               0x00000020
-#	define     R300_VTX_XY_FMT                       0x00000100
-#	define     R300_VTX_Z_FMT                        0x00000200
-#	define     R300_VTX_W0_FMT                       0x00000400
-#	define     R300_VTX_W0_NORMALIZE                 0x00000800
-#	define     R300_VTX_ST_DENORMALIZED              0x00001000
+#	define     R300_VPORT_X_SCALE_ENA                (1 << 0)
+#	define     R300_VPORT_X_OFFSET_ENA               (1 << 1)
+#	define     R300_VPORT_Y_SCALE_ENA                (1 << 2)
+#	define     R300_VPORT_Y_OFFSET_ENA               (1 << 3)
+#	define     R300_VPORT_Z_SCALE_ENA                (1 << 4)
+#	define     R300_VPORT_Z_OFFSET_ENA               (1 << 5)
+#	define     R300_VTX_XY_FMT                       (1 << 8)
+#	define     R300_VTX_Z_FMT                        (1 << 9)
+#	define     R300_VTX_W0_FMT                       (1 << 10)
+#	define     R300_SERIAL_PROC_ENA                  (1 << 11)
 
 /* BEGIN: Vertex data assembly - lots of uncertainties */
 
@@ -250,9 +249,26 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
  *    if vertex program uses only position, fglrx will set normal, too
  *  - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal.
  */
-#define R300_VAP_INPUT_CNTL_0               0x2180
-#       define R300_INPUT_CNTL_0_COLOR           0x00000001
-#define R300_VAP_INPUT_CNTL_1               0x2184
+#define R300_VAP_VTX_STATE_CNTL               0x2180
+#       define R300_COLOR_0_ASSEMBLY_SHIFT    0
+#       define R300_SEL_COLOR                 0
+#       define R300_SEL_USER_COLOR_0          1
+#       define R300_SEL_USER_COLOR_1          2
+#       define R300_COLOR_1_ASSEMBLY_SHIFT    2
+#       define R300_COLOR_2_ASSEMBLY_SHIFT    4
+#       define R300_COLOR_3_ASSEMBLY_SHIFT    6
+#       define R300_COLOR_4_ASSEMBLY_SHIFT    8
+#       define R300_COLOR_5_ASSEMBLY_SHIFT    10
+#       define R300_COLOR_6_ASSEMBLY_SHIFT    12
+#       define R300_COLOR_7_ASSEMBLY_SHIFT    14
+#       define R300_UPDATE_USER_COLOR_0_ENA   (1 << 16)
+
+/*
+ * Each bit in this field applies to the corresponding vector in the VSM
+ * memory (i.e. Bit 0 applies to VECTOR_0 (POSITION), etc.). If the bit
+ * is set, then the corresponding 4-Dword Vector is output into the Vertex Stream.
+ */
+#define R300_VAP_VSM_VTX_ASSM               0x2184
 #       define R300_INPUT_CNTL_POS               0x00000001
 #       define R300_INPUT_CNTL_NORMAL            0x00000002
 #       define R300_INPUT_CNTL_COLOR             0x00000004
@@ -345,25 +361,20 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
  * Multiple vertex programs and parameter sets can be loaded at once,
  * which could explain the size discrepancy.
  */
-#define R300_VAP_PVS_UPLOAD_ADDRESS         0x2200
-#       define R300_PVS_UPLOAD_PROGRAM           0x00000000
-/* gap */
-#       define R300_PVS_UPLOAD_PARAMETERS        0x00000200
-/* gap */
-#       define R300_PVS_UPLOAD_CLIP_PLANE0       0x00000400
-#       define R300_PVS_UPLOAD_CLIP_PLANE1       0x00000401
-#       define R300_PVS_UPLOAD_CLIP_PLANE2       0x00000402
-#       define R300_PVS_UPLOAD_CLIP_PLANE3       0x00000403
-#       define R300_PVS_UPLOAD_CLIP_PLANE4       0x00000404
-#       define R300_PVS_UPLOAD_CLIP_PLANE5       0x00000405
-#       define R300_PVS_UPLOAD_POINTSIZE         0x00000406
-
-#       define R500_PVS_UPLOAD_CLIP_PLANE0       0x00000600
-#       define R500_PVS_UPLOAD_CLIP_PLANE1       0x00000601
-#       define R500_PVS_UPLOAD_CLIP_PLANE2       0x00000602
-#       define R500_PVS_UPLOAD_CLIP_PLANE3       0x00000603
-#       define R500_PVS_UPLOAD_CLIP_PLANE4       0x00000604
-#       define R500_PVS_UPLOAD_CLIP_PLANE5       0x00000605
+#define R300_VAP_PVS_VECTOR_INDX_REG         0x2200
+#       define R300_PVS_CODE_START           0
+#       define R300_MAX_PVS_CODE_LINES       256
+#       define R500_MAX_PVS_CODE_LINES       1024
+#       define R300_PVS_CONST_START          512
+#       define R500_PVS_CONST_START          1024
+#       define R300_MAX_PVS_CONST_VECS       256
+#       define R500_MAX_PVS_CONST_VECS       1024
+#       define R300_PVS_UCP_START            1024
+#       define R500_PVS_UCP_START            1536
+#       define R300_POINT_VPORT_SCALE_OFFSET 1030
+#       define R500_POINT_VPORT_SCALE_OFFSET 1542
+#       define R300_POINT_GEN_TEX_OFFSET     1031
+#       define R500_POINT_GEN_TEX_OFFSET     1543
 
 /*
  * These are obsolete defines form r300_context.h, but they might give some
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index 27615fd568..89a0827b2f 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -1802,7 +1802,7 @@ static void r300SetupDefaultVertexProgram(r300ContextPtr rmesa)
 
 	prog->program.length = program_end;
 
-	r300SetupVertexProgramFragment(rmesa, R300_PVS_UPLOAD_PROGRAM,
+	r300SetupVertexProgramFragment(rmesa, R300_PVS_CODE_START,
 				       &(prog->program));
 	inst_count = (prog->program.length / 4) - 1;
 
@@ -1837,7 +1837,7 @@ static void r300SetupRealVertexProgram(r300ContextPtr rmesa)
 	bump_vpu_count(rmesa->hw.vpp.cmd, param_count);
 	param_count /= 4;
 
-	r300SetupVertexProgramFragment(rmesa, R300_PVS_UPLOAD_PROGRAM, &(prog->program));
+	r300SetupVertexProgramFragment(rmesa, R300_PVS_CODE_START, &(prog->program));
 	inst_count = (prog->program.length / 4) - 1;
 
 	R300_STATECHANGE(rmesa, pvs);
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 2f57d289fe..0f716a0b70 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -711,7 +711,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
    case PCI_CHIP_R520_710E:
    case PCI_CHIP_R520_710F:
       screen->chip_family = CHIP_FAMILY_R520;
-      //screen->chip_flags = RADEON_CHIPSET_TCL;
+      screen->chip_flags = RADEON_CHIPSET_TCL;
       fprintf(stderr, "Warning, R520 detected, 3D HAHAHAHAHA!!.\n");
       break;
 
@@ -754,7 +754,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
    case PCI_CHIP_RV515_7210:
    case PCI_CHIP_RV515_7211:
       screen->chip_family = CHIP_FAMILY_RV515;
-      //screen->chip_flags = RADEON_CHIPSET_TCL;
+      screen->chip_flags = RADEON_CHIPSET_TCL;
       fprintf(stderr, "Warning, RV515 detected, 3D HAHAHAHAHA!!.\n");
       break;
 
@@ -775,7 +775,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
    case PCI_CHIP_RV530_71DA:
    case PCI_CHIP_RV530_71DE:
       screen->chip_family = CHIP_FAMILY_RV530;
-      //screen->chip_flags = RADEON_CHIPSET_TCL;
+      screen->chip_flags = RADEON_CHIPSET_TCL;
       fprintf(stderr, "Warning, RV530 detected, 3D HAHAHAHAHA!!.\n");
       break;
 
@@ -795,7 +795,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
    case PCI_CHIP_R580_724F:
    case PCI_CHIP_R580_7284:
       screen->chip_family = CHIP_FAMILY_R580;
-      //screen->chip_flags = RADEON_CHIPSET_TCL;
+      screen->chip_flags = RADEON_CHIPSET_TCL;
       fprintf(stderr, "Warning, R580 detected, 3D HAHAHAHAHA!!.\n");
       break;
 
@@ -812,7 +812,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
    case PCI_CHIP_RV560_7293:
    case PCI_CHIP_RV560_7297:
       screen->chip_family = CHIP_FAMILY_RV560;
-      //screen->chip_flags = RADEON_CHIPSET_TCL;
+      screen->chip_flags = RADEON_CHIPSET_TCL;
       fprintf(stderr, "Warning, RV560 detected, 3D HAHAHAHAHA!!.\n");
       break;
 
-- 
cgit v1.2.3


From 37924cf175b5f61ca85dab685ec5d7879519ebc4 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Sat, 3 May 2008 22:08:11 +1000
Subject: r300: update r300 rs unit for swtcl need to fix r500 most likely

---
 src/mesa/drivers/dri/r300/r300_state.c | 74 ++++++++++++++++++++++++----------
 1 file changed, 52 insertions(+), 22 deletions(-)

(limited to 'src/mesa/drivers/dri/r300/r300_state.c')

diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index 89a0827b2f..4fc50b8494 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -1491,21 +1491,17 @@ static void r300SetupRSUnit(GLcontext * ctx)
 {
 	r300ContextPtr r300 = R300_CONTEXT(ctx);
 	/* I'm still unsure if these are needed */
-	GLuint interp_magic[8] = {
-		0x00,
-		R300_RS_COL_PTR(1),
-		R300_RS_COL_PTR(2),
-		R300_RS_COL_PTR(3),
-		0x00,
-		0x00,
-		0x00,
-		0x00
-	};
+	GLuint interp_col[8];
+        TNLcontext *tnl = TNL_CONTEXT(ctx);
+	struct vertex_buffer *VB = &tnl->vb;
 	union r300_outputs_written OutputsWritten;
 	GLuint InputsRead;
 	int fp_reg, high_rr;
-	int in_texcoords, col_interp_nr;
-	int i;
+	int col_interp_nr;
+	int rs_tex_count = 0, rs_col_count = 0;
+	int i, count;
+
+	memset(interp_col, 0, 8);
 
 	if (hw_tcl_on)
 		OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten;
@@ -1523,7 +1519,7 @@ static void r300SetupRSUnit(GLcontext * ctx)
 	R300_STATECHANGE(r300, rc);
 	R300_STATECHANGE(r300, rr);
 
-	fp_reg = in_texcoords = col_interp_nr = high_rr = 0;
+	fp_reg = col_interp_nr = high_rr = 0;
 
 	r300->hw.rr.cmd[R300_RR_INST_1] = 0;
 
@@ -1541,12 +1537,50 @@ static void r300SetupRSUnit(GLcontext * ctx)
 		InputsRead &= ~FRAG_BIT_WPOS;
 	}
 
+	if (InputsRead & FRAG_BIT_COL0) {
+		count = VB->AttribPtr[_TNL_ATTRIB_COLOR0]->size;
+		interp_col[0] |= R300_RS_COL_PTR(rs_col_count);
+		if (count == 3)
+			interp_col[0] |= R300_RS_COL_FMT(R300_RS_COL_FMT_RGB1);
+		rs_col_count += count;
+	}
+	else
+		interp_col[0] = R300_RS_COL_FMT(R300_RS_COL_FMT_0001);
+
+	if (InputsRead & FRAG_BIT_COL1) {
+		count = VB->AttribPtr[_TNL_ATTRIB_COLOR1]->size;
+		if (count == 3)
+			interp_col[1] |= R300_RS_COL_FMT(R300_RS_COL_FMT_RGB1);
+		interp_col[1] |= R300_RS_COL_PTR(1);
+		rs_col_count += count;
+	}
+
+
 	for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
-		r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = 0 | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3) | (in_texcoords << R300_RS_INTERP_SRC_SHIFT)
-		    | interp_magic[i];
+		int swiz;
+
+		/* with TCL we always seem to route 4 components */
+		if (hw_tcl_on)
+		  count = 4;
+		else
+		  count = VB->AttribPtr[_TNL_ATTRIB_TEX(i)]->size;
+
+		r300->hw.ri.cmd[R300_RI_INTERP_0 + i] = interp_col[i] | rs_tex_count;
+		switch(count) {
+		case 4:swiz = R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3); break;
+		case 3: swiz = R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(R300_RS_SEL_K1); break;
+		default:
+		case 1:
+		case 2: swiz = R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(R300_RS_SEL_K0) | R300_RS_SEL_Q(R300_RS_SEL_K1); break;
+		};
 
+		r300->hw.ri.cmd[R300_RI_INTERP_0 + i] |= swiz;
+ 
 		r300->hw.rr.cmd[R300_RR_INST_0 + fp_reg] = 0;
 		if (InputsRead & (FRAG_BIT_TEX0 << i)) {
+
+			rs_tex_count += count;
+
 			//assert(r300->state.texture.tc_count != 0);
 			r300->hw.rr.cmd[R300_RR_INST_0 + fp_reg] |= R300_RS_INST_TEX_CN_WRITE | i	/* source INTERP */
 			    | (fp_reg << R300_RS_INST_TEX_ADDR_SHIFT);
@@ -1560,10 +1594,6 @@ static void r300SetupRSUnit(GLcontext * ctx)
 				WARN_ONCE("fragprog wants coords for tex%d, vp doesn't provide them!\n", i);
 			}
 		}
-		/* Need to count all coords enabled at vof */
-		if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) {
-			in_texcoords++;
-		}
 	}
 
 	if (InputsRead & FRAG_BIT_COL0) {
@@ -1589,18 +1619,18 @@ static void r300SetupRSUnit(GLcontext * ctx)
 	}
 
 	/* Need at least one. This might still lock as the values are undefined... */
-	if (in_texcoords == 0 && col_interp_nr == 0) {
+	if (rs_tex_count == 0 && col_interp_nr == 0) {
 		r300->hw.rr.cmd[R300_RR_INST_0] |= R300_RS_INST_COL_ID(0) | R300_RS_INST_COL_CN_WRITE | (fp_reg++ << R300_RS_INST_COL_ADDR_SHIFT);
 		col_interp_nr++;
 	}
 
-	r300->hw.rc.cmd[1] = 0 | ((in_texcoords << 2) << R300_IT_COUNT_SHIFT)
+	r300->hw.rc.cmd[1] = 0 | (rs_tex_count << R300_IT_COUNT_SHIFT)
 	  | (col_interp_nr << R300_IC_COUNT_SHIFT)
 	  | R300_HIRES_EN;
 
 	assert(high_rr >= 0);
 	r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R300_RS_INST_0, high_rr + 1);
-	r300->hw.rc.cmd[2] = 0xC0 | high_rr;
+	r300->hw.rc.cmd[2] = high_rr;
 
 	if (InputsRead)
 		WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead);
-- 
cgit v1.2.3