From 88a409fa8e85a45eb71f99e5926340a5fe6a8071 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 4 Feb 2009 15:12:16 +1000 Subject: r300: fix up CS for modesetting - gears under kms works --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 105 +++++++++++++++++--------------- src/mesa/drivers/dri/r300/r300_emit.h | 4 +- src/mesa/drivers/dri/r300/r300_ioctl.c | 4 +- src/mesa/drivers/dri/r300/r300_render.c | 21 ++++--- 4 files changed, 73 insertions(+), 61 deletions(-) (limited to 'src/mesa/drivers/dri/r300') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 9098931602..779307f5eb 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -185,38 +185,41 @@ void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom) r300ContextPtr r300 = R300_CONTEXT(ctx); BATCH_LOCALS(&r300->radeon); drm_r300_cmd_header_t cmd; - uint32_t addr, ndw, i; - - if (!r300->radeon.radeonScreen->kernel_mm) { - uint32_t dwords; - dwords = (*atom->check) (ctx, atom); - BEGIN_BATCH_NO_AUTOSTATE(dwords); - OUT_BATCH_TABLE(atom->cmd, dwords); - END_BATCH(); - return; - } - - cmd.u = atom->cmd[0]; - addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo; + uint32_t addr, ndw, i; + + if (!r300->radeon.radeonScreen->kernel_mm) { + uint32_t dwords; + dwords = (*atom->check) (ctx, atom); + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_BATCH_TABLE(atom->cmd, dwords); + END_BATCH(); + return; + } + + cmd.u = atom->cmd[0]; + addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo; ndw = cmd.vpu.count * 4; - if (ndw) { - /* flush processing vertices */ - OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0)); - OUT_BATCH(0x0); - OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); - OUT_BATCH((1 << 15) | (1 << 28)); - OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0)); - OUT_BATCH(0x00FFFFFF); - OUT_BATCH(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0)); - OUT_BATCH(1); - /* write vpu */ - OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_ADDRESS, 0)); - OUT_BATCH(addr); - OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR); - for (i = 0; i < ndw; i++) { - OUT_BATCH(atom->cmd[i+1]); - } - } + if (ndw) { + BEGIN_BATCH_NO_AUTOSTATE(11 + ndw); + + /* flush processing vertices */ + OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0)); + OUT_BATCH(0x0); + OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); + OUT_BATCH((1 << 15) | (1 << 28)); + OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0)); + OUT_BATCH(0x00FFFFFF); + OUT_BATCH(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0)); + OUT_BATCH(1); + /* write vpu */ + OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_ADDRESS, 0)); + OUT_BATCH(addr); + OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR); + for (i = 0; i < ndw; i++) { + OUT_BATCH(atom->cmd[i+1]); + } + END_BATCH(); + } } void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom) @@ -250,12 +253,14 @@ void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom) ndw = sz * stride; if (ndw) { + BEGIN_BATCH_NO_AUTOSTATE(3 + ndw); OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0)); OUT_BATCH(addr); OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR); for (i = 0; i < ndw; i++) { OUT_BATCH(atom->cmd[i+1]); } + END_BATCH(); } } @@ -269,23 +274,23 @@ static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) int i; for(i = 0; i < numtmus; ++i) { - BEGIN_BATCH(2); - OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); - radeonTexObj *t = r300->hw.textures[i]; - if (t && !t->image_override) { - OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, - RADEON_GEM_DOMAIN_VRAM, 0, 0); - } else if (!t) { - OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]); - } else { - if (t->bo) { - OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, - RADEON_GEM_DOMAIN_VRAM, 0, 0); - } else { - OUT_BATCH(t->override_offset); - } - } - END_BATCH(); + BEGIN_BATCH_NO_AUTOSTATE(2); + OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); + radeonTexObj *t = r300->hw.textures[i]; + if (t && !t->image_override) { + OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, + RADEON_GEM_DOMAIN_VRAM, 0, 0); + } else if (!t) { + OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]); + } else { + if (t->bo) { + OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, + RADEON_GEM_DOMAIN_VRAM, 0, 0); + } else { + OUT_BATCH(t->override_offset); + } + } + END_BATCH(); } } } @@ -312,7 +317,7 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) cbpitch |= R300_COLOR_TILE_ENABLE; - BEGIN_BATCH(4); + BEGIN_BATCH_NO_AUTOSTATE(6); OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1); OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1); @@ -339,7 +344,7 @@ static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom) zbpitch |= R300_DEPTHMICROTILE_TILED; } - BEGIN_BATCH(4); + BEGIN_BATCH_NO_AUTOSTATE(6); OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1); OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch); diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h index d6df2e9edf..94b0a7ebe8 100644 --- a/src/mesa/drivers/dri/r300/r300_emit.h +++ b/src/mesa/drivers/dri/r300/r300_emit.h @@ -136,10 +136,10 @@ static INLINE uint32_t cmdpacify(struct radeon_screen *rscrn) * Outputs 2 dwords and expects (num_extra+1) additional dwords afterwards. */ #define OUT_BATCH_PACKET3(packet, num_extra) do {\ - if (!b_l_rmesa->radeonScreen->kernel_mm) { \ + if (!b_l_rmesa->radeonScreen->kernel_mm) { \ OUT_BATCH(cmdpacket3(b_l_rmesa->radeonScreen,\ R300_CMD_PACKET3_RAW)); \ - }\ + } else b_l_rmesa->cmdbuf.cs->section_cdw++;\ OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ } while(0) diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index b0a579bf84..f07252fbe2 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -99,7 +99,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, if (flags & CLEARBUFFER_COLOR) { assert(rrb != 0); - BEGIN_BATCH_NO_AUTOSTATE(4); + BEGIN_BATCH_NO_AUTOSTATE(6); OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1); OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGVAL(R300_RB3D_COLORPITCH0, cbpitch); @@ -115,7 +115,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, if (rrbd->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){ cbpitch |= R300_DEPTHMICROTILE_TILED; } - BEGIN_BATCH_NO_AUTOSTATE(4); + BEGIN_BATCH_NO_AUTOSTATE(6); OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1); OUT_BATCH_RELOC(0, rrbd->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, cbpitch); diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index 8db22b777f..7af9691cde 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -229,12 +229,12 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) fprintf(stderr, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__, nr, offset); - BEGIN_BATCH(sz+2); - OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1); - OUT_BATCH(nr); - if (!rmesa->radeon.radeonScreen->kernel_mm) { + BEGIN_BATCH(sz+2); + OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1); + OUT_BATCH(nr); + for (i = 0; i + 1 < nr; i += 2) { OUT_BATCH((rmesa->state.aos[i].components << 0) | (rmesa->state.aos[i].stride << 8) | @@ -246,10 +246,10 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) OUT_BATCH_RELOC(voffset, rmesa->state.aos[i].bo, voffset, - RADEON_GEM_DOMAIN_GTT, + RADEON_GEM_DOMAIN_GTT, 0, 0); voffset = rmesa->state.aos[i + 1].offset + - offset * 4 * rmesa->state.aos[i + 1].stride; + offset * 4 * rmesa->state.aos[i + 1].stride; OUT_BATCH_RELOC(voffset, rmesa->state.aos[i+1].bo, voffset, @@ -268,7 +268,13 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) RADEON_GEM_DOMAIN_GTT, 0, 0); } + END_BATCH(); } else { + + BEGIN_BATCH(sz+2+(nr * 2)); + OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1); + OUT_BATCH(nr); + for (i = 0; i + 1 < nr; i += 2) { OUT_BATCH((rmesa->state.aos[i].components << 0) | (rmesa->state.aos[i].stride << 8) | @@ -312,8 +318,9 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) RADEON_GEM_DOMAIN_GTT, 0, 0); } + END_BATCH(); } - END_BATCH(); + } static void r300FireAOS(r300ContextPtr rmesa, int vertex_count, int type) -- cgit v1.2.3