From 4138bdb3b1e845d8a6172015025e1231fda7dcd1 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 8 Apr 2009 15:16:35 -0400 Subject: R600: initial copy of r300 code --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 669 ++++++++++++++++++++++++++++++++ 1 file changed, 669 insertions(+) create mode 100644 src/mesa/drivers/dri/r600/r600_cmdbuf.c (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c new file mode 100644 index 0000000000..1ae6dc82bd --- /dev/null +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -0,0 +1,669 @@ +/* +Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + +The Weather Channel (TM) funded Tungsten Graphics to develop the +initial release of the Radeon 8500 driver under the XFree86 license. +This notice must be preserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/** + * \file + * + * \author Nicolai Haehnle + */ + +#include "main/glheader.h" +#include "main/state.h" +#include "main/imports.h" +#include "main/macros.h" +#include "main/context.h" +#include "main/simple_list.h" +#include "swrast/swrast.h" + +#include "drm.h" +#include "radeon_drm.h" + +#include "r600_context.h" +#include "r600_ioctl.h" +#include "radeon_reg.h" +#include "r600_reg.h" +#include "r600_cmdbuf.h" +#include "r600_emit.h" +#include "radeon_bocs_wrapper.h" +#include "radeon_mipmap_tree.h" +#include "r600_state.h" +#include "radeon_reg.h" + +#define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200 +# define RADEON_ONE_REG_WR (1 << 15) + +/** # of dwords reserved for additional instructions that may need to be written + * during flushing. + */ +#define SPACE_FOR_FLUSHING 4 + +static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt) +{ + if (r300->radeon.radeonScreen->kernel_mm) { + return ((((*pkt) >> 16) & 0x3FFF) + 1); + } else { + drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt; + return t->packet0.count; + } + return 0; +} + +#define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count) +#define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count) + +void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom) +{ + r300ContextPtr r300 = R300_CONTEXT(ctx); + BATCH_LOCALS(&r300->radeon); + drm_r300_cmd_header_t cmd; + uint32_t addr, ndw, i; + + if (!r300->radeon.radeonScreen->kernel_mm) { + uint32_t dwords; + dwords = (*atom->check) (ctx, atom); + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_BATCH_TABLE(atom->cmd, dwords); + END_BATCH(); + return; + } + + cmd.u = atom->cmd[0]; + addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo; + ndw = cmd.vpu.count * 4; + if (ndw) { + + if (r300->vap_flush_needed) { + BEGIN_BATCH_NO_AUTOSTATE(15 + ndw); + + /* flush processing vertices */ + OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0); + OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); + OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); + OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0xffffff); + OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0); + r300->vap_flush_needed = GL_FALSE; + } else { + BEGIN_BATCH_NO_AUTOSTATE(5 + ndw); + } + OUT_BATCH_REGVAL(R300_VAP_PVS_UPLOAD_ADDRESS, addr); + OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR); + for (i = 0; i < ndw; i++) { + OUT_BATCH(atom->cmd[i+1]); + } + OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0); + END_BATCH(); + } +} + +void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom) +{ + r300ContextPtr r300 = R300_CONTEXT(ctx); + BATCH_LOCALS(&r300->radeon); + drm_r300_cmd_header_t cmd; + uint32_t addr, ndw, i, sz; + int type, clamp, stride; + + if (!r300->radeon.radeonScreen->kernel_mm) { + uint32_t dwords; + dwords = (*atom->check) (ctx, atom); + BEGIN_BATCH_NO_AUTOSTATE(dwords); + OUT_BATCH_TABLE(atom->cmd, dwords); + END_BATCH(); + return; + } + + cmd.u = atom->cmd[0]; + sz = cmd.r500fp.count; + addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo; + type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE); + clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP); + + addr |= (type << 16); + addr |= (clamp << 17); + + stride = type ? 4 : 6; + + ndw = sz * stride; + if (ndw) { + + BEGIN_BATCH_NO_AUTOSTATE(3 + ndw); + OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0)); + OUT_BATCH(addr); + OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR); + for (i = 0; i < ndw; i++) { + OUT_BATCH(atom->cmd[i+1]); + } + END_BATCH(); + } +} + +static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) +{ + r300ContextPtr r300 = R300_CONTEXT(ctx); + BATCH_LOCALS(&r300->radeon); + int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd); + int notexture = 0; + + if (numtmus) { + int i; + + for(i = 0; i < numtmus; ++i) { + radeonTexObj *t = r300->hw.textures[i]; + + if (!t) + notexture = 1; + } + + if (r300->radeon.radeonScreen->kernel_mm && notexture) { + return; + } + BEGIN_BATCH_NO_AUTOSTATE(4 * numtmus); + for(i = 0; i < numtmus; ++i) { + radeonTexObj *t = r300->hw.textures[i]; + OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); + if (t && !t->image_override) { + OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + } else if (!t) { + OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]); + } else { /* override cases */ + if (t->bo) { + OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + } else if (!r300->radeon.radeonScreen->kernel_mm) { + OUT_BATCH(t->override_offset); + } + else + OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]); + } + } + END_BATCH(); + } +} + +static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) +{ + r300ContextPtr r300 = R300_CONTEXT(ctx); + BATCH_LOCALS(&r300->radeon); + struct radeon_renderbuffer *rrb; + uint32_t cbpitch; + uint32_t offset = r300->radeon.state.color.draw_offset; + + rrb = radeon_get_colorbuffer(&r300->radeon); + if (!rrb || !rrb->bo) { + fprintf(stderr, "no rrb\n"); + return; + } + + cbpitch = (rrb->pitch / rrb->cpp); + if (rrb->cpp == 4) + cbpitch |= R300_COLOR_FORMAT_ARGB8888; + else + cbpitch |= R300_COLOR_FORMAT_RGB565; + + if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) + cbpitch |= R300_COLOR_TILE_ENABLE; + + BEGIN_BATCH_NO_AUTOSTATE(8); + OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1); + OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0); + OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1); + OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0); + END_BATCH(); + if (r300->radeon.radeonScreen->driScreen->dri2.enabled) { + if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { + BEGIN_BATCH_NO_AUTOSTATE(3); + OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2); + OUT_BATCH(0); + OUT_BATCH((rrb->width << R300_SCISSORS_X_SHIFT) | + (rrb->height << R300_SCISSORS_Y_SHIFT)); + END_BATCH(); + } else { + BEGIN_BATCH_NO_AUTOSTATE(3); + OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2); + OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) | + (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT)); + OUT_BATCH(((rrb->width + R300_SCISSORS_OFFSET) << R300_SCISSORS_X_SHIFT) | + ((rrb->height + R300_SCISSORS_OFFSET) << R300_SCISSORS_Y_SHIFT)); + END_BATCH(); + } + } +} + +static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom) +{ + r300ContextPtr r300 = R300_CONTEXT(ctx); + BATCH_LOCALS(&r300->radeon); + struct radeon_renderbuffer *rrb; + uint32_t zbpitch; + + rrb = radeon_get_depthbuffer(&r300->radeon); + if (!rrb) + return; + + zbpitch = (rrb->pitch / rrb->cpp); + if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { + zbpitch |= R300_DEPTHMACROTILE_ENABLE; + } + if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){ + zbpitch |= R300_DEPTHMICROTILE_TILED; + } + + BEGIN_BATCH_NO_AUTOSTATE(6); + OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); + OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch); + END_BATCH(); +} + +static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom) +{ + r300ContextPtr r300 = R300_CONTEXT(ctx); + BATCH_LOCALS(&r300->radeon); + struct radeon_renderbuffer *rrb; + uint32_t format = 0; + + rrb = radeon_get_depthbuffer(&r300->radeon); + if (!rrb) + format = 0; + else { + if (rrb->cpp == 2) + format = R300_DEPTHFORMAT_16BIT_INT_Z; + else if (rrb->cpp == 4) + format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL; + } + + OUT_BATCH(atom->cmd[0]); + atom->cmd[1] &= ~0xf; + atom->cmd[1] |= format; + OUT_BATCH(atom->cmd[1]); + OUT_BATCH(atom->cmd[2]); + OUT_BATCH(atom->cmd[3]); + OUT_BATCH(atom->cmd[4]); +} + +static int check_always(GLcontext *ctx, struct radeon_state_atom *atom) +{ + return atom->cmd_size; +} + +static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r300ContextPtr r300 = R300_CONTEXT(ctx); + int cnt; + if (atom->cmd[0] == CP_PACKET2) { + return 0; + } + cnt = packet0_count(r300, atom->cmd); + return cnt ? cnt + 1 : 0; +} + +int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom) +{ + int cnt; + + cnt = vpu_count(atom->cmd); + return cnt ? (cnt * 4) + 1 : 0; +} + +int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom) +{ + int cnt; + + cnt = r500fp_count(atom->cmd); + return cnt ? (cnt * 6) + 1 : 0; +} + +int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom) +{ + int cnt; + + cnt = r500fp_count(atom->cmd); + return cnt ? (cnt * 4) + 1 : 0; +} + +#define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \ + do { \ + r300->hw.ATOM.cmd_size = (SZ); \ + r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \ + r300->hw.ATOM.name = #ATOM; \ + r300->hw.ATOM.idx = (IDX); \ + r300->hw.ATOM.check = check_##CHK; \ + r300->hw.ATOM.dirty = GL_FALSE; \ + r300->radeon.hw.max_state_size += (SZ); \ + insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \ + } while (0) +/** + * Allocate memory for the command buffer and initialize the state atom + * list. Note that the initial hardware state is set by r300InitState(). + */ +void r300InitCmdBuf(r300ContextPtr r300) +{ + int mtu; + int has_tcl = 1; + int is_r500 = 0; + int i; + + if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) + has_tcl = 0; + + if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) + is_r500 = 1; + + r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */ + + mtu = r300->radeon.glCtx->Const.MaxTextureUnits; + if (RADEON_DEBUG & DEBUG_TEXTURE) { + fprintf(stderr, "Using %d maximum texture units..\n", mtu); + } + + /* Setup the atom linked list */ + make_empty_list(&r300->radeon.hw.atomlist); + r300->radeon.hw.atomlist.name = "atom-list"; + + /* Initialize state atoms */ + ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0); + r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6); + ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0); + r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1); + r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0; + r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1); + if (is_r500) { + ALLOC_STATE(vap_index_offset, always, 2, 0); + r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1); + r300->hw.vap_index_offset.cmd[1] = 0; + } + ALLOC_STATE(vte, always, 3, 0); + r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2); + ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0); + r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2); + ALLOC_STATE(vap_cntl_status, always, 2, 0); + r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1); + ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0); + r300->hw.vir[0].cmd[R300_VIR_CMD_0] = + cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1); + ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1); + r300->hw.vir[1].cmd[R300_VIR_CMD_0] = + cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1); + ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0); + r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2); + ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0); + r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE); + + if (has_tcl) { + ALLOC_STATE(vap_clip_cntl, always, 2, 0); + r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1); + ALLOC_STATE(vap_clip, always, 5, 0); + r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4); + ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0); + r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1); + } + + ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0); + r300->hw.vof.cmd[R300_VOF_CMD_0] = + cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2); + + if (has_tcl) { + ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0); + r300->hw.pvs.cmd[R300_PVS_CMD_0] = + cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3); + } + + ALLOC_STATE(gb_enable, always, 2, 0); + r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1); + ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0); + r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 5); + ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0); + r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1); + ALLOC_STATE(ga_point_s0, always, 5, 0); + r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4); + ALLOC_STATE(ga_triangle_stipple, always, 2, 0); + r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1); + ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0); + r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1); + ALLOC_STATE(ga_point_minmax, always, 4, 0); + r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3); + ALLOC_STATE(lcntl, always, 2, 0); + r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1); + ALLOC_STATE(ga_line_stipple, always, 4, 0); + r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3); + ALLOC_STATE(shade, always, 5, 0); + r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 4); + ALLOC_STATE(polygon_mode, always, 4, 0); + r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3); + ALLOC_STATE(fogp, always, 3, 0); + r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2); + ALLOC_STATE(zbias_cntl, always, 2, 0); + r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1); + ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0); + r300->hw.zbs.cmd[R300_ZBS_CMD_0] = + cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4); + ALLOC_STATE(occlusion_cntl, always, 2, 0); + r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1); + ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0); + r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1); + ALLOC_STATE(su_depth_scale, always, 3, 0); + r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2); + ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0); + r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2); + if (is_r500) { + ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0); + r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16); + for (i = 0; i < 8; i++) { + r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] = + (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) | + (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) | + (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | + (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT); + } + ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0); + r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1); + } else { + ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0); + r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8); + ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0); + r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1); + } + ALLOC_STATE(sc_hyperz, always, 3, 0); + r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2); + ALLOC_STATE(sc_screendoor, always, 2, 0); + r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1); + ALLOC_STATE(us_out_fmt, always, 6, 0); + r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5); + + if (is_r500) { + ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0); + r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2); + r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO; + r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3); + r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1); + r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */ + + ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0); + r300->hw.r500fp.cmd[R300_FPI_CMD_0] = + cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0); + r300->hw.r500fp.emit = emit_r500fp; + ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0); + r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] = + cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0); + r300->hw.r500fp_const.emit = emit_r500fp; + } else { + ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0); + r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3); + r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4); + + ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0); + r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0); + + ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0); + r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1); + ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1); + r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1); + ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2); + r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1); + ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3); + r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1); + ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0); + r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0); + } + ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0); + r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1); + ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0); + r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3); + ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0); + r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2); + ALLOC_STATE(fg_depth_src, always, 2, 0); + r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1); + ALLOC_STATE(rb3d_cctl, always, 2, 0); + r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1); + ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0); + r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2); + ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0); + r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1); + if (is_r500) { + ALLOC_STATE(blend_color, always, 3, 0); + r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2); + } else { + ALLOC_STATE(blend_color, always, 2, 0); + r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1); + } + ALLOC_STATE(rop, always, 2, 0); + r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1); + ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0); + r300->hw.cb.emit = &emit_cb_offset; + ALLOC_STATE(rb3d_dither_ctl, always, 10, 0); + r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9); + ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0); + r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1); + ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0); + r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2); + ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0); + r300->hw.zs.cmd[R300_ZS_CMD_0] = + cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3); + + ALLOC_STATE(zstencil_format, always, 5, 0); + r300->hw.zstencil_format.cmd[0] = + cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4); + r300->hw.zstencil_format.emit = emit_zstencil_format; + + ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0); + r300->hw.zb.emit = emit_zb_offset; + ALLOC_STATE(zb_depthclearvalue, always, 2, 0); + r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1); + ALLOC_STATE(unk4F30, always, 3, 0); + r300->hw.unk4F30.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4F30, 2); + ALLOC_STATE(zb_hiz_offset, always, 2, 0); + r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1); + ALLOC_STATE(zb_hiz_pitch, always, 2, 0); + r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1); + + /* VPU only on TCL */ + if (has_tcl) { + int i; + ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0); + r300->hw.vpi.cmd[0] = + cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0); + r300->hw.vpi.emit = emit_vpu; + + if (is_r500) { + ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0); + r300->hw.vpp.cmd[0] = + cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0); + r300->hw.vpp.emit = emit_vpu; + + ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0); + r300->hw.vps.cmd[0] = + cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1); + r300->hw.vps.emit = emit_vpu; + + for (i = 0; i < 6; i++) { + ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0); + r300->hw.vpucp[i].cmd[0] = + cmdvpu(r300->radeon.radeonScreen, + R500_PVS_UCP_START + i, 1); + r300->hw.vpucp[i].emit = emit_vpu; + } + } else { + ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0); + r300->hw.vpp.cmd[0] = + cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0); + r300->hw.vpp.emit = emit_vpu; + + ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0); + r300->hw.vps.cmd[0] = + cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1); + r300->hw.vps.emit = emit_vpu; + + for (i = 0; i < 6; i++) { + ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0); + r300->hw.vpucp[i].cmd[0] = + cmdvpu(r300->radeon.radeonScreen, + R300_PVS_UCP_START + i, 1); + r300->hw.vpucp[i].emit = emit_vpu; + } + } + } + + /* Textures */ + ALLOC_STATE(tex.filter, variable, mtu + 1, 0); + r300->hw.tex.filter.cmd[R300_TEX_CMD_0] = + cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0); + + ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0); + r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] = + cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0); + + ALLOC_STATE(tex.size, variable, mtu + 1, 0); + r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0); + + ALLOC_STATE(tex.format, variable, mtu + 1, 0); + r300->hw.tex.format.cmd[R300_TEX_CMD_0] = + cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0); + + ALLOC_STATE(tex.pitch, variable, mtu + 1, 0); + r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0); + + ALLOC_STATE(tex.offset, variable, 1, 0); + r300->hw.tex.offset.cmd[R300_TEX_CMD_0] = + cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0); + r300->hw.tex.offset.emit = &emit_tex_offsets; + + ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0); + r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] = + cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0); + + ALLOC_STATE(tex.border_color, variable, mtu + 1, 0); + r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] = + cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0); + + r300->radeon.hw.is_dirty = GL_TRUE; + r300->radeon.hw.all_dirty = GL_TRUE; + + rcommonInitCmdBuf(&r300->radeon); +} -- cgit v1.2.3 From e24e4ae2e8f69447c0917655d25fa96b62b94298 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 9 Apr 2009 10:55:41 -0400 Subject: R6xx/R7xx: r300 -> r600 symbols --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 498 ++-- src/mesa/drivers/dri/r600/r600_cmdbuf.h | 2 +- src/mesa/drivers/dri/r600/r600_context.c | 152 +- src/mesa/drivers/dri/r600/r600_context.h | 490 ++-- src/mesa/drivers/dri/r600/r600_emit.c | 146 +- src/mesa/drivers/dri/r600/r600_emit.h | 24 +- src/mesa/drivers/dri/r600/r600_fragprog.c | 112 +- src/mesa/drivers/dri/r600/r600_fragprog.h | 60 +- src/mesa/drivers/dri/r600/r600_fragprog_emit.c | 106 +- src/mesa/drivers/dri/r600/r600_fragprog_swizzle.c | 38 +- src/mesa/drivers/dri/r600/r600_fragprog_swizzle.h | 10 +- src/mesa/drivers/dri/r600/r600_ioctl.c | 374 +-- src/mesa/drivers/dri/r600/r600_ioctl.h | 2 +- src/mesa/drivers/dri/r600/r600_reg.h | 2794 ++++++++++----------- src/mesa/drivers/dri/r600/r600_render.c | 154 +- src/mesa/drivers/dri/r600/r600_shader.c | 44 +- src/mesa/drivers/dri/r600/r600_state.c | 1558 ++++++------ src/mesa/drivers/dri/r600/r600_state.h | 30 +- src/mesa/drivers/dri/r600/r600_swtcl.c | 214 +- src/mesa/drivers/dri/r600/r600_swtcl.h | 16 +- src/mesa/drivers/dri/r600/r600_tex.c | 100 +- src/mesa/drivers/dri/r600/r600_tex.h | 12 +- src/mesa/drivers/dri/r600/r600_texstate.c | 168 +- src/mesa/drivers/dri/r600/r600_vertprog.c | 158 +- src/mesa/drivers/dri/r600/r700_fragprog.c | 28 +- src/mesa/drivers/dri/r600/r700_fragprog.h | 4 +- src/mesa/drivers/dri/r600/r700_fragprog_emit.c | 2 +- src/mesa/drivers/dri/radeon/radeon_screen.c | 16 +- 28 files changed, 3656 insertions(+), 3656 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 1ae6dc82bd..73de822397 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -55,7 +55,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r600_state.h" #include "radeon_reg.h" -#define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200 +#define R600_VAP_PVS_UPLOAD_ADDRESS 0x2200 # define RADEON_ONE_REG_WR (1 << 15) /** # of dwords reserved for additional instructions that may need to be written @@ -63,9 +63,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #define SPACE_FOR_FLUSHING 4 -static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt) +static unsigned packet0_count(r600ContextPtr r600, uint32_t *pkt) { - if (r300->radeon.radeonScreen->kernel_mm) { + if (r600->radeon.radeonScreen->kernel_mm) { return ((((*pkt) >> 16) & 0x3FFF) + 1); } else { drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt; @@ -79,12 +79,12 @@ static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt) void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom) { - r300ContextPtr r300 = R300_CONTEXT(ctx); - BATCH_LOCALS(&r300->radeon); + r600ContextPtr r600 = R600_CONTEXT(ctx); + BATCH_LOCALS(&r600->radeon); drm_r300_cmd_header_t cmd; uint32_t addr, ndw, i; - if (!r300->radeon.radeonScreen->kernel_mm) { + if (!r600->radeon.radeonScreen->kernel_mm) { uint32_t dwords; dwords = (*atom->check) (ctx, atom); BEGIN_BATCH_NO_AUTOSTATE(dwords); @@ -98,38 +98,38 @@ void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom) ndw = cmd.vpu.count * 4; if (ndw) { - if (r300->vap_flush_needed) { + if (r600->vap_flush_needed) { BEGIN_BATCH_NO_AUTOSTATE(15 + ndw); /* flush processing vertices */ - OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0); - OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); + OUT_BATCH_REGVAL(R600_SC_SCREENDOOR, 0); + OUT_BATCH_REGVAL(R600_RB3D_DSTCACHE_CTLSTAT, R600_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); - OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0xffffff); - OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0); - r300->vap_flush_needed = GL_FALSE; + OUT_BATCH_REGVAL(R600_SC_SCREENDOOR, 0xffffff); + OUT_BATCH_REGVAL(R600_VAP_PVS_STATE_FLUSH_REG, 0); + r600->vap_flush_needed = GL_FALSE; } else { BEGIN_BATCH_NO_AUTOSTATE(5 + ndw); } - OUT_BATCH_REGVAL(R300_VAP_PVS_UPLOAD_ADDRESS, addr); - OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR); + OUT_BATCH_REGVAL(R600_VAP_PVS_UPLOAD_ADDRESS, addr); + OUT_BATCH(CP_PACKET0(R600_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR); for (i = 0; i < ndw; i++) { OUT_BATCH(atom->cmd[i+1]); } - OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0); + OUT_BATCH_REGVAL(R600_VAP_PVS_STATE_FLUSH_REG, 0); END_BATCH(); } } void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom) { - r300ContextPtr r300 = R300_CONTEXT(ctx); - BATCH_LOCALS(&r300->radeon); + r600ContextPtr r600 = R600_CONTEXT(ctx); + BATCH_LOCALS(&r600->radeon); drm_r300_cmd_header_t cmd; uint32_t addr, ndw, i, sz; int type, clamp, stride; - if (!r300->radeon.radeonScreen->kernel_mm) { + if (!r600->radeon.radeonScreen->kernel_mm) { uint32_t dwords; dwords = (*atom->check) (ctx, atom); BEGIN_BATCH_NO_AUTOSTATE(dwords); @@ -165,42 +165,42 @@ void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom) static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) { - r300ContextPtr r300 = R300_CONTEXT(ctx); - BATCH_LOCALS(&r300->radeon); - int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd); + r600ContextPtr r600 = R600_CONTEXT(ctx); + BATCH_LOCALS(&r600->radeon); + int numtmus = packet0_count(r600, r600->hw.tex.offset.cmd); int notexture = 0; if (numtmus) { int i; for(i = 0; i < numtmus; ++i) { - radeonTexObj *t = r300->hw.textures[i]; + radeonTexObj *t = r600->hw.textures[i]; if (!t) notexture = 1; } - if (r300->radeon.radeonScreen->kernel_mm && notexture) { + if (r600->radeon.radeonScreen->kernel_mm && notexture) { return; } BEGIN_BATCH_NO_AUTOSTATE(4 * numtmus); for(i = 0; i < numtmus; ++i) { - radeonTexObj *t = r300->hw.textures[i]; - OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); + radeonTexObj *t = r600->hw.textures[i]; + OUT_BATCH_REGSEQ(R600_TX_OFFSET_0 + (i * 4), 1); if (t && !t->image_override) { OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); } else if (!t) { - OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]); + OUT_BATCH(r600->radeon.radeonScreen->texOffset[0]); } else { /* override cases */ if (t->bo) { OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - } else if (!r300->radeon.radeonScreen->kernel_mm) { + } else if (!r600->radeon.radeonScreen->kernel_mm) { OUT_BATCH(t->override_offset); } else - OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]); + OUT_BATCH(r600->radeon.radeonScreen->texOffset[0]); } } END_BATCH(); @@ -209,13 +209,13 @@ static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) { - r300ContextPtr r300 = R300_CONTEXT(ctx); - BATCH_LOCALS(&r300->radeon); + r600ContextPtr r600 = R600_CONTEXT(ctx); + BATCH_LOCALS(&r600->radeon); struct radeon_renderbuffer *rrb; uint32_t cbpitch; - uint32_t offset = r300->radeon.state.color.draw_offset; + uint32_t offset = r600->radeon.state.color.draw_offset; - rrb = radeon_get_colorbuffer(&r300->radeon); + rrb = radeon_get_colorbuffer(&r600->radeon); if (!rrb || !rrb->bo) { fprintf(stderr, "no rrb\n"); return; @@ -223,34 +223,34 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) cbpitch = (rrb->pitch / rrb->cpp); if (rrb->cpp == 4) - cbpitch |= R300_COLOR_FORMAT_ARGB8888; + cbpitch |= R600_COLOR_FORMAT_ARGB8888; else - cbpitch |= R300_COLOR_FORMAT_RGB565; + cbpitch |= R600_COLOR_FORMAT_RGB565; if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) - cbpitch |= R300_COLOR_TILE_ENABLE; + cbpitch |= R600_COLOR_TILE_ENABLE; BEGIN_BATCH_NO_AUTOSTATE(8); - OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1); + OUT_BATCH_REGSEQ(R600_RB3D_COLOROFFSET0, 1); OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0); - OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1); + OUT_BATCH_REGSEQ(R600_RB3D_COLORPITCH0, 1); OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); - if (r300->radeon.radeonScreen->driScreen->dri2.enabled) { - if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { + if (r600->radeon.radeonScreen->driScreen->dri2.enabled) { + if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { BEGIN_BATCH_NO_AUTOSTATE(3); - OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2); + OUT_BATCH_REGSEQ(R600_SC_SCISSORS_TL, 2); OUT_BATCH(0); - OUT_BATCH((rrb->width << R300_SCISSORS_X_SHIFT) | - (rrb->height << R300_SCISSORS_Y_SHIFT)); + OUT_BATCH((rrb->width << R600_SCISSORS_X_SHIFT) | + (rrb->height << R600_SCISSORS_Y_SHIFT)); END_BATCH(); } else { BEGIN_BATCH_NO_AUTOSTATE(3); - OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2); - OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) | - (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT)); - OUT_BATCH(((rrb->width + R300_SCISSORS_OFFSET) << R300_SCISSORS_X_SHIFT) | - ((rrb->height + R300_SCISSORS_OFFSET) << R300_SCISSORS_Y_SHIFT)); + OUT_BATCH_REGSEQ(R600_SC_SCISSORS_TL, 2); + OUT_BATCH((R600_SCISSORS_OFFSET << R600_SCISSORS_X_SHIFT) | + (R600_SCISSORS_OFFSET << R600_SCISSORS_Y_SHIFT)); + OUT_BATCH(((rrb->width + R600_SCISSORS_OFFSET) << R600_SCISSORS_X_SHIFT) | + ((rrb->height + R600_SCISSORS_OFFSET) << R600_SCISSORS_Y_SHIFT)); END_BATCH(); } } @@ -258,45 +258,45 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom) { - r300ContextPtr r300 = R300_CONTEXT(ctx); - BATCH_LOCALS(&r300->radeon); + r600ContextPtr r600 = R600_CONTEXT(ctx); + BATCH_LOCALS(&r600->radeon); struct radeon_renderbuffer *rrb; uint32_t zbpitch; - rrb = radeon_get_depthbuffer(&r300->radeon); + rrb = radeon_get_depthbuffer(&r600->radeon); if (!rrb) return; zbpitch = (rrb->pitch / rrb->cpp); if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { - zbpitch |= R300_DEPTHMACROTILE_ENABLE; + zbpitch |= R600_DEPTHMACROTILE_ENABLE; } if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){ - zbpitch |= R300_DEPTHMICROTILE_TILED; + zbpitch |= R600_DEPTHMICROTILE_TILED; } BEGIN_BATCH_NO_AUTOSTATE(6); - OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1); + OUT_BATCH_REGSEQ(R600_ZB_DEPTHOFFSET, 1); OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); - OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch); + OUT_BATCH_REGVAL(R600_ZB_DEPTHPITCH, zbpitch); END_BATCH(); } static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom) { - r300ContextPtr r300 = R300_CONTEXT(ctx); - BATCH_LOCALS(&r300->radeon); + r600ContextPtr r600 = R600_CONTEXT(ctx); + BATCH_LOCALS(&r600->radeon); struct radeon_renderbuffer *rrb; uint32_t format = 0; - rrb = radeon_get_depthbuffer(&r300->radeon); + rrb = radeon_get_depthbuffer(&r600->radeon); if (!rrb) format = 0; else { if (rrb->cpp == 2) - format = R300_DEPTHFORMAT_16BIT_INT_Z; + format = R600_DEPTHFORMAT_16BIT_INT_Z; else if (rrb->cpp == 4) - format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL; + format = R600_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL; } OUT_BATCH(atom->cmd[0]); @@ -315,12 +315,12 @@ static int check_always(GLcontext *ctx, struct radeon_state_atom *atom) static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom) { - r300ContextPtr r300 = R300_CONTEXT(ctx); + r600ContextPtr r600 = R600_CONTEXT(ctx); int cnt; if (atom->cmd[0] == CP_PACKET2) { return 0; } - cnt = packet0_count(r300, atom->cmd); + cnt = packet0_count(r600, atom->cmd); return cnt ? cnt + 1 : 0; } @@ -350,320 +350,320 @@ int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom) #define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \ do { \ - r300->hw.ATOM.cmd_size = (SZ); \ - r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \ - r300->hw.ATOM.name = #ATOM; \ - r300->hw.ATOM.idx = (IDX); \ - r300->hw.ATOM.check = check_##CHK; \ - r300->hw.ATOM.dirty = GL_FALSE; \ - r300->radeon.hw.max_state_size += (SZ); \ - insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \ + r600->hw.ATOM.cmd_size = (SZ); \ + r600->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \ + r600->hw.ATOM.name = #ATOM; \ + r600->hw.ATOM.idx = (IDX); \ + r600->hw.ATOM.check = check_##CHK; \ + r600->hw.ATOM.dirty = GL_FALSE; \ + r600->radeon.hw.max_state_size += (SZ); \ + insert_at_tail(&r600->radeon.hw.atomlist, &r600->hw.ATOM); \ } while (0) /** * Allocate memory for the command buffer and initialize the state atom - * list. Note that the initial hardware state is set by r300InitState(). + * list. Note that the initial hardware state is set by r600InitState(). */ -void r300InitCmdBuf(r300ContextPtr r300) +void r600InitCmdBuf(r600ContextPtr r600) { int mtu; int has_tcl = 1; int is_r500 = 0; int i; - if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) + if (!(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) has_tcl = 0; - if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) + if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) is_r500 = 1; - r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */ + r600->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */ - mtu = r300->radeon.glCtx->Const.MaxTextureUnits; + mtu = r600->radeon.glCtx->Const.MaxTextureUnits; if (RADEON_DEBUG & DEBUG_TEXTURE) { fprintf(stderr, "Using %d maximum texture units..\n", mtu); } /* Setup the atom linked list */ - make_empty_list(&r300->radeon.hw.atomlist); - r300->radeon.hw.atomlist.name = "atom-list"; + make_empty_list(&r600->radeon.hw.atomlist); + r600->radeon.hw.atomlist.name = "atom-list"; /* Initialize state atoms */ - ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0); - r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6); - ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0); - r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1); - r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0; - r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1); + ALLOC_STATE(vpt, always, R600_VPT_CMDSIZE, 0); + r600->hw.vpt.cmd[R600_VPT_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_SE_VPORT_XSCALE, 6); + ALLOC_STATE(vap_cntl, always, R600_VAP_CNTL_SIZE, 0); + r600->hw.vap_cntl.cmd[R600_VAP_CNTL_FLUSH] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PVS_STATE_FLUSH_REG, 1); + r600->hw.vap_cntl.cmd[R600_VAP_CNTL_FLUSH_1] = 0; + r600->hw.vap_cntl.cmd[R600_VAP_CNTL_CMD] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_CNTL, 1); if (is_r500) { ALLOC_STATE(vap_index_offset, always, 2, 0); - r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1); - r300->hw.vap_index_offset.cmd[1] = 0; + r600->hw.vap_index_offset.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1); + r600->hw.vap_index_offset.cmd[1] = 0; } ALLOC_STATE(vte, always, 3, 0); - r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2); + r600->hw.vte.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SE_VTE_CNTL, 2); ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0); - r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2); + r600->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_VF_MAX_VTX_INDX, 2); ALLOC_STATE(vap_cntl_status, always, 2, 0); - r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1); - ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0); - r300->hw.vir[0].cmd[R300_VIR_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1); - ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1); - r300->hw.vir[1].cmd[R300_VIR_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1); - ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0); - r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2); + r600->hw.vap_cntl_status.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_CNTL_STATUS, 1); + ALLOC_STATE(vir[0], variable, R600_VIR_CMDSIZE, 0); + r600->hw.vir[0].cmd[R600_VIR_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PROG_STREAM_CNTL_0, 1); + ALLOC_STATE(vir[1], variable, R600_VIR_CMDSIZE, 1); + r600->hw.vir[1].cmd[R600_VIR_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PROG_STREAM_CNTL_EXT_0, 1); + ALLOC_STATE(vic, always, R600_VIC_CMDSIZE, 0); + r600->hw.vic.cmd[R600_VIC_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_VTX_STATE_CNTL, 2); ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0); - r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE); + r600->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE); if (has_tcl) { ALLOC_STATE(vap_clip_cntl, always, 2, 0); - r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1); + r600->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_CLIP_CNTL, 1); ALLOC_STATE(vap_clip, always, 5, 0); - r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4); + r600->hw.vap_clip.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_GB_VERT_CLIP_ADJ, 4); ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0); - r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1); + r600->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1); } - ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0); - r300->hw.vof.cmd[R300_VOF_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2); + ALLOC_STATE(vof, always, R600_VOF_CMDSIZE, 0); + r600->hw.vof.cmd[R600_VOF_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_VAP_OUTPUT_VTX_FMT_0, 2); if (has_tcl) { - ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0); - r300->hw.pvs.cmd[R300_PVS_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3); + ALLOC_STATE(pvs, always, R600_PVS_CMDSIZE, 0); + r600->hw.pvs.cmd[R600_PVS_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PVS_CODE_CNTL_0, 3); } ALLOC_STATE(gb_enable, always, 2, 0); - r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1); - ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0); - r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 5); - ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0); - r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1); + r600->hw.gb_enable.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GB_ENABLE, 1); + ALLOC_STATE(gb_misc, always, R600_GB_MISC_CMDSIZE, 0); + r600->hw.gb_misc.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GB_MSPOS0, 5); + ALLOC_STATE(txe, always, R600_TXE_CMDSIZE, 0); + r600->hw.txe.cmd[R600_TXE_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_TX_ENABLE, 1); ALLOC_STATE(ga_point_s0, always, 5, 0); - r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4); + r600->hw.ga_point_s0.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_POINT_S0, 4); ALLOC_STATE(ga_triangle_stipple, always, 2, 0); - r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1); - ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0); - r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1); + r600->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_TRIANGLE_STIPPLE, 1); + ALLOC_STATE(ps, always, R600_PS_CMDSIZE, 0); + r600->hw.ps.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_POINT_SIZE, 1); ALLOC_STATE(ga_point_minmax, always, 4, 0); - r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3); + r600->hw.ga_point_minmax.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_POINT_MINMAX, 3); ALLOC_STATE(lcntl, always, 2, 0); - r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1); + r600->hw.lcntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_LINE_CNTL, 1); ALLOC_STATE(ga_line_stipple, always, 4, 0); - r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3); + r600->hw.ga_line_stipple.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_LINE_STIPPLE_VALUE, 3); ALLOC_STATE(shade, always, 5, 0); - r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 4); + r600->hw.shade.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_ENHANCE, 4); ALLOC_STATE(polygon_mode, always, 4, 0); - r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3); + r600->hw.polygon_mode.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_POLY_MODE, 3); ALLOC_STATE(fogp, always, 3, 0); - r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2); + r600->hw.fogp.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_FOG_SCALE, 2); ALLOC_STATE(zbias_cntl, always, 2, 0); - r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1); - ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0); - r300->hw.zbs.cmd[R300_ZBS_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4); + r600->hw.zbias_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_TEX_WRAP, 1); + ALLOC_STATE(zbs, always, R600_ZBS_CMDSIZE, 0); + r600->hw.zbs.cmd[R600_ZBS_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_SU_POLY_OFFSET_FRONT_SCALE, 4); ALLOC_STATE(occlusion_cntl, always, 2, 0); - r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1); - ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0); - r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1); + r600->hw.occlusion_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_POLY_OFFSET_ENABLE, 1); + ALLOC_STATE(cul, always, R600_CUL_CMDSIZE, 0); + r600->hw.cul.cmd[R600_CUL_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_CULL_MODE, 1); ALLOC_STATE(su_depth_scale, always, 3, 0); - r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2); - ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0); - r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2); + r600->hw.su_depth_scale.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_DEPTH_SCALE, 2); + ALLOC_STATE(rc, always, R600_RC_CMDSIZE, 0); + r600->hw.rc.cmd[R600_RC_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_COUNT, 2); if (is_r500) { ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0); - r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16); + r600->hw.ri.cmd[R600_RI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R500_RS_IP_0, 16); for (i = 0; i < 8; i++) { - r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] = + r600->hw.ri.cmd[R600_RI_CMD_0 + i +1] = (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT); } - ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0); - r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1); + ALLOC_STATE(rr, variable, R600_RR_CMDSIZE, 0); + r600->hw.rr.cmd[R600_RR_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R500_RS_INST_0, 1); } else { - ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0); - r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8); - ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0); - r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1); + ALLOC_STATE(ri, always, R600_RI_CMDSIZE, 0); + r600->hw.ri.cmd[R600_RI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_IP_0, 8); + ALLOC_STATE(rr, variable, R600_RR_CMDSIZE, 0); + r600->hw.rr.cmd[R600_RR_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_INST_0, 1); } ALLOC_STATE(sc_hyperz, always, 3, 0); - r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2); + r600->hw.sc_hyperz.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SC_HYPERZ, 2); ALLOC_STATE(sc_screendoor, always, 2, 0); - r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1); + r600->hw.sc_screendoor.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SC_SCREENDOOR, 1); ALLOC_STATE(us_out_fmt, always, 6, 0); - r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5); + r600->hw.us_out_fmt.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_OUT_FMT, 5); if (is_r500) { ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0); - r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2); - r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO; - r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3); - r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1); - r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */ + r600->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R500_US_CONFIG, 2); + r600->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO; + r600->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r600->radeon.radeonScreen, R500_US_CODE_ADDR, 3); + r600->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r600->radeon.radeonScreen, R500_US_FC_CTRL, 1); + r600->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */ ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0); - r300->hw.r500fp.cmd[R300_FPI_CMD_0] = - cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0); - r300->hw.r500fp.emit = emit_r500fp; + r600->hw.r500fp.cmd[R600_FPI_CMD_0] = + cmdr500fp(r600->radeon.radeonScreen, 0, 0, 0, 0); + r600->hw.r500fp.emit = emit_r500fp; ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0); - r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] = - cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0); - r300->hw.r500fp_const.emit = emit_r500fp; + r600->hw.r500fp_const.cmd[R600_FPI_CMD_0] = + cmdr500fp(r600->radeon.radeonScreen, 0, 0, 1, 0); + r600->hw.r500fp_const.emit = emit_r500fp; } else { - ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0); - r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3); - r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4); - - ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0); - r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0); - - ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0); - r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1); - ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1); - r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1); - ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2); - r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1); - ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3); - r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1); - ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0); - r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0); + ALLOC_STATE(fp, always, R600_FP_CMDSIZE, 0); + r600->hw.fp.cmd[R600_FP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_CONFIG, 3); + r600->hw.fp.cmd[R600_FP_CMD_1] = cmdpacket0(r600->radeon.radeonScreen, R600_US_CODE_ADDR_0, 4); + + ALLOC_STATE(fpt, variable, R600_FPT_CMDSIZE, 0); + r600->hw.fpt.cmd[R600_FPT_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_TEX_INST_0, 0); + + ALLOC_STATE(fpi[0], variable, R600_FPI_CMDSIZE, 0); + r600->hw.fpi[0].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_RGB_INST_0, 1); + ALLOC_STATE(fpi[1], variable, R600_FPI_CMDSIZE, 1); + r600->hw.fpi[1].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_RGB_ADDR_0, 1); + ALLOC_STATE(fpi[2], variable, R600_FPI_CMDSIZE, 2); + r600->hw.fpi[2].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_ALPHA_INST_0, 1); + ALLOC_STATE(fpi[3], variable, R600_FPI_CMDSIZE, 3); + r600->hw.fpi[3].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_ALPHA_ADDR_0, 1); + ALLOC_STATE(fpp, variable, R600_FPP_CMDSIZE, 0); + r600->hw.fpp.cmd[R600_FPP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_PFS_PARAM_0_X, 0); } - ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0); - r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1); - ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0); - r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3); - ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0); - r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2); + ALLOC_STATE(fogs, always, R600_FOGS_CMDSIZE, 0); + r600->hw.fogs.cmd[R600_FOGS_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_FOG_BLEND, 1); + ALLOC_STATE(fogc, always, R600_FOGC_CMDSIZE, 0); + r600->hw.fogc.cmd[R600_FOGC_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_FOG_COLOR_R, 3); + ALLOC_STATE(at, always, R600_AT_CMDSIZE, 0); + r600->hw.at.cmd[R600_AT_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_ALPHA_FUNC, 2); ALLOC_STATE(fg_depth_src, always, 2, 0); - r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1); + r600->hw.fg_depth_src.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_DEPTH_SRC, 1); ALLOC_STATE(rb3d_cctl, always, 2, 0); - r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1); - ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0); - r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2); - ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0); - r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1); + r600->hw.rb3d_cctl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_CCTL, 1); + ALLOC_STATE(bld, always, R600_BLD_CMDSIZE, 0); + r600->hw.bld.cmd[R600_BLD_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_CBLEND, 2); + ALLOC_STATE(cmk, always, R600_CMK_CMDSIZE, 0); + r600->hw.cmk.cmd[R600_CMK_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1); if (is_r500) { ALLOC_STATE(blend_color, always, 3, 0); - r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2); + r600->hw.blend_color.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2); } else { ALLOC_STATE(blend_color, always, 2, 0); - r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1); + r600->hw.blend_color.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_BLEND_COLOR, 1); } ALLOC_STATE(rop, always, 2, 0); - r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1); - ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0); - r300->hw.cb.emit = &emit_cb_offset; + r600->hw.rop.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_ROPCNTL, 1); + ALLOC_STATE(cb, always, R600_CB_CMDSIZE, 0); + r600->hw.cb.emit = &emit_cb_offset; ALLOC_STATE(rb3d_dither_ctl, always, 10, 0); - r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9); + r600->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_DITHER_CTL, 9); ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0); - r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1); + r600->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_AARESOLVE_CTL, 1); ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0); - r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2); - ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0); - r300->hw.zs.cmd[R300_ZS_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3); + r600->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2); + ALLOC_STATE(zs, always, R600_ZS_CMDSIZE, 0); + r600->hw.zs.cmd[R600_ZS_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_ZB_CNTL, 3); ALLOC_STATE(zstencil_format, always, 5, 0); - r300->hw.zstencil_format.cmd[0] = - cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4); - r300->hw.zstencil_format.emit = emit_zstencil_format; + r600->hw.zstencil_format.cmd[0] = + cmdpacket0(r600->radeon.radeonScreen, R600_ZB_FORMAT, 4); + r600->hw.zstencil_format.emit = emit_zstencil_format; - ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0); - r300->hw.zb.emit = emit_zb_offset; + ALLOC_STATE(zb, always, R600_ZB_CMDSIZE, 0); + r600->hw.zb.emit = emit_zb_offset; ALLOC_STATE(zb_depthclearvalue, always, 2, 0); - r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1); + r600->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_ZB_DEPTHCLEARVALUE, 1); ALLOC_STATE(unk4F30, always, 3, 0); - r300->hw.unk4F30.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4F30, 2); + r600->hw.unk4F30.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, 0x4F30, 2); ALLOC_STATE(zb_hiz_offset, always, 2, 0); - r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1); + r600->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_ZB_HIZ_OFFSET, 1); ALLOC_STATE(zb_hiz_pitch, always, 2, 0); - r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1); + r600->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_ZB_HIZ_PITCH, 1); /* VPU only on TCL */ if (has_tcl) { int i; - ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0); - r300->hw.vpi.cmd[0] = - cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0); - r300->hw.vpi.emit = emit_vpu; + ALLOC_STATE(vpi, vpu, R600_VPI_CMDSIZE, 0); + r600->hw.vpi.cmd[0] = + cmdvpu(r600->radeon.radeonScreen, R600_PVS_CODE_START, 0); + r600->hw.vpi.emit = emit_vpu; if (is_r500) { - ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0); - r300->hw.vpp.cmd[0] = - cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0); - r300->hw.vpp.emit = emit_vpu; + ALLOC_STATE(vpp, vpu, R600_VPP_CMDSIZE, 0); + r600->hw.vpp.cmd[0] = + cmdvpu(r600->radeon.radeonScreen, R500_PVS_CONST_START, 0); + r600->hw.vpp.emit = emit_vpu; - ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0); - r300->hw.vps.cmd[0] = - cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1); - r300->hw.vps.emit = emit_vpu; + ALLOC_STATE(vps, vpu, R600_VPS_CMDSIZE, 0); + r600->hw.vps.cmd[0] = + cmdvpu(r600->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1); + r600->hw.vps.emit = emit_vpu; for (i = 0; i < 6; i++) { - ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0); - r300->hw.vpucp[i].cmd[0] = - cmdvpu(r300->radeon.radeonScreen, + ALLOC_STATE(vpucp[i], vpu, R600_VPUCP_CMDSIZE, 0); + r600->hw.vpucp[i].cmd[0] = + cmdvpu(r600->radeon.radeonScreen, R500_PVS_UCP_START + i, 1); - r300->hw.vpucp[i].emit = emit_vpu; + r600->hw.vpucp[i].emit = emit_vpu; } } else { - ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0); - r300->hw.vpp.cmd[0] = - cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0); - r300->hw.vpp.emit = emit_vpu; + ALLOC_STATE(vpp, vpu, R600_VPP_CMDSIZE, 0); + r600->hw.vpp.cmd[0] = + cmdvpu(r600->radeon.radeonScreen, R600_PVS_CONST_START, 0); + r600->hw.vpp.emit = emit_vpu; - ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0); - r300->hw.vps.cmd[0] = - cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1); - r300->hw.vps.emit = emit_vpu; + ALLOC_STATE(vps, vpu, R600_VPS_CMDSIZE, 0); + r600->hw.vps.cmd[0] = + cmdvpu(r600->radeon.radeonScreen, R600_POINT_VPORT_SCALE_OFFSET, 1); + r600->hw.vps.emit = emit_vpu; for (i = 0; i < 6; i++) { - ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0); - r300->hw.vpucp[i].cmd[0] = - cmdvpu(r300->radeon.radeonScreen, - R300_PVS_UCP_START + i, 1); - r300->hw.vpucp[i].emit = emit_vpu; + ALLOC_STATE(vpucp[i], vpu, R600_VPUCP_CMDSIZE, 0); + r600->hw.vpucp[i].cmd[0] = + cmdvpu(r600->radeon.radeonScreen, + R600_PVS_UCP_START + i, 1); + r600->hw.vpucp[i].emit = emit_vpu; } } } /* Textures */ ALLOC_STATE(tex.filter, variable, mtu + 1, 0); - r300->hw.tex.filter.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0); + r600->hw.tex.filter.cmd[R600_TEX_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_TX_FILTER0_0, 0); ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0); - r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0); + r600->hw.tex.filter_1.cmd[R600_TEX_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_TX_FILTER1_0, 0); ALLOC_STATE(tex.size, variable, mtu + 1, 0); - r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0); + r600->hw.tex.size.cmd[R600_TEX_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_TX_SIZE_0, 0); ALLOC_STATE(tex.format, variable, mtu + 1, 0); - r300->hw.tex.format.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0); + r600->hw.tex.format.cmd[R600_TEX_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_TX_FORMAT_0, 0); ALLOC_STATE(tex.pitch, variable, mtu + 1, 0); - r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0); + r600->hw.tex.pitch.cmd[R600_TEX_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_TX_FORMAT2_0, 0); ALLOC_STATE(tex.offset, variable, 1, 0); - r300->hw.tex.offset.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0); - r300->hw.tex.offset.emit = &emit_tex_offsets; + r600->hw.tex.offset.cmd[R600_TEX_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_TX_OFFSET_0, 0); + r600->hw.tex.offset.emit = &emit_tex_offsets; ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0); - r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0); + r600->hw.tex.chroma_key.cmd[R600_TEX_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_TX_CHROMA_KEY_0, 0); ALLOC_STATE(tex.border_color, variable, mtu + 1, 0); - r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0); + r600->hw.tex.border_color.cmd[R600_TEX_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_TX_BORDER_COLOR_0, 0); - r300->radeon.hw.is_dirty = GL_TRUE; - r300->radeon.hw.all_dirty = GL_TRUE; + r600->radeon.hw.is_dirty = GL_TRUE; + r600->radeon.hw.all_dirty = GL_TRUE; - rcommonInitCmdBuf(&r300->radeon); + rcommonInitCmdBuf(&r600->radeon); } diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.h b/src/mesa/drivers/dri/r600/r600_cmdbuf.h index eeaca96fdf..6a921a23f6 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.h +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.h @@ -38,7 +38,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r600_context.h" -extern void r300InitCmdBuf(r300ContextPtr r300); +extern void r600InitCmdBuf(r600ContextPtr r600); void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom); int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom); diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 0b351b1237..60b14fb706 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -155,14 +155,14 @@ const struct dri_extension gl_20_extension[] = { }; -extern struct tnl_pipeline_stage _r300_render_stage; -extern const struct tnl_pipeline_stage _r300_tcl_stage; +extern struct tnl_pipeline_stage _r600_render_stage; +extern const struct tnl_pipeline_stage _r600_tcl_stage; -static const struct tnl_pipeline_stage *r300_pipeline[] = { +static const struct tnl_pipeline_stage *r600_pipeline[] = { /* Try and go straight to t&l */ - &_r300_tcl_stage, + &_r600_tcl_stage, /* Catch any t&l fallbacks */ @@ -186,12 +186,12 @@ static const struct tnl_pipeline_stage *r300_pipeline[] = { /* Else do them here. */ - &_r300_render_stage, + &_r600_render_stage, &_tnl_render_stage, /* FALLBACK */ 0, }; -static void r300RunPipeline(GLcontext * ctx) +static void r600RunPipeline(GLcontext * ctx) { _mesa_lock_context_textures(ctx); @@ -202,7 +202,7 @@ static void r300RunPipeline(GLcontext * ctx) _mesa_unlock_context_textures(ctx); } -static void r300_get_lock(radeonContextPtr rmesa) +static void r600_get_lock(radeonContextPtr rmesa) { drm_radeon_sarea_t *sarea = rmesa->sarea; @@ -213,79 +213,79 @@ static void r300_get_lock(radeonContextPtr rmesa) } } -static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) +static void r600_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) { /* please flush pipe do all pending work */ radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, - R300_SC_SCREENDOOR, 1)); + R600_SC_SCREENDOOR, 1)); radeon_cs_write_dword(cs, 0x0); radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, - R300_SC_SCREENDOOR, 1)); + R600_SC_SCREENDOOR, 1)); radeon_cs_write_dword(cs, 0x00FFFFFF); radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, - R300_SC_HYPERZ, 1)); + R600_SC_HYPERZ, 1)); radeon_cs_write_dword(cs, 0x0); radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, - R300_US_CONFIG, 1)); + R600_US_CONFIG, 1)); radeon_cs_write_dword(cs, 0x0); radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, - R300_ZB_CNTL, 1)); + R600_ZB_CNTL, 1)); radeon_cs_write_dword(cs, 0x0); radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D)); radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, - R300_RB3D_DSTCACHE_CTLSTAT, 1)); - radeon_cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); + R600_RB3D_DSTCACHE_CTLSTAT, 1)); + radeon_cs_write_dword(cs, R600_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, - R300_ZB_ZCACHE_CTLSTAT, 1)); - radeon_cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE); + R600_ZB_ZCACHE_CTLSTAT, 1)); + radeon_cs_write_dword(cs, R600_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE); radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D | R300_WAIT_3D_CLEAN)); } -static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon) +static void r600_vtbl_pre_emit_atoms(radeonContextPtr radeon) { - r300ContextPtr r300 = (r300ContextPtr)radeon; + r600ContextPtr r600 = (r600ContextPtr)radeon; BATCH_LOCALS(radeon); - r300->vap_flush_needed = GL_TRUE; + r600->vap_flush_needed = GL_TRUE; cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN); BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH); + OUT_BATCH_REGVAL(R600_TX_INVALTAGS, R600_TX_FLUSH); END_BATCH(); end_3d(radeon); } -static void r300_fallback(GLcontext *ctx, GLuint bit, GLboolean mode) +static void r600_fallback(GLcontext *ctx, GLuint bit, GLboolean mode) { - r300ContextPtr r300 = R300_CONTEXT(ctx); + r600ContextPtr r600 = R600_CONTEXT(ctx); if (mode) - r300->radeon.Fallback |= bit; + r600->radeon.Fallback |= bit; else - r300->radeon.Fallback &= ~bit; + r600->radeon.Fallback &= ~bit; } -static void r300_init_vtbl(radeonContextPtr radeon) +static void r600_init_vtbl(radeonContextPtr radeon) { - radeon->vtbl.get_lock = r300_get_lock; - radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset; - radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header; - radeon->vtbl.swtcl_flush = r300_swtcl_flush; - radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms; - radeon->vtbl.fallback = r300_fallback; + radeon->vtbl.get_lock = r600_get_lock; + radeon->vtbl.update_viewport_offset = r600UpdateViewportOffset; + radeon->vtbl.emit_cs_header = r600_vtbl_emit_cs_header; + radeon->vtbl.swtcl_flush = r600_swtcl_flush; + radeon->vtbl.pre_emit_atoms = r600_vtbl_pre_emit_atoms; + radeon->vtbl.fallback = r600_fallback; } /* Create the device specific rendering context. */ -GLboolean r300CreateContext(const __GLcontextModes * glVisual, +GLboolean r600CreateContext(const __GLcontextModes * glVisual, __DRIcontextPrivate * driContextPriv, void *sharedContextPrivate) { __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); struct dd_function_table functions; - r300ContextPtr r300; + r600ContextPtr r600; GLcontext *ctx; int tcl_mode; @@ -293,52 +293,52 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, assert(driContextPriv); assert(screen); - /* Allocate the R300 context */ - r300 = (r300ContextPtr) CALLOC(sizeof(*r300)); - if (!r300) + /* Allocate the R600 context */ + r600 = (r600ContextPtr) CALLOC(sizeof(*r600)); + if (!r600) return GL_FALSE; if (!(screen->chip_flags & RADEON_CHIPSET_TCL)) hw_tcl_on = future_hw_tcl_on = 0; - r300_init_vtbl(&r300->radeon); + r600_init_vtbl(&r600->radeon); /* Parse configuration files. * Do this here so that initialMaxAnisotropy is set before we create * the default textures. */ - driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache, - screen->driScreen->myNum, "r300"); - r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, + driParseConfigFiles(&r600->radeon.optionCache, &screen->optionCache, + screen->driScreen->myNum, "r600"); + r600->radeon.initialMaxAnisotropy = driQueryOptionf(&r600->radeon.optionCache, "def_max_anisotropy"); - /* Init default driver functions then plug in our R300-specific functions + /* Init default driver functions then plug in our R600-specific functions * (the texture functions are especially important) */ _mesa_init_driver_functions(&functions); - r300InitIoctlFuncs(&functions); - r300InitStateFuncs(&functions); - r300InitTextureFuncs(&functions); - r300InitShaderFuncs(&functions); + r600InitIoctlFuncs(&functions); + r600InitStateFuncs(&functions); + r600InitTextureFuncs(&functions); + r600InitShaderFuncs(&functions); - if (!radeonInitContext(&r300->radeon, &functions, + if (!radeonInitContext(&r600->radeon, &functions, glVisual, driContextPriv, sharedContextPrivate)) { - FREE(r300); + FREE(r600); return GL_FALSE; } - /* Init r300 context data */ + /* Init r600 context data */ /* Set the maximum texture size small enough that we can guarentee that * all texture units can bind a maximal texture and have them both in * texturable memory at once. */ - ctx = r300->radeon.glCtx; + ctx = r600->radeon.glCtx; ctx->Const.MaxTextureImageUnits = - driQueryOptioni(&r300->radeon.optionCache, "texture_image_units"); + driQueryOptioni(&r600->radeon.optionCache, "texture_image_units"); ctx->Const.MaxTextureCoordUnits = - driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units"); + driQueryOptioni(&r600->radeon.optionCache, "texture_coord_units"); ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureImageUnits, ctx->Const.MaxTextureCoordUnits); @@ -352,13 +352,13 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, ctx->Const.MinPointSize = 1.0; ctx->Const.MinPointSizeAA = 1.0; - ctx->Const.MaxPointSize = R300_POINTSIZE_MAX; - ctx->Const.MaxPointSizeAA = R300_POINTSIZE_MAX; + ctx->Const.MaxPointSize = R600_POINTSIZE_MAX; + ctx->Const.MaxPointSizeAA = R600_POINTSIZE_MAX; ctx->Const.MinLineWidth = 1.0; ctx->Const.MinLineWidthAA = 1.0; - ctx->Const.MaxLineWidth = R300_LINESIZE_MAX; - ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX; + ctx->Const.MaxLineWidth = R600_LINESIZE_MAX; + ctx->Const.MaxLineWidthAA = R600_LINESIZE_MAX; /* Needs further modifications */ #if 0 @@ -380,7 +380,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, /* Install the customized pipeline: */ _tnl_destroy_pipeline(ctx); - _tnl_install_pipeline(ctx, r300_pipeline); + _tnl_install_pipeline(ctx, r600_pipeline); /* Try and keep materials and vertices separate: */ @@ -420,50 +420,50 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE; driInitExtensions(ctx, card_extensions, GL_TRUE); - if (r300->radeon.radeonScreen->kernel_mm) + if (r600->radeon.radeonScreen->kernel_mm) driInitExtensions(ctx, mm_extensions, GL_FALSE); if (driQueryOptionb - (&r300->radeon.optionCache, "disable_stencil_two_side")) + (&r600->radeon.optionCache, "disable_stencil_two_side")) _mesa_disable_extension(ctx, "GL_EXT_stencil_two_side"); - if (r300->radeon.glCtx->Mesa_DXTn - && !driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc")) { + if (r600->radeon.glCtx->Mesa_DXTn + && !driQueryOptionb(&r600->radeon.optionCache, "disable_s3tc")) { _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc"); _mesa_enable_extension(ctx, "GL_S3_s3tc"); } else - if (driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable")) + if (driQueryOptionb(&r600->radeon.optionCache, "force_s3tc_enable")) { _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc"); } - r300->disable_lowimpact_fallback = - driQueryOptionb(&r300->radeon.optionCache, + r600->disable_lowimpact_fallback = + driQueryOptionb(&r600->radeon.optionCache, "disable_lowimpact_fallback"); - radeon_fbo_init(&r300->radeon); + radeon_fbo_init(&r600->radeon); radeonInitSpanFuncs( ctx ); - r300InitCmdBuf(r300); - r300InitState(r300); + r600InitCmdBuf(r600); + r600InitState(r600); if (!(screen->chip_flags & RADEON_CHIPSET_TCL)) - r300InitSwtcl(ctx); + r600InitSwtcl(ctx); - TNL_CONTEXT(ctx)->Driver.RunPipeline = r300RunPipeline; + TNL_CONTEXT(ctx)->Driver.RunPipeline = r600RunPipeline; - tcl_mode = driQueryOptioni(&r300->radeon.optionCache, "tcl_mode"); - if (driQueryOptionb(&r300->radeon.optionCache, "no_rast")) { + tcl_mode = driQueryOptioni(&r600->radeon.optionCache, "tcl_mode"); + if (driQueryOptionb(&r600->radeon.optionCache, "no_rast")) { fprintf(stderr, "disabling 3D acceleration\n"); #if R200_MERGED - FALLBACK(&r300->radeon, RADEON_FALLBACK_DISABLE, 1); + FALLBACK(&r600->radeon, RADEON_FALLBACK_DISABLE, 1); #endif } if (tcl_mode == DRI_CONF_TCL_SW || - !(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { - if (r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { - r300->radeon.radeonScreen->chip_flags &= + !(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { + if (r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { + r600->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL; fprintf(stderr, "Disabling HW TCL support\n"); } - TCL_FALLBACK(r300->radeon.glCtx, + TCL_FALLBACK(r600->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1); } diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index 0d713f7635..0decf5d6a9 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -48,9 +48,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/mtypes.h" #include "main/colormac.h" -struct r300_context; -typedef struct r300_context r300ContextRec; -typedef struct r300_context *r300ContextPtr; +struct r600_context; +typedef struct r600_context r600ContextRec; +typedef struct r600_context *r600ContextPtr; #include "main/mm.h" @@ -80,116 +80,116 @@ typedef struct r300_context *r300ContextPtr; /* The blit width for texture uploads */ -#define R300_BLIT_WIDTH_BYTES 1024 -#define R300_MAX_TEXTURE_UNITS 8 +#define R600_BLIT_WIDTH_BYTES 1024 +#define R600_MAX_TEXTURE_UNITS 8 -struct r300_texture_state { +struct r600_texture_state { int tc_count; /* number of incoming texture coordinates from VAP */ }; -#define R300_VPT_CMD_0 0 -#define R300_VPT_XSCALE 1 -#define R300_VPT_XOFFSET 2 -#define R300_VPT_YSCALE 3 -#define R300_VPT_YOFFSET 4 -#define R300_VPT_ZSCALE 5 -#define R300_VPT_ZOFFSET 6 -#define R300_VPT_CMDSIZE 7 - -#define R300_VIR_CMD_0 0 /* vir is variable size (at least 1) */ -#define R300_VIR_CNTL_0 1 -#define R300_VIR_CNTL_1 2 -#define R300_VIR_CNTL_2 3 -#define R300_VIR_CNTL_3 4 -#define R300_VIR_CNTL_4 5 -#define R300_VIR_CNTL_5 6 -#define R300_VIR_CNTL_6 7 -#define R300_VIR_CNTL_7 8 -#define R300_VIR_CMDSIZE 9 - -#define R300_VIC_CMD_0 0 -#define R300_VIC_CNTL_0 1 -#define R300_VIC_CNTL_1 2 -#define R300_VIC_CMDSIZE 3 - -#define R300_VOF_CMD_0 0 -#define R300_VOF_CNTL_0 1 -#define R300_VOF_CNTL_1 2 -#define R300_VOF_CMDSIZE 3 - -#define R300_PVS_CMD_0 0 -#define R300_PVS_CNTL_1 1 -#define R300_PVS_CNTL_2 2 -#define R300_PVS_CNTL_3 3 -#define R300_PVS_CMDSIZE 4 - -#define R300_GB_MISC_CMD_0 0 -#define R300_GB_MISC_MSPOS_0 1 -#define R300_GB_MISC_MSPOS_1 2 -#define R300_GB_MISC_TILE_CONFIG 3 -#define R300_GB_MISC_SELECT 4 -#define R300_GB_MISC_AA_CONFIG 5 -#define R300_GB_MISC_CMDSIZE 6 - -#define R300_TXE_CMD_0 0 -#define R300_TXE_ENABLE 1 -#define R300_TXE_CMDSIZE 2 - -#define R300_PS_CMD_0 0 -#define R300_PS_POINTSIZE 1 -#define R300_PS_CMDSIZE 2 - -#define R300_ZBS_CMD_0 0 -#define R300_ZBS_T_FACTOR 1 -#define R300_ZBS_T_CONSTANT 2 -#define R300_ZBS_W_FACTOR 3 -#define R300_ZBS_W_CONSTANT 4 -#define R300_ZBS_CMDSIZE 5 - -#define R300_CUL_CMD_0 0 -#define R300_CUL_CULL 1 -#define R300_CUL_CMDSIZE 2 - -#define R300_RC_CMD_0 0 -#define R300_RC_CNTL_0 1 -#define R300_RC_CNTL_1 2 -#define R300_RC_CMDSIZE 3 - -#define R300_RI_CMD_0 0 -#define R300_RI_INTERP_0 1 -#define R300_RI_INTERP_1 2 -#define R300_RI_INTERP_2 3 -#define R300_RI_INTERP_3 4 -#define R300_RI_INTERP_4 5 -#define R300_RI_INTERP_5 6 -#define R300_RI_INTERP_6 7 -#define R300_RI_INTERP_7 8 -#define R300_RI_CMDSIZE 9 +#define R600_VPT_CMD_0 0 +#define R600_VPT_XSCALE 1 +#define R600_VPT_XOFFSET 2 +#define R600_VPT_YSCALE 3 +#define R600_VPT_YOFFSET 4 +#define R600_VPT_ZSCALE 5 +#define R600_VPT_ZOFFSET 6 +#define R600_VPT_CMDSIZE 7 + +#define R600_VIR_CMD_0 0 /* vir is variable size (at least 1) */ +#define R600_VIR_CNTL_0 1 +#define R600_VIR_CNTL_1 2 +#define R600_VIR_CNTL_2 3 +#define R600_VIR_CNTL_3 4 +#define R600_VIR_CNTL_4 5 +#define R600_VIR_CNTL_5 6 +#define R600_VIR_CNTL_6 7 +#define R600_VIR_CNTL_7 8 +#define R600_VIR_CMDSIZE 9 + +#define R600_VIC_CMD_0 0 +#define R600_VIC_CNTL_0 1 +#define R600_VIC_CNTL_1 2 +#define R600_VIC_CMDSIZE 3 + +#define R600_VOF_CMD_0 0 +#define R600_VOF_CNTL_0 1 +#define R600_VOF_CNTL_1 2 +#define R600_VOF_CMDSIZE 3 + +#define R600_PVS_CMD_0 0 +#define R600_PVS_CNTL_1 1 +#define R600_PVS_CNTL_2 2 +#define R600_PVS_CNTL_3 3 +#define R600_PVS_CMDSIZE 4 + +#define R600_GB_MISC_CMD_0 0 +#define R600_GB_MISC_MSPOS_0 1 +#define R600_GB_MISC_MSPOS_1 2 +#define R600_GB_MISC_TILE_CONFIG 3 +#define R600_GB_MISC_SELECT 4 +#define R600_GB_MISC_AA_CONFIG 5 +#define R600_GB_MISC_CMDSIZE 6 + +#define R600_TXE_CMD_0 0 +#define R600_TXE_ENABLE 1 +#define R600_TXE_CMDSIZE 2 + +#define R600_PS_CMD_0 0 +#define R600_PS_POINTSIZE 1 +#define R600_PS_CMDSIZE 2 + +#define R600_ZBS_CMD_0 0 +#define R600_ZBS_T_FACTOR 1 +#define R600_ZBS_T_CONSTANT 2 +#define R600_ZBS_W_FACTOR 3 +#define R600_ZBS_W_CONSTANT 4 +#define R600_ZBS_CMDSIZE 5 + +#define R600_CUL_CMD_0 0 +#define R600_CUL_CULL 1 +#define R600_CUL_CMDSIZE 2 + +#define R600_RC_CMD_0 0 +#define R600_RC_CNTL_0 1 +#define R600_RC_CNTL_1 2 +#define R600_RC_CMDSIZE 3 + +#define R600_RI_CMD_0 0 +#define R600_RI_INTERP_0 1 +#define R600_RI_INTERP_1 2 +#define R600_RI_INTERP_2 3 +#define R600_RI_INTERP_3 4 +#define R600_RI_INTERP_4 5 +#define R600_RI_INTERP_5 6 +#define R600_RI_INTERP_6 7 +#define R600_RI_INTERP_7 8 +#define R600_RI_CMDSIZE 9 #define R500_RI_CMDSIZE 17 -#define R300_RR_CMD_0 0 /* rr is variable size (at least 1) */ -#define R300_RR_INST_0 1 -#define R300_RR_INST_1 2 -#define R300_RR_INST_2 3 -#define R300_RR_INST_3 4 -#define R300_RR_INST_4 5 -#define R300_RR_INST_5 6 -#define R300_RR_INST_6 7 -#define R300_RR_INST_7 8 -#define R300_RR_CMDSIZE 9 - -#define R300_FP_CMD_0 0 -#define R300_FP_CNTL0 1 -#define R300_FP_CNTL1 2 -#define R300_FP_CNTL2 3 -#define R300_FP_CMD_1 4 -#define R300_FP_NODE0 5 -#define R300_FP_NODE1 6 -#define R300_FP_NODE2 7 -#define R300_FP_NODE3 8 -#define R300_FP_CMDSIZE 9 +#define R600_RR_CMD_0 0 /* rr is variable size (at least 1) */ +#define R600_RR_INST_0 1 +#define R600_RR_INST_1 2 +#define R600_RR_INST_2 3 +#define R600_RR_INST_3 4 +#define R600_RR_INST_4 5 +#define R600_RR_INST_5 6 +#define R600_RR_INST_6 7 +#define R600_RR_INST_7 8 +#define R600_RR_CMDSIZE 9 + +#define R600_FP_CMD_0 0 +#define R600_FP_CNTL0 1 +#define R600_FP_CNTL1 2 +#define R600_FP_CNTL2 3 +#define R600_FP_CMD_1 4 +#define R600_FP_NODE0 5 +#define R600_FP_NODE1 6 +#define R600_FP_NODE2 7 +#define R600_FP_NODE3 8 +#define R600_FP_CMDSIZE 9 #define R500_FP_CMD_0 0 #define R500_FP_CNTL 1 @@ -202,107 +202,107 @@ struct r300_texture_state { #define R500_FP_FC_CNTL 8 #define R500_FP_CMDSIZE 9 -#define R300_FPT_CMD_0 0 -#define R300_FPT_INSTR_0 1 -#define R300_FPT_CMDSIZE 65 +#define R600_FPT_CMD_0 0 +#define R600_FPT_INSTR_0 1 +#define R600_FPT_CMDSIZE 65 -#define R300_FPI_CMD_0 0 -#define R300_FPI_INSTR_0 1 -#define R300_FPI_CMDSIZE 65 +#define R600_FPI_CMD_0 0 +#define R600_FPI_INSTR_0 1 +#define R600_FPI_CMDSIZE 65 /* R500 has space for 512 instructions - 6 dwords per instruction */ #define R500_FPI_CMDSIZE (512*6+1) -#define R300_FPP_CMD_0 0 -#define R300_FPP_PARAM_0 1 -#define R300_FPP_CMDSIZE (32*4+1) +#define R600_FPP_CMD_0 0 +#define R600_FPP_PARAM_0 1 +#define R600_FPP_CMDSIZE (32*4+1) /* R500 has spcae for 256 constants - 4 dwords per constant */ #define R500_FPP_CMDSIZE (256*4+1) -#define R300_FOGS_CMD_0 0 -#define R300_FOGS_STATE 1 -#define R300_FOGS_CMDSIZE 2 - -#define R300_FOGC_CMD_0 0 -#define R300_FOGC_R 1 -#define R300_FOGC_G 2 -#define R300_FOGC_B 3 -#define R300_FOGC_CMDSIZE 4 - -#define R300_FOGP_CMD_0 0 -#define R300_FOGP_SCALE 1 -#define R300_FOGP_START 2 -#define R300_FOGP_CMDSIZE 3 - -#define R300_AT_CMD_0 0 -#define R300_AT_ALPHA_TEST 1 -#define R300_AT_UNKNOWN 2 -#define R300_AT_CMDSIZE 3 - -#define R300_BLD_CMD_0 0 -#define R300_BLD_CBLEND 1 -#define R300_BLD_ABLEND 2 -#define R300_BLD_CMDSIZE 3 - -#define R300_CMK_CMD_0 0 -#define R300_CMK_COLORMASK 1 -#define R300_CMK_CMDSIZE 2 - -#define R300_CB_CMD_0 0 -#define R300_CB_OFFSET 1 -#define R300_CB_CMD_1 2 -#define R300_CB_PITCH 3 -#define R300_CB_CMDSIZE 4 - -#define R300_ZS_CMD_0 0 -#define R300_ZS_CNTL_0 1 -#define R300_ZS_CNTL_1 2 -#define R300_ZS_CNTL_2 3 -#define R300_ZS_CMDSIZE 4 - -#define R300_ZB_CMD_0 0 -#define R300_ZB_OFFSET 1 -#define R300_ZB_PITCH 2 -#define R300_ZB_CMDSIZE 3 - -#define R300_VAP_CNTL_FLUSH 0 -#define R300_VAP_CNTL_FLUSH_1 1 -#define R300_VAP_CNTL_CMD 2 -#define R300_VAP_CNTL_INSTR 3 -#define R300_VAP_CNTL_SIZE 4 - -#define R300_VPI_CMD_0 0 -#define R300_VPI_INSTR_0 1 -#define R300_VPI_CMDSIZE 1025 /* 256 16 byte instructions */ - -#define R300_VPP_CMD_0 0 -#define R300_VPP_PARAM_0 1 -#define R300_VPP_CMDSIZE 1025 /* 256 4-component parameters */ - -#define R300_VPUCP_CMD_0 0 -#define R300_VPUCP_X 1 -#define R300_VPUCP_Y 2 -#define R300_VPUCP_Z 3 -#define R300_VPUCP_W 4 -#define R300_VPUCP_CMDSIZE 5 /* 256 4-component parameters */ - -#define R300_VPS_CMD_0 0 -#define R300_VPS_ZERO_0 1 -#define R300_VPS_ZERO_1 2 -#define R300_VPS_POINTSIZE 3 -#define R300_VPS_ZERO_3 4 -#define R300_VPS_CMDSIZE 5 +#define R600_FOGS_CMD_0 0 +#define R600_FOGS_STATE 1 +#define R600_FOGS_CMDSIZE 2 + +#define R600_FOGC_CMD_0 0 +#define R600_FOGC_R 1 +#define R600_FOGC_G 2 +#define R600_FOGC_B 3 +#define R600_FOGC_CMDSIZE 4 + +#define R600_FOGP_CMD_0 0 +#define R600_FOGP_SCALE 1 +#define R600_FOGP_START 2 +#define R600_FOGP_CMDSIZE 3 + +#define R600_AT_CMD_0 0 +#define R600_AT_ALPHA_TEST 1 +#define R600_AT_UNKNOWN 2 +#define R600_AT_CMDSIZE 3 + +#define R600_BLD_CMD_0 0 +#define R600_BLD_CBLEND 1 +#define R600_BLD_ABLEND 2 +#define R600_BLD_CMDSIZE 3 + +#define R600_CMK_CMD_0 0 +#define R600_CMK_COLORMASK 1 +#define R600_CMK_CMDSIZE 2 + +#define R600_CB_CMD_0 0 +#define R600_CB_OFFSET 1 +#define R600_CB_CMD_1 2 +#define R600_CB_PITCH 3 +#define R600_CB_CMDSIZE 4 + +#define R600_ZS_CMD_0 0 +#define R600_ZS_CNTL_0 1 +#define R600_ZS_CNTL_1 2 +#define R600_ZS_CNTL_2 3 +#define R600_ZS_CMDSIZE 4 + +#define R600_ZB_CMD_0 0 +#define R600_ZB_OFFSET 1 +#define R600_ZB_PITCH 2 +#define R600_ZB_CMDSIZE 3 + +#define R600_VAP_CNTL_FLUSH 0 +#define R600_VAP_CNTL_FLUSH_1 1 +#define R600_VAP_CNTL_CMD 2 +#define R600_VAP_CNTL_INSTR 3 +#define R600_VAP_CNTL_SIZE 4 + +#define R600_VPI_CMD_0 0 +#define R600_VPI_INSTR_0 1 +#define R600_VPI_CMDSIZE 1025 /* 256 16 byte instructions */ + +#define R600_VPP_CMD_0 0 +#define R600_VPP_PARAM_0 1 +#define R600_VPP_CMDSIZE 1025 /* 256 4-component parameters */ + +#define R600_VPUCP_CMD_0 0 +#define R600_VPUCP_X 1 +#define R600_VPUCP_Y 2 +#define R600_VPUCP_Z 3 +#define R600_VPUCP_W 4 +#define R600_VPUCP_CMDSIZE 5 /* 256 4-component parameters */ + +#define R600_VPS_CMD_0 0 +#define R600_VPS_ZERO_0 1 +#define R600_VPS_ZERO_1 2 +#define R600_VPS_POINTSIZE 3 +#define R600_VPS_ZERO_3 4 +#define R600_VPS_CMDSIZE 5 /* the layout is common for all fields inside tex */ -#define R300_TEX_CMD_0 0 -#define R300_TEX_VALUE_0 1 +#define R600_TEX_CMD_0 0 +#define R600_TEX_VALUE_0 1 /* We don't really use this, instead specify mtu+1 dynamically -#define R300_TEX_CMDSIZE (MAX_TEXTURE_UNITS+1) +#define R600_TEX_CMDSIZE (MAX_TEXTURE_UNITS+1) */ /** * Cache for hardware register state. */ -struct r300_hw_state { +struct r600_hw_state { struct radeon_state_atom vpt; /* viewport (1D98) */ struct radeon_state_atom vap_cntl; struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */ @@ -388,7 +388,7 @@ struct r300_hw_state { } tex; struct radeon_state_atom txe; /* tex enable (4104) */ - radeonTexObj *textures[R300_MAX_TEXTURE_UNITS]; + radeonTexObj *textures[R600_MAX_TEXTURE_UNITS]; }; /** @@ -398,16 +398,16 @@ struct r300_hw_state { /* Vertex shader state */ /* Perhaps more if we store programs in vmem? */ -/* drm_r300_cmd_header_t->vpu->count is unsigned char */ +/* drm_r600_cmd_header_t->vpu->count is unsigned char */ #define VSF_MAX_FRAGMENT_LENGTH (255*4) /* Can be tested with colormat currently. */ #define VSF_MAX_FRAGMENT_TEMPS (14) -#define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0) -#define STATE_R300_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1) +#define STATE_R600_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0) +#define STATE_R600_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1) -struct r300_vertex_shader_fragment { +struct r600_vertex_shader_fragment { int length; union { GLuint d[VSF_MAX_FRAGMENT_LENGTH]; @@ -416,39 +416,39 @@ struct r300_vertex_shader_fragment { } body; }; -struct r300_vertex_shader_state { - struct r300_vertex_shader_fragment program; +struct r600_vertex_shader_state { + struct r600_vertex_shader_fragment program; }; extern int hw_tcl_on; #define COLOR_IS_RGBA -#define TAG(x) r300##x +#define TAG(x) r600##x #include "tnl_dd/t_dd_vertex.h" #undef TAG //#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current) -#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp) +#define CURRENT_VERTEX_SHADER(ctx) (R600_CONTEXT(ctx)->selected_vp) /* Should but doesnt work */ -//#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp) +//#define CURRENT_VERTEX_SHADER(ctx) (R600_CONTEXT(ctx)->curr_vp) -/* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday. +/* r600_vertex_shader_state and r600_vertex_program should probably be merged together someday. * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly. */ -struct r300_vertex_program_key { +struct r600_vertex_program_key { GLuint InputsRead; GLuint OutputsWritten; GLuint OutputsAdded; }; -struct r300_vertex_program { - struct r300_vertex_program *next; - struct r300_vertex_program_key key; +struct r600_vertex_program { + struct r600_vertex_program *next; + struct r600_vertex_program_key key; int translated; - struct r300_vertex_shader_fragment program; + struct r600_vertex_shader_fragment program; int pos_end; int num_temporaries; /* Number of temp vars used by program */ @@ -460,10 +460,10 @@ struct r300_vertex_program { int use_ref_count; }; -struct r300_vertex_program_cont { +struct r600_vertex_program_cont { struct gl_vertex_program mesa_program; /* Must be first */ - struct r300_vertex_shader_fragment params; - struct r300_vertex_program *progs; + struct r600_vertex_shader_fragment params; + struct r600_vertex_program *progs; }; #define PFS_MAX_ALU_INST 64 @@ -472,13 +472,13 @@ struct r300_vertex_program_cont { #define PFS_NUM_TEMP_REGS 32 #define PFS_NUM_CONST_REGS 16 -struct r300_pfs_compile_state; +struct r600_pfs_compile_state; /** * Stores state that influences the compilation of a fragment program. */ -struct r300_fragment_program_external_state { +struct r600_fragment_program_external_state { struct { /** * If the sampler is used as a shadow sampler, @@ -502,7 +502,7 @@ struct r300_fragment_program_external_state { }; -struct r300_fragment_program_node { +struct r600_fragment_program_node { int tex_offset; /**< first tex instruction */ int tex_end; /**< last tex instruction, relative to tex_offset */ int alu_offset; /**< first ALU instruction */ @@ -511,9 +511,9 @@ struct r300_fragment_program_node { }; /** - * Stores an R300 fragment program in its compiled-to-hardware form. + * Stores an R600 fragment program in its compiled-to-hardware form. */ -struct r300_fragment_program_code { +struct r600_fragment_program_code { struct { int length; /**< total # of texture instructions used */ GLuint inst[PFS_MAX_TEX_INST]; @@ -529,7 +529,7 @@ struct r300_fragment_program_code { } inst[PFS_MAX_ALU_INST]; } alu; - struct r300_fragment_program_node node[4]; + struct r600_fragment_program_node node[4]; int cur_node; int first_node_has_tex; @@ -547,14 +547,14 @@ struct r300_fragment_program_code { * Store everything about a fragment program that is needed * to render with that program. */ -struct r300_fragment_program { +struct r600_fragment_program { struct gl_fragment_program mesa_program; GLboolean translated; GLboolean error; - struct r300_fragment_program_external_state state; - struct r300_fragment_program_code code; + struct r600_fragment_program_external_state state; + struct r600_fragment_program_code code; GLboolean WritesDepth; GLuint optimization; @@ -623,30 +623,30 @@ struct r500_fragment_program { GLuint optimization; }; -#define R300_MAX_AOS_ARRAYS 16 +#define R600_MAX_AOS_ARRAYS 16 #define REG_COORDS 0 #define REG_COLOR0 1 #define REG_TEX0 2 -struct r300_state { - struct r300_texture_state texture; +struct r600_state { + struct r600_texture_state texture; int sw_tcl_inputs[VERT_ATTRIB_MAX]; - struct r300_vertex_shader_state vertex_shader; + struct r600_vertex_shader_state vertex_shader; - DECLARE_RENDERINPUTS(render_inputs_bitset); /* actual render inputs that R300 was configured for. + DECLARE_RENDERINPUTS(render_inputs_bitset); /* actual render inputs that R600 was configured for. They are the same as tnl->render_inputs for fixed pipeline */ }; -#define R300_FALLBACK_NONE 0 -#define R300_FALLBACK_TCL 1 -#define R300_FALLBACK_RAST 2 +#define R600_FALLBACK_NONE 0 +#define R600_FALLBACK_TCL 1 +#define R600_FALLBACK_RAST 2 -/* r300_swtcl.c +/* r600_swtcl.c */ -struct r300_swtcl_info { +struct r600_swtcl_info { /* * Offset of the 4UB color data within a hardware (swtcl) vertex. */ @@ -670,16 +670,16 @@ struct r300_swtcl_info { /** - * \brief R300 context structure. + * \brief R600 context structure. */ -struct r300_context { +struct r600_context { struct radeon_context radeon; /* parent class, must be first */ - struct r300_hw_state hw; + struct r600_hw_state hw; - struct r300_state state; + struct r600_state state; struct gl_vertex_program *curr_vp; - struct r300_vertex_program *selected_vp; + struct r600_vertex_program *selected_vp; /* Vertex buffers */ @@ -688,21 +688,21 @@ struct r300_context { GLboolean disable_lowimpact_fallback; - struct r300_swtcl_info swtcl; + struct r600_swtcl_info swtcl; GLboolean vap_flush_needed; }; -#define R300_CONTEXT(ctx) ((r300ContextPtr)(ctx->DriverCtx)) +#define R600_CONTEXT(ctx) ((r600ContextPtr)(ctx->DriverCtx)) -extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv); -extern GLboolean r300CreateContext(const __GLcontextModes * glVisual, +extern void r600DestroyContext(__DRIcontextPrivate * driContextPriv); +extern GLboolean r600CreateContext(const __GLcontextModes * glVisual, __DRIcontextPrivate * driContextPriv, void *sharedContextPrivate); -extern void r300SelectVertexShader(r300ContextPtr r300); -extern void r300InitShaderFuncs(struct dd_function_table *functions); -extern int r300VertexProgUpdateParams(GLcontext * ctx, - struct r300_vertex_program_cont *vp, +extern void r600SelectVertexShader(r600ContextPtr r600); +extern void r600InitShaderFuncs(struct dd_function_table *functions); +extern int r600VertexProgUpdateParams(GLcontext * ctx, + struct r600_vertex_program_cont *vp, float *dst); #define RADEON_D_CAPTURE 0 @@ -710,7 +710,7 @@ extern int r300VertexProgUpdateParams(GLcontext * ctx, #define RADEON_D_PLAYBACK_RAW 2 #define RADEON_D_T 3 -#define r300PackFloat32 radeonPackFloat32 -#define r300PackFloat24 radeonPackFloat24 +#define r600PackFloat32 radeonPackFloat32 +#define r600PackFloat24 radeonPackFloat24 -#endif /* __R300_CONTEXT_H__ */ +#endif /* __R600_CONTEXT_H__ */ diff --git a/src/mesa/drivers/dri/r600/r600_emit.c b/src/mesa/drivers/dri/r600/r600_emit.c index 4d16ad8106..7004f7a2b7 100644 --- a/src/mesa/drivers/dri/r600/r600_emit.c +++ b/src/mesa/drivers/dri/r600/r600_emit.c @@ -51,21 +51,21 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r600_ioctl.h" -#if SWIZZLE_X != R300_INPUT_ROUTE_SELECT_X || \ - SWIZZLE_Y != R300_INPUT_ROUTE_SELECT_Y || \ - SWIZZLE_Z != R300_INPUT_ROUTE_SELECT_Z || \ - SWIZZLE_W != R300_INPUT_ROUTE_SELECT_W || \ - SWIZZLE_ZERO != R300_INPUT_ROUTE_SELECT_ZERO || \ - SWIZZLE_ONE != R300_INPUT_ROUTE_SELECT_ONE +#if SWIZZLE_X != R600_INPUT_ROUTE_SELECT_X || \ + SWIZZLE_Y != R600_INPUT_ROUTE_SELECT_Y || \ + SWIZZLE_Z != R600_INPUT_ROUTE_SELECT_Z || \ + SWIZZLE_W != R600_INPUT_ROUTE_SELECT_W || \ + SWIZZLE_ZERO != R600_INPUT_ROUTE_SELECT_ZERO || \ + SWIZZLE_ONE != R600_INPUT_ROUTE_SELECT_ONE #error Cannot change these! #endif #define DEBUG_ALL DEBUG_VERTS -#define DW_SIZE(x) ((inputs[tab[(x)]] << R300_DST_VEC_LOC_SHIFT) | \ - (attribptr[tab[(x)]]->size - 1) << R300_DATA_TYPE_0_SHIFT) +#define DW_SIZE(x) ((inputs[tab[(x)]] << R600_DST_VEC_LOC_SHIFT) | \ + (attribptr[tab[(x)]]->size - 1) << R600_DATA_TYPE_0_SHIFT) -GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr, +GLuint r600VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr, int *inputs, GLint * tab, GLuint nr) { GLuint i, dw; @@ -74,15 +74,15 @@ GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr, for (i = 0; i < nr; i += 2) { /* make sure input is valid, would lockup the gpu */ assert(inputs[tab[i]] != -1); - dw = (R300_SIGNED | DW_SIZE(i)); + dw = (R600_SIGNED | DW_SIZE(i)); if (i + 1 == nr) { - dw |= R300_LAST_VEC << R300_DATA_TYPE_0_SHIFT; + dw |= R600_LAST_VEC << R600_DATA_TYPE_0_SHIFT; } else { assert(inputs[tab[i + 1]] != -1); - dw |= (R300_SIGNED | - DW_SIZE(i + 1)) << R300_DATA_TYPE_1_SHIFT; + dw |= (R600_SIGNED | + DW_SIZE(i + 1)) << R600_DATA_TYPE_1_SHIFT; if (i + 2 == nr) { - dw |= R300_LAST_VEC << R300_DATA_TYPE_1_SHIFT; + dw |= R600_LAST_VEC << R600_DATA_TYPE_1_SHIFT; } } dst[i >> 1] = dw; @@ -91,26 +91,26 @@ GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr, return (nr + 1) >> 1; } -static GLuint r300VAPInputRoute1Swizzle(int swizzle[4]) +static GLuint r600VAPInputRoute1Swizzle(int swizzle[4]) { - return (swizzle[0] << R300_SWIZZLE_SELECT_X_SHIFT) | - (swizzle[1] << R300_SWIZZLE_SELECT_Y_SHIFT) | - (swizzle[2] << R300_SWIZZLE_SELECT_Z_SHIFT) | - (swizzle[3] << R300_SWIZZLE_SELECT_W_SHIFT); + return (swizzle[0] << R600_SWIZZLE_SELECT_X_SHIFT) | + (swizzle[1] << R600_SWIZZLE_SELECT_Y_SHIFT) | + (swizzle[2] << R600_SWIZZLE_SELECT_Z_SHIFT) | + (swizzle[3] << R600_SWIZZLE_SELECT_W_SHIFT); } -GLuint r300VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr) +GLuint r600VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr) { GLuint i, dw; for (i = 0; i < nr; i += 2) { - dw = (r300VAPInputRoute1Swizzle(swizzle[i]) | - ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | - R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE0_SHIFT; + dw = (r600VAPInputRoute1Swizzle(swizzle[i]) | + ((R600_WRITE_ENA_X | R600_WRITE_ENA_Y | + R600_WRITE_ENA_Z | R600_WRITE_ENA_W) << R600_WRITE_ENA_SHIFT)) << R600_SWIZZLE0_SHIFT; if (i + 1 < nr) { - dw |= (r300VAPInputRoute1Swizzle(swizzle[i + 1]) | - ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | - R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE1_SHIFT; + dw |= (r600VAPInputRoute1Swizzle(swizzle[i + 1]) | + ((R600_WRITE_ENA_X | R600_WRITE_ENA_Y | + R600_WRITE_ENA_Z | R600_WRITE_ENA_W) << R600_WRITE_ENA_SHIFT)) << R600_SWIZZLE1_SHIFT; } dst[i >> 1] = dw; } @@ -118,64 +118,64 @@ GLuint r300VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr) return (nr + 1) >> 1; } -GLuint r300VAPInputCntl0(GLcontext * ctx, GLuint InputsRead) +GLuint r600VAPInputCntl0(GLcontext * ctx, GLuint InputsRead) { /* No idea what this value means. I have seen other values written to * this register... */ return 0x5555; } -GLuint r300VAPInputCntl1(GLcontext * ctx, GLuint InputsRead) +GLuint r600VAPInputCntl1(GLcontext * ctx, GLuint InputsRead) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); GLuint i, vic_1 = 0; if (InputsRead & (1 << VERT_ATTRIB_POS)) - vic_1 |= R300_INPUT_CNTL_POS; + vic_1 |= R600_INPUT_CNTL_POS; if (InputsRead & (1 << VERT_ATTRIB_NORMAL)) - vic_1 |= R300_INPUT_CNTL_NORMAL; + vic_1 |= R600_INPUT_CNTL_NORMAL; if (InputsRead & (1 << VERT_ATTRIB_COLOR0)) - vic_1 |= R300_INPUT_CNTL_COLOR; + vic_1 |= R600_INPUT_CNTL_COLOR; rmesa->state.texture.tc_count = 0; for (i = 0; i < ctx->Const.MaxTextureUnits; i++) if (InputsRead & (1 << (VERT_ATTRIB_TEX0 + i))) { rmesa->state.texture.tc_count++; - vic_1 |= R300_INPUT_CNTL_TC0 << i; + vic_1 |= R600_INPUT_CNTL_TC0 << i; } return vic_1; } -GLuint r300VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten) +GLuint r600VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten) { GLuint ret = 0; if (OutputsWritten & (1 << VERT_RESULT_HPOS)) - ret |= R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT; + ret |= R600_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT; if (OutputsWritten & (1 << VERT_RESULT_COL0)) - ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT; + ret |= R600_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT; if (OutputsWritten & (1 << VERT_RESULT_COL1)) - ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT; + ret |= R600_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT; if (OutputsWritten & (1 << VERT_RESULT_BFC0) || OutputsWritten & (1 << VERT_RESULT_BFC1)) ret |= - R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT | - R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT | - R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT; + R600_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT | + R600_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT | + R600_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT; if (OutputsWritten & (1 << VERT_RESULT_PSIZ)) - ret |= R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT; + ret |= R600_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT; return ret; } -GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten) +GLuint r600VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten) { GLuint i, ret = 0, first_free_texcoord = 0; @@ -199,11 +199,11 @@ GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten) /* Emit vertex data to GART memory * Route inputs to the vertex processor - * This function should never return R300_FALLBACK_TCL when using software tcl. + * This function should never return R600_FALLBACK_TCL when using software tcl. */ -int r300EmitArrays(GLcontext * ctx) +int r600EmitArrays(GLcontext * ctx) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; GLuint nr; @@ -214,8 +214,8 @@ int r300EmitArrays(GLcontext * ctx) int vir_inputs[VERT_ATTRIB_MAX]; GLint tab[VERT_ATTRIB_MAX]; int swizzle[VERT_ATTRIB_MAX][4]; - struct r300_vertex_program *prog = - (struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx); + struct r600_vertex_program *prog = + (struct r600_vertex_program *)CURRENT_VERTEX_SHADER(ctx); if (hw_tcl_on) { inputs = prog->inputs; @@ -287,8 +287,8 @@ int r300EmitArrays(GLcontext * ctx) } } - if (nr > R300_MAX_AOS_ARRAYS) { - return R300_FALLBACK_TCL; + if (nr > R600_MAX_AOS_ARRAYS) { + return R600_FALLBACK_TCL; } for (i = 0; i < nr; i++) { @@ -310,55 +310,55 @@ int r300EmitArrays(GLcontext * ctx) /* Setup INPUT_ROUTE. */ if (rmesa->radeon.radeonScreen->kernel_mm) { - R300_STATECHANGE(rmesa, vir[0]); + R600_STATECHANGE(rmesa, vir[0]); rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF; rmesa->hw.vir[1].cmd[0] &= 0xC000FFFF; rmesa->hw.vir[0].cmd[0] |= - (r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0], + (r600VAPInputRoute0(&rmesa->hw.vir[0].cmd[R600_VIR_CNTL_0], vb->AttribPtr, inputs, tab, nr) & 0x3FFF) << 16; - R300_STATECHANGE(rmesa, vir[1]); + R600_STATECHANGE(rmesa, vir[1]); rmesa->hw.vir[1].cmd[0] |= - (r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle, + (r600VAPInputRoute1(&rmesa->hw.vir[1].cmd[R600_VIR_CNTL_0], swizzle, nr) & 0x3FFF) << 16; } else { - R300_STATECHANGE(rmesa, vir[0]); + R600_STATECHANGE(rmesa, vir[0]); ((drm_r300_cmd_header_t *) rmesa->hw.vir[0].cmd)->packet0.count = - r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0], + r600VAPInputRoute0(&rmesa->hw.vir[0].cmd[R600_VIR_CNTL_0], vb->AttribPtr, inputs, tab, nr); - R300_STATECHANGE(rmesa, vir[1]); + R600_STATECHANGE(rmesa, vir[1]); ((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = - r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle, + r600VAPInputRoute1(&rmesa->hw.vir[1].cmd[R600_VIR_CNTL_0], swizzle, nr); } /* Setup INPUT_CNTL. */ - R300_STATECHANGE(rmesa, vic); - rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead); - rmesa->hw.vic.cmd[R300_VIC_CNTL_1] = r300VAPInputCntl1(ctx, InputsRead); + R600_STATECHANGE(rmesa, vic); + rmesa->hw.vic.cmd[R600_VIC_CNTL_0] = r600VAPInputCntl0(ctx, InputsRead); + rmesa->hw.vic.cmd[R600_VIC_CNTL_1] = r600VAPInputCntl1(ctx, InputsRead); /* Setup OUTPUT_VTX_FMT. */ - R300_STATECHANGE(rmesa, vof); - rmesa->hw.vof.cmd[R300_VOF_CNTL_0] = - r300VAPOutputCntl0(ctx, OutputsWritten); - rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = - r300VAPOutputCntl1(ctx, OutputsWritten); + R600_STATECHANGE(rmesa, vof); + rmesa->hw.vof.cmd[R600_VOF_CNTL_0] = + r600VAPOutputCntl0(ctx, OutputsWritten); + rmesa->hw.vof.cmd[R600_VOF_CNTL_1] = + r600VAPOutputCntl1(ctx, OutputsWritten); rmesa->radeon.tcl.aos_count = nr; - return R300_FALLBACK_NONE; + return R600_FALLBACK_NONE; } -void r300EmitCacheFlush(r300ContextPtr rmesa) +void r600EmitCacheFlush(r600ContextPtr rmesa) { BATCH_LOCALS(&rmesa->radeon); BEGIN_BATCH_NO_AUTOSTATE(4); - OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, - R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS | - R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); - OUT_BATCH_REGVAL(R300_ZB_ZCACHE_CTLSTAT, - R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE | - R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); + OUT_BATCH_REGVAL(R600_RB3D_DSTCACHE_CTLSTAT, + R600_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS | + R600_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); + OUT_BATCH_REGVAL(R600_ZB_ZCACHE_CTLSTAT, + R600_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE | + R600_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); END_BATCH(); COMMIT_BATCH(); } diff --git a/src/mesa/drivers/dri/r600/r600_emit.h b/src/mesa/drivers/dri/r600/r600_emit.h index 14c17c0c6d..bf106a8ad2 100644 --- a/src/mesa/drivers/dri/r600/r600_emit.h +++ b/src/mesa/drivers/dri/r600/r600_emit.h @@ -34,7 +34,7 @@ * Jerome Glisse */ -/* This files defines functions for accessing R300 hardware. +/* This files defines functions for accessing R600 hardware. */ #ifndef __R600_EMIT_H__ #define __R600_EMIT_H__ @@ -165,7 +165,7 @@ void static INLINE end_3d(radeonContextPtr radeon) } } -void static INLINE cp_delay(r300ContextPtr rmesa, unsigned short count) +void static INLINE cp_delay(r600ContextPtr rmesa, unsigned short count) { BATCH_LOCALS(&rmesa->radeon); @@ -216,19 +216,19 @@ void static INLINE cp_wait(radeonContextPtr radeon, unsigned char flags) } } -extern int r300EmitArrays(GLcontext * ctx); +extern int r600EmitArrays(GLcontext * ctx); -extern int r300PrimitiveType(r300ContextPtr rmesa, int prim); -extern int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim); +extern int r600PrimitiveType(r600ContextPtr rmesa, int prim); +extern int r600NumVerts(r600ContextPtr rmesa, int num_verts, int prim); -extern void r300EmitCacheFlush(r300ContextPtr rmesa); +extern void r600EmitCacheFlush(r600ContextPtr rmesa); -extern GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr, +extern GLuint r600VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr, int *inputs, GLint * tab, GLuint nr); -extern GLuint r300VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr); -extern GLuint r300VAPInputCntl0(GLcontext * ctx, GLuint InputsRead); -extern GLuint r300VAPInputCntl1(GLcontext * ctx, GLuint InputsRead); -extern GLuint r300VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten); -extern GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten); +extern GLuint r600VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr); +extern GLuint r600VAPInputCntl0(GLcontext * ctx, GLuint InputsRead); +extern GLuint r600VAPInputCntl1(GLcontext * ctx, GLuint InputsRead); +extern GLuint r600VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten); +extern GLuint r600VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten); #endif diff --git a/src/mesa/drivers/dri/r600/r600_fragprog.c b/src/mesa/drivers/dri/r600/r600_fragprog.c index 4d2dddc32a..c836723fb0 100644 --- a/src/mesa/drivers/dri/r600/r600_fragprog.c +++ b/src/mesa/drivers/dri/r600/r600_fragprog.c @@ -85,8 +85,8 @@ static GLboolean transform_TEX( struct radeon_transform_context *t, struct prog_instruction* orig_inst, void* data) { - struct r300_fragment_program_compiler *compiler = - (struct r300_fragment_program_compiler*)data; + struct r600_fragment_program_compiler *compiler = + (struct r600_fragment_program_compiler*)data; struct prog_instruction inst = *orig_inst; struct prog_instruction* tgt; GLboolean destredirect = GL_FALSE; @@ -127,7 +127,7 @@ static GLboolean transform_TEX( */ if (inst.Opcode != OPCODE_KIL && inst.TexSrcTarget == TEXTURE_RECT_INDEX) { gl_state_index tokens[STATE_LENGTH] = { - STATE_INTERNAL, STATE_R300_TEXRECT_FACTOR, 0, 0, + STATE_INTERNAL, STATE_R600_TEXRECT_FACTOR, 0, 0, 0 }; @@ -247,13 +247,13 @@ static GLboolean transform_TEX( } -static void update_params(r300ContextPtr r300, struct r300_fragment_program *fp) +static void update_params(r600ContextPtr r600, struct r600_fragment_program *fp) { struct gl_fragment_program *mp = &fp->mesa_program; /* Ask Mesa nicely to fill in ParameterValues for us */ if (mp->Base.Parameters) - _mesa_load_state_parameters(r300->radeon.glCtx, mp->Base.Parameters); + _mesa_load_state_parameters(r600->radeon.glCtx, mp->Base.Parameters); } @@ -268,7 +268,7 @@ static void update_params(r300ContextPtr r300, struct r300_fragment_program *fp) * \todo if/when r5xx supports the radeon_program architecture, this is a * likely candidate for code sharing. */ -static void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler) +static void insert_WPOS_trailer(struct r600_fragment_program_compiler *compiler) { GLuint InputsRead = compiler->fp->mesa_program.Base.InputsRead; @@ -276,7 +276,7 @@ static void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler) return; static gl_state_index tokens[STATE_LENGTH] = { - STATE_INTERNAL, STATE_R300_WINDOW_DIMENSION, 0, 0, 0 + STATE_INTERNAL, STATE_R600_WINDOW_DIMENSION, 0, 0, 0 }; struct prog_instruction *fpi; GLuint window_index; @@ -382,9 +382,9 @@ static GLuint build_func(GLuint comparefunc) * fragment program. */ static void build_state( - r300ContextPtr r300, - struct r300_fragment_program *fp, - struct r300_fragment_program_external_state *state) + r600ContextPtr r600, + struct r600_fragment_program *fp, + struct r600_fragment_program_external_state *state) { int unit; @@ -392,7 +392,7 @@ static void build_state( for(unit = 0; unit < 16; ++unit) { if (fp->mesa_program.Base.ShadowSamplers & (1 << unit)) { - struct gl_texture_object* tex = r300->radeon.glCtx->Texture.Unit[unit]._Current; + struct gl_texture_object* tex = r600->radeon.glCtx->Texture.Unit[unit]._Current; state->unit[unit].depth_texture_mode = build_dtm(tex->DepthMode); state->unit[unit].texture_compare_func = build_func(tex->CompareFunc); @@ -401,12 +401,12 @@ static void build_state( } -void r300TranslateFragmentShader(r300ContextPtr r300, - struct r300_fragment_program *fp) +void r600TranslateFragmentShader(r600ContextPtr r600, + struct r600_fragment_program *fp) { - struct r300_fragment_program_external_state state; + struct r600_fragment_program_external_state state; - build_state(r300, fp, &state); + build_state(r600, fp, &state); if (_mesa_memcmp(&fp->state, &state, sizeof(state))) { /* TODO: cache compiled programs */ fp->translated = GL_FALSE; @@ -414,12 +414,12 @@ void r300TranslateFragmentShader(r300ContextPtr r300, } if (!fp->translated) { - struct r300_fragment_program_compiler compiler; + struct r600_fragment_program_compiler compiler; - compiler.r300 = r300; + compiler.r600 = r600; compiler.fp = fp; compiler.code = &fp->code; - compiler.program = _mesa_clone_program(r300->radeon.glCtx, &fp->mesa_program.Base); + compiler.program = _mesa_clone_program(r600->radeon.glCtx, &fp->mesa_program.Base); if (RADEON_DEBUG & DEBUG_PIXEL) { _mesa_printf("Fragment Program: Initial program:\n"); @@ -434,7 +434,7 @@ void r300TranslateFragmentShader(r300ContextPtr r300, { &radeonTransformTrigSimple, 0 } }; radeonLocalTransform( - r300->radeon.glCtx, + r600->radeon.glCtx, compiler.program, 3, transformations); @@ -445,18 +445,18 @@ void r300TranslateFragmentShader(r300ContextPtr r300, struct radeon_nqssadce_descr nqssadce = { .Init = &nqssadce_init, - .IsNativeSwizzle = &r300FPIsNativeSwizzle, - .BuildSwizzle = &r300FPBuildSwizzle, + .IsNativeSwizzle = &r600FPIsNativeSwizzle, + .BuildSwizzle = &r600FPBuildSwizzle, .RewriteDepthOut = GL_TRUE }; - radeonNqssaDce(r300->radeon.glCtx, compiler.program, &nqssadce); + radeonNqssaDce(r600->radeon.glCtx, compiler.program, &nqssadce); if (RADEON_DEBUG & DEBUG_PIXEL) { _mesa_printf("Compiler: after NqSSA-DCE:\n"); _mesa_print_program(compiler.program); } - if (!r300FragmentProgramEmit(&compiler)) + if (!r600FragmentProgramEmit(&compiler)) fp->error = GL_TRUE; /* Subtle: Rescue any parameters that have been added during transformations */ @@ -464,22 +464,22 @@ void r300TranslateFragmentShader(r300ContextPtr r300, fp->mesa_program.Base.Parameters = compiler.program->Parameters; compiler.program->Parameters = 0; - _mesa_reference_program(r300->radeon.glCtx, &compiler.program, NULL); + _mesa_reference_program(r600->radeon.glCtx, &compiler.program, NULL); if (!fp->error) fp->translated = GL_TRUE; if (fp->error || (RADEON_DEBUG & DEBUG_PIXEL)) - r300FragmentProgramDump(fp, &fp->code); - r300UpdateStateParameters(r300->radeon.glCtx, _NEW_PROGRAM); + r600FragmentProgramDump(fp, &fp->code); + r600UpdateStateParameters(r600->radeon.glCtx, _NEW_PROGRAM); } - update_params(r300, fp); + update_params(r600, fp); } /* just some random things... */ -void r300FragmentProgramDump( - struct r300_fragment_program *fp, - struct r300_fragment_program_code *code) +void r600FragmentProgramDump( + struct r600_fragment_program *fp, + struct r600_fragment_program_code *code) { int n, i, j; static int pc = 0; @@ -505,18 +505,18 @@ void r300FragmentProgramDump( const char *instr; switch ((code->tex. - inst[i] >> R300_TEX_INST_SHIFT) & + inst[i] >> R600_TEX_INST_SHIFT) & 15) { - case R300_TEX_OP_LD: + case R600_TEX_OP_LD: instr = "TEX"; break; - case R300_TEX_OP_KIL: + case R600_TEX_OP_KIL: instr = "KIL"; break; - case R300_TEX_OP_TXP: + case R600_TEX_OP_TXP: instr = "TXP"; break; - case R300_TEX_OP_TXB: + case R600_TEX_OP_TXB: instr = "TXB"; break; default: @@ -527,13 +527,13 @@ void r300FragmentProgramDump( " %s t%i, %c%i, texture[%i] (%08x)\n", instr, (code->tex. - inst[i] >> R300_DST_ADDR_SHIFT) & 31, + inst[i] >> R600_DST_ADDR_SHIFT) & 31, 't', (code->tex. - inst[i] >> R300_SRC_ADDR_SHIFT) & 31, + inst[i] >> R600_SRC_ADDR_SHIFT) & 31, (code->tex. - inst[i] & R300_TEX_ID_MASK) >> - R300_TEX_ID_SHIFT, + inst[i] & R600_TEX_ID_MASK) >> + R600_TEX_ID_SHIFT, code->tex.inst[i]); } } @@ -559,45 +559,45 @@ void r300FragmentProgramDump( dstc[0] = 0; sprintf(flags, "%s%s%s", (code->alu.inst[i]. - inst1 & R300_ALU_DSTC_REG_X) ? "x" : "", + inst1 & R600_ALU_DSTC_REG_X) ? "x" : "", (code->alu.inst[i]. - inst1 & R300_ALU_DSTC_REG_Y) ? "y" : "", + inst1 & R600_ALU_DSTC_REG_Y) ? "y" : "", (code->alu.inst[i]. - inst1 & R300_ALU_DSTC_REG_Z) ? "z" : ""); + inst1 & R600_ALU_DSTC_REG_Z) ? "z" : ""); if (flags[0] != 0) { sprintf(dstc, "t%i.%s ", (code->alu.inst[i]. - inst1 >> R300_ALU_DSTC_SHIFT) & 31, + inst1 >> R600_ALU_DSTC_SHIFT) & 31, flags); } sprintf(flags, "%s%s%s", (code->alu.inst[i]. - inst1 & R300_ALU_DSTC_OUTPUT_X) ? "x" : "", + inst1 & R600_ALU_DSTC_OUTPUT_X) ? "x" : "", (code->alu.inst[i]. - inst1 & R300_ALU_DSTC_OUTPUT_Y) ? "y" : "", + inst1 & R600_ALU_DSTC_OUTPUT_Y) ? "y" : "", (code->alu.inst[i]. - inst1 & R300_ALU_DSTC_OUTPUT_Z) ? "z" : ""); + inst1 & R600_ALU_DSTC_OUTPUT_Z) ? "z" : ""); if (flags[0] != 0) { sprintf(tmp, "o%i.%s", (code->alu.inst[i]. - inst1 >> R300_ALU_DSTC_SHIFT) & 31, + inst1 >> R600_ALU_DSTC_SHIFT) & 31, flags); strcat(dstc, tmp); } dsta[0] = 0; - if (code->alu.inst[i].inst3 & R300_ALU_DSTA_REG) { + if (code->alu.inst[i].inst3 & R600_ALU_DSTA_REG) { sprintf(dsta, "t%i.w ", (code->alu.inst[i]. - inst3 >> R300_ALU_DSTA_SHIFT) & 31); + inst3 >> R600_ALU_DSTA_SHIFT) & 31); } - if (code->alu.inst[i].inst3 & R300_ALU_DSTA_OUTPUT) { + if (code->alu.inst[i].inst3 & R600_ALU_DSTA_OUTPUT) { sprintf(tmp, "o%i.w ", (code->alu.inst[i]. - inst3 >> R300_ALU_DSTA_SHIFT) & 31); + inst3 >> R600_ALU_DSTA_SHIFT) & 31); strcat(dsta, tmp); } - if (code->alu.inst[i].inst3 & R300_ALU_DSTA_DEPTH) { + if (code->alu.inst[i].inst3 & R600_ALU_DSTA_DEPTH) { strcat(dsta, "Z"); } @@ -617,19 +617,19 @@ void r300FragmentProgramDump( d = regc & 31; if (d < 12) { switch (d % 4) { - case R300_ALU_ARGC_SRC0C_XYZ: + case R600_ALU_ARGC_SRC0C_XYZ: sprintf(buf, "%s.xyz", srcc[d / 4]); break; - case R300_ALU_ARGC_SRC0C_XXX: + case R600_ALU_ARGC_SRC0C_XXX: sprintf(buf, "%s.xxx", srcc[d / 4]); break; - case R300_ALU_ARGC_SRC0C_YYY: + case R600_ALU_ARGC_SRC0C_YYY: sprintf(buf, "%s.yyy", srcc[d / 4]); break; - case R300_ALU_ARGC_SRC0C_ZZZ: + case R600_ALU_ARGC_SRC0C_ZZZ: sprintf(buf, "%s.zzz", srcc[d / 4]); break; diff --git a/src/mesa/drivers/dri/r600/r600_fragprog.h b/src/mesa/drivers/dri/r600/r600_fragprog.h index 38139850a3..f6ca5995a2 100644 --- a/src/mesa/drivers/dri/r600/r600_fragprog.h +++ b/src/mesa/drivers/dri/r600/r600_fragprog.h @@ -66,67 +66,67 @@ #define FP_SELC_MASK_XYZ 7 #define FP_SELC(destidx,regmask,outmask,src0,src1,src2) \ - (((destidx) << R300_ALU_DSTC_SHIFT) | \ + (((destidx) << R600_ALU_DSTC_SHIFT) | \ (FP_SELC_MASK_##regmask << 23) | \ (FP_SELC_MASK_##outmask << 26) | \ - ((src0) << R300_ALU_SRC0C_SHIFT) | \ - ((src1) << R300_ALU_SRC1C_SHIFT) | \ - ((src2) << R300_ALU_SRC2C_SHIFT)) + ((src0) << R600_ALU_SRC0C_SHIFT) | \ + ((src1) << R600_ALU_SRC1C_SHIFT) | \ + ((src2) << R600_ALU_SRC2C_SHIFT)) #define FP_SELA_MASK_NO 0 #define FP_SELA_MASK_W 1 #define FP_SELA(destidx,regmask,outmask,src0,src1,src2) \ - (((destidx) << R300_ALU_DSTA_SHIFT) | \ + (((destidx) << R600_ALU_DSTA_SHIFT) | \ (FP_SELA_MASK_##regmask << 23) | \ (FP_SELA_MASK_##outmask << 24) | \ - ((src0) << R300_ALU_SRC0A_SHIFT) | \ - ((src1) << R300_ALU_SRC1A_SHIFT) | \ - ((src2) << R300_ALU_SRC2A_SHIFT)) + ((src0) << R600_ALU_SRC0A_SHIFT) | \ + ((src1) << R600_ALU_SRC1A_SHIFT) | \ + ((src2) << R600_ALU_SRC2A_SHIFT)) /* Produce unshifted argument selectors */ -#define FP_ARGC(source) R300_ALU_ARGC_##source -#define FP_ARGA(source) R300_ALU_ARGA_##source +#define FP_ARGC(source) R600_ALU_ARGC_##source +#define FP_ARGA(source) R600_ALU_ARGA_##source #define FP_ABS(arg) ((arg) | (1 << 6)) #define FP_NEG(arg) ((arg) ^ (1 << 5)) /* Produce instruction dword */ #define FP_INSTRC(opcode,arg0,arg1,arg2) \ - (R300_ALU_OUTC_##opcode | \ - ((arg0) << R300_ALU_ARG0C_SHIFT) | \ - ((arg1) << R300_ALU_ARG1C_SHIFT) | \ - ((arg2) << R300_ALU_ARG2C_SHIFT)) + (R600_ALU_OUTC_##opcode | \ + ((arg0) << R600_ALU_ARG0C_SHIFT) | \ + ((arg1) << R600_ALU_ARG1C_SHIFT) | \ + ((arg2) << R600_ALU_ARG2C_SHIFT)) #define FP_INSTRA(opcode,arg0,arg1,arg2) \ - (R300_ALU_OUTA_##opcode | \ - ((arg0) << R300_ALU_ARG0A_SHIFT) | \ - ((arg1) << R300_ALU_ARG1A_SHIFT) | \ - ((arg2) << R300_ALU_ARG2A_SHIFT)) + (R600_ALU_OUTA_##opcode | \ + ((arg0) << R600_ALU_ARG0A_SHIFT) | \ + ((arg1) << R600_ALU_ARG1A_SHIFT) | \ + ((arg2) << R600_ALU_ARG2A_SHIFT)) #endif -struct r300_fragment_program; +struct r600_fragment_program; -extern void r300TranslateFragmentShader(r300ContextPtr r300, - struct r300_fragment_program *fp); +extern void r600TranslateFragmentShader(r600ContextPtr r600, + struct r600_fragment_program *fp); /** - * Used internally by the r300 fragment program code to store compile-time + * Used internally by the r600 fragment program code to store compile-time * only data. */ -struct r300_fragment_program_compiler { - r300ContextPtr r300; - struct r300_fragment_program *fp; - struct r300_fragment_program_code *code; +struct r600_fragment_program_compiler { + r600ContextPtr r600; + struct r600_fragment_program *fp; + struct r600_fragment_program_code *code; struct gl_program *program; }; -extern GLboolean r300FragmentProgramEmit(struct r300_fragment_program_compiler *compiler); +extern GLboolean r600FragmentProgramEmit(struct r600_fragment_program_compiler *compiler); -extern void r300FragmentProgramDump( - struct r300_fragment_program *fp, - struct r300_fragment_program_code *code); +extern void r600FragmentProgramDump( + struct r600_fragment_program *fp, + struct r600_fragment_program_code *code); #endif diff --git a/src/mesa/drivers/dri/r600/r600_fragprog_emit.c b/src/mesa/drivers/dri/r600/r600_fragprog_emit.c index f03559b6cb..de1e38b816 100644 --- a/src/mesa/drivers/dri/r600/r600_fragprog_emit.c +++ b/src/mesa/drivers/dri/r600/r600_fragprog_emit.c @@ -28,7 +28,7 @@ /** * \file * - * Emit the r300_fragment_program_code that can be understood by the hardware. + * Emit the r600_fragment_program_code that can be understood by the hardware. * Input is a pre-transformed radeon_program. * * \author Ben Skeggs @@ -46,8 +46,8 @@ #define PROG_CODE \ - struct r300_fragment_program_compiler *c = (struct r300_fragment_program_compiler*)data; \ - struct r300_fragment_program_code *code = c->code + struct r600_fragment_program_compiler *c = (struct r600_fragment_program_compiler*)data; \ + struct r600_fragment_program_code *code = c->code #define error(fmt, args...) do { \ fprintf(stderr, "%s::%s(): " fmt "\n", \ @@ -83,7 +83,7 @@ static GLboolean emit_const(void* data, GLuint file, GLuint index, GLuint *hwind /** * Mark a temporary register as used. */ -static void use_temporary(struct r300_fragment_program_code *code, GLuint index) +static void use_temporary(struct r600_fragment_program_code *code, GLuint index) { if (index > code->max_temp_idx) code->max_temp_idx = index; @@ -93,41 +93,41 @@ static void use_temporary(struct r300_fragment_program_code *code, GLuint index) static GLuint translate_rgb_opcode(GLuint opcode) { switch(opcode) { - case OPCODE_CMP: return R300_ALU_OUTC_CMP; - case OPCODE_DP3: return R300_ALU_OUTC_DP3; - case OPCODE_DP4: return R300_ALU_OUTC_DP4; - case OPCODE_FRC: return R300_ALU_OUTC_FRC; + case OPCODE_CMP: return R600_ALU_OUTC_CMP; + case OPCODE_DP3: return R600_ALU_OUTC_DP3; + case OPCODE_DP4: return R600_ALU_OUTC_DP4; + case OPCODE_FRC: return R600_ALU_OUTC_FRC; default: error("translate_rgb_opcode(%i): Unknown opcode", opcode); /* fall through */ case OPCODE_NOP: /* fall through */ - case OPCODE_MAD: return R300_ALU_OUTC_MAD; - case OPCODE_MAX: return R300_ALU_OUTC_MAX; - case OPCODE_MIN: return R300_ALU_OUTC_MIN; - case OPCODE_REPL_ALPHA: return R300_ALU_OUTC_REPL_ALPHA; + case OPCODE_MAD: return R600_ALU_OUTC_MAD; + case OPCODE_MAX: return R600_ALU_OUTC_MAX; + case OPCODE_MIN: return R600_ALU_OUTC_MIN; + case OPCODE_REPL_ALPHA: return R600_ALU_OUTC_REPL_ALPHA; } } static GLuint translate_alpha_opcode(GLuint opcode) { switch(opcode) { - case OPCODE_CMP: return R300_ALU_OUTA_CMP; - case OPCODE_DP3: return R300_ALU_OUTA_DP4; - case OPCODE_DP4: return R300_ALU_OUTA_DP4; - case OPCODE_EX2: return R300_ALU_OUTA_EX2; - case OPCODE_FRC: return R300_ALU_OUTA_FRC; - case OPCODE_LG2: return R300_ALU_OUTA_LG2; + case OPCODE_CMP: return R600_ALU_OUTA_CMP; + case OPCODE_DP3: return R600_ALU_OUTA_DP4; + case OPCODE_DP4: return R600_ALU_OUTA_DP4; + case OPCODE_EX2: return R600_ALU_OUTA_EX2; + case OPCODE_FRC: return R600_ALU_OUTA_FRC; + case OPCODE_LG2: return R600_ALU_OUTA_LG2; default: error("translate_rgb_opcode(%i): Unknown opcode", opcode); /* fall through */ case OPCODE_NOP: /* fall through */ - case OPCODE_MAD: return R300_ALU_OUTA_MAD; - case OPCODE_MAX: return R300_ALU_OUTA_MAX; - case OPCODE_MIN: return R300_ALU_OUTA_MIN; - case OPCODE_RCP: return R300_ALU_OUTA_RCP; - case OPCODE_RSQ: return R300_ALU_OUTA_RSQ; + case OPCODE_MAD: return R600_ALU_OUTA_MAD; + case OPCODE_MAX: return R600_ALU_OUTA_MAX; + case OPCODE_MIN: return R600_ALU_OUTA_MIN; + case OPCODE_RCP: return R600_ALU_OUTA_RCP; + case OPCODE_RSQ: return R600_ALU_OUTA_RSQ; } } @@ -161,46 +161,46 @@ static GLboolean emit_alu(void* data, struct radeon_pair_instruction* inst) use_temporary(code, inst->Alpha.Src[j].Index); code->alu.inst[ip].inst3 |= src << (6*j); - GLuint arg = r300FPTranslateRGBSwizzle(inst->RGB.Arg[j].Source, inst->RGB.Arg[j].Swizzle); + GLuint arg = r600FPTranslateRGBSwizzle(inst->RGB.Arg[j].Source, inst->RGB.Arg[j].Swizzle); arg |= inst->RGB.Arg[j].Abs << 6; arg |= inst->RGB.Arg[j].Negate << 5; code->alu.inst[ip].inst0 |= arg << (7*j); - arg = r300FPTranslateAlphaSwizzle(inst->Alpha.Arg[j].Source, inst->Alpha.Arg[j].Swizzle); + arg = r600FPTranslateAlphaSwizzle(inst->Alpha.Arg[j].Source, inst->Alpha.Arg[j].Swizzle); arg |= inst->Alpha.Arg[j].Abs << 6; arg |= inst->Alpha.Arg[j].Negate << 5; code->alu.inst[ip].inst2 |= arg << (7*j); } if (inst->RGB.Saturate) - code->alu.inst[ip].inst0 |= R300_ALU_OUTC_CLAMP; + code->alu.inst[ip].inst0 |= R600_ALU_OUTC_CLAMP; if (inst->Alpha.Saturate) - code->alu.inst[ip].inst2 |= R300_ALU_OUTA_CLAMP; + code->alu.inst[ip].inst2 |= R600_ALU_OUTA_CLAMP; if (inst->RGB.WriteMask) { use_temporary(code, inst->RGB.DestIndex); code->alu.inst[ip].inst1 |= - (inst->RGB.DestIndex << R300_ALU_DSTC_SHIFT) | - (inst->RGB.WriteMask << R300_ALU_DSTC_REG_MASK_SHIFT); + (inst->RGB.DestIndex << R600_ALU_DSTC_SHIFT) | + (inst->RGB.WriteMask << R600_ALU_DSTC_REG_MASK_SHIFT); } if (inst->RGB.OutputWriteMask) { - code->alu.inst[ip].inst1 |= (inst->RGB.OutputWriteMask << R300_ALU_DSTC_OUTPUT_MASK_SHIFT); - code->node[code->cur_node].flags |= R300_RGBA_OUT; + code->alu.inst[ip].inst1 |= (inst->RGB.OutputWriteMask << R600_ALU_DSTC_OUTPUT_MASK_SHIFT); + code->node[code->cur_node].flags |= R600_RGBA_OUT; } if (inst->Alpha.WriteMask) { use_temporary(code, inst->Alpha.DestIndex); code->alu.inst[ip].inst3 |= - (inst->Alpha.DestIndex << R300_ALU_DSTA_SHIFT) | - R300_ALU_DSTA_REG; + (inst->Alpha.DestIndex << R600_ALU_DSTA_SHIFT) | + R600_ALU_DSTA_REG; } if (inst->Alpha.OutputWriteMask) { - code->alu.inst[ip].inst3 |= R300_ALU_DSTA_OUTPUT; - code->node[code->cur_node].flags |= R300_RGBA_OUT; + code->alu.inst[ip].inst3 |= R600_ALU_DSTA_OUTPUT; + code->node[code->cur_node].flags |= R600_RGBA_OUT; } if (inst->Alpha.DepthWriteMask) { - code->alu.inst[ip].inst3 |= R300_ALU_DSTA_DEPTH; - code->node[code->cur_node].flags |= R300_W_OUT; + code->alu.inst[ip].inst3 |= R600_ALU_DSTA_DEPTH; + code->node[code->cur_node].flags |= R600_W_OUT; c->fp->WritesDepth = GL_TRUE; } @@ -211,10 +211,10 @@ static GLboolean emit_alu(void* data, struct radeon_pair_instruction* inst) /** * Finish the current node without advancing to the next one. */ -static GLboolean finish_node(struct r300_fragment_program_compiler *c) +static GLboolean finish_node(struct r600_fragment_program_compiler *c) { - struct r300_fragment_program_code *code = c->code; - struct r300_fragment_program_node *node = &code->node[code->cur_node]; + struct r600_fragment_program_code *code = c->code; + struct r600_fragment_program_node *node = &code->node[code->cur_node]; if (node->alu_end < 0) { /* Generate a single NOP for this node */ @@ -262,7 +262,7 @@ static GLboolean begin_tex(void* data) if (!finish_node(c)) return GL_FALSE; - struct r300_fragment_program_node *node = &code->node[++code->cur_node]; + struct r600_fragment_program_node *node = &code->node[++code->cur_node]; node->alu_offset = code->alu.length; node->alu_end = -1; node->tex_offset = code->tex.length; @@ -285,10 +285,10 @@ static GLboolean emit_tex(void* data, struct prog_instruction* inst) GLuint opcode; switch(inst->Opcode) { - case OPCODE_KIL: opcode = R300_TEX_OP_KIL; break; - case OPCODE_TEX: opcode = R300_TEX_OP_LD; break; - case OPCODE_TXB: opcode = R300_TEX_OP_TXB; break; - case OPCODE_TXP: opcode = R300_TEX_OP_TXP; break; + case OPCODE_KIL: opcode = R600_TEX_OP_KIL; break; + case OPCODE_TEX: opcode = R600_TEX_OP_LD; break; + case OPCODE_TXB: opcode = R600_TEX_OP_TXB; break; + case OPCODE_TXP: opcode = R600_TEX_OP_TXP; break; default: error("Unknown texture opcode %i", inst->Opcode); return GL_FALSE; @@ -305,10 +305,10 @@ static GLboolean emit_tex(void* data, struct prog_instruction* inst) code->node[code->cur_node].tex_end++; code->tex.inst[code->tex.length++] = - (inst->SrcReg[0].Index << R300_SRC_ADDR_SHIFT) | - (dest << R300_DST_ADDR_SHIFT) | - (unit << R300_TEX_ID_SHIFT) | - (opcode << R300_TEX_INST_SHIFT); + (inst->SrcReg[0].Index << R600_SRC_ADDR_SHIFT) | + (dest << R600_DST_ADDR_SHIFT) | + (unit << R600_TEX_ID_SHIFT) | + (opcode << R600_TEX_INST_SHIFT); return GL_TRUE; } @@ -325,15 +325,15 @@ static const struct radeon_pair_handler pair_handler = { * Final compilation step: Turn the intermediate radeon_program into * machine-readable instructions. */ -GLboolean r300FragmentProgramEmit(struct r300_fragment_program_compiler *compiler) +GLboolean r600FragmentProgramEmit(struct r600_fragment_program_compiler *compiler) { - struct r300_fragment_program_code *code = compiler->code; + struct r600_fragment_program_code *code = compiler->code; - _mesa_bzero(code, sizeof(struct r300_fragment_program_code)); + _mesa_bzero(code, sizeof(struct r600_fragment_program_code)); code->node[0].alu_end = -1; code->node[0].tex_end = -1; - if (!radeonPairProgram(compiler->r300->radeon.glCtx, compiler->program, &pair_handler, compiler)) + if (!radeonPairProgram(compiler->r600->radeon.glCtx, compiler->program, &pair_handler, compiler)) return GL_FALSE; if (!finish_node(compiler)) diff --git a/src/mesa/drivers/dri/r600/r600_fragprog_swizzle.c b/src/mesa/drivers/dri/r600/r600_fragprog_swizzle.c index 16c5fc8ec7..36136cc849 100644 --- a/src/mesa/drivers/dri/r600/r600_fragprog_swizzle.c +++ b/src/mesa/drivers/dri/r600/r600_fragprog_swizzle.c @@ -27,7 +27,7 @@ /** * @file - * Utilities to deal with the somewhat odd restriction on R300 fragment + * Utilities to deal with the somewhat odd restriction on R600 fragment * program swizzles. */ @@ -45,16 +45,16 @@ struct swizzle_data { }; static const struct swizzle_data native_swizzles[] = { - {MAKE_SWZ3(X, Y, Z), R300_ALU_ARGC_SRC0C_XYZ, 4}, - {MAKE_SWZ3(X, X, X), R300_ALU_ARGC_SRC0C_XXX, 4}, - {MAKE_SWZ3(Y, Y, Y), R300_ALU_ARGC_SRC0C_YYY, 4}, - {MAKE_SWZ3(Z, Z, Z), R300_ALU_ARGC_SRC0C_ZZZ, 4}, - {MAKE_SWZ3(W, W, W), R300_ALU_ARGC_SRC0A, 1}, - {MAKE_SWZ3(Y, Z, X), R300_ALU_ARGC_SRC0C_YZX, 1}, - {MAKE_SWZ3(Z, X, Y), R300_ALU_ARGC_SRC0C_ZXY, 1}, - {MAKE_SWZ3(W, Z, Y), R300_ALU_ARGC_SRC0CA_WZY, 1}, - {MAKE_SWZ3(ONE, ONE, ONE), R300_ALU_ARGC_ONE, 0}, - {MAKE_SWZ3(ZERO, ZERO, ZERO), R300_ALU_ARGC_ZERO, 0} + {MAKE_SWZ3(X, Y, Z), R600_ALU_ARGC_SRC0C_XYZ, 4}, + {MAKE_SWZ3(X, X, X), R600_ALU_ARGC_SRC0C_XXX, 4}, + {MAKE_SWZ3(Y, Y, Y), R600_ALU_ARGC_SRC0C_YYY, 4}, + {MAKE_SWZ3(Z, Z, Z), R600_ALU_ARGC_SRC0C_ZZZ, 4}, + {MAKE_SWZ3(W, W, W), R600_ALU_ARGC_SRC0A, 1}, + {MAKE_SWZ3(Y, Z, X), R600_ALU_ARGC_SRC0C_YZX, 1}, + {MAKE_SWZ3(Z, X, Y), R600_ALU_ARGC_SRC0C_ZXY, 1}, + {MAKE_SWZ3(W, Z, Y), R600_ALU_ARGC_SRC0CA_WZY, 1}, + {MAKE_SWZ3(ONE, ONE, ONE), R600_ALU_ARGC_ONE, 0}, + {MAKE_SWZ3(ZERO, ZERO, ZERO), R600_ALU_ARGC_ZERO, 0} }; static const int num_native_swizzles = sizeof(native_swizzles)/sizeof(native_swizzles[0]); @@ -89,7 +89,7 @@ static const struct swizzle_data* lookup_native_swizzle(GLuint swizzle) * Check whether the given instruction supports the swizzle and negate * combinations in the given source register. */ -GLboolean r300FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg) +GLboolean r600FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg) { if (reg.Abs) reg.NegateBase = 0; @@ -134,7 +134,7 @@ GLboolean r300FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg) /** * Generate MOV dst, src using only native swizzles. */ -void r300FPBuildSwizzle(struct nqssadce_state *s, struct prog_dst_register dst, struct prog_src_register src) +void r600FPBuildSwizzle(struct nqssadce_state *s, struct prog_dst_register dst, struct prog_src_register src) { if (src.Abs) src.NegateBase = 0; @@ -196,7 +196,7 @@ void r300FPBuildSwizzle(struct nqssadce_state *s, struct prog_dst_register dst, * Translate an RGB (XYZ) swizzle into the hardware code for the given * instruction source. */ -GLuint r300FPTranslateRGBSwizzle(GLuint src, GLuint swizzle) +GLuint r600FPTranslateRGBSwizzle(GLuint src, GLuint swizzle) { const struct swizzle_data* sd = lookup_native_swizzle(swizzle); @@ -213,15 +213,15 @@ GLuint r300FPTranslateRGBSwizzle(GLuint src, GLuint swizzle) * Translate an Alpha (W) swizzle into the hardware code for the given * instruction source. */ -GLuint r300FPTranslateAlphaSwizzle(GLuint src, GLuint swizzle) +GLuint r600FPTranslateAlphaSwizzle(GLuint src, GLuint swizzle) { if (swizzle < 3) return swizzle + 3*src; switch(swizzle) { - case SWIZZLE_W: return R300_ALU_ARGA_SRC0A + src; - case SWIZZLE_ONE: return R300_ALU_ARGA_ONE; - case SWIZZLE_ZERO: return R300_ALU_ARGA_ZERO; - default: return R300_ALU_ARGA_ONE; + case SWIZZLE_W: return R600_ALU_ARGA_SRC0A + src; + case SWIZZLE_ONE: return R600_ALU_ARGA_ONE; + case SWIZZLE_ZERO: return R600_ALU_ARGA_ZERO; + default: return R600_ALU_ARGA_ONE; } } diff --git a/src/mesa/drivers/dri/r600/r600_fragprog_swizzle.h b/src/mesa/drivers/dri/r600/r600_fragprog_swizzle.h index 4a0f8cce4f..721155f859 100644 --- a/src/mesa/drivers/dri/r600/r600_fragprog_swizzle.h +++ b/src/mesa/drivers/dri/r600/r600_fragprog_swizzle.h @@ -33,10 +33,10 @@ struct nqssadce_state; -GLboolean r300FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg); -void r300FPBuildSwizzle(struct nqssadce_state*, struct prog_dst_register dst, struct prog_src_register src); +GLboolean r600FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg); +void r600FPBuildSwizzle(struct nqssadce_state*, struct prog_dst_register dst, struct prog_src_register src); -GLuint r300FPTranslateRGBSwizzle(GLuint src, GLuint swizzle); -GLuint r300FPTranslateAlphaSwizzle(GLuint src, GLuint swizzle); +GLuint r600FPTranslateRGBSwizzle(GLuint src, GLuint swizzle); +GLuint r600FPTranslateAlphaSwizzle(GLuint src, GLuint swizzle); -#endif /* __R300_FRAGPROG_SWIZZLE_H_ */ +#endif /* __R600_FRAGPROG_SWIZZLE_H_ */ diff --git a/src/mesa/drivers/dri/r600/r600_ioctl.c b/src/mesa/drivers/dri/r600/r600_ioctl.c index c75354ae45..7e180a1a6e 100644 --- a/src/mesa/drivers/dri/r600/r600_ioctl.c +++ b/src/mesa/drivers/dri/r600/r600_ioctl.c @@ -66,22 +66,22 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define CLEARBUFFER_DEPTH 0x2 #define CLEARBUFFER_STENCIL 0x4 -static void r300EmitClearState(GLcontext * ctx); +static void r600EmitClearState(GLcontext * ctx); -static void r300UserClear(GLcontext *ctx, GLuint mask) +static void r600UserClear(GLcontext *ctx, GLuint mask) { radeon_clear_tris(ctx, mask); } -static void r300ClearBuffer(r300ContextPtr r300, int flags, +static void r600ClearBuffer(r600ContextPtr r600, int flags, struct radeon_renderbuffer *rrb, struct radeon_renderbuffer *rrbd) { - BATCH_LOCALS(&r300->radeon); - GLcontext *ctx = r300->radeon.glCtx; - __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; + BATCH_LOCALS(&r600->radeon); + GLcontext *ctx = r600->radeon.glCtx; + __DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable; GLuint cbpitch = 0; - r300ContextPtr rmesa = r300; + r600ContextPtr rmesa = r600; if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s: buffer %p (%i,%i %ix%i)\n", @@ -91,25 +91,25 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, if (rrb) { cbpitch = (rrb->pitch / rrb->cpp); if (rrb->cpp == 4) - cbpitch |= R300_COLOR_FORMAT_ARGB8888; + cbpitch |= R600_COLOR_FORMAT_ARGB8888; else - cbpitch |= R300_COLOR_FORMAT_RGB565; + cbpitch |= R600_COLOR_FORMAT_RGB565; if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){ - cbpitch |= R300_COLOR_TILE_ENABLE; + cbpitch |= R600_COLOR_TILE_ENABLE; } } /* TODO in bufmgr */ - cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN); + cp_wait(&r600->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN); end_3d(&rmesa->radeon); if (flags & CLEARBUFFER_COLOR) { assert(rrb != 0); BEGIN_BATCH_NO_AUTOSTATE(6); - OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1); + OUT_BATCH_REGSEQ(R600_RB3D_COLOROFFSET0, 1); OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); - OUT_BATCH_REGVAL(R300_RB3D_COLORPITCH0, cbpitch); + OUT_BATCH_REGVAL(R600_RB3D_COLORPITCH0, cbpitch); END_BATCH(); } #if 1 @@ -117,15 +117,15 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, assert(rrbd != 0); cbpitch = (rrbd->pitch / rrbd->cpp); if (rrbd->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){ - cbpitch |= R300_DEPTHMACROTILE_ENABLE; + cbpitch |= R600_DEPTHMACROTILE_ENABLE; } if (rrbd->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){ - cbpitch |= R300_DEPTHMICROTILE_TILED; + cbpitch |= R600_DEPTHMICROTILE_TILED; } BEGIN_BATCH_NO_AUTOSTATE(6); - OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1); + OUT_BATCH_REGSEQ(R600_ZB_DEPTHOFFSET, 1); OUT_BATCH_RELOC(0, rrbd->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); - OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, cbpitch); + OUT_BATCH_REGVAL(R600_ZB_DEPTHPITCH, cbpitch); END_BATCH(); } #endif @@ -148,36 +148,36 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, t2 = 0x0; if (flags & CLEARBUFFER_DEPTH) { - t1 |= R300_Z_ENABLE | R300_Z_WRITE_ENABLE; + t1 |= R600_Z_ENABLE | R600_Z_WRITE_ENABLE; t2 |= - (R300_ZS_ALWAYS << R300_Z_FUNC_SHIFT); + (R600_ZS_ALWAYS << R600_Z_FUNC_SHIFT); } if (flags & CLEARBUFFER_STENCIL) { - t1 |= R300_STENCIL_ENABLE; + t1 |= R600_STENCIL_ENABLE; t2 |= - (R300_ZS_ALWAYS << - R300_S_FRONT_FUNC_SHIFT) | - (R300_ZS_REPLACE << - R300_S_FRONT_SFAIL_OP_SHIFT) | - (R300_ZS_REPLACE << - R300_S_FRONT_ZPASS_OP_SHIFT) | - (R300_ZS_REPLACE << - R300_S_FRONT_ZFAIL_OP_SHIFT); + (R600_ZS_ALWAYS << + R600_S_FRONT_FUNC_SHIFT) | + (R600_ZS_REPLACE << + R600_S_FRONT_SFAIL_OP_SHIFT) | + (R600_ZS_REPLACE << + R600_S_FRONT_ZPASS_OP_SHIFT) | + (R600_ZS_REPLACE << + R600_S_FRONT_ZFAIL_OP_SHIFT); } - OUT_BATCH_REGSEQ(R300_ZB_CNTL, 3); + OUT_BATCH_REGSEQ(R600_ZB_CNTL, 3); OUT_BATCH(t1); OUT_BATCH(t2); - OUT_BATCH(((ctx->Stencil.WriteMask[0] & R300_STENCILREF_MASK) << - R300_STENCILWRITEMASK_SHIFT) | - (ctx->Stencil.Clear & R300_STENCILREF_MASK)); + OUT_BATCH(((ctx->Stencil.WriteMask[0] & R600_STENCILREF_MASK) << + R600_STENCILWRITEMASK_SHIFT) | + (ctx->Stencil.Clear & R600_STENCILREF_MASK)); END_BATCH(); } if (!rmesa->radeon.radeonScreen->kernel_mm) { BEGIN_BATCH_NO_AUTOSTATE(9); - OUT_BATCH(cmdpacket3(r300->radeon.radeonScreen, R300_CMD_PACKET3_CLEAR)); + OUT_BATCH(cmdpacket3(r600->radeon.radeonScreen, R300_CMD_PACKET3_CLEAR)); OUT_BATCH_FLOAT32(dPriv->w / 2.0); OUT_BATCH_FLOAT32(dPriv->h / 2.0); OUT_BATCH_FLOAT32(ctx->Depth.Clear); @@ -189,8 +189,8 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, END_BATCH(); } else { OUT_BATCH(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); - OUT_BATCH(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING | - (1 << R300_PRIM_NUM_VERTICES_SHIFT)); + OUT_BATCH(R600_PRIM_TYPE_POINT | R600_PRIM_WALK_RING | + (1 << R600_PRIM_NUM_VERTICES_SHIFT)); OUT_BATCH_FLOAT32(dPriv->w / 2.0); OUT_BATCH_FLOAT32(dPriv->h / 2.0); OUT_BATCH_FLOAT32(ctx->Depth.Clear); @@ -201,28 +201,28 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]); } - r300EmitCacheFlush(rmesa); - cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN); + r600EmitCacheFlush(rmesa); + cp_wait(&r600->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN); - R300_STATECHANGE(r300, cb); - R300_STATECHANGE(r300, cmk); - R300_STATECHANGE(r300, zs); + R600_STATECHANGE(r600, cb); + R600_STATECHANGE(r600, cmk); + R600_STATECHANGE(r600, zs); } -static void r300EmitClearState(GLcontext * ctx) +static void r600EmitClearState(GLcontext * ctx) { - r300ContextPtr r300 = R300_CONTEXT(ctx); - BATCH_LOCALS(&r300->radeon); - __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; + r600ContextPtr r600 = R600_CONTEXT(ctx); + BATCH_LOCALS(&r600->radeon); + __DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable; int i; int has_tcl = 1; int is_r500 = 0; GLuint vap_cntl; - if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) + if (!(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) has_tcl = 0; - if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) + if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) is_r500 = 1; /* State atom dirty tracking is a little subtle here. @@ -233,61 +233,61 @@ static void r300EmitClearState(GLcontext * ctx) * BEGIN_BATCH cannot be a BEGIN_BATCH_NO_AUTOSTATE. * * On the other hand, implicit state emission clears the state atom - * dirty bits, so we have to call R300_STATECHANGE later than the + * dirty bits, so we have to call R600_STATECHANGE later than the * first BEGIN_BATCH. * * The final trickiness is that, because we change state, we need * to ensure that any stored swtcl primitives are flushed properly - * before we start changing state. See the R300_NEWPRIM in r300Clear + * before we start changing state. See the R600_NEWPRIM in r600Clear * for this. */ BEGIN_BATCH(31); - OUT_BATCH_REGSEQ(R300_VAP_PROG_STREAM_CNTL_0, 1); + OUT_BATCH_REGSEQ(R600_VAP_PROG_STREAM_CNTL_0, 1); if (!has_tcl) - OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) | - ((R300_LAST_VEC | (2 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT))); + OUT_BATCH(((((0 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_0_SHIFT) | + ((R600_LAST_VEC | (2 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_1_SHIFT))); else - OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) | - ((R300_LAST_VEC | (1 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT))); - - OUT_BATCH_REGVAL(R300_FG_FOG_BLEND, 0); - OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_EXT_0, - ((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) | - (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) | - (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) | - (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) | - ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT)) - << R300_SWIZZLE0_SHIFT) | - (((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) | - (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) | - (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) | - (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) | - ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT)) - << R300_SWIZZLE1_SHIFT))); - - /* R300_VAP_INPUT_CNTL_0, R300_VAP_INPUT_CNTL_1 */ - OUT_BATCH_REGSEQ(R300_VAP_VTX_STATE_CNTL, 2); - OUT_BATCH((R300_SEL_USER_COLOR_0 << R300_COLOR_0_ASSEMBLY_SHIFT)); - OUT_BATCH(R300_INPUT_CNTL_POS | R300_INPUT_CNTL_COLOR | R300_INPUT_CNTL_TC0); + OUT_BATCH(((((0 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_0_SHIFT) | + ((R600_LAST_VEC | (1 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_1_SHIFT))); + + OUT_BATCH_REGVAL(R600_FG_FOG_BLEND, 0); + OUT_BATCH_REGVAL(R600_VAP_PROG_STREAM_CNTL_EXT_0, + ((((R600_SWIZZLE_SELECT_X << R600_SWIZZLE_SELECT_X_SHIFT) | + (R600_SWIZZLE_SELECT_Y << R600_SWIZZLE_SELECT_Y_SHIFT) | + (R600_SWIZZLE_SELECT_Z << R600_SWIZZLE_SELECT_Z_SHIFT) | + (R600_SWIZZLE_SELECT_W << R600_SWIZZLE_SELECT_W_SHIFT) | + ((R600_WRITE_ENA_X | R600_WRITE_ENA_Y | R600_WRITE_ENA_Z | R600_WRITE_ENA_W) << R600_WRITE_ENA_SHIFT)) + << R600_SWIZZLE0_SHIFT) | + (((R600_SWIZZLE_SELECT_X << R600_SWIZZLE_SELECT_X_SHIFT) | + (R600_SWIZZLE_SELECT_Y << R600_SWIZZLE_SELECT_Y_SHIFT) | + (R600_SWIZZLE_SELECT_Z << R600_SWIZZLE_SELECT_Z_SHIFT) | + (R600_SWIZZLE_SELECT_W << R600_SWIZZLE_SELECT_W_SHIFT) | + ((R600_WRITE_ENA_X | R600_WRITE_ENA_Y | R600_WRITE_ENA_Z | R600_WRITE_ENA_W) << R600_WRITE_ENA_SHIFT)) + << R600_SWIZZLE1_SHIFT))); + + /* R600_VAP_INPUT_CNTL_0, R600_VAP_INPUT_CNTL_1 */ + OUT_BATCH_REGSEQ(R600_VAP_VTX_STATE_CNTL, 2); + OUT_BATCH((R600_SEL_USER_COLOR_0 << R600_COLOR_0_ASSEMBLY_SHIFT)); + OUT_BATCH(R600_INPUT_CNTL_POS | R600_INPUT_CNTL_COLOR | R600_INPUT_CNTL_TC0); /* comes from fglrx startup of clear */ - OUT_BATCH_REGSEQ(R300_SE_VTE_CNTL, 2); - OUT_BATCH(R300_VTX_W0_FMT | R300_VPORT_X_SCALE_ENA | - R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA | - R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA | - R300_VPORT_Z_OFFSET_ENA); + OUT_BATCH_REGSEQ(R600_SE_VTE_CNTL, 2); + OUT_BATCH(R600_VTX_W0_FMT | R600_VPORT_X_SCALE_ENA | + R600_VPORT_X_OFFSET_ENA | R600_VPORT_Y_SCALE_ENA | + R600_VPORT_Y_OFFSET_ENA | R600_VPORT_Z_SCALE_ENA | + R600_VPORT_Z_OFFSET_ENA); OUT_BATCH(0x8); - OUT_BATCH_REGVAL(R300_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa); + OUT_BATCH_REGVAL(R600_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa); - OUT_BATCH_REGSEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2); - OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT | - R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT); + OUT_BATCH_REGSEQ(R600_VAP_OUTPUT_VTX_FMT_0, 2); + OUT_BATCH(R600_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT | + R600_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT); OUT_BATCH(0); /* no textures */ - OUT_BATCH_REGVAL(R300_TX_ENABLE, 0); + OUT_BATCH_REGVAL(R600_TX_ENABLE, 0); - OUT_BATCH_REGSEQ(R300_SE_VPORT_XSCALE, 6); + OUT_BATCH_REGSEQ(R600_SE_VPORT_XSCALE, 6); OUT_BATCH_FLOAT32(1.0); OUT_BATCH_FLOAT32(dPriv->x); OUT_BATCH_FLOAT32(1.0); @@ -295,59 +295,59 @@ static void r300EmitClearState(GLcontext * ctx) OUT_BATCH_FLOAT32(1.0); OUT_BATCH_FLOAT32(0.0); - OUT_BATCH_REGVAL(R300_FG_ALPHA_FUNC, 0); + OUT_BATCH_REGVAL(R600_FG_ALPHA_FUNC, 0); - OUT_BATCH_REGSEQ(R300_RB3D_CBLEND, 2); + OUT_BATCH_REGSEQ(R600_RB3D_CBLEND, 2); OUT_BATCH(0x0); OUT_BATCH(0x0); END_BATCH(); - R300_STATECHANGE(r300, vir[0]); - R300_STATECHANGE(r300, fogs); - R300_STATECHANGE(r300, vir[1]); - R300_STATECHANGE(r300, vic); - R300_STATECHANGE(r300, vte); - R300_STATECHANGE(r300, vof); - R300_STATECHANGE(r300, txe); - R300_STATECHANGE(r300, vpt); - R300_STATECHANGE(r300, at); - R300_STATECHANGE(r300, bld); - R300_STATECHANGE(r300, ps); + R600_STATECHANGE(r600, vir[0]); + R600_STATECHANGE(r600, fogs); + R600_STATECHANGE(r600, vir[1]); + R600_STATECHANGE(r600, vic); + R600_STATECHANGE(r600, vte); + R600_STATECHANGE(r600, vof); + R600_STATECHANGE(r600, txe); + R600_STATECHANGE(r600, vpt); + R600_STATECHANGE(r600, at); + R600_STATECHANGE(r600, bld); + R600_STATECHANGE(r600, ps); if (has_tcl) { - R300_STATECHANGE(r300, vap_clip_cntl); + R600_STATECHANGE(r600, vap_clip_cntl); BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL, R300_PS_UCP_MODE_CLIP_AS_TRIFAN | R300_CLIP_DISABLE); + OUT_BATCH_REGVAL(R600_VAP_CLIP_CNTL, R600_PS_UCP_MODE_CLIP_AS_TRIFAN | R600_CLIP_DISABLE); END_BATCH(); } BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH_REGVAL(R300_GA_POINT_SIZE, - ((dPriv->w * 6) << R300_POINTSIZE_X_SHIFT) | - ((dPriv->h * 6) << R300_POINTSIZE_Y_SHIFT)); + OUT_BATCH_REGVAL(R600_GA_POINT_SIZE, + ((dPriv->w * 6) << R600_POINTSIZE_X_SHIFT) | + ((dPriv->h * 6) << R600_POINTSIZE_Y_SHIFT)); END_BATCH(); if (!is_r500) { - R300_STATECHANGE(r300, ri); - R300_STATECHANGE(r300, rc); - R300_STATECHANGE(r300, rr); + R600_STATECHANGE(r600, ri); + R600_STATECHANGE(r600, rc); + R600_STATECHANGE(r600, rr); BEGIN_BATCH(14); - OUT_BATCH_REGSEQ(R300_RS_IP_0, 8); + OUT_BATCH_REGSEQ(R600_RS_IP_0, 8); for (i = 0; i < 8; ++i) - OUT_BATCH(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3)); + OUT_BATCH(R600_RS_SEL_T(1) | R600_RS_SEL_R(2) | R600_RS_SEL_Q(3)); - OUT_BATCH_REGSEQ(R300_RS_COUNT, 2); - OUT_BATCH((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN); + OUT_BATCH_REGSEQ(R600_RS_COUNT, 2); + OUT_BATCH((1 << R600_IC_COUNT_SHIFT) | R600_HIRES_EN); OUT_BATCH(0x0); - OUT_BATCH_REGVAL(R300_RS_INST_0, R300_RS_INST_COL_CN_WRITE); + OUT_BATCH_REGVAL(R600_RS_INST_0, R600_RS_INST_COL_CN_WRITE); END_BATCH(); } else { - R300_STATECHANGE(r300, ri); - R300_STATECHANGE(r300, rc); - R300_STATECHANGE(r300, rr); + R600_STATECHANGE(r600, ri); + R600_STATECHANGE(r600, rc); + R600_STATECHANGE(r600, rr); BEGIN_BATCH(14); OUT_BATCH_REGSEQ(R500_RS_IP_0, 8); @@ -358,8 +358,8 @@ static void r300EmitClearState(GLcontext * ctx) (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)); } - OUT_BATCH_REGSEQ(R300_RS_COUNT, 2); - OUT_BATCH((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN); + OUT_BATCH_REGSEQ(R600_RS_COUNT, 2); + OUT_BATCH((1 << R600_IC_COUNT_SHIFT) | R600_HIRES_EN); OUT_BATCH(0x0); OUT_BATCH_REGVAL(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE); @@ -367,38 +367,38 @@ static void r300EmitClearState(GLcontext * ctx) } if (!is_r500) { - R300_STATECHANGE(r300, fp); - R300_STATECHANGE(r300, fpi[0]); - R300_STATECHANGE(r300, fpi[1]); - R300_STATECHANGE(r300, fpi[2]); - R300_STATECHANGE(r300, fpi[3]); + R600_STATECHANGE(r600, fp); + R600_STATECHANGE(r600, fpi[0]); + R600_STATECHANGE(r600, fpi[1]); + R600_STATECHANGE(r600, fpi[2]); + R600_STATECHANGE(r600, fpi[3]); BEGIN_BATCH(17); - OUT_BATCH_REGSEQ(R300_US_CONFIG, 3); + OUT_BATCH_REGSEQ(R600_US_CONFIG, 3); OUT_BATCH(0x0); OUT_BATCH(0x0); OUT_BATCH(0x0); - OUT_BATCH_REGSEQ(R300_US_CODE_ADDR_0, 4); + OUT_BATCH_REGSEQ(R600_US_CODE_ADDR_0, 4); OUT_BATCH(0x0); OUT_BATCH(0x0); OUT_BATCH(0x0); - OUT_BATCH(R300_RGBA_OUT); + OUT_BATCH(R600_RGBA_OUT); - OUT_BATCH_REGVAL(R300_US_ALU_RGB_INST_0, + OUT_BATCH_REGVAL(R600_US_ALU_RGB_INST_0, FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO))); - OUT_BATCH_REGVAL(R300_US_ALU_RGB_ADDR_0, + OUT_BATCH_REGVAL(R600_US_ALU_RGB_ADDR_0, FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0)); - OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_INST_0, + OUT_BATCH_REGVAL(R600_US_ALU_ALPHA_INST_0, FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO))); - OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_ADDR_0, + OUT_BATCH_REGVAL(R600_US_ALU_ALPHA_ADDR_0, FP_SELA(0, NO, W, FP_TMP(0), 0, 0)); END_BATCH(); } else { struct radeon_state_atom r500fp; uint32_t _cmd[10]; - R300_STATECHANGE(r300, fp); - R300_STATECHANGE(r300, r500fp); + R600_STATECHANGE(r600, fp); + R600_STATECHANGE(r600, r500fp); BEGIN_BATCH(7); OUT_BATCH_REGSEQ(R500_US_CONFIG, 2); @@ -412,7 +412,7 @@ static void r300EmitClearState(GLcontext * ctx) r500fp.check = check_r500fp; r500fp.cmd = _cmd; - r500fp.cmd[0] = cmdr500fp(r300->radeon.radeonScreen, 0, 1, 0, 0); + r500fp.cmd[0] = cmdr500fp(r600->radeon.radeonScreen, 0, 1, 0, 0); r500fp.cmd[1] = R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT | R500_INST_LAST | @@ -454,61 +454,61 @@ static void r300EmitClearState(GLcontext * ctx) } BEGIN_BATCH(2); - OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0); + OUT_BATCH_REGVAL(R600_VAP_PVS_STATE_FLUSH_REG, 0); END_BATCH(); if (has_tcl) { - vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | - (5 << R300_PVS_NUM_CNTLRS_SHIFT) | - (12 << R300_VF_MAX_VTX_NUM_SHIFT)); - if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) + vap_cntl = ((10 << R600_PVS_NUM_SLOTS_SHIFT) | + (5 << R600_PVS_NUM_CNTLRS_SHIFT) | + (12 << R600_VF_MAX_VTX_NUM_SHIFT)); + if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) vap_cntl |= R500_TCL_STATE_OPTIMIZATION; } else { - vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | - (5 << R300_PVS_NUM_CNTLRS_SHIFT) | - (5 << R300_VF_MAX_VTX_NUM_SHIFT)); + vap_cntl = ((10 << R600_PVS_NUM_SLOTS_SHIFT) | + (5 << R600_PVS_NUM_CNTLRS_SHIFT) | + (5 << R600_VF_MAX_VTX_NUM_SHIFT)); } - if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515) - vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT); - else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) || - (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560) || - (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570)) - vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); - else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) || - (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420)) - vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); - else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) || - (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580)) - vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); + if (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515) + vap_cntl |= (2 << R600_PVS_NUM_FPUS_SHIFT); + else if ((r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) || + (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560) || + (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570)) + vap_cntl |= (5 << R600_PVS_NUM_FPUS_SHIFT); + else if ((r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) || + (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420)) + vap_cntl |= (6 << R600_PVS_NUM_FPUS_SHIFT); + else if ((r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) || + (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580)) + vap_cntl |= (8 << R600_PVS_NUM_FPUS_SHIFT); else - vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); + vap_cntl |= (4 << R600_PVS_NUM_FPUS_SHIFT); - R300_STATECHANGE(r300, vap_cntl); + R600_STATECHANGE(r600, vap_cntl); BEGIN_BATCH(2); - OUT_BATCH_REGVAL(R300_VAP_CNTL, vap_cntl); + OUT_BATCH_REGVAL(R600_VAP_CNTL, vap_cntl); END_BATCH(); if (has_tcl) { struct radeon_state_atom vpu; uint32_t _cmd[10]; - R300_STATECHANGE(r300, pvs); - R300_STATECHANGE(r300, vpi); + R600_STATECHANGE(r600, pvs); + R600_STATECHANGE(r600, vpi); BEGIN_BATCH(4); - OUT_BATCH_REGSEQ(R300_VAP_PVS_CODE_CNTL_0, 3); - OUT_BATCH((0 << R300_PVS_FIRST_INST_SHIFT) | - (0 << R300_PVS_XYZW_VALID_INST_SHIFT) | - (1 << R300_PVS_LAST_INST_SHIFT)); - OUT_BATCH((0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) | - (0 << R300_PVS_MAX_CONST_ADDR_SHIFT)); - OUT_BATCH(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT); + OUT_BATCH_REGSEQ(R600_VAP_PVS_CODE_CNTL_0, 3); + OUT_BATCH((0 << R600_PVS_FIRST_INST_SHIFT) | + (0 << R600_PVS_XYZW_VALID_INST_SHIFT) | + (1 << R600_PVS_LAST_INST_SHIFT)); + OUT_BATCH((0 << R600_PVS_CONST_BASE_OFFSET_SHIFT) | + (0 << R600_PVS_MAX_CONST_ADDR_SHIFT)); + OUT_BATCH(1 << R600_PVS_LAST_VTX_SRC_INST_SHIFT); END_BATCH(); vpu.check = check_vpu; vpu.cmd = _cmd; - vpu.cmd[0] = cmdvpu(r300->radeon.radeonScreen, 0, 2); + vpu.cmd[0] = cmdvpu(r600->radeon.radeonScreen, 0, 2); vpu.cmd[1] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 0, 0xf, PVS_DST_REG_OUT); @@ -536,24 +536,24 @@ static void r300EmitClearState(GLcontext * ctx) PVS_SRC_REG_INPUT, VSF_FLAG_NONE); vpu.cmd[8] = 0x0; - r300->vap_flush_needed = GL_TRUE; + r600->vap_flush_needed = GL_TRUE; emit_vpu(ctx, &vpu); } } -static void r300KernelClear(GLcontext *ctx, GLuint flags) +static void r600KernelClear(GLcontext *ctx, GLuint flags) { - r300ContextPtr r300 = R300_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; + r600ContextPtr r600 = R600_CONTEXT(ctx); + __DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable; struct radeon_framebuffer *rfb = dPriv->driverPrivate; struct radeon_renderbuffer *rrb; struct radeon_renderbuffer *rrbd; int bits = 0; /* Make sure it fits there. */ - rcommonEnsureCmdBufSpace(&r300->radeon, 421 * 3, __FUNCTION__); + rcommonEnsureCmdBufSpace(&r600->radeon, 421 * 3, __FUNCTION__); if (flags || bits) - r300EmitClearState(ctx); + r600EmitClearState(ctx); rrbd = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH); if (rrbd && (flags & BUFFER_BIT_DEPTH)) bits |= CLEARBUFFER_DEPTH; @@ -563,24 +563,24 @@ static void r300KernelClear(GLcontext *ctx, GLuint flags) if (flags & BUFFER_BIT_COLOR0) { rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_COLOR0); - r300ClearBuffer(r300, CLEARBUFFER_COLOR, rrb, NULL); + r600ClearBuffer(r600, CLEARBUFFER_COLOR, rrb, NULL); bits = 0; } if (flags & BUFFER_BIT_FRONT_LEFT) { rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT); - r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd); + r600ClearBuffer(r600, bits | CLEARBUFFER_COLOR, rrb, rrbd); bits = 0; } if (flags & BUFFER_BIT_BACK_LEFT) { rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT); - r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd); + r600ClearBuffer(r600, bits | CLEARBUFFER_COLOR, rrb, rrbd); bits = 0; } if (bits) - r300ClearBuffer(r300, bits, NULL, rrbd); + r600ClearBuffer(r600, bits, NULL, rrbd); COMMIT_BATCH(); } @@ -588,30 +588,30 @@ static void r300KernelClear(GLcontext *ctx, GLuint flags) /** * Buffer clear */ -static void r300Clear(GLcontext * ctx, GLbitfield mask) +static void r600Clear(GLcontext * ctx, GLbitfield mask) { - r300ContextPtr r300 = R300_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; + r600ContextPtr r600 = R600_CONTEXT(ctx); + __DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable; const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask); GLbitfield swrast_mask = 0, tri_mask = 0; int i; struct gl_framebuffer *fb = ctx->DrawBuffer; if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "r300Clear\n"); + fprintf(stderr, "r600Clear\n"); - if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) { - LOCK_HARDWARE(&r300->radeon); - UNLOCK_HARDWARE(&r300->radeon); + if (!r600->radeon.radeonScreen->driScreen->dri2.enabled) { + LOCK_HARDWARE(&r600->radeon); + UNLOCK_HARDWARE(&r600->radeon); if (dPriv->numClipRects == 0) return; } /* Flush swtcl vertices if necessary, because we will change hardware * state during clear. See also the state-related comment in - * r300EmitClearState. + * r600EmitClearState. */ - R300_NEWPRIM(r300); + R600_NEWPRIM(r600); if (colorMask == ~0) tri_mask |= (mask & BUFFER_BITS_COLOR); @@ -645,10 +645,10 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) swrast_mask = mask & ~tri_mask; if (tri_mask) { - if (r300->radeon.radeonScreen->kernel_mm) - r300UserClear(ctx, tri_mask); + if (r600->radeon.radeonScreen->kernel_mm) + r600UserClear(ctx, tri_mask); else - r300KernelClear(ctx, tri_mask); + r600KernelClear(ctx, tri_mask); } if (swrast_mask) { if (RADEON_DEBUG & DEBUG_FALLBACKS) @@ -659,9 +659,9 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask) } -void r300InitIoctlFuncs(struct dd_function_table *functions) +void r600InitIoctlFuncs(struct dd_function_table *functions) { - functions->Clear = r300Clear; + functions->Clear = r600Clear; functions->Finish = radeonFinish; functions->Flush = radeonFlush; } diff --git a/src/mesa/drivers/dri/r600/r600_ioctl.h b/src/mesa/drivers/dri/r600/r600_ioctl.h index 63beab92a4..bef8acf23c 100644 --- a/src/mesa/drivers/dri/r600/r600_ioctl.h +++ b/src/mesa/drivers/dri/r600/r600_ioctl.h @@ -39,6 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r600_context.h" #include "radeon_drm.h" -extern void r300InitIoctlFuncs(struct dd_function_table *functions); +extern void r600InitIoctlFuncs(struct dd_function_table *functions); #endif /* __R600_IOCTL_H__ */ diff --git a/src/mesa/drivers/dri/r600/r600_reg.h b/src/mesa/drivers/dri/r600/r600_reg.h index ed552d09bb..bb5416e458 100644 --- a/src/mesa/drivers/dri/r600/r600_reg.h +++ b/src/mesa/drivers/dri/r600/r600_reg.h @@ -25,172 +25,172 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* *INDENT-OFF* */ -#ifndef _R300_REG_H -#define _R300_REG_H - -#define R300_MC_INIT_MISC_LAT_TIMER 0x180 -# define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0 -# define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT 4 -# define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT 8 -# define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT 12 -# define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT 16 -# define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT 20 -# define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 24 -# define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 28 - - -#define R300_MC_INIT_GFX_LAT_TIMER 0x154 -# define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0 -# define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 4 -# define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT 8 -# define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT 12 -# define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT 16 -# define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT 20 -# define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT 24 -# define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 28 +#ifndef _R600_REG_H +#define _R600_REG_H + +#define R600_MC_INIT_MISC_LAT_TIMER 0x180 +# define R600_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0 +# define R600_MC_MISC__MC_VF_INIT_LAT_SHIFT 4 +# define R600_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT 8 +# define R600_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT 12 +# define R600_MC_MISC__MC_FIXED_INIT_LAT_SHIFT 16 +# define R600_MC_MISC__MC_E2R_INIT_LAT_SHIFT 20 +# define R600_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 24 +# define R600_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 28 + + +#define R600_MC_INIT_GFX_LAT_TIMER 0x154 +# define R600_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0 +# define R600_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 4 +# define R600_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT 8 +# define R600_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT 12 +# define R600_MC_MISC__MC_TX0R_INIT_LAT_SHIFT 16 +# define R600_MC_MISC__MC_TX1R_INIT_LAT_SHIFT 20 +# define R600_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT 24 +# define R600_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 28 /* - * This file contains registers and constants for the R300. They have been + * This file contains registers and constants for the R600. They have been * found mostly by examining command buffers captured using glxtest, as well * as by extrapolating some known registers and constants from the R200. * I am fairly certain that they are correct unless stated otherwise * in comments. */ -#define R300_SE_VPORT_XSCALE 0x1D98 -#define R300_SE_VPORT_XOFFSET 0x1D9C -#define R300_SE_VPORT_YSCALE 0x1DA0 -#define R300_SE_VPORT_YOFFSET 0x1DA4 -#define R300_SE_VPORT_ZSCALE 0x1DA8 -#define R300_SE_VPORT_ZOFFSET 0x1DAC +#define R600_SE_VPORT_XSCALE 0x1D98 +#define R600_SE_VPORT_XOFFSET 0x1D9C +#define R600_SE_VPORT_YSCALE 0x1DA0 +#define R600_SE_VPORT_YOFFSET 0x1DA4 +#define R600_SE_VPORT_ZSCALE 0x1DA8 +#define R600_SE_VPORT_ZOFFSET 0x1DAC -#define R300_VAP_PORT_IDX0 0x2040 +#define R600_VAP_PORT_IDX0 0x2040 /* * Vertex Array Processing (VAP) Control */ -#define R300_VAP_CNTL 0x2080 -# define R300_PVS_NUM_SLOTS_SHIFT 0 -# define R300_PVS_NUM_CNTLRS_SHIFT 4 -# define R300_PVS_NUM_FPUS_SHIFT 8 -# define R300_VF_MAX_VTX_NUM_SHIFT 18 -# define R300_GL_CLIP_SPACE_DEF (0 << 22) -# define R300_DX_CLIP_SPACE_DEF (1 << 22) +#define R600_VAP_CNTL 0x2080 +# define R600_PVS_NUM_SLOTS_SHIFT 0 +# define R600_PVS_NUM_CNTLRS_SHIFT 4 +# define R600_PVS_NUM_FPUS_SHIFT 8 +# define R600_VF_MAX_VTX_NUM_SHIFT 18 +# define R600_GL_CLIP_SPACE_DEF (0 << 22) +# define R600_DX_CLIP_SPACE_DEF (1 << 22) # define R500_TCL_STATE_OPTIMIZATION (1 << 23) /* This register is written directly and also starts data section * in many 3d CP_PACKET3's */ -#define R300_VAP_VF_CNTL 0x2084 -# define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0 -# define R300_VAP_VF_CNTL__PRIM_NONE (0<<0) -# define R300_VAP_VF_CNTL__PRIM_POINTS (1<<0) -# define R300_VAP_VF_CNTL__PRIM_LINES (2<<0) -# define R300_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0) -# define R300_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0) -# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0) -# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0) -# define R300_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0) -# define R300_VAP_VF_CNTL__PRIM_QUADS (13<<0) -# define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0) -# define R300_VAP_VF_CNTL__PRIM_POLYGON (15<<0) - -# define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT 4 +#define R600_VAP_VF_CNTL 0x2084 +# define R600_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0 +# define R600_VAP_VF_CNTL__PRIM_NONE (0<<0) +# define R600_VAP_VF_CNTL__PRIM_POINTS (1<<0) +# define R600_VAP_VF_CNTL__PRIM_LINES (2<<0) +# define R600_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0) +# define R600_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0) +# define R600_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0) +# define R600_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0) +# define R600_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0) +# define R600_VAP_VF_CNTL__PRIM_QUADS (13<<0) +# define R600_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0) +# define R600_VAP_VF_CNTL__PRIM_POLYGON (15<<0) + +# define R600_VAP_VF_CNTL__PRIM_WALK__SHIFT 4 /* State based - direct writes to registers trigger vertex generation */ -# define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4) -# define R300_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4) -# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4) -# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4) +# define R600_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4) +# define R600_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4) +# define R600_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4) +# define R600_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4) /* I don't think I saw these three used.. */ -# define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6 -# define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9 -# define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10 +# define R600_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6 +# define R600_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9 +# define R600_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10 /* index size - when not set the indices are assumed to be 16 bit */ -# define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11) +# define R600_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11) /* number of vertices */ -# define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16 +# define R600_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16 #define R500_VAP_INDEX_OFFSET 0x208c -#define R300_VAP_OUTPUT_VTX_FMT_0 0x2090 -# define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0) -# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT (1<<1) -# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) -# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) -# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) -# define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) +#define R600_VAP_OUTPUT_VTX_FMT_0 0x2090 +# define R600_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0) +# define R600_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT (1<<1) +# define R600_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) +# define R600_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) +# define R600_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) +# define R600_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) -#define R300_VAP_OUTPUT_VTX_FMT_1 0x2094 +#define R600_VAP_OUTPUT_VTX_FMT_1 0x2094 /* each of the following is 3 bits wide, specifies number of components */ -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 -# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 -# define R300_VAP_OUTPUT_VTX_FMT_1__NOT_PRESENT 0 -# define R300_VAP_OUTPUT_VTX_FMT_1__1_COMPONENT 1 -# define R300_VAP_OUTPUT_VTX_FMT_1__2_COMPONENTS 2 -# define R300_VAP_OUTPUT_VTX_FMT_1__3_COMPONENTS 3 -# define R300_VAP_OUTPUT_VTX_FMT_1__4_COMPONENTS 4 - -#define R300_SE_VTE_CNTL 0x20b0 -# define R300_VPORT_X_SCALE_ENA (1 << 0) -# define R300_VPORT_X_OFFSET_ENA (1 << 1) -# define R300_VPORT_Y_SCALE_ENA (1 << 2) -# define R300_VPORT_Y_OFFSET_ENA (1 << 3) -# define R300_VPORT_Z_SCALE_ENA (1 << 4) -# define R300_VPORT_Z_OFFSET_ENA (1 << 5) -# define R300_VTX_XY_FMT (1 << 8) -# define R300_VTX_Z_FMT (1 << 9) -# define R300_VTX_W0_FMT (1 << 10) -# define R300_SERIAL_PROC_ENA (1 << 11) +# define R600_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 +# define R600_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 +# define R600_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 +# define R600_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 +# define R600_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 +# define R600_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 +# define R600_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 +# define R600_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 +# define R600_VAP_OUTPUT_VTX_FMT_1__NOT_PRESENT 0 +# define R600_VAP_OUTPUT_VTX_FMT_1__1_COMPONENT 1 +# define R600_VAP_OUTPUT_VTX_FMT_1__2_COMPONENTS 2 +# define R600_VAP_OUTPUT_VTX_FMT_1__3_COMPONENTS 3 +# define R600_VAP_OUTPUT_VTX_FMT_1__4_COMPONENTS 4 + +#define R600_SE_VTE_CNTL 0x20b0 +# define R600_VPORT_X_SCALE_ENA (1 << 0) +# define R600_VPORT_X_OFFSET_ENA (1 << 1) +# define R600_VPORT_Y_SCALE_ENA (1 << 2) +# define R600_VPORT_Y_OFFSET_ENA (1 << 3) +# define R600_VPORT_Z_SCALE_ENA (1 << 4) +# define R600_VPORT_Z_OFFSET_ENA (1 << 5) +# define R600_VTX_XY_FMT (1 << 8) +# define R600_VTX_Z_FMT (1 << 9) +# define R600_VTX_W0_FMT (1 << 10) +# define R600_SERIAL_PROC_ENA (1 << 11) /* BEGIN: Vertex data assembly - lots of uncertainties */ /* gap */ /* Maximum Vertex Indx Clamp */ -#define R300_VAP_VF_MAX_VTX_INDX 0x2134 +#define R600_VAP_VF_MAX_VTX_INDX 0x2134 /* Minimum Vertex Indx Clamp */ -#define R300_VAP_VF_MIN_VTX_INDX 0x2138 +#define R600_VAP_VF_MIN_VTX_INDX 0x2138 /** Vertex assembler/processor control status */ -#define R300_VAP_CNTL_STATUS 0x2140 +#define R600_VAP_CNTL_STATUS 0x2140 /* No swap at all (default) */ -# define R300_VC_NO_SWAP (0 << 0) +# define R600_VC_NO_SWAP (0 << 0) /* 16-bit swap: 0xAABBCCDD becomes 0xBBAADDCC */ -# define R300_VC_16BIT_SWAP (1 << 0) +# define R600_VC_16BIT_SWAP (1 << 0) /* 32-bit swap: 0xAABBCCDD becomes 0xDDCCBBAA */ -# define R300_VC_32BIT_SWAP (2 << 0) +# define R600_VC_32BIT_SWAP (2 << 0) /* Half-dword swap: 0xAABBCCDD becomes 0xCCDDAABB */ -# define R300_VC_HALF_DWORD_SWAP (3 << 0) +# define R600_VC_HALF_DWORD_SWAP (3 << 0) /* The TCL engine will not be used (as it is logically or even physically removed) */ -# define R300_VAP_TCL_BYPASS (1 << 8) +# define R600_VAP_TCL_BYPASS (1 << 8) /* Read only flag if TCL engine is busy. */ -# define R300_VAP_PVS_BUSY (1 << 11) +# define R600_VAP_PVS_BUSY (1 << 11) /* TODO: gap for MAX_MPS */ /* Read only flag if the vertex store is busy. */ -# define R300_VAP_VS_BUSY (1 << 24) +# define R600_VAP_VS_BUSY (1 << 24) /* Read only flag if the reciprocal engine is busy. */ -# define R300_VAP_RCP_BUSY (1 << 25) +# define R600_VAP_RCP_BUSY (1 << 25) /* Read only flag if the viewport transform engine is busy. */ -# define R300_VAP_VTE_BUSY (1 << 26) +# define R600_VAP_VTE_BUSY (1 << 26) /* Read only flag if the memory interface unit is busy. */ -# define R300_VAP_MUI_BUSY (1 << 27) +# define R600_VAP_MUI_BUSY (1 << 27) /* Read only flag if the vertex cache is busy. */ -# define R300_VAP_VC_BUSY (1 << 28) +# define R600_VAP_VC_BUSY (1 << 28) /* Read only flag if the vertex fetcher is busy. */ -# define R300_VAP_VF_BUSY (1 << 29) +# define R600_VAP_VF_BUSY (1 << 29) /* Read only flag if the register pipeline is busy. */ -# define R300_VAP_REGPIPE_BUSY (1 << 30) +# define R600_VAP_REGPIPE_BUSY (1 << 30) /* Read only flag if the VAP engine is busy. */ -# define R300_VAP_VAP_BUSY (1 << 31) +# define R600_VAP_VAP_BUSY (1 << 31) /* gap */ @@ -218,31 +218,31 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * Always set COMPONENTS_4 in immediate mode. */ -#define R300_VAP_PROG_STREAM_CNTL_0 0x2150 -# define R300_DATA_TYPE_0_SHIFT 0 -# define R300_DATA_TYPE_FLOAT_1 0 -# define R300_DATA_TYPE_FLOAT_2 1 -# define R300_DATA_TYPE_FLOAT_3 2 -# define R300_DATA_TYPE_FLOAT_4 3 -# define R300_DATA_TYPE_BYTE 4 -# define R300_DATA_TYPE_D3DCOLOR 5 -# define R300_DATA_TYPE_SHORT_2 6 -# define R300_DATA_TYPE_SHORT_4 7 -# define R300_DATA_TYPE_VECTOR_3_TTT 8 -# define R300_DATA_TYPE_VECTOR_3_EET 9 -# define R300_SKIP_DWORDS_SHIFT 4 -# define R300_DST_VEC_LOC_SHIFT 8 -# define R300_LAST_VEC (1 << 13) -# define R300_SIGNED (1 << 14) -# define R300_NORMALIZE (1 << 15) -# define R300_DATA_TYPE_1_SHIFT 16 -#define R300_VAP_PROG_STREAM_CNTL_1 0x2154 -#define R300_VAP_PROG_STREAM_CNTL_2 0x2158 -#define R300_VAP_PROG_STREAM_CNTL_3 0x215C -#define R300_VAP_PROG_STREAM_CNTL_4 0x2160 -#define R300_VAP_PROG_STREAM_CNTL_5 0x2164 -#define R300_VAP_PROG_STREAM_CNTL_6 0x2168 -#define R300_VAP_PROG_STREAM_CNTL_7 0x216C +#define R600_VAP_PROG_STREAM_CNTL_0 0x2150 +# define R600_DATA_TYPE_0_SHIFT 0 +# define R600_DATA_TYPE_FLOAT_1 0 +# define R600_DATA_TYPE_FLOAT_2 1 +# define R600_DATA_TYPE_FLOAT_3 2 +# define R600_DATA_TYPE_FLOAT_4 3 +# define R600_DATA_TYPE_BYTE 4 +# define R600_DATA_TYPE_D3DCOLOR 5 +# define R600_DATA_TYPE_SHORT_2 6 +# define R600_DATA_TYPE_SHORT_4 7 +# define R600_DATA_TYPE_VECTOR_3_TTT 8 +# define R600_DATA_TYPE_VECTOR_3_EET 9 +# define R600_SKIP_DWORDS_SHIFT 4 +# define R600_DST_VEC_LOC_SHIFT 8 +# define R600_LAST_VEC (1 << 13) +# define R600_SIGNED (1 << 14) +# define R600_NORMALIZE (1 << 15) +# define R600_DATA_TYPE_1_SHIFT 16 +#define R600_VAP_PROG_STREAM_CNTL_1 0x2154 +#define R600_VAP_PROG_STREAM_CNTL_2 0x2158 +#define R600_VAP_PROG_STREAM_CNTL_3 0x215C +#define R600_VAP_PROG_STREAM_CNTL_4 0x2160 +#define R600_VAP_PROG_STREAM_CNTL_5 0x2164 +#define R600_VAP_PROG_STREAM_CNTL_6 0x2168 +#define R600_VAP_PROG_STREAM_CNTL_7 0x216C /* gap */ /* Notes: @@ -250,40 +250,40 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * if vertex program uses only position, fglrx will set normal, too * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal. */ -#define R300_VAP_VTX_STATE_CNTL 0x2180 -# define R300_COLOR_0_ASSEMBLY_SHIFT 0 -# define R300_SEL_COLOR 0 -# define R300_SEL_USER_COLOR_0 1 -# define R300_SEL_USER_COLOR_1 2 -# define R300_COLOR_1_ASSEMBLY_SHIFT 2 -# define R300_COLOR_2_ASSEMBLY_SHIFT 4 -# define R300_COLOR_3_ASSEMBLY_SHIFT 6 -# define R300_COLOR_4_ASSEMBLY_SHIFT 8 -# define R300_COLOR_5_ASSEMBLY_SHIFT 10 -# define R300_COLOR_6_ASSEMBLY_SHIFT 12 -# define R300_COLOR_7_ASSEMBLY_SHIFT 14 -# define R300_UPDATE_USER_COLOR_0_ENA (1 << 16) +#define R600_VAP_VTX_STATE_CNTL 0x2180 +# define R600_COLOR_0_ASSEMBLY_SHIFT 0 +# define R600_SEL_COLOR 0 +# define R600_SEL_USER_COLOR_0 1 +# define R600_SEL_USER_COLOR_1 2 +# define R600_COLOR_1_ASSEMBLY_SHIFT 2 +# define R600_COLOR_2_ASSEMBLY_SHIFT 4 +# define R600_COLOR_3_ASSEMBLY_SHIFT 6 +# define R600_COLOR_4_ASSEMBLY_SHIFT 8 +# define R600_COLOR_5_ASSEMBLY_SHIFT 10 +# define R600_COLOR_6_ASSEMBLY_SHIFT 12 +# define R600_COLOR_7_ASSEMBLY_SHIFT 14 +# define R600_UPDATE_USER_COLOR_0_ENA (1 << 16) /* * Each bit in this field applies to the corresponding vector in the VSM * memory (i.e. Bit 0 applies to VECTOR_0 (POSITION), etc.). If the bit * is set, then the corresponding 4-Dword Vector is output into the Vertex Stream. */ -#define R300_VAP_VSM_VTX_ASSM 0x2184 -# define R300_INPUT_CNTL_POS 0x00000001 -# define R300_INPUT_CNTL_NORMAL 0x00000002 -# define R300_INPUT_CNTL_COLOR 0x00000004 -# define R300_INPUT_CNTL_TC0 0x00000400 -# define R300_INPUT_CNTL_TC1 0x00000800 -# define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */ -# define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */ -# define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */ -# define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */ -# define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */ -# define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */ +#define R600_VAP_VSM_VTX_ASSM 0x2184 +# define R600_INPUT_CNTL_POS 0x00000001 +# define R600_INPUT_CNTL_NORMAL 0x00000002 +# define R600_INPUT_CNTL_COLOR 0x00000004 +# define R600_INPUT_CNTL_TC0 0x00000400 +# define R600_INPUT_CNTL_TC1 0x00000800 +# define R600_INPUT_CNTL_TC2 0x00001000 /* GUESS */ +# define R600_INPUT_CNTL_TC3 0x00002000 /* GUESS */ +# define R600_INPUT_CNTL_TC4 0x00004000 /* GUESS */ +# define R600_INPUT_CNTL_TC5 0x00008000 /* GUESS */ +# define R600_INPUT_CNTL_TC6 0x00010000 /* GUESS */ +# define R600_INPUT_CNTL_TC7 0x00020000 /* GUESS */ /* Programmable Stream Control Signed Normalize Control */ -#define R300_VAP_PSC_SGN_NORM_CNTL 0x21dc +#define R600_VAP_PSC_SGN_NORM_CNTL 0x21dc # define SGN_NORM_ZERO 0 # define SGN_NORM_ZERO_CLAMP_MINUS_ONE 1 # define SGN_NORM_NO_ZERO 2 @@ -297,40 +297,40 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * mode, the swizzling pattern is e.g. used to set zw components in texture * coordinates with only tweo components. */ -#define R300_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0 -# define R300_SWIZZLE0_SHIFT 0 -# define R300_SWIZZLE_SELECT_X_SHIFT 0 -# define R300_SWIZZLE_SELECT_Y_SHIFT 3 -# define R300_SWIZZLE_SELECT_Z_SHIFT 6 -# define R300_SWIZZLE_SELECT_W_SHIFT 9 - -# define R300_SWIZZLE_SELECT_X 0 -# define R300_SWIZZLE_SELECT_Y 1 -# define R300_SWIZZLE_SELECT_Z 2 -# define R300_SWIZZLE_SELECT_W 3 -# define R300_SWIZZLE_SELECT_FP_ZERO 4 -# define R300_SWIZZLE_SELECT_FP_ONE 5 -/* alternate forms for r300_emit.c */ -# define R300_INPUT_ROUTE_SELECT_X 0 -# define R300_INPUT_ROUTE_SELECT_Y 1 -# define R300_INPUT_ROUTE_SELECT_Z 2 -# define R300_INPUT_ROUTE_SELECT_W 3 -# define R300_INPUT_ROUTE_SELECT_ZERO 4 -# define R300_INPUT_ROUTE_SELECT_ONE 5 - -# define R300_WRITE_ENA_SHIFT 12 -# define R300_WRITE_ENA_X 1 -# define R300_WRITE_ENA_Y 2 -# define R300_WRITE_ENA_Z 4 -# define R300_WRITE_ENA_W 8 -# define R300_SWIZZLE1_SHIFT 16 -#define R300_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4 -#define R300_VAP_PROG_STREAM_CNTL_EXT_2 0x21e8 -#define R300_VAP_PROG_STREAM_CNTL_EXT_3 0x21ec -#define R300_VAP_PROG_STREAM_CNTL_EXT_4 0x21f0 -#define R300_VAP_PROG_STREAM_CNTL_EXT_5 0x21f4 -#define R300_VAP_PROG_STREAM_CNTL_EXT_6 0x21f8 -#define R300_VAP_PROG_STREAM_CNTL_EXT_7 0x21fc +#define R600_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0 +# define R600_SWIZZLE0_SHIFT 0 +# define R600_SWIZZLE_SELECT_X_SHIFT 0 +# define R600_SWIZZLE_SELECT_Y_SHIFT 3 +# define R600_SWIZZLE_SELECT_Z_SHIFT 6 +# define R600_SWIZZLE_SELECT_W_SHIFT 9 + +# define R600_SWIZZLE_SELECT_X 0 +# define R600_SWIZZLE_SELECT_Y 1 +# define R600_SWIZZLE_SELECT_Z 2 +# define R600_SWIZZLE_SELECT_W 3 +# define R600_SWIZZLE_SELECT_FP_ZERO 4 +# define R600_SWIZZLE_SELECT_FP_ONE 5 +/* alternate forms for r600_emit.c */ +# define R600_INPUT_ROUTE_SELECT_X 0 +# define R600_INPUT_ROUTE_SELECT_Y 1 +# define R600_INPUT_ROUTE_SELECT_Z 2 +# define R600_INPUT_ROUTE_SELECT_W 3 +# define R600_INPUT_ROUTE_SELECT_ZERO 4 +# define R600_INPUT_ROUTE_SELECT_ONE 5 + +# define R600_WRITE_ENA_SHIFT 12 +# define R600_WRITE_ENA_X 1 +# define R600_WRITE_ENA_Y 2 +# define R600_WRITE_ENA_Z 4 +# define R600_WRITE_ENA_W 8 +# define R600_SWIZZLE1_SHIFT 16 +#define R600_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4 +#define R600_VAP_PROG_STREAM_CNTL_EXT_2 0x21e8 +#define R600_VAP_PROG_STREAM_CNTL_EXT_3 0x21ec +#define R600_VAP_PROG_STREAM_CNTL_EXT_4 0x21f0 +#define R600_VAP_PROG_STREAM_CNTL_EXT_5 0x21f4 +#define R600_VAP_PROG_STREAM_CNTL_EXT_6 0x21f8 +#define R600_VAP_PROG_STREAM_CNTL_EXT_7 0x21fc /* END: Vertex data assembly */ @@ -357,28 +357,28 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * * At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the * floating point pointsize. The exact purpose of this state is uncertain, - * as there is also the R300_RE_POINTSIZE register. + * as there is also the R600_RE_POINTSIZE register. * * Multiple vertex programs and parameter sets can be loaded at once, * which could explain the size discrepancy. */ -#define R300_VAP_PVS_VECTOR_INDX_REG 0x2200 -# define R300_PVS_CODE_START 0 -# define R300_MAX_PVS_CODE_LINES 256 +#define R600_VAP_PVS_VECTOR_INDX_REG 0x2200 +# define R600_PVS_CODE_START 0 +# define R600_MAX_PVS_CODE_LINES 256 # define R500_MAX_PVS_CODE_LINES 1024 -# define R300_PVS_CONST_START 512 +# define R600_PVS_CONST_START 512 # define R500_PVS_CONST_START 1024 -# define R300_MAX_PVS_CONST_VECS 256 +# define R600_MAX_PVS_CONST_VECS 256 # define R500_MAX_PVS_CONST_VECS 1024 -# define R300_PVS_UCP_START 1024 +# define R600_PVS_UCP_START 1024 # define R500_PVS_UCP_START 1536 -# define R300_POINT_VPORT_SCALE_OFFSET 1030 +# define R600_POINT_VPORT_SCALE_OFFSET 1030 # define R500_POINT_VPORT_SCALE_OFFSET 1542 -# define R300_POINT_GEN_TEX_OFFSET 1031 +# define R600_POINT_GEN_TEX_OFFSET 1031 # define R500_POINT_GEN_TEX_OFFSET 1543 /* - * These are obsolete defines form r300_context.h, but they might give some + * These are obsolete defines form r600_context.h, but they might give some * clues when investigating the addresses further... */ #if 0 @@ -394,7 +394,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* gap */ -#define R300_VAP_PVS_UPLOAD_DATA 0x2208 +#define R600_VAP_PVS_UPLOAD_DATA 0x2208 /* END: Upload vertex program and data */ @@ -409,20 +409,20 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * * See bug #9871. http://bugs.freedesktop.org/attachment.cgi?id=10672&action=view */ -#define R300_VAP_CLIP_CNTL 0x221C -# define R300_VAP_UCP_ENABLE_0 (1 << 0) -# define R300_VAP_UCP_ENABLE_1 (1 << 1) -# define R300_VAP_UCP_ENABLE_2 (1 << 2) -# define R300_VAP_UCP_ENABLE_3 (1 << 3) -# define R300_VAP_UCP_ENABLE_4 (1 << 4) -# define R300_VAP_UCP_ENABLE_5 (1 << 5) -# define R300_PS_UCP_MODE_DIST_COP (0 << 14) -# define R300_PS_UCP_MODE_RADIUS_COP (1 << 14) -# define R300_PS_UCP_MODE_RADIUS_COP_CLIP (2 << 14) -# define R300_PS_UCP_MODE_CLIP_AS_TRIFAN (3 << 14) -# define R300_CLIP_DISABLE (1 << 16) -# define R300_UCP_CULL_ONLY_ENABLE (1 << 17) -# define R300_BOUNDARY_EDGE_FLAG_ENABLE (1 << 18) +#define R600_VAP_CLIP_CNTL 0x221C +# define R600_VAP_UCP_ENABLE_0 (1 << 0) +# define R600_VAP_UCP_ENABLE_1 (1 << 1) +# define R600_VAP_UCP_ENABLE_2 (1 << 2) +# define R600_VAP_UCP_ENABLE_3 (1 << 3) +# define R600_VAP_UCP_ENABLE_4 (1 << 4) +# define R600_VAP_UCP_ENABLE_5 (1 << 5) +# define R600_PS_UCP_MODE_DIST_COP (0 << 14) +# define R600_PS_UCP_MODE_RADIUS_COP (1 << 14) +# define R600_PS_UCP_MODE_RADIUS_COP_CLIP (2 << 14) +# define R600_PS_UCP_MODE_CLIP_AS_TRIFAN (3 << 14) +# define R600_CLIP_DISABLE (1 << 16) +# define R600_UCP_CULL_ONLY_ENABLE (1 << 17) +# define R600_BOUNDARY_EDGE_FLAG_ENABLE (1 << 18) # define R500_COLOR2_IS_TEXTURE (1 << 20) # define R500_COLOR3_IS_TEXTURE (1 << 21) @@ -433,10 +433,10 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * * These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest. */ -#define R300_VAP_GB_VERT_CLIP_ADJ 0x2220 -#define R300_VAP_GB_VERT_DISC_ADJ 0x2224 -#define R300_VAP_GB_HORZ_CLIP_ADJ 0x2228 -#define R300_VAP_GB_HORZ_DISC_ADJ 0x222c +#define R600_VAP_GB_VERT_CLIP_ADJ 0x2220 +#define R600_VAP_GB_VERT_DISC_ADJ 0x2224 +#define R600_VAP_GB_HORZ_CLIP_ADJ 0x2228 +#define R600_VAP_GB_HORZ_DISC_ADJ 0x222c /* gap */ @@ -445,7 +445,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and * avoids bugs caused by still running shaders reading bad data from memory. */ -#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 +#define R600_VAP_PVS_STATE_FLUSH_REG 0x2284 /* This register is used to define the number of core clocks to wait for a * vertex to be received by the VAP input controller (while the primitive @@ -453,8 +453,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * to the vertex processing path. */ #define VAP_PVS_VTX_TIMEOUT_REG 0x2288 -# define R300_2288_R300 0x00750000 /* -- nh */ -# define R300_2288_RV350 0x0000FFFF /* -- Vladimir */ +# define R600_2288_R600 0x00750000 /* -- nh */ +# define R600_2288_RV350 0x0000FFFF /* -- Vladimir */ /* gap */ @@ -467,7 +467,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * inside the vertex program, otherwise the GPU locks up. * * fglrx usually sets CNTL_3_UNKNOWN to the end of the program and - * R300_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to + * R600_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to * position takes place. * * Most likely this is used to ignore rest of the program in cases @@ -475,59 +475,59 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * is sometimes accepted other instruction that have no relationship with * position calculations. */ -#define R300_VAP_PVS_CODE_CNTL_0 0x22D0 -# define R300_PVS_FIRST_INST_SHIFT 0 -# define R300_PVS_XYZW_VALID_INST_SHIFT 10 -# define R300_PVS_LAST_INST_SHIFT 20 +#define R600_VAP_PVS_CODE_CNTL_0 0x22D0 +# define R600_PVS_FIRST_INST_SHIFT 0 +# define R600_PVS_XYZW_VALID_INST_SHIFT 10 +# define R600_PVS_LAST_INST_SHIFT 20 /* Addresses are relative the the vertex program parameters area. */ -#define R300_VAP_PVS_CONST_CNTL 0x22D4 -# define R300_PVS_CONST_BASE_OFFSET_SHIFT 0 -# define R300_PVS_MAX_CONST_ADDR_SHIFT 16 -#define R300_VAP_PVS_CODE_CNTL_1 0x22D8 -# define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0 -#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22DC +#define R600_VAP_PVS_CONST_CNTL 0x22D4 +# define R600_PVS_CONST_BASE_OFFSET_SHIFT 0 +# define R600_PVS_MAX_CONST_ADDR_SHIFT 16 +#define R600_VAP_PVS_CODE_CNTL_1 0x22D8 +# define R600_PVS_LAST_VTX_SRC_INST_SHIFT 0 +#define R600_VAP_PVS_FLOW_CNTL_OPC 0x22DC /* The entire range from 0x2300 to 0x2AC inclusive seems to be used for * immediate vertices */ -#define R300_VAP_VTX_COLOR_R 0x2464 -#define R300_VAP_VTX_COLOR_G 0x2468 -#define R300_VAP_VTX_COLOR_B 0x246C -#define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */ -#define R300_VAP_VTX_POS_0_Y_1 0x2494 -#define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */ -#define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */ -#define R300_VAP_VTX_POS_0_Y_2 0x24A4 -#define R300_VAP_VTX_POS_0_Z_2 0x24A8 +#define R600_VAP_VTX_COLOR_R 0x2464 +#define R600_VAP_VTX_COLOR_G 0x2468 +#define R600_VAP_VTX_COLOR_B 0x246C +#define R600_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */ +#define R600_VAP_VTX_POS_0_Y_1 0x2494 +#define R600_VAP_VTX_COLOR_PKD 0x249C /* RGBA */ +#define R600_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */ +#define R600_VAP_VTX_POS_0_Y_2 0x24A4 +#define R600_VAP_VTX_POS_0_Z_2 0x24A8 /* write 0 to indicate end of packet? */ -#define R300_VAP_VTX_END_OF_PKT 0x24AC +#define R600_VAP_VTX_END_OF_PKT 0x24AC /* gap */ -/* These are values from r300_reg/r300_reg.h - they are known to be correct +/* These are values from r600_reg/r600_reg.h - they are known to be correct * and are here so we can use one register file instead of several * - Vladimir */ -#define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000 -# define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0) -# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1) -# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2) -# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3) -# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4) -# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5) -# define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16) - -#define R300_GB_VAP_RASTER_VTX_FMT_1 0x4004 +#define R600_GB_VAP_RASTER_VTX_FMT_0 0x4000 +# define R600_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0) +# define R600_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1) +# define R600_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2) +# define R600_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3) +# define R600_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4) +# define R600_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5) +# define R600_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16) + +#define R600_GB_VAP_RASTER_VTX_FMT_1 0x4004 /* each of the following is 3 bits wide, specifies number of components */ -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 -# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 +# define R600_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 +# define R600_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 +# define R600_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 +# define R600_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 +# define R600_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 +# define R600_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 +# define R600_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 +# define R600_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 /* UNK30 seems to enables point to quad transformation on textures * (or something closely related to that). @@ -535,76 +535,76 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * shader side * Specifies top of Raster pipe specific enable controls. */ -#define R300_GB_ENABLE 0x4008 -# define R300_GB_POINT_STUFF_DISABLE (0 << 0) -# define R300_GB_POINT_STUFF_ENABLE (1 << 0) /* Specifies if points will have stuffed texture coordinates. */ -# define R300_GB_LINE_STUFF_DISABLE (0 << 1) -# define R300_GB_LINE_STUFF_ENABLE (1 << 1) /* Specifies if lines will have stuffed texture coordinates. */ -# define R300_GB_TRIANGLE_STUFF_DISABLE (0 << 2) -# define R300_GB_TRIANGLE_STUFF_ENABLE (1 << 2) /* Specifies if triangles will have stuffed texture coordinates. */ -# define R300_GB_STENCIL_AUTO_DISABLE (0 << 4) -# define R300_GB_STENCIL_AUTO_ENABLE (1 << 4) /* Enable stencil auto inc/dec based on triangle cw/ccw, force into dzy low bit. */ -# define R300_GB_STENCIL_AUTO_FORCE (2 << 4) /* Force 0 into dzy low bit. */ +#define R600_GB_ENABLE 0x4008 +# define R600_GB_POINT_STUFF_DISABLE (0 << 0) +# define R600_GB_POINT_STUFF_ENABLE (1 << 0) /* Specifies if points will have stuffed texture coordinates. */ +# define R600_GB_LINE_STUFF_DISABLE (0 << 1) +# define R600_GB_LINE_STUFF_ENABLE (1 << 1) /* Specifies if lines will have stuffed texture coordinates. */ +# define R600_GB_TRIANGLE_STUFF_DISABLE (0 << 2) +# define R600_GB_TRIANGLE_STUFF_ENABLE (1 << 2) /* Specifies if triangles will have stuffed texture coordinates. */ +# define R600_GB_STENCIL_AUTO_DISABLE (0 << 4) +# define R600_GB_STENCIL_AUTO_ENABLE (1 << 4) /* Enable stencil auto inc/dec based on triangle cw/ccw, force into dzy low bit. */ +# define R600_GB_STENCIL_AUTO_FORCE (2 << 4) /* Force 0 into dzy low bit. */ /* each of the following is 2 bits wide */ -#define R300_GB_TEX_REPLICATE 0 /* Replicate VAP source texture coordinates (S,T,[R,Q]). */ -#define R300_GB_TEX_ST 1 /* Stuff with source texture coordinates (S,T). */ -#define R300_GB_TEX_STR 2 /* Stuff with source texture coordinates (S,T,R). */ -# define R300_GB_TEX0_SOURCE_SHIFT 16 -# define R300_GB_TEX1_SOURCE_SHIFT 18 -# define R300_GB_TEX2_SOURCE_SHIFT 20 -# define R300_GB_TEX3_SOURCE_SHIFT 22 -# define R300_GB_TEX4_SOURCE_SHIFT 24 -# define R300_GB_TEX5_SOURCE_SHIFT 26 -# define R300_GB_TEX6_SOURCE_SHIFT 28 -# define R300_GB_TEX7_SOURCE_SHIFT 30 +#define R600_GB_TEX_REPLICATE 0 /* Replicate VAP source texture coordinates (S,T,[R,Q]). */ +#define R600_GB_TEX_ST 1 /* Stuff with source texture coordinates (S,T). */ +#define R600_GB_TEX_STR 2 /* Stuff with source texture coordinates (S,T,R). */ +# define R600_GB_TEX0_SOURCE_SHIFT 16 +# define R600_GB_TEX1_SOURCE_SHIFT 18 +# define R600_GB_TEX2_SOURCE_SHIFT 20 +# define R600_GB_TEX3_SOURCE_SHIFT 22 +# define R600_GB_TEX4_SOURCE_SHIFT 24 +# define R600_GB_TEX5_SOURCE_SHIFT 26 +# define R600_GB_TEX6_SOURCE_SHIFT 28 +# define R600_GB_TEX7_SOURCE_SHIFT 30 /* MSPOS - positions for multisample antialiasing (?) */ -#define R300_GB_MSPOS0 0x4010 +#define R600_GB_MSPOS0 0x4010 /* shifts - each of the fields is 4 bits */ -# define R300_GB_MSPOS0__MS_X0_SHIFT 0 -# define R300_GB_MSPOS0__MS_Y0_SHIFT 4 -# define R300_GB_MSPOS0__MS_X1_SHIFT 8 -# define R300_GB_MSPOS0__MS_Y1_SHIFT 12 -# define R300_GB_MSPOS0__MS_X2_SHIFT 16 -# define R300_GB_MSPOS0__MS_Y2_SHIFT 20 -# define R300_GB_MSPOS0__MSBD0_Y 24 -# define R300_GB_MSPOS0__MSBD0_X 28 - -#define R300_GB_MSPOS1 0x4014 -# define R300_GB_MSPOS1__MS_X3_SHIFT 0 -# define R300_GB_MSPOS1__MS_Y3_SHIFT 4 -# define R300_GB_MSPOS1__MS_X4_SHIFT 8 -# define R300_GB_MSPOS1__MS_Y4_SHIFT 12 -# define R300_GB_MSPOS1__MS_X5_SHIFT 16 -# define R300_GB_MSPOS1__MS_Y5_SHIFT 20 -# define R300_GB_MSPOS1__MSBD1 24 +# define R600_GB_MSPOS0__MS_X0_SHIFT 0 +# define R600_GB_MSPOS0__MS_Y0_SHIFT 4 +# define R600_GB_MSPOS0__MS_X1_SHIFT 8 +# define R600_GB_MSPOS0__MS_Y1_SHIFT 12 +# define R600_GB_MSPOS0__MS_X2_SHIFT 16 +# define R600_GB_MSPOS0__MS_Y2_SHIFT 20 +# define R600_GB_MSPOS0__MSBD0_Y 24 +# define R600_GB_MSPOS0__MSBD0_X 28 + +#define R600_GB_MSPOS1 0x4014 +# define R600_GB_MSPOS1__MS_X3_SHIFT 0 +# define R600_GB_MSPOS1__MS_Y3_SHIFT 4 +# define R600_GB_MSPOS1__MS_X4_SHIFT 8 +# define R600_GB_MSPOS1__MS_Y4_SHIFT 12 +# define R600_GB_MSPOS1__MS_X5_SHIFT 16 +# define R600_GB_MSPOS1__MS_Y5_SHIFT 20 +# define R600_GB_MSPOS1__MSBD1 24 /* Specifies the graphics pipeline configuration for rasterization. */ -#define R300_GB_TILE_CONFIG 0x4018 -# define R300_GB_TILE_DISABLE (0 << 0) -# define R300_GB_TILE_ENABLE (1 << 0) -# define R300_GB_TILE_PIPE_COUNT_RV300 (0 << 1) /* RV350 (1 pipe, 1 ctx) */ -# define R300_GB_TILE_PIPE_COUNT_R300 (3 << 1) /* R300 (2 pipes, 1 ctx) */ -# define R300_GB_TILE_PIPE_COUNT_R420_3P (6 << 1) /* R420-3P (3 pipes, 1 ctx) */ -# define R300_GB_TILE_PIPE_COUNT_R420 (7 << 1) /* R420 (4 pipes, 1 ctx) */ -# define R300_GB_TILE_SIZE_8 (0 << 4) -# define R300_GB_TILE_SIZE_16 (1 << 4) -# define R300_GB_TILE_SIZE_32 (2 << 4) -# define R300_GB_SUPER_SIZE_1 (0 << 6) -# define R300_GB_SUPER_SIZE_2 (1 << 6) -# define R300_GB_SUPER_SIZE_4 (2 << 6) -# define R300_GB_SUPER_SIZE_8 (3 << 6) -# define R300_GB_SUPER_SIZE_16 (4 << 6) -# define R300_GB_SUPER_SIZE_32 (5 << 6) -# define R300_GB_SUPER_SIZE_64 (6 << 6) -# define R300_GB_SUPER_SIZE_128 (7 << 6) -# define R300_GB_SUPER_X_SHIFT 9 /* 3 bits wide */ -# define R300_GB_SUPER_Y_SHIFT 12 /* 3 bits wide */ -# define R300_GB_SUPER_TILE_A (0 << 15) -# define R300_GB_SUPER_TILE_B (1 << 15) -# define R300_GB_SUBPIXEL_1_12 (0 << 16) -# define R300_GB_SUBPIXEL_1_16 (1 << 16) +#define R600_GB_TILE_CONFIG 0x4018 +# define R600_GB_TILE_DISABLE (0 << 0) +# define R600_GB_TILE_ENABLE (1 << 0) +# define R600_GB_TILE_PIPE_COUNT_RV300 (0 << 1) /* RV350 (1 pipe, 1 ctx) */ +# define R600_GB_TILE_PIPE_COUNT_R600 (3 << 1) /* R600 (2 pipes, 1 ctx) */ +# define R600_GB_TILE_PIPE_COUNT_R420_3P (6 << 1) /* R420-3P (3 pipes, 1 ctx) */ +# define R600_GB_TILE_PIPE_COUNT_R420 (7 << 1) /* R420 (4 pipes, 1 ctx) */ +# define R600_GB_TILE_SIZE_8 (0 << 4) +# define R600_GB_TILE_SIZE_16 (1 << 4) +# define R600_GB_TILE_SIZE_32 (2 << 4) +# define R600_GB_SUPER_SIZE_1 (0 << 6) +# define R600_GB_SUPER_SIZE_2 (1 << 6) +# define R600_GB_SUPER_SIZE_4 (2 << 6) +# define R600_GB_SUPER_SIZE_8 (3 << 6) +# define R600_GB_SUPER_SIZE_16 (4 << 6) +# define R600_GB_SUPER_SIZE_32 (5 << 6) +# define R600_GB_SUPER_SIZE_64 (6 << 6) +# define R600_GB_SUPER_SIZE_128 (7 << 6) +# define R600_GB_SUPER_X_SHIFT 9 /* 3 bits wide */ +# define R600_GB_SUPER_Y_SHIFT 12 /* 3 bits wide */ +# define R600_GB_SUPER_TILE_A (0 << 15) +# define R600_GB_SUPER_TILE_B (1 << 15) +# define R600_GB_SUBPIXEL_1_12 (0 << 16) +# define R600_GB_SUBPIXEL_1_16 (1 << 16) # define GB_TILE_CONFIG_QUADS_PER_RAS_4 (0 << 17) # define GB_TILE_CONFIG_QUADS_PER_RAS_8 (1 << 17) # define GB_TILE_CONFIG_QUADS_PER_RAS_16 (2 << 17) @@ -621,51 +621,51 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define GB_TILE_CONFIG_Z_EXTENDED_S25_1 (1 << 24) /* Specifies the sizes of the various FIFO`s in the sc/rs/us. This register must be the first one written */ -#define R300_GB_FIFO_SIZE 0x4024 +#define R600_GB_FIFO_SIZE 0x4024 /* each of the following is 2 bits wide */ -#define R300_GB_FIFO_SIZE_32 0 -#define R300_GB_FIFO_SIZE_64 1 -#define R300_GB_FIFO_SIZE_128 2 -#define R300_GB_FIFO_SIZE_256 3 -# define R300_SC_IFIFO_SIZE_SHIFT 0 -# define R300_SC_TZFIFO_SIZE_SHIFT 2 -# define R300_SC_BFIFO_SIZE_SHIFT 4 - -# define R300_US_OFIFO_SIZE_SHIFT 12 -# define R300_US_WFIFO_SIZE_SHIFT 14 +#define R600_GB_FIFO_SIZE_32 0 +#define R600_GB_FIFO_SIZE_64 1 +#define R600_GB_FIFO_SIZE_128 2 +#define R600_GB_FIFO_SIZE_256 3 +# define R600_SC_IFIFO_SIZE_SHIFT 0 +# define R600_SC_TZFIFO_SIZE_SHIFT 2 +# define R600_SC_BFIFO_SIZE_SHIFT 4 + +# define R600_US_OFIFO_SIZE_SHIFT 12 +# define R600_US_WFIFO_SIZE_SHIFT 14 /* the following use the same constants as above, but meaning is is times 2 (i.e. instead of 32 words it means 64 */ -# define R300_RS_TFIFO_SIZE_SHIFT 6 -# define R300_RS_CFIFO_SIZE_SHIFT 8 -# define R300_US_RAM_SIZE_SHIFT 10 +# define R600_RS_TFIFO_SIZE_SHIFT 6 +# define R600_RS_CFIFO_SIZE_SHIFT 8 +# define R600_US_RAM_SIZE_SHIFT 10 /* watermarks, 3 bits wide */ -# define R300_RS_HIGHWATER_COL_SHIFT 16 -# define R300_RS_HIGHWATER_TEX_SHIFT 19 -# define R300_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */ -# define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT 24 +# define R600_RS_HIGHWATER_COL_SHIFT 16 +# define R600_RS_HIGHWATER_TEX_SHIFT 19 +# define R600_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */ +# define R600_CUBE_FIFO_HIGHWATER_COL_SHIFT 24 #define GB_Z_PEQ_CONFIG 0x4028 # define GB_Z_PEQ_CONFIG_Z_PEQ_SIZE_4_4 (0 << 0) # define GB_Z_PEQ_CONFIG_Z_PEQ_SIZE_8_8 (1 << 0) /* Specifies various polygon specific selects (fog, depth, perspective). */ -#define R300_GB_SELECT 0x401c -# define R300_GB_FOG_SELECT_C0A (0 << 0) -# define R300_GB_FOG_SELECT_C1A (1 << 0) -# define R300_GB_FOG_SELECT_C2A (2 << 0) -# define R300_GB_FOG_SELECT_C3A (3 << 0) -# define R300_GB_FOG_SELECT_1_1_W (4 << 0) -# define R300_GB_FOG_SELECT_Z (5 << 0) -# define R300_GB_DEPTH_SELECT_Z (0 << 3) -# define R300_GB_DEPTH_SELECT_1_1_W (1 << 3) -# define R300_GB_W_SELECT_1_W (0 << 4) -# define R300_GB_W_SELECT_1 (1 << 4) -# define R300_GB_FOG_STUFF_DISABLE (0 << 5) -# define R300_GB_FOG_STUFF_ENABLE (1 << 5) -# define R300_GB_FOG_STUFF_TEX_SHIFT 6 -# define R300_GB_FOG_STUFF_TEX_MASK 0x000003c0 -# define R300_GB_FOG_STUFF_COMP_SHIFT 10 -# define R300_GB_FOG_STUFF_COMP_MASK 0x00000c00 +#define R600_GB_SELECT 0x401c +# define R600_GB_FOG_SELECT_C0A (0 << 0) +# define R600_GB_FOG_SELECT_C1A (1 << 0) +# define R600_GB_FOG_SELECT_C2A (2 << 0) +# define R600_GB_FOG_SELECT_C3A (3 << 0) +# define R600_GB_FOG_SELECT_1_1_W (4 << 0) +# define R600_GB_FOG_SELECT_Z (5 << 0) +# define R600_GB_DEPTH_SELECT_Z (0 << 3) +# define R600_GB_DEPTH_SELECT_1_1_W (1 << 3) +# define R600_GB_W_SELECT_1_W (0 << 4) +# define R600_GB_W_SELECT_1 (1 << 4) +# define R600_GB_FOG_STUFF_DISABLE (0 << 5) +# define R600_GB_FOG_STUFF_ENABLE (1 << 5) +# define R600_GB_FOG_STUFF_TEX_SHIFT 6 +# define R600_GB_FOG_STUFF_TEX_MASK 0x000003c0 +# define R600_GB_FOG_STUFF_COMP_SHIFT 10 +# define R600_GB_FOG_STUFF_COMP_MASK 0x00000c00 /* Specifies the graphics pipeline configuration for antialiasing. */ #define GB_AA_CONFIG 0x4020 @@ -739,27 +739,27 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* gap */ /* Zero to flush caches. */ -#define R300_TX_INVALTAGS 0x4100 -#define R300_TX_FLUSH 0x0 +#define R600_TX_INVALTAGS 0x4100 +#define R600_TX_FLUSH 0x0 /* The upper enable bits are guessed, based on fglrx reported limits. */ -#define R300_TX_ENABLE 0x4104 -# define R300_TX_ENABLE_0 (1 << 0) -# define R300_TX_ENABLE_1 (1 << 1) -# define R300_TX_ENABLE_2 (1 << 2) -# define R300_TX_ENABLE_3 (1 << 3) -# define R300_TX_ENABLE_4 (1 << 4) -# define R300_TX_ENABLE_5 (1 << 5) -# define R300_TX_ENABLE_6 (1 << 6) -# define R300_TX_ENABLE_7 (1 << 7) -# define R300_TX_ENABLE_8 (1 << 8) -# define R300_TX_ENABLE_9 (1 << 9) -# define R300_TX_ENABLE_10 (1 << 10) -# define R300_TX_ENABLE_11 (1 << 11) -# define R300_TX_ENABLE_12 (1 << 12) -# define R300_TX_ENABLE_13 (1 << 13) -# define R300_TX_ENABLE_14 (1 << 14) -# define R300_TX_ENABLE_15 (1 << 15) +#define R600_TX_ENABLE 0x4104 +# define R600_TX_ENABLE_0 (1 << 0) +# define R600_TX_ENABLE_1 (1 << 1) +# define R600_TX_ENABLE_2 (1 << 2) +# define R600_TX_ENABLE_3 (1 << 3) +# define R600_TX_ENABLE_4 (1 << 4) +# define R600_TX_ENABLE_5 (1 << 5) +# define R600_TX_ENABLE_6 (1 << 6) +# define R600_TX_ENABLE_7 (1 << 7) +# define R600_TX_ENABLE_8 (1 << 8) +# define R600_TX_ENABLE_9 (1 << 9) +# define R600_TX_ENABLE_10 (1 << 10) +# define R600_TX_ENABLE_11 (1 << 11) +# define R600_TX_ENABLE_12 (1 << 12) +# define R600_TX_ENABLE_13 (1 << 13) +# define R600_TX_ENABLE_14 (1 << 14) +# define R600_TX_ENABLE_15 (1 << 15) #define R500_TX_FILTER_4 0x4110 # define R500_TX_WEIGHT_1_SHIFT (0) @@ -770,37 +770,37 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R500_TX_DIRECTION_VERITCAL (1<<27) /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) */ -#define R300_GA_POINT_S0 0x4200 +#define R600_GA_POINT_S0 0x4200 /* T Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) */ -#define R300_GA_POINT_T0 0x4204 +#define R600_GA_POINT_T0 0x4204 /* S Texture Coordinate of Vertex 2 for Point texture stuffing (URC) */ -#define R300_GA_POINT_S1 0x4208 +#define R600_GA_POINT_S1 0x4208 /* T Texture Coordinate of Vertex 2 for Point texture stuffing (URC) */ -#define R300_GA_POINT_T1 0x420c +#define R600_GA_POINT_T1 0x420c /* Specifies amount to shift integer position of vertex (screen space) before * converting to float for triangle stipple. */ -#define R300_GA_TRIANGLE_STIPPLE 0x4214 -# define R300_GA_TRIANGLE_STIPPLE_X_SHIFT_SHIFT 0 -# define R300_GA_TRIANGLE_STIPPLE_X_SHIFT_MASK 0x0000000f -# define R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT 16 -# define R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_MASK 0x000f0000 +#define R600_GA_TRIANGLE_STIPPLE 0x4214 +# define R600_GA_TRIANGLE_STIPPLE_X_SHIFT_SHIFT 0 +# define R600_GA_TRIANGLE_STIPPLE_X_SHIFT_MASK 0x0000000f +# define R600_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT 16 +# define R600_GA_TRIANGLE_STIPPLE_Y_SHIFT_MASK 0x000f0000 /* The pointsize is given in multiples of 6. The pointsize can be enormous: * Clear() renders a single point that fills the entire framebuffer. * 1/2 Height of point; fixed (16.0), subpixel format (1/12 or 1/16, even if in * 8b precision). */ -#define R300_GA_POINT_SIZE 0x421C -# define R300_POINTSIZE_Y_SHIFT 0 -# define R300_POINTSIZE_Y_MASK 0x0000ffff -# define R300_POINTSIZE_X_SHIFT 16 -# define R300_POINTSIZE_X_MASK 0xffff0000 -# define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6) +#define R600_GA_POINT_SIZE 0x421C +# define R600_POINTSIZE_Y_SHIFT 0 +# define R600_POINTSIZE_Y_MASK 0x0000ffff +# define R600_POINTSIZE_X_SHIFT 16 +# define R600_POINTSIZE_X_MASK 0xffff0000 +# define R600_POINTSIZE_MAX (R600_POINTSIZE_Y_MASK / 6) /* Blue fill color */ #define R500_GA_FILL_R 0x4220 @@ -818,11 +818,11 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* Specifies maximum and minimum point & sprite sizes for per vertex size * specification. The lower part (15:0) is MIN and (31:16) is max. */ -#define R300_GA_POINT_MINMAX 0x4230 -# define R300_GA_POINT_MINMAX_MIN_SHIFT 0 -# define R300_GA_POINT_MINMAX_MIN_MASK (0xFFFF << 0) -# define R300_GA_POINT_MINMAX_MAX_SHIFT 16 -# define R300_GA_POINT_MINMAX_MAX_MASK (0xFFFF << 16) +#define R600_GA_POINT_MINMAX 0x4230 +# define R600_GA_POINT_MINMAX_MIN_SHIFT 0 +# define R600_GA_POINT_MINMAX_MIN_MASK (0xFFFF << 0) +# define R600_GA_POINT_MINMAX_MAX_SHIFT 16 +# define R600_GA_POINT_MINMAX_MAX_MASK (0xFFFF << 16) /* 1/2 width of line, in subpixels (1/12 or 1/16 only, even in 8b * subprecision); (16.0) fixed format. @@ -833,29 +833,29 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * VE: vertical or horizontal * HO & VE: no classification */ -#define R300_GA_LINE_CNTL 0x4234 -# define R300_GA_LINE_CNTL_WIDTH_SHIFT 0 -# define R300_GA_LINE_CNTL_WIDTH_MASK 0x0000ffff -# define R300_GA_LINE_CNTL_END_TYPE_HOR (0 << 16) -# define R300_GA_LINE_CNTL_END_TYPE_VER (1 << 16) -# define R300_GA_LINE_CNTL_END_TYPE_SQR (2 << 16) /* horizontal or vertical depending upon slope */ -# define R300_GA_LINE_CNTL_END_TYPE_COMP (3 << 16) /* Computed (perpendicular to slope) */ +#define R600_GA_LINE_CNTL 0x4234 +# define R600_GA_LINE_CNTL_WIDTH_SHIFT 0 +# define R600_GA_LINE_CNTL_WIDTH_MASK 0x0000ffff +# define R600_GA_LINE_CNTL_END_TYPE_HOR (0 << 16) +# define R600_GA_LINE_CNTL_END_TYPE_VER (1 << 16) +# define R600_GA_LINE_CNTL_END_TYPE_SQR (2 << 16) /* horizontal or vertical depending upon slope */ +# define R600_GA_LINE_CNTL_END_TYPE_COMP (3 << 16) /* Computed (perpendicular to slope) */ # define R500_GA_LINE_CNTL_SORT_NO (0 << 18) # define R500_GA_LINE_CNTL_SORT_MINX_MINY (1 << 18) /** TODO: looks wrong */ -# define R300_LINESIZE_MAX (R300_GA_LINE_CNTL_WIDTH_MASK / 6) +# define R600_LINESIZE_MAX (R600_GA_LINE_CNTL_WIDTH_MASK / 6) /** TODO: looks wrong */ -# define R300_LINE_CNT_HO (1 << 16) +# define R600_LINE_CNT_HO (1 << 16) /** TODO: looks wrong */ -# define R300_LINE_CNT_VE (1 << 17) +# define R600_LINE_CNT_VE (1 << 17) /* Line Stipple configuration information. */ -#define R300_GA_LINE_STIPPLE_CONFIG 0x4238 -# define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_NO (0 << 0) -# define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE (1 << 0) -# define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_PACKET (2 << 0) -# define R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_SHIFT 2 -# define R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK 0xfffffffc +#define R600_GA_LINE_STIPPLE_CONFIG 0x4238 +# define R600_GA_LINE_STIPPLE_CONFIG_LINE_RESET_NO (0 << 0) +# define R600_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE (1 << 0) +# define R600_GA_LINE_STIPPLE_CONFIG_LINE_RESET_PACKET (2 << 0) +# define R600_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_SHIFT 2 +# define R600_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK 0xfffffffc /* Used to load US instructions and constants */ #define R500_GA_US_VECTOR_INDEX 0x4250 @@ -960,12 +960,12 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R500_GA_IDLE_GA_UNIT2_IDLE (0 << 26) /* Current value of stipple accumulator. */ -#define R300_GA_LINE_STIPPLE_VALUE 0x4260 +#define R600_GA_LINE_STIPPLE_VALUE 0x4260 /* S Texture Coordinate Value for Vertex 0 of Line (stuff textures -- i.e. AA) */ -#define R300_GA_LINE_S0 0x4264 +#define R600_GA_LINE_S0 0x4264 /* S Texture Coordinate Value for Vertex 1 of Lines (V2 of parallelogram -- stuff textures -- i.e. AA) */ -#define R300_GA_LINE_S1 0x4268 +#define R600_GA_LINE_S1 0x4268 /* GA Input fifo high water marks */ #define R500_GA_FIFO_CNTL 0x4270 @@ -977,69 +977,69 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R500_GA_FIFO_CNTL_VERTEX_REG_SHIFT 6 /* GA enhance/tweaks */ -#define R300_GA_ENHANCE 0x4274 -# define R300_GA_ENHANCE_DEADLOCK_CNTL_NO_EFFECT (0 << 0) -# define R300_GA_ENHANCE_DEADLOCK_CNTL_PREVENT_TCL (1 << 0) /* Prevents TCL interface from deadlocking on GA side. */ -# define R300_GA_ENHANCE_FASTSYNC_CNTL_NO_EFFECT (0 << 1) -# define R300_GA_ENHANCE_FASTSYNC_CNTL_ENABLE (1 << 1) /* Enables high-performance register/primitive switching. */ +#define R600_GA_ENHANCE 0x4274 +# define R600_GA_ENHANCE_DEADLOCK_CNTL_NO_EFFECT (0 << 0) +# define R600_GA_ENHANCE_DEADLOCK_CNTL_PREVENT_TCL (1 << 0) /* Prevents TCL interface from deadlocking on GA side. */ +# define R600_GA_ENHANCE_FASTSYNC_CNTL_NO_EFFECT (0 << 1) +# define R600_GA_ENHANCE_FASTSYNC_CNTL_ENABLE (1 << 1) /* Enables high-performance register/primitive switching. */ # define R500_GA_ENHANCE_REG_READWRITE_NO_EFFECT (0 << 2) /* R520+ only */ # define R500_GA_ENHANCE_REG_READWRITE_ENABLE (1 << 2) /* R520+ only, Enables GA support of simultaneous register reads and writes. */ # define R500_GA_ENHANCE_REG_NOSTALL_NO_EFFECT (0 << 3) # define R500_GA_ENHANCE_REG_NOSTALL_ENABLE (1 << 3) /* Enables GA support of no-stall reads for register read back. */ -#define R300_GA_COLOR_CONTROL 0x4278 -# define R300_GA_COLOR_CONTROL_RGB0_SHADING_SOLID (0 << 0) -# define R300_GA_COLOR_CONTROL_RGB0_SHADING_FLAT (1 << 0) -# define R300_GA_COLOR_CONTROL_RGB0_SHADING_GOURAUD (2 << 0) -# define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_SOLID (0 << 2) -# define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_FLAT (1 << 2) -# define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_GOURAUD (2 << 2) -# define R300_GA_COLOR_CONTROL_RGB1_SHADING_SOLID (0 << 4) -# define R300_GA_COLOR_CONTROL_RGB1_SHADING_FLAT (1 << 4) -# define R300_GA_COLOR_CONTROL_RGB1_SHADING_GOURAUD (2 << 4) -# define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_SOLID (0 << 6) -# define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_FLAT (1 << 6) -# define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD (2 << 6) -# define R300_GA_COLOR_CONTROL_RGB2_SHADING_SOLID (0 << 8) -# define R300_GA_COLOR_CONTROL_RGB2_SHADING_FLAT (1 << 8) -# define R300_GA_COLOR_CONTROL_RGB2_SHADING_GOURAUD (2 << 8) -# define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_SOLID (0 << 10) -# define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_FLAT (1 << 10) -# define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_GOURAUD (2 << 10) -# define R300_GA_COLOR_CONTROL_RGB3_SHADING_SOLID (0 << 12) -# define R300_GA_COLOR_CONTROL_RGB3_SHADING_FLAT (1 << 12) -# define R300_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD (2 << 12) -# define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_SOLID (0 << 14) -# define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_FLAT (1 << 14) -# define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD (2 << 14) -# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_FIRST (0 << 16) -# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_SECOND (1 << 16) -# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_THIRD (2 << 16) -# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST (3 << 16) +#define R600_GA_COLOR_CONTROL 0x4278 +# define R600_GA_COLOR_CONTROL_RGB0_SHADING_SOLID (0 << 0) +# define R600_GA_COLOR_CONTROL_RGB0_SHADING_FLAT (1 << 0) +# define R600_GA_COLOR_CONTROL_RGB0_SHADING_GOURAUD (2 << 0) +# define R600_GA_COLOR_CONTROL_ALPHA0_SHADING_SOLID (0 << 2) +# define R600_GA_COLOR_CONTROL_ALPHA0_SHADING_FLAT (1 << 2) +# define R600_GA_COLOR_CONTROL_ALPHA0_SHADING_GOURAUD (2 << 2) +# define R600_GA_COLOR_CONTROL_RGB1_SHADING_SOLID (0 << 4) +# define R600_GA_COLOR_CONTROL_RGB1_SHADING_FLAT (1 << 4) +# define R600_GA_COLOR_CONTROL_RGB1_SHADING_GOURAUD (2 << 4) +# define R600_GA_COLOR_CONTROL_ALPHA1_SHADING_SOLID (0 << 6) +# define R600_GA_COLOR_CONTROL_ALPHA1_SHADING_FLAT (1 << 6) +# define R600_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD (2 << 6) +# define R600_GA_COLOR_CONTROL_RGB2_SHADING_SOLID (0 << 8) +# define R600_GA_COLOR_CONTROL_RGB2_SHADING_FLAT (1 << 8) +# define R600_GA_COLOR_CONTROL_RGB2_SHADING_GOURAUD (2 << 8) +# define R600_GA_COLOR_CONTROL_ALPHA2_SHADING_SOLID (0 << 10) +# define R600_GA_COLOR_CONTROL_ALPHA2_SHADING_FLAT (1 << 10) +# define R600_GA_COLOR_CONTROL_ALPHA2_SHADING_GOURAUD (2 << 10) +# define R600_GA_COLOR_CONTROL_RGB3_SHADING_SOLID (0 << 12) +# define R600_GA_COLOR_CONTROL_RGB3_SHADING_FLAT (1 << 12) +# define R600_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD (2 << 12) +# define R600_GA_COLOR_CONTROL_ALPHA3_SHADING_SOLID (0 << 14) +# define R600_GA_COLOR_CONTROL_ALPHA3_SHADING_FLAT (1 << 14) +# define R600_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD (2 << 14) +# define R600_GA_COLOR_CONTROL_PROVOKING_VERTEX_FIRST (0 << 16) +# define R600_GA_COLOR_CONTROL_PROVOKING_VERTEX_SECOND (1 << 16) +# define R600_GA_COLOR_CONTROL_PROVOKING_VERTEX_THIRD (2 << 16) +# define R600_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST (3 << 16) /** TODO: might be candidate for removal */ -# define R300_RE_SHADE_MODEL_SMOOTH ( \ - R300_GA_COLOR_CONTROL_RGB0_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA0_SHADING_GOURAUD | \ - R300_GA_COLOR_CONTROL_RGB1_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD | \ - R300_GA_COLOR_CONTROL_RGB2_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA2_SHADING_GOURAUD | \ - R300_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD | \ - R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST ) +# define R600_RE_SHADE_MODEL_SMOOTH ( \ + R600_GA_COLOR_CONTROL_RGB0_SHADING_GOURAUD | R600_GA_COLOR_CONTROL_ALPHA0_SHADING_GOURAUD | \ + R600_GA_COLOR_CONTROL_RGB1_SHADING_GOURAUD | R600_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD | \ + R600_GA_COLOR_CONTROL_RGB2_SHADING_GOURAUD | R600_GA_COLOR_CONTROL_ALPHA2_SHADING_GOURAUD | \ + R600_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD | R600_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD | \ + R600_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST ) /** TODO: might be candidate for removal, the GOURAUD stuff also looks buggy to me */ -# define R300_RE_SHADE_MODEL_FLAT ( \ - R300_GA_COLOR_CONTROL_RGB0_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA0_SHADING_FLAT | \ - R300_GA_COLOR_CONTROL_RGB1_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD | \ - R300_GA_COLOR_CONTROL_RGB2_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA2_SHADING_FLAT | \ - R300_GA_COLOR_CONTROL_RGB3_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD | \ - R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST ) +# define R600_RE_SHADE_MODEL_FLAT ( \ + R600_GA_COLOR_CONTROL_RGB0_SHADING_FLAT | R600_GA_COLOR_CONTROL_ALPHA0_SHADING_FLAT | \ + R600_GA_COLOR_CONTROL_RGB1_SHADING_FLAT | R600_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD | \ + R600_GA_COLOR_CONTROL_RGB2_SHADING_FLAT | R600_GA_COLOR_CONTROL_ALPHA2_SHADING_FLAT | \ + R600_GA_COLOR_CONTROL_RGB3_SHADING_FLAT | R600_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD | \ + R600_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST ) /* Specifies red & green components of fill color -- S312 format -- Backwards comp. */ -#define R300_GA_SOLID_RG 0x427c +#define R600_GA_SOLID_RG 0x427c # define GA_SOLID_RG_COLOR_GREEN_SHIFT 0 # define GA_SOLID_RG_COLOR_GREEN_MASK 0x0000ffff # define GA_SOLID_RG_COLOR_RED_SHIFT 16 # define GA_SOLID_RG_COLOR_RED_MASK 0xffff0000 /* Specifies blue & alpha components of fill color -- S312 format -- Backwards comp. */ -#define R300_GA_SOLID_BA 0x4280 +#define R600_GA_SOLID_BA 0x4280 # define GA_SOLID_BA_COLOR_ALPHA_SHIFT 0 # define GA_SOLID_BA_COLOR_ALPHA_MASK 0x0000ffff # define GA_SOLID_BA_COLOR_BLUE_SHIFT 16 @@ -1048,29 +1048,29 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* Polygon Mode * Dangerous */ -#define R300_GA_POLY_MODE 0x4288 -# define R300_GA_POLY_MODE_DISABLE (0 << 0) -# define R300_GA_POLY_MODE_DUAL (1 << 0) /* send 2 sets of 3 polys with specified poly type */ +#define R600_GA_POLY_MODE 0x4288 +# define R600_GA_POLY_MODE_DISABLE (0 << 0) +# define R600_GA_POLY_MODE_DUAL (1 << 0) /* send 2 sets of 3 polys with specified poly type */ /* reserved */ -# define R300_GA_POLY_MODE_FRONT_PTYPE_POINT (0 << 4) -# define R300_GA_POLY_MODE_FRONT_PTYPE_LINE (1 << 4) -# define R300_GA_POLY_MODE_FRONT_PTYPE_TRI (2 << 4) +# define R600_GA_POLY_MODE_FRONT_PTYPE_POINT (0 << 4) +# define R600_GA_POLY_MODE_FRONT_PTYPE_LINE (1 << 4) +# define R600_GA_POLY_MODE_FRONT_PTYPE_TRI (2 << 4) /* reserved */ -# define R300_GA_POLY_MODE_BACK_PTYPE_POINT (0 << 7) -# define R300_GA_POLY_MODE_BACK_PTYPE_LINE (1 << 7) -# define R300_GA_POLY_MODE_BACK_PTYPE_TRI (2 << 7) +# define R600_GA_POLY_MODE_BACK_PTYPE_POINT (0 << 7) +# define R600_GA_POLY_MODE_BACK_PTYPE_LINE (1 << 7) +# define R600_GA_POLY_MODE_BACK_PTYPE_TRI (2 << 7) /* reserved */ /* Specifies the rouding mode for geometry & color SPFP to FP conversions. */ -#define R300_GA_ROUND_MODE 0x428c -# define R300_GA_ROUND_MODE_GEOMETRY_ROUND_TRUNC (0 << 0) -# define R300_GA_ROUND_MODE_GEOMETRY_ROUND_NEAREST (1 << 0) -# define R300_GA_ROUND_MODE_COLOR_ROUND_TRUNC (0 << 2) -# define R300_GA_ROUND_MODE_COLOR_ROUND_NEAREST (1 << 2) -# define R300_GA_ROUND_MODE_RGB_CLAMP_RGB (0 << 4) -# define R300_GA_ROUND_MODE_RGB_CLAMP_FP20 (1 << 4) -# define R300_GA_ROUND_MODE_ALPHA_CLAMP_RGB (0 << 5) -# define R300_GA_ROUND_MODE_ALPHA_CLAMP_FP20 (1 << 5) +#define R600_GA_ROUND_MODE 0x428c +# define R600_GA_ROUND_MODE_GEOMETRY_ROUND_TRUNC (0 << 0) +# define R600_GA_ROUND_MODE_GEOMETRY_ROUND_NEAREST (1 << 0) +# define R600_GA_ROUND_MODE_COLOR_ROUND_TRUNC (0 << 2) +# define R600_GA_ROUND_MODE_COLOR_ROUND_NEAREST (1 << 2) +# define R600_GA_ROUND_MODE_RGB_CLAMP_RGB (0 << 4) +# define R600_GA_ROUND_MODE_RGB_CLAMP_FP20 (1 << 4) +# define R600_GA_ROUND_MODE_ALPHA_CLAMP_RGB (0 << 5) +# define R600_GA_ROUND_MODE_ALPHA_CLAMP_FP20 (1 << 5) # define R500_GA_ROUND_MODE_GEOMETRY_MASK_SHIFT 6 # define R500_GA_ROUND_MODE_GEOMETRY_MASK_MASK 0x000003c0 @@ -1078,18 +1078,18 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * Offsets are in S15 format (subpixels -- 1/12 or 1/16, even in 8b * subprecision). */ -#define R300_GA_OFFSET 0x4290 -# define R300_GA_OFFSET_X_OFFSET_SHIFT 0 -# define R300_GA_OFFSET_X_OFFSET_MASK 0x0000ffff -# define R300_GA_OFFSET_Y_OFFSET_SHIFT 16 -# define R300_GA_OFFSET_Y_OFFSET_MASK 0xffff0000 +#define R600_GA_OFFSET 0x4290 +# define R600_GA_OFFSET_X_OFFSET_SHIFT 0 +# define R600_GA_OFFSET_X_OFFSET_MASK 0x0000ffff +# define R600_GA_OFFSET_Y_OFFSET_SHIFT 16 +# define R600_GA_OFFSET_Y_OFFSET_MASK 0xffff0000 /* Specifies the scale to apply to fog. */ -#define R300_GA_FOG_SCALE 0x4294 +#define R600_GA_FOG_SCALE 0x4294 /* Specifies the offset to apply to fog. */ -#define R300_GA_FOG_OFFSET 0x4298 +#define R600_GA_FOG_OFFSET 0x4298 /* Specifies number of cycles to assert reset, and also causes RB3D soft reset to assert. */ -#define R300_GA_SOFT_RESET 0x429c +#define R600_GA_SOFT_RESET 0x429c /* Not sure why there are duplicate of factor and constant values. * My best guess so far is that there are seperate zbiases for test and write. @@ -1097,14 +1097,14 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * Some of the tests indicate that fgl has a fallback implementation of zbias * via pixel shaders. */ -#define R300_SU_TEX_WRAP 0x42A0 -#define R300_SU_POLY_OFFSET_FRONT_SCALE 0x42A4 -#define R300_SU_POLY_OFFSET_FRONT_OFFSET 0x42A8 -#define R300_SU_POLY_OFFSET_BACK_SCALE 0x42AC -#define R300_SU_POLY_OFFSET_BACK_OFFSET 0x42B0 +#define R600_SU_TEX_WRAP 0x42A0 +#define R600_SU_POLY_OFFSET_FRONT_SCALE 0x42A4 +#define R600_SU_POLY_OFFSET_FRONT_OFFSET 0x42A8 +#define R600_SU_POLY_OFFSET_BACK_SCALE 0x42AC +#define R600_SU_POLY_OFFSET_BACK_OFFSET 0x42B0 /* This register needs to be set to (1<<1) for RV350 to correctly - * perform depth test (see --vb-triangles in r300_demo) + * perform depth test (see --vb-triangles in r600_demo) * Don't know about other chips. - Vladimir * This is set to 3 when GL_POLYGON_OFFSET_FILL is on. * My guess is that there are two bits for each zbias primitive @@ -1112,21 +1112,21 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * One to enable depth test and one for depth write. * Yet this doesnt explain why depth writes work ... */ -#define R300_SU_POLY_OFFSET_ENABLE 0x42B4 -# define R300_FRONT_ENABLE (1 << 0) -# define R300_BACK_ENABLE (1 << 1) -# define R300_PARA_ENABLE (1 << 2) +#define R600_SU_POLY_OFFSET_ENABLE 0x42B4 +# define R600_FRONT_ENABLE (1 << 0) +# define R600_BACK_ENABLE (1 << 1) +# define R600_PARA_ENABLE (1 << 2) -#define R300_SU_CULL_MODE 0x42B8 -# define R300_CULL_FRONT (1 << 0) -# define R300_CULL_BACK (1 << 1) -# define R300_FRONT_FACE_CCW (0 << 2) -# define R300_FRONT_FACE_CW (1 << 2) +#define R600_SU_CULL_MODE 0x42B8 +# define R600_CULL_FRONT (1 << 0) +# define R600_CULL_BACK (1 << 1) +# define R600_FRONT_FACE_CCW (0 << 2) +# define R600_FRONT_FACE_CW (1 << 2) /* SU Depth Scale value */ -#define R300_SU_DEPTH_SCALE 0x42c0 +#define R600_SU_DEPTH_SCALE 0x42c0 /* SU Depth Offset value */ -#define R300_SU_DEPTH_OFFSET 0x42c4 +#define R600_SU_DEPTH_OFFSET 0x42c4 /* BEGIN: Rasterization / Interpolators - many guesses */ @@ -1135,21 +1135,21 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends * on the vertex program, *not* the fragment program) */ -#define R300_RS_COUNT 0x4300 -# define R300_IT_COUNT_SHIFT 0 -# define R300_IT_COUNT_MASK 0x0000007f -# define R300_IC_COUNT_SHIFT 7 -# define R300_IC_COUNT_MASK 0x00000780 -# define R300_W_ADDR_SHIFT 12 -# define R300_W_ADDR_MASK 0x0003f000 -# define R300_HIRES_DIS (0 << 18) -# define R300_HIRES_EN (1 << 18) - -#define R300_RS_INST_COUNT 0x4304 -# define R300_RS_INST_COUNT_SHIFT 0 -# define R300_RS_INST_COUNT_MASK 0x0000000f -# define R300_RS_TX_OFFSET_SHIFT 5 -# define R300_RS_TX_OFFSET_MASK 0x000000e0 +#define R600_RS_COUNT 0x4300 +# define R600_IT_COUNT_SHIFT 0 +# define R600_IT_COUNT_MASK 0x0000007f +# define R600_IC_COUNT_SHIFT 7 +# define R600_IC_COUNT_MASK 0x00000780 +# define R600_W_ADDR_SHIFT 12 +# define R600_W_ADDR_MASK 0x0003f000 +# define R600_HIRES_DIS (0 << 18) +# define R600_HIRES_EN (1 << 18) + +#define R600_RS_INST_COUNT 0x4304 +# define R600_RS_INST_COUNT_SHIFT 0 +# define R600_RS_INST_COUNT_MASK 0x0000000f +# define R600_RS_TX_OFFSET_SHIFT 5 +# define R600_RS_TX_OFFSET_MASK 0x000000e0 /* gap */ @@ -1166,34 +1166,34 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * Note: The _UNKNOWN constants are always set in their respective * register. I don't know if this is necessary. */ -#define R300_RS_IP_0 0x4310 -#define R300_RS_IP_1 0x4314 -#define R300_RS_IP_2 0x4318 -#define R300_RS_IP_3 0x431C -# define R300_RS_INTERP_SRC_SHIFT 2 /* TODO: check for removal */ -# define R300_RS_INTERP_SRC_MASK (7 << 2) /* TODO: check for removal */ -# define R300_RS_TEX_PTR(x) ((x) << 0) -# define R300_RS_COL_PTR(x) ((x) << 6) -# define R300_RS_COL_FMT(x) ((x) << 9) -# define R300_RS_COL_FMT_RGBA 0 -# define R300_RS_COL_FMT_RGB0 1 -# define R300_RS_COL_FMT_RGB1 2 -# define R300_RS_COL_FMT_000A 4 -# define R300_RS_COL_FMT_0000 5 -# define R300_RS_COL_FMT_0001 6 -# define R300_RS_COL_FMT_111A 8 -# define R300_RS_COL_FMT_1110 9 -# define R300_RS_COL_FMT_1111 10 -# define R300_RS_SEL_S(x) ((x) << 13) -# define R300_RS_SEL_T(x) ((x) << 16) -# define R300_RS_SEL_R(x) ((x) << 19) -# define R300_RS_SEL_Q(x) ((x) << 22) -# define R300_RS_SEL_C0 0 -# define R300_RS_SEL_C1 1 -# define R300_RS_SEL_C2 2 -# define R300_RS_SEL_C3 3 -# define R300_RS_SEL_K0 4 -# define R300_RS_SEL_K1 5 +#define R600_RS_IP_0 0x4310 +#define R600_RS_IP_1 0x4314 +#define R600_RS_IP_2 0x4318 +#define R600_RS_IP_3 0x431C +# define R600_RS_INTERP_SRC_SHIFT 2 /* TODO: check for removal */ +# define R600_RS_INTERP_SRC_MASK (7 << 2) /* TODO: check for removal */ +# define R600_RS_TEX_PTR(x) ((x) << 0) +# define R600_RS_COL_PTR(x) ((x) << 6) +# define R600_RS_COL_FMT(x) ((x) << 9) +# define R600_RS_COL_FMT_RGBA 0 +# define R600_RS_COL_FMT_RGB0 1 +# define R600_RS_COL_FMT_RGB1 2 +# define R600_RS_COL_FMT_000A 4 +# define R600_RS_COL_FMT_0000 5 +# define R600_RS_COL_FMT_0001 6 +# define R600_RS_COL_FMT_111A 8 +# define R600_RS_COL_FMT_1110 9 +# define R600_RS_COL_FMT_1111 10 +# define R600_RS_SEL_S(x) ((x) << 13) +# define R600_RS_SEL_T(x) ((x) << 16) +# define R600_RS_SEL_R(x) ((x) << 19) +# define R600_RS_SEL_Q(x) ((x) << 22) +# define R600_RS_SEL_C0 0 +# define R600_RS_SEL_C1 1 +# define R600_RS_SEL_C2 2 +# define R600_RS_SEL_C3 3 +# define R600_RS_SEL_K0 4 +# define R600_RS_SEL_K1 5 /* */ @@ -1232,47 +1232,47 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* These DWORDs control how vertex data is routed into fragment program * registers, after interpolators. */ -#define R300_RS_INST_0 0x4330 -#define R300_RS_INST_1 0x4334 -#define R300_RS_INST_2 0x4338 -#define R300_RS_INST_3 0x433C /* GUESS */ -#define R300_RS_INST_4 0x4340 /* GUESS */ -#define R300_RS_INST_5 0x4344 /* GUESS */ -#define R300_RS_INST_6 0x4348 /* GUESS */ -#define R300_RS_INST_7 0x434C /* GUESS */ -# define R300_RS_INST_TEX_ID(x) ((x) << 0) -# define R300_RS_INST_TEX_CN_WRITE (1 << 3) -# define R300_RS_INST_TEX_ADDR_SHIFT 6 -# define R300_RS_INST_TEX_ADDR(x) ((x) << R300_RS_INST_TEX_ADDR_SHIFT) -# define R300_RS_INST_COL_ID(x) ((x) << 11) -# define R300_RS_INST_COL_CN_WRITE (1 << 14) -# define R300_RS_INST_COL_ADDR_SHIFT 17 -# define R300_RS_INST_COL_ADDR(x) ((x) << R300_RS_INST_COL_ADDR_SHIFT) -# define R300_RS_INST_TEX_ADJ (1 << 22) -# define R300_RS_COL_BIAS_UNUSED_SHIFT 23 +#define R600_RS_INST_0 0x4330 +#define R600_RS_INST_1 0x4334 +#define R600_RS_INST_2 0x4338 +#define R600_RS_INST_3 0x433C /* GUESS */ +#define R600_RS_INST_4 0x4340 /* GUESS */ +#define R600_RS_INST_5 0x4344 /* GUESS */ +#define R600_RS_INST_6 0x4348 /* GUESS */ +#define R600_RS_INST_7 0x434C /* GUESS */ +# define R600_RS_INST_TEX_ID(x) ((x) << 0) +# define R600_RS_INST_TEX_CN_WRITE (1 << 3) +# define R600_RS_INST_TEX_ADDR_SHIFT 6 +# define R600_RS_INST_TEX_ADDR(x) ((x) << R600_RS_INST_TEX_ADDR_SHIFT) +# define R600_RS_INST_COL_ID(x) ((x) << 11) +# define R600_RS_INST_COL_CN_WRITE (1 << 14) +# define R600_RS_INST_COL_ADDR_SHIFT 17 +# define R600_RS_INST_COL_ADDR(x) ((x) << R600_RS_INST_COL_ADDR_SHIFT) +# define R600_RS_INST_TEX_ADJ (1 << 22) +# define R600_RS_COL_BIAS_UNUSED_SHIFT 23 /* END: Rasterization / Interpolators - many guesses */ /* Hierarchical Z Enable */ -#define R300_SC_HYPERZ 0x43a4 -# define R300_SC_HYPERZ_DISABLE (0 << 0) -# define R300_SC_HYPERZ_ENABLE (1 << 0) -# define R300_SC_HYPERZ_MIN (0 << 1) -# define R300_SC_HYPERZ_MAX (1 << 1) -# define R300_SC_HYPERZ_ADJ_256 (0 << 2) -# define R300_SC_HYPERZ_ADJ_128 (1 << 2) -# define R300_SC_HYPERZ_ADJ_64 (2 << 2) -# define R300_SC_HYPERZ_ADJ_32 (3 << 2) -# define R300_SC_HYPERZ_ADJ_16 (4 << 2) -# define R300_SC_HYPERZ_ADJ_8 (5 << 2) -# define R300_SC_HYPERZ_ADJ_4 (6 << 2) -# define R300_SC_HYPERZ_ADJ_2 (7 << 2) -# define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5) -# define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5) -# define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6) -# define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6) - -#define R300_SC_EDGERULE 0x43a8 +#define R600_SC_HYPERZ 0x43a4 +# define R600_SC_HYPERZ_DISABLE (0 << 0) +# define R600_SC_HYPERZ_ENABLE (1 << 0) +# define R600_SC_HYPERZ_MIN (0 << 1) +# define R600_SC_HYPERZ_MAX (1 << 1) +# define R600_SC_HYPERZ_ADJ_256 (0 << 2) +# define R600_SC_HYPERZ_ADJ_128 (1 << 2) +# define R600_SC_HYPERZ_ADJ_64 (2 << 2) +# define R600_SC_HYPERZ_ADJ_32 (3 << 2) +# define R600_SC_HYPERZ_ADJ_16 (4 << 2) +# define R600_SC_HYPERZ_ADJ_8 (5 << 2) +# define R600_SC_HYPERZ_ADJ_4 (6 << 2) +# define R600_SC_HYPERZ_ADJ_2 (7 << 2) +# define R600_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5) +# define R600_SC_HYPERZ_HZ_Z0MIN (1 << 5) +# define R600_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6) +# define R600_SC_HYPERZ_HZ_Z0MAX (1 << 6) + +#define R600_SC_EDGERULE 0x43a8 /* BEGIN: Scissors and cliprects */ @@ -1290,50 +1290,50 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * For some reason, the top-left corner of the framebuffer is at (1440, 1440) * for the purpose of clipping and scissors. */ -#define R300_SC_CLIPRECT_TL_0 0x43B0 -#define R300_SC_CLIPRECT_BR_0 0x43B4 -#define R300_SC_CLIPRECT_TL_1 0x43B8 -#define R300_SC_CLIPRECT_BR_1 0x43BC -#define R300_SC_CLIPRECT_TL_2 0x43C0 -#define R300_SC_CLIPRECT_BR_2 0x43C4 -#define R300_SC_CLIPRECT_TL_3 0x43C8 -#define R300_SC_CLIPRECT_BR_3 0x43CC -# define R300_CLIPRECT_OFFSET 1440 -# define R300_CLIPRECT_MASK 0x1FFF -# define R300_CLIPRECT_X_SHIFT 0 -# define R300_CLIPRECT_X_MASK (0x1FFF << 0) -# define R300_CLIPRECT_Y_SHIFT 13 -# define R300_CLIPRECT_Y_MASK (0x1FFF << 13) -#define R300_SC_CLIP_RULE 0x43D0 -# define R300_CLIP_OUT (1 << 0) -# define R300_CLIP_0 (1 << 1) -# define R300_CLIP_1 (1 << 2) -# define R300_CLIP_10 (1 << 3) -# define R300_CLIP_2 (1 << 4) -# define R300_CLIP_20 (1 << 5) -# define R300_CLIP_21 (1 << 6) -# define R300_CLIP_210 (1 << 7) -# define R300_CLIP_3 (1 << 8) -# define R300_CLIP_30 (1 << 9) -# define R300_CLIP_31 (1 << 10) -# define R300_CLIP_310 (1 << 11) -# define R300_CLIP_32 (1 << 12) -# define R300_CLIP_320 (1 << 13) -# define R300_CLIP_321 (1 << 14) -# define R300_CLIP_3210 (1 << 15) +#define R600_SC_CLIPRECT_TL_0 0x43B0 +#define R600_SC_CLIPRECT_BR_0 0x43B4 +#define R600_SC_CLIPRECT_TL_1 0x43B8 +#define R600_SC_CLIPRECT_BR_1 0x43BC +#define R600_SC_CLIPRECT_TL_2 0x43C0 +#define R600_SC_CLIPRECT_BR_2 0x43C4 +#define R600_SC_CLIPRECT_TL_3 0x43C8 +#define R600_SC_CLIPRECT_BR_3 0x43CC +# define R600_CLIPRECT_OFFSET 1440 +# define R600_CLIPRECT_MASK 0x1FFF +# define R600_CLIPRECT_X_SHIFT 0 +# define R600_CLIPRECT_X_MASK (0x1FFF << 0) +# define R600_CLIPRECT_Y_SHIFT 13 +# define R600_CLIPRECT_Y_MASK (0x1FFF << 13) +#define R600_SC_CLIP_RULE 0x43D0 +# define R600_CLIP_OUT (1 << 0) +# define R600_CLIP_0 (1 << 1) +# define R600_CLIP_1 (1 << 2) +# define R600_CLIP_10 (1 << 3) +# define R600_CLIP_2 (1 << 4) +# define R600_CLIP_20 (1 << 5) +# define R600_CLIP_21 (1 << 6) +# define R600_CLIP_210 (1 << 7) +# define R600_CLIP_3 (1 << 8) +# define R600_CLIP_30 (1 << 9) +# define R600_CLIP_31 (1 << 10) +# define R600_CLIP_310 (1 << 11) +# define R600_CLIP_32 (1 << 12) +# define R600_CLIP_320 (1 << 13) +# define R600_CLIP_321 (1 << 14) +# define R600_CLIP_3210 (1 << 15) /* gap */ -#define R300_SC_SCISSORS_TL 0x43E0 -#define R300_SC_SCISSORS_BR 0x43E4 -# define R300_SCISSORS_OFFSET 1440 -# define R300_SCISSORS_X_SHIFT 0 -# define R300_SCISSORS_X_MASK (0x1FFF << 0) -# define R300_SCISSORS_Y_SHIFT 13 -# define R300_SCISSORS_Y_MASK (0x1FFF << 13) +#define R600_SC_SCISSORS_TL 0x43E0 +#define R600_SC_SCISSORS_BR 0x43E4 +# define R600_SCISSORS_OFFSET 1440 +# define R600_SCISSORS_X_SHIFT 0 +# define R600_SCISSORS_X_MASK (0x1FFF << 0) +# define R600_SCISSORS_Y_SHIFT 13 +# define R600_SCISSORS_Y_MASK (0x1FFF << 13) /* Screen door sample mask */ -#define R300_SC_SCREENDOOR 0x43e8 +#define R600_SC_SCREENDOOR 0x43e8 /* END: Scissors and cliprects */ @@ -1344,183 +1344,183 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * unit. This means that e.g. the offset for texture image unit N is found in * register TX_OFFSET_0 + (4*N) */ -#define R300_TX_FILTER0_0 0x4400 -#define R300_TX_FILTER0_1 0x4404 -#define R300_TX_FILTER0_2 0x4408 -#define R300_TX_FILTER0_3 0x440c -#define R300_TX_FILTER0_4 0x4410 -#define R300_TX_FILTER0_5 0x4414 -#define R300_TX_FILTER0_6 0x4418 -#define R300_TX_FILTER0_7 0x441c -#define R300_TX_FILTER0_8 0x4420 -#define R300_TX_FILTER0_9 0x4424 -#define R300_TX_FILTER0_10 0x4428 -#define R300_TX_FILTER0_11 0x442c -#define R300_TX_FILTER0_12 0x4430 -#define R300_TX_FILTER0_13 0x4434 -#define R300_TX_FILTER0_14 0x4438 -#define R300_TX_FILTER0_15 0x443c -# define R300_TX_REPEAT 0 -# define R300_TX_MIRRORED 1 -# define R300_TX_CLAMP_TO_EDGE 2 -# define R300_TX_MIRROR_ONCE_TO_EDGE 3 -# define R300_TX_CLAMP 4 -# define R300_TX_MIRROR_ONCE 5 -# define R300_TX_CLAMP_TO_BORDER 6 -# define R300_TX_MIRROR_ONCE_TO_BORDER 7 -# define R300_TX_WRAP_S_SHIFT 0 -# define R300_TX_WRAP_S_MASK (7 << 0) -# define R300_TX_WRAP_T_SHIFT 3 -# define R300_TX_WRAP_T_MASK (7 << 3) -# define R300_TX_WRAP_R_SHIFT 6 -# define R300_TX_WRAP_R_MASK (7 << 6) -# define R300_TX_MAG_FILTER_4 (0 << 9) -# define R300_TX_MAG_FILTER_NEAREST (1 << 9) -# define R300_TX_MAG_FILTER_LINEAR (2 << 9) -# define R300_TX_MAG_FILTER_ANISO (3 << 9) -# define R300_TX_MAG_FILTER_MASK (3 << 9) -# define R300_TX_MIN_FILTER_NEAREST (1 << 11) -# define R300_TX_MIN_FILTER_LINEAR (2 << 11) -# define R300_TX_MIN_FILTER_ANISO (3 << 11) -# define R300_TX_MIN_FILTER_MASK (3 << 11) -# define R300_TX_MIN_FILTER_MIP_NONE (0 << 13) -# define R300_TX_MIN_FILTER_MIP_NEAREST (1 << 13) -# define R300_TX_MIN_FILTER_MIP_LINEAR (2 << 13) -# define R300_TX_MIN_FILTER_MIP_MASK (3 << 13) -# define R300_TX_MAX_ANISO_1_TO_1 (0 << 21) -# define R300_TX_MAX_ANISO_2_TO_1 (1 << 21) -# define R300_TX_MAX_ANISO_4_TO_1 (2 << 21) -# define R300_TX_MAX_ANISO_8_TO_1 (3 << 21) -# define R300_TX_MAX_ANISO_16_TO_1 (4 << 21) -# define R300_TX_MAX_ANISO_MASK (7 << 21) - -#define R300_TX_FILTER1_0 0x4440 -# define R300_CHROMA_KEY_MODE_DISABLE 0 -# define R300_CHROMA_KEY_FORCE 1 -# define R300_CHROMA_KEY_BLEND 2 -# define R300_MC_ROUND_NORMAL (0<<2) -# define R300_MC_ROUND_MPEG4 (1<<2) -# define R300_LOD_BIAS_SHIFT 3 -# define R300_LOD_BIAS_MASK 0x1ff8 -# define R300_EDGE_ANISO_EDGE_DIAG (0<<13) -# define R300_EDGE_ANISO_EDGE_ONLY (1<<13) -# define R300_MC_COORD_TRUNCATE_DISABLE (0<<14) -# define R300_MC_COORD_TRUNCATE_MPEG (1<<14) -# define R300_TX_TRI_PERF_0_8 (0<<15) -# define R300_TX_TRI_PERF_1_8 (1<<15) -# define R300_TX_TRI_PERF_1_4 (2<<15) -# define R300_TX_TRI_PERF_3_8 (3<<15) -# define R300_ANISO_THRESHOLD_MASK (7<<17) +#define R600_TX_FILTER0_0 0x4400 +#define R600_TX_FILTER0_1 0x4404 +#define R600_TX_FILTER0_2 0x4408 +#define R600_TX_FILTER0_3 0x440c +#define R600_TX_FILTER0_4 0x4410 +#define R600_TX_FILTER0_5 0x4414 +#define R600_TX_FILTER0_6 0x4418 +#define R600_TX_FILTER0_7 0x441c +#define R600_TX_FILTER0_8 0x4420 +#define R600_TX_FILTER0_9 0x4424 +#define R600_TX_FILTER0_10 0x4428 +#define R600_TX_FILTER0_11 0x442c +#define R600_TX_FILTER0_12 0x4430 +#define R600_TX_FILTER0_13 0x4434 +#define R600_TX_FILTER0_14 0x4438 +#define R600_TX_FILTER0_15 0x443c +# define R600_TX_REPEAT 0 +# define R600_TX_MIRRORED 1 +# define R600_TX_CLAMP_TO_EDGE 2 +# define R600_TX_MIRROR_ONCE_TO_EDGE 3 +# define R600_TX_CLAMP 4 +# define R600_TX_MIRROR_ONCE 5 +# define R600_TX_CLAMP_TO_BORDER 6 +# define R600_TX_MIRROR_ONCE_TO_BORDER 7 +# define R600_TX_WRAP_S_SHIFT 0 +# define R600_TX_WRAP_S_MASK (7 << 0) +# define R600_TX_WRAP_T_SHIFT 3 +# define R600_TX_WRAP_T_MASK (7 << 3) +# define R600_TX_WRAP_R_SHIFT 6 +# define R600_TX_WRAP_R_MASK (7 << 6) +# define R600_TX_MAG_FILTER_4 (0 << 9) +# define R600_TX_MAG_FILTER_NEAREST (1 << 9) +# define R600_TX_MAG_FILTER_LINEAR (2 << 9) +# define R600_TX_MAG_FILTER_ANISO (3 << 9) +# define R600_TX_MAG_FILTER_MASK (3 << 9) +# define R600_TX_MIN_FILTER_NEAREST (1 << 11) +# define R600_TX_MIN_FILTER_LINEAR (2 << 11) +# define R600_TX_MIN_FILTER_ANISO (3 << 11) +# define R600_TX_MIN_FILTER_MASK (3 << 11) +# define R600_TX_MIN_FILTER_MIP_NONE (0 << 13) +# define R600_TX_MIN_FILTER_MIP_NEAREST (1 << 13) +# define R600_TX_MIN_FILTER_MIP_LINEAR (2 << 13) +# define R600_TX_MIN_FILTER_MIP_MASK (3 << 13) +# define R600_TX_MAX_ANISO_1_TO_1 (0 << 21) +# define R600_TX_MAX_ANISO_2_TO_1 (1 << 21) +# define R600_TX_MAX_ANISO_4_TO_1 (2 << 21) +# define R600_TX_MAX_ANISO_8_TO_1 (3 << 21) +# define R600_TX_MAX_ANISO_16_TO_1 (4 << 21) +# define R600_TX_MAX_ANISO_MASK (7 << 21) + +#define R600_TX_FILTER1_0 0x4440 +# define R600_CHROMA_KEY_MODE_DISABLE 0 +# define R600_CHROMA_KEY_FORCE 1 +# define R600_CHROMA_KEY_BLEND 2 +# define R600_MC_ROUND_NORMAL (0<<2) +# define R600_MC_ROUND_MPEG4 (1<<2) +# define R600_LOD_BIAS_SHIFT 3 +# define R600_LOD_BIAS_MASK 0x1ff8 +# define R600_EDGE_ANISO_EDGE_DIAG (0<<13) +# define R600_EDGE_ANISO_EDGE_ONLY (1<<13) +# define R600_MC_COORD_TRUNCATE_DISABLE (0<<14) +# define R600_MC_COORD_TRUNCATE_MPEG (1<<14) +# define R600_TX_TRI_PERF_0_8 (0<<15) +# define R600_TX_TRI_PERF_1_8 (1<<15) +# define R600_TX_TRI_PERF_1_4 (2<<15) +# define R600_TX_TRI_PERF_3_8 (3<<15) +# define R600_ANISO_THRESHOLD_MASK (7<<17) # define R500_MACRO_SWITCH (1<<22) # define R500_BORDER_FIX (1<<31) -#define R300_TX_SIZE_0 0x4480 -# define R300_TX_WIDTHMASK_SHIFT 0 -# define R300_TX_WIDTHMASK_MASK (2047 << 0) -# define R300_TX_HEIGHTMASK_SHIFT 11 -# define R300_TX_HEIGHTMASK_MASK (2047 << 11) -# define R300_TX_DEPTHMASK_SHIFT 22 -# define R300_TX_DEPTHMASK_MASK (0xf << 22) -# define R300_TX_MAX_MIP_LEVEL_SHIFT 26 -# define R300_TX_MAX_MIP_LEVEL_MASK (0xf << 26) -# define R300_TX_SIZE_PROJECTED (1<<30) -# define R300_TX_SIZE_TXPITCH_EN (1<<31) -#define R300_TX_FORMAT_0 0x44C0 +#define R600_TX_SIZE_0 0x4480 +# define R600_TX_WIDTHMASK_SHIFT 0 +# define R600_TX_WIDTHMASK_MASK (2047 << 0) +# define R600_TX_HEIGHTMASK_SHIFT 11 +# define R600_TX_HEIGHTMASK_MASK (2047 << 11) +# define R600_TX_DEPTHMASK_SHIFT 22 +# define R600_TX_DEPTHMASK_MASK (0xf << 22) +# define R600_TX_MAX_MIP_LEVEL_SHIFT 26 +# define R600_TX_MAX_MIP_LEVEL_MASK (0xf << 26) +# define R600_TX_SIZE_PROJECTED (1<<30) +# define R600_TX_SIZE_TXPITCH_EN (1<<31) +#define R600_TX_FORMAT_0 0x44C0 /* The interpretation of the format word by Wladimir van der Laan */ /* The X, Y, Z and W refer to the layout of the components. They are given meanings as R, G, B and Alpha by the swizzle specification */ -# define R300_TX_FORMAT_X8 0x0 +# define R600_TX_FORMAT_X8 0x0 # define R500_TX_FORMAT_X1 0x0 // bit set in format 2 -# define R300_TX_FORMAT_X16 0x1 +# define R600_TX_FORMAT_X16 0x1 # define R500_TX_FORMAT_X1_REV 0x0 // bit set in format 2 -# define R300_TX_FORMAT_Y4X4 0x2 -# define R300_TX_FORMAT_Y8X8 0x3 -# define R300_TX_FORMAT_Y16X16 0x4 -# define R300_TX_FORMAT_Z3Y3X2 0x5 -# define R300_TX_FORMAT_Z5Y6X5 0x6 -# define R300_TX_FORMAT_Z6Y5X5 0x7 -# define R300_TX_FORMAT_Z11Y11X10 0x8 -# define R300_TX_FORMAT_Z10Y11X11 0x9 -# define R300_TX_FORMAT_W4Z4Y4X4 0xA -# define R300_TX_FORMAT_W1Z5Y5X5 0xB -# define R300_TX_FORMAT_W8Z8Y8X8 0xC -# define R300_TX_FORMAT_W2Z10Y10X10 0xD -# define R300_TX_FORMAT_W16Z16Y16X16 0xE -# define R300_TX_FORMAT_DXT1 0xF -# define R300_TX_FORMAT_DXT3 0x10 -# define R300_TX_FORMAT_DXT5 0x11 -# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ -# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ -# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ -# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ +# define R600_TX_FORMAT_Y4X4 0x2 +# define R600_TX_FORMAT_Y8X8 0x3 +# define R600_TX_FORMAT_Y16X16 0x4 +# define R600_TX_FORMAT_Z3Y3X2 0x5 +# define R600_TX_FORMAT_Z5Y6X5 0x6 +# define R600_TX_FORMAT_Z6Y5X5 0x7 +# define R600_TX_FORMAT_Z11Y11X10 0x8 +# define R600_TX_FORMAT_Z10Y11X11 0x9 +# define R600_TX_FORMAT_W4Z4Y4X4 0xA +# define R600_TX_FORMAT_W1Z5Y5X5 0xB +# define R600_TX_FORMAT_W8Z8Y8X8 0xC +# define R600_TX_FORMAT_W2Z10Y10X10 0xD +# define R600_TX_FORMAT_W16Z16Y16X16 0xE +# define R600_TX_FORMAT_DXT1 0xF +# define R600_TX_FORMAT_DXT3 0x10 +# define R600_TX_FORMAT_DXT5 0x11 +# define R600_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ +# define R600_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ +# define R600_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ +# define R600_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ /* These two values are wrong, but they're the only values that - * produce any even vaguely correct results. Can r300 only do 16-bit + * produce any even vaguely correct results. Can r600 only do 16-bit * depth textures? */ -# define R300_TX_FORMAT_X24_Y8 0x1e -# define R300_TX_FORMAT_X32 0x1e +# define R600_TX_FORMAT_X24_Y8 0x1e +# define R600_TX_FORMAT_X32 0x1e /* 0x16 - some 16 bit green format.. ?? */ -# define R300_TX_FORMAT_3D (1 << 25) -# define R300_TX_FORMAT_CUBIC_MAP (2 << 25) +# define R600_TX_FORMAT_3D (1 << 25) +# define R600_TX_FORMAT_CUBIC_MAP (2 << 25) /* gap */ /* Floating point formats */ /* Note - hardware supports both 16 and 32 bit floating point */ -# define R300_TX_FORMAT_FL_I16 0x18 -# define R300_TX_FORMAT_FL_I16A16 0x19 -# define R300_TX_FORMAT_FL_R16G16B16A16 0x1A -# define R300_TX_FORMAT_FL_I32 0x1B -# define R300_TX_FORMAT_FL_I32A32 0x1C -# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D +# define R600_TX_FORMAT_FL_I16 0x18 +# define R600_TX_FORMAT_FL_I16A16 0x19 +# define R600_TX_FORMAT_FL_R16G16B16A16 0x1A +# define R600_TX_FORMAT_FL_I32 0x1B +# define R600_TX_FORMAT_FL_I32A32 0x1C +# define R600_TX_FORMAT_FL_R32G32B32A32 0x1D /* alpha modes, convenience mostly */ /* if you have alpha, pick constant appropriate to the number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ -# define R300_TX_FORMAT_ALPHA_1CH 0x000 -# define R300_TX_FORMAT_ALPHA_2CH 0x200 -# define R300_TX_FORMAT_ALPHA_4CH 0x600 -# define R300_TX_FORMAT_ALPHA_NONE 0xA00 +# define R600_TX_FORMAT_ALPHA_1CH 0x000 +# define R600_TX_FORMAT_ALPHA_2CH 0x200 +# define R600_TX_FORMAT_ALPHA_4CH 0x600 +# define R600_TX_FORMAT_ALPHA_NONE 0xA00 /* Swizzling */ /* constants */ -# define R300_TX_FORMAT_X 0 -# define R300_TX_FORMAT_Y 1 -# define R300_TX_FORMAT_Z 2 -# define R300_TX_FORMAT_W 3 -# define R300_TX_FORMAT_ZERO 4 -# define R300_TX_FORMAT_ONE 5 +# define R600_TX_FORMAT_X 0 +# define R600_TX_FORMAT_Y 1 +# define R600_TX_FORMAT_Z 2 +# define R600_TX_FORMAT_W 3 +# define R600_TX_FORMAT_ZERO 4 +# define R600_TX_FORMAT_ONE 5 /* 2.0*Z, everything above 1.0 is set to 0.0 */ -# define R300_TX_FORMAT_CUT_Z 6 +# define R600_TX_FORMAT_CUT_Z 6 /* 2.0*W, everything above 1.0 is set to 0.0 */ -# define R300_TX_FORMAT_CUT_W 7 +# define R600_TX_FORMAT_CUT_W 7 -# define R300_TX_FORMAT_B_SHIFT 18 -# define R300_TX_FORMAT_G_SHIFT 15 -# define R300_TX_FORMAT_R_SHIFT 12 -# define R300_TX_FORMAT_A_SHIFT 9 +# define R600_TX_FORMAT_B_SHIFT 18 +# define R600_TX_FORMAT_G_SHIFT 15 +# define R600_TX_FORMAT_R_SHIFT 12 +# define R600_TX_FORMAT_A_SHIFT 9 /* Convenience macro to take care of layout and swizzling */ -# define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \ - ((R300_TX_FORMAT_##B)<radeon, &rmesa->radeon.tcl.elt_dma_bo, @@ -183,31 +183,31 @@ static void r300EmitElts(GLcontext * ctx, void *elts, unsigned long n_elts) radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo); } -static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) +static void r600FireEB(r600ContextPtr rmesa, int vertex_count, int type) { BATCH_LOCALS(&rmesa->radeon); if (vertex_count > 0) { BEGIN_BATCH(10); - OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_INDX_2, 0); - OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | + OUT_BATCH_PACKET3(R600_PACKET3_3D_DRAW_INDX_2, 0); + OUT_BATCH(R600_VAP_VF_CNTL__PRIM_WALK_INDICES | ((vertex_count + 0) << 16) | type | - R300_VAP_VF_CNTL__INDEX_SIZE_32bit); + R600_VAP_VF_CNTL__INDEX_SIZE_32bit); if (!rmesa->radeon.radeonScreen->kernel_mm) { - OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); - OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) | - (R300_VAP_PORT_IDX0 >> 2)); + OUT_BATCH_PACKET3(R600_PACKET3_INDX_BUFFER, 2); + OUT_BATCH(R600_INDX_BUFFER_ONE_REG_WR | (0 << R600_INDX_BUFFER_SKIP_SHIFT) | + (R600_VAP_PORT_IDX0 >> 2)); OUT_BATCH_RELOC(rmesa->radeon.tcl.elt_dma_offset, rmesa->radeon.tcl.elt_dma_bo, rmesa->radeon.tcl.elt_dma_offset, RADEON_GEM_DOMAIN_GTT, 0, 0); OUT_BATCH(vertex_count); } else { - OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); - OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) | - (R300_VAP_PORT_IDX0 >> 2)); + OUT_BATCH_PACKET3(R600_PACKET3_INDX_BUFFER, 2); + OUT_BATCH(R600_INDX_BUFFER_ONE_REG_WR | (0 << R600_INDX_BUFFER_SKIP_SHIFT) | + (R600_VAP_PORT_IDX0 >> 2)); OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset); OUT_BATCH(vertex_count); radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, @@ -218,7 +218,7 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) } } -static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) +static void r600EmitAOS(r600ContextPtr rmesa, GLuint nr, GLuint offset) { BATCH_LOCALS(&rmesa->radeon); uint32_t voffset; @@ -232,7 +232,7 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) if (!rmesa->radeon.radeonScreen->kernel_mm) { BEGIN_BATCH(sz+2+(nr * 2)); - OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1); + OUT_BATCH_PACKET3(R600_PACKET3_3D_LOAD_VBPNTR, sz - 1); OUT_BATCH(nr); for (i = 0; i + 1 < nr; i += 2) { @@ -272,7 +272,7 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) } else { BEGIN_BATCH(sz+2+(nr * 2)); - OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1); + OUT_BATCH_PACKET3(R600_PACKET3_3D_LOAD_VBPNTR, sz - 1); OUT_BATCH(nr); for (i = 0; i + 1 < nr; i += 2) { @@ -323,25 +323,25 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) } -static void r300FireAOS(r300ContextPtr rmesa, int vertex_count, int type) +static void r600FireAOS(r600ContextPtr rmesa, int vertex_count, int type) { BATCH_LOCALS(&rmesa->radeon); BEGIN_BATCH(3); - OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0); - OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (vertex_count << 16) | type); + OUT_BATCH_PACKET3(R600_PACKET3_3D_DRAW_VBUF_2, 0); + OUT_BATCH(R600_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (vertex_count << 16) | type); END_BATCH(); } -static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx, +static void r600RunRenderPrimitive(r600ContextPtr rmesa, GLcontext * ctx, int start, int end, int prim) { int type, num_verts; TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; - type = r300PrimitiveType(rmesa, prim); - num_verts = r300NumVerts(rmesa, end - start, prim); + type = r600PrimitiveType(rmesa, prim); + num_verts = r600NumVerts(rmesa, end - start, prim); if (type < 0 || num_verts <= 0) return; @@ -369,20 +369,20 @@ static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx, * allocating the index array might actually evict the vertex * arrays. *sigh* */ - r300EmitElts(ctx, vb->Elts, num_verts); - r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start); - r300FireEB(rmesa, num_verts, type); + r600EmitElts(ctx, vb->Elts, num_verts); + r600EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start); + r600FireEB(rmesa, num_verts, type); } else { - r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start); - r300FireAOS(rmesa, num_verts, type); + r600EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start); + r600FireAOS(rmesa, num_verts, type); } COMMIT_BATCH(); } -static GLboolean r300RunRender(GLcontext * ctx, +static GLboolean r600RunRender(GLcontext * ctx, struct tnl_pipeline_stage *stage) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); int i; TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; @@ -390,23 +390,23 @@ static GLboolean r300RunRender(GLcontext * ctx, if (RADEON_DEBUG & DEBUG_PRIMS) fprintf(stderr, "%s\n", __FUNCTION__); - r300UpdateShaders(rmesa); - if (r300EmitArrays(ctx)) + r600UpdateShaders(rmesa); + if (r600EmitArrays(ctx)) return GL_TRUE; - r300UpdateShaderStates(rmesa); + r600UpdateShaderStates(rmesa); - r300EmitCacheFlush(rmesa); + r600EmitCacheFlush(rmesa); radeonEmitState(&rmesa->radeon); for (i = 0; i < vb->PrimitiveCount; i++) { GLuint prim = _tnl_translate_prim(&vb->Primitive[i]); GLuint start = vb->Primitive[i].start; GLuint end = vb->Primitive[i].start + vb->Primitive[i].count; - r300RunRenderPrimitive(rmesa, ctx, start, end, prim); + r600RunRenderPrimitive(rmesa, ctx, start, end, prim); } - r300EmitCacheFlush(rmesa); + r600EmitCacheFlush(rmesa); radeonReleaseArrays(ctx, ~0); @@ -419,33 +419,33 @@ static GLboolean r300RunRender(GLcontext * ctx, if (1 || RADEON_DEBUG & DEBUG_FALLBACKS) \ WARN_ONCE("Software fallback:%s\n", \ #expr); \ - return R300_FALLBACK_RAST; \ + return R600_FALLBACK_RAST; \ } \ } while(0) -static int r300Fallback(GLcontext * ctx) +static int r600Fallback(GLcontext * ctx) { - r300ContextPtr r300 = R300_CONTEXT(ctx); + r600ContextPtr r600 = R600_CONTEXT(ctx); const unsigned back = ctx->Stencil._BackFace; - FALLBACK_IF(r300->radeon.Fallback); + FALLBACK_IF(r600->radeon.Fallback); /* Do we need to use new-style shaders? * Also is there a better way to do this? */ - if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { + if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { struct r500_fragment_program *fp = (struct r500_fragment_program *) (char *)ctx->FragmentProgram._Current; if (fp) { if (!fp->translated) { - r500TranslateFragmentShader(r300, fp); + r500TranslateFragmentShader(r600, fp); FALLBACK_IF(!fp->translated); } } } else { - struct r300_fragment_program *fp = (struct r300_fragment_program *) + struct r600_fragment_program *fp = (struct r600_fragment_program *) (char *)ctx->FragmentProgram._Current; if (fp) { if (!fp->translated) { - r300TranslateFragmentShader(r300, fp); + r600TranslateFragmentShader(r600, fp); FALLBACK_IF(!fp->translated); } } @@ -465,7 +465,7 @@ static int r300Fallback(GLcontext * ctx) if (ctx->Extensions.NV_point_sprite || ctx->Extensions.ARB_point_sprite) FALLBACK_IF(ctx->Point.PointSprite); - if (!r300->disable_lowimpact_fallback) { + if (!r600->disable_lowimpact_fallback) { FALLBACK_IF(ctx->Polygon.StippleFlag); FALLBACK_IF(ctx->Multisample._Enabled); FALLBACK_IF(ctx->Line.StippleFlag); @@ -473,34 +473,34 @@ static int r300Fallback(GLcontext * ctx) FALLBACK_IF(ctx->Point.SmoothFlag); } - return R300_FALLBACK_NONE; + return R600_FALLBACK_NONE; } -static GLboolean r300RunNonTCLRender(GLcontext * ctx, +static GLboolean r600RunNonTCLRender(GLcontext * ctx, struct tnl_pipeline_stage *stage) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); if (RADEON_DEBUG & DEBUG_PRIMS) fprintf(stderr, "%s\n", __FUNCTION__); - if (r300Fallback(ctx) >= R300_FALLBACK_RAST) + if (r600Fallback(ctx) >= R600_FALLBACK_RAST) return GL_TRUE; if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) return GL_TRUE; - if (!r300ValidateBuffers(ctx)) + if (!r600ValidateBuffers(ctx)) return GL_TRUE; - return r300RunRender(ctx, stage); + return r600RunRender(ctx, stage); } -static GLboolean r300RunTCLRender(GLcontext * ctx, +static GLboolean r600RunTCLRender(GLcontext * ctx, struct tnl_pipeline_stage *stage) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct r300_vertex_program *vp; + r600ContextPtr rmesa = R600_CONTEXT(ctx); + struct r600_vertex_program *vp; hw_tcl_on = future_hw_tcl_on; @@ -510,39 +510,39 @@ static GLboolean r300RunTCLRender(GLcontext * ctx, if (hw_tcl_on == GL_FALSE) return GL_TRUE; - if (r300Fallback(ctx) >= R300_FALLBACK_TCL) { + if (r600Fallback(ctx) >= R600_FALLBACK_TCL) { hw_tcl_on = GL_FALSE; return GL_TRUE; } - if (!r300ValidateBuffers(ctx)) + if (!r600ValidateBuffers(ctx)) return GL_TRUE; - r300UpdateShaders(rmesa); + r600UpdateShaders(rmesa); - vp = (struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx); + vp = (struct r600_vertex_program *)CURRENT_VERTEX_SHADER(ctx); if (vp->native == GL_FALSE) { hw_tcl_on = GL_FALSE; return GL_TRUE; } - return r300RunRender(ctx, stage); + return r600RunRender(ctx, stage); } -const struct tnl_pipeline_stage _r300_render_stage = { - "r300 Hardware Rasterization", +const struct tnl_pipeline_stage _r600_render_stage = { + "r600 Hardware Rasterization", NULL, NULL, NULL, NULL, - r300RunNonTCLRender + r600RunNonTCLRender }; -const struct tnl_pipeline_stage _r300_tcl_stage = { - "r300 Hardware Transform, Clipping and Lighting", +const struct tnl_pipeline_stage _r600_tcl_stage = { + "r600 Hardware Transform, Clipping and Lighting", NULL, NULL, NULL, NULL, - r300RunTCLRender + r600RunTCLRender }; diff --git a/src/mesa/drivers/dri/r600/r600_shader.c b/src/mesa/drivers/dri/r600/r600_shader.c index 63d4b45b9f..ebf4a72191 100644 --- a/src/mesa/drivers/dri/r600/r600_shader.c +++ b/src/mesa/drivers/dri/r600/r600_shader.c @@ -6,18 +6,18 @@ #include "r600_context.h" #include "r600_fragprog.h" -static struct gl_program *r300NewProgram(GLcontext * ctx, GLenum target, +static struct gl_program *r600NewProgram(GLcontext * ctx, GLenum target, GLuint id) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct r300_vertex_program_cont *vp; - struct r300_fragment_program *r300_fp; + r600ContextPtr rmesa = R600_CONTEXT(ctx); + struct r600_vertex_program_cont *vp; + struct r600_fragment_program *r600_fp; struct r500_fragment_program *r500_fp; switch (target) { case GL_VERTEX_STATE_PROGRAM_NV: case GL_VERTEX_PROGRAM_ARB: - vp = CALLOC_STRUCT(r300_vertex_program_cont); + vp = CALLOC_STRUCT(r600_vertex_program_cont); return _mesa_init_vertex_program(ctx, &vp->mesa_program, target, id); case GL_FRAGMENT_PROGRAM_ARB: @@ -27,8 +27,8 @@ static struct gl_program *r300NewProgram(GLcontext * ctx, GLenum target, return _mesa_init_fragment_program(ctx, &r500_fp->mesa_program, target, id); } else { - r300_fp = CALLOC_STRUCT(r300_fragment_program); - return _mesa_init_fragment_program(ctx, &r300_fp->mesa_program, + r600_fp = CALLOC_STRUCT(r600_fragment_program); + return _mesa_init_fragment_program(ctx, &r600_fp->mesa_program, target, id); } @@ -38,28 +38,28 @@ static struct gl_program *r300NewProgram(GLcontext * ctx, GLenum target, return _mesa_init_fragment_program(ctx, &r500_fp->mesa_program, target, id); } else { - r300_fp = CALLOC_STRUCT(r300_fragment_program); - return _mesa_init_fragment_program(ctx, &r300_fp->mesa_program, + r600_fp = CALLOC_STRUCT(r600_fragment_program); + return _mesa_init_fragment_program(ctx, &r600_fp->mesa_program, target, id); } default: - _mesa_problem(ctx, "Bad target in r300NewProgram"); + _mesa_problem(ctx, "Bad target in r600NewProgram"); } return NULL; } -static void r300DeleteProgram(GLcontext * ctx, struct gl_program *prog) +static void r600DeleteProgram(GLcontext * ctx, struct gl_program *prog) { _mesa_delete_program(ctx, prog); } static void -r300ProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog) +r600ProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); - struct r300_vertex_program_cont *vp = (void *)prog; - struct r300_fragment_program *r300_fp = (struct r300_fragment_program *)prog; + r600ContextPtr rmesa = R600_CONTEXT(ctx); + struct r600_vertex_program_cont *vp = (void *)prog; + struct r600_fragment_program *r600_fp = (struct r600_fragment_program *)prog; struct r500_fragment_program *r500_fp = (struct r500_fragment_program *)prog; switch (target) { @@ -70,7 +70,7 @@ r300ProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog) if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) r500_fp->translated = GL_FALSE; else - r300_fp->translated = GL_FALSE; + r600_fp->translated = GL_FALSE; break; } @@ -79,15 +79,15 @@ r300ProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog) } static GLboolean -r300IsProgramNative(GLcontext * ctx, GLenum target, struct gl_program *prog) +r600IsProgramNative(GLcontext * ctx, GLenum target, struct gl_program *prog) { return GL_TRUE; } -void r300InitShaderFuncs(struct dd_function_table *functions) +void r600InitShaderFuncs(struct dd_function_table *functions) { - functions->NewProgram = r300NewProgram; - functions->DeleteProgram = r300DeleteProgram; - functions->ProgramStringNotify = r300ProgramStringNotify; - functions->IsProgramNative = r300IsProgramNative; + functions->NewProgram = r600NewProgram; + functions->DeleteProgram = r600DeleteProgram; + functions->ProgramStringNotify = r600ProgramStringNotify; + functions->IsProgramNative = r600IsProgramNative; } diff --git a/src/mesa/drivers/dri/r600/r600_state.c b/src/mesa/drivers/dri/r600/r600_state.c index 8cb9c7cb6f..19588d4b1d 100644 --- a/src/mesa/drivers/dri/r600/r600_state.c +++ b/src/mesa/drivers/dri/r600/r600_state.c @@ -67,11 +67,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. extern int future_hw_tcl_on; extern void _tnl_UpdateFixedFunctionProgram(GLcontext * ctx); -static void r300BlendColor(GLcontext * ctx, const GLfloat cf[4]) +static void r600BlendColor(GLcontext * ctx, const GLfloat cf[4]) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); - R300_STATECHANGE(rmesa, blend_color); + R600_STATECHANGE(rmesa, blend_color); if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { GLuint r = IROUND(cf[0]*1023.0f); @@ -111,54 +111,54 @@ static int blend_factor(GLenum factor, GLboolean is_src) { switch (factor) { case GL_ZERO: - return R300_BLEND_GL_ZERO; + return R600_BLEND_GL_ZERO; break; case GL_ONE: - return R300_BLEND_GL_ONE; + return R600_BLEND_GL_ONE; break; case GL_DST_COLOR: - return R300_BLEND_GL_DST_COLOR; + return R600_BLEND_GL_DST_COLOR; break; case GL_ONE_MINUS_DST_COLOR: - return R300_BLEND_GL_ONE_MINUS_DST_COLOR; + return R600_BLEND_GL_ONE_MINUS_DST_COLOR; break; case GL_SRC_COLOR: - return R300_BLEND_GL_SRC_COLOR; + return R600_BLEND_GL_SRC_COLOR; break; case GL_ONE_MINUS_SRC_COLOR: - return R300_BLEND_GL_ONE_MINUS_SRC_COLOR; + return R600_BLEND_GL_ONE_MINUS_SRC_COLOR; break; case GL_SRC_ALPHA: - return R300_BLEND_GL_SRC_ALPHA; + return R600_BLEND_GL_SRC_ALPHA; break; case GL_ONE_MINUS_SRC_ALPHA: - return R300_BLEND_GL_ONE_MINUS_SRC_ALPHA; + return R600_BLEND_GL_ONE_MINUS_SRC_ALPHA; break; case GL_DST_ALPHA: - return R300_BLEND_GL_DST_ALPHA; + return R600_BLEND_GL_DST_ALPHA; break; case GL_ONE_MINUS_DST_ALPHA: - return R300_BLEND_GL_ONE_MINUS_DST_ALPHA; + return R600_BLEND_GL_ONE_MINUS_DST_ALPHA; break; case GL_SRC_ALPHA_SATURATE: - return (is_src) ? R300_BLEND_GL_SRC_ALPHA_SATURATE : - R300_BLEND_GL_ZERO; + return (is_src) ? R600_BLEND_GL_SRC_ALPHA_SATURATE : + R600_BLEND_GL_ZERO; break; case GL_CONSTANT_COLOR: - return R300_BLEND_GL_CONST_COLOR; + return R600_BLEND_GL_CONST_COLOR; break; case GL_ONE_MINUS_CONSTANT_COLOR: - return R300_BLEND_GL_ONE_MINUS_CONST_COLOR; + return R600_BLEND_GL_ONE_MINUS_CONST_COLOR; break; case GL_CONSTANT_ALPHA: - return R300_BLEND_GL_CONST_ALPHA; + return R600_BLEND_GL_CONST_ALPHA; break; case GL_ONE_MINUS_CONSTANT_ALPHA: - return R300_BLEND_GL_ONE_MINUS_CONST_ALPHA; + return R600_BLEND_GL_ONE_MINUS_CONST_ALPHA; break; default: fprintf(stderr, "unknown blend factor %x\n", factor); - return (is_src) ? R300_BLEND_GL_ONE : R300_BLEND_GL_ZERO; + return (is_src) ? R600_BLEND_GL_ONE : R600_BLEND_GL_ZERO; break; } } @@ -175,7 +175,7 @@ static int blend_factor(GLenum factor, GLboolean is_src) */ /* helper function */ -static void r300SetBlendCntl(r300ContextPtr r300, int func, int eqn, +static void r600SetBlendCntl(r600ContextPtr r600, int func, int eqn, int cbits, int funcA, int eqnA) { GLuint new_ablend, new_cblend; @@ -196,63 +196,63 @@ static void r300SetBlendCntl(r300ContextPtr r300, int func, int eqn, */ #if 0 if (new_ablend == new_cblend) { - new_cblend |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0; + new_cblend |= R600_DISCARD_SRC_PIXELS_SRC_ALPHA_0; } #endif new_cblend |= cbits; - if ((new_ablend != r300->hw.bld.cmd[R300_BLD_ABLEND]) || - (new_cblend != r300->hw.bld.cmd[R300_BLD_CBLEND])) { - R300_STATECHANGE(r300, bld); - r300->hw.bld.cmd[R300_BLD_ABLEND] = new_ablend; - r300->hw.bld.cmd[R300_BLD_CBLEND] = new_cblend; + if ((new_ablend != r600->hw.bld.cmd[R600_BLD_ABLEND]) || + (new_cblend != r600->hw.bld.cmd[R600_BLD_CBLEND])) { + R600_STATECHANGE(r600, bld); + r600->hw.bld.cmd[R600_BLD_ABLEND] = new_ablend; + r600->hw.bld.cmd[R600_BLD_CBLEND] = new_cblend; } } -static void r300SetBlendState(GLcontext * ctx) +static void r600SetBlendState(GLcontext * ctx) { - r300ContextPtr r300 = R300_CONTEXT(ctx); - int func = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) | - (R300_BLEND_GL_ZERO << R300_DST_BLEND_SHIFT); - int eqn = R300_COMB_FCN_ADD_CLAMP; - int funcA = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) | - (R300_BLEND_GL_ZERO << R300_DST_BLEND_SHIFT); - int eqnA = R300_COMB_FCN_ADD_CLAMP; + r600ContextPtr r600 = R600_CONTEXT(ctx); + int func = (R600_BLEND_GL_ONE << R600_SRC_BLEND_SHIFT) | + (R600_BLEND_GL_ZERO << R600_DST_BLEND_SHIFT); + int eqn = R600_COMB_FCN_ADD_CLAMP; + int funcA = (R600_BLEND_GL_ONE << R600_SRC_BLEND_SHIFT) | + (R600_BLEND_GL_ZERO << R600_DST_BLEND_SHIFT); + int eqnA = R600_COMB_FCN_ADD_CLAMP; if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) { - r300SetBlendCntl(r300, func, eqn, 0, func, eqn); + r600SetBlendCntl(r600, func, eqn, 0, func, eqn); return; } func = (blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE) << - R300_SRC_BLEND_SHIFT) | (blend_factor(ctx->Color.BlendDstRGB, + R600_SRC_BLEND_SHIFT) | (blend_factor(ctx->Color.BlendDstRGB, GL_FALSE) << - R300_DST_BLEND_SHIFT); + R600_DST_BLEND_SHIFT); switch (ctx->Color.BlendEquationRGB) { case GL_FUNC_ADD: - eqn = R300_COMB_FCN_ADD_CLAMP; + eqn = R600_COMB_FCN_ADD_CLAMP; break; case GL_FUNC_SUBTRACT: - eqn = R300_COMB_FCN_SUB_CLAMP; + eqn = R600_COMB_FCN_SUB_CLAMP; break; case GL_FUNC_REVERSE_SUBTRACT: - eqn = R300_COMB_FCN_RSUB_CLAMP; + eqn = R600_COMB_FCN_RSUB_CLAMP; break; case GL_MIN: - eqn = R300_COMB_FCN_MIN; - func = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) | - (R300_BLEND_GL_ONE << R300_DST_BLEND_SHIFT); + eqn = R600_COMB_FCN_MIN; + func = (R600_BLEND_GL_ONE << R600_SRC_BLEND_SHIFT) | + (R600_BLEND_GL_ONE << R600_DST_BLEND_SHIFT); break; case GL_MAX: - eqn = R300_COMB_FCN_MAX; - func = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) | - (R300_BLEND_GL_ONE << R300_DST_BLEND_SHIFT); + eqn = R600_COMB_FCN_MAX; + func = (R600_BLEND_GL_ONE << R600_SRC_BLEND_SHIFT) | + (R600_BLEND_GL_ONE << R600_DST_BLEND_SHIFT); break; default: @@ -264,33 +264,33 @@ static void r300SetBlendState(GLcontext * ctx) funcA = (blend_factor(ctx->Color.BlendSrcA, GL_TRUE) << - R300_SRC_BLEND_SHIFT) | (blend_factor(ctx->Color.BlendDstA, + R600_SRC_BLEND_SHIFT) | (blend_factor(ctx->Color.BlendDstA, GL_FALSE) << - R300_DST_BLEND_SHIFT); + R600_DST_BLEND_SHIFT); switch (ctx->Color.BlendEquationA) { case GL_FUNC_ADD: - eqnA = R300_COMB_FCN_ADD_CLAMP; + eqnA = R600_COMB_FCN_ADD_CLAMP; break; case GL_FUNC_SUBTRACT: - eqnA = R300_COMB_FCN_SUB_CLAMP; + eqnA = R600_COMB_FCN_SUB_CLAMP; break; case GL_FUNC_REVERSE_SUBTRACT: - eqnA = R300_COMB_FCN_RSUB_CLAMP; + eqnA = R600_COMB_FCN_RSUB_CLAMP; break; case GL_MIN: - eqnA = R300_COMB_FCN_MIN; - funcA = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) | - (R300_BLEND_GL_ONE << R300_DST_BLEND_SHIFT); + eqnA = R600_COMB_FCN_MIN; + funcA = (R600_BLEND_GL_ONE << R600_SRC_BLEND_SHIFT) | + (R600_BLEND_GL_ONE << R600_DST_BLEND_SHIFT); break; case GL_MAX: - eqnA = R300_COMB_FCN_MAX; - funcA = (R300_BLEND_GL_ONE << R300_SRC_BLEND_SHIFT) | - (R300_BLEND_GL_ONE << R300_DST_BLEND_SHIFT); + eqnA = R600_COMB_FCN_MAX; + funcA = (R600_BLEND_GL_ONE << R600_SRC_BLEND_SHIFT) | + (R600_BLEND_GL_ONE << R600_DST_BLEND_SHIFT); break; default: @@ -300,24 +300,24 @@ static void r300SetBlendState(GLcontext * ctx) return; } - r300SetBlendCntl(r300, + r600SetBlendCntl(r600, func, eqn, - (R300_SEPARATE_ALPHA_ENABLE | - R300_READ_ENABLE | - R300_ALPHA_BLEND_ENABLE), funcA, eqnA); + (R600_SEPARATE_ALPHA_ENABLE | + R600_READ_ENABLE | + R600_ALPHA_BLEND_ENABLE), funcA, eqnA); } -static void r300BlendEquationSeparate(GLcontext * ctx, +static void r600BlendEquationSeparate(GLcontext * ctx, GLenum modeRGB, GLenum modeA) { - r300SetBlendState(ctx); + r600SetBlendState(ctx); } -static void r300BlendFuncSeparate(GLcontext * ctx, +static void r600BlendFuncSeparate(GLcontext * ctx, GLenum sfactorRGB, GLenum dfactorRGB, GLenum sfactorA, GLenum dfactorA) { - r300SetBlendState(ctx); + r600SetBlendState(ctx); } /** @@ -329,22 +329,22 @@ static GLuint translate_logicop(GLenum logicop) { GLuint bits = logicop - GL_CLEAR; bits = ((bits & 1) << 3) | ((bits & 2) << 1) | ((bits & 4) >> 1) | ((bits & 8) >> 3); - return bits << R300_RB3D_ROPCNTL_ROP_SHIFT; + return bits << R600_RB3D_ROPCNTL_ROP_SHIFT; } /** - * Used internally to update the r300->hw hardware state to match the + * Used internally to update the r600->hw hardware state to match the * current OpenGL state. */ -static void r300SetLogicOpState(GLcontext *ctx) +static void r600SetLogicOpState(GLcontext *ctx) { - r300ContextPtr r300 = R300_CONTEXT(ctx); - R300_STATECHANGE(r300, rop); + r600ContextPtr r600 = R600_CONTEXT(ctx); + R600_STATECHANGE(r600, rop); if (RGBA_LOGICOP_ENABLED(ctx)) { - r300->hw.rop.cmd[1] = R300_RB3D_ROPCNTL_ROP_ENABLE | + r600->hw.rop.cmd[1] = R600_RB3D_ROPCNTL_ROP_ENABLE | translate_logicop(ctx->Color.LogicOp); } else { - r300->hw.rop.cmd[1] = 0; + r600->hw.rop.cmd[1] = 0; } } @@ -352,15 +352,15 @@ static void r300SetLogicOpState(GLcontext *ctx) * Called by Mesa when an application program changes the LogicOp state * via glLogicOp. */ -static void r300LogicOpcode(GLcontext *ctx, GLenum logicop) +static void r600LogicOpcode(GLcontext *ctx, GLenum logicop) { if (RGBA_LOGICOP_ENABLED(ctx)) - r300SetLogicOpState(ctx); + r600SetLogicOpState(ctx); } -static void r300ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) +static void r600ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); GLint p; GLint *ip; @@ -371,50 +371,50 @@ static void r300ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) p = (GLint) plane - (GLint) GL_CLIP_PLANE0; ip = (GLint *)ctx->Transform._ClipUserPlane[p]; - R300_STATECHANGE( rmesa, vpucp[p] ); - rmesa->hw.vpucp[p].cmd[R300_VPUCP_X] = ip[0]; - rmesa->hw.vpucp[p].cmd[R300_VPUCP_Y] = ip[1]; - rmesa->hw.vpucp[p].cmd[R300_VPUCP_Z] = ip[2]; - rmesa->hw.vpucp[p].cmd[R300_VPUCP_W] = ip[3]; + R600_STATECHANGE( rmesa, vpucp[p] ); + rmesa->hw.vpucp[p].cmd[R600_VPUCP_X] = ip[0]; + rmesa->hw.vpucp[p].cmd[R600_VPUCP_Y] = ip[1]; + rmesa->hw.vpucp[p].cmd[R600_VPUCP_Z] = ip[2]; + rmesa->hw.vpucp[p].cmd[R600_VPUCP_W] = ip[3]; } -static void r300SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state) +static void r600SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state) { - r300ContextPtr r300 = R300_CONTEXT(ctx); + r600ContextPtr r600 = R600_CONTEXT(ctx); GLuint p; /* no VAP UCP on non-TCL chipsets */ - if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) + if (!(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) return; p = cap - GL_CLIP_PLANE0; - R300_STATECHANGE(r300, vap_clip_cntl); + R600_STATECHANGE(r600, vap_clip_cntl); if (state) { - r300->hw.vap_clip_cntl.cmd[1] |= (R300_VAP_UCP_ENABLE_0 << p); - r300ClipPlane(ctx, cap, NULL); + r600->hw.vap_clip_cntl.cmd[1] |= (R600_VAP_UCP_ENABLE_0 << p); + r600ClipPlane(ctx, cap, NULL); } else { - r300->hw.vap_clip_cntl.cmd[1] &= ~(R300_VAP_UCP_ENABLE_0 << p); + r600->hw.vap_clip_cntl.cmd[1] &= ~(R600_VAP_UCP_ENABLE_0 << p); } } /** * Update our tracked culling state based on Mesa's state. */ -static void r300UpdateCulling(GLcontext * ctx) +static void r600UpdateCulling(GLcontext * ctx) { - r300ContextPtr r300 = R300_CONTEXT(ctx); + r600ContextPtr r600 = R600_CONTEXT(ctx); uint32_t val = 0; if (ctx->Polygon.CullFlag) { switch (ctx->Polygon.CullFaceMode) { case GL_FRONT: - val = R300_CULL_FRONT; + val = R600_CULL_FRONT; break; case GL_BACK: - val = R300_CULL_BACK; + val = R600_CULL_BACK; break; case GL_FRONT_AND_BACK: - val = R300_CULL_FRONT | R300_CULL_BACK; + val = R600_CULL_FRONT | R600_CULL_BACK; break; default: break; @@ -423,37 +423,37 @@ static void r300UpdateCulling(GLcontext * ctx) switch (ctx->Polygon.FrontFace) { case GL_CW: - val |= R300_FRONT_FACE_CW; + val |= R600_FRONT_FACE_CW; break; case GL_CCW: - val |= R300_FRONT_FACE_CCW; + val |= R600_FRONT_FACE_CCW; break; default: break; } - R300_STATECHANGE(r300, cul); - r300->hw.cul.cmd[R300_CUL_CULL] = val; + R600_STATECHANGE(r600, cul); + r600->hw.cul.cmd[R600_CUL_CULL] = val; } -static void r300SetPolygonOffsetState(GLcontext * ctx, GLboolean state) +static void r600SetPolygonOffsetState(GLcontext * ctx, GLboolean state) { - r300ContextPtr r300 = R300_CONTEXT(ctx); + r600ContextPtr r600 = R600_CONTEXT(ctx); - R300_STATECHANGE(r300, occlusion_cntl); + R600_STATECHANGE(r600, occlusion_cntl); if (state) { - r300->hw.occlusion_cntl.cmd[1] |= (3 << 0); + r600->hw.occlusion_cntl.cmd[1] |= (3 << 0); } else { - r300->hw.occlusion_cntl.cmd[1] &= ~(3 << 0); + r600->hw.occlusion_cntl.cmd[1] &= ~(3 << 0); } } static GLboolean current_fragment_program_writes_depth(GLcontext* ctx) { - r300ContextPtr r300 = R300_CONTEXT(ctx); + r600ContextPtr r600 = R600_CONTEXT(ctx); - if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) { - struct r300_fragment_program *fp = (struct r300_fragment_program *) + if (r600->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) { + struct r600_fragment_program *fp = (struct r600_fragment_program *) (char *)ctx->FragmentProgram._Current; return (fp && fp->WritesDepth); } else { @@ -464,29 +464,29 @@ static GLboolean current_fragment_program_writes_depth(GLcontext* ctx) } } -static void r300SetEarlyZState(GLcontext * ctx) +static void r600SetEarlyZState(GLcontext * ctx) { - r300ContextPtr r300 = R300_CONTEXT(ctx); - GLuint topZ = R300_ZTOP_ENABLE; + r600ContextPtr r600 = R600_CONTEXT(ctx); + GLuint topZ = R600_ZTOP_ENABLE; if (ctx->Color.AlphaEnabled && ctx->Color.AlphaFunc != GL_ALWAYS) - topZ = R300_ZTOP_DISABLE; + topZ = R600_ZTOP_DISABLE; if (current_fragment_program_writes_depth(ctx)) - topZ = R300_ZTOP_DISABLE; + topZ = R600_ZTOP_DISABLE; - if (topZ != r300->hw.zstencil_format.cmd[2]) { + if (topZ != r600->hw.zstencil_format.cmd[2]) { /* Note: This completely reemits the stencil format. * I have not tested whether this is strictly necessary, * or if emitting a write to ZB_ZTOP is enough. */ - R300_STATECHANGE(r300, zstencil_format); - r300->hw.zstencil_format.cmd[2] = topZ; + R600_STATECHANGE(r600, zstencil_format); + r600->hw.zstencil_format.cmd[2] = topZ; } } -static void r300SetAlphaState(GLcontext * ctx) +static void r600SetAlphaState(GLcontext * ctx) { - r300ContextPtr r300 = R300_CONTEXT(ctx); + r600ContextPtr r600 = R600_CONTEXT(ctx); GLubyte refByte; uint32_t pp_misc = 0x0; GLboolean really_enabled = ctx->Color.AlphaEnabled; @@ -495,25 +495,25 @@ static void r300SetAlphaState(GLcontext * ctx) switch (ctx->Color.AlphaFunc) { case GL_NEVER: - pp_misc |= R300_FG_ALPHA_FUNC_NEVER; + pp_misc |= R600_FG_ALPHA_FUNC_NEVER; break; case GL_LESS: - pp_misc |= R300_FG_ALPHA_FUNC_LESS; + pp_misc |= R600_FG_ALPHA_FUNC_LESS; break; case GL_EQUAL: - pp_misc |= R300_FG_ALPHA_FUNC_EQUAL; + pp_misc |= R600_FG_ALPHA_FUNC_EQUAL; break; case GL_LEQUAL: - pp_misc |= R300_FG_ALPHA_FUNC_LE; + pp_misc |= R600_FG_ALPHA_FUNC_LE; break; case GL_GREATER: - pp_misc |= R300_FG_ALPHA_FUNC_GREATER; + pp_misc |= R600_FG_ALPHA_FUNC_GREATER; break; case GL_NOTEQUAL: - pp_misc |= R300_FG_ALPHA_FUNC_NOTEQUAL; + pp_misc |= R600_FG_ALPHA_FUNC_NOTEQUAL; break; case GL_GEQUAL: - pp_misc |= R300_FG_ALPHA_FUNC_GE; + pp_misc |= R600_FG_ALPHA_FUNC_GE; break; case GL_ALWAYS: /*pp_misc |= FG_ALPHA_FUNC_ALWAYS; */ @@ -522,72 +522,72 @@ static void r300SetAlphaState(GLcontext * ctx) } if (really_enabled) { - pp_misc |= R300_FG_ALPHA_FUNC_ENABLE; + pp_misc |= R600_FG_ALPHA_FUNC_ENABLE; pp_misc |= R500_FG_ALPHA_FUNC_8BIT; - pp_misc |= (refByte & R300_FG_ALPHA_FUNC_VAL_MASK); + pp_misc |= (refByte & R600_FG_ALPHA_FUNC_VAL_MASK); } else { pp_misc = 0x0; } - R300_STATECHANGE(r300, at); - r300->hw.at.cmd[R300_AT_ALPHA_TEST] = pp_misc; - r300->hw.at.cmd[R300_AT_UNKNOWN] = 0; + R600_STATECHANGE(r600, at); + r600->hw.at.cmd[R600_AT_ALPHA_TEST] = pp_misc; + r600->hw.at.cmd[R600_AT_UNKNOWN] = 0; - r300SetEarlyZState(ctx); + r600SetEarlyZState(ctx); } -static void r300AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) +static void r600AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) { (void)func; (void)ref; - r300SetAlphaState(ctx); + r600SetAlphaState(ctx); } static int translate_func(int func) { switch (func) { case GL_NEVER: - return R300_ZS_NEVER; + return R600_ZS_NEVER; case GL_LESS: - return R300_ZS_LESS; + return R600_ZS_LESS; case GL_EQUAL: - return R300_ZS_EQUAL; + return R600_ZS_EQUAL; case GL_LEQUAL: - return R300_ZS_LEQUAL; + return R600_ZS_LEQUAL; case GL_GREATER: - return R300_ZS_GREATER; + return R600_ZS_GREATER; case GL_NOTEQUAL: - return R300_ZS_NOTEQUAL; + return R600_ZS_NOTEQUAL; case GL_GEQUAL: - return R300_ZS_GEQUAL; + return R600_ZS_GEQUAL; case GL_ALWAYS: - return R300_ZS_ALWAYS; + return R600_ZS_ALWAYS; } return 0; } -static void r300SetDepthState(GLcontext * ctx) +static void r600SetDepthState(GLcontext * ctx) { - r300ContextPtr r300 = R300_CONTEXT(ctx); + r600ContextPtr r600 = R600_CONTEXT(ctx); - R300_STATECHANGE(r300, zs); - r300->hw.zs.cmd[R300_ZS_CNTL_0] &= R300_STENCIL_ENABLE|R300_STENCIL_FRONT_BACK; - r300->hw.zs.cmd[R300_ZS_CNTL_1] &= ~(R300_ZS_MASK << R300_Z_FUNC_SHIFT); + R600_STATECHANGE(r600, zs); + r600->hw.zs.cmd[R600_ZS_CNTL_0] &= R600_STENCIL_ENABLE|R600_STENCIL_FRONT_BACK; + r600->hw.zs.cmd[R600_ZS_CNTL_1] &= ~(R600_ZS_MASK << R600_Z_FUNC_SHIFT); if (ctx->Depth.Test) { - r300->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_Z_ENABLE; + r600->hw.zs.cmd[R600_ZS_CNTL_0] |= R600_Z_ENABLE; if (ctx->Depth.Mask) - r300->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_Z_WRITE_ENABLE; - r300->hw.zs.cmd[R300_ZS_CNTL_1] |= - translate_func(ctx->Depth.Func) << R300_Z_FUNC_SHIFT; + r600->hw.zs.cmd[R600_ZS_CNTL_0] |= R600_Z_WRITE_ENABLE; + r600->hw.zs.cmd[R600_ZS_CNTL_1] |= + translate_func(ctx->Depth.Func) << R600_Z_FUNC_SHIFT; } - r300SetEarlyZState(ctx); + r600SetEarlyZState(ctx); } -static void r300SetStencilState(GLcontext * ctx, GLboolean state) +static void r600SetStencilState(GLcontext * ctx, GLboolean state) { - r300ContextPtr r300 = R300_CONTEXT(ctx); + r600ContextPtr r600 = R600_CONTEXT(ctx); GLboolean hw_stencil = GL_FALSE; if (ctx->DrawBuffer) { struct radeon_renderbuffer *rrbStencil @@ -596,25 +596,25 @@ static void r300SetStencilState(GLcontext * ctx, GLboolean state) } if (hw_stencil) { - R300_STATECHANGE(r300, zs); + R600_STATECHANGE(r600, zs); if (state) { - r300->hw.zs.cmd[R300_ZS_CNTL_0] |= - R300_STENCIL_ENABLE; + r600->hw.zs.cmd[R600_ZS_CNTL_0] |= + R600_STENCIL_ENABLE; } else { - r300->hw.zs.cmd[R300_ZS_CNTL_0] &= - ~R300_STENCIL_ENABLE; + r600->hw.zs.cmd[R600_ZS_CNTL_0] &= + ~R600_STENCIL_ENABLE; } } else { #if R200_MERGED - FALLBACK(&r300->radeon, RADEON_FALLBACK_STENCIL, state); + FALLBACK(&r600->radeon, RADEON_FALLBACK_STENCIL, state); #endif } } -static void r300UpdatePolygonMode(GLcontext * ctx) +static void r600UpdatePolygonMode(GLcontext * ctx) { - r300ContextPtr r300 = R300_CONTEXT(ctx); - uint32_t hw_mode = R300_GA_POLY_MODE_DISABLE; + r600ContextPtr r600 = R600_CONTEXT(ctx); + uint32_t hw_mode = R600_GA_POLY_MODE_DISABLE; /* Only do something if a polygon mode is wanted, default is GL_FILL */ if (ctx->Polygon.FrontMode != GL_FILL || @@ -633,40 +633,40 @@ static void r300UpdatePolygonMode(GLcontext * ctx) } /* Enable polygon mode */ - hw_mode |= R300_GA_POLY_MODE_DUAL; + hw_mode |= R600_GA_POLY_MODE_DUAL; switch (f) { case GL_LINE: - hw_mode |= R300_GA_POLY_MODE_FRONT_PTYPE_LINE; + hw_mode |= R600_GA_POLY_MODE_FRONT_PTYPE_LINE; break; case GL_POINT: - hw_mode |= R300_GA_POLY_MODE_FRONT_PTYPE_POINT; + hw_mode |= R600_GA_POLY_MODE_FRONT_PTYPE_POINT; break; case GL_FILL: - hw_mode |= R300_GA_POLY_MODE_FRONT_PTYPE_TRI; + hw_mode |= R600_GA_POLY_MODE_FRONT_PTYPE_TRI; break; } switch (b) { case GL_LINE: - hw_mode |= R300_GA_POLY_MODE_BACK_PTYPE_LINE; + hw_mode |= R600_GA_POLY_MODE_BACK_PTYPE_LINE; break; case GL_POINT: - hw_mode |= R300_GA_POLY_MODE_BACK_PTYPE_POINT; + hw_mode |= R600_GA_POLY_MODE_BACK_PTYPE_POINT; break; case GL_FILL: - hw_mode |= R300_GA_POLY_MODE_BACK_PTYPE_TRI; + hw_mode |= R600_GA_POLY_MODE_BACK_PTYPE_TRI; break; } } - if (r300->hw.polygon_mode.cmd[1] != hw_mode) { - R300_STATECHANGE(r300, polygon_mode); - r300->hw.polygon_mode.cmd[1] = hw_mode; + if (r600->hw.polygon_mode.cmd[1] != hw_mode) { + R600_STATECHANGE(r600, polygon_mode); + r600->hw.polygon_mode.cmd[1] = hw_mode; } - r300->hw.polygon_mode.cmd[2] = 0x00000001; - r300->hw.polygon_mode.cmd[3] = 0x00000000; + r600->hw.polygon_mode.cmd[2] = 0x00000001; + r600->hw.polygon_mode.cmd[3] = 0x00000000; } /** @@ -674,11 +674,11 @@ static void r300UpdatePolygonMode(GLcontext * ctx) * * \note Mesa already filters redundant calls to this function. */ -static void r300CullFace(GLcontext * ctx, GLenum mode) +static void r600CullFace(GLcontext * ctx, GLenum mode) { (void)mode; - r300UpdateCulling(ctx); + r600UpdateCulling(ctx); } /** @@ -686,12 +686,12 @@ static void r300CullFace(GLcontext * ctx, GLenum mode) * * \note Mesa already filters redundant calls to this function. */ -static void r300FrontFace(GLcontext * ctx, GLenum mode) +static void r600FrontFace(GLcontext * ctx, GLenum mode) { (void)mode; - r300UpdateCulling(ctx); - r300UpdatePolygonMode(ctx); + r600UpdateCulling(ctx); + r600UpdatePolygonMode(ctx); } /** @@ -699,10 +699,10 @@ static void r300FrontFace(GLcontext * ctx, GLenum mode) * * \note Mesa already filters redundant calls to this function. */ -static void r300DepthFunc(GLcontext * ctx, GLenum func) +static void r600DepthFunc(GLcontext * ctx, GLenum func) { (void)func; - r300SetDepthState(ctx); + r600SetDepthState(ctx); } /** @@ -710,60 +710,60 @@ static void r300DepthFunc(GLcontext * ctx, GLenum func) * * \note Mesa already filters redundant calls to this function. */ -static void r300DepthMask(GLcontext * ctx, GLboolean mask) +static void r600DepthMask(GLcontext * ctx, GLboolean mask) { (void)mask; - r300SetDepthState(ctx); + r600SetDepthState(ctx); } /** * Handle glColorMask() */ -static void r300ColorMask(GLcontext * ctx, +static void r600ColorMask(GLcontext * ctx, GLboolean r, GLboolean g, GLboolean b, GLboolean a) { - r300ContextPtr r300 = R300_CONTEXT(ctx); + r600ContextPtr r600 = R600_CONTEXT(ctx); int mask = (r ? RB3D_COLOR_CHANNEL_MASK_RED_MASK0 : 0) | (g ? RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0 : 0) | (b ? RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 : 0) | (a ? RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0 : 0); - if (mask != r300->hw.cmk.cmd[R300_CMK_COLORMASK]) { - R300_STATECHANGE(r300, cmk); - r300->hw.cmk.cmd[R300_CMK_COLORMASK] = mask; + if (mask != r600->hw.cmk.cmd[R600_CMK_COLORMASK]) { + R600_STATECHANGE(r600, cmk); + r600->hw.cmk.cmd[R600_CMK_COLORMASK] = mask; } } /* ============================================================= * Point state */ -static void r300PointSize(GLcontext * ctx, GLfloat size) +static void r600PointSize(GLcontext * ctx, GLfloat size) { - r300ContextPtr r300 = R300_CONTEXT(ctx); + r600ContextPtr r600 = R600_CONTEXT(ctx); /* same size limits for AA, non-AA points */ size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize); - R300_STATECHANGE(r300, ps); - r300->hw.ps.cmd[R300_PS_POINTSIZE] = - ((int)(size * 6) << R300_POINTSIZE_X_SHIFT) | - ((int)(size * 6) << R300_POINTSIZE_Y_SHIFT); + R600_STATECHANGE(r600, ps); + r600->hw.ps.cmd[R600_PS_POINTSIZE] = + ((int)(size * 6) << R600_POINTSIZE_X_SHIFT) | + ((int)(size * 6) << R600_POINTSIZE_Y_SHIFT); } -static void r300PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) +static void r600PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) { - r300ContextPtr r300 = R300_CONTEXT(ctx); + r600ContextPtr r600 = R600_CONTEXT(ctx); switch (pname) { case GL_POINT_SIZE_MIN: - R300_STATECHANGE(r300, ga_point_minmax); - r300->hw.ga_point_minmax.cmd[1] &= ~R300_GA_POINT_MINMAX_MIN_MASK; - r300->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MinSize * 6.0); + R600_STATECHANGE(r600, ga_point_minmax); + r600->hw.ga_point_minmax.cmd[1] &= ~R600_GA_POINT_MINMAX_MIN_MASK; + r600->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MinSize * 6.0); break; case GL_POINT_SIZE_MAX: - R300_STATECHANGE(r300, ga_point_minmax); - r300->hw.ga_point_minmax.cmd[1] &= ~R300_GA_POINT_MINMAX_MAX_MASK; - r300->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MaxSize * 6.0) - << R300_GA_POINT_MINMAX_MAX_SHIFT; + R600_STATECHANGE(r600, ga_point_minmax); + r600->hw.ga_point_minmax.cmd[1] &= ~R600_GA_POINT_MINMAX_MAX_MASK; + r600->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MaxSize * 6.0) + << R600_GA_POINT_MINMAX_MAX_SHIFT; break; case GL_POINT_DISTANCE_ATTENUATION: break; @@ -777,24 +777,24 @@ static void r300PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * pa /* ============================================================= * Line state */ -static void r300LineWidth(GLcontext * ctx, GLfloat widthf) +static void r600LineWidth(GLcontext * ctx, GLfloat widthf) { - r300ContextPtr r300 = R300_CONTEXT(ctx); + r600ContextPtr r600 = R600_CONTEXT(ctx); widthf = CLAMP(widthf, ctx->Const.MinPointSize, ctx->Const.MaxPointSize); - R300_STATECHANGE(r300, lcntl); - r300->hw.lcntl.cmd[1] = - R300_LINE_CNT_HO | R300_LINE_CNT_VE | (int)(widthf * 6.0); + R600_STATECHANGE(r600, lcntl); + r600->hw.lcntl.cmd[1] = + R600_LINE_CNT_HO | R600_LINE_CNT_VE | (int)(widthf * 6.0); } -static void r300PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) +static void r600PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) { (void)face; (void)mode; - r300UpdatePolygonMode(ctx); + r600UpdatePolygonMode(ctx); } /* ============================================================= @@ -805,40 +805,40 @@ static int translate_stencil_op(int op) { switch (op) { case GL_KEEP: - return R300_ZS_KEEP; + return R600_ZS_KEEP; case GL_ZERO: - return R300_ZS_ZERO; + return R600_ZS_ZERO; case GL_REPLACE: - return R300_ZS_REPLACE; + return R600_ZS_REPLACE; case GL_INCR: - return R300_ZS_INCR; + return R600_ZS_INCR; case GL_DECR: - return R300_ZS_DECR; + return R600_ZS_DECR; case GL_INCR_WRAP_EXT: - return R300_ZS_INCR_WRAP; + return R600_ZS_INCR_WRAP; case GL_DECR_WRAP_EXT: - return R300_ZS_DECR_WRAP; + return R600_ZS_DECR_WRAP; case GL_INVERT: - return R300_ZS_INVERT; + return R600_ZS_INVERT; default: WARN_ONCE("Do not know how to translate stencil op"); - return R300_ZS_KEEP; + return R600_ZS_KEEP; } return 0; } -static void r300ShadeModel(GLcontext * ctx, GLenum mode) +static void r600ShadeModel(GLcontext * ctx, GLenum mode) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); - R300_STATECHANGE(rmesa, shade); + R600_STATECHANGE(rmesa, shade); rmesa->hw.shade.cmd[1] = 0x00000002; switch (mode) { case GL_FLAT: - rmesa->hw.shade.cmd[2] = R300_RE_SHADE_MODEL_FLAT; + rmesa->hw.shade.cmd[2] = R600_RE_SHADE_MODEL_FLAT; break; case GL_SMOOTH: - rmesa->hw.shade.cmd[2] = R300_RE_SHADE_MODEL_SMOOTH; + rmesa->hw.shade.cmd[2] = R600_RE_SHADE_MODEL_SMOOTH; break; default: return; @@ -847,80 +847,80 @@ static void r300ShadeModel(GLcontext * ctx, GLenum mode) rmesa->hw.shade.cmd[4] = 0x00000000; } -static void r300StencilFuncSeparate(GLcontext * ctx, GLenum face, +static void r600StencilFuncSeparate(GLcontext * ctx, GLenum face, GLenum func, GLint ref, GLuint mask) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); GLuint refmask = - ((ctx->Stencil.Ref[0] & 0xff) << R300_STENCILREF_SHIFT) - | ((ctx->Stencil.ValueMask[0] & 0xff) << R300_STENCILMASK_SHIFT); + ((ctx->Stencil.Ref[0] & 0xff) << R600_STENCILREF_SHIFT) + | ((ctx->Stencil.ValueMask[0] & 0xff) << R600_STENCILMASK_SHIFT); const unsigned back = ctx->Stencil._BackFace; GLuint flag; - R300_STATECHANGE(rmesa, zs); - rmesa->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_STENCIL_FRONT_BACK; - rmesa->hw.zs.cmd[R300_ZS_CNTL_1] &= ~((R300_ZS_MASK << - R300_S_FRONT_FUNC_SHIFT) - | (R300_ZS_MASK << - R300_S_BACK_FUNC_SHIFT)); + R600_STATECHANGE(rmesa, zs); + rmesa->hw.zs.cmd[R600_ZS_CNTL_0] |= R600_STENCIL_FRONT_BACK; + rmesa->hw.zs.cmd[R600_ZS_CNTL_1] &= ~((R600_ZS_MASK << + R600_S_FRONT_FUNC_SHIFT) + | (R600_ZS_MASK << + R600_S_BACK_FUNC_SHIFT)); - rmesa->hw.zs.cmd[R300_ZS_CNTL_2] &= - ~((R300_STENCILREF_MASK << R300_STENCILREF_SHIFT) | - (R300_STENCILREF_MASK << R300_STENCILMASK_SHIFT)); + rmesa->hw.zs.cmd[R600_ZS_CNTL_2] &= + ~((R600_STENCILREF_MASK << R600_STENCILREF_SHIFT) | + (R600_STENCILREF_MASK << R600_STENCILMASK_SHIFT)); flag = translate_func(ctx->Stencil.Function[0]); - rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |= - (flag << R300_S_FRONT_FUNC_SHIFT); + rmesa->hw.zs.cmd[R600_ZS_CNTL_1] |= + (flag << R600_S_FRONT_FUNC_SHIFT); flag = translate_func(ctx->Stencil.Function[back]); - rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |= - (flag << R300_S_BACK_FUNC_SHIFT); - rmesa->hw.zs.cmd[R300_ZS_CNTL_2] |= refmask; + rmesa->hw.zs.cmd[R600_ZS_CNTL_1] |= + (flag << R600_S_BACK_FUNC_SHIFT); + rmesa->hw.zs.cmd[R600_ZS_CNTL_2] |= refmask; } -static void r300StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) +static void r600StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); - R300_STATECHANGE(rmesa, zs); - rmesa->hw.zs.cmd[R300_ZS_CNTL_2] &= - ~(R300_STENCILREF_MASK << - R300_STENCILWRITEMASK_SHIFT); - rmesa->hw.zs.cmd[R300_ZS_CNTL_2] |= + R600_STATECHANGE(rmesa, zs); + rmesa->hw.zs.cmd[R600_ZS_CNTL_2] &= + ~(R600_STENCILREF_MASK << + R600_STENCILWRITEMASK_SHIFT); + rmesa->hw.zs.cmd[R600_ZS_CNTL_2] |= (ctx->Stencil. - WriteMask[0] & R300_STENCILREF_MASK) << - R300_STENCILWRITEMASK_SHIFT; + WriteMask[0] & R600_STENCILREF_MASK) << + R600_STENCILWRITEMASK_SHIFT; } -static void r300StencilOpSeparate(GLcontext * ctx, GLenum face, +static void r600StencilOpSeparate(GLcontext * ctx, GLenum face, GLenum fail, GLenum zfail, GLenum zpass) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); const unsigned back = ctx->Stencil._BackFace; - R300_STATECHANGE(rmesa, zs); + R600_STATECHANGE(rmesa, zs); /* It is easier to mask what's left.. */ - rmesa->hw.zs.cmd[R300_ZS_CNTL_1] &= - (R300_ZS_MASK << R300_Z_FUNC_SHIFT) | - (R300_ZS_MASK << R300_S_FRONT_FUNC_SHIFT) | - (R300_ZS_MASK << R300_S_BACK_FUNC_SHIFT); + rmesa->hw.zs.cmd[R600_ZS_CNTL_1] &= + (R600_ZS_MASK << R600_Z_FUNC_SHIFT) | + (R600_ZS_MASK << R600_S_FRONT_FUNC_SHIFT) | + (R600_ZS_MASK << R600_S_BACK_FUNC_SHIFT); - rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |= + rmesa->hw.zs.cmd[R600_ZS_CNTL_1] |= (translate_stencil_op(ctx->Stencil.FailFunc[0]) << - R300_S_FRONT_SFAIL_OP_SHIFT) + R600_S_FRONT_SFAIL_OP_SHIFT) | (translate_stencil_op(ctx->Stencil.ZFailFunc[0]) << - R300_S_FRONT_ZFAIL_OP_SHIFT) + R600_S_FRONT_ZFAIL_OP_SHIFT) | (translate_stencil_op(ctx->Stencil.ZPassFunc[0]) << - R300_S_FRONT_ZPASS_OP_SHIFT); + R600_S_FRONT_ZPASS_OP_SHIFT); - rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |= + rmesa->hw.zs.cmd[R600_ZS_CNTL_1] |= (translate_stencil_op(ctx->Stencil.FailFunc[back]) << - R300_S_BACK_SFAIL_OP_SHIFT) + R600_S_BACK_SFAIL_OP_SHIFT) | (translate_stencil_op(ctx->Stencil.ZFailFunc[back]) << - R300_S_BACK_ZFAIL_OP_SHIFT) + R600_S_BACK_ZFAIL_OP_SHIFT) | (translate_stencil_op(ctx->Stencil.ZPassFunc[back]) << - R300_S_BACK_ZPASS_OP_SHIFT); + R600_S_BACK_ZPASS_OP_SHIFT); } /* ============================================================= @@ -933,9 +933,9 @@ static void r300StencilOpSeparate(GLcontext * ctx, GLenum face, #define SUBPIXEL_X 0.125 #define SUBPIXEL_Y 0.125 -static void r300UpdateWindow(GLcontext * ctx) +static void r600UpdateWindow(GLcontext * ctx) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; @@ -959,36 +959,36 @@ static void r300UpdateWindow(GLcontext * ctx) GLfloat sz = v[MAT_SZ] * depthScale; GLfloat tz = v[MAT_TZ] * depthScale; - R300_STATECHANGE(rmesa, vpt); + R600_STATECHANGE(rmesa, vpt); - rmesa->hw.vpt.cmd[R300_VPT_XSCALE] = r300PackFloat32(sx); - rmesa->hw.vpt.cmd[R300_VPT_XOFFSET] = r300PackFloat32(tx); - rmesa->hw.vpt.cmd[R300_VPT_YSCALE] = r300PackFloat32(sy); - rmesa->hw.vpt.cmd[R300_VPT_YOFFSET] = r300PackFloat32(ty); - rmesa->hw.vpt.cmd[R300_VPT_ZSCALE] = r300PackFloat32(sz); - rmesa->hw.vpt.cmd[R300_VPT_ZOFFSET] = r300PackFloat32(tz); + rmesa->hw.vpt.cmd[R600_VPT_XSCALE] = r600PackFloat32(sx); + rmesa->hw.vpt.cmd[R600_VPT_XOFFSET] = r600PackFloat32(tx); + rmesa->hw.vpt.cmd[R600_VPT_YSCALE] = r600PackFloat32(sy); + rmesa->hw.vpt.cmd[R600_VPT_YOFFSET] = r600PackFloat32(ty); + rmesa->hw.vpt.cmd[R600_VPT_ZSCALE] = r600PackFloat32(sz); + rmesa->hw.vpt.cmd[R600_VPT_ZOFFSET] = r600PackFloat32(tz); } -static void r300Viewport(GLcontext * ctx, GLint x, GLint y, +static void r600Viewport(GLcontext * ctx, GLint x, GLint y, GLsizei width, GLsizei height) { /* Don't pipeline viewport changes, conflict with window offset * setting below. Could apply deltas to rescue pipelined viewport * values, or keep the originals hanging around. */ - r300UpdateWindow(ctx); + r600UpdateWindow(ctx); radeon_viewport(ctx, x, y, width, height); } -static void r300DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) +static void r600DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) { - r300UpdateWindow(ctx); + r600UpdateWindow(ctx); } -void r300UpdateViewportOffset(GLcontext * ctx) +void r600UpdateViewportOffset(GLcontext * ctx) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); __DRIdrawablePrivate *dPriv = ((radeonContextPtr) rmesa)->dri.drawable; GLfloat xoffset = (GLfloat) dPriv->x; GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h; @@ -997,14 +997,14 @@ void r300UpdateViewportOffset(GLcontext * ctx) GLfloat tx = v[MAT_TX] + xoffset + SUBPIXEL_X; GLfloat ty = (-v[MAT_TY]) + yoffset + SUBPIXEL_Y; - if (rmesa->hw.vpt.cmd[R300_VPT_XOFFSET] != r300PackFloat32(tx) || - rmesa->hw.vpt.cmd[R300_VPT_YOFFSET] != r300PackFloat32(ty)) { + if (rmesa->hw.vpt.cmd[R600_VPT_XOFFSET] != r600PackFloat32(tx) || + rmesa->hw.vpt.cmd[R600_VPT_YOFFSET] != r600PackFloat32(ty)) { /* Note: this should also modify whatever data the context reset * code uses... */ - R300_STATECHANGE(rmesa, vpt); - rmesa->hw.vpt.cmd[R300_VPT_XOFFSET] = r300PackFloat32(tx); - rmesa->hw.vpt.cmd[R300_VPT_YOFFSET] = r300PackFloat32(ty); + R600_STATECHANGE(rmesa, vpt); + rmesa->hw.vpt.cmd[R600_VPT_XOFFSET] = r600PackFloat32(tx); + rmesa->hw.vpt.cmd[R600_VPT_YOFFSET] = r600PackFloat32(ty); } @@ -1012,23 +1012,23 @@ void r300UpdateViewportOffset(GLcontext * ctx) } static void -r300FetchStateParameter(GLcontext * ctx, +r600FetchStateParameter(GLcontext * ctx, const gl_state_index state[STATE_LENGTH], GLfloat * value) { - r300ContextPtr r300 = R300_CONTEXT(ctx); + r600ContextPtr r600 = R600_CONTEXT(ctx); switch (state[0]) { case STATE_INTERNAL: switch (state[1]) { - case STATE_R300_WINDOW_DIMENSION: - value[0] = r300->radeon.dri.drawable->w * 0.5f; /* width*0.5 */ - value[1] = r300->radeon.dri.drawable->h * 0.5f; /* height*0.5 */ + case STATE_R600_WINDOW_DIMENSION: + value[0] = r600->radeon.dri.drawable->w * 0.5f; /* width*0.5 */ + value[1] = r600->radeon.dri.drawable->h * 0.5f; /* height*0.5 */ value[2] = 0.5F; /* for moving range [-1 1] -> [0 1] */ value[3] = 1.0F; /* not used */ break; - case STATE_R300_TEXRECT_FACTOR:{ + case STATE_R600_TEXRECT_FACTOR:{ struct gl_texture_object *t = ctx->Texture.Unit[state[2]].CurrentTex[TEXTURE_RECT_INDEX]; @@ -1057,19 +1057,19 @@ r300FetchStateParameter(GLcontext * ctx, } /** - * Update R300's own internal state parameters. - * For now just STATE_R300_WINDOW_DIMENSION + * Update R600's own internal state parameters. + * For now just STATE_R600_WINDOW_DIMENSION */ -void r300UpdateStateParameters(GLcontext * ctx, GLuint new_state) +void r600UpdateStateParameters(GLcontext * ctx, GLuint new_state) { - struct r300_fragment_program *fp; + struct r600_fragment_program *fp; struct gl_program_parameter_list *paramList; GLuint i; if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM))) return; - fp = (struct r300_fragment_program *)ctx->FragmentProgram._Current; + fp = (struct r600_fragment_program *)ctx->FragmentProgram._Current; if (!fp) return; @@ -1080,7 +1080,7 @@ void r300UpdateStateParameters(GLcontext * ctx, GLuint new_state) for (i = 0; i < paramList->NumParameters; i++) { if (paramList->Parameters[i].Type == PROGRAM_STATE_VAR) { - r300FetchStateParameter(ctx, + r600FetchStateParameter(ctx, paramList->Parameters[i]. StateIndexes, paramList->ParameterValues[i]); @@ -1091,9 +1091,9 @@ void r300UpdateStateParameters(GLcontext * ctx, GLuint new_state) /* ============================================================= * Polygon state */ -static void r300PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) +static void r600PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); GLfloat constant = units; switch (ctx->Visual.depthBits) { @@ -1109,22 +1109,22 @@ static void r300PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) /* fprintf(stderr, "%s f:%f u:%f\n", __FUNCTION__, factor, constant); */ - R300_STATECHANGE(rmesa, zbs); - rmesa->hw.zbs.cmd[R300_ZBS_T_FACTOR] = r300PackFloat32(factor); - rmesa->hw.zbs.cmd[R300_ZBS_T_CONSTANT] = r300PackFloat32(constant); - rmesa->hw.zbs.cmd[R300_ZBS_W_FACTOR] = r300PackFloat32(factor); - rmesa->hw.zbs.cmd[R300_ZBS_W_CONSTANT] = r300PackFloat32(constant); + R600_STATECHANGE(rmesa, zbs); + rmesa->hw.zbs.cmd[R600_ZBS_T_FACTOR] = r600PackFloat32(factor); + rmesa->hw.zbs.cmd[R600_ZBS_T_CONSTANT] = r600PackFloat32(constant); + rmesa->hw.zbs.cmd[R600_ZBS_W_FACTOR] = r600PackFloat32(factor); + rmesa->hw.zbs.cmd[R600_ZBS_W_CONSTANT] = r600PackFloat32(constant); } /* Routing and texture-related */ -/* r300 doesnt handle GL_CLAMP and GL_MIRROR_CLAMP_EXT correctly when filter is NEAREST. +/* r600 doesnt handle GL_CLAMP and GL_MIRROR_CLAMP_EXT correctly when filter is NEAREST. * Since texwrap produces same results for GL_CLAMP and GL_CLAMP_TO_EDGE we use them instead. * We need to recalculate wrap modes whenever filter mode is changed because someone might do: * glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_NEAREST); * glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_WRAP_S, GL_CLAMP); * glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_LINEAR); - * Since r300 completely ignores R300_TX_CLAMP when either min or mag is nearest it cant handle + * Since r600 completely ignores R600_TX_CLAMP when either min or mag is nearest it cant handle * combinations where only one of them is nearest. */ static unsigned long gen_fixed_filter(unsigned long f) @@ -1133,103 +1133,103 @@ static unsigned long gen_fixed_filter(unsigned long f) //return f; /* We ignore MIRROR bit so we dont have to do everything twice */ - if ((f & ((7 - 1) << R300_TX_WRAP_S_SHIFT)) == - (R300_TX_CLAMP << R300_TX_WRAP_S_SHIFT)) { + if ((f & ((7 - 1) << R600_TX_WRAP_S_SHIFT)) == + (R600_TX_CLAMP << R600_TX_WRAP_S_SHIFT)) { needs_fixing |= 1; } - if ((f & ((7 - 1) << R300_TX_WRAP_T_SHIFT)) == - (R300_TX_CLAMP << R300_TX_WRAP_T_SHIFT)) { + if ((f & ((7 - 1) << R600_TX_WRAP_T_SHIFT)) == + (R600_TX_CLAMP << R600_TX_WRAP_T_SHIFT)) { needs_fixing |= 2; } - if ((f & ((7 - 1) << R300_TX_WRAP_R_SHIFT)) == - (R300_TX_CLAMP << R300_TX_WRAP_R_SHIFT)) { + if ((f & ((7 - 1) << R600_TX_WRAP_R_SHIFT)) == + (R600_TX_CLAMP << R600_TX_WRAP_R_SHIFT)) { needs_fixing |= 4; } if (!needs_fixing) return f; - mag = f & R300_TX_MAG_FILTER_MASK; - min = f & (R300_TX_MIN_FILTER_MASK|R300_TX_MIN_FILTER_MIP_MASK); + mag = f & R600_TX_MAG_FILTER_MASK; + min = f & (R600_TX_MIN_FILTER_MASK|R600_TX_MIN_FILTER_MIP_MASK); /* TODO: Check for anisto filters too */ - if ((mag != R300_TX_MAG_FILTER_NEAREST) - && (min != R300_TX_MIN_FILTER_NEAREST)) + if ((mag != R600_TX_MAG_FILTER_NEAREST) + && (min != R600_TX_MIN_FILTER_NEAREST)) return f; - /* r300 cant handle these modes hence we force nearest to linear */ - if ((mag == R300_TX_MAG_FILTER_NEAREST) - && (min != R300_TX_MIN_FILTER_NEAREST)) { - f &= ~R300_TX_MAG_FILTER_NEAREST; - f |= R300_TX_MAG_FILTER_LINEAR; + /* r600 cant handle these modes hence we force nearest to linear */ + if ((mag == R600_TX_MAG_FILTER_NEAREST) + && (min != R600_TX_MIN_FILTER_NEAREST)) { + f &= ~R600_TX_MAG_FILTER_NEAREST; + f |= R600_TX_MAG_FILTER_LINEAR; return f; } - if ((min == R300_TX_MIN_FILTER_NEAREST) - && (mag != R300_TX_MAG_FILTER_NEAREST)) { - f &= ~R300_TX_MIN_FILTER_NEAREST; - f |= R300_TX_MIN_FILTER_LINEAR; + if ((min == R600_TX_MIN_FILTER_NEAREST) + && (mag != R600_TX_MAG_FILTER_NEAREST)) { + f &= ~R600_TX_MIN_FILTER_NEAREST; + f |= R600_TX_MIN_FILTER_LINEAR; return f; } /* Both are nearest */ if (needs_fixing & 1) { - f &= ~((7 - 1) << R300_TX_WRAP_S_SHIFT); - f |= R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_S_SHIFT; + f &= ~((7 - 1) << R600_TX_WRAP_S_SHIFT); + f |= R600_TX_CLAMP_TO_EDGE << R600_TX_WRAP_S_SHIFT; } if (needs_fixing & 2) { - f &= ~((7 - 1) << R300_TX_WRAP_T_SHIFT); - f |= R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_T_SHIFT; + f &= ~((7 - 1) << R600_TX_WRAP_T_SHIFT); + f |= R600_TX_CLAMP_TO_EDGE << R600_TX_WRAP_T_SHIFT; } if (needs_fixing & 4) { - f &= ~((7 - 1) << R300_TX_WRAP_R_SHIFT); - f |= R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_R_SHIFT; + f &= ~((7 - 1) << R600_TX_WRAP_R_SHIFT); + f |= R600_TX_CLAMP_TO_EDGE << R600_TX_WRAP_R_SHIFT; } return f; } -static void r300SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings) +static void r600SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings) { - r300ContextPtr r300 = R300_CONTEXT(ctx); + r600ContextPtr r600 = R600_CONTEXT(ctx); int i; - struct r300_fragment_program *fp = (struct r300_fragment_program *) + struct r600_fragment_program *fp = (struct r600_fragment_program *) (char *)ctx->FragmentProgram._Current; - struct r300_fragment_program_code *code = &fp->code; + struct r600_fragment_program_code *code = &fp->code; - R300_STATECHANGE(r300, fpt); + R600_STATECHANGE(r600, fpt); for (i = 0; i < code->tex.length; i++) { int unit; int opcode; unsigned long val; - unit = code->tex.inst[i] >> R300_TEX_ID_SHIFT; + unit = code->tex.inst[i] >> R600_TEX_ID_SHIFT; unit &= 15; val = code->tex.inst[i]; - val &= ~R300_TEX_ID_MASK; + val &= ~R600_TEX_ID_MASK; opcode = - (val & R300_TEX_INST_MASK) >> R300_TEX_INST_SHIFT; - if (opcode == R300_TEX_OP_KIL) { - r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val; + (val & R600_TEX_INST_MASK) >> R600_TEX_INST_SHIFT; + if (opcode == R600_TEX_OP_KIL) { + r600->hw.fpt.cmd[R600_FPT_INSTR_0 + i] = val; } else { if (tmu_mappings[unit] >= 0) { val |= tmu_mappings[unit] << - R300_TEX_ID_SHIFT; - r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val; + R600_TEX_ID_SHIFT; + r600->hw.fpt.cmd[R600_FPT_INSTR_0 + i] = val; } else { // We get here when the corresponding texture image is incomplete // (e.g. incomplete mipmaps etc.) - r300->hw.fpt.cmd[R300_FPT_INSTR_0 + i] = val; + r600->hw.fpt.cmd[R600_FPT_INSTR_0 + i] = val; } } } - r300->hw.fpt.cmd[R300_FPT_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, - R300_US_TEX_INST_0, code->tex.length); + r600->hw.fpt.cmd[R600_FPT_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, + R600_US_TEX_INST_0, code->tex.length); } static void r500SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings) @@ -1274,40 +1274,40 @@ static GLuint translate_lod_bias(GLfloat bias) b = (1 << 9)-1; else if (b < -(1 << 9)) b = -(1 << 9); - return (((GLuint)b) << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK; + return (((GLuint)b) << R600_LOD_BIAS_SHIFT) & R600_LOD_BIAS_MASK; } -static void r300SetupTextures(GLcontext * ctx) +static void r600SetupTextures(GLcontext * ctx) { int i, mtu; struct radeon_tex_obj *t; - r300ContextPtr r300 = R300_CONTEXT(ctx); + r600ContextPtr r600 = R600_CONTEXT(ctx); int hw_tmu = 0; int last_hw_tmu = -1; /* -1 translates into no setup costs for fields */ - int tmu_mappings[R300_MAX_TEXTURE_UNITS] = { -1, }; - struct r300_fragment_program *fp = (struct r300_fragment_program *) + int tmu_mappings[R600_MAX_TEXTURE_UNITS] = { -1, }; + struct r600_fragment_program *fp = (struct r600_fragment_program *) (char *)ctx->FragmentProgram._Current; - R300_STATECHANGE(r300, txe); - R300_STATECHANGE(r300, tex.filter); - R300_STATECHANGE(r300, tex.filter_1); - R300_STATECHANGE(r300, tex.size); - R300_STATECHANGE(r300, tex.format); - R300_STATECHANGE(r300, tex.pitch); - R300_STATECHANGE(r300, tex.offset); - R300_STATECHANGE(r300, tex.chroma_key); - R300_STATECHANGE(r300, tex.border_color); + R600_STATECHANGE(r600, txe); + R600_STATECHANGE(r600, tex.filter); + R600_STATECHANGE(r600, tex.filter_1); + R600_STATECHANGE(r600, tex.size); + R600_STATECHANGE(r600, tex.format); + R600_STATECHANGE(r600, tex.pitch); + R600_STATECHANGE(r600, tex.offset); + R600_STATECHANGE(r600, tex.chroma_key); + R600_STATECHANGE(r600, tex.border_color); - r300->hw.txe.cmd[R300_TXE_ENABLE] = 0x0; + r600->hw.txe.cmd[R600_TXE_ENABLE] = 0x0; - mtu = r300->radeon.glCtx->Const.MaxTextureUnits; + mtu = r600->radeon.glCtx->Const.MaxTextureUnits; if (RADEON_DEBUG & DEBUG_STATE) fprintf(stderr, "mtu=%d\n", mtu); - if (mtu > R300_MAX_TEXTURE_UNITS) { + if (mtu > R600_MAX_TEXTURE_UNITS) { fprintf(stderr, - "Aiiee ! mtu=%d is greater than R300_MAX_TEXTURE_UNITS=%d\n", - mtu, R300_MAX_TEXTURE_UNITS); + "Aiiee ! mtu=%d is greater than R600_MAX_TEXTURE_UNITS=%d\n", + mtu, R600_MAX_TEXTURE_UNITS); _mesa_exit(-1); } @@ -1330,9 +1330,9 @@ static void r300SetupTextures(GLcontext * ctx) fprintf(stderr, "Activating texture unit %d\n", i); - r300->hw.txe.cmd[R300_TXE_ENABLE] |= (1 << hw_tmu); + r600->hw.txe.cmd[R600_TXE_ENABLE] |= (1 << hw_tmu); - r300->hw.tex.filter.cmd[R300_TEX_VALUE_0 + + r600->hw.tex.filter.cmd[R600_TEX_VALUE_0 + hw_tmu] = gen_fixed_filter(t->pp_txfilter) | (hw_tmu << 28); /* Note: There is a LOD bias per texture unit and a LOD bias @@ -1340,28 +1340,28 @@ static void r300SetupTextures(GLcontext * ctx) * (The per-texture object LOD bias was introduced in OpenGL 1.4 * and is not present in the EXT_texture_object extension). */ - r300->hw.tex.filter_1.cmd[R300_TEX_VALUE_0 + hw_tmu] = + r600->hw.tex.filter_1.cmd[R600_TEX_VALUE_0 + hw_tmu] = t->pp_txfilter_1 | translate_lod_bias(ctx->Texture.Unit[i].LodBias + t->base.LodBias); - r300->hw.tex.size.cmd[R300_TEX_VALUE_0 + hw_tmu] = + r600->hw.tex.size.cmd[R600_TEX_VALUE_0 + hw_tmu] = t->pp_txsize; - r300->hw.tex.format.cmd[R300_TEX_VALUE_0 + + r600->hw.tex.format.cmd[R600_TEX_VALUE_0 + hw_tmu] = t->pp_txformat; - r300->hw.tex.pitch.cmd[R300_TEX_VALUE_0 + hw_tmu] = + r600->hw.tex.pitch.cmd[R600_TEX_VALUE_0 + hw_tmu] = t->pp_txpitch; - r300->hw.textures[hw_tmu] = t; + r600->hw.textures[hw_tmu] = t; - if (t->tile_bits & R300_TXO_MACRO_TILE) { + if (t->tile_bits & R600_TXO_MACRO_TILE) { WARN_ONCE("macro tiling enabled!\n"); } - if (t->tile_bits & R300_TXO_MICRO_TILE) { + if (t->tile_bits & R600_TXO_MICRO_TILE) { WARN_ONCE("micro tiling enabled!\n"); } - r300->hw.tex.chroma_key.cmd[R300_TEX_VALUE_0 + + r600->hw.tex.chroma_key.cmd[R600_TEX_VALUE_0 + hw_tmu] = 0x0; - r300->hw.tex.border_color.cmd[R300_TEX_VALUE_0 + + r600->hw.tex.border_color.cmd[R600_TEX_VALUE_0 + hw_tmu] = t->pp_border_color; @@ -1371,59 +1371,59 @@ static void r300SetupTextures(GLcontext * ctx) } } - r300->hw.tex.filter.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, last_hw_tmu + 1); - r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, last_hw_tmu + 1); - r300->hw.tex.size.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, last_hw_tmu + 1); - r300->hw.tex.format.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, last_hw_tmu + 1); - r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, last_hw_tmu + 1); - r300->hw.tex.offset.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, last_hw_tmu + 1); - r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, last_hw_tmu + 1); - r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, last_hw_tmu + 1); + r600->hw.tex.filter.cmd[R600_TEX_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_TX_FILTER0_0, last_hw_tmu + 1); + r600->hw.tex.filter_1.cmd[R600_TEX_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_TX_FILTER1_0, last_hw_tmu + 1); + r600->hw.tex.size.cmd[R600_TEX_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_TX_SIZE_0, last_hw_tmu + 1); + r600->hw.tex.format.cmd[R600_TEX_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_TX_FORMAT_0, last_hw_tmu + 1); + r600->hw.tex.pitch.cmd[R600_TEX_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_TX_FORMAT2_0, last_hw_tmu + 1); + r600->hw.tex.offset.cmd[R600_TEX_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_TX_OFFSET_0, last_hw_tmu + 1); + r600->hw.tex.chroma_key.cmd[R600_TEX_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_TX_CHROMA_KEY_0, last_hw_tmu + 1); + r600->hw.tex.border_color.cmd[R600_TEX_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_TX_BORDER_COLOR_0, last_hw_tmu + 1); if (!fp) /* should only happenen once, just after context is created */ return; - if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) { + if (r600->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) { if (fp->mesa_program.UsesKill && last_hw_tmu < 0) { // The KILL operation requires the first texture unit // to be enabled. - r300->hw.txe.cmd[R300_TXE_ENABLE] |= 1; - r300->hw.tex.filter.cmd[R300_TEX_VALUE_0] = 0; - r300->hw.tex.filter.cmd[R300_TEX_CMD_0] = - cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 1); + r600->hw.txe.cmd[R600_TXE_ENABLE] |= 1; + r600->hw.tex.filter.cmd[R600_TEX_VALUE_0] = 0; + r600->hw.tex.filter.cmd[R600_TEX_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_TX_FILTER0_0, 1); } - r300SetupFragmentShaderTextures(ctx, tmu_mappings); + r600SetupFragmentShaderTextures(ctx, tmu_mappings); } else r500SetupFragmentShaderTextures(ctx, tmu_mappings); if (RADEON_DEBUG & DEBUG_STATE) fprintf(stderr, "TX_ENABLE: %08x last_hw_tmu=%d\n", - r300->hw.txe.cmd[R300_TXE_ENABLE], last_hw_tmu); + r600->hw.txe.cmd[R600_TXE_ENABLE], last_hw_tmu); } -union r300_outputs_written { +union r600_outputs_written { GLuint vp_outputs; /* hw_tcl_on */ DECLARE_RENDERINPUTS(index_bitset); /* !hw_tcl_on */ }; -#define R300_OUTPUTS_WRITTEN_TEST(ow, vp_result, tnl_attrib) \ +#define R600_OUTPUTS_WRITTEN_TEST(ow, vp_result, tnl_attrib) \ ((hw_tcl_on) ? (ow).vp_outputs & (1 << (vp_result)) : \ RENDERINPUTS_TEST( (ow.index_bitset), (tnl_attrib) )) -static void r300SetupRSUnit(GLcontext * ctx) +static void r600SetupRSUnit(GLcontext * ctx) { - r300ContextPtr r300 = R300_CONTEXT(ctx); + r600ContextPtr r600 = R600_CONTEXT(ctx); TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *VB = &tnl->vb; - union r300_outputs_written OutputsWritten; + union r600_outputs_written OutputsWritten; GLuint InputsRead; int fp_reg, high_rr; int col_ip, tex_ip; @@ -1433,7 +1433,7 @@ static void r300SetupRSUnit(GLcontext * ctx) if (hw_tcl_on) OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten; else - RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->state.render_inputs_bitset); + RENDERINPUTS_COPY(OutputsWritten.index_bitset, r600->state.render_inputs_bitset); if (ctx->FragmentProgram._Current) InputsRead = ctx->FragmentProgram._Current->Base.InputsRead; @@ -1442,33 +1442,33 @@ static void r300SetupRSUnit(GLcontext * ctx) return; /* This should only ever happen once.. */ } - R300_STATECHANGE(r300, ri); - R300_STATECHANGE(r300, rc); - R300_STATECHANGE(r300, rr); + R600_STATECHANGE(r600, ri); + R600_STATECHANGE(r600, rc); + R600_STATECHANGE(r600, rr); fp_reg = col_ip = tex_ip = col_fmt = 0; - r300->hw.rc.cmd[1] = 0; - r300->hw.rc.cmd[2] = 0; - for (i=0; ihw.rr.cmd[R300_RR_INST_0 + i] = 0; + r600->hw.rc.cmd[1] = 0; + r600->hw.rc.cmd[2] = 0; + for (i=0; ihw.rr.cmd[R600_RR_INST_0 + i] = 0; - for (i=0; ihw.ri.cmd[R300_RI_INTERP_0 + i] = 0; + for (i=0; ihw.ri.cmd[R600_RI_INTERP_0 + i] = 0; if (InputsRead & FRAG_BIT_COL0) { - if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) { + if (R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) { count = VB->AttribPtr[_TNL_ATTRIB_COLOR0]->size; if (count == 4) - col_fmt = R300_RS_COL_FMT_RGBA; + col_fmt = R600_RS_COL_FMT_RGBA; else if (count == 3) - col_fmt = R300_RS_COL_FMT_RGB1; + col_fmt = R600_RS_COL_FMT_RGB1; else - col_fmt = R300_RS_COL_FMT_0001; + col_fmt = R600_RS_COL_FMT_0001; - r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R300_RS_COL_PTR(col_ip) | R300_RS_COL_FMT(col_fmt); - r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R300_RS_INST_COL_ID(col_ip) | R300_RS_INST_COL_CN_WRITE | R300_RS_INST_COL_ADDR(fp_reg); + r600->hw.ri.cmd[R600_RI_INTERP_0 + col_ip] = R600_RS_COL_PTR(col_ip) | R600_RS_COL_FMT(col_fmt); + r600->hw.rr.cmd[R600_RR_INST_0 + col_ip] = R600_RS_INST_COL_ID(col_ip) | R600_RS_INST_COL_CN_WRITE | R600_RS_INST_COL_ADDR(fp_reg); InputsRead &= ~FRAG_BIT_COL0; ++col_ip; ++fp_reg; @@ -1478,17 +1478,17 @@ static void r300SetupRSUnit(GLcontext * ctx) } if (InputsRead & FRAG_BIT_COL1) { - if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) { + if (R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) { count = VB->AttribPtr[_TNL_ATTRIB_COLOR1]->size; if (count == 4) - col_fmt = R300_RS_COL_FMT_RGBA; + col_fmt = R600_RS_COL_FMT_RGBA; else if (count == 3) - col_fmt = R300_RS_COL_FMT_RGB1; + col_fmt = R600_RS_COL_FMT_RGB1; else - col_fmt = R300_RS_COL_FMT_0001; + col_fmt = R600_RS_COL_FMT_0001; - r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R300_RS_COL_PTR(col_ip) | R300_RS_COL_FMT(col_fmt); - r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R300_RS_INST_COL_ID(col_ip) | R300_RS_INST_COL_CN_WRITE | R300_RS_INST_COL_ADDR(fp_reg); + r600->hw.ri.cmd[R600_RI_INTERP_0 + col_ip] = R600_RS_COL_PTR(col_ip) | R600_RS_COL_FMT(col_fmt); + r600->hw.rr.cmd[R600_RR_INST_0 + col_ip] = R600_RS_INST_COL_ID(col_ip) | R600_RS_INST_COL_CN_WRITE | R600_RS_INST_COL_ADDR(fp_reg); InputsRead &= ~FRAG_BIT_COL1; ++col_ip; ++fp_reg; @@ -1501,7 +1501,7 @@ static void r300SetupRSUnit(GLcontext * ctx) if (! ( InputsRead & FRAG_BIT_TEX(i) ) ) continue; - if (!R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) { + if (!R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) { WARN_ONCE("fragprog wants coords for tex%d, vp doesn't provide them!\n", i); continue; } @@ -1515,15 +1515,15 @@ static void r300SetupRSUnit(GLcontext * ctx) count = VB->AttribPtr[_TNL_ATTRIB_TEX(i)]->size; switch(count) { - case 4: swiz = R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3); break; - case 3: swiz = R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(R300_RS_SEL_K1); break; + case 4: swiz = R600_RS_SEL_S(0) | R600_RS_SEL_T(1) | R600_RS_SEL_R(2) | R600_RS_SEL_Q(3); break; + case 3: swiz = R600_RS_SEL_S(0) | R600_RS_SEL_T(1) | R600_RS_SEL_R(2) | R600_RS_SEL_Q(R600_RS_SEL_K1); break; default: case 1: - case 2: swiz = R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(R300_RS_SEL_K0) | R300_RS_SEL_Q(R300_RS_SEL_K1); break; + case 2: swiz = R600_RS_SEL_S(0) | R600_RS_SEL_T(1) | R600_RS_SEL_R(R600_RS_SEL_K0) | R600_RS_SEL_Q(R600_RS_SEL_K1); break; }; - r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= swiz | R300_RS_TEX_PTR(rs_tex_count); - r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R300_RS_INST_TEX_ID(tex_ip) | R300_RS_INST_TEX_CN_WRITE | R300_RS_INST_TEX_ADDR(fp_reg); + r600->hw.ri.cmd[R600_RI_INTERP_0 + tex_ip] |= swiz | R600_RS_TEX_PTR(rs_tex_count); + r600->hw.rr.cmd[R600_RR_INST_0 + tex_ip] |= R600_RS_INST_TEX_ID(tex_ip) | R600_RS_INST_TEX_CN_WRITE | R600_RS_INST_TEX_ADDR(fp_reg); InputsRead &= ~(FRAG_BIT_TEX0 << i); rs_tex_count += count; ++tex_ip; @@ -1531,9 +1531,9 @@ static void r300SetupRSUnit(GLcontext * ctx) } if (InputsRead & FRAG_BIT_FOGC) { - if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_FOGC, _TNL_ATTRIB_FOG)) { - r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3) | R300_RS_TEX_PTR(rs_tex_count); - r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R300_RS_INST_TEX_ID(tex_ip) | R300_RS_INST_TEX_CN_WRITE | R300_RS_INST_TEX_ADDR(fp_reg); + if (R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_FOGC, _TNL_ATTRIB_FOG)) { + r600->hw.ri.cmd[R600_RI_INTERP_0 + tex_ip] |= R600_RS_SEL_S(0) | R600_RS_SEL_T(1) | R600_RS_SEL_R(2) | R600_RS_SEL_Q(3) | R600_RS_TEX_PTR(rs_tex_count); + r600->hw.rr.cmd[R600_RR_INST_0 + tex_ip] |= R600_RS_INST_TEX_ID(tex_ip) | R600_RS_INST_TEX_CN_WRITE | R600_RS_INST_TEX_ADDR(fp_reg); InputsRead &= ~FRAG_BIT_FOGC; rs_tex_count += 4; ++tex_ip; @@ -1544,8 +1544,8 @@ static void r300SetupRSUnit(GLcontext * ctx) } if (InputsRead & FRAG_BIT_WPOS) { - r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= R300_RS_SEL_S(0) | R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3) | R300_RS_TEX_PTR(rs_tex_count); - r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R300_RS_INST_TEX_ID(tex_ip) | R300_RS_INST_TEX_CN_WRITE | R300_RS_INST_TEX_ADDR(fp_reg); + r600->hw.ri.cmd[R600_RI_INTERP_0 + tex_ip] |= R600_RS_SEL_S(0) | R600_RS_SEL_T(1) | R600_RS_SEL_R(2) | R600_RS_SEL_Q(3) | R600_RS_TEX_PTR(rs_tex_count); + r600->hw.rr.cmd[R600_RR_INST_0 + tex_ip] |= R600_RS_INST_TEX_ID(tex_ip) | R600_RS_INST_TEX_CN_WRITE | R600_RS_INST_TEX_ADDR(fp_reg); InputsRead &= ~FRAG_BIT_WPOS; rs_tex_count += 4; ++tex_ip; @@ -1555,15 +1555,15 @@ static void r300SetupRSUnit(GLcontext * ctx) /* Setup default color if no color or tex was set */ if (rs_tex_count == 0 && col_ip == 0) { - r300->hw.rr.cmd[R300_RR_INST_0] = R300_RS_INST_COL_ID(0) | R300_RS_INST_COL_CN_WRITE | R300_RS_INST_COL_ADDR(0) | R300_RS_COL_FMT(R300_RS_COL_FMT_0001); + r600->hw.rr.cmd[R600_RR_INST_0] = R600_RS_INST_COL_ID(0) | R600_RS_INST_COL_CN_WRITE | R600_RS_INST_COL_ADDR(0) | R600_RS_COL_FMT(R600_RS_COL_FMT_0001); ++col_ip; } high_rr = (col_ip > tex_ip) ? col_ip : tex_ip; - r300->hw.rc.cmd[1] |= (rs_tex_count << R300_IT_COUNT_SHIFT) | (col_ip << R300_IC_COUNT_SHIFT) | R300_HIRES_EN; - r300->hw.rc.cmd[2] |= high_rr - 1; + r600->hw.rc.cmd[1] |= (rs_tex_count << R600_IT_COUNT_SHIFT) | (col_ip << R600_IC_COUNT_SHIFT) | R600_HIRES_EN; + r600->hw.rc.cmd[2] |= high_rr - 1; - r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, high_rr); + r600->hw.rr.cmd[R600_RR_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_INST_0, high_rr); if (InputsRead) WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead); @@ -1571,10 +1571,10 @@ static void r300SetupRSUnit(GLcontext * ctx) static void r500SetupRSUnit(GLcontext * ctx) { - r300ContextPtr r300 = R300_CONTEXT(ctx); + r600ContextPtr r600 = R600_CONTEXT(ctx); TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *VB = &tnl->vb; - union r300_outputs_written OutputsWritten; + union r600_outputs_written OutputsWritten; GLuint InputsRead; int fp_reg, high_rr; int col_ip, tex_ip; @@ -1584,7 +1584,7 @@ static void r500SetupRSUnit(GLcontext * ctx) if (hw_tcl_on) OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten; else - RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->state.render_inputs_bitset); + RENDERINPUTS_COPY(OutputsWritten.index_bitset, r600->state.render_inputs_bitset); if (ctx->FragmentProgram._Current) InputsRead = ctx->FragmentProgram._Current->Base.InputsRead; @@ -1593,33 +1593,33 @@ static void r500SetupRSUnit(GLcontext * ctx) return; /* This should only ever happen once.. */ } - R300_STATECHANGE(r300, ri); - R300_STATECHANGE(r300, rc); - R300_STATECHANGE(r300, rr); + R600_STATECHANGE(r600, ri); + R600_STATECHANGE(r600, rc); + R600_STATECHANGE(r600, rr); fp_reg = col_ip = tex_ip = col_fmt = 0; - r300->hw.rc.cmd[1] = 0; - r300->hw.rc.cmd[2] = 0; - for (i=0; ihw.rr.cmd[R300_RR_INST_0 + i] = 0; + r600->hw.rc.cmd[1] = 0; + r600->hw.rc.cmd[2] = 0; + for (i=0; ihw.rr.cmd[R600_RR_INST_0 + i] = 0; for (i=0; ihw.ri.cmd[R300_RI_INTERP_0 + i] = 0; + r600->hw.ri.cmd[R600_RI_INTERP_0 + i] = 0; if (InputsRead & FRAG_BIT_COL0) { - if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) { + if (R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) { count = VB->AttribPtr[_TNL_ATTRIB_COLOR0]->size; if (count == 4) - col_fmt = R300_RS_COL_FMT_RGBA; + col_fmt = R600_RS_COL_FMT_RGBA; else if (count == 3) - col_fmt = R300_RS_COL_FMT_RGB1; + col_fmt = R600_RS_COL_FMT_RGB1; else - col_fmt = R300_RS_COL_FMT_0001; + col_fmt = R600_RS_COL_FMT_0001; - r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(col_fmt); - r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R500_RS_INST_COL_ID(col_ip) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(fp_reg); + r600->hw.ri.cmd[R600_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(col_fmt); + r600->hw.rr.cmd[R600_RR_INST_0 + col_ip] = R500_RS_INST_COL_ID(col_ip) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(fp_reg); InputsRead &= ~FRAG_BIT_COL0; ++col_ip; ++fp_reg; @@ -1629,17 +1629,17 @@ static void r500SetupRSUnit(GLcontext * ctx) } if (InputsRead & FRAG_BIT_COL1) { - if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) { + if (R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) { count = VB->AttribPtr[_TNL_ATTRIB_COLOR1]->size; if (count == 4) - col_fmt = R300_RS_COL_FMT_RGBA; + col_fmt = R600_RS_COL_FMT_RGBA; else if (count == 3) - col_fmt = R300_RS_COL_FMT_RGB1; + col_fmt = R600_RS_COL_FMT_RGB1; else - col_fmt = R300_RS_COL_FMT_0001; + col_fmt = R600_RS_COL_FMT_0001; - r300->hw.ri.cmd[R300_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(col_fmt); - r300->hw.rr.cmd[R300_RR_INST_0 + col_ip] = R500_RS_INST_COL_ID(col_ip) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(fp_reg); + r600->hw.ri.cmd[R600_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(col_fmt); + r600->hw.rr.cmd[R600_RR_INST_0 + col_ip] = R500_RS_INST_COL_ID(col_ip) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(fp_reg); InputsRead &= ~FRAG_BIT_COL1; ++col_ip; ++fp_reg; @@ -1653,7 +1653,7 @@ static void r500SetupRSUnit(GLcontext * ctx) if (! ( InputsRead & FRAG_BIT_TEX(i) ) ) continue; - if (!R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) { + if (!R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) { WARN_ONCE("fragprog wants coords for tex%d, vp doesn't provide them!\n", i); continue; } @@ -1693,8 +1693,8 @@ static void r500SetupRSUnit(GLcontext * ctx) swiz |= R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT; } - r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= swiz; - r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg); + r600->hw.ri.cmd[R600_RI_INTERP_0 + tex_ip] |= swiz; + r600->hw.rr.cmd[R600_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg); InputsRead &= ~(FRAG_BIT_TEX0 << i); rs_tex_count += count; ++tex_ip; @@ -1702,13 +1702,13 @@ static void r500SetupRSUnit(GLcontext * ctx) } if (InputsRead & FRAG_BIT_FOGC) { - if (R300_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_FOGC, _TNL_ATTRIB_FOG)) { - r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= ((rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT) | + if (R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_FOGC, _TNL_ATTRIB_FOG)) { + r600->hw.ri.cmd[R600_RI_INTERP_0 + tex_ip] |= ((rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT) | ((rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT) | ((rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT) | ((rs_tex_count + 3) << R500_RS_IP_TEX_PTR_Q_SHIFT); - r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg); + r600->hw.rr.cmd[R600_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg); InputsRead &= ~FRAG_BIT_FOGC; rs_tex_count += 4; ++tex_ip; @@ -1719,12 +1719,12 @@ static void r500SetupRSUnit(GLcontext * ctx) } if (InputsRead & FRAG_BIT_WPOS) { - r300->hw.ri.cmd[R300_RI_INTERP_0 + tex_ip] |= ((rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT) | + r600->hw.ri.cmd[R600_RI_INTERP_0 + tex_ip] |= ((rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT) | ((rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT) | ((rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT) | ((rs_tex_count + 3) << R500_RS_IP_TEX_PTR_Q_SHIFT); - r300->hw.rr.cmd[R300_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg); + r600->hw.rr.cmd[R600_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg); InputsRead &= ~FRAG_BIT_WPOS; rs_tex_count += 4; ++tex_ip; @@ -1733,15 +1733,15 @@ static void r500SetupRSUnit(GLcontext * ctx) /* Setup default color if no color or tex was set */ if (rs_tex_count == 0 && col_ip == 0) { - r300->hw.rr.cmd[R300_RR_INST_0] |= R500_RS_INST_COL_ID(0) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(0) | R500_RS_COL_FMT(R300_RS_COL_FMT_0001); + r600->hw.rr.cmd[R600_RR_INST_0] |= R500_RS_INST_COL_ID(0) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(0) | R500_RS_COL_FMT(R600_RS_COL_FMT_0001); ++col_ip; } high_rr = (col_ip > tex_ip) ? col_ip : tex_ip; - r300->hw.rc.cmd[1] |= (rs_tex_count << R300_IT_COUNT_SHIFT) | (col_ip << R300_IC_COUNT_SHIFT) | R300_HIRES_EN; - r300->hw.rc.cmd[2] |= 0xC0 | (high_rr - 1); + r600->hw.rc.cmd[1] |= (rs_tex_count << R600_IT_COUNT_SHIFT) | (col_ip << R600_IC_COUNT_SHIFT) | R600_HIRES_EN; + r600->hw.rc.cmd[2] |= 0xC0 | (high_rr - 1); - r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, high_rr); + r600->hw.rr.cmd[R600_RR_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R500_RS_INST_0, high_rr); if (InputsRead) WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead); @@ -1757,7 +1757,7 @@ static void r500SetupRSUnit(GLcontext * ctx) if(_nc>_p->vpu.count)_p->vpu.count=_nc;\ }while(0) -static INLINE void r300SetupVertexProgramFragment(r300ContextPtr r300, int dest, struct r300_vertex_shader_fragment *vsf) +static INLINE void r600SetupVertexProgramFragment(r600ContextPtr r600, int dest, struct r600_vertex_shader_fragment *vsf) { int i; @@ -1771,23 +1771,23 @@ static INLINE void r300SetupVertexProgramFragment(r300ContextPtr r300, int dest, switch ((dest >> 8) & 0xf) { case 0: - R300_STATECHANGE(r300, vpi); + R600_STATECHANGE(r600, vpi); for (i = 0; i < vsf->length; i++) - r300->hw.vpi.cmd[R300_VPI_INSTR_0 + i + 4 * (dest & 0xff)] = (vsf->body.d[i]); - bump_vpu_count(r300->hw.vpi.cmd, vsf->length + 4 * (dest & 0xff)); + r600->hw.vpi.cmd[R600_VPI_INSTR_0 + i + 4 * (dest & 0xff)] = (vsf->body.d[i]); + bump_vpu_count(r600->hw.vpi.cmd, vsf->length + 4 * (dest & 0xff)); break; case 2: - R300_STATECHANGE(r300, vpp); + R600_STATECHANGE(r600, vpp); for (i = 0; i < vsf->length; i++) - r300->hw.vpp.cmd[R300_VPP_PARAM_0 + i + 4 * (dest & 0xff)] = (vsf->body.d[i]); - bump_vpu_count(r300->hw.vpp.cmd, vsf->length + 4 * (dest & 0xff)); + r600->hw.vpp.cmd[R600_VPP_PARAM_0 + i + 4 * (dest & 0xff)] = (vsf->body.d[i]); + bump_vpu_count(r600->hw.vpp.cmd, vsf->length + 4 * (dest & 0xff)); break; case 4: - R300_STATECHANGE(r300, vps); + R600_STATECHANGE(r600, vps); for (i = 0; i < vsf->length; i++) - r300->hw.vps.cmd[1 + i + 4 * (dest & 0xff)] = (vsf->body.d[i]); - bump_vpu_count(r300->hw.vps.cmd, vsf->length + 4 * (dest & 0xff)); + r600->hw.vps.cmd[1 + i + 4 * (dest & 0xff)] = (vsf->body.d[i]); + bump_vpu_count(r600->hw.vps.cmd, vsf->length + 4 * (dest & 0xff)); break; default: fprintf(stderr, "%s:%s don't know how to handle dest %04x\n", __FILE__, __FUNCTION__, dest); @@ -1798,7 +1798,7 @@ static INLINE void r300SetupVertexProgramFragment(r300ContextPtr r300, int dest, #define MIN3(a, b, c) ((a) < (b) ? MIN2(a, c) : MIN2(b, c)) -static void r300VapCntl(r300ContextPtr rmesa, GLuint input_count, +static void r600VapCntl(r600ContextPtr rmesa, GLuint input_count, GLuint output_count, GLuint temp_count) { int vtx_mem_size; @@ -1821,40 +1821,40 @@ static void r300VapCntl(r300ContextPtr rmesa, GLuint input_count, pvs_num_slots = MIN3(10, vtx_mem_size/input_count, vtx_mem_size/output_count); pvs_num_cntrls = MIN2(6, vtx_mem_size/temp_count); - R300_STATECHANGE(rmesa, vap_cntl); + R600_STATECHANGE(rmesa, vap_cntl); if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { - rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] = - (pvs_num_slots << R300_PVS_NUM_SLOTS_SHIFT) | - (pvs_num_cntrls << R300_PVS_NUM_CNTLRS_SHIFT) | - (12 << R300_VF_MAX_VTX_NUM_SHIFT); + rmesa->hw.vap_cntl.cmd[R600_VAP_CNTL_INSTR] = + (pvs_num_slots << R600_PVS_NUM_SLOTS_SHIFT) | + (pvs_num_cntrls << R600_PVS_NUM_CNTLRS_SHIFT) | + (12 << R600_VF_MAX_VTX_NUM_SHIFT); if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) - rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= R500_TCL_STATE_OPTIMIZATION; + rmesa->hw.vap_cntl.cmd[R600_VAP_CNTL_INSTR] |= R500_TCL_STATE_OPTIMIZATION; } else /* not sure about non-tcl */ - rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | - (5 << R300_PVS_NUM_CNTLRS_SHIFT) | - (5 << R300_VF_MAX_VTX_NUM_SHIFT)); + rmesa->hw.vap_cntl.cmd[R600_VAP_CNTL_INSTR] = ((10 << R600_PVS_NUM_SLOTS_SHIFT) | + (5 << R600_PVS_NUM_CNTLRS_SHIFT) | + (5 << R600_VF_MAX_VTX_NUM_SHIFT)); if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515) - rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (2 << R300_PVS_NUM_FPUS_SHIFT); + rmesa->hw.vap_cntl.cmd[R600_VAP_CNTL_INSTR] |= (2 << R600_PVS_NUM_FPUS_SHIFT); else if ((rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) || (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560) || (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570)) - rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (5 << R300_PVS_NUM_FPUS_SHIFT); + rmesa->hw.vap_cntl.cmd[R600_VAP_CNTL_INSTR] |= (5 << R600_PVS_NUM_FPUS_SHIFT); else if ((rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) || (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420)) - rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (6 << R300_PVS_NUM_FPUS_SHIFT); + rmesa->hw.vap_cntl.cmd[R600_VAP_CNTL_INSTR] |= (6 << R600_PVS_NUM_FPUS_SHIFT); else if ((rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) || (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580)) - rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (8 << R300_PVS_NUM_FPUS_SHIFT); + rmesa->hw.vap_cntl.cmd[R600_VAP_CNTL_INSTR] |= (8 << R600_PVS_NUM_FPUS_SHIFT); else - rmesa->hw.vap_cntl.cmd[R300_VAP_CNTL_INSTR] |= (4 << R300_PVS_NUM_FPUS_SHIFT); + rmesa->hw.vap_cntl.cmd[R600_VAP_CNTL_INSTR] |= (4 << R600_PVS_NUM_FPUS_SHIFT); } -static void r300SetupDefaultVertexProgram(r300ContextPtr rmesa) +static void r600SetupDefaultVertexProgram(r600ContextPtr rmesa) { - struct r300_vertex_shader_state *prog = &(rmesa->state.vertex_shader); + struct r600_vertex_shader_state *prog = &(rmesa->state.vertex_shader); GLuint o_reg = 0; GLuint i_reg = 0; int i; @@ -1875,22 +1875,22 @@ static void r300SetupDefaultVertexProgram(r300ContextPtr rmesa) prog->program.length = program_end; - r300SetupVertexProgramFragment(rmesa, R300_PVS_CODE_START, + r600SetupVertexProgramFragment(rmesa, R600_PVS_CODE_START, &(prog->program)); inst_count = (prog->program.length / 4) - 1; - r300VapCntl(rmesa, i_reg, o_reg, 0); + r600VapCntl(rmesa, i_reg, o_reg, 0); - R300_STATECHANGE(rmesa, pvs); - rmesa->hw.pvs.cmd[R300_PVS_CNTL_1] = - (0 << R300_PVS_FIRST_INST_SHIFT) | - (inst_count << R300_PVS_XYZW_VALID_INST_SHIFT) | - (inst_count << R300_PVS_LAST_INST_SHIFT); - rmesa->hw.pvs.cmd[R300_PVS_CNTL_2] = - (0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) | - (param_count << R300_PVS_MAX_CONST_ADDR_SHIFT); - rmesa->hw.pvs.cmd[R300_PVS_CNTL_3] = - (inst_count << R300_PVS_LAST_VTX_SRC_INST_SHIFT); + R600_STATECHANGE(rmesa, pvs); + rmesa->hw.pvs.cmd[R600_PVS_CNTL_1] = + (0 << R600_PVS_FIRST_INST_SHIFT) | + (inst_count << R600_PVS_XYZW_VALID_INST_SHIFT) | + (inst_count << R600_PVS_LAST_INST_SHIFT); + rmesa->hw.pvs.cmd[R600_PVS_CNTL_2] = + (0 << R600_PVS_CONST_BASE_OFFSET_SHIFT) | + (param_count << R600_PVS_MAX_CONST_ADDR_SHIFT); + rmesa->hw.pvs.cmd[R600_PVS_CNTL_3] = + (inst_count << R600_PVS_LAST_VTX_SRC_INST_SHIFT); } static int bit_count (int x) @@ -1902,44 +1902,44 @@ static int bit_count (int x) return (x >> 8) + (x & 0x00ff); } -static void r300SetupRealVertexProgram(r300ContextPtr rmesa) +static void r600SetupRealVertexProgram(r600ContextPtr rmesa) { GLcontext *ctx = rmesa->radeon.glCtx; - struct r300_vertex_program *prog = (struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx); + struct r600_vertex_program *prog = (struct r600_vertex_program *)CURRENT_VERTEX_SHADER(ctx); int inst_count = 0; int param_count = 0; - /* FIXME: r300SetupVertexProgramFragment */ - R300_STATECHANGE(rmesa, vpp); + /* FIXME: r600SetupVertexProgramFragment */ + R600_STATECHANGE(rmesa, vpp); param_count = - r300VertexProgUpdateParams(ctx, - (struct r300_vertex_program_cont *) + r600VertexProgUpdateParams(ctx, + (struct r600_vertex_program_cont *) ctx->VertexProgram._Current, (float *)&rmesa->hw.vpp. - cmd[R300_VPP_PARAM_0]); + cmd[R600_VPP_PARAM_0]); bump_vpu_count(rmesa->hw.vpp.cmd, param_count); param_count /= 4; - r300SetupVertexProgramFragment(rmesa, R300_PVS_CODE_START, &(prog->program)); + r600SetupVertexProgramFragment(rmesa, R600_PVS_CODE_START, &(prog->program)); inst_count = (prog->program.length / 4) - 1; - r300VapCntl(rmesa, bit_count(prog->key.InputsRead), + r600VapCntl(rmesa, bit_count(prog->key.InputsRead), bit_count(prog->key.OutputsWritten), prog->num_temporaries); - R300_STATECHANGE(rmesa, pvs); - rmesa->hw.pvs.cmd[R300_PVS_CNTL_1] = - (0 << R300_PVS_FIRST_INST_SHIFT) | - (inst_count << R300_PVS_XYZW_VALID_INST_SHIFT) | - (inst_count << R300_PVS_LAST_INST_SHIFT); - rmesa->hw.pvs.cmd[R300_PVS_CNTL_2] = - (0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) | - (param_count << R300_PVS_MAX_CONST_ADDR_SHIFT); - rmesa->hw.pvs.cmd[R300_PVS_CNTL_3] = - (inst_count << R300_PVS_LAST_VTX_SRC_INST_SHIFT); + R600_STATECHANGE(rmesa, pvs); + rmesa->hw.pvs.cmd[R600_PVS_CNTL_1] = + (0 << R600_PVS_FIRST_INST_SHIFT) | + (inst_count << R600_PVS_XYZW_VALID_INST_SHIFT) | + (inst_count << R600_PVS_LAST_INST_SHIFT); + rmesa->hw.pvs.cmd[R600_PVS_CNTL_2] = + (0 << R600_PVS_CONST_BASE_OFFSET_SHIFT) | + (param_count << R600_PVS_MAX_CONST_ADDR_SHIFT); + rmesa->hw.pvs.cmd[R600_PVS_CNTL_3] = + (inst_count << R600_PVS_LAST_VTX_SRC_INST_SHIFT); } -static void r300SetupVertexProgram(r300ContextPtr rmesa) +static void r600SetupVertexProgram(r600ContextPtr rmesa) { GLcontext *ctx = rmesa->radeon.glCtx; @@ -1952,11 +1952,11 @@ static void r300SetupVertexProgram(r300ContextPtr rmesa) 0x400 area might have something to do with pixel shaders as it appears right after pfs programming. 0x406 is set to { 0.0, 0.0, 1.0, 0.0 } most of the time but should change with smooth points and in other rare cases. */ //setup_vertex_shader_fragment(rmesa, 0x406, &unk4); - if (hw_tcl_on && ((struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx))->translated) { - r300SetupRealVertexProgram(rmesa); + if (hw_tcl_on && ((struct r600_vertex_program *)CURRENT_VERTEX_SHADER(ctx))->translated) { + r600SetupRealVertexProgram(rmesa); } else { /* FIXME: This needs to be replaced by vertex shader generation code. */ - r300SetupDefaultVertexProgram(rmesa); + r600SetupDefaultVertexProgram(rmesa); } } @@ -1966,9 +1966,9 @@ static void r300SetupVertexProgram(r300ContextPtr rmesa) * * \note Mesa already filters redundant calls to this function. */ -static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) +static void r600Enable(GLcontext * ctx, GLenum cap, GLboolean state) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); if (RADEON_DEBUG & DEBUG_STATE) fprintf(stderr, "%s( %s = %s )\n", __FUNCTION__, _mesa_lookup_enum_by_nr(cap), @@ -1984,13 +1984,13 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) /* empty */ break; case GL_ALPHA_TEST: - r300SetAlphaState(ctx); + r600SetAlphaState(ctx); break; case GL_COLOR_LOGIC_OP: - r300SetLogicOpState(ctx); + r600SetLogicOpState(ctx); /* fall-through, because logic op overrides blending */ case GL_BLEND: - r300SetBlendState(ctx); + r600SetBlendState(ctx); break; case GL_CLIP_PLANE0: case GL_CLIP_PLANE1: @@ -1998,21 +1998,21 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) case GL_CLIP_PLANE3: case GL_CLIP_PLANE4: case GL_CLIP_PLANE5: - r300SetClipPlaneState(ctx, cap, state); + r600SetClipPlaneState(ctx, cap, state); break; case GL_DEPTH_TEST: - r300SetDepthState(ctx); + r600SetDepthState(ctx); break; case GL_STENCIL_TEST: - r300SetStencilState(ctx, state); + r600SetStencilState(ctx, state); break; case GL_CULL_FACE: - r300UpdateCulling(ctx); + r600UpdateCulling(ctx); break; case GL_POLYGON_OFFSET_POINT: case GL_POLYGON_OFFSET_LINE: case GL_POLYGON_OFFSET_FILL: - r300SetPolygonOffsetState(ctx, state); + r600SetPolygonOffsetState(ctx, state); break; case GL_SCISSOR_TEST: radeon_firevertices(&rmesa->radeon); @@ -2027,221 +2027,221 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state) /** * Completely recalculates hardware state based on the Mesa state. */ -static void r300ResetHwState(r300ContextPtr r300) +static void r600ResetHwState(r600ContextPtr r600) { - GLcontext *ctx = r300->radeon.glCtx; + GLcontext *ctx = r600->radeon.glCtx; int has_tcl = 1; - if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) + if (!(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) has_tcl = 0; if (RADEON_DEBUG & DEBUG_STATE) fprintf(stderr, "%s\n", __FUNCTION__); - radeon_firevertices(&r300->radeon); + radeon_firevertices(&r600->radeon); - r300ColorMask(ctx, + r600ColorMask(ctx, ctx->Color.ColorMask[RCOMP], ctx->Color.ColorMask[GCOMP], ctx->Color.ColorMask[BCOMP], ctx->Color.ColorMask[ACOMP]); - r300Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test); - r300DepthMask(ctx, ctx->Depth.Mask); - r300DepthFunc(ctx, ctx->Depth.Func); + r600Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test); + r600DepthMask(ctx, ctx->Depth.Mask); + r600DepthFunc(ctx, ctx->Depth.Func); /* stencil */ - r300Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled); - r300StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]); - r300StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0], + r600Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled); + r600StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]); + r600StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0], ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]); - r300StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0], + r600StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0], ctx->Stencil.ZFailFunc[0], ctx->Stencil.ZPassFunc[0]); - r300UpdateCulling(ctx); + r600UpdateCulling(ctx); - r300SetBlendState(ctx); - r300SetLogicOpState(ctx); + r600SetBlendState(ctx); + r600SetLogicOpState(ctx); - r300AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef); - r300Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled); + r600AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef); + r600Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled); - r300->hw.vte.cmd[1] = R300_VPORT_X_SCALE_ENA - | R300_VPORT_X_OFFSET_ENA - | R300_VPORT_Y_SCALE_ENA - | R300_VPORT_Y_OFFSET_ENA - | R300_VPORT_Z_SCALE_ENA - | R300_VPORT_Z_OFFSET_ENA | R300_VTX_W0_FMT; - r300->hw.vte.cmd[2] = 0x00000008; + r600->hw.vte.cmd[1] = R600_VPORT_X_SCALE_ENA + | R600_VPORT_X_OFFSET_ENA + | R600_VPORT_Y_SCALE_ENA + | R600_VPORT_Y_OFFSET_ENA + | R600_VPORT_Z_SCALE_ENA + | R600_VPORT_Z_OFFSET_ENA | R600_VTX_W0_FMT; + r600->hw.vte.cmd[2] = 0x00000008; - r300->hw.vap_vf_max_vtx_indx.cmd[1] = 0x00FFFFFF; - r300->hw.vap_vf_max_vtx_indx.cmd[2] = 0x00000000; + r600->hw.vap_vf_max_vtx_indx.cmd[1] = 0x00FFFFFF; + r600->hw.vap_vf_max_vtx_indx.cmd[2] = 0x00000000; #ifdef MESA_LITTLE_ENDIAN - r300->hw.vap_cntl_status.cmd[1] = R300_VC_NO_SWAP; + r600->hw.vap_cntl_status.cmd[1] = R600_VC_NO_SWAP; #else - r300->hw.vap_cntl_status.cmd[1] = R300_VC_32BIT_SWAP; + r600->hw.vap_cntl_status.cmd[1] = R600_VC_32BIT_SWAP; #endif /* disable VAP/TCL on non-TCL capable chips */ if (!has_tcl) - r300->hw.vap_cntl_status.cmd[1] |= R300_VAP_TCL_BYPASS; + r600->hw.vap_cntl_status.cmd[1] |= R600_VAP_TCL_BYPASS; - r300->hw.vap_psc_sgn_norm_cntl.cmd[1] = 0xAAAAAAAA; + r600->hw.vap_psc_sgn_norm_cntl.cmd[1] = 0xAAAAAAAA; /* XXX: Other families? */ if (has_tcl) { - r300->hw.vap_clip_cntl.cmd[1] = R300_PS_UCP_MODE_DIST_COP; + r600->hw.vap_clip_cntl.cmd[1] = R600_PS_UCP_MODE_DIST_COP; - r300->hw.vap_clip.cmd[1] = r300PackFloat32(1.0); /* X */ - r300->hw.vap_clip.cmd[2] = r300PackFloat32(1.0); /* X */ - r300->hw.vap_clip.cmd[3] = r300PackFloat32(1.0); /* Y */ - r300->hw.vap_clip.cmd[4] = r300PackFloat32(1.0); /* Y */ + r600->hw.vap_clip.cmd[1] = r600PackFloat32(1.0); /* X */ + r600->hw.vap_clip.cmd[2] = r600PackFloat32(1.0); /* X */ + r600->hw.vap_clip.cmd[3] = r600PackFloat32(1.0); /* Y */ + r600->hw.vap_clip.cmd[4] = r600PackFloat32(1.0); /* Y */ - switch (r300->radeon.radeonScreen->chip_family) { - case CHIP_FAMILY_R300: - r300->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R300_2288_R300; + switch (r600->radeon.radeonScreen->chip_family) { + case CHIP_FAMILY_R600: + r600->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R600_2288_R600; break; default: - r300->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R300_2288_RV350; + r600->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R600_2288_RV350; break; } } - r300->hw.gb_enable.cmd[1] = R300_GB_POINT_STUFF_ENABLE - | R300_GB_LINE_STUFF_ENABLE - | R300_GB_TRIANGLE_STUFF_ENABLE; + r600->hw.gb_enable.cmd[1] = R600_GB_POINT_STUFF_ENABLE + | R600_GB_LINE_STUFF_ENABLE + | R600_GB_TRIANGLE_STUFF_ENABLE; - r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_0] = 0x66666666; - r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_1] = 0x06666666; + r600->hw.gb_misc.cmd[R600_GB_MISC_MSPOS_0] = 0x66666666; + r600->hw.gb_misc.cmd[R600_GB_MISC_MSPOS_1] = 0x06666666; - r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] = - R300_GB_TILE_ENABLE | R300_GB_TILE_SIZE_16 /*| R300_GB_SUBPIXEL_1_16*/; - switch (r300->radeon.radeonScreen->num_gb_pipes) { + r600->hw.gb_misc.cmd[R600_GB_MISC_TILE_CONFIG] = + R600_GB_TILE_ENABLE | R600_GB_TILE_SIZE_16 /*| R600_GB_SUBPIXEL_1_16*/; + switch (r600->radeon.radeonScreen->num_gb_pipes) { case 1: default: - r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |= - R300_GB_TILE_PIPE_COUNT_RV300; + r600->hw.gb_misc.cmd[R600_GB_MISC_TILE_CONFIG] |= + R600_GB_TILE_PIPE_COUNT_RV300; break; case 2: - r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |= - R300_GB_TILE_PIPE_COUNT_R300; + r600->hw.gb_misc.cmd[R600_GB_MISC_TILE_CONFIG] |= + R600_GB_TILE_PIPE_COUNT_R600; break; case 3: - r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |= - R300_GB_TILE_PIPE_COUNT_R420_3P; + r600->hw.gb_misc.cmd[R600_GB_MISC_TILE_CONFIG] |= + R600_GB_TILE_PIPE_COUNT_R420_3P; break; case 4: - r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |= - R300_GB_TILE_PIPE_COUNT_R420; + r600->hw.gb_misc.cmd[R600_GB_MISC_TILE_CONFIG] |= + R600_GB_TILE_PIPE_COUNT_R420; break; } /* XXX: Enable anti-aliasing? */ - r300->hw.gb_misc.cmd[R300_GB_MISC_AA_CONFIG] = GB_AA_CONFIG_AA_DISABLE; - r300->hw.gb_misc.cmd[R300_GB_MISC_SELECT] = 0; + r600->hw.gb_misc.cmd[R600_GB_MISC_AA_CONFIG] = GB_AA_CONFIG_AA_DISABLE; + r600->hw.gb_misc.cmd[R600_GB_MISC_SELECT] = 0; - r300->hw.ga_point_s0.cmd[1] = r300PackFloat32(0.0); - r300->hw.ga_point_s0.cmd[2] = r300PackFloat32(0.0); - r300->hw.ga_point_s0.cmd[3] = r300PackFloat32(1.0); - r300->hw.ga_point_s0.cmd[4] = r300PackFloat32(1.0); + r600->hw.ga_point_s0.cmd[1] = r600PackFloat32(0.0); + r600->hw.ga_point_s0.cmd[2] = r600PackFloat32(0.0); + r600->hw.ga_point_s0.cmd[3] = r600PackFloat32(1.0); + r600->hw.ga_point_s0.cmd[4] = r600PackFloat32(1.0); - r300->hw.ga_triangle_stipple.cmd[1] = 0x00050005; + r600->hw.ga_triangle_stipple.cmd[1] = 0x00050005; - r300PointSize(ctx, 1.0); + r600PointSize(ctx, 1.0); - r300->hw.ga_point_minmax.cmd[1] = 0x18000006; - r300->hw.ga_point_minmax.cmd[2] = 0x00020006; - r300->hw.ga_point_minmax.cmd[3] = r300PackFloat32(1.0 / 192.0); + r600->hw.ga_point_minmax.cmd[1] = 0x18000006; + r600->hw.ga_point_minmax.cmd[2] = 0x00020006; + r600->hw.ga_point_minmax.cmd[3] = r600PackFloat32(1.0 / 192.0); - r300LineWidth(ctx, 1.0); + r600LineWidth(ctx, 1.0); - r300->hw.ga_line_stipple.cmd[1] = 0; - r300->hw.ga_line_stipple.cmd[2] = r300PackFloat32(0.0); - r300->hw.ga_line_stipple.cmd[3] = r300PackFloat32(1.0); + r600->hw.ga_line_stipple.cmd[1] = 0; + r600->hw.ga_line_stipple.cmd[2] = r600PackFloat32(0.0); + r600->hw.ga_line_stipple.cmd[3] = r600PackFloat32(1.0); - r300ShadeModel(ctx, ctx->Light.ShadeModel); + r600ShadeModel(ctx, ctx->Light.ShadeModel); - r300PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode); - r300PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode); - r300->hw.zbias_cntl.cmd[1] = 0x00000000; + r600PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode); + r600PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode); + r600->hw.zbias_cntl.cmd[1] = 0x00000000; - r300PolygonOffset(ctx, ctx->Polygon.OffsetFactor, + r600PolygonOffset(ctx, ctx->Polygon.OffsetFactor, ctx->Polygon.OffsetUnits); - r300Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint); - r300Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine); - r300Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill); + r600Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint); + r600Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine); + r600Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill); - r300->hw.su_depth_scale.cmd[1] = 0x4B7FFFFF; - r300->hw.su_depth_scale.cmd[2] = 0x00000000; + r600->hw.su_depth_scale.cmd[1] = 0x4B7FFFFF; + r600->hw.su_depth_scale.cmd[2] = 0x00000000; - r300->hw.sc_hyperz.cmd[1] = 0x0000001C; - r300->hw.sc_hyperz.cmd[2] = 0x2DA49525; + r600->hw.sc_hyperz.cmd[1] = 0x0000001C; + r600->hw.sc_hyperz.cmd[2] = 0x2DA49525; - r300->hw.sc_screendoor.cmd[1] = 0x00FFFFFF; + r600->hw.sc_screendoor.cmd[1] = 0x00FFFFFF; - r300->hw.us_out_fmt.cmd[1] = R500_OUT_FMT_C4_8 | + r600->hw.us_out_fmt.cmd[1] = R500_OUT_FMT_C4_8 | R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A; - r300->hw.us_out_fmt.cmd[2] = R500_OUT_FMT_UNUSED | + r600->hw.us_out_fmt.cmd[2] = R500_OUT_FMT_UNUSED | R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A; - r300->hw.us_out_fmt.cmd[3] = R500_OUT_FMT_UNUSED | + r600->hw.us_out_fmt.cmd[3] = R500_OUT_FMT_UNUSED | R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A; - r300->hw.us_out_fmt.cmd[4] = R500_OUT_FMT_UNUSED | + r600->hw.us_out_fmt.cmd[4] = R500_OUT_FMT_UNUSED | R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A; - r300->hw.us_out_fmt.cmd[5] = R300_W_FMT_W0 | R300_W_SRC_US; + r600->hw.us_out_fmt.cmd[5] = R600_W_FMT_W0 | R600_W_SRC_US; /* disable fog unit */ - r300->hw.fogs.cmd[R300_FOGS_STATE] = 0; - r300->hw.fg_depth_src.cmd[1] = R300_FG_DEPTH_SRC_SCAN; + r600->hw.fogs.cmd[R600_FOGS_STATE] = 0; + r600->hw.fg_depth_src.cmd[1] = R600_FG_DEPTH_SRC_SCAN; - r300->hw.rb3d_cctl.cmd[1] = 0; + r600->hw.rb3d_cctl.cmd[1] = 0; - r300BlendColor(ctx, ctx->Color.BlendColor); + r600BlendColor(ctx, ctx->Color.BlendColor); - r300->hw.rb3d_dither_ctl.cmd[1] = 0; - r300->hw.rb3d_dither_ctl.cmd[2] = 0; - r300->hw.rb3d_dither_ctl.cmd[3] = 0; - r300->hw.rb3d_dither_ctl.cmd[4] = 0; - r300->hw.rb3d_dither_ctl.cmd[5] = 0; - r300->hw.rb3d_dither_ctl.cmd[6] = 0; - r300->hw.rb3d_dither_ctl.cmd[7] = 0; - r300->hw.rb3d_dither_ctl.cmd[8] = 0; - r300->hw.rb3d_dither_ctl.cmd[9] = 0; + r600->hw.rb3d_dither_ctl.cmd[1] = 0; + r600->hw.rb3d_dither_ctl.cmd[2] = 0; + r600->hw.rb3d_dither_ctl.cmd[3] = 0; + r600->hw.rb3d_dither_ctl.cmd[4] = 0; + r600->hw.rb3d_dither_ctl.cmd[5] = 0; + r600->hw.rb3d_dither_ctl.cmd[6] = 0; + r600->hw.rb3d_dither_ctl.cmd[7] = 0; + r600->hw.rb3d_dither_ctl.cmd[8] = 0; + r600->hw.rb3d_dither_ctl.cmd[9] = 0; - r300->hw.rb3d_aaresolve_ctl.cmd[1] = 0; + r600->hw.rb3d_aaresolve_ctl.cmd[1] = 0; - r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000; - r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff; + r600->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000; + r600->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff; - r300->hw.zb_depthclearvalue.cmd[1] = 0; + r600->hw.zb_depthclearvalue.cmd[1] = 0; - r300->hw.zstencil_format.cmd[2] = R300_ZTOP_DISABLE; - r300->hw.zstencil_format.cmd[3] = 0x00000003; - r300->hw.zstencil_format.cmd[4] = 0x00000000; - r300SetEarlyZState(ctx); + r600->hw.zstencil_format.cmd[2] = R600_ZTOP_DISABLE; + r600->hw.zstencil_format.cmd[3] = 0x00000003; + r600->hw.zstencil_format.cmd[4] = 0x00000000; + r600SetEarlyZState(ctx); - r300->hw.unk4F30.cmd[1] = 0; - r300->hw.unk4F30.cmd[2] = 0; + r600->hw.unk4F30.cmd[1] = 0; + r600->hw.unk4F30.cmd[2] = 0; - r300->hw.zb_hiz_offset.cmd[1] = 0; + r600->hw.zb_hiz_offset.cmd[1] = 0; - r300->hw.zb_hiz_pitch.cmd[1] = 0; + r600->hw.zb_hiz_pitch.cmd[1] = 0; - r300VapCntl(r300, 0, 0, 0); + r600VapCntl(r600, 0, 0, 0); if (has_tcl) { - r300->hw.vps.cmd[R300_VPS_ZERO_0] = 0; - r300->hw.vps.cmd[R300_VPS_ZERO_1] = 0; - r300->hw.vps.cmd[R300_VPS_POINTSIZE] = r300PackFloat32(1.0); - r300->hw.vps.cmd[R300_VPS_ZERO_3] = 0; + r600->hw.vps.cmd[R600_VPS_ZERO_0] = 0; + r600->hw.vps.cmd[R600_VPS_ZERO_1] = 0; + r600->hw.vps.cmd[R600_VPS_POINTSIZE] = r600PackFloat32(1.0); + r600->hw.vps.cmd[R600_VPS_ZERO_3] = 0; } - r300->radeon.hw.all_dirty = GL_TRUE; + r600->radeon.hw.all_dirty = GL_TRUE; } -void r300UpdateShaders(r300ContextPtr rmesa) +void r600UpdateShaders(r600ContextPtr rmesa) { GLcontext *ctx; - struct r300_vertex_program *vp; + struct r600_vertex_program *vp; int i; ctx = rmesa->radeon.glCtx; @@ -2263,21 +2263,21 @@ void r300UpdateShaders(r300ContextPtr rmesa) rmesa->temp_attrib[i]; } - r300SelectVertexShader(rmesa); - vp = (struct r300_vertex_program *) + r600SelectVertexShader(rmesa); + vp = (struct r600_vertex_program *) CURRENT_VERTEX_SHADER(ctx); /*if (vp->translated == GL_FALSE) - r300TranslateVertexShader(vp); */ + r600TranslateVertexShader(vp); */ if (vp->translated == GL_FALSE) { fprintf(stderr, "Failing back to sw-tcl\n"); hw_tcl_on = future_hw_tcl_on = 0; - r300ResetHwState(rmesa); + r600ResetHwState(rmesa); - r300UpdateStateParameters(ctx, _NEW_PROGRAM); + r600UpdateStateParameters(ctx, _NEW_PROGRAM); return; } } - r300UpdateStateParameters(ctx, _NEW_PROGRAM); + r600UpdateStateParameters(ctx, _NEW_PROGRAM); } static const GLfloat *get_fragmentprogram_constant(GLcontext *ctx, @@ -2301,18 +2301,18 @@ static const GLfloat *get_fragmentprogram_constant(GLcontext *ctx, } -static void r300SetupPixelShader(r300ContextPtr rmesa) +static void r600SetupPixelShader(r600ContextPtr rmesa) { GLcontext *ctx = rmesa->radeon.glCtx; - struct r300_fragment_program *fp = (struct r300_fragment_program *) + struct r600_fragment_program *fp = (struct r600_fragment_program *) (char *)ctx->FragmentProgram._Current; - struct r300_fragment_program_code *code; + struct r600_fragment_program_code *code; int i, k; if (!fp) /* should only happenen once, just after context is created */ return; - r300TranslateFragmentShader(rmesa, fp); + r600TranslateFragmentShader(rmesa, fp); if (!fp->translated) { fprintf(stderr, "%s: No valid fragment shader, exiting\n", __FUNCTION__); @@ -2320,54 +2320,54 @@ static void r300SetupPixelShader(r300ContextPtr rmesa) } code = &fp->code; - r300SetupTextures(ctx); + r600SetupTextures(ctx); - R300_STATECHANGE(rmesa, fpi[0]); - R300_STATECHANGE(rmesa, fpi[1]); - R300_STATECHANGE(rmesa, fpi[2]); - R300_STATECHANGE(rmesa, fpi[3]); - rmesa->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, code->alu.length); - rmesa->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, code->alu.length); - rmesa->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, code->alu.length); - rmesa->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, code->alu.length); + R600_STATECHANGE(rmesa, fpi[0]); + R600_STATECHANGE(rmesa, fpi[1]); + R600_STATECHANGE(rmesa, fpi[2]); + R600_STATECHANGE(rmesa, fpi[3]); + rmesa->hw.fpi[0].cmd[R600_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R600_US_ALU_RGB_INST_0, code->alu.length); + rmesa->hw.fpi[1].cmd[R600_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R600_US_ALU_RGB_ADDR_0, code->alu.length); + rmesa->hw.fpi[2].cmd[R600_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R600_US_ALU_ALPHA_INST_0, code->alu.length); + rmesa->hw.fpi[3].cmd[R600_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R600_US_ALU_ALPHA_ADDR_0, code->alu.length); for (i = 0; i < code->alu.length; i++) { - rmesa->hw.fpi[0].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst0; - rmesa->hw.fpi[1].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst1; - rmesa->hw.fpi[2].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst2; - rmesa->hw.fpi[3].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst3; - } - - R300_STATECHANGE(rmesa, fp); - rmesa->hw.fp.cmd[R300_FP_CNTL0] = code->cur_node | (code->first_node_has_tex << 3); - rmesa->hw.fp.cmd[R300_FP_CNTL1] = code->max_temp_idx; - rmesa->hw.fp.cmd[R300_FP_CNTL2] = - (0 << R300_PFS_CNTL_ALU_OFFSET_SHIFT) | - ((code->alu.length-1) << R300_PFS_CNTL_ALU_END_SHIFT) | - (0 << R300_PFS_CNTL_TEX_OFFSET_SHIFT) | - ((code->tex.length ? code->tex.length-1 : 0) << R300_PFS_CNTL_TEX_END_SHIFT); + rmesa->hw.fpi[0].cmd[R600_FPI_INSTR_0 + i] = code->alu.inst[i].inst0; + rmesa->hw.fpi[1].cmd[R600_FPI_INSTR_0 + i] = code->alu.inst[i].inst1; + rmesa->hw.fpi[2].cmd[R600_FPI_INSTR_0 + i] = code->alu.inst[i].inst2; + rmesa->hw.fpi[3].cmd[R600_FPI_INSTR_0 + i] = code->alu.inst[i].inst3; + } + + R600_STATECHANGE(rmesa, fp); + rmesa->hw.fp.cmd[R600_FP_CNTL0] = code->cur_node | (code->first_node_has_tex << 3); + rmesa->hw.fp.cmd[R600_FP_CNTL1] = code->max_temp_idx; + rmesa->hw.fp.cmd[R600_FP_CNTL2] = + (0 << R600_PFS_CNTL_ALU_OFFSET_SHIFT) | + ((code->alu.length-1) << R600_PFS_CNTL_ALU_END_SHIFT) | + (0 << R600_PFS_CNTL_TEX_OFFSET_SHIFT) | + ((code->tex.length ? code->tex.length-1 : 0) << R600_PFS_CNTL_TEX_END_SHIFT); /* I just want to say, the way these nodes are stored.. weird.. */ for (i = 0, k = (4 - (code->cur_node + 1)); i < 4; i++, k++) { if (i < (code->cur_node + 1)) { - rmesa->hw.fp.cmd[R300_FP_NODE0 + k] = - (code->node[i].alu_offset << R300_ALU_START_SHIFT) | - (code->node[i].alu_end << R300_ALU_SIZE_SHIFT) | - (code->node[i].tex_offset << R300_TEX_START_SHIFT) | - (code->node[i].tex_end << R300_TEX_SIZE_SHIFT) | + rmesa->hw.fp.cmd[R600_FP_NODE0 + k] = + (code->node[i].alu_offset << R600_ALU_START_SHIFT) | + (code->node[i].alu_end << R600_ALU_SIZE_SHIFT) | + (code->node[i].tex_offset << R600_TEX_START_SHIFT) | + (code->node[i].tex_end << R600_TEX_SIZE_SHIFT) | code->node[i].flags; } else { - rmesa->hw.fp.cmd[R300_FP_NODE0 + (3 - i)] = 0; + rmesa->hw.fp.cmd[R600_FP_NODE0 + (3 - i)] = 0; } } - R300_STATECHANGE(rmesa, fpp); - rmesa->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_PFS_PARAM_0_X, code->const_nr * 4); + R600_STATECHANGE(rmesa, fpp); + rmesa->hw.fpp.cmd[R600_FPP_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R600_PFS_PARAM_0_X, code->const_nr * 4); for (i = 0; i < code->const_nr; i++) { const GLfloat *constant = get_fragmentprogram_constant(ctx, &fp->mesa_program.Base, code->constant[i]); - rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 0] = r300PackFloat24(constant[0]); - rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 1] = r300PackFloat24(constant[1]); - rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 2] = r300PackFloat24(constant[2]); - rmesa->hw.fpp.cmd[R300_FPP_PARAM_0 + 4 * i + 3] = r300PackFloat24(constant[3]); + rmesa->hw.fpp.cmd[R600_FPP_PARAM_0 + 4 * i + 0] = r600PackFloat24(constant[0]); + rmesa->hw.fpp.cmd[R600_FPP_PARAM_0 + 4 * i + 1] = r600PackFloat24(constant[1]); + rmesa->hw.fpp.cmd[R600_FPP_PARAM_0 + 4 * i + 2] = r600PackFloat24(constant[2]); + rmesa->hw.fpp.cmd[R600_FPP_PARAM_0 + 4 * i + 3] = r600PackFloat24(constant[3]); } } @@ -2385,7 +2385,7 @@ static void r300SetupPixelShader(r300ContextPtr rmesa) if(_nc>_p->r500fp.count)_p->r500fp.count=_nc;\ } while(0) -static void r500SetupPixelShader(r300ContextPtr rmesa) +static void r500SetupPixelShader(r600ContextPtr rmesa) { GLcontext *ctx = rmesa->radeon.glCtx; struct r500_fragment_program *fp = (struct r500_fragment_program *) @@ -2407,9 +2407,9 @@ static void r500SetupPixelShader(r300ContextPtr rmesa) } code = &fp->code; - r300SetupTextures(ctx); + r600SetupTextures(ctx); - R300_STATECHANGE(rmesa, fp); + R600_STATECHANGE(rmesa, fp); rmesa->hw.fp.cmd[R500_FP_PIXSIZE] = code->max_temp_idx; rmesa->hw.fp.cmd[R500_FP_CODE_ADDR] = @@ -2421,7 +2421,7 @@ static void r500SetupPixelShader(r300ContextPtr rmesa) rmesa->hw.fp.cmd[R500_FP_CODE_OFFSET] = R500_US_CODE_OFFSET_ADDR(0); /* FIXME when we add flow control */ - R300_STATECHANGE(rmesa, r500fp); + R600_STATECHANGE(rmesa, r500fp); /* Emit our shader... */ for (i = 0; i < code->inst_end+1; i++) { rmesa->hw.r500fp.cmd[i*6+1] = code->inst[i].inst0; @@ -2434,68 +2434,68 @@ static void r500SetupPixelShader(r300ContextPtr rmesa) bump_r500fp_count(rmesa->hw.r500fp.cmd, (code->inst_end + 1) * 6); - R300_STATECHANGE(rmesa, r500fp_const); + R600_STATECHANGE(rmesa, r500fp_const); for (i = 0; i < code->const_nr; i++) { const GLfloat *constant = get_fragmentprogram_constant(ctx, &fp->mesa_program.Base, code->constant[i]); - rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 0] = r300PackFloat32(constant[0]); - rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 1] = r300PackFloat32(constant[1]); - rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 2] = r300PackFloat32(constant[2]); - rmesa->hw.r500fp_const.cmd[R300_FPP_PARAM_0 + 4 * i + 3] = r300PackFloat32(constant[3]); + rmesa->hw.r500fp_const.cmd[R600_FPP_PARAM_0 + 4 * i + 0] = r600PackFloat32(constant[0]); + rmesa->hw.r500fp_const.cmd[R600_FPP_PARAM_0 + 4 * i + 1] = r600PackFloat32(constant[1]); + rmesa->hw.r500fp_const.cmd[R600_FPP_PARAM_0 + 4 * i + 2] = r600PackFloat32(constant[2]); + rmesa->hw.r500fp_const.cmd[R600_FPP_PARAM_0 + 4 * i + 3] = r600PackFloat32(constant[3]); } bump_r500fp_const_count(rmesa->hw.r500fp_const.cmd, code->const_nr * 4); } -void r300UpdateShaderStates(r300ContextPtr rmesa) +void r600UpdateShaderStates(r600ContextPtr rmesa) { GLcontext *ctx; ctx = rmesa->radeon.glCtx; - r300SetEarlyZState(ctx); + r600SetEarlyZState(ctx); /* w_fmt value is set to get best performance * see p.130 R5xx 3D acceleration guide v1.3 */ GLuint w_fmt, fgdepthsrc; if (current_fragment_program_writes_depth(ctx)) { - fgdepthsrc = R300_FG_DEPTH_SRC_SHADER; - w_fmt = R300_W_FMT_W24 | R300_W_SRC_US; + fgdepthsrc = R600_FG_DEPTH_SRC_SHADER; + w_fmt = R600_W_FMT_W24 | R600_W_SRC_US; } else { - fgdepthsrc = R300_FG_DEPTH_SRC_SCAN; - w_fmt = R300_W_FMT_W0 | R300_W_SRC_US; + fgdepthsrc = R600_FG_DEPTH_SRC_SCAN; + w_fmt = R600_W_FMT_W0 | R600_W_SRC_US; } if (w_fmt != rmesa->hw.us_out_fmt.cmd[5]) { - R300_STATECHANGE(rmesa, us_out_fmt); + R600_STATECHANGE(rmesa, us_out_fmt); rmesa->hw.us_out_fmt.cmd[5] = w_fmt; } if (fgdepthsrc != rmesa->hw.fg_depth_src.cmd[1]) { - R300_STATECHANGE(rmesa, fg_depth_src); + R600_STATECHANGE(rmesa, fg_depth_src); rmesa->hw.fg_depth_src.cmd[1] = fgdepthsrc; } if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) r500SetupPixelShader(rmesa); else - r300SetupPixelShader(rmesa); + r600SetupPixelShader(rmesa); if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) r500SetupRSUnit(ctx); else - r300SetupRSUnit(ctx); + r600SetupRSUnit(ctx); if ((rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) - r300SetupVertexProgram(rmesa); + r600SetupVertexProgram(rmesa); } /** * Called by Mesa after an internal state update. */ -static void r300InvalidateState(GLcontext * ctx, GLuint new_state) +static void r600InvalidateState(GLcontext * ctx, GLuint new_state) { - r300ContextPtr r300 = R300_CONTEXT(ctx); + r600ContextPtr r600 = R600_CONTEXT(ctx); _swrast_InvalidateState(ctx, new_state); _swsetup_InvalidateState(ctx, new_state); @@ -2508,12 +2508,12 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state) /* this updates the DrawBuffer's Width/Height if it's a FBO */ _mesa_update_draw_buffer_bounds(ctx); - R300_STATECHANGE(r300, cb); + R600_STATECHANGE(r600, cb); } - r300UpdateStateParameters(ctx, new_state); + r600UpdateStateParameters(ctx, new_state); - r300->radeon.NewGLState |= new_state; + r600->radeon.NewGLState |= new_state; } /** @@ -2521,34 +2521,34 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state) * Assumes that the command buffer and state atoms have been * initialized already. */ -void r300InitState(r300ContextPtr r300) +void r600InitState(r600ContextPtr r600) { - memset(&(r300->state.texture), 0, sizeof(r300->state.texture)); + memset(&(r600->state.texture), 0, sizeof(r600->state.texture)); - r300ResetHwState(r300); + r600ResetHwState(r600); } -static void r300RenderMode(GLcontext * ctx, GLenum mode) +static void r600RenderMode(GLcontext * ctx, GLenum mode) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); (void)rmesa; (void)mode; } -void r300UpdateClipPlanes( GLcontext *ctx ) +void r600UpdateClipPlanes( GLcontext *ctx ) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); GLuint p; for (p = 0; p < ctx->Const.MaxClipPlanes; p++) { if (ctx->Transform.ClipPlanesEnabled & (1 << p)) { GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p]; - R300_STATECHANGE( rmesa, vpucp[p] ); - rmesa->hw.vpucp[p].cmd[R300_VPUCP_X] = ip[0]; - rmesa->hw.vpucp[p].cmd[R300_VPUCP_Y] = ip[1]; - rmesa->hw.vpucp[p].cmd[R300_VPUCP_Z] = ip[2]; - rmesa->hw.vpucp[p].cmd[R300_VPUCP_W] = ip[3]; + R600_STATECHANGE( rmesa, vpucp[p] ); + rmesa->hw.vpucp[p].cmd[R600_VPUCP_X] = ip[0]; + rmesa->hw.vpucp[p].cmd[R600_VPUCP_Y] = ip[1]; + rmesa->hw.vpucp[p].cmd[R600_VPUCP_Z] = ip[2]; + rmesa->hw.vpucp[p].cmd[R600_VPUCP_W] = ip[3]; } } } @@ -2556,43 +2556,43 @@ void r300UpdateClipPlanes( GLcontext *ctx ) /** * Initialize driver's state callback functions */ -void r300InitStateFuncs(struct dd_function_table *functions) -{ - - functions->UpdateState = r300InvalidateState; - functions->AlphaFunc = r300AlphaFunc; - functions->BlendColor = r300BlendColor; - functions->BlendEquationSeparate = r300BlendEquationSeparate; - functions->BlendFuncSeparate = r300BlendFuncSeparate; - functions->Enable = r300Enable; - functions->ColorMask = r300ColorMask; - functions->DepthFunc = r300DepthFunc; - functions->DepthMask = r300DepthMask; - functions->CullFace = r300CullFace; - functions->FrontFace = r300FrontFace; - functions->ShadeModel = r300ShadeModel; - functions->LogicOpcode = r300LogicOpcode; +void r600InitStateFuncs(struct dd_function_table *functions) +{ + + functions->UpdateState = r600InvalidateState; + functions->AlphaFunc = r600AlphaFunc; + functions->BlendColor = r600BlendColor; + functions->BlendEquationSeparate = r600BlendEquationSeparate; + functions->BlendFuncSeparate = r600BlendFuncSeparate; + functions->Enable = r600Enable; + functions->ColorMask = r600ColorMask; + functions->DepthFunc = r600DepthFunc; + functions->DepthMask = r600DepthMask; + functions->CullFace = r600CullFace; + functions->FrontFace = r600FrontFace; + functions->ShadeModel = r600ShadeModel; + functions->LogicOpcode = r600LogicOpcode; /* ARB_point_parameters */ - functions->PointParameterfv = r300PointParameter; + functions->PointParameterfv = r600PointParameter; /* Stencil related */ - functions->StencilFuncSeparate = r300StencilFuncSeparate; - functions->StencilMaskSeparate = r300StencilMaskSeparate; - functions->StencilOpSeparate = r300StencilOpSeparate; + functions->StencilFuncSeparate = r600StencilFuncSeparate; + functions->StencilMaskSeparate = r600StencilMaskSeparate; + functions->StencilOpSeparate = r600StencilOpSeparate; /* Viewport related */ - functions->Viewport = r300Viewport; - functions->DepthRange = r300DepthRange; - functions->PointSize = r300PointSize; - functions->LineWidth = r300LineWidth; + functions->Viewport = r600Viewport; + functions->DepthRange = r600DepthRange; + functions->PointSize = r600PointSize; + functions->LineWidth = r600LineWidth; - functions->PolygonOffset = r300PolygonOffset; - functions->PolygonMode = r300PolygonMode; + functions->PolygonOffset = r600PolygonOffset; + functions->PolygonMode = r600PolygonMode; - functions->RenderMode = r300RenderMode; + functions->RenderMode = r600RenderMode; - functions->ClipPlane = r300ClipPlane; + functions->ClipPlane = r600ClipPlane; functions->Scissor = radeonScissor; functions->DrawBuffer = radeonDrawBuffer; diff --git a/src/mesa/drivers/dri/r600/r600_state.h b/src/mesa/drivers/dri/r600/r600_state.h index bc33da9760..2aca95ca25 100644 --- a/src/mesa/drivers/dri/r600/r600_state.h +++ b/src/mesa/drivers/dri/r600/r600_state.h @@ -37,29 +37,29 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r600_context.h" -#define R300_NEWPRIM( rmesa ) \ +#define R600_NEWPRIM( rmesa ) \ do { \ if ( rmesa->radeon.dma.flush ) \ rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \ } while (0) -#define R300_STATECHANGE(r300, atom) \ +#define R600_STATECHANGE(r600, atom) \ do { \ - R300_NEWPRIM(r300); \ - r300->hw.atom.dirty = GL_TRUE; \ - r300->radeon.hw.is_dirty = GL_TRUE; \ + R600_NEWPRIM(r600); \ + r600->hw.atom.dirty = GL_TRUE; \ + r600->radeon.hw.is_dirty = GL_TRUE; \ } while(0) -// r300_state.c +// r600_state.c extern int future_hw_tcl_on; void _tnl_UpdateFixedFunctionProgram (GLcontext * ctx); -void r300UpdateViewportOffset (GLcontext * ctx); -void r300UpdateDrawBuffer (GLcontext * ctx); -void r300UpdateStateParameters (GLcontext * ctx, GLuint new_state); -void r300UpdateShaders (r300ContextPtr rmesa); -void r300UpdateShaderStates (r300ContextPtr rmesa); -void r300InitState (r300ContextPtr r300); -void r300UpdateClipPlanes (GLcontext * ctx); -void r300InitStateFuncs (struct dd_function_table *functions); +void r600UpdateViewportOffset (GLcontext * ctx); +void r600UpdateDrawBuffer (GLcontext * ctx); +void r600UpdateStateParameters (GLcontext * ctx, GLuint new_state); +void r600UpdateShaders (r600ContextPtr rmesa); +void r600UpdateShaderStates (r600ContextPtr rmesa); +void r600InitState (r600ContextPtr r600); +void r600UpdateClipPlanes (GLcontext * ctx); +void r600InitStateFuncs (struct dd_function_table *functions); -#endif /* __R300_STATE_H__ */ +#endif /* __R600_STATE_H__ */ diff --git a/src/mesa/drivers/dri/r600/r600_swtcl.c b/src/mesa/drivers/dri/r600/r600_swtcl.c index 9c8b62465f..fdb6f78754 100644 --- a/src/mesa/drivers/dri/r600/r600_swtcl.c +++ b/src/mesa/drivers/dri/r600/r600_swtcl.c @@ -63,9 +63,9 @@ do { \ ++num_attrs; \ } while (0) -static void r300SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsWritten) +static void r600SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsWritten) { - r300ContextPtr rmesa = R300_CONTEXT( ctx ); + r600ContextPtr rmesa = R600_CONTEXT( ctx ); TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *VB = &tnl->vb; struct vertex_attribute *attrs = rmesa->swtcl.vert_attrs; @@ -74,27 +74,27 @@ static void r300SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsW uint32_t *vir0 = &rmesa->hw.vir[0].cmd[1]; uint32_t *vir1 = &rmesa->hw.vir[1].cmd[1]; - for (i = 0; i < R300_VIR_CMDSIZE-1; ++i) + for (i = 0; i < R600_VIR_CMDSIZE-1; ++i) vir0[i] = vir1[i] = 0; for (i = 0, j = 0; i < rmesa->radeon.swtcl.vertex_attr_count; ++i) { int tmp, data_format; switch (attrs[i].format) { case EMIT_1F: - data_format = R300_DATA_TYPE_FLOAT_1; + data_format = R600_DATA_TYPE_FLOAT_1; break; case EMIT_2F: - data_format = R300_DATA_TYPE_FLOAT_2; + data_format = R600_DATA_TYPE_FLOAT_2; break; case EMIT_3F: - data_format = R300_DATA_TYPE_FLOAT_3; + data_format = R600_DATA_TYPE_FLOAT_3; break; case EMIT_4F: - data_format = R300_DATA_TYPE_FLOAT_4; + data_format = R600_DATA_TYPE_FLOAT_4; break; case EMIT_4UB_4F_RGBA: case EMIT_4UB_4F_ABGR: - data_format = R300_DATA_TYPE_BYTE | R300_NORMALIZE; + data_format = R600_DATA_TYPE_BYTE | R600_NORMALIZE; break; default: fprintf(stderr, "%s: Invalid data format type", __FUNCTION__); @@ -102,29 +102,29 @@ static void r300SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsW break; } - tmp = data_format | (attrs[i].dst_loc << R300_DST_VEC_LOC_SHIFT); + tmp = data_format | (attrs[i].dst_loc << R600_DST_VEC_LOC_SHIFT); if (i % 2 == 0) { - vir0[j] = tmp << R300_DATA_TYPE_0_SHIFT; - vir1[j] = attrs[i].swizzle | (attrs[i].write_mask << R300_WRITE_ENA_SHIFT); + vir0[j] = tmp << R600_DATA_TYPE_0_SHIFT; + vir1[j] = attrs[i].swizzle | (attrs[i].write_mask << R600_WRITE_ENA_SHIFT); } else { - vir0[j] |= tmp << R300_DATA_TYPE_1_SHIFT; - vir1[j] |= (attrs[i].swizzle | (attrs[i].write_mask << R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE1_SHIFT; + vir0[j] |= tmp << R600_DATA_TYPE_1_SHIFT; + vir1[j] |= (attrs[i].swizzle | (attrs[i].write_mask << R600_WRITE_ENA_SHIFT)) << R600_SWIZZLE1_SHIFT; ++j; } } reg_count = (rmesa->radeon.swtcl.vertex_attr_count + 1) >> 1; if (rmesa->radeon.swtcl.vertex_attr_count % 2 != 0) { - vir0[reg_count-1] |= R300_LAST_VEC << R300_DATA_TYPE_0_SHIFT; + vir0[reg_count-1] |= R600_LAST_VEC << R600_DATA_TYPE_0_SHIFT; } else { - vir0[reg_count-1] |= R300_LAST_VEC << R300_DATA_TYPE_1_SHIFT; + vir0[reg_count-1] |= R600_LAST_VEC << R600_DATA_TYPE_1_SHIFT; } - R300_STATECHANGE(rmesa, vir[0]); - R300_STATECHANGE(rmesa, vir[1]); - R300_STATECHANGE(rmesa, vof); - R300_STATECHANGE(rmesa, vte); - R300_STATECHANGE(rmesa, vic); + R600_STATECHANGE(rmesa, vir[0]); + R600_STATECHANGE(rmesa, vir[1]); + R600_STATECHANGE(rmesa, vof); + R600_STATECHANGE(rmesa, vte); + R600_STATECHANGE(rmesa, vic); if (rmesa->radeon.radeonScreen->kernel_mm) { rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF; @@ -136,22 +136,22 @@ static void r300SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsW ((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = reg_count; } - rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead); - rmesa->hw.vic.cmd[R300_VIC_CNTL_1] = r300VAPInputCntl1(ctx, InputsRead); - rmesa->hw.vof.cmd[R300_VOF_CNTL_0] = r300VAPOutputCntl0(ctx, OutputsWritten); - rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = r300VAPOutputCntl1(ctx, OutputsWritten); + rmesa->hw.vic.cmd[R600_VIC_CNTL_0] = r600VAPInputCntl0(ctx, InputsRead); + rmesa->hw.vic.cmd[R600_VIC_CNTL_1] = r600VAPInputCntl1(ctx, InputsRead); + rmesa->hw.vof.cmd[R600_VOF_CNTL_0] = r600VAPOutputCntl0(ctx, OutputsWritten); + rmesa->hw.vof.cmd[R600_VOF_CNTL_1] = r600VAPOutputCntl1(ctx, OutputsWritten); vte = rmesa->hw.vte.cmd[1]; - vte &= ~(R300_VTX_XY_FMT | R300_VTX_Z_FMT | R300_VTX_W0_FMT); + vte &= ~(R600_VTX_XY_FMT | R600_VTX_Z_FMT | R600_VTX_W0_FMT); /* Important: */ if ( VB->NdcPtr != NULL ) { VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr; - vte |= R300_VTX_XY_FMT | R300_VTX_Z_FMT; + vte |= R600_VTX_XY_FMT | R600_VTX_Z_FMT; } else { VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr; - vte |= R300_VTX_W0_FMT; + vte |= R600_VTX_W0_FMT; } assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL ); @@ -161,9 +161,9 @@ static void r300SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsW } -static void r300SetVertexFormat( GLcontext *ctx ) +static void r600SetVertexFormat( GLcontext *ctx ) { - r300ContextPtr rmesa = R300_CONTEXT( ctx ); + r600ContextPtr rmesa = R600_CONTEXT( ctx ); TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *VB = &tnl->vb; int fog_id = -1; @@ -306,8 +306,8 @@ static void r300SetVertexFormat( GLcontext *ctx ) ADD_ATTR(VERT_ATTRIB_TEX0 + first_free_tex, EMIT_4F, SWTCL_OVM_TEX(first_free_tex), SWIZZLE_XYZW, MASK_XYZW); } - R300_NEWPRIM(rmesa); - r300SwtclVAPSetup(ctx, InputsRead, OutputsWritten); + R600_NEWPRIM(rmesa); + r600SwtclVAPSetup(ctx, InputsRead, OutputsWritten); rmesa->radeon.swtcl.vertex_size = _tnl_install_attrs( ctx, @@ -334,8 +334,8 @@ static GLuint reduced_prim[] = { GL_TRIANGLES, }; -static void r300RasterPrimitive( GLcontext *ctx, GLuint prim ); -static void r300RenderPrimitive( GLcontext *ctx, GLenum prim ); +static void r600RasterPrimitive( GLcontext *ctx, GLuint prim ); +static void r600RenderPrimitive( GLcontext *ctx, GLenum prim ); /*********************************************************************** * Emit primitives as inline vertices * @@ -356,16 +356,16 @@ static void r300RenderPrimitive( GLcontext *ctx, GLenum prim ); #undef LOCAL_VARS #undef ALLOC_VERTS -#define CTX_ARG r300ContextPtr rmesa +#define CTX_ARG r600ContextPtr rmesa #define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size #define ALLOC_VERTS( n, size ) rcommonAllocDmaLowVerts( &rmesa->radeon, n, size * 4 ) #define LOCAL_VARS \ - r300ContextPtr rmesa = R300_CONTEXT(ctx); \ - const char *r300verts = (char *)rmesa->radeon.swtcl.verts; -#define VERT(x) (r300Vertex *)(r300verts + ((x) * vertsize * sizeof(int))) -#define VERTEX r300Vertex + r600ContextPtr rmesa = R600_CONTEXT(ctx); \ + const char *r600verts = (char *)rmesa->radeon.swtcl.verts; +#define VERT(x) (r600Vertex *)(r600verts + ((x) * vertsize * sizeof(int))) +#define VERTEX r600Vertex #undef TAG -#define TAG(x) r300_##x +#define TAG(x) r600_##x #include "tnl_dd/t_dd_triemit.h" @@ -374,29 +374,29 @@ static void r300RenderPrimitive( GLcontext *ctx, GLenum prim ); * Macros for t_dd_tritmp.h to draw basic primitives * ***********************************************************************/ -#define QUAD( a, b, c, d ) r300_quad( rmesa, a, b, c, d ) -#define TRI( a, b, c ) r300_triangle( rmesa, a, b, c ) -#define LINE( a, b ) r300_line( rmesa, a, b ) -#define POINT( a ) r300_point( rmesa, a ) +#define QUAD( a, b, c, d ) r600_quad( rmesa, a, b, c, d ) +#define TRI( a, b, c ) r600_triangle( rmesa, a, b, c ) +#define LINE( a, b ) r600_line( rmesa, a, b ) +#define POINT( a ) r600_point( rmesa, a ) /*********************************************************************** * Build render functions from dd templates * ***********************************************************************/ -#define R300_TWOSIDE_BIT 0x01 -#define R300_UNFILLED_BIT 0x02 -#define R300_MAX_TRIFUNC 0x04 +#define R600_TWOSIDE_BIT 0x01 +#define R600_UNFILLED_BIT 0x02 +#define R600_MAX_TRIFUNC 0x04 static struct { tnl_points_func points; tnl_line_func line; tnl_triangle_func triangle; tnl_quad_func quad; -} rast_tab[R300_MAX_TRIFUNC]; +} rast_tab[R600_MAX_TRIFUNC]; #define DO_FALLBACK 0 -#define DO_UNFILLED (IND & R300_UNFILLED_BIT) -#define DO_TWOSIDE (IND & R300_TWOSIDE_BIT) +#define DO_UNFILLED (IND & R600_UNFILLED_BIT) +#define DO_TWOSIDE (IND & R600_TWOSIDE_BIT) #define DO_FLAT 0 #define DO_OFFSET 0 #define DO_TRI 1 @@ -422,7 +422,7 @@ static struct { #define VERT_SET_RGBA( v, c ) \ do { \ - r300_color_t *color = (r300_color_t *)&((v)->ui[coloroffset]); \ + r600_color_t *color = (r600_color_t *)&((v)->ui[coloroffset]); \ UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]); \ UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]); \ UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]); \ @@ -459,7 +459,7 @@ do { \ #undef INIT #define LOCAL_VARS(n) \ - r300ContextPtr rmesa = R300_CONTEXT(ctx); \ + r600ContextPtr rmesa = R600_CONTEXT(ctx); \ GLuint color[n] = { 0, }, spec[n] = { 0, }; \ GLuint coloroffset = rmesa->swtcl.coloroffset; \ GLuint specoffset = rmesa->swtcl.specoffset; \ @@ -469,7 +469,7 @@ do { \ * Helpers for rendering unfilled primitives * ***********************************************************************/ -#define RASTERIZE(x) r300RasterPrimitive( ctx, reduced_prim[x] ) +#define RASTERIZE(x) r600RasterPrimitive( ctx, reduced_prim[x] ) #define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive #undef TAG #define TAG(x) x @@ -486,15 +486,15 @@ do { \ #define TAG(x) x #include "tnl_dd/t_dd_tritmp.h" -#define IND (R300_TWOSIDE_BIT) +#define IND (R600_TWOSIDE_BIT) #define TAG(x) x##_twoside #include "tnl_dd/t_dd_tritmp.h" -#define IND (R300_UNFILLED_BIT) +#define IND (R600_UNFILLED_BIT) #define TAG(x) x##_unfilled #include "tnl_dd/t_dd_tritmp.h" -#define IND (R300_TWOSIDE_BIT|R300_UNFILLED_BIT) +#define IND (R600_TWOSIDE_BIT|R600_UNFILLED_BIT) #define TAG(x) x##_twoside_unfilled #include "tnl_dd/t_dd_tritmp.h" @@ -514,21 +514,21 @@ static void init_rast_tab( void ) #define RENDER_POINTS( start, count ) \ for ( ; start < count ; start++) \ - r300_point( rmesa, VERT(start) ) + r600_point( rmesa, VERT(start) ) #define RENDER_LINE( v0, v1 ) \ - r300_line( rmesa, VERT(v0), VERT(v1) ) + r600_line( rmesa, VERT(v0), VERT(v1) ) #define RENDER_TRI( v0, v1, v2 ) \ - r300_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) ) + r600_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) ) #define RENDER_QUAD( v0, v1, v2, v3 ) \ - r300_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) ) + r600_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) ) #define INIT(x) do { \ - r300RenderPrimitive( ctx, x ); \ + r600RenderPrimitive( ctx, x ); \ } while (0) #undef LOCAL_VARS #define LOCAL_VARS \ - r300ContextPtr rmesa = R300_CONTEXT(ctx); \ + r600ContextPtr rmesa = R600_CONTEXT(ctx); \ const GLuint vertsize = rmesa->radeon.swtcl.vertex_size; \ - const char *r300verts = (char *)rmesa->radeon.swtcl.verts; \ + const char *r600verts = (char *)rmesa->radeon.swtcl.verts; \ const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \ const GLboolean stipple = ctx->Line.StippleFlag; \ (void) elt; (void) stipple; @@ -536,11 +536,11 @@ static void init_rast_tab( void ) #define RESET_OCCLUSION #define PRESERVE_VB_DEFS #define ELT(x) (x) -#define TAG(x) r300_##x##_verts +#define TAG(x) r600_##x##_verts #include "tnl/t_vb_rendertmp.h" #undef ELT #undef TAG -#define TAG(x) r300_##x##_elts +#define TAG(x) r600_##x##_elts #define ELT(x) elt[x] #include "tnl/t_vb_rendertmp.h" @@ -550,15 +550,15 @@ static void init_rast_tab( void ) /**********************************************************************/ /* Choose render functions */ /**********************************************************************/ -static void r300ChooseRenderState( GLcontext *ctx ) +static void r600ChooseRenderState( GLcontext *ctx ) { TNLcontext *tnl = TNL_CONTEXT(ctx); - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); GLuint index = 0; GLuint flags = ctx->_TriangleCaps; - if (flags & DD_TRI_LIGHT_TWOSIDE) index |= R300_TWOSIDE_BIT; - if (flags & DD_TRI_UNFILLED) index |= R300_UNFILLED_BIT; + if (flags & DD_TRI_LIGHT_TWOSIDE) index |= R600_TWOSIDE_BIT; + if (flags & DD_TRI_UNFILLED) index |= R600_UNFILLED_BIT; if (index != rmesa->radeon.swtcl.RenderIndex) { tnl->Driver.Render.Points = rast_tab[index].points; @@ -568,9 +568,9 @@ static void r300ChooseRenderState( GLcontext *ctx ) tnl->Driver.Render.Quad = rast_tab[index].quad; if (index == 0) { - tnl->Driver.Render.PrimTabVerts = r300_render_tab_verts; - tnl->Driver.Render.PrimTabElts = r300_render_tab_elts; - tnl->Driver.Render.ClippedPolygon = r300_fast_clipped_poly; + tnl->Driver.Render.PrimTabVerts = r600_render_tab_verts; + tnl->Driver.Render.PrimTabElts = r600_render_tab_elts; + tnl->Driver.Render.ClippedPolygon = r600_fast_clipped_poly; } else { tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts; tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts; @@ -582,19 +582,19 @@ static void r300ChooseRenderState( GLcontext *ctx ) } -static void r300RenderStart(GLcontext *ctx) +static void r600RenderStart(GLcontext *ctx) { - r300ContextPtr rmesa = R300_CONTEXT( ctx ); + r600ContextPtr rmesa = R600_CONTEXT( ctx ); - r300ChooseRenderState(ctx); - r300SetVertexFormat(ctx); + r600ChooseRenderState(ctx); + r600SetVertexFormat(ctx); - r300ValidateBuffers(ctx); + r600ValidateBuffers(ctx); - r300UpdateShaders(rmesa); - r300UpdateShaderStates(rmesa); + r600UpdateShaders(rmesa); + r600UpdateShaderStates(rmesa); - r300EmitCacheFlush(rmesa); + r600EmitCacheFlush(rmesa); /* investigate if we can put back flush optimisation if needed */ if (rmesa->radeon.dma.flush != NULL) { @@ -602,40 +602,40 @@ static void r300RenderStart(GLcontext *ctx) } } -static void r300RenderFinish(GLcontext *ctx) +static void r600RenderFinish(GLcontext *ctx) { } -static void r300RasterPrimitive( GLcontext *ctx, GLuint hwprim ) +static void r600RasterPrimitive( GLcontext *ctx, GLuint hwprim ) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); if (rmesa->radeon.swtcl.hw_primitive != hwprim) { - R300_NEWPRIM( rmesa ); + R600_NEWPRIM( rmesa ); rmesa->radeon.swtcl.hw_primitive = hwprim; } } -static void r300RenderPrimitive(GLcontext *ctx, GLenum prim) +static void r600RenderPrimitive(GLcontext *ctx, GLenum prim) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); rmesa->radeon.swtcl.render_primitive = prim; if ((prim == GL_TRIANGLES) && (ctx->_TriangleCaps & DD_TRI_UNFILLED)) return; - r300RasterPrimitive( ctx, reduced_prim[prim] ); + r600RasterPrimitive( ctx, reduced_prim[prim] ); } -static void r300ResetLineStipple(GLcontext *ctx) +static void r600ResetLineStipple(GLcontext *ctx) { } -void r300InitSwtcl(GLcontext *ctx) +void r600InitSwtcl(GLcontext *ctx) { TNLcontext *tnl = TNL_CONTEXT(ctx); - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); static int firsttime = 1; if (firsttime) { @@ -643,10 +643,10 @@ void r300InitSwtcl(GLcontext *ctx) firsttime = 0; } - tnl->Driver.Render.Start = r300RenderStart; - tnl->Driver.Render.Finish = r300RenderFinish; - tnl->Driver.Render.PrimitiveNotify = r300RenderPrimitive; - tnl->Driver.Render.ResetLineStipple = r300ResetLineStipple; + tnl->Driver.Render.Start = r600RenderStart; + tnl->Driver.Render.Finish = r600RenderFinish; + tnl->Driver.Render.PrimitiveNotify = r600RenderPrimitive; + tnl->Driver.Render.ResetLineStipple = r600ResetLineStipple; tnl->Driver.Render.BuildVertices = _tnl_build_vertices; tnl->Driver.Render.CopyPV = _tnl_copy_pv; tnl->Driver.Render.Interp = _tnl_interp; @@ -664,14 +664,14 @@ void r300InitSwtcl(GLcontext *ctx) _tnl_invalidate_vertices( ctx, ~0 ); _tnl_need_projected_coords( ctx, GL_FALSE ); - r300ChooseRenderState(ctx); + r600ChooseRenderState(ctx); } -void r300DestroySwtcl(GLcontext *ctx) +void r600DestroySwtcl(GLcontext *ctx) { } -static void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset) +static void r600EmitVertexAOS(r600ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset) { BATCH_LOCALS(&rmesa->radeon); @@ -680,43 +680,43 @@ static void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct r __FUNCTION__, vertex_size, offset); BEGIN_BATCH(7); - OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, 2); + OUT_BATCH_PACKET3(R600_PACKET3_3D_LOAD_VBPNTR, 2); OUT_BATCH(1); OUT_BATCH(vertex_size | (vertex_size << 8)); OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0); END_BATCH(); } -static void r300EmitVbufPrim(r300ContextPtr rmesa, GLuint primitive, GLuint vertex_nr) +static void r600EmitVbufPrim(r600ContextPtr rmesa, GLuint primitive, GLuint vertex_nr) { BATCH_LOCALS(&rmesa->radeon); int type, num_verts; - type = r300PrimitiveType(rmesa, primitive); - num_verts = r300NumVerts(rmesa, vertex_nr, primitive); + type = r600PrimitiveType(rmesa, primitive); + num_verts = r600NumVerts(rmesa, vertex_nr, primitive); BEGIN_BATCH(3); - OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0); - OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type); + OUT_BATCH_PACKET3(R600_PACKET3_3D_DRAW_VBUF_2, 0); + OUT_BATCH(R600_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type); END_BATCH(); } -void r300_swtcl_flush(GLcontext *ctx, uint32_t current_offset) +void r600_swtcl_flush(GLcontext *ctx, uint32_t current_offset) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->radeon.hw.max_state_size + (12*sizeof(int)), __FUNCTION__); radeonEmitState(&rmesa->radeon); - r300EmitVertexAOS(rmesa, + r600EmitVertexAOS(rmesa, rmesa->radeon.swtcl.vertex_size, rmesa->radeon.dma.current, current_offset); - r300EmitVbufPrim(rmesa, + r600EmitVbufPrim(rmesa, rmesa->radeon.swtcl.hw_primitive, rmesa->radeon.swtcl.numverts); - r300EmitCacheFlush(rmesa); + r600EmitCacheFlush(rmesa); COMMIT_BATCH(); } diff --git a/src/mesa/drivers/dri/r600/r600_swtcl.h b/src/mesa/drivers/dri/r600/r600_swtcl.h index d1739f8db8..bc0fdaf830 100644 --- a/src/mesa/drivers/dri/r600/r600_swtcl.h +++ b/src/mesa/drivers/dri/r600/r600_swtcl.h @@ -39,11 +39,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast/swrast.h" #include "r600_context.h" -#define MASK_XYZW (R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) -#define MASK_X R300_WRITE_ENA_X -#define MASK_Y R300_WRITE_ENA_Y -#define MASK_Z R300_WRITE_ENA_Z -#define MASK_W R300_WRITE_ENA_W +#define MASK_XYZW (R600_WRITE_ENA_X | R600_WRITE_ENA_Y | R600_WRITE_ENA_Z | R600_WRITE_ENA_W) +#define MASK_X R600_WRITE_ENA_X +#define MASK_Y R600_WRITE_ENA_Y +#define MASK_Z R600_WRITE_ENA_Z +#define MASK_W R600_WRITE_ENA_W /* * Here are definitions of OVM locations of vertex attributes for non TCL hw @@ -55,8 +55,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define SWTCL_OVM_POINT_SIZE 15 -extern void r300InitSwtcl( GLcontext *ctx ); -extern void r300DestroySwtcl( GLcontext *ctx ); +extern void r600InitSwtcl( GLcontext *ctx ); +extern void r600DestroySwtcl( GLcontext *ctx ); -extern void r300_swtcl_flush(GLcontext *ctx, uint32_t current_offset); +extern void r600_swtcl_flush(GLcontext *ctx, uint32_t current_offset); #endif diff --git a/src/mesa/drivers/dri/r600/r600_tex.c b/src/mesa/drivers/dri/r600/r600_tex.c index 70bf6c4b94..39c1760c62 100644 --- a/src/mesa/drivers/dri/r600/r600_tex.c +++ b/src/mesa/drivers/dri/r600/r600_tex.c @@ -59,14 +59,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. static unsigned int translate_wrap_mode(GLenum wrapmode) { switch(wrapmode) { - case GL_REPEAT: return R300_TX_REPEAT; - case GL_CLAMP: return R300_TX_CLAMP; - case GL_CLAMP_TO_EDGE: return R300_TX_CLAMP_TO_EDGE; - case GL_CLAMP_TO_BORDER: return R300_TX_CLAMP_TO_BORDER; - case GL_MIRRORED_REPEAT: return R300_TX_REPEAT | R300_TX_MIRRORED; - case GL_MIRROR_CLAMP_EXT: return R300_TX_CLAMP | R300_TX_MIRRORED; - case GL_MIRROR_CLAMP_TO_EDGE_EXT: return R300_TX_CLAMP_TO_EDGE | R300_TX_MIRRORED; - case GL_MIRROR_CLAMP_TO_BORDER_EXT: return R300_TX_CLAMP_TO_BORDER | R300_TX_MIRRORED; + case GL_REPEAT: return R600_TX_REPEAT; + case GL_CLAMP: return R600_TX_CLAMP; + case GL_CLAMP_TO_EDGE: return R600_TX_CLAMP_TO_EDGE; + case GL_CLAMP_TO_BORDER: return R600_TX_CLAMP_TO_BORDER; + case GL_MIRRORED_REPEAT: return R600_TX_REPEAT | R600_TX_MIRRORED; + case GL_MIRROR_CLAMP_EXT: return R600_TX_CLAMP | R600_TX_MIRRORED; + case GL_MIRROR_CLAMP_TO_EDGE_EXT: return R600_TX_CLAMP_TO_EDGE | R600_TX_MIRRORED; + case GL_MIRROR_CLAMP_TO_BORDER_EXT: return R600_TX_CLAMP_TO_BORDER | R600_TX_MIRRORED; default: _mesa_problem(NULL, "bad wrap mode in %s", __FUNCTION__); return 0; @@ -79,35 +79,35 @@ static unsigned int translate_wrap_mode(GLenum wrapmode) * * \param t Texture object whose wrap modes are to be set */ -static void r300UpdateTexWrap(radeonTexObjPtr t) +static void r600UpdateTexWrap(radeonTexObjPtr t) { struct gl_texture_object *tObj = &t->base; t->pp_txfilter &= - ~(R300_TX_WRAP_S_MASK | R300_TX_WRAP_T_MASK | R300_TX_WRAP_R_MASK); + ~(R600_TX_WRAP_S_MASK | R600_TX_WRAP_T_MASK | R600_TX_WRAP_R_MASK); - t->pp_txfilter |= translate_wrap_mode(tObj->WrapS) << R300_TX_WRAP_S_SHIFT; + t->pp_txfilter |= translate_wrap_mode(tObj->WrapS) << R600_TX_WRAP_S_SHIFT; if (tObj->Target != GL_TEXTURE_1D) { - t->pp_txfilter |= translate_wrap_mode(tObj->WrapT) << R300_TX_WRAP_T_SHIFT; + t->pp_txfilter |= translate_wrap_mode(tObj->WrapT) << R600_TX_WRAP_T_SHIFT; if (tObj->Target == GL_TEXTURE_3D) - t->pp_txfilter |= translate_wrap_mode(tObj->WrapR) << R300_TX_WRAP_R_SHIFT; + t->pp_txfilter |= translate_wrap_mode(tObj->WrapR) << R600_TX_WRAP_R_SHIFT; } } static GLuint aniso_filter(GLfloat anisotropy) { if (anisotropy >= 16.0) { - return R300_TX_MAX_ANISO_16_TO_1; + return R600_TX_MAX_ANISO_16_TO_1; } else if (anisotropy >= 8.0) { - return R300_TX_MAX_ANISO_8_TO_1; + return R600_TX_MAX_ANISO_8_TO_1; } else if (anisotropy >= 4.0) { - return R300_TX_MAX_ANISO_4_TO_1; + return R600_TX_MAX_ANISO_4_TO_1; } else if (anisotropy >= 2.0) { - return R300_TX_MAX_ANISO_2_TO_1; + return R600_TX_MAX_ANISO_2_TO_1; } else { - return R300_TX_MAX_ANISO_1_TO_1; + return R600_TX_MAX_ANISO_1_TO_1; } } @@ -119,13 +119,13 @@ static GLuint aniso_filter(GLfloat anisotropy) * \param magf Texture magnification mode * \param anisotropy Maximum anisotropy level */ -static void r300SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloat anisotropy) +static void r600SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloat anisotropy) { /* Force revalidation to account for switches from/to mipmapping. */ t->validated = GL_FALSE; - t->pp_txfilter &= ~(R300_TX_MIN_FILTER_MASK | R300_TX_MIN_FILTER_MIP_MASK | R300_TX_MAG_FILTER_MASK | R300_TX_MAX_ANISO_MASK); - t->pp_txfilter_1 &= ~R300_EDGE_ANISO_EDGE_ONLY; + t->pp_txfilter &= ~(R600_TX_MIN_FILTER_MASK | R600_TX_MIN_FILTER_MIP_MASK | R600_TX_MAG_FILTER_MASK | R600_TX_MAX_ANISO_MASK); + t->pp_txfilter_1 &= ~R600_EDGE_ANISO_EDGE_ONLY; /* Note that EXT_texture_filter_anisotropic is extremely vague about * how anisotropic filtering interacts with the "normal" filter modes. @@ -133,9 +133,9 @@ static void r300SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloa * filter settings completely. This includes driconf's settings. */ if (anisotropy >= 2.0 && (minf != GL_NEAREST) && (magf != GL_NEAREST)) { - t->pp_txfilter |= R300_TX_MAG_FILTER_ANISO - | R300_TX_MIN_FILTER_ANISO - | R300_TX_MIN_FILTER_MIP_LINEAR + t->pp_txfilter |= R600_TX_MAG_FILTER_ANISO + | R600_TX_MIN_FILTER_ANISO + | R600_TX_MIN_FILTER_MIP_LINEAR | aniso_filter(anisotropy); if (RADEON_DEBUG & DEBUG_TEXTURE) fprintf(stderr, "Using maximum anisotropy of %f\n", anisotropy); @@ -144,22 +144,22 @@ static void r300SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloa switch (minf) { case GL_NEAREST: - t->pp_txfilter |= R300_TX_MIN_FILTER_NEAREST; + t->pp_txfilter |= R600_TX_MIN_FILTER_NEAREST; break; case GL_LINEAR: - t->pp_txfilter |= R300_TX_MIN_FILTER_LINEAR; + t->pp_txfilter |= R600_TX_MIN_FILTER_LINEAR; break; case GL_NEAREST_MIPMAP_NEAREST: - t->pp_txfilter |= R300_TX_MIN_FILTER_NEAREST|R300_TX_MIN_FILTER_MIP_NEAREST; + t->pp_txfilter |= R600_TX_MIN_FILTER_NEAREST|R600_TX_MIN_FILTER_MIP_NEAREST; break; case GL_NEAREST_MIPMAP_LINEAR: - t->pp_txfilter |= R300_TX_MIN_FILTER_NEAREST|R300_TX_MIN_FILTER_MIP_LINEAR; + t->pp_txfilter |= R600_TX_MIN_FILTER_NEAREST|R600_TX_MIN_FILTER_MIP_LINEAR; break; case GL_LINEAR_MIPMAP_NEAREST: - t->pp_txfilter |= R300_TX_MIN_FILTER_LINEAR|R300_TX_MIN_FILTER_MIP_NEAREST; + t->pp_txfilter |= R600_TX_MIN_FILTER_LINEAR|R600_TX_MIN_FILTER_MIP_NEAREST; break; case GL_LINEAR_MIPMAP_LINEAR: - t->pp_txfilter |= R300_TX_MIN_FILTER_LINEAR|R300_TX_MIN_FILTER_MIP_LINEAR; + t->pp_txfilter |= R600_TX_MIN_FILTER_LINEAR|R600_TX_MIN_FILTER_MIP_LINEAR; break; } @@ -168,15 +168,15 @@ static void r300SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloa */ switch (magf) { case GL_NEAREST: - t->pp_txfilter |= R300_TX_MAG_FILTER_NEAREST; + t->pp_txfilter |= R600_TX_MAG_FILTER_NEAREST; break; case GL_LINEAR: - t->pp_txfilter |= R300_TX_MAG_FILTER_LINEAR; + t->pp_txfilter |= R600_TX_MAG_FILTER_LINEAR; break; } } -static void r300SetTexBorderColor(radeonTexObjPtr t, GLubyte c[4]) +static void r600SetTexBorderColor(radeonTexObjPtr t, GLubyte c[4]) { t->pp_border_color = PACK_COLOR_8888(c[3], c[0], c[1], c[2]); } @@ -186,7 +186,7 @@ static void r300SetTexBorderColor(radeonTexObjPtr t, GLubyte c[4]) * next UpdateTextureState */ -static void r300TexParameter(GLcontext * ctx, GLenum target, +static void r600TexParameter(GLcontext * ctx, GLenum target, struct gl_texture_object *texObj, GLenum pname, const GLfloat * params) { @@ -201,17 +201,17 @@ static void r300TexParameter(GLcontext * ctx, GLenum target, case GL_TEXTURE_MIN_FILTER: case GL_TEXTURE_MAG_FILTER: case GL_TEXTURE_MAX_ANISOTROPY_EXT: - r300SetTexFilter(t, texObj->MinFilter, texObj->MagFilter, texObj->MaxAnisotropy); + r600SetTexFilter(t, texObj->MinFilter, texObj->MagFilter, texObj->MaxAnisotropy); break; case GL_TEXTURE_WRAP_S: case GL_TEXTURE_WRAP_T: case GL_TEXTURE_WRAP_R: - r300UpdateTexWrap(t); + r600UpdateTexWrap(t); break; case GL_TEXTURE_BORDER_COLOR: - r300SetTexBorderColor(t, texObj->_BorderChan); + r600SetTexBorderColor(t, texObj->_BorderChan); break; case GL_TEXTURE_BASE_LEVEL: @@ -235,7 +235,7 @@ static void r300TexParameter(GLcontext * ctx, GLenum target, return; if (texObj->Image[0][texObj->BaseLevel]->TexFormat->BaseFormat == GL_DEPTH_COMPONENT) { - r300SetDepthTexMode(texObj); + r600SetDepthTexMode(texObj); break; } else { /* If the texture isn't a depth texture, changing this @@ -250,9 +250,9 @@ static void r300TexParameter(GLcontext * ctx, GLenum target, } } -static void r300DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) +static void r600DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); radeonTexObj* t = radeon_tex_obj(texObj); if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { @@ -265,7 +265,7 @@ static void r300DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) int i; radeon_firevertices(&rmesa->radeon); - for(i = 0; i < R300_MAX_TEXTURE_UNITS; ++i) + for(i = 0; i < R600_MAX_TEXTURE_UNITS; ++i) if (rmesa->hw.textures[i] == t) rmesa->hw.textures[i] = 0; } @@ -289,11 +289,11 @@ static void r300DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) * allocate the default texture objects. * Fixup MaxAnisotropy according to user preference. */ -static struct gl_texture_object *r300NewTextureObject(GLcontext * ctx, +static struct gl_texture_object *r600NewTextureObject(GLcontext * ctx, GLuint name, GLenum target) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj); @@ -306,14 +306,14 @@ static struct gl_texture_object *r300NewTextureObject(GLcontext * ctx, t->base.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy; /* Initialize hardware state */ - r300UpdateTexWrap(t); - r300SetTexFilter(t, t->base.MinFilter, t->base.MagFilter, t->base.MaxAnisotropy); - r300SetTexBorderColor(t, t->base._BorderChan); + r600UpdateTexWrap(t); + r600SetTexFilter(t, t->base.MinFilter, t->base.MagFilter, t->base.MaxAnisotropy); + r600SetTexBorderColor(t, t->base._BorderChan); return &t->base; } -void r300InitTextureFuncs(struct dd_function_table *functions) +void r600InitTextureFuncs(struct dd_function_table *functions) { /* Note: we only plug in the functions we implement in the driver * since _mesa_init_driver_functions() was already called. @@ -332,11 +332,11 @@ void r300InitTextureFuncs(struct dd_function_table *functions) functions->TexSubImage3D = radeonTexSubImage3D; functions->GetTexImage = radeonGetTexImage; functions->GetCompressedTexImage = radeonGetCompressedTexImage; - functions->NewTextureObject = r300NewTextureObject; - functions->DeleteTexture = r300DeleteTexture; + functions->NewTextureObject = r600NewTextureObject; + functions->DeleteTexture = r600DeleteTexture; functions->IsTextureResident = driIsTextureResident; - functions->TexParameter = r300TexParameter; + functions->TexParameter = r600TexParameter; functions->CompressedTexImage2D = radeonCompressedTexImage2D; functions->CompressedTexSubImage2D = radeonCompressedTexSubImage2D; diff --git a/src/mesa/drivers/dri/r600/r600_tex.h b/src/mesa/drivers/dri/r600/r600_tex.h index 1d7d396f6d..a1d50ec698 100644 --- a/src/mesa/drivers/dri/r600/r600_tex.h +++ b/src/mesa/drivers/dri/r600/r600_tex.h @@ -35,20 +35,20 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef __r600_TEX_H__ #define __r600_TEX_H__ -extern void r300SetDepthTexMode(struct gl_texture_object *tObj); +extern void r600SetDepthTexMode(struct gl_texture_object *tObj); -extern void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, +extern void r600SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv); -extern void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, +extern void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint format, __DRIdrawable *dPriv); -extern void r300SetTexOffset(__DRIcontext *pDRICtx, GLint texname, +extern void r600SetTexOffset(__DRIcontext *pDRICtx, GLint texname, unsigned long long offset, GLint depth, GLuint pitch); -extern GLboolean r300ValidateBuffers(GLcontext * ctx); +extern GLboolean r600ValidateBuffers(GLcontext * ctx); -extern void r300InitTextureFuncs(struct dd_function_table *functions); +extern void r600InitTextureFuncs(struct dd_function_table *functions); #endif /* __r600_TEX_H__ */ diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 3168d5a8b2..6beafafe83 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -32,7 +32,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * \author Keith Whitwell * - * \todo Enable R300 texture tiling code? + * \todo Enable R600 texture tiling code? */ #include "main/glheader.h" @@ -63,8 +63,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * Note that the _REV formats are the same as the non-REV formats. This is * because the REV and non-REV formats are identical as a byte string, but * differ when accessed as 16-bit or 32-bit words depending on the endianness of - * the host. Since the textures are transferred to the R300 as a byte string - * (i.e. without any byte-swapping), the R300 sees the REV and non-REV formats + * the host. Since the textures are transferred to the R600 as a byte string + * (i.e. without any byte-swapping), the R600 sees the REV and non-REV formats * identically. -- paulus */ @@ -73,73 +73,73 @@ static const struct tx_table { } tx_table[] = { /* *INDENT-OFF* */ #ifdef MESA_LITTLE_ENDIAN - _ASSIGN(RGBA8888, R300_EASY_TX_FORMAT(Y, Z, W, X, W8Z8Y8X8)), - _ASSIGN(RGBA8888_REV, R300_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8)), - _ASSIGN(ARGB8888, R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8)), - _ASSIGN(ARGB8888_REV, R300_EASY_TX_FORMAT(W, Z, Y, X, W8Z8Y8X8)), + _ASSIGN(RGBA8888, R600_EASY_TX_FORMAT(Y, Z, W, X, W8Z8Y8X8)), + _ASSIGN(RGBA8888_REV, R600_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8)), + _ASSIGN(ARGB8888, R600_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8)), + _ASSIGN(ARGB8888_REV, R600_EASY_TX_FORMAT(W, Z, Y, X, W8Z8Y8X8)), #else - _ASSIGN(RGBA8888, R300_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8)), - _ASSIGN(RGBA8888_REV, R300_EASY_TX_FORMAT(Y, Z, W, X, W8Z8Y8X8)), - _ASSIGN(ARGB8888, R300_EASY_TX_FORMAT(W, Z, Y, X, W8Z8Y8X8)), - _ASSIGN(ARGB8888_REV, R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8)), + _ASSIGN(RGBA8888, R600_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8)), + _ASSIGN(RGBA8888_REV, R600_EASY_TX_FORMAT(Y, Z, W, X, W8Z8Y8X8)), + _ASSIGN(ARGB8888, R600_EASY_TX_FORMAT(W, Z, Y, X, W8Z8Y8X8)), + _ASSIGN(ARGB8888_REV, R600_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8)), #endif - _ASSIGN(RGB888, R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8)), - _ASSIGN(RGB565, R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5)), - _ASSIGN(RGB565_REV, R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5)), - _ASSIGN(ARGB4444, R300_EASY_TX_FORMAT(X, Y, Z, W, W4Z4Y4X4)), - _ASSIGN(ARGB4444_REV, R300_EASY_TX_FORMAT(X, Y, Z, W, W4Z4Y4X4)), - _ASSIGN(ARGB1555, R300_EASY_TX_FORMAT(X, Y, Z, W, W1Z5Y5X5)), - _ASSIGN(ARGB1555_REV, R300_EASY_TX_FORMAT(X, Y, Z, W, W1Z5Y5X5)), - _ASSIGN(AL88, R300_EASY_TX_FORMAT(X, X, X, Y, Y8X8)), - _ASSIGN(AL88_REV, R300_EASY_TX_FORMAT(X, X, X, Y, Y8X8)), - _ASSIGN(RGB332, R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z3Y3X2)), - _ASSIGN(A8, R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X8)), - _ASSIGN(L8, R300_EASY_TX_FORMAT(X, X, X, ONE, X8)), - _ASSIGN(I8, R300_EASY_TX_FORMAT(X, X, X, X, X8)), - _ASSIGN(CI8, R300_EASY_TX_FORMAT(X, X, X, X, X8)), - _ASSIGN(YCBCR, R300_EASY_TX_FORMAT(X, Y, Z, ONE, G8R8_G8B8) | R300_TX_FORMAT_YUV_MODE), - _ASSIGN(YCBCR_REV, R300_EASY_TX_FORMAT(X, Y, Z, ONE, G8R8_G8B8) | R300_TX_FORMAT_YUV_MODE), - _ASSIGN(RGB_DXT1, R300_EASY_TX_FORMAT(X, Y, Z, ONE, DXT1)), - _ASSIGN(RGBA_DXT1, R300_EASY_TX_FORMAT(X, Y, Z, W, DXT1)), - _ASSIGN(RGBA_DXT3, R300_EASY_TX_FORMAT(X, Y, Z, W, DXT3)), - _ASSIGN(RGBA_DXT5, R300_EASY_TX_FORMAT(Y, Z, W, X, DXT5)), - _ASSIGN(RGBA_FLOAT32, R300_EASY_TX_FORMAT(Z, Y, X, W, FL_R32G32B32A32)), - _ASSIGN(RGBA_FLOAT16, R300_EASY_TX_FORMAT(Z, Y, X, W, FL_R16G16B16A16)), + _ASSIGN(RGB888, R600_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8)), + _ASSIGN(RGB565, R600_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5)), + _ASSIGN(RGB565_REV, R600_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5)), + _ASSIGN(ARGB4444, R600_EASY_TX_FORMAT(X, Y, Z, W, W4Z4Y4X4)), + _ASSIGN(ARGB4444_REV, R600_EASY_TX_FORMAT(X, Y, Z, W, W4Z4Y4X4)), + _ASSIGN(ARGB1555, R600_EASY_TX_FORMAT(X, Y, Z, W, W1Z5Y5X5)), + _ASSIGN(ARGB1555_REV, R600_EASY_TX_FORMAT(X, Y, Z, W, W1Z5Y5X5)), + _ASSIGN(AL88, R600_EASY_TX_FORMAT(X, X, X, Y, Y8X8)), + _ASSIGN(AL88_REV, R600_EASY_TX_FORMAT(X, X, X, Y, Y8X8)), + _ASSIGN(RGB332, R600_EASY_TX_FORMAT(X, Y, Z, ONE, Z3Y3X2)), + _ASSIGN(A8, R600_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X8)), + _ASSIGN(L8, R600_EASY_TX_FORMAT(X, X, X, ONE, X8)), + _ASSIGN(I8, R600_EASY_TX_FORMAT(X, X, X, X, X8)), + _ASSIGN(CI8, R600_EASY_TX_FORMAT(X, X, X, X, X8)), + _ASSIGN(YCBCR, R600_EASY_TX_FORMAT(X, Y, Z, ONE, G8R8_G8B8) | R600_TX_FORMAT_YUV_MODE), + _ASSIGN(YCBCR_REV, R600_EASY_TX_FORMAT(X, Y, Z, ONE, G8R8_G8B8) | R600_TX_FORMAT_YUV_MODE), + _ASSIGN(RGB_DXT1, R600_EASY_TX_FORMAT(X, Y, Z, ONE, DXT1)), + _ASSIGN(RGBA_DXT1, R600_EASY_TX_FORMAT(X, Y, Z, W, DXT1)), + _ASSIGN(RGBA_DXT3, R600_EASY_TX_FORMAT(X, Y, Z, W, DXT3)), + _ASSIGN(RGBA_DXT5, R600_EASY_TX_FORMAT(Y, Z, W, X, DXT5)), + _ASSIGN(RGBA_FLOAT32, R600_EASY_TX_FORMAT(Z, Y, X, W, FL_R32G32B32A32)), + _ASSIGN(RGBA_FLOAT16, R600_EASY_TX_FORMAT(Z, Y, X, W, FL_R16G16B16A16)), _ASSIGN(RGB_FLOAT32, 0xffffffff), _ASSIGN(RGB_FLOAT16, 0xffffffff), - _ASSIGN(ALPHA_FLOAT32, R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, FL_I32)), - _ASSIGN(ALPHA_FLOAT16, R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, FL_I16)), - _ASSIGN(LUMINANCE_FLOAT32, R300_EASY_TX_FORMAT(X, X, X, ONE, FL_I32)), - _ASSIGN(LUMINANCE_FLOAT16, R300_EASY_TX_FORMAT(X, X, X, ONE, FL_I16)), - _ASSIGN(LUMINANCE_ALPHA_FLOAT32, R300_EASY_TX_FORMAT(X, X, X, Y, FL_I32A32)), - _ASSIGN(LUMINANCE_ALPHA_FLOAT16, R300_EASY_TX_FORMAT(X, X, X, Y, FL_I16A16)), - _ASSIGN(INTENSITY_FLOAT32, R300_EASY_TX_FORMAT(X, X, X, X, FL_I32)), - _ASSIGN(INTENSITY_FLOAT16, R300_EASY_TX_FORMAT(X, X, X, X, FL_I16)), - _ASSIGN(Z16, R300_EASY_TX_FORMAT(X, X, X, X, X16)), - _ASSIGN(Z24_S8, R300_EASY_TX_FORMAT(X, X, X, X, X24_Y8)), - _ASSIGN(Z32, R300_EASY_TX_FORMAT(X, X, X, X, X32)), + _ASSIGN(ALPHA_FLOAT32, R600_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, FL_I32)), + _ASSIGN(ALPHA_FLOAT16, R600_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, FL_I16)), + _ASSIGN(LUMINANCE_FLOAT32, R600_EASY_TX_FORMAT(X, X, X, ONE, FL_I32)), + _ASSIGN(LUMINANCE_FLOAT16, R600_EASY_TX_FORMAT(X, X, X, ONE, FL_I16)), + _ASSIGN(LUMINANCE_ALPHA_FLOAT32, R600_EASY_TX_FORMAT(X, X, X, Y, FL_I32A32)), + _ASSIGN(LUMINANCE_ALPHA_FLOAT16, R600_EASY_TX_FORMAT(X, X, X, Y, FL_I16A16)), + _ASSIGN(INTENSITY_FLOAT32, R600_EASY_TX_FORMAT(X, X, X, X, FL_I32)), + _ASSIGN(INTENSITY_FLOAT16, R600_EASY_TX_FORMAT(X, X, X, X, FL_I16)), + _ASSIGN(Z16, R600_EASY_TX_FORMAT(X, X, X, X, X16)), + _ASSIGN(Z24_S8, R600_EASY_TX_FORMAT(X, X, X, X, X24_Y8)), + _ASSIGN(Z32, R600_EASY_TX_FORMAT(X, X, X, X, X32)), /* *INDENT-ON* */ }; #undef _ASSIGN -void r300SetDepthTexMode(struct gl_texture_object *tObj) +void r600SetDepthTexMode(struct gl_texture_object *tObj) { static const GLuint formats[3][3] = { { - R300_EASY_TX_FORMAT(X, X, X, ONE, X16), - R300_EASY_TX_FORMAT(X, X, X, X, X16), - R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X16), + R600_EASY_TX_FORMAT(X, X, X, ONE, X16), + R600_EASY_TX_FORMAT(X, X, X, X, X16), + R600_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X16), }, { - R300_EASY_TX_FORMAT(X, X, X, ONE, X24_Y8), - R300_EASY_TX_FORMAT(X, X, X, X, X24_Y8), - R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X24_Y8), + R600_EASY_TX_FORMAT(X, X, X, ONE, X24_Y8), + R600_EASY_TX_FORMAT(X, X, X, X, X24_Y8), + R600_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X24_Y8), }, { - R300_EASY_TX_FORMAT(X, X, X, ONE, X32), - R300_EASY_TX_FORMAT(X, X, X, X, X32), - R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X32), + R600_EASY_TX_FORMAT(X, X, X, ONE, X32), + R600_EASY_TX_FORMAT(X, X, X, X, X32), + R600_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X32), }, }; const GLuint *format; @@ -192,9 +192,9 @@ void r300SetDepthTexMode(struct gl_texture_object *tObj) * Compute the cached hardware register values for the given texture object. * * \param rmesa Context pointer - * \param t the r300 texture object + * \param t the r600 texture object */ -static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t) +static void setup_hardware_state(r600ContextPtr rmesa, radeonTexObj *t) { const struct gl_texture_image *firstImage; int firstlevel = t->mt ? t->mt->firstLevel : 0; @@ -204,7 +204,7 @@ static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t) if (!t->image_override && VALID_FORMAT(firstImage->TexFormat->MesaFormat)) { if (firstImage->TexFormat->BaseFormat == GL_DEPTH_COMPONENT) { - r300SetDepthTexMode(&t->base); + r600SetDepthTexMode(&t->base); } else { t->pp_txformat = tx_table[firstImage->TexFormat->MesaFormat].format; } @@ -219,22 +219,22 @@ static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t) if (t->image_override && t->bo) return; - t->pp_txsize = (((firstImage->Width - 1) << R300_TX_WIDTHMASK_SHIFT) - | ((firstImage->Height - 1) << R300_TX_HEIGHTMASK_SHIFT) - | ((firstImage->DepthLog2) << R300_TX_DEPTHMASK_SHIFT) - | ((t->mt->lastLevel - t->mt->firstLevel) << R300_TX_MAX_MIP_LEVEL_SHIFT)); + t->pp_txsize = (((firstImage->Width - 1) << R600_TX_WIDTHMASK_SHIFT) + | ((firstImage->Height - 1) << R600_TX_HEIGHTMASK_SHIFT) + | ((firstImage->DepthLog2) << R600_TX_DEPTHMASK_SHIFT) + | ((t->mt->lastLevel - t->mt->firstLevel) << R600_TX_MAX_MIP_LEVEL_SHIFT)); t->tile_bits = 0; if (t->base.Target == GL_TEXTURE_CUBE_MAP) - t->pp_txformat |= R300_TX_FORMAT_CUBIC_MAP; + t->pp_txformat |= R600_TX_FORMAT_CUBIC_MAP; if (t->base.Target == GL_TEXTURE_3D) - t->pp_txformat |= R300_TX_FORMAT_3D; + t->pp_txformat |= R600_TX_FORMAT_3D; if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) { unsigned int align = (64 / t->mt->bpp) - 1; - t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN; + t->pp_txsize |= R600_TX_SIZE_TXPITCH_EN; if (!t->image_override) t->pp_txpitch = ((firstImage->Width + align) & ~align) - 1; } @@ -252,9 +252,9 @@ static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t) * * Mostly this means populating the texture object's mipmap tree. */ -static GLboolean r300_validate_texture(GLcontext * ctx, struct gl_texture_object *texObj) +static GLboolean r600_validate_texture(GLcontext * ctx, struct gl_texture_object *texObj) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); radeonTexObj *t = radeon_tex_obj(texObj); if (!radeon_validate_texture_miptree(ctx, texObj)) @@ -271,9 +271,9 @@ static GLboolean r300_validate_texture(GLcontext * ctx, struct gl_texture_object /** * Ensure all enabled and complete textures are uploaded along with any buffers being used. */ -GLboolean r300ValidateBuffers(GLcontext * ctx) +GLboolean r600ValidateBuffers(GLcontext * ctx) { - r300ContextPtr rmesa = R300_CONTEXT(ctx); + r600ContextPtr rmesa = R600_CONTEXT(ctx); struct radeon_renderbuffer *rrb; int i; @@ -299,7 +299,7 @@ GLboolean r300ValidateBuffers(GLcontext * ctx) if (!ctx->Texture.Unit[i]._ReallyEnabled) continue; - if (!r300_validate_texture(ctx, ctx->Texture.Unit[i]._Current)) { + if (!r600_validate_texture(ctx, ctx->Texture.Unit[i]._Current)) { _mesa_warning(ctx, "failed to validate texture for unit %d.\n", i); @@ -319,10 +319,10 @@ GLboolean r300ValidateBuffers(GLcontext * ctx) return radeon_revalidate_bos(ctx); } -void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, +void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname, unsigned long long offset, GLint depth, GLuint pitch) { - r300ContextPtr rmesa = pDRICtx->driverPrivate; + r600ContextPtr rmesa = pDRICtx->driverPrivate; struct gl_texture_object *tObj = _mesa_lookup_texture(rmesa->radeon.glCtx, texname); radeonTexObjPtr t = radeon_tex_obj(tObj); @@ -343,18 +343,18 @@ void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, switch (depth) { case 32: - t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8); + t->pp_txformat = R600_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8); t->pp_txfilter |= tx_table[2].filter; pitch_val /= 4; break; case 24: default: - t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8); + t->pp_txformat = R600_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8); t->pp_txfilter |= tx_table[4].filter; pitch_val /= 4; break; case 16: - t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5); + t->pp_txformat = R600_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5); t->pp_txfilter |= tx_table[5].filter; pitch_val /= 2; break; @@ -364,7 +364,7 @@ void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname, t->pp_txpitch |= pitch_val; } -void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, __DRIdrawable *dPriv) +void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, __DRIdrawable *dPriv) { struct gl_texture_unit *texUnit; struct gl_texture_object *texObj; @@ -372,7 +372,7 @@ void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo struct radeon_renderbuffer *rb; radeon_texture_image *rImage; radeonContextPtr radeon; - r300ContextPtr rmesa; + r600ContextPtr rmesa; struct radeon_framebuffer *rfb; radeonTexObjPtr t; uint32_t pitch_val; @@ -449,26 +449,26 @@ void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo pitch_val = rb->pitch; switch (rb->cpp) { case 4: - t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8); + t->pp_txformat = R600_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8); t->pp_txfilter |= tx_table[2].filter; pitch_val /= 4; break; case 3: default: - t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8); + t->pp_txformat = R600_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8); t->pp_txfilter |= tx_table[4].filter; pitch_val /= 4; break; case 2: - t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5); + t->pp_txformat = R600_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5); t->pp_txfilter |= tx_table[5].filter; pitch_val /= 2; break; } pitch_val--; - t->pp_txsize = ((rb->width - 1) << R300_TX_WIDTHMASK_SHIFT) | - ((rb->height - 1) << R300_TX_HEIGHTMASK_SHIFT); - t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN; + t->pp_txsize = ((rb->width - 1) << R600_TX_WIDTHMASK_SHIFT) | + ((rb->height - 1) << R600_TX_HEIGHTMASK_SHIFT); + t->pp_txsize |= R600_TX_SIZE_TXPITCH_EN; t->pp_txpitch |= pitch_val; if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { @@ -482,7 +482,7 @@ void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo return; } -void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) +void r600SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) { - r300SetTexBuffer2(pDRICtx, target, GLX_TEXTURE_FORMAT_RGBA_EXT, dPriv); + r600SetTexBuffer2(pDRICtx, target, GLX_TEXTURE_FORMAT_RGBA_EXT, dPriv); } diff --git a/src/mesa/drivers/dri/r600/r600_vertprog.c b/src/mesa/drivers/dri/r600/r600_vertprog.c index 946d8beb46..8e4506403f 100644 --- a/src/mesa/drivers/dri/r600/r600_vertprog.c +++ b/src/mesa/drivers/dri/r600/r600_vertprog.c @@ -69,8 +69,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. u_temp_i=VSF_MAX_FRAGMENT_TEMPS-1; \ } while (0) -int r300VertexProgUpdateParams(GLcontext * ctx, - struct r300_vertex_program_cont *vp, float *dst) +int r600VertexProgUpdateParams(GLcontext * ctx, + struct r600_vertex_program_cont *vp, float *dst) { int pi; struct gl_vertex_program *mesa_vp = &vp->mesa_program; @@ -152,7 +152,7 @@ static unsigned long t_dst_class(gl_register_file file) } } -static unsigned long t_dst_index(struct r300_vertex_program *vp, +static unsigned long t_dst_index(struct r600_vertex_program *vp, struct prog_dst_register *dst) { if (dst->File == PROGRAM_OUTPUT) @@ -193,7 +193,7 @@ static INLINE unsigned long t_swizzle(GLubyte swizzle) } #if 0 -static void vp_dump_inputs(struct r300_vertex_program *vp, char *caller) +static void vp_dump_inputs(struct r600_vertex_program *vp, char *caller) { int i; @@ -211,7 +211,7 @@ static void vp_dump_inputs(struct r300_vertex_program *vp, char *caller) } #endif -static unsigned long t_src_index(struct r300_vertex_program *vp, +static unsigned long t_src_index(struct r600_vertex_program *vp, struct prog_src_register *src) { int i; @@ -242,7 +242,7 @@ static unsigned long t_src_index(struct r300_vertex_program *vp, /* these two functions should probably be merged... */ -static unsigned long t_src(struct r300_vertex_program *vp, +static unsigned long t_src(struct r600_vertex_program *vp, struct prog_src_register *src) { /* src->NegateBase uses the NEGATE_ flags from program_instruction.h, @@ -257,7 +257,7 @@ static unsigned long t_src(struct r300_vertex_program *vp, src->NegateBase) | (src->RelAddr << 4); } -static unsigned long t_src_scalar(struct r300_vertex_program *vp, +static unsigned long t_src_scalar(struct r600_vertex_program *vp, struct prog_src_register *src) { /* src->NegateBase uses the NEGATE_ flags from program_instruction.h, @@ -274,7 +274,7 @@ static unsigned long t_src_scalar(struct r300_vertex_program *vp, (src->RelAddr << 4); } -static GLboolean valid_dst(struct r300_vertex_program *vp, +static GLboolean valid_dst(struct r600_vertex_program *vp, struct prog_dst_register *dst) { if (dst->File == PROGRAM_OUTPUT && vp->outputs[dst->Index] == -1) { @@ -286,7 +286,7 @@ static GLboolean valid_dst(struct r300_vertex_program *vp, return GL_TRUE; } -static GLuint *r300TranslateOpcodeABS(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeABS(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -314,7 +314,7 @@ static GLuint *r300TranslateOpcodeABS(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeADD(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeADD(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -332,7 +332,7 @@ static GLuint *r300TranslateOpcodeADD(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeARL(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeARL(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -350,7 +350,7 @@ static GLuint *r300TranslateOpcodeARL(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeDP3(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeDP3(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -386,7 +386,7 @@ static GLuint *r300TranslateOpcodeDP3(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeDP4(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeDP4(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -404,7 +404,7 @@ static GLuint *r300TranslateOpcodeDP4(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeDPH(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeDPH(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -431,7 +431,7 @@ static GLuint *r300TranslateOpcodeDPH(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeDST(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeDST(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -449,7 +449,7 @@ static GLuint *r300TranslateOpcodeDST(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeEX2(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeEX2(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -467,7 +467,7 @@ static GLuint *r300TranslateOpcodeEX2(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeEXP(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeEXP(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -485,7 +485,7 @@ static GLuint *r300TranslateOpcodeEXP(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeFLR(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeFLR(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3], @@ -527,7 +527,7 @@ static GLuint *r300TranslateOpcodeFLR(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeFRC(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeFRC(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -545,7 +545,7 @@ static GLuint *r300TranslateOpcodeFRC(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeLG2(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeLG2(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -573,7 +573,7 @@ static GLuint *r300TranslateOpcodeLG2(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeLIT(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeLIT(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -615,7 +615,7 @@ static GLuint *r300TranslateOpcodeLIT(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeLOG(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeLOG(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -633,7 +633,7 @@ static GLuint *r300TranslateOpcodeLOG(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeMAD(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeMAD(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -651,7 +651,7 @@ static GLuint *r300TranslateOpcodeMAD(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeMAX(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeMAX(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -669,7 +669,7 @@ static GLuint *r300TranslateOpcodeMAX(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeMIN(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeMIN(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -687,7 +687,7 @@ static GLuint *r300TranslateOpcodeMIN(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeMOV(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeMOV(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -707,7 +707,7 @@ static GLuint *r300TranslateOpcodeMOV(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeMUL(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeMUL(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -725,7 +725,7 @@ static GLuint *r300TranslateOpcodeMUL(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodePOW(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodePOW(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -743,7 +743,7 @@ static GLuint *r300TranslateOpcodePOW(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeRCP(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeRCP(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -761,7 +761,7 @@ static GLuint *r300TranslateOpcodeRCP(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeRSQ(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeRSQ(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -779,7 +779,7 @@ static GLuint *r300TranslateOpcodeRSQ(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeSGE(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeSGE(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -797,7 +797,7 @@ static GLuint *r300TranslateOpcodeSGE(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeSLT(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeSLT(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -815,7 +815,7 @@ static GLuint *r300TranslateOpcodeSLT(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeSUB(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeSUB(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -864,7 +864,7 @@ static GLuint *r300TranslateOpcodeSUB(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeSWZ(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeSWZ(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3]) @@ -884,7 +884,7 @@ static GLuint *r300TranslateOpcodeSWZ(struct r300_vertex_program *vp, return inst; } -static GLuint *r300TranslateOpcodeXPD(struct r300_vertex_program *vp, +static GLuint *r600TranslateOpcodeXPD(struct r600_vertex_program *vp, struct prog_instruction *vpi, GLuint * inst, struct prog_src_register src[3], @@ -951,7 +951,7 @@ static GLuint *r300TranslateOpcodeXPD(struct r300_vertex_program *vp, return inst; } -static void t_inputs_outputs(struct r300_vertex_program *vp) +static void t_inputs_outputs(struct r600_vertex_program *vp) { int i; int cur_reg = 0; @@ -1005,14 +1005,14 @@ static void t_inputs_outputs(struct r300_vertex_program *vp) } } -static void r300TranslateVertexShader(struct r300_vertex_program *vp, +static void r600TranslateVertexShader(struct r600_vertex_program *vp, struct prog_instruction *vpi) { int i; GLuint *inst; unsigned long num_operands; /* Initial value should be last tmp reg that hw supports. - Strangely enough r300 doesnt mind even though these would be out of range. + Strangely enough r600 doesnt mind even though these would be out of range. Smart enough to realize that it doesnt need it? */ int u_temp_i = VSF_MAX_FRAGMENT_TEMPS - 1; struct prog_src_register src[3]; @@ -1104,86 +1104,86 @@ static void r300TranslateVertexShader(struct r300_vertex_program *vp, switch (vpi->Opcode) { case OPCODE_ABS: - inst = r300TranslateOpcodeABS(vp, vpi, inst, src); + inst = r600TranslateOpcodeABS(vp, vpi, inst, src); break; case OPCODE_ADD: - inst = r300TranslateOpcodeADD(vp, vpi, inst, src); + inst = r600TranslateOpcodeADD(vp, vpi, inst, src); break; case OPCODE_ARL: - inst = r300TranslateOpcodeARL(vp, vpi, inst, src); + inst = r600TranslateOpcodeARL(vp, vpi, inst, src); break; case OPCODE_DP3: - inst = r300TranslateOpcodeDP3(vp, vpi, inst, src); + inst = r600TranslateOpcodeDP3(vp, vpi, inst, src); break; case OPCODE_DP4: - inst = r300TranslateOpcodeDP4(vp, vpi, inst, src); + inst = r600TranslateOpcodeDP4(vp, vpi, inst, src); break; case OPCODE_DPH: - inst = r300TranslateOpcodeDPH(vp, vpi, inst, src); + inst = r600TranslateOpcodeDPH(vp, vpi, inst, src); break; case OPCODE_DST: - inst = r300TranslateOpcodeDST(vp, vpi, inst, src); + inst = r600TranslateOpcodeDST(vp, vpi, inst, src); break; case OPCODE_EX2: - inst = r300TranslateOpcodeEX2(vp, vpi, inst, src); + inst = r600TranslateOpcodeEX2(vp, vpi, inst, src); break; case OPCODE_EXP: - inst = r300TranslateOpcodeEXP(vp, vpi, inst, src); + inst = r600TranslateOpcodeEXP(vp, vpi, inst, src); break; case OPCODE_FLR: - inst = r300TranslateOpcodeFLR(vp, vpi, inst, src, /* FIXME */ + inst = r600TranslateOpcodeFLR(vp, vpi, inst, src, /* FIXME */ &u_temp_i); break; case OPCODE_FRC: - inst = r300TranslateOpcodeFRC(vp, vpi, inst, src); + inst = r600TranslateOpcodeFRC(vp, vpi, inst, src); break; case OPCODE_LG2: - inst = r300TranslateOpcodeLG2(vp, vpi, inst, src); + inst = r600TranslateOpcodeLG2(vp, vpi, inst, src); break; case OPCODE_LIT: - inst = r300TranslateOpcodeLIT(vp, vpi, inst, src); + inst = r600TranslateOpcodeLIT(vp, vpi, inst, src); break; case OPCODE_LOG: - inst = r300TranslateOpcodeLOG(vp, vpi, inst, src); + inst = r600TranslateOpcodeLOG(vp, vpi, inst, src); break; case OPCODE_MAD: - inst = r300TranslateOpcodeMAD(vp, vpi, inst, src); + inst = r600TranslateOpcodeMAD(vp, vpi, inst, src); break; case OPCODE_MAX: - inst = r300TranslateOpcodeMAX(vp, vpi, inst, src); + inst = r600TranslateOpcodeMAX(vp, vpi, inst, src); break; case OPCODE_MIN: - inst = r300TranslateOpcodeMIN(vp, vpi, inst, src); + inst = r600TranslateOpcodeMIN(vp, vpi, inst, src); break; case OPCODE_MOV: - inst = r300TranslateOpcodeMOV(vp, vpi, inst, src); + inst = r600TranslateOpcodeMOV(vp, vpi, inst, src); break; case OPCODE_MUL: - inst = r300TranslateOpcodeMUL(vp, vpi, inst, src); + inst = r600TranslateOpcodeMUL(vp, vpi, inst, src); break; case OPCODE_POW: - inst = r300TranslateOpcodePOW(vp, vpi, inst, src); + inst = r600TranslateOpcodePOW(vp, vpi, inst, src); break; case OPCODE_RCP: - inst = r300TranslateOpcodeRCP(vp, vpi, inst, src); + inst = r600TranslateOpcodeRCP(vp, vpi, inst, src); break; case OPCODE_RSQ: - inst = r300TranslateOpcodeRSQ(vp, vpi, inst, src); + inst = r600TranslateOpcodeRSQ(vp, vpi, inst, src); break; case OPCODE_SGE: - inst = r300TranslateOpcodeSGE(vp, vpi, inst, src); + inst = r600TranslateOpcodeSGE(vp, vpi, inst, src); break; case OPCODE_SLT: - inst = r300TranslateOpcodeSLT(vp, vpi, inst, src); + inst = r600TranslateOpcodeSLT(vp, vpi, inst, src); break; case OPCODE_SUB: - inst = r300TranslateOpcodeSUB(vp, vpi, inst, src); + inst = r600TranslateOpcodeSUB(vp, vpi, inst, src); break; case OPCODE_SWZ: - inst = r300TranslateOpcodeSWZ(vp, vpi, inst, src); + inst = r600TranslateOpcodeSWZ(vp, vpi, inst, src); break; case OPCODE_XPD: - inst = r300TranslateOpcodeXPD(vp, vpi, inst, src, /* FIXME */ + inst = r600TranslateOpcodeXPD(vp, vpi, inst, src, /* FIXME */ &u_temp_i); break; default: @@ -1309,7 +1309,7 @@ static void position_invariant(struct gl_program *prog) assert(vpi->Opcode == OPCODE_END); } -static void insert_wpos(struct r300_vertex_program *vp, struct gl_program *prog, +static void insert_wpos(struct r600_vertex_program *vp, struct gl_program *prog, GLuint temp_index) { struct prog_instruction *vpi; @@ -1361,7 +1361,7 @@ static void insert_wpos(struct r300_vertex_program *vp, struct gl_program *prog, assert(vpi->Opcode == OPCODE_END); } -static void pos_as_texcoord(struct r300_vertex_program *vp, +static void pos_as_texcoord(struct r600_vertex_program *vp, struct gl_program *prog) { struct prog_instruction *vpi; @@ -1379,11 +1379,11 @@ static void pos_as_texcoord(struct r300_vertex_program *vp, insert_wpos(vp, prog, tempregi); } -static struct r300_vertex_program *build_program(struct r300_vertex_program_key +static struct r600_vertex_program *build_program(struct r600_vertex_program_key *wanted_key, struct gl_vertex_program *mesa_vp, GLint wpos_idx) { - struct r300_vertex_program *vp; + struct r600_vertex_program *vp; vp = _mesa_calloc(sizeof(*vp)); _mesa_memcpy(&vp->key, wanted_key, sizeof(vp->key)); @@ -1399,12 +1399,12 @@ static struct r300_vertex_program *build_program(struct r300_vertex_program_key assert(mesa_vp->Base.NumInstructions); vp->num_temporaries = mesa_vp->Base.NumTemporaries; - r300TranslateVertexShader(vp, mesa_vp->Base.Instructions); + r600TranslateVertexShader(vp, mesa_vp->Base.Instructions); return vp; } -static void add_outputs(struct r300_vertex_program_key *key, GLint vert) +static void add_outputs(struct r600_vertex_program_key *key, GLint vert) { if (key->OutputsWritten & (1 << vert)) return; @@ -1413,17 +1413,17 @@ static void add_outputs(struct r300_vertex_program_key *key, GLint vert) key->OutputsAdded |= 1 << vert; } -void r300SelectVertexShader(r300ContextPtr r300) +void r600SelectVertexShader(r600ContextPtr r600) { - GLcontext *ctx = ctx = r300->radeon.glCtx; + GLcontext *ctx = ctx = r600->radeon.glCtx; GLuint InputsRead; - struct r300_vertex_program_key wanted_key = { 0 }; + struct r600_vertex_program_key wanted_key = { 0 }; GLint i; - struct r300_vertex_program_cont *vpc; - struct r300_vertex_program *vp; + struct r600_vertex_program_cont *vpc; + struct r600_vertex_program *vp; GLint wpos_idx; - vpc = (struct r300_vertex_program_cont *)ctx->VertexProgram._Current; + vpc = (struct r600_vertex_program_cont *)ctx->VertexProgram._Current; wanted_key.InputsRead = vpc->mesa_program.Base.InputsRead; wanted_key.OutputsWritten = vpc->mesa_program.Base.OutputsWritten; InputsRead = ctx->FragmentProgram._Current->Base.InputsRead; @@ -1467,7 +1467,7 @@ void r300SelectVertexShader(r300ContextPtr r300) for (vp = vpc->progs; vp; vp = vp->next) if (_mesa_memcmp(&vp->key, &wanted_key, sizeof(wanted_key)) == 0) { - r300->selected_vp = vp; + r600->selected_vp = vp; return; } //_mesa_print_program(&vpc->mesa_program.Base); @@ -1475,5 +1475,5 @@ void r300SelectVertexShader(r300ContextPtr r300) vp = build_program(&wanted_key, &vpc->mesa_program, wpos_idx); vp->next = vpc->progs; vpc->progs = vp; - r300->selected_vp = vp; + r600->selected_vp = vp; } diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index c8041b4a27..c14c7d36a4 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -189,13 +189,13 @@ static GLboolean transform_TEX( } -static void update_params(r300ContextPtr r300, struct r500_fragment_program *fp) +static void update_params(r600ContextPtr r600, struct r500_fragment_program *fp) { struct gl_fragment_program *mp = &fp->mesa_program; /* Ask Mesa nicely to fill in ParameterValues for us */ if (mp->Base.Parameters) - _mesa_load_state_parameters(r300->radeon.glCtx, mp->Base.Parameters); + _mesa_load_state_parameters(r600->radeon.glCtx, mp->Base.Parameters); } @@ -218,7 +218,7 @@ static void insert_WPOS_trailer(struct r500_fragment_program_compiler *compiler) return; static gl_state_index tokens[STATE_LENGTH] = { - STATE_INTERNAL, STATE_R300_WINDOW_DIMENSION, 0, 0, 0 + STATE_INTERNAL, STATE_R600_WINDOW_DIMENSION, 0, 0, 0 }; struct prog_instruction *fpi; GLuint window_index; @@ -419,7 +419,7 @@ static GLuint build_func(GLuint comparefunc) * fragment program. */ static void build_state( - r300ContextPtr r300, + r600ContextPtr r600, struct r500_fragment_program *fp, struct r500_fragment_program_external_state *state) { @@ -429,7 +429,7 @@ static void build_state( for(unit = 0; unit < 16; ++unit) { if (fp->mesa_program.Base.ShadowSamplers & (1 << unit)) { - struct gl_texture_object* tex = r300->radeon.glCtx->Texture.Unit[unit]._Current; + struct gl_texture_object* tex = r600->radeon.glCtx->Texture.Unit[unit]._Current; state->unit[unit].depth_texture_mode = build_dtm(tex->DepthMode); state->unit[unit].texture_compare_func = build_func(tex->CompareFunc); @@ -439,12 +439,12 @@ static void build_state( static void dump_program(struct r500_fragment_program_code *code); -void r500TranslateFragmentShader(r300ContextPtr r300, +void r500TranslateFragmentShader(r600ContextPtr r600, struct r500_fragment_program *fp) { struct r500_fragment_program_external_state state; - build_state(r300, fp, &state); + build_state(r600, fp, &state); if (_mesa_memcmp(&fp->state, &state, sizeof(state))) { /* TODO: cache compiled programs */ fp->translated = GL_FALSE; @@ -454,10 +454,10 @@ void r500TranslateFragmentShader(r300ContextPtr r300, if (!fp->translated) { struct r500_fragment_program_compiler compiler; - compiler.r300 = r300; + compiler.r600 = r600; compiler.fp = fp; compiler.code = &fp->code; - compiler.program = _mesa_clone_program(r300->radeon.glCtx, &fp->mesa_program.Base); + compiler.program = _mesa_clone_program(r600->radeon.glCtx, &fp->mesa_program.Base); if (RADEON_DEBUG & DEBUG_PIXEL) { _mesa_printf("Compiler: Initial program:\n"); @@ -472,7 +472,7 @@ void r500TranslateFragmentShader(r300ContextPtr r300, { &radeonTransformDeriv, 0 }, { &radeonTransformTrigScale, 0 } }; - radeonLocalTransform(r300->radeon.glCtx, compiler.program, + radeonLocalTransform(r600->radeon.glCtx, compiler.program, 4, transformations); if (RADEON_DEBUG & DEBUG_PIXEL) { @@ -486,7 +486,7 @@ void r500TranslateFragmentShader(r300ContextPtr r300, .BuildSwizzle = &nqssadce_build_swizzle, .RewriteDepthOut = GL_TRUE }; - radeonNqssaDce(r300->radeon.glCtx, compiler.program, &nqssadce); + radeonNqssaDce(r600->radeon.glCtx, compiler.program, &nqssadce); if (RADEON_DEBUG & DEBUG_PIXEL) { _mesa_printf("Compiler: after NqSSA-DCE:\n"); @@ -500,9 +500,9 @@ void r500TranslateFragmentShader(r300ContextPtr r300, fp->mesa_program.Base.Parameters = compiler.program->Parameters; compiler.program->Parameters = 0; - _mesa_reference_program(r300->radeon.glCtx, &compiler.program, 0); + _mesa_reference_program(r600->radeon.glCtx, &compiler.program, 0); - r300UpdateStateParameters(r300->radeon.glCtx, _NEW_PROGRAM); + r600UpdateStateParameters(r600->radeon.glCtx, _NEW_PROGRAM); if (RADEON_DEBUG & DEBUG_PIXEL) { if (fp->translated) { @@ -513,7 +513,7 @@ void r500TranslateFragmentShader(r300ContextPtr r300, } - update_params(r300, fp); + update_params(r600, fp); } diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.h b/src/mesa/drivers/dri/r600/r700_fragprog.h index e48cb60a54..c19ad181e4 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.h +++ b/src/mesa/drivers/dri/r600/r700_fragprog.h @@ -47,11 +47,11 @@ struct r500_fragment_program; -extern void r500TranslateFragmentShader(r300ContextPtr r300, +extern void r500TranslateFragmentShader(r600ContextPtr r600, struct r500_fragment_program *fp); struct r500_fragment_program_compiler { - r300ContextPtr r300; + r600ContextPtr r600; struct r500_fragment_program *fp; struct r500_fragment_program_code *code; struct gl_program *program; diff --git a/src/mesa/drivers/dri/r600/r700_fragprog_emit.c b/src/mesa/drivers/dri/r600/r700_fragprog_emit.c index ccffd7c28e..425015195d 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog_emit.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog_emit.c @@ -308,7 +308,7 @@ GLboolean r500FragmentProgramEmit(struct r500_fragment_program_compiler *compile code->inst_offset = 0; code->inst_end = -1; - if (!radeonPairProgram(compiler->r300->radeon.glCtx, compiler->program, &pair_handler, compiler)) + if (!radeonPairProgram(compiler->r600->radeon.glCtx, compiler->program, &pair_handler, compiler)) return GL_FALSE; if ((code->inst[code->inst_end].inst0 & R500_INST_TYPE_MASK) != R500_INST_TYPE_OUT) { diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index ef1f84634b..08a24a2c2b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -398,15 +398,15 @@ static const __DRItexBufferExtension r300TexBufferExtension = { #endif #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) -static const __DRItexOffsetExtension r300texOffsetExtension = { +static const __DRItexOffsetExtension r600texOffsetExtension = { { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, - r300SetTexOffset, + r600SetTexOffset, }; -static const __DRItexBufferExtension r300TexBufferExtension = { +static const __DRItexBufferExtension r600TexBufferExtension = { { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, - r300SetTexBuffer, - r300SetTexBuffer2, + r600SetTexBuffer, + r600SetTexBuffer2, }; #endif @@ -1201,7 +1201,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) #endif #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) - screen->extensions[i++] = &r300texOffsetExtension.base; + screen->extensions[i++] = &r600texOffsetExtension.base; #endif } @@ -1334,7 +1334,7 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv) #endif #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) - screen->extensions[i++] = &r300TexBufferExtension.base; + screen->extensions[i++] = &r600TexBufferExtension.base; #endif screen->extensions[i++] = NULL; @@ -1532,7 +1532,7 @@ static GLboolean radeonCreateContext(const __GLcontextModes * glVisual, radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) if (IS_R600_CLASS(screen)) - return r300CreateContext(glVisual, driContextPriv, sharedContextPriv); + return r600CreateContext(glVisual, driContextPriv, sharedContextPriv); #endif #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) -- cgit v1.2.3 From c0419f190c836130932164ac47cfb53de668d423 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 10 Apr 2009 16:36:18 -0400 Subject: Remove r500 stuff --- src/mesa/drivers/dri/r600/Makefile | 2 - src/mesa/drivers/dri/r600/r600_cmdbuf.c | 252 ++------ src/mesa/drivers/dri/r600/r600_context.c | 26 +- src/mesa/drivers/dri/r600/r600_ioctl.c | 206 ++----- src/mesa/drivers/dri/r600/r600_reg.h | 801 ------------------------- src/mesa/drivers/dri/r600/r600_render.c | 13 +- src/mesa/drivers/dri/r600/r600_shader.c | 33 +- src/mesa/drivers/dri/r600/r600_state.c | 432 ++----------- src/mesa/drivers/dri/r600/r600_texstate.c | 12 - src/mesa/drivers/dri/r600/r700_fragprog.c | 719 ---------------------- src/mesa/drivers/dri/r600/r700_fragprog_emit.c | 327 ---------- 11 files changed, 172 insertions(+), 2651 deletions(-) delete mode 100644 src/mesa/drivers/dri/r600/r700_fragprog.c delete mode 100644 src/mesa/drivers/dri/r600/r700_fragprog_emit.c (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/Makefile b/src/mesa/drivers/dri/r600/Makefile index e1fc4061ad..528396df27 100644 --- a/src/mesa/drivers/dri/r600/Makefile +++ b/src/mesa/drivers/dri/r600/Makefile @@ -51,8 +51,6 @@ DRIVER_SOURCES = \ r600_fragprog.c \ r600_fragprog_swizzle.c \ r600_fragprog_emit.c \ - r700_fragprog.c \ - r700_fragprog_emit.c \ r600_shader.c \ r600_emit.c \ r600_swtcl.c \ diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 73de822397..e379984417 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -75,7 +75,6 @@ static unsigned packet0_count(r600ContextPtr r600, uint32_t *pkt) } #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count) -#define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count) void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom) { @@ -121,48 +120,6 @@ void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom) } } -void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom) -{ - r600ContextPtr r600 = R600_CONTEXT(ctx); - BATCH_LOCALS(&r600->radeon); - drm_r300_cmd_header_t cmd; - uint32_t addr, ndw, i, sz; - int type, clamp, stride; - - if (!r600->radeon.radeonScreen->kernel_mm) { - uint32_t dwords; - dwords = (*atom->check) (ctx, atom); - BEGIN_BATCH_NO_AUTOSTATE(dwords); - OUT_BATCH_TABLE(atom->cmd, dwords); - END_BATCH(); - return; - } - - cmd.u = atom->cmd[0]; - sz = cmd.r500fp.count; - addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo; - type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE); - clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP); - - addr |= (type << 16); - addr |= (clamp << 17); - - stride = type ? 4 : 6; - - ndw = sz * stride; - if (ndw) { - - BEGIN_BATCH_NO_AUTOSTATE(3 + ndw); - OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0)); - OUT_BATCH(addr); - OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR); - for (i = 0; i < ndw; i++) { - OUT_BATCH(atom->cmd[i+1]); - } - END_BATCH(); - } -} - static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) { r600ContextPtr r600 = R600_CONTEXT(ctx); @@ -332,22 +289,6 @@ int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom) return cnt ? (cnt * 4) + 1 : 0; } -int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom) -{ - int cnt; - - cnt = r500fp_count(atom->cmd); - return cnt ? (cnt * 6) + 1 : 0; -} - -int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom) -{ - int cnt; - - cnt = r500fp_count(atom->cmd); - return cnt ? (cnt * 4) + 1 : 0; -} - #define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \ do { \ r600->hw.ATOM.cmd_size = (SZ); \ @@ -366,16 +307,8 @@ int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom) void r600InitCmdBuf(r600ContextPtr r600) { int mtu; - int has_tcl = 1; - int is_r500 = 0; int i; - if (!(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) - has_tcl = 0; - - if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) - is_r500 = 1; - r600->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */ mtu = r600->radeon.glCtx->Const.MaxTextureUnits; @@ -394,11 +327,7 @@ void r600InitCmdBuf(r600ContextPtr r600) r600->hw.vap_cntl.cmd[R600_VAP_CNTL_FLUSH] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PVS_STATE_FLUSH_REG, 1); r600->hw.vap_cntl.cmd[R600_VAP_CNTL_FLUSH_1] = 0; r600->hw.vap_cntl.cmd[R600_VAP_CNTL_CMD] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_CNTL, 1); - if (is_r500) { - ALLOC_STATE(vap_index_offset, always, 2, 0); - r600->hw.vap_index_offset.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1); - r600->hw.vap_index_offset.cmd[1] = 0; - } + ALLOC_STATE(vte, always, 3, 0); r600->hw.vte.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SE_VTE_CNTL, 2); ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0); @@ -416,24 +345,20 @@ void r600InitCmdBuf(r600ContextPtr r600) ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0); r600->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE); - if (has_tcl) { - ALLOC_STATE(vap_clip_cntl, always, 2, 0); - r600->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_CLIP_CNTL, 1); - ALLOC_STATE(vap_clip, always, 5, 0); - r600->hw.vap_clip.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_GB_VERT_CLIP_ADJ, 4); - ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0); - r600->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1); - } + ALLOC_STATE(vap_clip_cntl, always, 2, 0); + r600->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_CLIP_CNTL, 1); + ALLOC_STATE(vap_clip, always, 5, 0); + r600->hw.vap_clip.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_GB_VERT_CLIP_ADJ, 4); + ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0); + r600->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1); ALLOC_STATE(vof, always, R600_VOF_CMDSIZE, 0); r600->hw.vof.cmd[R600_VOF_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_OUTPUT_VTX_FMT_0, 2); - if (has_tcl) { - ALLOC_STATE(pvs, always, R600_PVS_CMDSIZE, 0); - r600->hw.pvs.cmd[R600_PVS_CMD_0] = - cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PVS_CODE_CNTL_0, 3); - } + ALLOC_STATE(pvs, always, R600_PVS_CMDSIZE, 0); + r600->hw.pvs.cmd[R600_PVS_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PVS_CODE_CNTL_0, 3); ALLOC_STATE(gb_enable, always, 2, 0); r600->hw.gb_enable.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GB_ENABLE, 1); @@ -472,24 +397,12 @@ void r600InitCmdBuf(r600ContextPtr r600) r600->hw.su_depth_scale.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_DEPTH_SCALE, 2); ALLOC_STATE(rc, always, R600_RC_CMDSIZE, 0); r600->hw.rc.cmd[R600_RC_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_COUNT, 2); - if (is_r500) { - ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0); - r600->hw.ri.cmd[R600_RI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R500_RS_IP_0, 16); - for (i = 0; i < 8; i++) { - r600->hw.ri.cmd[R600_RI_CMD_0 + i +1] = - (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) | - (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) | - (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | - (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT); - } - ALLOC_STATE(rr, variable, R600_RR_CMDSIZE, 0); - r600->hw.rr.cmd[R600_RR_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R500_RS_INST_0, 1); - } else { - ALLOC_STATE(ri, always, R600_RI_CMDSIZE, 0); - r600->hw.ri.cmd[R600_RI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_IP_0, 8); - ALLOC_STATE(rr, variable, R600_RR_CMDSIZE, 0); - r600->hw.rr.cmd[R600_RR_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_INST_0, 1); - } + + ALLOC_STATE(ri, always, R600_RI_CMDSIZE, 0); + r600->hw.ri.cmd[R600_RI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_IP_0, 8); + ALLOC_STATE(rr, variable, R600_RR_CMDSIZE, 0); + r600->hw.rr.cmd[R600_RR_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_INST_0, 1); + ALLOC_STATE(sc_hyperz, always, 3, 0); r600->hw.sc_hyperz.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SC_HYPERZ, 2); ALLOC_STATE(sc_screendoor, always, 2, 0); @@ -497,41 +410,24 @@ void r600InitCmdBuf(r600ContextPtr r600) ALLOC_STATE(us_out_fmt, always, 6, 0); r600->hw.us_out_fmt.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_OUT_FMT, 5); - if (is_r500) { - ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0); - r600->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R500_US_CONFIG, 2); - r600->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO; - r600->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r600->radeon.radeonScreen, R500_US_CODE_ADDR, 3); - r600->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r600->radeon.radeonScreen, R500_US_FC_CTRL, 1); - r600->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */ - - ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0); - r600->hw.r500fp.cmd[R600_FPI_CMD_0] = - cmdr500fp(r600->radeon.radeonScreen, 0, 0, 0, 0); - r600->hw.r500fp.emit = emit_r500fp; - ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0); - r600->hw.r500fp_const.cmd[R600_FPI_CMD_0] = - cmdr500fp(r600->radeon.radeonScreen, 0, 0, 1, 0); - r600->hw.r500fp_const.emit = emit_r500fp; - } else { - ALLOC_STATE(fp, always, R600_FP_CMDSIZE, 0); - r600->hw.fp.cmd[R600_FP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_CONFIG, 3); - r600->hw.fp.cmd[R600_FP_CMD_1] = cmdpacket0(r600->radeon.radeonScreen, R600_US_CODE_ADDR_0, 4); - - ALLOC_STATE(fpt, variable, R600_FPT_CMDSIZE, 0); - r600->hw.fpt.cmd[R600_FPT_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_TEX_INST_0, 0); - - ALLOC_STATE(fpi[0], variable, R600_FPI_CMDSIZE, 0); - r600->hw.fpi[0].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_RGB_INST_0, 1); - ALLOC_STATE(fpi[1], variable, R600_FPI_CMDSIZE, 1); - r600->hw.fpi[1].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_RGB_ADDR_0, 1); - ALLOC_STATE(fpi[2], variable, R600_FPI_CMDSIZE, 2); - r600->hw.fpi[2].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_ALPHA_INST_0, 1); - ALLOC_STATE(fpi[3], variable, R600_FPI_CMDSIZE, 3); - r600->hw.fpi[3].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_ALPHA_ADDR_0, 1); - ALLOC_STATE(fpp, variable, R600_FPP_CMDSIZE, 0); - r600->hw.fpp.cmd[R600_FPP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_PFS_PARAM_0_X, 0); - } + ALLOC_STATE(fp, always, R600_FP_CMDSIZE, 0); + r600->hw.fp.cmd[R600_FP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_CONFIG, 3); + r600->hw.fp.cmd[R600_FP_CMD_1] = cmdpacket0(r600->radeon.radeonScreen, R600_US_CODE_ADDR_0, 4); + + ALLOC_STATE(fpt, variable, R600_FPT_CMDSIZE, 0); + r600->hw.fpt.cmd[R600_FPT_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_TEX_INST_0, 0); + + ALLOC_STATE(fpi[0], variable, R600_FPI_CMDSIZE, 0); + r600->hw.fpi[0].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_RGB_INST_0, 1); + ALLOC_STATE(fpi[1], variable, R600_FPI_CMDSIZE, 1); + r600->hw.fpi[1].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_RGB_ADDR_0, 1); + ALLOC_STATE(fpi[2], variable, R600_FPI_CMDSIZE, 2); + r600->hw.fpi[2].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_ALPHA_INST_0, 1); + ALLOC_STATE(fpi[3], variable, R600_FPI_CMDSIZE, 3); + r600->hw.fpi[3].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_ALPHA_ADDR_0, 1); + ALLOC_STATE(fpp, variable, R600_FPP_CMDSIZE, 0); + r600->hw.fpp.cmd[R600_FPP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_PFS_PARAM_0_X, 0); + ALLOC_STATE(fogs, always, R600_FOGS_CMDSIZE, 0); r600->hw.fogs.cmd[R600_FOGS_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_FOG_BLEND, 1); ALLOC_STATE(fogc, always, R600_FOGC_CMDSIZE, 0); @@ -546,13 +442,10 @@ void r600InitCmdBuf(r600ContextPtr r600) r600->hw.bld.cmd[R600_BLD_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_CBLEND, 2); ALLOC_STATE(cmk, always, R600_CMK_CMDSIZE, 0); r600->hw.cmk.cmd[R600_CMK_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1); - if (is_r500) { - ALLOC_STATE(blend_color, always, 3, 0); - r600->hw.blend_color.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2); - } else { - ALLOC_STATE(blend_color, always, 2, 0); - r600->hw.blend_color.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_BLEND_COLOR, 1); - } + + ALLOC_STATE(blend_color, always, 2, 0); + r600->hw.blend_color.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_BLEND_COLOR, 1); + ALLOC_STATE(rop, always, 2, 0); r600->hw.rop.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_ROPCNTL, 1); ALLOC_STATE(cb, always, R600_CB_CMDSIZE, 0); @@ -561,8 +454,7 @@ void r600InitCmdBuf(r600ContextPtr r600) r600->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_DITHER_CTL, 9); ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0); r600->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_AARESOLVE_CTL, 1); - ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0); - r600->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2); + ALLOC_STATE(zs, always, R600_ZS_CMDSIZE, 0); r600->hw.zs.cmd[R600_ZS_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_ZB_CNTL, 3); @@ -583,51 +475,27 @@ void r600InitCmdBuf(r600ContextPtr r600) ALLOC_STATE(zb_hiz_pitch, always, 2, 0); r600->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_ZB_HIZ_PITCH, 1); - /* VPU only on TCL */ - if (has_tcl) { - int i; - ALLOC_STATE(vpi, vpu, R600_VPI_CMDSIZE, 0); - r600->hw.vpi.cmd[0] = - cmdvpu(r600->radeon.radeonScreen, R600_PVS_CODE_START, 0); - r600->hw.vpi.emit = emit_vpu; - - if (is_r500) { - ALLOC_STATE(vpp, vpu, R600_VPP_CMDSIZE, 0); - r600->hw.vpp.cmd[0] = - cmdvpu(r600->radeon.radeonScreen, R500_PVS_CONST_START, 0); - r600->hw.vpp.emit = emit_vpu; - - ALLOC_STATE(vps, vpu, R600_VPS_CMDSIZE, 0); - r600->hw.vps.cmd[0] = - cmdvpu(r600->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1); - r600->hw.vps.emit = emit_vpu; - - for (i = 0; i < 6; i++) { - ALLOC_STATE(vpucp[i], vpu, R600_VPUCP_CMDSIZE, 0); - r600->hw.vpucp[i].cmd[0] = - cmdvpu(r600->radeon.radeonScreen, - R500_PVS_UCP_START + i, 1); - r600->hw.vpucp[i].emit = emit_vpu; - } - } else { - ALLOC_STATE(vpp, vpu, R600_VPP_CMDSIZE, 0); - r600->hw.vpp.cmd[0] = - cmdvpu(r600->radeon.radeonScreen, R600_PVS_CONST_START, 0); - r600->hw.vpp.emit = emit_vpu; - - ALLOC_STATE(vps, vpu, R600_VPS_CMDSIZE, 0); - r600->hw.vps.cmd[0] = - cmdvpu(r600->radeon.radeonScreen, R600_POINT_VPORT_SCALE_OFFSET, 1); - r600->hw.vps.emit = emit_vpu; - - for (i = 0; i < 6; i++) { - ALLOC_STATE(vpucp[i], vpu, R600_VPUCP_CMDSIZE, 0); - r600->hw.vpucp[i].cmd[0] = - cmdvpu(r600->radeon.radeonScreen, - R600_PVS_UCP_START + i, 1); - r600->hw.vpucp[i].emit = emit_vpu; - } - } + ALLOC_STATE(vpi, vpu, R600_VPI_CMDSIZE, 0); + r600->hw.vpi.cmd[0] = + cmdvpu(r600->radeon.radeonScreen, R600_PVS_CODE_START, 0); + r600->hw.vpi.emit = emit_vpu; + + ALLOC_STATE(vpp, vpu, R600_VPP_CMDSIZE, 0); + r600->hw.vpp.cmd[0] = + cmdvpu(r600->radeon.radeonScreen, R600_PVS_CONST_START, 0); + r600->hw.vpp.emit = emit_vpu; + + ALLOC_STATE(vps, vpu, R600_VPS_CMDSIZE, 0); + r600->hw.vps.cmd[0] = + cmdvpu(r600->radeon.radeonScreen, R600_POINT_VPORT_SCALE_OFFSET, 1); + r600->hw.vps.emit = emit_vpu; + + for (i = 0; i < 6; i++) { + ALLOC_STATE(vpucp[i], vpu, R600_VPUCP_CMDSIZE, 0); + r600->hw.vpucp[i].cmd[0] = + cmdvpu(r600->radeon.radeonScreen, + R600_PVS_UCP_START + i, 1); + r600->hw.vpucp[i].emit = emit_vpu; } /* Textures */ diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 60b14fb706..6754acba4d 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -345,10 +345,8 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, ctx->Const.MaxTextureMaxAnisotropy = 16.0; ctx->Const.MaxTextureLodBias = 16.0; - if (screen->chip_family >= CHIP_FAMILY_RV515) { - ctx->Const.MaxTextureLevels = 13; - ctx->Const.MaxTextureRectSize = 4096; - } + ctx->Const.MaxTextureLevels = 13; + ctx->Const.MaxTextureRectSize = 4096; ctx->Const.MinPointSize = 1.0; ctx->Const.MinPointSizeAA = 1.0; @@ -394,17 +392,15 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, _tnl_allow_vertex_fog(ctx, GL_TRUE); /* currently bogus data */ - if (screen->chip_flags & RADEON_CHIPSET_TCL) { - ctx->Const.VertexProgram.MaxInstructions = VSF_MAX_FRAGMENT_LENGTH / 4; - ctx->Const.VertexProgram.MaxNativeInstructions = - VSF_MAX_FRAGMENT_LENGTH / 4; - ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */ - ctx->Const.VertexProgram.MaxTemps = 32; - ctx->Const.VertexProgram.MaxNativeTemps = - /*VSF_MAX_FRAGMENT_TEMPS */ 32; - ctx->Const.VertexProgram.MaxNativeParameters = 256; /* r420 */ - ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; - } + ctx->Const.VertexProgram.MaxInstructions = VSF_MAX_FRAGMENT_LENGTH / 4; + ctx->Const.VertexProgram.MaxNativeInstructions = + VSF_MAX_FRAGMENT_LENGTH / 4; + ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */ + ctx->Const.VertexProgram.MaxTemps = 32; + ctx->Const.VertexProgram.MaxNativeTemps = + /*VSF_MAX_FRAGMENT_TEMPS */ 32; + ctx->Const.VertexProgram.MaxNativeParameters = 256; /* r420 */ + ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; ctx->Const.FragmentProgram.MaxNativeTemps = PFS_NUM_TEMP_REGS; ctx->Const.FragmentProgram.MaxNativeAttribs = 11; /* copy i915... */ diff --git a/src/mesa/drivers/dri/r600/r600_ioctl.c b/src/mesa/drivers/dri/r600/r600_ioctl.c index 7e180a1a6e..f93970e9f5 100644 --- a/src/mesa/drivers/dri/r600/r600_ioctl.c +++ b/src/mesa/drivers/dri/r600/r600_ioctl.c @@ -215,16 +215,8 @@ static void r600EmitClearState(GLcontext * ctx) BATCH_LOCALS(&r600->radeon); __DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable; int i; - int has_tcl = 1; - int is_r500 = 0; GLuint vap_cntl; - if (!(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) - has_tcl = 0; - - if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) - is_r500 = 1; - /* State atom dirty tracking is a little subtle here. * * On the one hand, we need to make sure base state is emitted @@ -243,12 +235,9 @@ static void r600EmitClearState(GLcontext * ctx) */ BEGIN_BATCH(31); OUT_BATCH_REGSEQ(R600_VAP_PROG_STREAM_CNTL_0, 1); - if (!has_tcl) - OUT_BATCH(((((0 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_0_SHIFT) | - ((R600_LAST_VEC | (2 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_1_SHIFT))); - else - OUT_BATCH(((((0 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_0_SHIFT) | - ((R600_LAST_VEC | (1 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_1_SHIFT))); + + OUT_BATCH(((((0 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_0_SHIFT) | + ((R600_LAST_VEC | (1 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_1_SHIFT))); OUT_BATCH_REGVAL(R600_FG_FOG_BLEND, 0); OUT_BATCH_REGVAL(R600_VAP_PROG_STREAM_CNTL_EXT_0, @@ -314,13 +303,11 @@ static void r600EmitClearState(GLcontext * ctx) R600_STATECHANGE(r600, bld); R600_STATECHANGE(r600, ps); - if (has_tcl) { - R600_STATECHANGE(r600, vap_clip_cntl); + R600_STATECHANGE(r600, vap_clip_cntl); - BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH_REGVAL(R600_VAP_CLIP_CNTL, R600_PS_UCP_MODE_CLIP_AS_TRIFAN | R600_CLIP_DISABLE); - END_BATCH(); - } + BEGIN_BATCH_NO_AUTOSTATE(2); + OUT_BATCH_REGVAL(R600_VAP_CLIP_CNTL, R600_PS_UCP_MODE_CLIP_AS_TRIFAN | R600_CLIP_DISABLE); + END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(2); OUT_BATCH_REGVAL(R600_GA_POINT_SIZE, @@ -328,146 +315,57 @@ static void r600EmitClearState(GLcontext * ctx) ((dPriv->h * 6) << R600_POINTSIZE_Y_SHIFT)); END_BATCH(); - if (!is_r500) { - R600_STATECHANGE(r600, ri); - R600_STATECHANGE(r600, rc); - R600_STATECHANGE(r600, rr); - - BEGIN_BATCH(14); - OUT_BATCH_REGSEQ(R600_RS_IP_0, 8); - for (i = 0; i < 8; ++i) - OUT_BATCH(R600_RS_SEL_T(1) | R600_RS_SEL_R(2) | R600_RS_SEL_Q(3)); - OUT_BATCH_REGSEQ(R600_RS_COUNT, 2); - OUT_BATCH((1 << R600_IC_COUNT_SHIFT) | R600_HIRES_EN); - OUT_BATCH(0x0); + R600_STATECHANGE(r600, ri); + R600_STATECHANGE(r600, rc); + R600_STATECHANGE(r600, rr); - OUT_BATCH_REGVAL(R600_RS_INST_0, R600_RS_INST_COL_CN_WRITE); - END_BATCH(); - } else { - R600_STATECHANGE(r600, ri); - R600_STATECHANGE(r600, rc); - R600_STATECHANGE(r600, rr); - - BEGIN_BATCH(14); - OUT_BATCH_REGSEQ(R500_RS_IP_0, 8); - for (i = 0; i < 8; ++i) { - OUT_BATCH((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) | - (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) | - (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | - (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)); - } + BEGIN_BATCH(14); + OUT_BATCH_REGSEQ(R600_RS_IP_0, 8); + for (i = 0; i < 8; ++i) + OUT_BATCH(R600_RS_SEL_T(1) | R600_RS_SEL_R(2) | R600_RS_SEL_Q(3)); - OUT_BATCH_REGSEQ(R600_RS_COUNT, 2); - OUT_BATCH((1 << R600_IC_COUNT_SHIFT) | R600_HIRES_EN); - OUT_BATCH(0x0); - - OUT_BATCH_REGVAL(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE); - END_BATCH(); - } + OUT_BATCH_REGSEQ(R600_RS_COUNT, 2); + OUT_BATCH((1 << R600_IC_COUNT_SHIFT) | R600_HIRES_EN); + OUT_BATCH(0x0); - if (!is_r500) { - R600_STATECHANGE(r600, fp); - R600_STATECHANGE(r600, fpi[0]); - R600_STATECHANGE(r600, fpi[1]); - R600_STATECHANGE(r600, fpi[2]); - R600_STATECHANGE(r600, fpi[3]); - - BEGIN_BATCH(17); - OUT_BATCH_REGSEQ(R600_US_CONFIG, 3); - OUT_BATCH(0x0); - OUT_BATCH(0x0); - OUT_BATCH(0x0); - OUT_BATCH_REGSEQ(R600_US_CODE_ADDR_0, 4); - OUT_BATCH(0x0); - OUT_BATCH(0x0); - OUT_BATCH(0x0); - OUT_BATCH(R600_RGBA_OUT); - - OUT_BATCH_REGVAL(R600_US_ALU_RGB_INST_0, - FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO))); - OUT_BATCH_REGVAL(R600_US_ALU_RGB_ADDR_0, - FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0)); - OUT_BATCH_REGVAL(R600_US_ALU_ALPHA_INST_0, - FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO))); - OUT_BATCH_REGVAL(R600_US_ALU_ALPHA_ADDR_0, - FP_SELA(0, NO, W, FP_TMP(0), 0, 0)); - END_BATCH(); - } else { - struct radeon_state_atom r500fp; - uint32_t _cmd[10]; + OUT_BATCH_REGVAL(R600_RS_INST_0, R600_RS_INST_COL_CN_WRITE); + END_BATCH(); - R600_STATECHANGE(r600, fp); - R600_STATECHANGE(r600, r500fp); - - BEGIN_BATCH(7); - OUT_BATCH_REGSEQ(R500_US_CONFIG, 2); - OUT_BATCH(R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); - OUT_BATCH(0x0); - OUT_BATCH_REGSEQ(R500_US_CODE_ADDR, 3); - OUT_BATCH(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1)); - OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1)); - OUT_BATCH(R500_US_CODE_OFFSET_ADDR(0)); - END_BATCH(); + R600_STATECHANGE(r600, fp); + R600_STATECHANGE(r600, fpi[0]); + R600_STATECHANGE(r600, fpi[1]); + R600_STATECHANGE(r600, fpi[2]); + R600_STATECHANGE(r600, fpi[3]); - r500fp.check = check_r500fp; - r500fp.cmd = _cmd; - r500fp.cmd[0] = cmdr500fp(r600->radeon.radeonScreen, 0, 1, 0, 0); - r500fp.cmd[1] = R500_INST_TYPE_OUT | - R500_INST_TEX_SEM_WAIT | - R500_INST_LAST | - R500_INST_RGB_OMASK_R | - R500_INST_RGB_OMASK_G | - R500_INST_RGB_OMASK_B | - R500_INST_ALPHA_OMASK | - R500_INST_RGB_CLAMP | - R500_INST_ALPHA_CLAMP; - r500fp.cmd[2] = R500_RGB_ADDR0(0) | - R500_RGB_ADDR1(0) | - R500_RGB_ADDR1_CONST | - R500_RGB_ADDR2(0) | - R500_RGB_ADDR2_CONST; - r500fp.cmd[3] = R500_ALPHA_ADDR0(0) | - R500_ALPHA_ADDR1(0) | - R500_ALPHA_ADDR1_CONST | - R500_ALPHA_ADDR2(0) | - R500_ALPHA_ADDR2_CONST; - r500fp.cmd[4] = R500_ALU_RGB_SEL_A_SRC0 | - R500_ALU_RGB_R_SWIZ_A_R | - R500_ALU_RGB_G_SWIZ_A_G | - R500_ALU_RGB_B_SWIZ_A_B | - R500_ALU_RGB_SEL_B_SRC0 | - R500_ALU_RGB_R_SWIZ_B_R | - R500_ALU_RGB_B_SWIZ_B_G | - R500_ALU_RGB_G_SWIZ_B_B; - r500fp.cmd[5] = R500_ALPHA_OP_CMP | - R500_ALPHA_SWIZ_A_A | - R500_ALPHA_SWIZ_B_A; - r500fp.cmd[6] = R500_ALU_RGBA_OP_CMP | - R500_ALU_RGBA_R_SWIZ_0 | - R500_ALU_RGBA_G_SWIZ_0 | - R500_ALU_RGBA_B_SWIZ_0 | - R500_ALU_RGBA_A_SWIZ_0; - - r500fp.cmd[7] = 0; - emit_r500fp(ctx, &r500fp); - } + BEGIN_BATCH(17); + OUT_BATCH_REGSEQ(R600_US_CONFIG, 3); + OUT_BATCH(0x0); + OUT_BATCH(0x0); + OUT_BATCH(0x0); + OUT_BATCH_REGSEQ(R600_US_CODE_ADDR_0, 4); + OUT_BATCH(0x0); + OUT_BATCH(0x0); + OUT_BATCH(0x0); + OUT_BATCH(R600_RGBA_OUT); + + OUT_BATCH_REGVAL(R600_US_ALU_RGB_INST_0, + FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO))); + OUT_BATCH_REGVAL(R600_US_ALU_RGB_ADDR_0, + FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0)); + OUT_BATCH_REGVAL(R600_US_ALU_ALPHA_INST_0, + FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO))); + OUT_BATCH_REGVAL(R600_US_ALU_ALPHA_ADDR_0, + FP_SELA(0, NO, W, FP_TMP(0), 0, 0)); + END_BATCH(); BEGIN_BATCH(2); OUT_BATCH_REGVAL(R600_VAP_PVS_STATE_FLUSH_REG, 0); END_BATCH(); - if (has_tcl) { - vap_cntl = ((10 << R600_PVS_NUM_SLOTS_SHIFT) | - (5 << R600_PVS_NUM_CNTLRS_SHIFT) | - (12 << R600_VF_MAX_VTX_NUM_SHIFT)); - if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) - vap_cntl |= R500_TCL_STATE_OPTIMIZATION; - } else { - vap_cntl = ((10 << R600_PVS_NUM_SLOTS_SHIFT) | - (5 << R600_PVS_NUM_CNTLRS_SHIFT) | - (5 << R600_VF_MAX_VTX_NUM_SHIFT)); - } + vap_cntl = ((10 << R600_PVS_NUM_SLOTS_SHIFT) | + (5 << R600_PVS_NUM_CNTLRS_SHIFT) | + (12 << R600_VF_MAX_VTX_NUM_SHIFT)); if (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515) vap_cntl |= (2 << R600_PVS_NUM_FPUS_SHIFT); @@ -490,9 +388,9 @@ static void r600EmitClearState(GLcontext * ctx) OUT_BATCH_REGVAL(R600_VAP_CNTL, vap_cntl); END_BATCH(); - if (has_tcl) { - struct radeon_state_atom vpu; - uint32_t _cmd[10]; + { + struct radeon_state_atom vpu; + uint32_t _cmd[10]; R600_STATECHANGE(r600, pvs); R600_STATECHANGE(r600, vpi); @@ -542,7 +440,7 @@ static void r600EmitClearState(GLcontext * ctx) } static void r600KernelClear(GLcontext *ctx, GLuint flags) -{ +{ r600ContextPtr r600 = R600_CONTEXT(ctx); __DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable; struct radeon_framebuffer *rfb = dPriv->driverPrivate; @@ -566,7 +464,7 @@ static void r600KernelClear(GLcontext *ctx, GLuint flags) r600ClearBuffer(r600, CLEARBUFFER_COLOR, rrb, NULL); bits = 0; } - + if (flags & BUFFER_BIT_FRONT_LEFT) { rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT); r600ClearBuffer(r600, bits | CLEARBUFFER_COLOR, rrb, rrbd); diff --git a/src/mesa/drivers/dri/r600/r600_reg.h b/src/mesa/drivers/dri/r600/r600_reg.h index bb5416e458..73ce069e4f 100644 --- a/src/mesa/drivers/dri/r600/r600_reg.h +++ b/src/mesa/drivers/dri/r600/r600_reg.h @@ -75,7 +75,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R600_VF_MAX_VTX_NUM_SHIFT 18 # define R600_GL_CLIP_SPACE_DEF (0 << 22) # define R600_DX_CLIP_SPACE_DEF (1 << 22) -# define R500_TCL_STATE_OPTIMIZATION (1 << 23) /* This register is written directly and also starts data section * in many 3d CP_PACKET3's @@ -112,7 +111,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* number of vertices */ # define R600_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16 -#define R500_VAP_INDEX_OFFSET 0x208c #define R600_VAP_OUTPUT_VTX_FMT_0 0x2090 # define R600_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0) @@ -365,17 +363,11 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #define R600_VAP_PVS_VECTOR_INDX_REG 0x2200 # define R600_PVS_CODE_START 0 # define R600_MAX_PVS_CODE_LINES 256 -# define R500_MAX_PVS_CODE_LINES 1024 # define R600_PVS_CONST_START 512 -# define R500_PVS_CONST_START 1024 # define R600_MAX_PVS_CONST_VECS 256 -# define R500_MAX_PVS_CONST_VECS 1024 # define R600_PVS_UCP_START 1024 -# define R500_PVS_UCP_START 1536 # define R600_POINT_VPORT_SCALE_OFFSET 1030 -# define R500_POINT_VPORT_SCALE_OFFSET 1542 # define R600_POINT_GEN_TEX_OFFSET 1031 -# define R500_POINT_GEN_TEX_OFFSET 1543 /* * These are obsolete defines form r600_context.h, but they might give some @@ -423,8 +415,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R600_CLIP_DISABLE (1 << 16) # define R600_UCP_CULL_ONLY_ENABLE (1 << 17) # define R600_BOUNDARY_EDGE_FLAG_ENABLE (1 << 18) -# define R500_COLOR2_IS_TEXTURE (1 << 20) -# define R500_COLOR3_IS_TEXTURE (1 << 21) /* These seem to be per-pixel and per-vertex X and Y clipping planes. The first * plane is per-pixel and the second plane is per-vertex. @@ -703,39 +693,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define GB_FIFO_SIZE1_SC_HIGHWATER_TEX_SHIFT 18 # define GB_FIFO_SIZE1_SC_HIGHWATER_TEX_MASK 0x00fc0000 -/* This table specifies the source location and format for up to 16 texture - * addresses (i[0]:i[15]) and four colors (c[0]:c[3]) - */ -#define R500_RS_IP_0 0x4074 -#define R500_RS_IP_1 0x4078 -#define R500_RS_IP_2 0x407C -#define R500_RS_IP_3 0x4080 -#define R500_RS_IP_4 0x4084 -#define R500_RS_IP_5 0x4088 -#define R500_RS_IP_6 0x408C -#define R500_RS_IP_7 0x4090 -#define R500_RS_IP_8 0x4094 -#define R500_RS_IP_9 0x4098 -#define R500_RS_IP_10 0x409C -#define R500_RS_IP_11 0x40A0 -#define R500_RS_IP_12 0x40A4 -#define R500_RS_IP_13 0x40A8 -#define R500_RS_IP_14 0x40AC -#define R500_RS_IP_15 0x40B0 -#define R500_RS_IP_PTR_K0 62 -#define R500_RS_IP_PTR_K1 63 -#define R500_RS_IP_TEX_PTR_S_SHIFT 0 -#define R500_RS_IP_TEX_PTR_T_SHIFT 6 -#define R500_RS_IP_TEX_PTR_R_SHIFT 12 -#define R500_RS_IP_TEX_PTR_Q_SHIFT 18 -#define R500_RS_IP_COL_PTR_SHIFT 24 -#define R500_RS_IP_COL_FMT_SHIFT 27 -# define R500_RS_COL_PTR(x) ((x) << 24) -# define R500_RS_COL_FMT(x) ((x) << 27) -/* gap */ -#define R500_RS_IP_OFFSET_DIS (0 << 31) -#define R500_RS_IP_OFFSET_EN (1 << 31) - /* gap */ /* Zero to flush caches. */ @@ -761,14 +718,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R600_TX_ENABLE_14 (1 << 14) # define R600_TX_ENABLE_15 (1 << 15) -#define R500_TX_FILTER_4 0x4110 -# define R500_TX_WEIGHT_1_SHIFT (0) -# define R500_TX_WEIGHT_0_SHIFT (11) -# define R500_TX_WEIGHT_PAIR (1<<22) -# define R500_TX_PHASE_SHIFT (23) -# define R500_TX_DIRECTION_HORIZONTAL (0<<27) -# define R500_TX_DIRECTION_VERITCAL (1<<27) - /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) */ #define R600_GA_POINT_S0 0x4200 @@ -802,18 +751,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R600_POINTSIZE_X_MASK 0xffff0000 # define R600_POINTSIZE_MAX (R600_POINTSIZE_Y_MASK / 6) -/* Blue fill color */ -#define R500_GA_FILL_R 0x4220 - -/* Blue fill color */ -#define R500_GA_FILL_G 0x4224 - -/* Blue fill color */ -#define R500_GA_FILL_B 0x4228 - -/* Alpha fill color */ -#define R500_GA_FILL_A 0x422c - /* Specifies maximum and minimum point & sprite sizes for per vertex size * specification. The lower part (15:0) is MIN and (31:16) is max. @@ -840,8 +777,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R600_GA_LINE_CNTL_END_TYPE_VER (1 << 16) # define R600_GA_LINE_CNTL_END_TYPE_SQR (2 << 16) /* horizontal or vertical depending upon slope */ # define R600_GA_LINE_CNTL_END_TYPE_COMP (3 << 16) /* Computed (perpendicular to slope) */ -# define R500_GA_LINE_CNTL_SORT_NO (0 << 18) -# define R500_GA_LINE_CNTL_SORT_MINX_MINY (1 << 18) /** TODO: looks wrong */ # define R600_LINESIZE_MAX (R600_GA_LINE_CNTL_WIDTH_MASK / 6) /** TODO: looks wrong */ @@ -857,108 +792,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R600_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_SHIFT 2 # define R600_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK 0xfffffffc -/* Used to load US instructions and constants */ -#define R500_GA_US_VECTOR_INDEX 0x4250 -# define R500_GA_US_VECTOR_INDEX_SHIFT 0 -# define R500_GA_US_VECTOR_INDEX_MASK 0x000000ff -# define R500_GA_US_VECTOR_INDEX_TYPE_INSTR (0 << 16) -# define R500_GA_US_VECTOR_INDEX_TYPE_CONST (1 << 16) -# define R500_GA_US_VECTOR_INDEX_CLAMP_NO (0 << 17) -# define R500_GA_US_VECTOR_INDEX_CLAMP_CONST (1 << 17) - -/* Data register for loading US instructions and constants */ -#define R500_GA_US_VECTOR_DATA 0x4254 - -/* Specifies color properties and mappings of textures. */ -#define R500_GA_COLOR_CONTROL_PS3 0x4258 -# define R500_TEX0_SHADING_PS3_SOLID (0 << 0) -# define R500_TEX0_SHADING_PS3_FLAT (1 << 0) -# define R500_TEX0_SHADING_PS3_GOURAUD (2 << 0) -# define R500_TEX1_SHADING_PS3_SOLID (0 << 2) -# define R500_TEX1_SHADING_PS3_FLAT (1 << 2) -# define R500_TEX1_SHADING_PS3_GOURAUD (2 << 2) -# define R500_TEX2_SHADING_PS3_SOLID (0 << 4) -# define R500_TEX2_SHADING_PS3_FLAT (1 << 4) -# define R500_TEX2_SHADING_PS3_GOURAUD (2 << 4) -# define R500_TEX3_SHADING_PS3_SOLID (0 << 6) -# define R500_TEX3_SHADING_PS3_FLAT (1 << 6) -# define R500_TEX3_SHADING_PS3_GOURAUD (2 << 6) -# define R500_TEX4_SHADING_PS3_SOLID (0 << 8) -# define R500_TEX4_SHADING_PS3_FLAT (1 << 8) -# define R500_TEX4_SHADING_PS3_GOURAUD (2 << 8) -# define R500_TEX5_SHADING_PS3_SOLID (0 << 10) -# define R500_TEX5_SHADING_PS3_FLAT (1 << 10) -# define R500_TEX5_SHADING_PS3_GOURAUD (2 << 10) -# define R500_TEX6_SHADING_PS3_SOLID (0 << 12) -# define R500_TEX6_SHADING_PS3_FLAT (1 << 12) -# define R500_TEX6_SHADING_PS3_GOURAUD (2 << 12) -# define R500_TEX7_SHADING_PS3_SOLID (0 << 14) -# define R500_TEX7_SHADING_PS3_FLAT (1 << 14) -# define R500_TEX7_SHADING_PS3_GOURAUD (2 << 14) -# define R500_TEX8_SHADING_PS3_SOLID (0 << 16) -# define R500_TEX8_SHADING_PS3_FLAT (1 << 16) -# define R500_TEX8_SHADING_PS3_GOURAUD (2 << 16) -# define R500_TEX9_SHADING_PS3_SOLID (0 << 18) -# define R500_TEX9_SHADING_PS3_FLAT (1 << 18) -# define R500_TEX9_SHADING_PS3_GOURAUD (2 << 18) -# define R500_TEX10_SHADING_PS3_SOLID (0 << 20) -# define R500_TEX10_SHADING_PS3_FLAT (1 << 20) -# define R500_TEX10_SHADING_PS3_GOURAUD (2 << 20) -# define R500_COLOR0_TEX_OVERRIDE_NO (0 << 22) -# define R500_COLOR0_TEX_OVERRIDE_TEX_0 (1 << 22) -# define R500_COLOR0_TEX_OVERRIDE_TEX_1 (2 << 22) -# define R500_COLOR0_TEX_OVERRIDE_TEX_2 (3 << 22) -# define R500_COLOR0_TEX_OVERRIDE_TEX_3 (4 << 22) -# define R500_COLOR0_TEX_OVERRIDE_TEX_4 (5 << 22) -# define R500_COLOR0_TEX_OVERRIDE_TEX_5 (6 << 22) -# define R500_COLOR0_TEX_OVERRIDE_TEX_6 (7 << 22) -# define R500_COLOR0_TEX_OVERRIDE_TEX_7 (8 << 22) -# define R500_COLOR0_TEX_OVERRIDE_TEX_8_C2 (9 << 22) -# define R500_COLOR0_TEX_OVERRIDE_TEX_9_C3 (10 << 22) -# define R500_COLOR1_TEX_OVERRIDE_NO (0 << 26) -# define R500_COLOR1_TEX_OVERRIDE_TEX_0 (1 << 26) -# define R500_COLOR1_TEX_OVERRIDE_TEX_1 (2 << 26) -# define R500_COLOR1_TEX_OVERRIDE_TEX_2 (3 << 26) -# define R500_COLOR1_TEX_OVERRIDE_TEX_3 (4 << 26) -# define R500_COLOR1_TEX_OVERRIDE_TEX_4 (5 << 26) -# define R500_COLOR1_TEX_OVERRIDE_TEX_5 (6 << 26) -# define R500_COLOR1_TEX_OVERRIDE_TEX_6 (7 << 26) -# define R500_COLOR1_TEX_OVERRIDE_TEX_7 (8 << 26) -# define R500_COLOR1_TEX_OVERRIDE_TEX_8_C2 (9 << 26) -# define R500_COLOR1_TEX_OVERRIDE_TEX_9_C3 (10 << 26) - -/* Returns idle status of various G3D block, captured when GA_IDLE written or - * when hard or soft reset asserted. - */ -#define R500_GA_IDLE 0x425c -# define R500_GA_IDLE_PIPE3_Z_IDLE (0 << 0) -# define R500_GA_IDLE_PIPE2_Z_IDLE (0 << 1) -# define R500_GA_IDLE_PIPE3_CD_IDLE (0 << 2) -# define R500_GA_IDLE_PIPE2_CD_IDLE (0 << 3) -# define R500_GA_IDLE_PIPE3_FG_IDLE (0 << 4) -# define R500_GA_IDLE_PIPE2_FG_IDLE (0 << 5) -# define R500_GA_IDLE_PIPE3_US_IDLE (0 << 6) -# define R500_GA_IDLE_PIPE2_US_IDLE (0 << 7) -# define R500_GA_IDLE_PIPE3_SC_IDLE (0 << 8) -# define R500_GA_IDLE_PIPE2_SC_IDLE (0 << 9) -# define R500_GA_IDLE_PIPE3_RS_IDLE (0 << 10) -# define R500_GA_IDLE_PIPE2_RS_IDLE (0 << 11) -# define R500_GA_IDLE_PIPE1_Z_IDLE (0 << 12) -# define R500_GA_IDLE_PIPE0_Z_IDLE (0 << 13) -# define R500_GA_IDLE_PIPE1_CD_IDLE (0 << 14) -# define R500_GA_IDLE_PIPE0_CD_IDLE (0 << 15) -# define R500_GA_IDLE_PIPE1_FG_IDLE (0 << 16) -# define R500_GA_IDLE_PIPE0_FG_IDLE (0 << 17) -# define R500_GA_IDLE_PIPE1_US_IDLE (0 << 18) -# define R500_GA_IDLE_PIPE0_US_IDLE (0 << 19) -# define R500_GA_IDLE_PIPE1_SC_IDLE (0 << 20) -# define R500_GA_IDLE_PIPE0_SC_IDLE (0 << 21) -# define R500_GA_IDLE_PIPE1_RS_IDLE (0 << 22) -# define R500_GA_IDLE_PIPE0_RS_IDLE (0 << 23) -# define R500_GA_IDLE_SU_IDLE (0 << 24) -# define R500_GA_IDLE_GA_IDLE (0 << 25) -# define R500_GA_IDLE_GA_UNIT2_IDLE (0 << 26) - /* Current value of stipple accumulator. */ #define R600_GA_LINE_STIPPLE_VALUE 0x4260 @@ -967,25 +800,12 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* S Texture Coordinate Value for Vertex 1 of Lines (V2 of parallelogram -- stuff textures -- i.e. AA) */ #define R600_GA_LINE_S1 0x4268 -/* GA Input fifo high water marks */ -#define R500_GA_FIFO_CNTL 0x4270 -# define R500_GA_FIFO_CNTL_VERTEX_FIFO_MASK 0x00000007 -# define R500_GA_FIFO_CNTL_VERTEX_FIFO_SHIFT 0 -# define R500_GA_FIFO_CNTL_VERTEX_INDEX_MASK 0x00000038 -# define R500_GA_FIFO_CNTL_VERTEX_INDEX_SHIFT 3 -# define R500_GA_FIFO_CNTL_VERTEX_REG_MASK 0x00003fc0 -# define R500_GA_FIFO_CNTL_VERTEX_REG_SHIFT 6 - /* GA enhance/tweaks */ #define R600_GA_ENHANCE 0x4274 # define R600_GA_ENHANCE_DEADLOCK_CNTL_NO_EFFECT (0 << 0) # define R600_GA_ENHANCE_DEADLOCK_CNTL_PREVENT_TCL (1 << 0) /* Prevents TCL interface from deadlocking on GA side. */ # define R600_GA_ENHANCE_FASTSYNC_CNTL_NO_EFFECT (0 << 1) # define R600_GA_ENHANCE_FASTSYNC_CNTL_ENABLE (1 << 1) /* Enables high-performance register/primitive switching. */ -# define R500_GA_ENHANCE_REG_READWRITE_NO_EFFECT (0 << 2) /* R520+ only */ -# define R500_GA_ENHANCE_REG_READWRITE_ENABLE (1 << 2) /* R520+ only, Enables GA support of simultaneous register reads and writes. */ -# define R500_GA_ENHANCE_REG_NOSTALL_NO_EFFECT (0 << 3) -# define R500_GA_ENHANCE_REG_NOSTALL_ENABLE (1 << 3) /* Enables GA support of no-stall reads for register read back. */ #define R600_GA_COLOR_CONTROL 0x4278 # define R600_GA_COLOR_CONTROL_RGB0_SHADING_SOLID (0 << 0) @@ -1071,8 +891,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R600_GA_ROUND_MODE_RGB_CLAMP_FP20 (1 << 4) # define R600_GA_ROUND_MODE_ALPHA_CLAMP_RGB (0 << 5) # define R600_GA_ROUND_MODE_ALPHA_CLAMP_FP20 (1 << 5) -# define R500_GA_ROUND_MODE_GEOMETRY_MASK_SHIFT 6 -# define R500_GA_ROUND_MODE_GEOMETRY_MASK_MASK 0x000003c0 /* Specifies x & y offsets for vertex data after conversion to FP. * Offsets are in S15 format (subpixels -- 1/12 or 1/16, even in 8b @@ -1195,40 +1013,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R600_RS_SEL_K0 4 # define R600_RS_SEL_K1 5 - -/* */ -#define R500_RS_INST_0 0x4320 -#define R500_RS_INST_1 0x4324 -#define R500_RS_INST_2 0x4328 -#define R500_RS_INST_3 0x432c -#define R500_RS_INST_4 0x4330 -#define R500_RS_INST_5 0x4334 -#define R500_RS_INST_6 0x4338 -#define R500_RS_INST_7 0x433c -#define R500_RS_INST_8 0x4340 -#define R500_RS_INST_9 0x4344 -#define R500_RS_INST_10 0x4348 -#define R500_RS_INST_11 0x434c -#define R500_RS_INST_12 0x4350 -#define R500_RS_INST_13 0x4354 -#define R500_RS_INST_14 0x4358 -#define R500_RS_INST_15 0x435c -#define R500_RS_INST_TEX_ID_SHIFT 0 -#define R500_RS_INST_TEX_CN_WRITE (1 << 4) -#define R500_RS_INST_TEX_ADDR_SHIFT 5 -#define R500_RS_INST_COL_ID_SHIFT 12 -#define R500_RS_INST_COL_CN_NO_WRITE (0 << 16) -#define R500_RS_INST_COL_CN_WRITE (1 << 16) -#define R500_RS_INST_COL_CN_WRITE_FBUFFER (2 << 16) -#define R500_RS_INST_COL_CN_WRITE_BACKFACE (3 << 16) -#define R500_RS_INST_COL_ADDR_SHIFT 18 -#define R500_RS_INST_TEX_ADJ (1 << 25) -#define R500_RS_INST_W_CN (1 << 26) -#define R500_RS_INST_TEX_ID(x) ((x) << R500_RS_INST_TEX_ID_SHIFT) -#define R500_RS_INST_TEX_ADDR(x) ((x) << R500_RS_INST_TEX_ADDR_SHIFT) -#define R500_RS_INST_COL_ID(x) ((x) << R500_RS_INST_COL_ID_SHIFT) -#define R500_RS_INST_COL_ADDR(x) ((x) << R500_RS_INST_COL_ADDR_SHIFT) - /* These DWORDs control how vertex data is routed into fragment program * registers, after interpolators. */ @@ -1412,9 +1196,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R600_TX_TRI_PERF_3_8 (3<<15) # define R600_ANISO_THRESHOLD_MASK (7<<17) -# define R500_MACRO_SWITCH (1<<22) -# define R500_BORDER_FIX (1<<31) - #define R600_TX_SIZE_0 0x4480 # define R600_TX_WIDTHMASK_SHIFT 0 # define R600_TX_WIDTHMASK_MASK (2047 << 0) @@ -1432,9 +1213,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. They are given meanings as R, G, B and Alpha by the swizzle specification */ # define R600_TX_FORMAT_X8 0x0 -# define R500_TX_FORMAT_X1 0x0 // bit set in format 2 # define R600_TX_FORMAT_X16 0x1 -# define R500_TX_FORMAT_X1_REV 0x0 // bit set in format 2 # define R600_TX_FORMAT_Y4X4 0x2 # define R600_TX_FORMAT_Y8X8 0x3 # define R600_TX_FORMAT_Y16X16 0x4 @@ -1521,14 +1300,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #define R600_TX_FORMAT2_0 0x4500 /* obvious missing in gap */ # define R600_TX_PITCHMASK_SHIFT 0 # define R600_TX_PITCHMASK_MASK (2047 << 0) -# define R500_TXFORMAT_MSB (1 << 14) -# define R500_TXWIDTH_BIT11 (1 << 15) -# define R500_TXHEIGHT_BIT11 (1 << 16) -# define R500_POW2FIX2FLT (1 << 17) -# define R500_SEL_FILTER4_TC0 (0 << 18) -# define R500_SEL_FILTER4_TC1 (1 << 18) -# define R500_SEL_FILTER4_TC2 (2 << 18) -# define R500_SEL_FILTER4_TC3 (3 << 18) #define R600_TX_OFFSET_0 0x4540 #define R600_TX_OFFSET_1 0x4544 @@ -1983,9 +1754,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R600_FG_ALPHA_FUNC_DISABLE (0 << 11) # define R600_FG_ALPHA_FUNC_ENABLE (1 << 11) -# define R500_FG_ALPHA_FUNC_10BIT (0 << 12) -# define R500_FG_ALPHA_FUNC_8BIT (1 << 12) - # define R600_FG_ALPHA_FUNC_MASK_DISABLE (0 << 16) # define R600_FG_ALPHA_FUNC_MASK_ENABLE (1 << 16) # define R600_FG_ALPHA_FUNC_CFG_2_OF_4 (0 << 17) @@ -1994,24 +1762,11 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R600_FG_ALPHA_FUNC_DITH_DISABLE (0 << 20) # define R600_FG_ALPHA_FUNC_DITH_ENABLE (1 << 20) -# define R500_FG_ALPHA_FUNC_OFFSET_DISABLE (0 << 24) -# define R500_FG_ALPHA_FUNC_OFFSET_ENABLE (1 << 24) /* Not supported in R520 */ -# define R500_FG_ALPHA_FUNC_DISC_ZERO_MASK_DISABLE (0 << 25) -# define R500_FG_ALPHA_FUNC_DISC_ZERO_MASK_ENABLE (1 << 25) - -# define R500_FG_ALPHA_FUNC_FP16_DISABLE (0 << 28) -# define R500_FG_ALPHA_FUNC_FP16_ENABLE (1 << 28) - - /* Fog: Where does the depth come from? */ #define R600_FG_DEPTH_SRC 0x4bd8 # define R600_FG_DEPTH_SRC_SCAN (0 << 0) # define R600_FG_DEPTH_SRC_SHADER (1 << 0) -/* Fog: Alpha Compare Value */ -#define R500_FG_ALPHA_VALUE 0x4be0 -# define R500_FG_ALPHA_VALUE_MASK 0x0000ffff - /* gap */ /* Fragment program parameters in 7.16 floating point */ @@ -2169,12 +1924,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R600_COLOR_ENDIAN_WORD_SWAP (1 << 19) # define R600_COLOR_ENDIAN_DWORD_SWAP (2 << 19) # define R600_COLOR_ENDIAN_HALF_DWORD_SWAP (3 << 19) -# define R500_COLOR_FORMAT_ARGB10101010 (0 << 21) -# define R500_COLOR_FORMAT_UV1010 (1 << 21) -# define R500_COLOR_FORMAT_CI8 (2 << 21) /* 2D only */ # define R600_COLOR_FORMAT_ARGB1555 (3 << 21) # define R600_COLOR_FORMAT_RGB565 (4 << 21) -# define R500_COLOR_FORMAT_ARGB2101010 (5 << 21) # define R600_COLOR_FORMAT_ARGB8888 (6 << 21) # define R600_COLOR_FORMAT_ARGB32323232 (7 << 21) /* reserved */ @@ -2183,7 +1934,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R600_COLOR_FORMAT_VYUY (11 << 21) # define R600_COLOR_FORMAT_YVYU (12 << 21) # define R600_COLOR_FORMAT_UV88 (13 << 21) -# define R500_COLOR_FORMAT_I10 (14 << 21) # define R600_COLOR_FORMAT_ARGB4444 (15 << 21) #define R600_RB3D_COLORPITCH1 0x4E3C #define R600_RB3D_COLORPITCH2 0x4E40 @@ -2246,20 +1996,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R600_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_SAMPLE0 (0 << 2) # define R600_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_AVERAGE (1 << 2) - -/* Discard src pixels less than or equal to threshold. */ -#define R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD 0x4ea0 -/* Discard src pixels greater than or equal to threshold. */ -#define R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD 0x4ea4 -# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_BLUE_SHIFT 0 -# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_BLUE_MASK 0x000000ff -# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_GREEN_SHIFT 8 -# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_GREEN_MASK 0x0000ff00 -# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_RED_SHIFT 16 -# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_RED_MASK 0x00ff0000 -# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_ALPHA_SHIFT 24 -# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_ALPHA_MASK 0xff000000 - /* 3D ROP Control. Stalls the 2d/3d datapath until it is idle. */ #define R600_RB3D_ROPCNTL 0x4e18 # define R600_RB3D_ROPCNTL_ROP_ENABLE 0x00000004 @@ -2269,27 +2005,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* Color Compare Flip. Stalls the 2d/3d datapath until it is idle. */ #define R600_RB3D_CLRCMP_FLIPE 0x4e1c -/* Sets the fifo sizes */ -#define R500_RB3D_FIFO_SIZE 0x4ef4 -# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_FULL (0 << 0) -# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_HALF (1 << 0) -# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_QUATER (2 << 0) -# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_EIGTHS (3 << 0) - -/* Constant color used by the blender. Pipelined through the blender. */ -#define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8 -# define R500_RB3D_CONSTANT_COLOR_AR_RED_MASK 0x0000ffff -# define R500_RB3D_CONSTANT_COLOR_AR_RED_SHIFT 0 -# define R500_RB3D_CONSTANT_COLOR_AR_ALPHA_MASK 0xffff0000 -# define R500_RB3D_CONSTANT_COLOR_AR_ALPHA_SHIFT 16 - -/* Constant color used by the blender. Pipelined through the blender. */ -#define R500_RB3D_CONSTANT_COLOR_GB 0x4efc -# define R500_RB3D_CONSTANT_COLOR_AR_BLUE_MASK 0x0000ffff -# define R500_RB3D_CONSTANT_COLOR_AR_BLUE_SHIFT 0 -# define R500_RB3D_CONSTANT_COLOR_AR_GREEN_MASK 0xffff0000 -# define R500_RB3D_CONSTANT_COLOR_AR_GREEN_SHIFT 16 - /* gap */ /* There seems to be no "write only" setting, so use Z-test = ALWAYS * for this. @@ -2382,33 +2097,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R600_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6) # define R600_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6) -# define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7) -# define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7) -# define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8) -# define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8) - -# define R500_BMASK_ENABLE (0 << 10) -# define R500_BMASK_DISABLE (1 << 10) -# define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11) -# define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11) -# define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12) -# define R500_HIZ_FP_EXP_BITS_1 (1 << 12) -# define R500_HIZ_FP_EXP_BITS_2 (2 << 12) -# define R500_HIZ_FP_EXP_BITS_3 (3 << 12) -# define R500_HIZ_FP_EXP_BITS_4 (4 << 12) -# define R500_HIZ_FP_EXP_BITS_5 (5 << 12) -# define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15) -# define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15) -# define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16) -# define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16) -# define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17) -# define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17) -# define R500_PEQ_PACKING_DISABLE (0 << 18) -# define R500_PEQ_PACKING_ENABLE (1 << 18) -# define R500_COVERED_PTR_MASKING_DISABLE (0 << 18) -# define R500_COVERED_PTR_MASKING_ENABLE (1 << 18) - - /* gap */ /* Z Buffer Address Offset. @@ -2460,23 +2148,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R600_DEPTHY_OFFSET_SHIFT 17 # define R600_DEPTHY_OFFSET_MASK 0x07FE0000 -/* Sets the fifo sizes */ -#define R500_ZB_FIFO_SIZE 0x4fd0 -# define R500_OP_FIFO_SIZE_FULL (0 << 0) -# define R500_OP_FIFO_SIZE_HALF (1 << 0) -# define R500_OP_FIFO_SIZE_QUATER (2 << 0) -# define R500_OP_FIFO_SIZE_EIGTHS (4 << 0) - -/* Stencil Reference Value and Mask for backfacing quads */ -/* R600_ZB_STENCILREFMASK handles front face */ -#define R500_ZB_STENCILREFMASK_BF 0x4fd4 -# define R500_STENCILREF_SHIFT 0 -# define R500_STENCILREF_MASK 0x000000ff -# define R500_STENCILMASK_SHIFT 8 -# define R500_STENCILMASK_MASK 0x0000ff00 -# define R500_STENCILWRITEMASK_SHIFT 16 -# define R500_STENCILWRITEMASK_MASK 0x00ff0000 - /** * \defgroup R3XX_R5XX_PROGRAMMABLE_VERTEX_SHADER_DESCRIPTION R3XX-R5XX PROGRAMMABLE VERTEX SHADER DESCRIPTION * @@ -2692,478 +2363,6 @@ enum { #define R600_PRIM_NUM_VERTICES_SHIFT 16 #define R600_PRIM_NUM_VERTICES_MASK 0xffff - - -/* - * The R500 unified shader (US) registers come in banks of 512 each, one - * for each instruction slot in the shader. You can't touch them directly. - * R500_US_VECTOR_INDEX() sets the base instruction to modify; successive - * writes to R500_GA_US_VECTOR_DATA autoincrement the index after the - * instruction is fully specified. - */ -#define R500_US_ALU_ALPHA_INST_0 0xa800 -# define R500_ALPHA_OP_MAD 0 -# define R500_ALPHA_OP_DP 1 -# define R500_ALPHA_OP_MIN 2 -# define R500_ALPHA_OP_MAX 3 -/* #define R500_ALPHA_OP_RESERVED 4 */ -# define R500_ALPHA_OP_CND 5 -# define R500_ALPHA_OP_CMP 6 -# define R500_ALPHA_OP_FRC 7 -# define R500_ALPHA_OP_EX2 8 -# define R500_ALPHA_OP_LN2 9 -# define R500_ALPHA_OP_RCP 10 -# define R500_ALPHA_OP_RSQ 11 -# define R500_ALPHA_OP_SIN 12 -# define R500_ALPHA_OP_COS 13 -# define R500_ALPHA_OP_MDH 14 -# define R500_ALPHA_OP_MDV 15 -# define R500_ALPHA_ADDRD(x) ((x) << 4) -# define R500_ALPHA_ADDRD_REL (1 << 11) -# define R500_ALPHA_SEL_A_SHIFT 12 -# define R500_ALPHA_SEL_A_SRC0 (0 << 12) -# define R500_ALPHA_SEL_A_SRC1 (1 << 12) -# define R500_ALPHA_SEL_A_SRC2 (2 << 12) -# define R500_ALPHA_SEL_A_SRCP (3 << 12) -# define R500_ALPHA_SWIZ_A_R (0 << 14) -# define R500_ALPHA_SWIZ_A_G (1 << 14) -# define R500_ALPHA_SWIZ_A_B (2 << 14) -# define R500_ALPHA_SWIZ_A_A (3 << 14) -# define R500_ALPHA_SWIZ_A_0 (4 << 14) -# define R500_ALPHA_SWIZ_A_HALF (5 << 14) -# define R500_ALPHA_SWIZ_A_1 (6 << 14) -/* #define R500_ALPHA_SWIZ_A_UNUSED (7 << 14) */ -# define R500_ALPHA_MOD_A_NOP (0 << 17) -# define R500_ALPHA_MOD_A_NEG (1 << 17) -# define R500_ALPHA_MOD_A_ABS (2 << 17) -# define R500_ALPHA_MOD_A_NAB (3 << 17) -# define R500_ALPHA_SEL_B_SHIFT 19 -# define R500_ALPHA_SEL_B_SRC0 (0 << 19) -# define R500_ALPHA_SEL_B_SRC1 (1 << 19) -# define R500_ALPHA_SEL_B_SRC2 (2 << 19) -# define R500_ALPHA_SEL_B_SRCP (3 << 19) -# define R500_ALPHA_SWIZ_B_R (0 << 21) -# define R500_ALPHA_SWIZ_B_G (1 << 21) -# define R500_ALPHA_SWIZ_B_B (2 << 21) -# define R500_ALPHA_SWIZ_B_A (3 << 21) -# define R500_ALPHA_SWIZ_B_0 (4 << 21) -# define R500_ALPHA_SWIZ_B_HALF (5 << 21) -# define R500_ALPHA_SWIZ_B_1 (6 << 21) -/* #define R500_ALPHA_SWIZ_B_UNUSED (7 << 21) */ -# define R500_ALPHA_MOD_B_NOP (0 << 24) -# define R500_ALPHA_MOD_B_NEG (1 << 24) -# define R500_ALPHA_MOD_B_ABS (2 << 24) -# define R500_ALPHA_MOD_B_NAB (3 << 24) -# define R500_ALPHA_OMOD_IDENTITY (0 << 26) -# define R500_ALPHA_OMOD_MUL_2 (1 << 26) -# define R500_ALPHA_OMOD_MUL_4 (2 << 26) -# define R500_ALPHA_OMOD_MUL_8 (3 << 26) -# define R500_ALPHA_OMOD_DIV_2 (4 << 26) -# define R500_ALPHA_OMOD_DIV_4 (5 << 26) -# define R500_ALPHA_OMOD_DIV_8 (6 << 26) -# define R500_ALPHA_OMOD_DISABLE (7 << 26) -# define R500_ALPHA_TARGET(x) ((x) << 29) -# define R500_ALPHA_W_OMASK (1 << 31) -#define R500_US_ALU_ALPHA_ADDR_0 0x9800 -# define R500_ALPHA_ADDR0(x) ((x) << 0) -# define R500_ALPHA_ADDR0_CONST (1 << 8) -# define R500_ALPHA_ADDR0_REL (1 << 9) -# define R500_ALPHA_ADDR1(x) ((x) << 10) -# define R500_ALPHA_ADDR1_CONST (1 << 18) -# define R500_ALPHA_ADDR1_REL (1 << 19) -# define R500_ALPHA_ADDR2(x) ((x) << 20) -# define R500_ALPHA_ADDR2_CONST (1 << 28) -# define R500_ALPHA_ADDR2_REL (1 << 29) -# define R500_ALPHA_SRCP_OP_1_MINUS_2A0 (0 << 30) -# define R500_ALPHA_SRCP_OP_A1_MINUS_A0 (1 << 30) -# define R500_ALPHA_SRCP_OP_A1_PLUS_A0 (2 << 30) -# define R500_ALPHA_SRCP_OP_1_MINUS_A0 (3 << 30) -#define R500_US_ALU_RGBA_INST_0 0xb000 -# define R500_ALU_RGBA_OP_MAD (0 << 0) -# define R500_ALU_RGBA_OP_DP3 (1 << 0) -# define R500_ALU_RGBA_OP_DP4 (2 << 0) -# define R500_ALU_RGBA_OP_D2A (3 << 0) -# define R500_ALU_RGBA_OP_MIN (4 << 0) -# define R500_ALU_RGBA_OP_MAX (5 << 0) -/* #define R500_ALU_RGBA_OP_RESERVED (6 << 0) */ -# define R500_ALU_RGBA_OP_CND (7 << 0) -# define R500_ALU_RGBA_OP_CMP (8 << 0) -# define R500_ALU_RGBA_OP_FRC (9 << 0) -# define R500_ALU_RGBA_OP_SOP (10 << 0) -# define R500_ALU_RGBA_OP_MDH (11 << 0) -# define R500_ALU_RGBA_OP_MDV (12 << 0) -# define R500_ALU_RGBA_ADDRD(x) ((x) << 4) -# define R500_ALU_RGBA_ADDRD_REL (1 << 11) -# define R500_ALU_RGBA_SEL_C_SHIFT 12 -# define R500_ALU_RGBA_SEL_C_SRC0 (0 << 12) -# define R500_ALU_RGBA_SEL_C_SRC1 (1 << 12) -# define R500_ALU_RGBA_SEL_C_SRC2 (2 << 12) -# define R500_ALU_RGBA_SEL_C_SRCP (3 << 12) -# define R500_ALU_RGBA_R_SWIZ_R (0 << 14) -# define R500_ALU_RGBA_R_SWIZ_G (1 << 14) -# define R500_ALU_RGBA_R_SWIZ_B (2 << 14) -# define R500_ALU_RGBA_R_SWIZ_A (3 << 14) -# define R500_ALU_RGBA_R_SWIZ_0 (4 << 14) -# define R500_ALU_RGBA_R_SWIZ_HALF (5 << 14) -# define R500_ALU_RGBA_R_SWIZ_1 (6 << 14) -/* #define R500_ALU_RGBA_R_SWIZ_UNUSED (7 << 14) */ -# define R500_ALU_RGBA_G_SWIZ_R (0 << 17) -# define R500_ALU_RGBA_G_SWIZ_G (1 << 17) -# define R500_ALU_RGBA_G_SWIZ_B (2 << 17) -# define R500_ALU_RGBA_G_SWIZ_A (3 << 17) -# define R500_ALU_RGBA_G_SWIZ_0 (4 << 17) -# define R500_ALU_RGBA_G_SWIZ_HALF (5 << 17) -# define R500_ALU_RGBA_G_SWIZ_1 (6 << 17) -/* #define R500_ALU_RGBA_G_SWIZ_UNUSED (7 << 17) */ -# define R500_ALU_RGBA_B_SWIZ_R (0 << 20) -# define R500_ALU_RGBA_B_SWIZ_G (1 << 20) -# define R500_ALU_RGBA_B_SWIZ_B (2 << 20) -# define R500_ALU_RGBA_B_SWIZ_A (3 << 20) -# define R500_ALU_RGBA_B_SWIZ_0 (4 << 20) -# define R500_ALU_RGBA_B_SWIZ_HALF (5 << 20) -# define R500_ALU_RGBA_B_SWIZ_1 (6 << 20) -/* #define R500_ALU_RGBA_B_SWIZ_UNUSED (7 << 20) */ -# define R500_ALU_RGBA_MOD_C_NOP (0 << 23) -# define R500_ALU_RGBA_MOD_C_NEG (1 << 23) -# define R500_ALU_RGBA_MOD_C_ABS (2 << 23) -# define R500_ALU_RGBA_MOD_C_NAB (3 << 23) -# define R500_ALU_RGBA_ALPHA_SEL_C_SHIFT 25 -# define R500_ALU_RGBA_ALPHA_SEL_C_SRC0 (0 << 25) -# define R500_ALU_RGBA_ALPHA_SEL_C_SRC1 (1 << 25) -# define R500_ALU_RGBA_ALPHA_SEL_C_SRC2 (2 << 25) -# define R500_ALU_RGBA_ALPHA_SEL_C_SRCP (3 << 25) -# define R500_ALU_RGBA_A_SWIZ_R (0 << 27) -# define R500_ALU_RGBA_A_SWIZ_G (1 << 27) -# define R500_ALU_RGBA_A_SWIZ_B (2 << 27) -# define R500_ALU_RGBA_A_SWIZ_A (3 << 27) -# define R500_ALU_RGBA_A_SWIZ_0 (4 << 27) -# define R500_ALU_RGBA_A_SWIZ_HALF (5 << 27) -# define R500_ALU_RGBA_A_SWIZ_1 (6 << 27) -/* #define R500_ALU_RGBA_A_SWIZ_UNUSED (7 << 27) */ -# define R500_ALU_RGBA_ALPHA_MOD_C_NOP (0 << 30) -# define R500_ALU_RGBA_ALPHA_MOD_C_NEG (1 << 30) -# define R500_ALU_RGBA_ALPHA_MOD_C_ABS (2 << 30) -# define R500_ALU_RGBA_ALPHA_MOD_C_NAB (3 << 30) -#define R500_US_ALU_RGB_INST_0 0xa000 -# define R500_ALU_RGB_SEL_A_SHIFT 0 -# define R500_ALU_RGB_SEL_A_SRC0 (0 << 0) -# define R500_ALU_RGB_SEL_A_SRC1 (1 << 0) -# define R500_ALU_RGB_SEL_A_SRC2 (2 << 0) -# define R500_ALU_RGB_SEL_A_SRCP (3 << 0) -# define R500_ALU_RGB_R_SWIZ_A_R (0 << 2) -# define R500_ALU_RGB_R_SWIZ_A_G (1 << 2) -# define R500_ALU_RGB_R_SWIZ_A_B (2 << 2) -# define R500_ALU_RGB_R_SWIZ_A_A (3 << 2) -# define R500_ALU_RGB_R_SWIZ_A_0 (4 << 2) -# define R500_ALU_RGB_R_SWIZ_A_HALF (5 << 2) -# define R500_ALU_RGB_R_SWIZ_A_1 (6 << 2) -/* #define R500_ALU_RGB_R_SWIZ_A_UNUSED (7 << 2) */ -# define R500_ALU_RGB_G_SWIZ_A_R (0 << 5) -# define R500_ALU_RGB_G_SWIZ_A_G (1 << 5) -# define R500_ALU_RGB_G_SWIZ_A_B (2 << 5) -# define R500_ALU_RGB_G_SWIZ_A_A (3 << 5) -# define R500_ALU_RGB_G_SWIZ_A_0 (4 << 5) -# define R500_ALU_RGB_G_SWIZ_A_HALF (5 << 5) -# define R500_ALU_RGB_G_SWIZ_A_1 (6 << 5) -/* #define R500_ALU_RGB_G_SWIZ_A_UNUSED (7 << 5) */ -# define R500_ALU_RGB_B_SWIZ_A_R (0 << 8) -# define R500_ALU_RGB_B_SWIZ_A_G (1 << 8) -# define R500_ALU_RGB_B_SWIZ_A_B (2 << 8) -# define R500_ALU_RGB_B_SWIZ_A_A (3 << 8) -# define R500_ALU_RGB_B_SWIZ_A_0 (4 << 8) -# define R500_ALU_RGB_B_SWIZ_A_HALF (5 << 8) -# define R500_ALU_RGB_B_SWIZ_A_1 (6 << 8) -/* #define R500_ALU_RGB_B_SWIZ_A_UNUSED (7 << 8) */ -# define R500_ALU_RGB_MOD_A_NOP (0 << 11) -# define R500_ALU_RGB_MOD_A_NEG (1 << 11) -# define R500_ALU_RGB_MOD_A_ABS (2 << 11) -# define R500_ALU_RGB_MOD_A_NAB (3 << 11) -# define R500_ALU_RGB_SEL_B_SHIFT 13 -# define R500_ALU_RGB_SEL_B_SRC0 (0 << 13) -# define R500_ALU_RGB_SEL_B_SRC1 (1 << 13) -# define R500_ALU_RGB_SEL_B_SRC2 (2 << 13) -# define R500_ALU_RGB_SEL_B_SRCP (3 << 13) -# define R500_ALU_RGB_R_SWIZ_B_R (0 << 15) -# define R500_ALU_RGB_R_SWIZ_B_G (1 << 15) -# define R500_ALU_RGB_R_SWIZ_B_B (2 << 15) -# define R500_ALU_RGB_R_SWIZ_B_A (3 << 15) -# define R500_ALU_RGB_R_SWIZ_B_0 (4 << 15) -# define R500_ALU_RGB_R_SWIZ_B_HALF (5 << 15) -# define R500_ALU_RGB_R_SWIZ_B_1 (6 << 15) -/* #define R500_ALU_RGB_R_SWIZ_B_UNUSED (7 << 15) */ -# define R500_ALU_RGB_G_SWIZ_B_R (0 << 18) -# define R500_ALU_RGB_G_SWIZ_B_G (1 << 18) -# define R500_ALU_RGB_G_SWIZ_B_B (2 << 18) -# define R500_ALU_RGB_G_SWIZ_B_A (3 << 18) -# define R500_ALU_RGB_G_SWIZ_B_0 (4 << 18) -# define R500_ALU_RGB_G_SWIZ_B_HALF (5 << 18) -# define R500_ALU_RGB_G_SWIZ_B_1 (6 << 18) -/* #define R500_ALU_RGB_G_SWIZ_B_UNUSED (7 << 18) */ -# define R500_ALU_RGB_B_SWIZ_B_R (0 << 21) -# define R500_ALU_RGB_B_SWIZ_B_G (1 << 21) -# define R500_ALU_RGB_B_SWIZ_B_B (2 << 21) -# define R500_ALU_RGB_B_SWIZ_B_A (3 << 21) -# define R500_ALU_RGB_B_SWIZ_B_0 (4 << 21) -# define R500_ALU_RGB_B_SWIZ_B_HALF (5 << 21) -# define R500_ALU_RGB_B_SWIZ_B_1 (6 << 21) -/* #define R500_ALU_RGB_B_SWIZ_B_UNUSED (7 << 21) */ -# define R500_ALU_RGB_MOD_B_NOP (0 << 24) -# define R500_ALU_RGB_MOD_B_NEG (1 << 24) -# define R500_ALU_RGB_MOD_B_ABS (2 << 24) -# define R500_ALU_RGB_MOD_B_NAB (3 << 24) -# define R500_ALU_RGB_OMOD_IDENTITY (0 << 26) -# define R500_ALU_RGB_OMOD_MUL_2 (1 << 26) -# define R500_ALU_RGB_OMOD_MUL_4 (2 << 26) -# define R500_ALU_RGB_OMOD_MUL_8 (3 << 26) -# define R500_ALU_RGB_OMOD_DIV_2 (4 << 26) -# define R500_ALU_RGB_OMOD_DIV_4 (5 << 26) -# define R500_ALU_RGB_OMOD_DIV_8 (6 << 26) -# define R500_ALU_RGB_OMOD_DISABLE (7 << 26) -# define R500_ALU_RGB_TARGET(x) ((x) << 29) -# define R500_ALU_RGB_WMASK (1 << 31) -#define R500_US_ALU_RGB_ADDR_0 0x9000 -# define R500_RGB_ADDR0(x) ((x) << 0) -# define R500_RGB_ADDR0_CONST (1 << 8) -# define R500_RGB_ADDR0_REL (1 << 9) -# define R500_RGB_ADDR1(x) ((x) << 10) -# define R500_RGB_ADDR1_CONST (1 << 18) -# define R500_RGB_ADDR1_REL (1 << 19) -# define R500_RGB_ADDR2(x) ((x) << 20) -# define R500_RGB_ADDR2_CONST (1 << 28) -# define R500_RGB_ADDR2_REL (1 << 29) -# define R500_RGB_SRCP_OP_1_MINUS_2RGB0 (0 << 30) -# define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 (1 << 30) -# define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0 (2 << 30) -# define R500_RGB_SRCP_OP_1_MINUS_RGB0 (3 << 30) -#define R500_US_CMN_INST_0 0xb800 -# define R500_INST_TYPE_MASK (3 << 0) -# define R500_INST_TYPE_ALU (0 << 0) -# define R500_INST_TYPE_OUT (1 << 0) -# define R500_INST_TYPE_FC (2 << 0) -# define R500_INST_TYPE_TEX (3 << 0) -# define R500_INST_TEX_SEM_WAIT (1 << 2) -# define R500_INST_RGB_PRED_SEL_NONE (0 << 3) -# define R500_INST_RGB_PRED_SEL_RGBA (1 << 3) -# define R500_INST_RGB_PRED_SEL_RRRR (2 << 3) -# define R500_INST_RGB_PRED_SEL_GGGG (3 << 3) -# define R500_INST_RGB_PRED_SEL_BBBB (4 << 3) -# define R500_INST_RGB_PRED_SEL_AAAA (5 << 3) -# define R500_INST_RGB_PRED_INV (1 << 6) -# define R500_INST_WRITE_INACTIVE (1 << 7) -# define R500_INST_LAST (1 << 8) -# define R500_INST_NOP (1 << 9) -# define R500_INST_ALU_WAIT (1 << 10) -# define R500_INST_RGB_WMASK_R (1 << 11) -# define R500_INST_RGB_WMASK_G (1 << 12) -# define R500_INST_RGB_WMASK_B (1 << 13) -# define R500_INST_ALPHA_WMASK (1 << 14) -# define R500_INST_RGB_OMASK_R (1 << 15) -# define R500_INST_RGB_OMASK_G (1 << 16) -# define R500_INST_RGB_OMASK_B (1 << 17) -# define R500_INST_ALPHA_OMASK (1 << 18) -# define R500_INST_RGB_CLAMP (1 << 19) -# define R500_INST_ALPHA_CLAMP (1 << 20) -# define R500_INST_ALU_RESULT_SEL (1 << 21) -# define R500_INST_ALPHA_PRED_INV (1 << 22) -# define R500_INST_ALU_RESULT_OP_EQ (0 << 23) -# define R500_INST_ALU_RESULT_OP_LT (1 << 23) -# define R500_INST_ALU_RESULT_OP_GE (2 << 23) -# define R500_INST_ALU_RESULT_OP_NE (3 << 23) -# define R500_INST_ALPHA_PRED_SEL_NONE (0 << 25) -# define R500_INST_ALPHA_PRED_SEL_RGBA (1 << 25) -# define R500_INST_ALPHA_PRED_SEL_RRRR (2 << 25) -# define R500_INST_ALPHA_PRED_SEL_GGGG (3 << 25) -# define R500_INST_ALPHA_PRED_SEL_BBBB (4 << 25) -# define R500_INST_ALPHA_PRED_SEL_AAAA (5 << 25) -/* XXX next four are kind of guessed */ -# define R500_INST_STAT_WE_R (1 << 28) -# define R500_INST_STAT_WE_G (1 << 29) -# define R500_INST_STAT_WE_B (1 << 30) -# define R500_INST_STAT_WE_A (1 << 31) - -/* note that these are 8 bit lengths, despite the offsets, at least for R500 */ -#define R500_US_CODE_ADDR 0x4630 -# define R500_US_CODE_START_ADDR(x) ((x) << 0) -# define R500_US_CODE_END_ADDR(x) ((x) << 16) -#define R500_US_CODE_OFFSET 0x4638 -# define R500_US_CODE_OFFSET_ADDR(x) ((x) << 0) -#define R500_US_CODE_RANGE 0x4634 -# define R500_US_CODE_RANGE_ADDR(x) ((x) << 0) -# define R500_US_CODE_RANGE_SIZE(x) ((x) << 16) -#define R500_US_CONFIG 0x4600 -# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1) -#define R500_US_FC_ADDR_0 0xa000 -# define R500_FC_BOOL_ADDR(x) ((x) << 0) -# define R500_FC_INT_ADDR(x) ((x) << 8) -# define R500_FC_JUMP_ADDR(x) ((x) << 16) -# define R500_FC_JUMP_GLOBAL (1 << 31) -#define R500_US_FC_BOOL_CONST 0x4620 -# define R500_FC_KBOOL(x) (x) -#define R500_US_FC_CTRL 0x4624 -# define R500_FC_TEST_EN (1 << 30) -# define R500_FC_FULL_FC_EN (1 << 31) -#define R500_US_FC_INST_0 0x9800 -# define R500_FC_OP_JUMP (0 << 0) -# define R500_FC_OP_LOOP (1 << 0) -# define R500_FC_OP_ENDLOOP (2 << 0) -# define R500_FC_OP_REP (3 << 0) -# define R500_FC_OP_ENDREP (4 << 0) -# define R500_FC_OP_BREAKLOOP (5 << 0) -# define R500_FC_OP_BREAKREP (6 << 0) -# define R500_FC_OP_CONTINUE (7 << 0) -# define R500_FC_B_ELSE (1 << 4) -# define R500_FC_JUMP_ANY (1 << 5) -# define R500_FC_A_OP_NONE (0 << 6) -# define R500_FC_A_OP_POP (1 << 6) -# define R500_FC_A_OP_PUSH (2 << 6) -# define R500_FC_JUMP_FUNC(x) ((x) << 8) -# define R500_FC_B_POP_CNT(x) ((x) << 16) -# define R500_FC_B_OP0_NONE (0 << 24) -# define R500_FC_B_OP0_DECR (1 << 24) -# define R500_FC_B_OP0_INCR (2 << 24) -# define R500_FC_B_OP1_DECR (0 << 26) -# define R500_FC_B_OP1_NONE (1 << 26) -# define R500_FC_B_OP1_INCR (2 << 26) -# define R500_FC_IGNORE_UNCOVERED (1 << 28) -#define R500_US_FC_INT_CONST_0 0x4c00 -# define R500_FC_INT_CONST_KR(x) ((x) << 0) -# define R500_FC_INT_CONST_KG(x) ((x) << 8) -# define R500_FC_INT_CONST_KB(x) ((x) << 16) -/* _0 through _15 */ -#define R500_US_FORMAT0_0 0x4640 -# define R500_FORMAT_TXWIDTH(x) ((x) << 0) -# define R500_FORMAT_TXHEIGHT(x) ((x) << 11) -# define R500_FORMAT_TXDEPTH(x) ((x) << 22) -/* _0 through _3 */ -#define R500_US_OUT_FMT_0 0x46a4 -# define R500_OUT_FMT_C4_8 (0 << 0) -# define R500_OUT_FMT_C4_10 (1 << 0) -# define R500_OUT_FMT_C4_10_GAMMA (2 << 0) -# define R500_OUT_FMT_C_16 (3 << 0) -# define R500_OUT_FMT_C2_16 (4 << 0) -# define R500_OUT_FMT_C4_16 (5 << 0) -# define R500_OUT_FMT_C_16_MPEG (6 << 0) -# define R500_OUT_FMT_C2_16_MPEG (7 << 0) -# define R500_OUT_FMT_C2_4 (8 << 0) -# define R500_OUT_FMT_C_3_3_2 (9 << 0) -# define R500_OUT_FMT_C_6_5_6 (10 << 0) -# define R500_OUT_FMT_C_11_11_10 (11 << 0) -# define R500_OUT_FMT_C_10_11_11 (12 << 0) -# define R500_OUT_FMT_C_2_10_10_10 (13 << 0) -/* #define R500_OUT_FMT_RESERVED (14 << 0) */ -# define R500_OUT_FMT_UNUSED (15 << 0) -# define R500_OUT_FMT_C_16_FP (16 << 0) -# define R500_OUT_FMT_C2_16_FP (17 << 0) -# define R500_OUT_FMT_C4_16_FP (18 << 0) -# define R500_OUT_FMT_C_32_FP (19 << 0) -# define R500_OUT_FMT_C2_32_FP (20 << 0) -# define R500_OUT_FMT_C4_32_FP (21 << 0) -# define R500_C0_SEL_A (0 << 8) -# define R500_C0_SEL_R (1 << 8) -# define R500_C0_SEL_G (2 << 8) -# define R500_C0_SEL_B (3 << 8) -# define R500_C1_SEL_A (0 << 10) -# define R500_C1_SEL_R (1 << 10) -# define R500_C1_SEL_G (2 << 10) -# define R500_C1_SEL_B (3 << 10) -# define R500_C2_SEL_A (0 << 12) -# define R500_C2_SEL_R (1 << 12) -# define R500_C2_SEL_G (2 << 12) -# define R500_C2_SEL_B (3 << 12) -# define R500_C3_SEL_A (0 << 14) -# define R500_C3_SEL_R (1 << 14) -# define R500_C3_SEL_G (2 << 14) -# define R500_C3_SEL_B (3 << 14) -# define R500_OUT_SIGN(x) ((x) << 16) -# define R500_ROUND_ADJ (1 << 20) -#define R500_US_PIXSIZE 0x4604 -# define R500_PIX_SIZE(x) (x) -#define R500_US_TEX_ADDR_0 0x9800 -# define R500_TEX_SRC_ADDR(x) ((x) << 0) -# define R500_TEX_SRC_ADDR_REL (1 << 7) -# define R500_TEX_SRC_S_SWIZ_R (0 << 8) -# define R500_TEX_SRC_S_SWIZ_G (1 << 8) -# define R500_TEX_SRC_S_SWIZ_B (2 << 8) -# define R500_TEX_SRC_S_SWIZ_A (3 << 8) -# define R500_TEX_SRC_T_SWIZ_R (0 << 10) -# define R500_TEX_SRC_T_SWIZ_G (1 << 10) -# define R500_TEX_SRC_T_SWIZ_B (2 << 10) -# define R500_TEX_SRC_T_SWIZ_A (3 << 10) -# define R500_TEX_SRC_R_SWIZ_R (0 << 12) -# define R500_TEX_SRC_R_SWIZ_G (1 << 12) -# define R500_TEX_SRC_R_SWIZ_B (2 << 12) -# define R500_TEX_SRC_R_SWIZ_A (3 << 12) -# define R500_TEX_SRC_Q_SWIZ_R (0 << 14) -# define R500_TEX_SRC_Q_SWIZ_G (1 << 14) -# define R500_TEX_SRC_Q_SWIZ_B (2 << 14) -# define R500_TEX_SRC_Q_SWIZ_A (3 << 14) -# define R500_TEX_DST_ADDR(x) ((x) << 16) -# define R500_TEX_DST_ADDR_REL (1 << 23) -# define R500_TEX_DST_R_SWIZ_R (0 << 24) -# define R500_TEX_DST_R_SWIZ_G (1 << 24) -# define R500_TEX_DST_R_SWIZ_B (2 << 24) -# define R500_TEX_DST_R_SWIZ_A (3 << 24) -# define R500_TEX_DST_G_SWIZ_R (0 << 26) -# define R500_TEX_DST_G_SWIZ_G (1 << 26) -# define R500_TEX_DST_G_SWIZ_B (2 << 26) -# define R500_TEX_DST_G_SWIZ_A (3 << 26) -# define R500_TEX_DST_B_SWIZ_R (0 << 28) -# define R500_TEX_DST_B_SWIZ_G (1 << 28) -# define R500_TEX_DST_B_SWIZ_B (2 << 28) -# define R500_TEX_DST_B_SWIZ_A (3 << 28) -# define R500_TEX_DST_A_SWIZ_R (0 << 30) -# define R500_TEX_DST_A_SWIZ_G (1 << 30) -# define R500_TEX_DST_A_SWIZ_B (2 << 30) -# define R500_TEX_DST_A_SWIZ_A (3 << 30) -#define R500_US_TEX_ADDR_DXDY_0 0xa000 -# define R500_DX_ADDR(x) ((x) << 0) -# define R500_DX_ADDR_REL (1 << 7) -# define R500_DX_S_SWIZ_R (0 << 8) -# define R500_DX_S_SWIZ_G (1 << 8) -# define R500_DX_S_SWIZ_B (2 << 8) -# define R500_DX_S_SWIZ_A (3 << 8) -# define R500_DX_T_SWIZ_R (0 << 10) -# define R500_DX_T_SWIZ_G (1 << 10) -# define R500_DX_T_SWIZ_B (2 << 10) -# define R500_DX_T_SWIZ_A (3 << 10) -# define R500_DX_R_SWIZ_R (0 << 12) -# define R500_DX_R_SWIZ_G (1 << 12) -# define R500_DX_R_SWIZ_B (2 << 12) -# define R500_DX_R_SWIZ_A (3 << 12) -# define R500_DX_Q_SWIZ_R (0 << 14) -# define R500_DX_Q_SWIZ_G (1 << 14) -# define R500_DX_Q_SWIZ_B (2 << 14) -# define R500_DX_Q_SWIZ_A (3 << 14) -# define R500_DY_ADDR(x) ((x) << 16) -# define R500_DY_ADDR_REL (1 << 17) -# define R500_DY_S_SWIZ_R (0 << 24) -# define R500_DY_S_SWIZ_G (1 << 24) -# define R500_DY_S_SWIZ_B (2 << 24) -# define R500_DY_S_SWIZ_A (3 << 24) -# define R500_DY_T_SWIZ_R (0 << 26) -# define R500_DY_T_SWIZ_G (1 << 26) -# define R500_DY_T_SWIZ_B (2 << 26) -# define R500_DY_T_SWIZ_A (3 << 26) -# define R500_DY_R_SWIZ_R (0 << 28) -# define R500_DY_R_SWIZ_G (1 << 28) -# define R500_DY_R_SWIZ_B (2 << 28) -# define R500_DY_R_SWIZ_A (3 << 28) -# define R500_DY_Q_SWIZ_R (0 << 30) -# define R500_DY_Q_SWIZ_G (1 << 30) -# define R500_DY_Q_SWIZ_B (2 << 30) -# define R500_DY_Q_SWIZ_A (3 << 30) -#define R500_US_TEX_INST_0 0x9000 -# define R500_TEX_ID(x) ((x) << 16) -# define R500_TEX_INST_NOP (0 << 22) -# define R500_TEX_INST_LD (1 << 22) -# define R500_TEX_INST_TEXKILL (2 << 22) -# define R500_TEX_INST_PROJ (3 << 22) -# define R500_TEX_INST_LODBIAS (4 << 22) -# define R500_TEX_INST_LOD (5 << 22) -# define R500_TEX_INST_DXDY (6 << 22) -# define R500_TEX_SEM_ACQUIRE (1 << 25) -# define R500_TEX_IGNORE_UNCOVERED (1 << 26) -# define R500_TEX_UNSCALED (1 << 27) #define R600_US_W_FMT 0x46b4 # define R600_W_FMT_W0 (0 << 0) # define R600_W_FMT_W24 (1 << 0) diff --git a/src/mesa/drivers/dri/r600/r600_render.c b/src/mesa/drivers/dri/r600/r600_render.c index 27a5c9cd6f..7b4ecccc66 100644 --- a/src/mesa/drivers/dri/r600/r600_render.c +++ b/src/mesa/drivers/dri/r600/r600_render.c @@ -431,18 +431,9 @@ static int r600Fallback(GLcontext * ctx) FALLBACK_IF(r600->radeon.Fallback); /* Do we need to use new-style shaders? * Also is there a better way to do this? */ - if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - struct r500_fragment_program *fp = (struct r500_fragment_program *) - (char *)ctx->FragmentProgram._Current; - if (fp) { - if (!fp->translated) { - r500TranslateFragmentShader(r600, fp); - FALLBACK_IF(!fp->translated); - } - } - } else { + { struct r600_fragment_program *fp = (struct r600_fragment_program *) - (char *)ctx->FragmentProgram._Current; + (char *)ctx->FragmentProgram._Current; if (fp) { if (!fp->translated) { r600TranslateFragmentShader(r600, fp); diff --git a/src/mesa/drivers/dri/r600/r600_shader.c b/src/mesa/drivers/dri/r600/r600_shader.c index ebf4a72191..7d054e4fb0 100644 --- a/src/mesa/drivers/dri/r600/r600_shader.c +++ b/src/mesa/drivers/dri/r600/r600_shader.c @@ -12,7 +12,6 @@ static struct gl_program *r600NewProgram(GLcontext * ctx, GLenum target, r600ContextPtr rmesa = R600_CONTEXT(ctx); struct r600_vertex_program_cont *vp; struct r600_fragment_program *r600_fp; - struct r500_fragment_program *r500_fp; switch (target) { case GL_VERTEX_STATE_PROGRAM_NV: @@ -21,27 +20,13 @@ static struct gl_program *r600NewProgram(GLcontext * ctx, GLenum target, return _mesa_init_vertex_program(ctx, &vp->mesa_program, target, id); case GL_FRAGMENT_PROGRAM_ARB: - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - r500_fp = CALLOC_STRUCT(r500_fragment_program); - r500_fp->ctx = ctx; - return _mesa_init_fragment_program(ctx, &r500_fp->mesa_program, - target, id); - } else { - r600_fp = CALLOC_STRUCT(r600_fragment_program); - return _mesa_init_fragment_program(ctx, &r600_fp->mesa_program, - target, id); - } - + r600_fp = CALLOC_STRUCT(r600_fragment_program); + return _mesa_init_fragment_program(ctx, &r600_fp->mesa_program, + target, id); case GL_FRAGMENT_PROGRAM_NV: - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - r500_fp = CALLOC_STRUCT(r500_fragment_program); - return _mesa_init_fragment_program(ctx, &r500_fp->mesa_program, - target, id); - } else { - r600_fp = CALLOC_STRUCT(r600_fragment_program); - return _mesa_init_fragment_program(ctx, &r600_fp->mesa_program, - target, id); - } + r600_fp = CALLOC_STRUCT(r600_fragment_program); + return _mesa_init_fragment_program(ctx, &r600_fp->mesa_program, + target, id); default: _mesa_problem(ctx, "Bad target in r600NewProgram"); } @@ -60,17 +45,13 @@ r600ProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog) r600ContextPtr rmesa = R600_CONTEXT(ctx); struct r600_vertex_program_cont *vp = (void *)prog; struct r600_fragment_program *r600_fp = (struct r600_fragment_program *)prog; - struct r500_fragment_program *r500_fp = (struct r500_fragment_program *)prog; switch (target) { case GL_VERTEX_PROGRAM_ARB: vp->progs = NULL; break; case GL_FRAGMENT_PROGRAM_ARB: - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) - r500_fp->translated = GL_FALSE; - else - r600_fp->translated = GL_FALSE; + r600_fp->translated = GL_FALSE; break; } diff --git a/src/mesa/drivers/dri/r600/r600_state.c b/src/mesa/drivers/dri/r600/r600_state.c index 19588d4b1d..5150f0c602 100644 --- a/src/mesa/drivers/dri/r600/r600_state.c +++ b/src/mesa/drivers/dri/r600/r600_state.c @@ -70,27 +70,17 @@ extern void _tnl_UpdateFixedFunctionProgram(GLcontext * ctx); static void r600BlendColor(GLcontext * ctx, const GLfloat cf[4]) { r600ContextPtr rmesa = R600_CONTEXT(ctx); + GLubyte color[4]; R600_STATECHANGE(rmesa, blend_color); - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - GLuint r = IROUND(cf[0]*1023.0f); - GLuint g = IROUND(cf[1]*1023.0f); - GLuint b = IROUND(cf[2]*1023.0f); - GLuint a = IROUND(cf[3]*1023.0f); + CLAMPED_FLOAT_TO_UBYTE(color[0], cf[0]); + CLAMPED_FLOAT_TO_UBYTE(color[1], cf[1]); + CLAMPED_FLOAT_TO_UBYTE(color[2], cf[2]); + CLAMPED_FLOAT_TO_UBYTE(color[3], cf[3]); - rmesa->hw.blend_color.cmd[1] = r | (a << 16); - rmesa->hw.blend_color.cmd[2] = b | (g << 16); - } else { - GLubyte color[4]; - CLAMPED_FLOAT_TO_UBYTE(color[0], cf[0]); - CLAMPED_FLOAT_TO_UBYTE(color[1], cf[1]); - CLAMPED_FLOAT_TO_UBYTE(color[2], cf[2]); - CLAMPED_FLOAT_TO_UBYTE(color[3], cf[3]); - - rmesa->hw.blend_color.cmd[1] = PACK_COLOR_8888(color[3], color[0], - color[1], color[2]); - } + rmesa->hw.blend_color.cmd[1] = PACK_COLOR_8888(color[3], color[0], + color[1], color[2]); } /** @@ -364,10 +354,6 @@ static void r600ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) GLint p; GLint *ip; - /* no VAP UCP on non-TCL chipsets */ - if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) - return; - p = (GLint) plane - (GLint) GL_CLIP_PLANE0; ip = (GLint *)ctx->Transform._ClipUserPlane[p]; @@ -383,10 +369,6 @@ static void r600SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state) r600ContextPtr r600 = R600_CONTEXT(ctx); GLuint p; - /* no VAP UCP on non-TCL chipsets */ - if (!(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) - return; - p = cap - GL_CLIP_PLANE0; R600_STATECHANGE(r600, vap_clip_cntl); if (state) { @@ -452,16 +434,10 @@ static GLboolean current_fragment_program_writes_depth(GLcontext* ctx) { r600ContextPtr r600 = R600_CONTEXT(ctx); - if (r600->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) { - struct r600_fragment_program *fp = (struct r600_fragment_program *) - (char *)ctx->FragmentProgram._Current; - return (fp && fp->WritesDepth); - } else { - struct r500_fragment_program* fp = - (struct r500_fragment_program*)(char*) - ctx->FragmentProgram._Current; - return (fp && fp->writes_depth); - } + struct r600_fragment_program *fp = (struct r600_fragment_program *) + (char *)ctx->FragmentProgram._Current; + return (fp && fp->WritesDepth); + } static void r600SetEarlyZState(GLcontext * ctx) @@ -523,7 +499,6 @@ static void r600SetAlphaState(GLcontext * ctx) if (really_enabled) { pp_misc |= R600_FG_ALPHA_FUNC_ENABLE; - pp_misc |= R500_FG_ALPHA_FUNC_8BIT; pp_misc |= (refByte & R600_FG_ALPHA_FUNC_VAL_MASK); } else { pp_misc = 0x0; @@ -1232,41 +1207,6 @@ static void r600SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings) R600_US_TEX_INST_0, code->tex.length); } -static void r500SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings) -{ - int i; - struct r500_fragment_program *fp = (struct r500_fragment_program *) - (char *)ctx->FragmentProgram._Current; - struct r500_fragment_program_code *code = &fp->code; - - /* find all the texture instructions and relocate the texture units */ - for (i = 0; i < code->inst_end + 1; i++) { - if ((code->inst[i].inst0 & 0x3) == R500_INST_TYPE_TEX) { - uint32_t val; - int unit, opcode, new_unit; - - val = code->inst[i].inst1; - - unit = (val >> 16) & 0xf; - - val &= ~(0xf << 16); - - opcode = val & (0x7 << 22); - if (opcode == R500_TEX_INST_TEXKILL) { - new_unit = 0; - } else { - if (tmu_mappings[unit] >= 0) { - new_unit = tmu_mappings[unit]; - } else { - new_unit = 0; - } - } - val |= R500_TEX_ID(new_unit); - code->inst[i].inst1 = val; - } - } -} - static GLuint translate_lod_bias(GLfloat bias) { GLint b = (int)(bias*32); @@ -1391,18 +1331,15 @@ static void r600SetupTextures(GLcontext * ctx) if (!fp) /* should only happenen once, just after context is created */ return; - if (r600->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) { - if (fp->mesa_program.UsesKill && last_hw_tmu < 0) { - // The KILL operation requires the first texture unit - // to be enabled. - r600->hw.txe.cmd[R600_TXE_ENABLE] |= 1; - r600->hw.tex.filter.cmd[R600_TEX_VALUE_0] = 0; - r600->hw.tex.filter.cmd[R600_TEX_CMD_0] = - cmdpacket0(r600->radeon.radeonScreen, R600_TX_FILTER0_0, 1); - } - r600SetupFragmentShaderTextures(ctx, tmu_mappings); - } else - r500SetupFragmentShaderTextures(ctx, tmu_mappings); + if (fp->mesa_program.UsesKill && last_hw_tmu < 0) { + // The KILL operation requires the first texture unit + // to be enabled. + r600->hw.txe.cmd[R600_TXE_ENABLE] |= 1; + r600->hw.tex.filter.cmd[R600_TEX_VALUE_0] = 0; + r600->hw.tex.filter.cmd[R600_TEX_CMD_0] = + cmdpacket0(r600->radeon.radeonScreen, R600_TX_FILTER0_0, 1); + } + r600SetupFragmentShaderTextures(ctx, tmu_mappings); if (RADEON_DEBUG & DEBUG_STATE) fprintf(stderr, "TX_ENABLE: %08x last_hw_tmu=%d\n", @@ -1569,187 +1506,6 @@ static void r600SetupRSUnit(GLcontext * ctx) WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead); } -static void r500SetupRSUnit(GLcontext * ctx) -{ - r600ContextPtr r600 = R600_CONTEXT(ctx); - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *VB = &tnl->vb; - union r600_outputs_written OutputsWritten; - GLuint InputsRead; - int fp_reg, high_rr; - int col_ip, tex_ip; - int rs_tex_count = 0; - int i, count, col_fmt; - - if (hw_tcl_on) - OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten; - else - RENDERINPUTS_COPY(OutputsWritten.index_bitset, r600->state.render_inputs_bitset); - - if (ctx->FragmentProgram._Current) - InputsRead = ctx->FragmentProgram._Current->Base.InputsRead; - else { - fprintf(stderr, "No ctx->FragmentProgram._Current!!\n"); - return; /* This should only ever happen once.. */ - } - - R600_STATECHANGE(r600, ri); - R600_STATECHANGE(r600, rc); - R600_STATECHANGE(r600, rr); - - fp_reg = col_ip = tex_ip = col_fmt = 0; - - r600->hw.rc.cmd[1] = 0; - r600->hw.rc.cmd[2] = 0; - for (i=0; ihw.rr.cmd[R600_RR_INST_0 + i] = 0; - - for (i=0; ihw.ri.cmd[R600_RI_INTERP_0 + i] = 0; - - - if (InputsRead & FRAG_BIT_COL0) { - if (R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL0, _TNL_ATTRIB_COLOR0)) { - count = VB->AttribPtr[_TNL_ATTRIB_COLOR0]->size; - if (count == 4) - col_fmt = R600_RS_COL_FMT_RGBA; - else if (count == 3) - col_fmt = R600_RS_COL_FMT_RGB1; - else - col_fmt = R600_RS_COL_FMT_0001; - - r600->hw.ri.cmd[R600_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(col_fmt); - r600->hw.rr.cmd[R600_RR_INST_0 + col_ip] = R500_RS_INST_COL_ID(col_ip) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(fp_reg); - InputsRead &= ~FRAG_BIT_COL0; - ++col_ip; - ++fp_reg; - } else { - WARN_ONCE("fragprog wants col0, vp doesn't provide it\n"); - } - } - - if (InputsRead & FRAG_BIT_COL1) { - if (R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_COL1, _TNL_ATTRIB_COLOR1)) { - count = VB->AttribPtr[_TNL_ATTRIB_COLOR1]->size; - if (count == 4) - col_fmt = R600_RS_COL_FMT_RGBA; - else if (count == 3) - col_fmt = R600_RS_COL_FMT_RGB1; - else - col_fmt = R600_RS_COL_FMT_0001; - - r600->hw.ri.cmd[R600_RI_INTERP_0 + col_ip] = R500_RS_COL_PTR(col_ip) | R500_RS_COL_FMT(col_fmt); - r600->hw.rr.cmd[R600_RR_INST_0 + col_ip] = R500_RS_INST_COL_ID(col_ip) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(fp_reg); - InputsRead &= ~FRAG_BIT_COL1; - ++col_ip; - ++fp_reg; - } else { - WARN_ONCE("fragprog wants col1, vp doesn't provide it\n"); - } - } - - - for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - if (! ( InputsRead & FRAG_BIT_TEX(i) ) ) - continue; - - if (!R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_TEX0 + i, _TNL_ATTRIB_TEX(i))) { - WARN_ONCE("fragprog wants coords for tex%d, vp doesn't provide them!\n", i); - continue; - } - - int swiz = 0; - - /* with TCL we always seem to route 4 components */ - if (hw_tcl_on) - count = 4; - else - count = VB->AttribPtr[_TNL_ATTRIB_TEX(i)]->size; - - if (count == 4) { - swiz |= (rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT; - swiz |= (rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT; - swiz |= (rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT; - swiz |= (rs_tex_count + 3) << R500_RS_IP_TEX_PTR_Q_SHIFT; - } else if (count == 3) { - swiz |= (rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT; - swiz |= (rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT; - swiz |= (rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT; - swiz |= R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT; - } else if (count == 2) { - swiz |= (rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT; - swiz |= (rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT; - swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT; - swiz |= R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT; - } else if (count == 1) { - swiz |= (rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT; - swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT; - swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT; - swiz |= R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT; - } else { - swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT; - swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT; - swiz |= R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT; - swiz |= R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT; - } - - r600->hw.ri.cmd[R600_RI_INTERP_0 + tex_ip] |= swiz; - r600->hw.rr.cmd[R600_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg); - InputsRead &= ~(FRAG_BIT_TEX0 << i); - rs_tex_count += count; - ++tex_ip; - ++fp_reg; - } - - if (InputsRead & FRAG_BIT_FOGC) { - if (R600_OUTPUTS_WRITTEN_TEST(OutputsWritten, VERT_RESULT_FOGC, _TNL_ATTRIB_FOG)) { - r600->hw.ri.cmd[R600_RI_INTERP_0 + tex_ip] |= ((rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT) | - ((rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT) | - ((rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT) | - ((rs_tex_count + 3) << R500_RS_IP_TEX_PTR_Q_SHIFT); - - r600->hw.rr.cmd[R600_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg); - InputsRead &= ~FRAG_BIT_FOGC; - rs_tex_count += 4; - ++tex_ip; - ++fp_reg; - } else { - WARN_ONCE("fragprog wants fogc, vp doesn't provide it\n"); - } - } - - if (InputsRead & FRAG_BIT_WPOS) { - r600->hw.ri.cmd[R600_RI_INTERP_0 + tex_ip] |= ((rs_tex_count + 0) << R500_RS_IP_TEX_PTR_S_SHIFT) | - ((rs_tex_count + 1) << R500_RS_IP_TEX_PTR_T_SHIFT) | - ((rs_tex_count + 2) << R500_RS_IP_TEX_PTR_R_SHIFT) | - ((rs_tex_count + 3) << R500_RS_IP_TEX_PTR_Q_SHIFT); - - r600->hw.rr.cmd[R600_RR_INST_0 + tex_ip] |= R500_RS_INST_TEX_ID(tex_ip) | R500_RS_INST_TEX_CN_WRITE | R500_RS_INST_TEX_ADDR(fp_reg); - InputsRead &= ~FRAG_BIT_WPOS; - rs_tex_count += 4; - ++tex_ip; - ++fp_reg; - } - - /* Setup default color if no color or tex was set */ - if (rs_tex_count == 0 && col_ip == 0) { - r600->hw.rr.cmd[R600_RR_INST_0] |= R500_RS_INST_COL_ID(0) | R500_RS_INST_COL_CN_WRITE | R500_RS_INST_COL_ADDR(0) | R500_RS_COL_FMT(R600_RS_COL_FMT_0001); - ++col_ip; - } - - high_rr = (col_ip > tex_ip) ? col_ip : tex_ip; - r600->hw.rc.cmd[1] |= (rs_tex_count << R600_IT_COUNT_SHIFT) | (col_ip << R600_IC_COUNT_SHIFT) | R600_HIRES_EN; - r600->hw.rc.cmd[2] |= 0xC0 | (high_rr - 1); - - r600->hw.rr.cmd[R600_RR_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R500_RS_INST_0, high_rr); - - if (InputsRead) - WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead); -} - - - - #define bump_vpu_count(ptr, new_count) do{\ drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\ int _nc=(new_count)/4; \ @@ -1827,8 +1583,6 @@ static void r600VapCntl(r600ContextPtr rmesa, GLuint input_count, (pvs_num_slots << R600_PVS_NUM_SLOTS_SHIFT) | (pvs_num_cntrls << R600_PVS_NUM_CNTLRS_SHIFT) | (12 << R600_VF_MAX_VTX_NUM_SHIFT); - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) - rmesa->hw.vap_cntl.cmd[R600_VAP_CNTL_INSTR] |= R500_TCL_STATE_OPTIMIZATION; } else /* not sure about non-tcl */ rmesa->hw.vap_cntl.cmd[R600_VAP_CNTL_INSTR] = ((10 << R600_PVS_NUM_SLOTS_SHIFT) | @@ -2030,10 +1784,6 @@ static void r600Enable(GLcontext * ctx, GLenum cap, GLboolean state) static void r600ResetHwState(r600ContextPtr r600) { GLcontext *ctx = r600->radeon.glCtx; - int has_tcl = 1; - - if (!(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) - has_tcl = 0; if (RADEON_DEBUG & DEBUG_STATE) fprintf(stderr, "%s\n", __FUNCTION__); @@ -2083,29 +1833,22 @@ static void r600ResetHwState(r600ContextPtr r600) r600->hw.vap_cntl_status.cmd[1] = R600_VC_32BIT_SWAP; #endif - /* disable VAP/TCL on non-TCL capable chips */ - if (!has_tcl) - r600->hw.vap_cntl_status.cmd[1] |= R600_VAP_TCL_BYPASS; - r600->hw.vap_psc_sgn_norm_cntl.cmd[1] = 0xAAAAAAAA; - /* XXX: Other families? */ - if (has_tcl) { - r600->hw.vap_clip_cntl.cmd[1] = R600_PS_UCP_MODE_DIST_COP; + r600->hw.vap_clip_cntl.cmd[1] = R600_PS_UCP_MODE_DIST_COP; - r600->hw.vap_clip.cmd[1] = r600PackFloat32(1.0); /* X */ - r600->hw.vap_clip.cmd[2] = r600PackFloat32(1.0); /* X */ - r600->hw.vap_clip.cmd[3] = r600PackFloat32(1.0); /* Y */ - r600->hw.vap_clip.cmd[4] = r600PackFloat32(1.0); /* Y */ + r600->hw.vap_clip.cmd[1] = r600PackFloat32(1.0); /* X */ + r600->hw.vap_clip.cmd[2] = r600PackFloat32(1.0); /* X */ + r600->hw.vap_clip.cmd[3] = r600PackFloat32(1.0); /* Y */ + r600->hw.vap_clip.cmd[4] = r600PackFloat32(1.0); /* Y */ - switch (r600->radeon.radeonScreen->chip_family) { - case CHIP_FAMILY_R600: - r600->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R600_2288_R600; - break; - default: - r600->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R600_2288_RV350; - break; - } + switch (r600->radeon.radeonScreen->chip_family) { + case CHIP_FAMILY_R600: + r600->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R600_2288_R600; + break; + default: + r600->hw.vap_pvs_vtx_timeout_reg.cmd[1] = R600_2288_RV350; + break; } r600->hw.gb_enable.cmd[1] = R600_GB_POINT_STUFF_ENABLE @@ -2180,14 +1923,6 @@ static void r600ResetHwState(r600ContextPtr r600) r600->hw.sc_screendoor.cmd[1] = 0x00FFFFFF; - r600->hw.us_out_fmt.cmd[1] = R500_OUT_FMT_C4_8 | - R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A; - r600->hw.us_out_fmt.cmd[2] = R500_OUT_FMT_UNUSED | - R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A; - r600->hw.us_out_fmt.cmd[3] = R500_OUT_FMT_UNUSED | - R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A; - r600->hw.us_out_fmt.cmd[4] = R500_OUT_FMT_UNUSED | - R500_C0_SEL_B | R500_C1_SEL_G | R500_C2_SEL_R | R500_C3_SEL_A; r600->hw.us_out_fmt.cmd[5] = R600_W_FMT_W0 | R600_W_SRC_US; /* disable fog unit */ @@ -2210,9 +1945,6 @@ static void r600ResetHwState(r600ContextPtr r600) r600->hw.rb3d_aaresolve_ctl.cmd[1] = 0; - r600->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000; - r600->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff; - r600->hw.zb_depthclearvalue.cmd[1] = 0; r600->hw.zstencil_format.cmd[2] = R600_ZTOP_DISABLE; @@ -2228,12 +1960,11 @@ static void r600ResetHwState(r600ContextPtr r600) r600->hw.zb_hiz_pitch.cmd[1] = 0; r600VapCntl(r600, 0, 0, 0); - if (has_tcl) { - r600->hw.vps.cmd[R600_VPS_ZERO_0] = 0; - r600->hw.vps.cmd[R600_VPS_ZERO_1] = 0; - r600->hw.vps.cmd[R600_VPS_POINTSIZE] = r600PackFloat32(1.0); - r600->hw.vps.cmd[R600_VPS_ZERO_3] = 0; - } + + r600->hw.vps.cmd[R600_VPS_ZERO_0] = 0; + r600->hw.vps.cmd[R600_VPS_ZERO_1] = 0; + r600->hw.vps.cmd[R600_VPS_POINTSIZE] = r600PackFloat32(1.0); + r600->hw.vps.cmd[R600_VPS_ZERO_3] = 0; r600->radeon.hw.all_dirty = GL_TRUE; } @@ -2371,82 +2102,6 @@ static void r600SetupPixelShader(r600ContextPtr rmesa) } } -#define bump_r500fp_count(ptr, new_count) do{\ - drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\ - int _nc=(new_count)/6; \ - assert(_nc < 256); \ - if(_nc>_p->r500fp.count)_p->r500fp.count=_nc;\ -} while(0) - -#define bump_r500fp_const_count(ptr, new_count) do{\ - drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr));\ - int _nc=(new_count)/4; \ - assert(_nc < 256); \ - if(_nc>_p->r500fp.count)_p->r500fp.count=_nc;\ -} while(0) - -static void r500SetupPixelShader(r600ContextPtr rmesa) -{ - GLcontext *ctx = rmesa->radeon.glCtx; - struct r500_fragment_program *fp = (struct r500_fragment_program *) - (char *)ctx->FragmentProgram._Current; - int i; - struct r500_fragment_program_code *code; - - if (!fp) /* should only happenen once, just after context is created */ - return; - - ((drm_r300_cmd_header_t *) rmesa->hw.r500fp.cmd)->r500fp.count = 0; - ((drm_r300_cmd_header_t *) rmesa->hw.r500fp_const.cmd)->r500fp.count = 0; - - r500TranslateFragmentShader(rmesa, fp); - if (!fp->translated) { - fprintf(stderr, "%s: No valid fragment shader, exiting\n", - __FUNCTION__); - return; - } - code = &fp->code; - - r600SetupTextures(ctx); - - R600_STATECHANGE(rmesa, fp); - rmesa->hw.fp.cmd[R500_FP_PIXSIZE] = code->max_temp_idx; - - rmesa->hw.fp.cmd[R500_FP_CODE_ADDR] = - R500_US_CODE_START_ADDR(code->inst_offset) | - R500_US_CODE_END_ADDR(code->inst_end); - rmesa->hw.fp.cmd[R500_FP_CODE_RANGE] = - R500_US_CODE_RANGE_ADDR(code->inst_offset) | - R500_US_CODE_RANGE_SIZE(code->inst_end); - rmesa->hw.fp.cmd[R500_FP_CODE_OFFSET] = - R500_US_CODE_OFFSET_ADDR(0); /* FIXME when we add flow control */ - - R600_STATECHANGE(rmesa, r500fp); - /* Emit our shader... */ - for (i = 0; i < code->inst_end+1; i++) { - rmesa->hw.r500fp.cmd[i*6+1] = code->inst[i].inst0; - rmesa->hw.r500fp.cmd[i*6+2] = code->inst[i].inst1; - rmesa->hw.r500fp.cmd[i*6+3] = code->inst[i].inst2; - rmesa->hw.r500fp.cmd[i*6+4] = code->inst[i].inst3; - rmesa->hw.r500fp.cmd[i*6+5] = code->inst[i].inst4; - rmesa->hw.r500fp.cmd[i*6+6] = code->inst[i].inst5; - } - - bump_r500fp_count(rmesa->hw.r500fp.cmd, (code->inst_end + 1) * 6); - - R600_STATECHANGE(rmesa, r500fp_const); - for (i = 0; i < code->const_nr; i++) { - const GLfloat *constant = get_fragmentprogram_constant(ctx, - &fp->mesa_program.Base, code->constant[i]); - rmesa->hw.r500fp_const.cmd[R600_FPP_PARAM_0 + 4 * i + 0] = r600PackFloat32(constant[0]); - rmesa->hw.r500fp_const.cmd[R600_FPP_PARAM_0 + 4 * i + 1] = r600PackFloat32(constant[1]); - rmesa->hw.r500fp_const.cmd[R600_FPP_PARAM_0 + 4 * i + 2] = r600PackFloat32(constant[2]); - rmesa->hw.r500fp_const.cmd[R600_FPP_PARAM_0 + 4 * i + 3] = r600PackFloat32(constant[3]); - } - bump_r500fp_const_count(rmesa->hw.r500fp_const.cmd, code->const_nr * 4); - -} - void r600UpdateShaderStates(r600ContextPtr rmesa) { GLcontext *ctx; @@ -2475,18 +2130,11 @@ void r600UpdateShaderStates(r600ContextPtr rmesa) rmesa->hw.fg_depth_src.cmd[1] = fgdepthsrc; } - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) - r500SetupPixelShader(rmesa); - else - r600SetupPixelShader(rmesa); + r600SetupPixelShader(rmesa); - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) - r500SetupRSUnit(ctx); - else - r600SetupRSUnit(ctx); + r600SetupRSUnit(ctx); - if ((rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) - r600SetupVertexProgram(rmesa); + r600SetupVertexProgram(rmesa); } diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 6beafafe83..e9fbdf32b0 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -239,12 +239,6 @@ static void setup_hardware_state(r600ContextPtr rmesa, radeonTexObj *t) t->pp_txpitch = ((firstImage->Width + align) & ~align) - 1; } - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - if (firstImage->Width > 2048) - t->pp_txpitch |= R500_TXWIDTH_BIT11; - if (firstImage->Height > 2048) - t->pp_txpitch |= R500_TXHEIGHT_BIT11; - } } /** @@ -471,12 +465,6 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo t->pp_txsize |= R600_TX_SIZE_TXPITCH_EN; t->pp_txpitch |= pitch_val; - if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - if (rb->width > 2048) - t->pp_txpitch |= R500_TXWIDTH_BIT11; - if (rb->height > 2048) - t->pp_txpitch |= R500_TXHEIGHT_BIT11; - } t->validated = GL_TRUE; _mesa_unlock_texture(radeon->glCtx, texObj); return; diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c deleted file mode 100644 index c14c7d36a4..0000000000 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ /dev/null @@ -1,719 +0,0 @@ -/* - * Copyright 2008 Corbin Simpson - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "r700_fragprog.h" - -#include "radeon_nqssadce.h" -#include "radeon_program_alu.h" - - -static void reset_srcreg(struct prog_src_register* reg) -{ - _mesa_bzero(reg, sizeof(*reg)); - reg->Swizzle = SWIZZLE_NOOP; -} - -static struct prog_src_register shadow_ambient(struct gl_program *program, int tmu) -{ - gl_state_index fail_value_tokens[STATE_LENGTH] = { - STATE_INTERNAL, STATE_SHADOW_AMBIENT, 0, 0, 0 - }; - struct prog_src_register reg = { 0, }; - - fail_value_tokens[2] = tmu; - reg.File = PROGRAM_STATE_VAR; - reg.Index = _mesa_add_state_reference(program->Parameters, fail_value_tokens); - reg.Swizzle = SWIZZLE_WWWW; - return reg; -} - -/** - * Transform TEX, TXP, TXB, and KIL instructions in the following way: - * - premultiply texture coordinates for RECT - * - extract operand swizzles - * - introduce a temporary register when write masks are needed - * - */ -static GLboolean transform_TEX( - struct radeon_transform_context *t, - struct prog_instruction* orig_inst, void* data) -{ - struct r500_fragment_program_compiler *compiler = - (struct r500_fragment_program_compiler*)data; - struct prog_instruction inst = *orig_inst; - struct prog_instruction* tgt; - GLboolean destredirect = GL_FALSE; - - if (inst.Opcode != OPCODE_TEX && - inst.Opcode != OPCODE_TXB && - inst.Opcode != OPCODE_TXP && - inst.Opcode != OPCODE_KIL) - return GL_FALSE; - - /* ARB_shadow & EXT_shadow_funcs */ - if (inst.Opcode != OPCODE_KIL && - t->Program->ShadowSamplers & (1 << inst.TexSrcUnit)) { - GLuint comparefunc = GL_NEVER + compiler->fp->state.unit[inst.TexSrcUnit].texture_compare_func; - - if (comparefunc == GL_NEVER || comparefunc == GL_ALWAYS) { - tgt = radeonAppendInstructions(t->Program, 1); - - tgt->Opcode = OPCODE_MOV; - tgt->DstReg = inst.DstReg; - if (comparefunc == GL_ALWAYS) { - tgt->SrcReg[0].File = PROGRAM_BUILTIN; - tgt->SrcReg[0].Swizzle = SWIZZLE_1111; - } else { - tgt->SrcReg[0] = shadow_ambient(t->Program, inst.TexSrcUnit); - } - return GL_TRUE; - } - - inst.DstReg.File = PROGRAM_TEMPORARY; - inst.DstReg.Index = radeonFindFreeTemporary(t); - inst.DstReg.WriteMask = WRITEMASK_XYZW; - } else if (inst.Opcode != OPCODE_KIL && inst.DstReg.File != PROGRAM_TEMPORARY) { - int tempreg = radeonFindFreeTemporary(t); - - inst.DstReg.File = PROGRAM_TEMPORARY; - inst.DstReg.Index = tempreg; - inst.DstReg.WriteMask = WRITEMASK_XYZW; - destredirect = GL_TRUE; - } - - if (inst.SrcReg[0].File != PROGRAM_TEMPORARY && inst.SrcReg[0].File != PROGRAM_INPUT) { - int tmpreg = radeonFindFreeTemporary(t); - tgt = radeonAppendInstructions(t->Program, 1); - tgt->Opcode = OPCODE_MOV; - tgt->DstReg.File = PROGRAM_TEMPORARY; - tgt->DstReg.Index = tmpreg; - tgt->SrcReg[0] = inst.SrcReg[0]; - - reset_srcreg(&inst.SrcReg[0]); - inst.SrcReg[0].File = PROGRAM_TEMPORARY; - inst.SrcReg[0].Index = tmpreg; - } - - tgt = radeonAppendInstructions(t->Program, 1); - _mesa_copy_instructions(tgt, &inst, 1); - - if (inst.Opcode != OPCODE_KIL && - t->Program->ShadowSamplers & (1 << inst.TexSrcUnit)) { - GLuint comparefunc = GL_NEVER + compiler->fp->state.unit[inst.TexSrcUnit].texture_compare_func; - GLuint depthmode = compiler->fp->state.unit[inst.TexSrcUnit].depth_texture_mode; - int rcptemp = radeonFindFreeTemporary(t); - int pass, fail; - - tgt = radeonAppendInstructions(t->Program, 3); - - tgt[0].Opcode = OPCODE_RCP; - tgt[0].DstReg.File = PROGRAM_TEMPORARY; - tgt[0].DstReg.Index = rcptemp; - tgt[0].DstReg.WriteMask = WRITEMASK_W; - tgt[0].SrcReg[0] = inst.SrcReg[0]; - tgt[0].SrcReg[0].Swizzle = SWIZZLE_WWWW; - - tgt[1].Opcode = OPCODE_MAD; - tgt[1].DstReg = inst.DstReg; - tgt[1].DstReg.WriteMask = orig_inst->DstReg.WriteMask; - tgt[1].SrcReg[0] = inst.SrcReg[0]; - tgt[1].SrcReg[0].Swizzle = SWIZZLE_ZZZZ; - tgt[1].SrcReg[1].File = PROGRAM_TEMPORARY; - tgt[1].SrcReg[1].Index = rcptemp; - tgt[1].SrcReg[1].Swizzle = SWIZZLE_WWWW; - tgt[1].SrcReg[2].File = PROGRAM_TEMPORARY; - tgt[1].SrcReg[2].Index = inst.DstReg.Index; - if (depthmode == 0) /* GL_LUMINANCE */ - tgt[1].SrcReg[2].Swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z); - else if (depthmode == 2) /* GL_ALPHA */ - tgt[1].SrcReg[2].Swizzle = SWIZZLE_WWWW; - - /* Recall that SrcReg[0] is tex, SrcReg[2] is r and: - * r < tex <=> -tex+r < 0 - * r >= tex <=> not (-tex+r < 0 */ - if (comparefunc == GL_LESS || comparefunc == GL_GEQUAL) - tgt[1].SrcReg[2].NegateBase = tgt[0].SrcReg[2].NegateBase ^ NEGATE_XYZW; - else - tgt[1].SrcReg[0].NegateBase = tgt[0].SrcReg[0].NegateBase ^ NEGATE_XYZW; - - tgt[2].Opcode = OPCODE_CMP; - tgt[2].DstReg = orig_inst->DstReg; - tgt[2].SrcReg[0].File = PROGRAM_TEMPORARY; - tgt[2].SrcReg[0].Index = tgt[1].DstReg.Index; - - if (comparefunc == GL_LESS || comparefunc == GL_GREATER) { - pass = 1; - fail = 2; - } else { - pass = 2; - fail = 1; - } - - tgt[2].SrcReg[pass].File = PROGRAM_BUILTIN; - tgt[2].SrcReg[pass].Swizzle = SWIZZLE_1111; - tgt[2].SrcReg[fail] = shadow_ambient(t->Program, inst.TexSrcUnit); - } else if (destredirect) { - tgt = radeonAppendInstructions(t->Program, 1); - - tgt->Opcode = OPCODE_MOV; - tgt->DstReg = orig_inst->DstReg; - tgt->SrcReg[0].File = PROGRAM_TEMPORARY; - tgt->SrcReg[0].Index = inst.DstReg.Index; - } - - return GL_TRUE; -} - - -static void update_params(r600ContextPtr r600, struct r500_fragment_program *fp) -{ - struct gl_fragment_program *mp = &fp->mesa_program; - - /* Ask Mesa nicely to fill in ParameterValues for us */ - if (mp->Base.Parameters) - _mesa_load_state_parameters(r600->radeon.glCtx, mp->Base.Parameters); -} - - -/** - * Transform the program to support fragment.position. - * - * Introduce a small fragment at the start of the program that will be - * the only code that directly reads the FRAG_ATTRIB_WPOS input. - * All other code pieces that reference that input will be rewritten - * to read from a newly allocated temporary. - * - * \todo if/when r5xx supports the radeon_program architecture, this is a - * likely candidate for code sharing. - */ -static void insert_WPOS_trailer(struct r500_fragment_program_compiler *compiler) -{ - GLuint InputsRead = compiler->fp->mesa_program.Base.InputsRead; - - if (!(InputsRead & FRAG_BIT_WPOS)) - return; - - static gl_state_index tokens[STATE_LENGTH] = { - STATE_INTERNAL, STATE_R600_WINDOW_DIMENSION, 0, 0, 0 - }; - struct prog_instruction *fpi; - GLuint window_index; - int i = 0; - GLuint tempregi = _mesa_find_free_register(compiler->program, PROGRAM_TEMPORARY); - - _mesa_insert_instructions(compiler->program, 0, 3); - fpi = compiler->program->Instructions; - - /* perspective divide */ - fpi[i].Opcode = OPCODE_RCP; - - fpi[i].DstReg.File = PROGRAM_TEMPORARY; - fpi[i].DstReg.Index = tempregi; - fpi[i].DstReg.WriteMask = WRITEMASK_W; - fpi[i].DstReg.CondMask = COND_TR; - - fpi[i].SrcReg[0].File = PROGRAM_INPUT; - fpi[i].SrcReg[0].Index = FRAG_ATTRIB_WPOS; - fpi[i].SrcReg[0].Swizzle = SWIZZLE_WWWW; - i++; - - fpi[i].Opcode = OPCODE_MUL; - - fpi[i].DstReg.File = PROGRAM_TEMPORARY; - fpi[i].DstReg.Index = tempregi; - fpi[i].DstReg.WriteMask = WRITEMASK_XYZ; - fpi[i].DstReg.CondMask = COND_TR; - - fpi[i].SrcReg[0].File = PROGRAM_INPUT; - fpi[i].SrcReg[0].Index = FRAG_ATTRIB_WPOS; - fpi[i].SrcReg[0].Swizzle = SWIZZLE_XYZW; - - fpi[i].SrcReg[1].File = PROGRAM_TEMPORARY; - fpi[i].SrcReg[1].Index = tempregi; - fpi[i].SrcReg[1].Swizzle = SWIZZLE_WWWW; - i++; - - /* viewport transformation */ - window_index = _mesa_add_state_reference(compiler->program->Parameters, tokens); - - fpi[i].Opcode = OPCODE_MAD; - - fpi[i].DstReg.File = PROGRAM_TEMPORARY; - fpi[i].DstReg.Index = tempregi; - fpi[i].DstReg.WriteMask = WRITEMASK_XYZ; - fpi[i].DstReg.CondMask = COND_TR; - - fpi[i].SrcReg[0].File = PROGRAM_TEMPORARY; - fpi[i].SrcReg[0].Index = tempregi; - fpi[i].SrcReg[0].Swizzle = - MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO); - - fpi[i].SrcReg[1].File = PROGRAM_STATE_VAR; - fpi[i].SrcReg[1].Index = window_index; - fpi[i].SrcReg[1].Swizzle = - MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO); - - fpi[i].SrcReg[2].File = PROGRAM_STATE_VAR; - fpi[i].SrcReg[2].Index = window_index; - fpi[i].SrcReg[2].Swizzle = - MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO); - i++; - - for (; i < compiler->program->NumInstructions; ++i) { - int reg; - for (reg = 0; reg < 3; reg++) { - if (fpi[i].SrcReg[reg].File == PROGRAM_INPUT && - fpi[i].SrcReg[reg].Index == FRAG_ATTRIB_WPOS) { - fpi[i].SrcReg[reg].File = PROGRAM_TEMPORARY; - fpi[i].SrcReg[reg].Index = tempregi; - } - } - } -} - - -static void nqssadce_init(struct nqssadce_state* s) -{ - s->Outputs[FRAG_RESULT_COLOR].Sourced = WRITEMASK_XYZW; - s->Outputs[FRAG_RESULT_DEPTH].Sourced = WRITEMASK_W; -} - -static GLboolean is_native_swizzle(GLuint opcode, struct prog_src_register reg) -{ - GLuint relevant; - int i; - - if (opcode == OPCODE_TEX || - opcode == OPCODE_TXB || - opcode == OPCODE_TXP || - opcode == OPCODE_KIL) { - if (reg.Abs) - return GL_FALSE; - - if (reg.NegateAbs) - reg.NegateBase ^= 15; - - if (opcode == OPCODE_KIL) { - if (reg.Swizzle != SWIZZLE_NOOP) - return GL_FALSE; - } else { - for(i = 0; i < 4; ++i) { - GLuint swz = GET_SWZ(reg.Swizzle, i); - if (swz == SWIZZLE_NIL) { - reg.NegateBase &= ~(1 << i); - continue; - } - if (swz >= 4) - return GL_FALSE; - } - } - - if (reg.NegateBase) - return GL_FALSE; - - return GL_TRUE; - } else if (opcode == OPCODE_DDX || opcode == OPCODE_DDY) { - /* DDX/MDH and DDY/MDV explicitly ignore incoming swizzles; - * if it doesn't fit perfectly into a .xyzw case... */ - if (reg.Swizzle == SWIZZLE_NOOP && !reg.Abs - && !reg.NegateBase && !reg.NegateAbs) - return GL_TRUE; - - return GL_FALSE; - } else { - /* ALU instructions support almost everything */ - if (reg.Abs) - return GL_TRUE; - - relevant = 0; - for(i = 0; i < 3; ++i) { - GLuint swz = GET_SWZ(reg.Swizzle, i); - if (swz != SWIZZLE_NIL && swz != SWIZZLE_ZERO) - relevant |= 1 << i; - } - if ((reg.NegateBase & relevant) && ((reg.NegateBase & relevant) != relevant)) - return GL_FALSE; - - return GL_TRUE; - } -} - -/** - * Implement a MOV with a potentially non-native swizzle. - * - * The only thing we *cannot* do in an ALU instruction is per-component - * negation. Therefore, we split the MOV into two instructions when necessary. - */ -static void nqssadce_build_swizzle(struct nqssadce_state *s, - struct prog_dst_register dst, struct prog_src_register src) -{ - struct prog_instruction *inst; - GLuint negatebase[2] = { 0, 0 }; - int i; - - for(i = 0; i < 4; ++i) { - GLuint swz = GET_SWZ(src.Swizzle, i); - if (swz == SWIZZLE_NIL) - continue; - negatebase[GET_BIT(src.NegateBase, i)] |= 1 << i; - } - - _mesa_insert_instructions(s->Program, s->IP, (negatebase[0] ? 1 : 0) + (negatebase[1] ? 1 : 0)); - inst = s->Program->Instructions + s->IP; - - for(i = 0; i <= 1; ++i) { - if (!negatebase[i]) - continue; - - inst->Opcode = OPCODE_MOV; - inst->DstReg = dst; - inst->DstReg.WriteMask = negatebase[i]; - inst->SrcReg[0] = src; - inst++; - s->IP++; - } -} - -static GLuint build_dtm(GLuint depthmode) -{ - switch(depthmode) { - default: - case GL_LUMINANCE: return 0; - case GL_INTENSITY: return 1; - case GL_ALPHA: return 2; - } -} - -static GLuint build_func(GLuint comparefunc) -{ - return comparefunc - GL_NEVER; -} - - -/** - * Collect all external state that is relevant for compiling the given - * fragment program. - */ -static void build_state( - r600ContextPtr r600, - struct r500_fragment_program *fp, - struct r500_fragment_program_external_state *state) -{ - int unit; - - _mesa_bzero(state, sizeof(*state)); - - for(unit = 0; unit < 16; ++unit) { - if (fp->mesa_program.Base.ShadowSamplers & (1 << unit)) { - struct gl_texture_object* tex = r600->radeon.glCtx->Texture.Unit[unit]._Current; - - state->unit[unit].depth_texture_mode = build_dtm(tex->DepthMode); - state->unit[unit].texture_compare_func = build_func(tex->CompareFunc); - } - } -} - -static void dump_program(struct r500_fragment_program_code *code); - -void r500TranslateFragmentShader(r600ContextPtr r600, - struct r500_fragment_program *fp) -{ - struct r500_fragment_program_external_state state; - - build_state(r600, fp, &state); - if (_mesa_memcmp(&fp->state, &state, sizeof(state))) { - /* TODO: cache compiled programs */ - fp->translated = GL_FALSE; - _mesa_memcpy(&fp->state, &state, sizeof(state)); - } - - if (!fp->translated) { - struct r500_fragment_program_compiler compiler; - - compiler.r600 = r600; - compiler.fp = fp; - compiler.code = &fp->code; - compiler.program = _mesa_clone_program(r600->radeon.glCtx, &fp->mesa_program.Base); - - if (RADEON_DEBUG & DEBUG_PIXEL) { - _mesa_printf("Compiler: Initial program:\n"); - _mesa_print_program(compiler.program); - } - - insert_WPOS_trailer(&compiler); - - struct radeon_program_transformation transformations[] = { - { &transform_TEX, &compiler }, - { &radeonTransformALU, 0 }, - { &radeonTransformDeriv, 0 }, - { &radeonTransformTrigScale, 0 } - }; - radeonLocalTransform(r600->radeon.glCtx, compiler.program, - 4, transformations); - - if (RADEON_DEBUG & DEBUG_PIXEL) { - _mesa_printf("Compiler: after native rewrite:\n"); - _mesa_print_program(compiler.program); - } - - struct radeon_nqssadce_descr nqssadce = { - .Init = &nqssadce_init, - .IsNativeSwizzle = &is_native_swizzle, - .BuildSwizzle = &nqssadce_build_swizzle, - .RewriteDepthOut = GL_TRUE - }; - radeonNqssaDce(r600->radeon.glCtx, compiler.program, &nqssadce); - - if (RADEON_DEBUG & DEBUG_PIXEL) { - _mesa_printf("Compiler: after NqSSA-DCE:\n"); - _mesa_print_program(compiler.program); - } - - fp->translated = r500FragmentProgramEmit(&compiler); - - /* Subtle: Rescue any parameters that have been added during transformations */ - _mesa_free_parameter_list(fp->mesa_program.Base.Parameters); - fp->mesa_program.Base.Parameters = compiler.program->Parameters; - compiler.program->Parameters = 0; - - _mesa_reference_program(r600->radeon.glCtx, &compiler.program, 0); - - r600UpdateStateParameters(r600->radeon.glCtx, _NEW_PROGRAM); - - if (RADEON_DEBUG & DEBUG_PIXEL) { - if (fp->translated) { - _mesa_printf("Machine-readable code:\n"); - dump_program(&fp->code); - } - } - - } - - update_params(r600, fp); - -} - -static char *toswiz(int swiz_val) { - switch(swiz_val) { - case 0: return "R"; - case 1: return "G"; - case 2: return "B"; - case 3: return "A"; - case 4: return "0"; - case 5: return "1/2"; - case 6: return "1"; - case 7: return "U"; - } - return NULL; -} - -static char *toop(int op_val) -{ - char *str = NULL; - switch (op_val) { - case 0: str = "MAD"; break; - case 1: str = "DP3"; break; - case 2: str = "DP4"; break; - case 3: str = "D2A"; break; - case 4: str = "MIN"; break; - case 5: str = "MAX"; break; - case 6: str = "Reserved"; break; - case 7: str = "CND"; break; - case 8: str = "CMP"; break; - case 9: str = "FRC"; break; - case 10: str = "SOP"; break; - case 11: str = "MDH"; break; - case 12: str = "MDV"; break; - } - return str; -} - -static char *to_alpha_op(int op_val) -{ - char *str = NULL; - switch (op_val) { - case 0: str = "MAD"; break; - case 1: str = "DP"; break; - case 2: str = "MIN"; break; - case 3: str = "MAX"; break; - case 4: str = "Reserved"; break; - case 5: str = "CND"; break; - case 6: str = "CMP"; break; - case 7: str = "FRC"; break; - case 8: str = "EX2"; break; - case 9: str = "LN2"; break; - case 10: str = "RCP"; break; - case 11: str = "RSQ"; break; - case 12: str = "SIN"; break; - case 13: str = "COS"; break; - case 14: str = "MDH"; break; - case 15: str = "MDV"; break; - } - return str; -} - -static char *to_mask(int val) -{ - char *str = NULL; - switch(val) { - case 0: str = "NONE"; break; - case 1: str = "R"; break; - case 2: str = "G"; break; - case 3: str = "RG"; break; - case 4: str = "B"; break; - case 5: str = "RB"; break; - case 6: str = "GB"; break; - case 7: str = "RGB"; break; - case 8: str = "A"; break; - case 9: str = "AR"; break; - case 10: str = "AG"; break; - case 11: str = "ARG"; break; - case 12: str = "AB"; break; - case 13: str = "ARB"; break; - case 14: str = "AGB"; break; - case 15: str = "ARGB"; break; - } - return str; -} - -static char *to_texop(int val) -{ - switch(val) { - case 0: return "NOP"; - case 1: return "LD"; - case 2: return "TEXKILL"; - case 3: return "PROJ"; - case 4: return "LODBIAS"; - case 5: return "LOD"; - case 6: return "DXDY"; - } - return NULL; -} - -static void dump_program(struct r500_fragment_program_code *code) -{ - - fprintf(stderr, "R500 Fragment Program:\n--------\n"); - - int n; - uint32_t inst; - uint32_t inst0; - char *str = NULL; - - if (code->const_nr) { - fprintf(stderr, "--------\nConstants:\n"); - for (n = 0; n < code->const_nr; n++) { - fprintf(stderr, "Constant %d: %i[%i]\n", n, - code->constant[n].File, code->constant[n].Index); - } - fprintf(stderr, "--------\n"); - } - - for (n = 0; n < code->inst_end+1; n++) { - inst0 = inst = code->inst[n].inst0; - fprintf(stderr,"%d\t0:CMN_INST 0x%08x:", n, inst); - switch(inst & 0x3) { - case R500_INST_TYPE_ALU: str = "ALU"; break; - case R500_INST_TYPE_OUT: str = "OUT"; break; - case R500_INST_TYPE_FC: str = "FC"; break; - case R500_INST_TYPE_TEX: str = "TEX"; break; - }; - fprintf(stderr,"%s %s %s %s %s ", str, - inst & R500_INST_TEX_SEM_WAIT ? "TEX_WAIT" : "", - inst & R500_INST_LAST ? "LAST" : "", - inst & R500_INST_NOP ? "NOP" : "", - inst & R500_INST_ALU_WAIT ? "ALU WAIT" : ""); - fprintf(stderr,"wmask: %s omask: %s\n", to_mask((inst >> 11) & 0xf), - to_mask((inst >> 15) & 0xf)); - - switch(inst0 & 0x3) { - case 0: - case 1: - fprintf(stderr,"\t1:RGB_ADDR 0x%08x:", code->inst[n].inst1); - inst = code->inst[n].inst1; - - fprintf(stderr,"Addr0: %d%c, Addr1: %d%c, Addr2: %d%c, srcp:%d\n", - inst & 0xff, (inst & (1<<8)) ? 'c' : 't', - (inst >> 10) & 0xff, (inst & (1<<18)) ? 'c' : 't', - (inst >> 20) & 0xff, (inst & (1<<28)) ? 'c' : 't', - (inst >> 30)); - - fprintf(stderr,"\t2:ALPHA_ADDR 0x%08x:", code->inst[n].inst2); - inst = code->inst[n].inst2; - fprintf(stderr,"Addr0: %d%c, Addr1: %d%c, Addr2: %d%c, srcp:%d\n", - inst & 0xff, (inst & (1<<8)) ? 'c' : 't', - (inst >> 10) & 0xff, (inst & (1<<18)) ? 'c' : 't', - (inst >> 20) & 0xff, (inst & (1<<28)) ? 'c' : 't', - (inst >> 30)); - fprintf(stderr,"\t3 RGB_INST: 0x%08x:", code->inst[n].inst3); - inst = code->inst[n].inst3; - fprintf(stderr,"rgb_A_src:%d %s/%s/%s %d rgb_B_src:%d %s/%s/%s %d\n", - (inst) & 0x3, toswiz((inst >> 2) & 0x7), toswiz((inst >> 5) & 0x7), toswiz((inst >> 8) & 0x7), - (inst >> 11) & 0x3, - (inst >> 13) & 0x3, toswiz((inst >> 15) & 0x7), toswiz((inst >> 18) & 0x7), toswiz((inst >> 21) & 0x7), - (inst >> 24) & 0x3); - - - fprintf(stderr,"\t4 ALPHA_INST:0x%08x:", code->inst[n].inst4); - inst = code->inst[n].inst4; - fprintf(stderr,"%s dest:%d%s alp_A_src:%d %s %d alp_B_src:%d %s %d w:%d\n", to_alpha_op(inst & 0xf), - (inst >> 4) & 0x7f, inst & (1<<11) ? "(rel)":"", - (inst >> 12) & 0x3, toswiz((inst >> 14) & 0x7), (inst >> 17) & 0x3, - (inst >> 19) & 0x3, toswiz((inst >> 21) & 0x7), (inst >> 24) & 0x3, - (inst >> 31) & 0x1); - - fprintf(stderr,"\t5 RGBA_INST: 0x%08x:", code->inst[n].inst5); - inst = code->inst[n].inst5; - fprintf(stderr,"%s dest:%d%s rgb_C_src:%d %s/%s/%s %d alp_C_src:%d %s %d\n", toop(inst & 0xf), - (inst >> 4) & 0x7f, inst & (1<<11) ? "(rel)":"", - (inst >> 12) & 0x3, toswiz((inst >> 14) & 0x7), toswiz((inst >> 17) & 0x7), toswiz((inst >> 20) & 0x7), - (inst >> 23) & 0x3, - (inst >> 25) & 0x3, toswiz((inst >> 27) & 0x7), (inst >> 30) & 0x3); - break; - case 2: - break; - case 3: - inst = code->inst[n].inst1; - fprintf(stderr,"\t1:TEX_INST: 0x%08x: id: %d op:%s, %s, %s %s\n", inst, (inst >> 16) & 0xf, - to_texop((inst >> 22) & 0x7), (inst & (1<<25)) ? "ACQ" : "", - (inst & (1<<26)) ? "IGNUNC" : "", (inst & (1<<27)) ? "UNSCALED" : "SCALED"); - inst = code->inst[n].inst2; - fprintf(stderr,"\t2:TEX_ADDR: 0x%08x: src: %d%s %s/%s/%s/%s dst: %d%s %s/%s/%s/%s\n", inst, - inst & 127, inst & (1<<7) ? "(rel)" : "", - toswiz((inst >> 8) & 0x3), toswiz((inst >> 10) & 0x3), - toswiz((inst >> 12) & 0x3), toswiz((inst >> 14) & 0x3), - (inst >> 16) & 127, inst & (1<<23) ? "(rel)" : "", - toswiz((inst >> 24) & 0x3), toswiz((inst >> 26) & 0x3), - toswiz((inst >> 28) & 0x3), toswiz((inst >> 30) & 0x3)); - - fprintf(stderr,"\t3:TEX_DXDY: 0x%08x\n", code->inst[n].inst3); - break; - } - fprintf(stderr,"\n"); - } - -} diff --git a/src/mesa/drivers/dri/r600/r700_fragprog_emit.c b/src/mesa/drivers/dri/r600/r700_fragprog_emit.c deleted file mode 100644 index 425015195d..0000000000 --- a/src/mesa/drivers/dri/r600/r700_fragprog_emit.c +++ /dev/null @@ -1,327 +0,0 @@ -/* - * Copyright (C) 2005 Ben Skeggs. - * - * Copyright 2008 Corbin Simpson - * Adaptation and modification for ATI/AMD Radeon R500 GPU chipsets. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -/** - * \file - * - * \author Ben Skeggs - * - * \author Jerome Glisse - * - * \author Corbin Simpson - * - * \todo Depth write, WPOS/FOGC inputs - * - * \todo FogOption - * - */ - -#include "r700_fragprog.h" - -#include "radeon_program_pair.h" - - -#define PROG_CODE \ - struct r500_fragment_program_compiler *c = (struct r500_fragment_program_compiler*)data; \ - struct r500_fragment_program_code *code = c->code - -#define error(fmt, args...) do { \ - fprintf(stderr, "%s::%s(): " fmt "\n", \ - __FILE__, __FUNCTION__, ##args); \ - } while(0) - - -/** - * Callback to register hardware constants. - */ -static GLboolean emit_const(void *data, GLuint file, GLuint idx, GLuint *hwindex) -{ - PROG_CODE; - - for (*hwindex = 0; *hwindex < code->const_nr; ++*hwindex) { - if (code->constant[*hwindex].File == file && - code->constant[*hwindex].Index == idx) - break; - } - - if (*hwindex >= code->const_nr) { - if (*hwindex >= PFS_NUM_CONST_REGS) { - error("Out of hw constants!\n"); - return GL_FALSE; - } - - code->const_nr++; - code->constant[*hwindex].File = file; - code->constant[*hwindex].Index = idx; - } - - return GL_TRUE; -} - -static GLuint translate_rgb_op(GLuint opcode) -{ - switch(opcode) { - case OPCODE_CMP: return R500_ALU_RGBA_OP_CMP; - case OPCODE_DDX: return R500_ALU_RGBA_OP_MDH; - case OPCODE_DDY: return R500_ALU_RGBA_OP_MDV; - case OPCODE_DP3: return R500_ALU_RGBA_OP_DP3; - case OPCODE_DP4: return R500_ALU_RGBA_OP_DP4; - case OPCODE_FRC: return R500_ALU_RGBA_OP_FRC; - default: - error("translate_rgb_op(%d): unknown opcode\n", opcode); - /* fall through */ - case OPCODE_NOP: - /* fall through */ - case OPCODE_MAD: return R500_ALU_RGBA_OP_MAD; - case OPCODE_MAX: return R500_ALU_RGBA_OP_MAX; - case OPCODE_MIN: return R500_ALU_RGBA_OP_MIN; - case OPCODE_REPL_ALPHA: return R500_ALU_RGBA_OP_SOP; - } -} - -static GLuint translate_alpha_op(GLuint opcode) -{ - switch(opcode) { - case OPCODE_CMP: return R500_ALPHA_OP_CMP; - case OPCODE_COS: return R500_ALPHA_OP_COS; - case OPCODE_DDX: return R500_ALPHA_OP_MDH; - case OPCODE_DDY: return R500_ALPHA_OP_MDV; - case OPCODE_DP3: return R500_ALPHA_OP_DP; - case OPCODE_DP4: return R500_ALPHA_OP_DP; - case OPCODE_EX2: return R500_ALPHA_OP_EX2; - case OPCODE_FRC: return R500_ALPHA_OP_FRC; - case OPCODE_LG2: return R500_ALPHA_OP_LN2; - default: - error("translate_alpha_op(%d): unknown opcode\n", opcode); - /* fall through */ - case OPCODE_NOP: - /* fall through */ - case OPCODE_MAD: return R500_ALPHA_OP_MAD; - case OPCODE_MAX: return R500_ALPHA_OP_MAX; - case OPCODE_MIN: return R500_ALPHA_OP_MIN; - case OPCODE_RCP: return R500_ALPHA_OP_RCP; - case OPCODE_RSQ: return R500_ALPHA_OP_RSQ; - case OPCODE_SIN: return R500_ALPHA_OP_SIN; - } -} - -static GLuint fix_hw_swizzle(GLuint swz) -{ - if (swz == 5) swz = 6; - if (swz == SWIZZLE_NIL) swz = 4; - return swz; -} - -static GLuint translate_arg_rgb(struct radeon_pair_instruction *inst, int arg) -{ - GLuint t = inst->RGB.Arg[arg].Source; - int comp; - t |= inst->RGB.Arg[arg].Negate << 11; - t |= inst->RGB.Arg[arg].Abs << 12; - - for(comp = 0; comp < 3; ++comp) - t |= fix_hw_swizzle(GET_SWZ(inst->RGB.Arg[arg].Swizzle, comp)) << (3*comp + 2); - - return t; -} - -static GLuint translate_arg_alpha(struct radeon_pair_instruction *inst, int i) -{ - GLuint t = inst->Alpha.Arg[i].Source; - t |= fix_hw_swizzle(inst->Alpha.Arg[i].Swizzle) << 2; - t |= inst->Alpha.Arg[i].Negate << 5; - t |= inst->Alpha.Arg[i].Abs << 6; - return t; -} - -static void use_temporary(struct r500_fragment_program_code* code, GLuint index) -{ - if (index > code->max_temp_idx) - code->max_temp_idx = index; -} - -static GLuint use_source(struct r500_fragment_program_code* code, struct radeon_pair_instruction_source src) -{ - if (!src.Constant) - use_temporary(code, src.Index); - return src.Index | src.Constant << 8; -} - - -/** - * Emit a paired ALU instruction. - */ -static GLboolean emit_paired(void *data, struct radeon_pair_instruction *inst) -{ - PROG_CODE; - - if (code->inst_end >= 511) { - error("emit_alu: Too many instructions"); - return GL_FALSE; - } - - int ip = ++code->inst_end; - - code->inst[ip].inst5 = translate_rgb_op(inst->RGB.Opcode); - code->inst[ip].inst4 = translate_alpha_op(inst->Alpha.Opcode); - - if (inst->RGB.OutputWriteMask || inst->Alpha.OutputWriteMask || inst->Alpha.DepthWriteMask) - code->inst[ip].inst0 = R500_INST_TYPE_OUT; - else - code->inst[ip].inst0 = R500_INST_TYPE_ALU; - code->inst[ip].inst0 |= R500_INST_TEX_SEM_WAIT; - - code->inst[ip].inst0 |= (inst->RGB.WriteMask << 11) | (inst->Alpha.WriteMask << 14); - code->inst[ip].inst0 |= (inst->RGB.OutputWriteMask << 15) | (inst->Alpha.OutputWriteMask << 18); - if (inst->Alpha.DepthWriteMask) { - code->inst[ip].inst4 |= R500_ALPHA_W_OMASK; - c->fp->writes_depth = GL_TRUE; - } - - code->inst[ip].inst4 |= R500_ALPHA_ADDRD(inst->Alpha.DestIndex); - code->inst[ip].inst5 |= R500_ALU_RGBA_ADDRD(inst->RGB.DestIndex); - use_temporary(code, inst->Alpha.DestIndex); - use_temporary(code, inst->RGB.DestIndex); - - if (inst->RGB.Saturate) - code->inst[ip].inst0 |= R500_INST_RGB_CLAMP; - if (inst->Alpha.Saturate) - code->inst[ip].inst0 |= R500_INST_ALPHA_CLAMP; - - code->inst[ip].inst1 |= R500_RGB_ADDR0(use_source(code, inst->RGB.Src[0])); - code->inst[ip].inst1 |= R500_RGB_ADDR1(use_source(code, inst->RGB.Src[1])); - code->inst[ip].inst1 |= R500_RGB_ADDR2(use_source(code, inst->RGB.Src[2])); - - code->inst[ip].inst2 |= R500_ALPHA_ADDR0(use_source(code, inst->Alpha.Src[0])); - code->inst[ip].inst2 |= R500_ALPHA_ADDR1(use_source(code, inst->Alpha.Src[1])); - code->inst[ip].inst2 |= R500_ALPHA_ADDR2(use_source(code, inst->Alpha.Src[2])); - - code->inst[ip].inst3 |= translate_arg_rgb(inst, 0) << R500_ALU_RGB_SEL_A_SHIFT; - code->inst[ip].inst3 |= translate_arg_rgb(inst, 1) << R500_ALU_RGB_SEL_B_SHIFT; - code->inst[ip].inst5 |= translate_arg_rgb(inst, 2) << R500_ALU_RGBA_SEL_C_SHIFT; - - code->inst[ip].inst4 |= translate_arg_alpha(inst, 0) << R500_ALPHA_SEL_A_SHIFT; - code->inst[ip].inst4 |= translate_arg_alpha(inst, 1) << R500_ALPHA_SEL_B_SHIFT; - code->inst[ip].inst5 |= translate_arg_alpha(inst, 2) << R500_ALU_RGBA_ALPHA_SEL_C_SHIFT; - - return GL_TRUE; -} - -static GLuint translate_strq_swizzle(struct prog_src_register src) -{ - GLuint swiz = 0; - int i; - for (i = 0; i < 4; i++) - swiz |= (GET_SWZ(src.Swizzle, i) & 0x3) << i*2; - return swiz; -} - -/** - * Emit a single TEX instruction - */ -static GLboolean emit_tex(void *data, struct prog_instruction *inst) -{ - PROG_CODE; - - if (code->inst_end >= 511) { - error("emit_tex: Too many instructions"); - return GL_FALSE; - } - - int ip = ++code->inst_end; - - code->inst[ip].inst0 = R500_INST_TYPE_TEX - | (inst->DstReg.WriteMask << 11) - | R500_INST_TEX_SEM_WAIT; - code->inst[ip].inst1 = R500_TEX_ID(inst->TexSrcUnit) - | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED; - - if (inst->TexSrcTarget == TEXTURE_RECT_INDEX) - code->inst[ip].inst1 |= R500_TEX_UNSCALED; - - switch (inst->Opcode) { - case OPCODE_KIL: - code->inst[ip].inst1 |= R500_TEX_INST_TEXKILL; - break; - case OPCODE_TEX: - code->inst[ip].inst1 |= R500_TEX_INST_LD; - break; - case OPCODE_TXB: - code->inst[ip].inst1 |= R500_TEX_INST_LODBIAS; - break; - case OPCODE_TXP: - code->inst[ip].inst1 |= R500_TEX_INST_PROJ; - break; - default: - error("emit_tex can't handle opcode %x\n", inst->Opcode); - } - - code->inst[ip].inst2 = R500_TEX_SRC_ADDR(inst->SrcReg[0].Index) - | (translate_strq_swizzle(inst->SrcReg[0]) << 8) - | R500_TEX_DST_ADDR(inst->DstReg.Index) - | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G - | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A; - - return GL_TRUE; -} - -static const struct radeon_pair_handler pair_handler = { - .EmitConst = emit_const, - .EmitPaired = emit_paired, - .EmitTex = emit_tex, - .MaxHwTemps = 128 -}; - -GLboolean r500FragmentProgramEmit(struct r500_fragment_program_compiler *compiler) -{ - struct r500_fragment_program_code *code = compiler->code; - - _mesa_bzero(code, sizeof(*code)); - code->max_temp_idx = 1; - code->inst_offset = 0; - code->inst_end = -1; - - if (!radeonPairProgram(compiler->r600->radeon.glCtx, compiler->program, &pair_handler, compiler)) - return GL_FALSE; - - if ((code->inst[code->inst_end].inst0 & R500_INST_TYPE_MASK) != R500_INST_TYPE_OUT) { - /* This may happen when dead-code elimination is disabled or - * when most of the fragment program logic is leading to a KIL */ - if (code->inst_end >= 511) { - error("Introducing fake OUT: Too many instructions"); - return GL_FALSE; - } - - int ip = ++code->inst_end; - code->inst[ip].inst0 = R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT; - } - - return GL_TRUE; -} -- cgit v1.2.3 From 27c07b6b28cb5d9f0b2ba446846670a234e48228 Mon Sep 17 00:00:00 2001 From: Richard Li Date: Tue, 21 Apr 2009 12:54:20 -0400 Subject: Initial pull of code from r6xx-r7xx-support branch Not functional yet. --- src/mesa/drivers/dri/r600/Makefile | 24 +- src/mesa/drivers/dri/r600/defaultendian.h | 38 + src/mesa/drivers/dri/r600/r600_cmdbuf.c | 475 --- src/mesa/drivers/dri/r600/r600_cmdbuf.h | 7 - src/mesa/drivers/dri/r600/r600_context.c | 163 +- src/mesa/drivers/dri/r600/r600_context.h | 610 +--- src/mesa/drivers/dri/r600/r600_emit.c | 293 +- src/mesa/drivers/dri/r600/r600_reg_auto_r6xx.h | 3087 ++++++++++++++++++ src/mesa/drivers/dri/r600/r600_reg_r6xx.h | 492 +++ src/mesa/drivers/dri/r600/r600_reg_r7xx.h | 149 + src/mesa/drivers/dri/r600/r600_swtcl.c | 106 +- src/mesa/drivers/dri/r600/r700_assembler.c | 4068 ++++++++++++++++++++++++ src/mesa/drivers/dri/r600/r700_assembler.h | 512 +++ src/mesa/drivers/dri/r600/r700_chip.c | 420 +++ src/mesa/drivers/dri/r600/r700_chip.h | 458 +++ src/mesa/drivers/dri/r600/r700_chipoffset.h | 684 ++++ src/mesa/drivers/dri/r600/r700_clear.c | 267 ++ src/mesa/drivers/dri/r600/r700_clear.h | 33 + src/mesa/drivers/dri/r600/r700_debug.c | 80 + src/mesa/drivers/dri/r600/r700_debug.h | 93 + src/mesa/drivers/dri/r600/r700_fragprog.c | 365 +++ src/mesa/drivers/dri/r600/r700_fragprog.h | 89 +- src/mesa/drivers/dri/r600/r700_ioctl.c | 48 + src/mesa/drivers/dri/r600/r700_ioctl.h | 35 + src/mesa/drivers/dri/r600/r700_oglprog.c | 138 + src/mesa/drivers/dri/r600/r700_oglprog.h | 34 + src/mesa/drivers/dri/r600/r700_render.c | 462 +++ src/mesa/drivers/dri/r600/r700_shader.c | 528 +++ src/mesa/drivers/dri/r600/r700_shader.h | 150 + src/mesa/drivers/dri/r600/r700_shaderinst.c | 224 ++ src/mesa/drivers/dri/r600/r700_shaderinst.h | 321 ++ src/mesa/drivers/dri/r600/r700_state.c | 925 ++++++ src/mesa/drivers/dri/r600/r700_state.h | 47 + src/mesa/drivers/dri/r600/r700_tex.c | 1555 +++++++++ src/mesa/drivers/dri/r600/r700_tex.h | 102 + src/mesa/drivers/dri/r600/r700_vertprog.c | 466 +++ src/mesa/drivers/dri/r600/r700_vertprog.h | 92 + src/mesa/drivers/dri/r600/sq_micro_reg.h | 2008 ++++++++++++ src/mesa/drivers/dri/radeon/radeon_screen.c | 10 +- 39 files changed, 18128 insertions(+), 1530 deletions(-) create mode 100644 src/mesa/drivers/dri/r600/defaultendian.h create mode 100644 src/mesa/drivers/dri/r600/r600_reg_auto_r6xx.h create mode 100644 src/mesa/drivers/dri/r600/r600_reg_r6xx.h create mode 100644 src/mesa/drivers/dri/r600/r600_reg_r7xx.h create mode 100644 src/mesa/drivers/dri/r600/r700_assembler.c create mode 100644 src/mesa/drivers/dri/r600/r700_assembler.h create mode 100644 src/mesa/drivers/dri/r600/r700_chip.c create mode 100644 src/mesa/drivers/dri/r600/r700_chip.h create mode 100644 src/mesa/drivers/dri/r600/r700_chipoffset.h create mode 100644 src/mesa/drivers/dri/r600/r700_clear.c create mode 100644 src/mesa/drivers/dri/r600/r700_clear.h create mode 100644 src/mesa/drivers/dri/r600/r700_debug.c create mode 100644 src/mesa/drivers/dri/r600/r700_debug.h create mode 100644 src/mesa/drivers/dri/r600/r700_fragprog.c create mode 100644 src/mesa/drivers/dri/r600/r700_ioctl.c create mode 100644 src/mesa/drivers/dri/r600/r700_ioctl.h create mode 100644 src/mesa/drivers/dri/r600/r700_oglprog.c create mode 100644 src/mesa/drivers/dri/r600/r700_oglprog.h create mode 100644 src/mesa/drivers/dri/r600/r700_render.c create mode 100644 src/mesa/drivers/dri/r600/r700_shader.c create mode 100644 src/mesa/drivers/dri/r600/r700_shader.h create mode 100644 src/mesa/drivers/dri/r600/r700_shaderinst.c create mode 100644 src/mesa/drivers/dri/r600/r700_shaderinst.h create mode 100644 src/mesa/drivers/dri/r600/r700_state.c create mode 100644 src/mesa/drivers/dri/r600/r700_state.h create mode 100644 src/mesa/drivers/dri/r600/r700_tex.c create mode 100644 src/mesa/drivers/dri/r600/r700_tex.h create mode 100644 src/mesa/drivers/dri/r600/r700_vertprog.c create mode 100644 src/mesa/drivers/dri/r600/r700_vertprog.h create mode 100644 src/mesa/drivers/dri/r600/sq_micro_reg.h (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/Makefile b/src/mesa/drivers/dri/r600/Makefile index 528396df27..00c56c03cd 100644 --- a/src/mesa/drivers/dri/r600/Makefile +++ b/src/mesa/drivers/dri/r600/Makefile @@ -37,23 +37,23 @@ RADEON_COMMON_SOURCES = \ DRIVER_SOURCES = \ radeon_screen.c \ r600_context.c \ - r600_ioctl.c \ r600_cmdbuf.c \ - r600_state.c \ - r600_render.c \ - r600_tex.c \ - r600_texstate.c \ radeon_program.c \ radeon_program_alu.c \ radeon_program_pair.c \ radeon_nqssadce.c \ - r600_vertprog.c \ - r600_fragprog.c \ - r600_fragprog_swizzle.c \ - r600_fragprog_emit.c \ - r600_shader.c \ - r600_emit.c \ - r600_swtcl.c \ + r600_emit.c \ + r600_swtcl.c \ + r700_assembler.c \ + r700_fragprog.c \ + r700_vertprog.c \ + r700_shader.c \ + r700_ioctl.c \ + r700_oglprog.c \ + r700_chip.c \ + r700_render.c \ + r700_tex.c \ + r700_debug.c \ $(RADEON_COMMON_SOURCES) \ $(EGL_SOURCES) diff --git a/src/mesa/drivers/dri/r600/defaultendian.h b/src/mesa/drivers/dri/r600/defaultendian.h new file mode 100644 index 0000000000..32caf32cd2 --- /dev/null +++ b/src/mesa/drivers/dri/r600/defaultendian.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + */ + + +#ifndef _DEFINEENDIAN_H_ +#define _DEFINEENDIAN_H_ + +//We have to choose a reg bits orientation if there is no compile flag for it. +#if defined(LITTLEENDIAN_CPU) +#elif defined(BIGENDIAN_CPU) +#else +#define LITTLEENDIAN_CPU +#endif + +#endif //_DEFINEENDIAN_H_ diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index e379984417..bc14f9a755 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -45,493 +45,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_drm.h" #include "r600_context.h" -#include "r600_ioctl.h" #include "radeon_reg.h" -#include "r600_reg.h" #include "r600_cmdbuf.h" #include "r600_emit.h" #include "radeon_bocs_wrapper.h" #include "radeon_mipmap_tree.h" -#include "r600_state.h" #include "radeon_reg.h" -#define R600_VAP_PVS_UPLOAD_ADDRESS 0x2200 -# define RADEON_ONE_REG_WR (1 << 15) - -/** # of dwords reserved for additional instructions that may need to be written - * during flushing. - */ -#define SPACE_FOR_FLUSHING 4 - -static unsigned packet0_count(r600ContextPtr r600, uint32_t *pkt) -{ - if (r600->radeon.radeonScreen->kernel_mm) { - return ((((*pkt) >> 16) & 0x3FFF) + 1); - } else { - drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt; - return t->packet0.count; - } - return 0; -} - -#define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count) - -void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom) -{ - r600ContextPtr r600 = R600_CONTEXT(ctx); - BATCH_LOCALS(&r600->radeon); - drm_r300_cmd_header_t cmd; - uint32_t addr, ndw, i; - - if (!r600->radeon.radeonScreen->kernel_mm) { - uint32_t dwords; - dwords = (*atom->check) (ctx, atom); - BEGIN_BATCH_NO_AUTOSTATE(dwords); - OUT_BATCH_TABLE(atom->cmd, dwords); - END_BATCH(); - return; - } - - cmd.u = atom->cmd[0]; - addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo; - ndw = cmd.vpu.count * 4; - if (ndw) { - - if (r600->vap_flush_needed) { - BEGIN_BATCH_NO_AUTOSTATE(15 + ndw); - - /* flush processing vertices */ - OUT_BATCH_REGVAL(R600_SC_SCREENDOOR, 0); - OUT_BATCH_REGVAL(R600_RB3D_DSTCACHE_CTLSTAT, R600_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); - OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); - OUT_BATCH_REGVAL(R600_SC_SCREENDOOR, 0xffffff); - OUT_BATCH_REGVAL(R600_VAP_PVS_STATE_FLUSH_REG, 0); - r600->vap_flush_needed = GL_FALSE; - } else { - BEGIN_BATCH_NO_AUTOSTATE(5 + ndw); - } - OUT_BATCH_REGVAL(R600_VAP_PVS_UPLOAD_ADDRESS, addr); - OUT_BATCH(CP_PACKET0(R600_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR); - for (i = 0; i < ndw; i++) { - OUT_BATCH(atom->cmd[i+1]); - } - OUT_BATCH_REGVAL(R600_VAP_PVS_STATE_FLUSH_REG, 0); - END_BATCH(); - } -} - -static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) -{ - r600ContextPtr r600 = R600_CONTEXT(ctx); - BATCH_LOCALS(&r600->radeon); - int numtmus = packet0_count(r600, r600->hw.tex.offset.cmd); - int notexture = 0; - - if (numtmus) { - int i; - - for(i = 0; i < numtmus; ++i) { - radeonTexObj *t = r600->hw.textures[i]; - - if (!t) - notexture = 1; - } - - if (r600->radeon.radeonScreen->kernel_mm && notexture) { - return; - } - BEGIN_BATCH_NO_AUTOSTATE(4 * numtmus); - for(i = 0; i < numtmus; ++i) { - radeonTexObj *t = r600->hw.textures[i]; - OUT_BATCH_REGSEQ(R600_TX_OFFSET_0 + (i * 4), 1); - if (t && !t->image_override) { - OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - } else if (!t) { - OUT_BATCH(r600->radeon.radeonScreen->texOffset[0]); - } else { /* override cases */ - if (t->bo) { - OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - } else if (!r600->radeon.radeonScreen->kernel_mm) { - OUT_BATCH(t->override_offset); - } - else - OUT_BATCH(r600->radeon.radeonScreen->texOffset[0]); - } - } - END_BATCH(); - } -} - -static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) -{ - r600ContextPtr r600 = R600_CONTEXT(ctx); - BATCH_LOCALS(&r600->radeon); - struct radeon_renderbuffer *rrb; - uint32_t cbpitch; - uint32_t offset = r600->radeon.state.color.draw_offset; - - rrb = radeon_get_colorbuffer(&r600->radeon); - if (!rrb || !rrb->bo) { - fprintf(stderr, "no rrb\n"); - return; - } - - cbpitch = (rrb->pitch / rrb->cpp); - if (rrb->cpp == 4) - cbpitch |= R600_COLOR_FORMAT_ARGB8888; - else - cbpitch |= R600_COLOR_FORMAT_RGB565; - - if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) - cbpitch |= R600_COLOR_TILE_ENABLE; - - BEGIN_BATCH_NO_AUTOSTATE(8); - OUT_BATCH_REGSEQ(R600_RB3D_COLOROFFSET0, 1); - OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0); - OUT_BATCH_REGSEQ(R600_RB3D_COLORPITCH0, 1); - OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0); - END_BATCH(); - if (r600->radeon.radeonScreen->driScreen->dri2.enabled) { - if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) { - BEGIN_BATCH_NO_AUTOSTATE(3); - OUT_BATCH_REGSEQ(R600_SC_SCISSORS_TL, 2); - OUT_BATCH(0); - OUT_BATCH((rrb->width << R600_SCISSORS_X_SHIFT) | - (rrb->height << R600_SCISSORS_Y_SHIFT)); - END_BATCH(); - } else { - BEGIN_BATCH_NO_AUTOSTATE(3); - OUT_BATCH_REGSEQ(R600_SC_SCISSORS_TL, 2); - OUT_BATCH((R600_SCISSORS_OFFSET << R600_SCISSORS_X_SHIFT) | - (R600_SCISSORS_OFFSET << R600_SCISSORS_Y_SHIFT)); - OUT_BATCH(((rrb->width + R600_SCISSORS_OFFSET) << R600_SCISSORS_X_SHIFT) | - ((rrb->height + R600_SCISSORS_OFFSET) << R600_SCISSORS_Y_SHIFT)); - END_BATCH(); - } - } -} - -static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom) -{ - r600ContextPtr r600 = R600_CONTEXT(ctx); - BATCH_LOCALS(&r600->radeon); - struct radeon_renderbuffer *rrb; - uint32_t zbpitch; - - rrb = radeon_get_depthbuffer(&r600->radeon); - if (!rrb) - return; - - zbpitch = (rrb->pitch / rrb->cpp); - if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) { - zbpitch |= R600_DEPTHMACROTILE_ENABLE; - } - if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){ - zbpitch |= R600_DEPTHMICROTILE_TILED; - } - - BEGIN_BATCH_NO_AUTOSTATE(6); - OUT_BATCH_REGSEQ(R600_ZB_DEPTHOFFSET, 1); - OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); - OUT_BATCH_REGVAL(R600_ZB_DEPTHPITCH, zbpitch); - END_BATCH(); -} - -static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom) -{ - r600ContextPtr r600 = R600_CONTEXT(ctx); - BATCH_LOCALS(&r600->radeon); - struct radeon_renderbuffer *rrb; - uint32_t format = 0; - - rrb = radeon_get_depthbuffer(&r600->radeon); - if (!rrb) - format = 0; - else { - if (rrb->cpp == 2) - format = R600_DEPTHFORMAT_16BIT_INT_Z; - else if (rrb->cpp == 4) - format = R600_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL; - } - - OUT_BATCH(atom->cmd[0]); - atom->cmd[1] &= ~0xf; - atom->cmd[1] |= format; - OUT_BATCH(atom->cmd[1]); - OUT_BATCH(atom->cmd[2]); - OUT_BATCH(atom->cmd[3]); - OUT_BATCH(atom->cmd[4]); -} - -static int check_always(GLcontext *ctx, struct radeon_state_atom *atom) -{ - return atom->cmd_size; -} - -static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom) -{ - r600ContextPtr r600 = R600_CONTEXT(ctx); - int cnt; - if (atom->cmd[0] == CP_PACKET2) { - return 0; - } - cnt = packet0_count(r600, atom->cmd); - return cnt ? cnt + 1 : 0; -} - -int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom) -{ - int cnt; - - cnt = vpu_count(atom->cmd); - return cnt ? (cnt * 4) + 1 : 0; -} - -#define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \ - do { \ - r600->hw.ATOM.cmd_size = (SZ); \ - r600->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \ - r600->hw.ATOM.name = #ATOM; \ - r600->hw.ATOM.idx = (IDX); \ - r600->hw.ATOM.check = check_##CHK; \ - r600->hw.ATOM.dirty = GL_FALSE; \ - r600->radeon.hw.max_state_size += (SZ); \ - insert_at_tail(&r600->radeon.hw.atomlist, &r600->hw.ATOM); \ - } while (0) /** * Allocate memory for the command buffer and initialize the state atom * list. Note that the initial hardware state is set by r600InitState(). */ void r600InitCmdBuf(r600ContextPtr r600) { - int mtu; - int i; - - r600->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */ - - mtu = r600->radeon.glCtx->Const.MaxTextureUnits; - if (RADEON_DEBUG & DEBUG_TEXTURE) { - fprintf(stderr, "Using %d maximum texture units..\n", mtu); - } - - /* Setup the atom linked list */ - make_empty_list(&r600->radeon.hw.atomlist); - r600->radeon.hw.atomlist.name = "atom-list"; - - /* Initialize state atoms */ - ALLOC_STATE(vpt, always, R600_VPT_CMDSIZE, 0); - r600->hw.vpt.cmd[R600_VPT_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_SE_VPORT_XSCALE, 6); - ALLOC_STATE(vap_cntl, always, R600_VAP_CNTL_SIZE, 0); - r600->hw.vap_cntl.cmd[R600_VAP_CNTL_FLUSH] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PVS_STATE_FLUSH_REG, 1); - r600->hw.vap_cntl.cmd[R600_VAP_CNTL_FLUSH_1] = 0; - r600->hw.vap_cntl.cmd[R600_VAP_CNTL_CMD] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_CNTL, 1); - - ALLOC_STATE(vte, always, 3, 0); - r600->hw.vte.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SE_VTE_CNTL, 2); - ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0); - r600->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_VF_MAX_VTX_INDX, 2); - ALLOC_STATE(vap_cntl_status, always, 2, 0); - r600->hw.vap_cntl_status.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_CNTL_STATUS, 1); - ALLOC_STATE(vir[0], variable, R600_VIR_CMDSIZE, 0); - r600->hw.vir[0].cmd[R600_VIR_CMD_0] = - cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PROG_STREAM_CNTL_0, 1); - ALLOC_STATE(vir[1], variable, R600_VIR_CMDSIZE, 1); - r600->hw.vir[1].cmd[R600_VIR_CMD_0] = - cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PROG_STREAM_CNTL_EXT_0, 1); - ALLOC_STATE(vic, always, R600_VIC_CMDSIZE, 0); - r600->hw.vic.cmd[R600_VIC_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_VTX_STATE_CNTL, 2); - ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0); - r600->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE); - - ALLOC_STATE(vap_clip_cntl, always, 2, 0); - r600->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_CLIP_CNTL, 1); - ALLOC_STATE(vap_clip, always, 5, 0); - r600->hw.vap_clip.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_GB_VERT_CLIP_ADJ, 4); - ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0); - r600->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1); - - ALLOC_STATE(vof, always, R600_VOF_CMDSIZE, 0); - r600->hw.vof.cmd[R600_VOF_CMD_0] = - cmdpacket0(r600->radeon.radeonScreen, R600_VAP_OUTPUT_VTX_FMT_0, 2); - - ALLOC_STATE(pvs, always, R600_PVS_CMDSIZE, 0); - r600->hw.pvs.cmd[R600_PVS_CMD_0] = - cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PVS_CODE_CNTL_0, 3); - - ALLOC_STATE(gb_enable, always, 2, 0); - r600->hw.gb_enable.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GB_ENABLE, 1); - ALLOC_STATE(gb_misc, always, R600_GB_MISC_CMDSIZE, 0); - r600->hw.gb_misc.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GB_MSPOS0, 5); - ALLOC_STATE(txe, always, R600_TXE_CMDSIZE, 0); - r600->hw.txe.cmd[R600_TXE_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_TX_ENABLE, 1); - ALLOC_STATE(ga_point_s0, always, 5, 0); - r600->hw.ga_point_s0.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_POINT_S0, 4); - ALLOC_STATE(ga_triangle_stipple, always, 2, 0); - r600->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_TRIANGLE_STIPPLE, 1); - ALLOC_STATE(ps, always, R600_PS_CMDSIZE, 0); - r600->hw.ps.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_POINT_SIZE, 1); - ALLOC_STATE(ga_point_minmax, always, 4, 0); - r600->hw.ga_point_minmax.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_POINT_MINMAX, 3); - ALLOC_STATE(lcntl, always, 2, 0); - r600->hw.lcntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_LINE_CNTL, 1); - ALLOC_STATE(ga_line_stipple, always, 4, 0); - r600->hw.ga_line_stipple.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_LINE_STIPPLE_VALUE, 3); - ALLOC_STATE(shade, always, 5, 0); - r600->hw.shade.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_ENHANCE, 4); - ALLOC_STATE(polygon_mode, always, 4, 0); - r600->hw.polygon_mode.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_POLY_MODE, 3); - ALLOC_STATE(fogp, always, 3, 0); - r600->hw.fogp.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_FOG_SCALE, 2); - ALLOC_STATE(zbias_cntl, always, 2, 0); - r600->hw.zbias_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_TEX_WRAP, 1); - ALLOC_STATE(zbs, always, R600_ZBS_CMDSIZE, 0); - r600->hw.zbs.cmd[R600_ZBS_CMD_0] = - cmdpacket0(r600->radeon.radeonScreen, R600_SU_POLY_OFFSET_FRONT_SCALE, 4); - ALLOC_STATE(occlusion_cntl, always, 2, 0); - r600->hw.occlusion_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_POLY_OFFSET_ENABLE, 1); - ALLOC_STATE(cul, always, R600_CUL_CMDSIZE, 0); - r600->hw.cul.cmd[R600_CUL_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_CULL_MODE, 1); - ALLOC_STATE(su_depth_scale, always, 3, 0); - r600->hw.su_depth_scale.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_DEPTH_SCALE, 2); - ALLOC_STATE(rc, always, R600_RC_CMDSIZE, 0); - r600->hw.rc.cmd[R600_RC_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_COUNT, 2); - - ALLOC_STATE(ri, always, R600_RI_CMDSIZE, 0); - r600->hw.ri.cmd[R600_RI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_IP_0, 8); - ALLOC_STATE(rr, variable, R600_RR_CMDSIZE, 0); - r600->hw.rr.cmd[R600_RR_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_INST_0, 1); - - ALLOC_STATE(sc_hyperz, always, 3, 0); - r600->hw.sc_hyperz.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SC_HYPERZ, 2); - ALLOC_STATE(sc_screendoor, always, 2, 0); - r600->hw.sc_screendoor.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SC_SCREENDOOR, 1); - ALLOC_STATE(us_out_fmt, always, 6, 0); - r600->hw.us_out_fmt.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_OUT_FMT, 5); - - ALLOC_STATE(fp, always, R600_FP_CMDSIZE, 0); - r600->hw.fp.cmd[R600_FP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_CONFIG, 3); - r600->hw.fp.cmd[R600_FP_CMD_1] = cmdpacket0(r600->radeon.radeonScreen, R600_US_CODE_ADDR_0, 4); - - ALLOC_STATE(fpt, variable, R600_FPT_CMDSIZE, 0); - r600->hw.fpt.cmd[R600_FPT_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_TEX_INST_0, 0); - - ALLOC_STATE(fpi[0], variable, R600_FPI_CMDSIZE, 0); - r600->hw.fpi[0].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_RGB_INST_0, 1); - ALLOC_STATE(fpi[1], variable, R600_FPI_CMDSIZE, 1); - r600->hw.fpi[1].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_RGB_ADDR_0, 1); - ALLOC_STATE(fpi[2], variable, R600_FPI_CMDSIZE, 2); - r600->hw.fpi[2].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_ALPHA_INST_0, 1); - ALLOC_STATE(fpi[3], variable, R600_FPI_CMDSIZE, 3); - r600->hw.fpi[3].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_ALPHA_ADDR_0, 1); - ALLOC_STATE(fpp, variable, R600_FPP_CMDSIZE, 0); - r600->hw.fpp.cmd[R600_FPP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_PFS_PARAM_0_X, 0); - - ALLOC_STATE(fogs, always, R600_FOGS_CMDSIZE, 0); - r600->hw.fogs.cmd[R600_FOGS_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_FOG_BLEND, 1); - ALLOC_STATE(fogc, always, R600_FOGC_CMDSIZE, 0); - r600->hw.fogc.cmd[R600_FOGC_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_FOG_COLOR_R, 3); - ALLOC_STATE(at, always, R600_AT_CMDSIZE, 0); - r600->hw.at.cmd[R600_AT_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_ALPHA_FUNC, 2); - ALLOC_STATE(fg_depth_src, always, 2, 0); - r600->hw.fg_depth_src.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_DEPTH_SRC, 1); - ALLOC_STATE(rb3d_cctl, always, 2, 0); - r600->hw.rb3d_cctl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_CCTL, 1); - ALLOC_STATE(bld, always, R600_BLD_CMDSIZE, 0); - r600->hw.bld.cmd[R600_BLD_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_CBLEND, 2); - ALLOC_STATE(cmk, always, R600_CMK_CMDSIZE, 0); - r600->hw.cmk.cmd[R600_CMK_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1); - - ALLOC_STATE(blend_color, always, 2, 0); - r600->hw.blend_color.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_BLEND_COLOR, 1); - - ALLOC_STATE(rop, always, 2, 0); - r600->hw.rop.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_ROPCNTL, 1); - ALLOC_STATE(cb, always, R600_CB_CMDSIZE, 0); - r600->hw.cb.emit = &emit_cb_offset; - ALLOC_STATE(rb3d_dither_ctl, always, 10, 0); - r600->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_DITHER_CTL, 9); - ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0); - r600->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_AARESOLVE_CTL, 1); - - ALLOC_STATE(zs, always, R600_ZS_CMDSIZE, 0); - r600->hw.zs.cmd[R600_ZS_CMD_0] = - cmdpacket0(r600->radeon.radeonScreen, R600_ZB_CNTL, 3); - - ALLOC_STATE(zstencil_format, always, 5, 0); - r600->hw.zstencil_format.cmd[0] = - cmdpacket0(r600->radeon.radeonScreen, R600_ZB_FORMAT, 4); - r600->hw.zstencil_format.emit = emit_zstencil_format; - - ALLOC_STATE(zb, always, R600_ZB_CMDSIZE, 0); - r600->hw.zb.emit = emit_zb_offset; - ALLOC_STATE(zb_depthclearvalue, always, 2, 0); - r600->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_ZB_DEPTHCLEARVALUE, 1); - ALLOC_STATE(unk4F30, always, 3, 0); - r600->hw.unk4F30.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, 0x4F30, 2); - ALLOC_STATE(zb_hiz_offset, always, 2, 0); - r600->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_ZB_HIZ_OFFSET, 1); - ALLOC_STATE(zb_hiz_pitch, always, 2, 0); - r600->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_ZB_HIZ_PITCH, 1); - - ALLOC_STATE(vpi, vpu, R600_VPI_CMDSIZE, 0); - r600->hw.vpi.cmd[0] = - cmdvpu(r600->radeon.radeonScreen, R600_PVS_CODE_START, 0); - r600->hw.vpi.emit = emit_vpu; - - ALLOC_STATE(vpp, vpu, R600_VPP_CMDSIZE, 0); - r600->hw.vpp.cmd[0] = - cmdvpu(r600->radeon.radeonScreen, R600_PVS_CONST_START, 0); - r600->hw.vpp.emit = emit_vpu; - - ALLOC_STATE(vps, vpu, R600_VPS_CMDSIZE, 0); - r600->hw.vps.cmd[0] = - cmdvpu(r600->radeon.radeonScreen, R600_POINT_VPORT_SCALE_OFFSET, 1); - r600->hw.vps.emit = emit_vpu; - - for (i = 0; i < 6; i++) { - ALLOC_STATE(vpucp[i], vpu, R600_VPUCP_CMDSIZE, 0); - r600->hw.vpucp[i].cmd[0] = - cmdvpu(r600->radeon.radeonScreen, - R600_PVS_UCP_START + i, 1); - r600->hw.vpucp[i].emit = emit_vpu; - } - - /* Textures */ - ALLOC_STATE(tex.filter, variable, mtu + 1, 0); - r600->hw.tex.filter.cmd[R600_TEX_CMD_0] = - cmdpacket0(r600->radeon.radeonScreen, R600_TX_FILTER0_0, 0); - - ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0); - r600->hw.tex.filter_1.cmd[R600_TEX_CMD_0] = - cmdpacket0(r600->radeon.radeonScreen, R600_TX_FILTER1_0, 0); - - ALLOC_STATE(tex.size, variable, mtu + 1, 0); - r600->hw.tex.size.cmd[R600_TEX_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_TX_SIZE_0, 0); - - ALLOC_STATE(tex.format, variable, mtu + 1, 0); - r600->hw.tex.format.cmd[R600_TEX_CMD_0] = - cmdpacket0(r600->radeon.radeonScreen, R600_TX_FORMAT_0, 0); - - ALLOC_STATE(tex.pitch, variable, mtu + 1, 0); - r600->hw.tex.pitch.cmd[R600_TEX_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_TX_FORMAT2_0, 0); - - ALLOC_STATE(tex.offset, variable, 1, 0); - r600->hw.tex.offset.cmd[R600_TEX_CMD_0] = - cmdpacket0(r600->radeon.radeonScreen, R600_TX_OFFSET_0, 0); - r600->hw.tex.offset.emit = &emit_tex_offsets; - - ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0); - r600->hw.tex.chroma_key.cmd[R600_TEX_CMD_0] = - cmdpacket0(r600->radeon.radeonScreen, R600_TX_CHROMA_KEY_0, 0); - - ALLOC_STATE(tex.border_color, variable, mtu + 1, 0); - r600->hw.tex.border_color.cmd[R600_TEX_CMD_0] = - cmdpacket0(r600->radeon.radeonScreen, R600_TX_BORDER_COLOR_0, 0); - - r600->radeon.hw.is_dirty = GL_TRUE; - r600->radeon.hw.all_dirty = GL_TRUE; - rcommonInitCmdBuf(&r600->radeon); } diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.h b/src/mesa/drivers/dri/r600/r600_cmdbuf.h index 6a921a23f6..1bab9c5821 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.h +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.h @@ -40,11 +40,4 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. extern void r600InitCmdBuf(r600ContextPtr r600); -void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom); -int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom); - -void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom); -int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom); -int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom); - #endif /* __R600_CMDBUF_H__ */ diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 6754acba4d..1b43f68ac2 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -60,13 +60,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_context.h" #include "radeon_span.h" #include "r600_cmdbuf.h" -#include "r600_state.h" -#include "r600_ioctl.h" -#include "r600_tex.h" #include "r600_emit.h" #include "r600_swtcl.h" #include "radeon_bocs_wrapper.h" +#include "r700_chip.h" +#include "r700_state.h" +#include "r700_ioctl.h" + #include "vblank.h" #include "utils.h" @@ -216,44 +217,12 @@ static void r600_get_lock(radeonContextPtr rmesa) static void r600_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) { /* please flush pipe do all pending work */ - radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, - R600_SC_SCREENDOOR, 1)); - radeon_cs_write_dword(cs, 0x0); - radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, - R600_SC_SCREENDOOR, 1)); - radeon_cs_write_dword(cs, 0x00FFFFFF); - radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, - R600_SC_HYPERZ, 1)); - radeon_cs_write_dword(cs, 0x0); - radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, - R600_US_CONFIG, 1)); - radeon_cs_write_dword(cs, 0x0); - radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, - R600_ZB_CNTL, 1)); - radeon_cs_write_dword(cs, 0x0); - radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D)); - radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, - R600_RB3D_DSTCACHE_CTLSTAT, 1)); - radeon_cs_write_dword(cs, R600_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); - radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen, - R600_ZB_ZCACHE_CTLSTAT, 1)); - radeon_cs_write_dword(cs, R600_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE); - radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, - R300_WAIT_3D | R300_WAIT_3D_CLEAN)); + /* to be enabled */ } static void r600_vtbl_pre_emit_atoms(radeonContextPtr radeon) { - r600ContextPtr r600 = (r600ContextPtr)radeon; - BATCH_LOCALS(radeon); - - r600->vap_flush_needed = GL_TRUE; - - cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN); - BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH_REGVAL(R600_TX_INVALTAGS, R600_TX_FLUSH); - END_BATCH(); - end_3d(radeon); + /* to be enabled */ } static void r600_fallback(GLcontext *ctx, GLuint bit, GLboolean mode) @@ -268,13 +237,68 @@ static void r600_fallback(GLcontext *ctx, GLuint bit, GLboolean mode) static void r600_init_vtbl(radeonContextPtr radeon) { radeon->vtbl.get_lock = r600_get_lock; - radeon->vtbl.update_viewport_offset = r600UpdateViewportOffset; + radeon->vtbl.update_viewport_offset = r700UpdateViewportOffset; radeon->vtbl.emit_cs_header = r600_vtbl_emit_cs_header; radeon->vtbl.swtcl_flush = r600_swtcl_flush; radeon->vtbl.pre_emit_atoms = r600_vtbl_pre_emit_atoms; radeon->vtbl.fallback = r600_fallback; } +/* to be enabled */ +static void r600EmitShader(GLcontext * ctx, + struct r600_dma_region *rvb, + GLvoid * data, + int sizeinDWORD) +{ +} +/* to be enabled */ +static void r600FreeDmaRegion(context_t *context, + struct r600_dma_region *region) +{ +} +/* to be enabled */ +static void r600EmitVec(GLcontext * ctx, + struct r600_dma_region *rvb, + GLvoid * data, + int size, + int stride, + int count) +{ +} +/* to be enabled */ +static void r600ReleaseArrays(GLcontext * ctx) +{ +} +/* to be enabled */ +static GLboolean r600LoadMemSurf(context_t *context, + GLuint dst_offset, /* gpu addr */ + GLuint dst_pitch_in_pixel, + GLuint src_width_in_pixel, + GLuint height, + GLuint byte_per_pixel, + unsigned char* pSrc) /* source data */ +{ + return GL_TRUE; +} +/* to be enabled */ +static GLboolean r600AllocMemSurf(context_t *context, + void **ppmemBlock, + void **ppheap, + GLuint *prefered_heap, /* Now used RADEON_LOCAL_TEX_HEAP, return actual heap used. */ + GLuint totalSize) +{ +} +/* to be enabled */ +static int r600FlushCmdBuffer(context_t *context) +{ + int ret = 0; + + return ret; +} +/* to be enabled */ +static void r600MemUse(context_t *context, int id) +{ +} /* Create the device specific rendering context. */ @@ -315,10 +339,18 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, * (the texture functions are especially important) */ _mesa_init_driver_functions(&functions); - r600InitIoctlFuncs(&functions); - r600InitStateFuncs(&functions); - r600InitTextureFuncs(&functions); - r600InitShaderFuncs(&functions); + + r700InitChipObject(r600); /* let the eag... */ + + (r600->chipobj.InitFuncs)(&functions); + r600->chipobj.EmitShader = r600EmitShader; + r600->chipobj.FreeDmaRegion = r600FreeDmaRegion; + r600->chipobj.EmitVec = r600EmitVec; + r600->chipobj.ReleaseArrays = r600ReleaseArrays; + r600->chipobj.LoadMemSurf = r600LoadMemSurf; + r600->chipobj.AllocMemSurf = r600AllocMemSurf; + r600->chipobj.FlushCmdBuffer = r600FlushCmdBuffer; + r600->chipobj.MemUse = r600MemUse; if (!radeonInitContext(&r600->radeon, &functions, glVisual, driContextPriv, @@ -345,18 +377,20 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, ctx->Const.MaxTextureMaxAnisotropy = 16.0; ctx->Const.MaxTextureLodBias = 16.0; - ctx->Const.MaxTextureLevels = 13; - ctx->Const.MaxTextureRectSize = 4096; + if (screen->chip_family >= CHIP_FAMILY_RV515) { + ctx->Const.MaxTextureLevels = 13; + ctx->Const.MaxTextureRectSize = 4096; + } - ctx->Const.MinPointSize = 1.0; - ctx->Const.MinPointSizeAA = 1.0; - ctx->Const.MaxPointSize = R600_POINTSIZE_MAX; - ctx->Const.MaxPointSizeAA = R600_POINTSIZE_MAX; + ctx->Const.MinPointSize = 0x0001 / 8.0; + ctx->Const.MinPointSizeAA = 0x0001 / 8.0; + ctx->Const.MaxPointSize = 0xffff / 8.0; + ctx->Const.MaxPointSizeAA = 0xffff / 8.0; - ctx->Const.MinLineWidth = 1.0; - ctx->Const.MinLineWidthAA = 1.0; - ctx->Const.MaxLineWidth = R600_LINESIZE_MAX; - ctx->Const.MaxLineWidthAA = R600_LINESIZE_MAX; + ctx->Const.MinLineWidth = 0x0001 / 8.0; + ctx->Const.MinLineWidthAA = 0x0001 / 8.0; + ctx->Const.MaxLineWidth = 0xffff / 8.0; + ctx->Const.MaxLineWidthAA = 0xffff / 8.0; /* Needs further modifications */ #if 0 @@ -378,7 +412,7 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, /* Install the customized pipeline: */ _tnl_destroy_pipeline(ctx); - _tnl_install_pipeline(ctx, r600_pipeline); + _tnl_install_pipeline(ctx, (const struct tnl_pipeline_stage **)(r600->chipobj.stages)); /* Try and keep materials and vertices separate: */ @@ -392,15 +426,17 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, _tnl_allow_vertex_fog(ctx, GL_TRUE); /* currently bogus data */ - ctx->Const.VertexProgram.MaxInstructions = VSF_MAX_FRAGMENT_LENGTH / 4; - ctx->Const.VertexProgram.MaxNativeInstructions = - VSF_MAX_FRAGMENT_LENGTH / 4; - ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */ - ctx->Const.VertexProgram.MaxTemps = 32; - ctx->Const.VertexProgram.MaxNativeTemps = - /*VSF_MAX_FRAGMENT_TEMPS */ 32; - ctx->Const.VertexProgram.MaxNativeParameters = 256; /* r420 */ - ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; + if (screen->chip_flags & RADEON_CHIPSET_TCL) { + ctx->Const.VertexProgram.MaxInstructions = VSF_MAX_FRAGMENT_LENGTH / 4; + ctx->Const.VertexProgram.MaxNativeInstructions = + VSF_MAX_FRAGMENT_LENGTH / 4; + ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */ + ctx->Const.VertexProgram.MaxTemps = 32; + ctx->Const.VertexProgram.MaxNativeTemps = + /*VSF_MAX_FRAGMENT_TEMPS */ 32; + ctx->Const.VertexProgram.MaxNativeParameters = 256; /* r420 */ + ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; + } ctx->Const.FragmentProgram.MaxNativeTemps = PFS_NUM_TEMP_REGS; ctx->Const.FragmentProgram.MaxNativeAttribs = 11; /* copy i915... */ @@ -438,10 +474,13 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, "disable_lowimpact_fallback"); radeon_fbo_init(&r600->radeon); radeonInitSpanFuncs( ctx ); + r600InitCmdBuf(r600); +#if 0 /* to be enabled */ r600InitState(r600); if (!(screen->chip_flags & RADEON_CHIPSET_TCL)) r600InitSwtcl(ctx); +#endif TNL_CONTEXT(ctx)->Driver.RunPipeline = r600RunPipeline; diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index 0decf5d6a9..74e34e3684 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -52,6 +52,7 @@ struct r600_context; typedef struct r600_context r600ContextRec; typedef struct r600_context *r600ContextPtr; +typedef struct r600_context context_t; #include "main/mm.h" @@ -71,11 +72,6 @@ typedef struct r600_context *r600ContextPtr; } \ } -#include "r600_vertprog.h" -#include "r700_fragprog.h" - - - /************ DMA BUFFERS **************/ /* The blit width for texture uploads @@ -87,316 +83,6 @@ struct r600_texture_state { int tc_count; /* number of incoming texture coordinates from VAP */ }; - -#define R600_VPT_CMD_0 0 -#define R600_VPT_XSCALE 1 -#define R600_VPT_XOFFSET 2 -#define R600_VPT_YSCALE 3 -#define R600_VPT_YOFFSET 4 -#define R600_VPT_ZSCALE 5 -#define R600_VPT_ZOFFSET 6 -#define R600_VPT_CMDSIZE 7 - -#define R600_VIR_CMD_0 0 /* vir is variable size (at least 1) */ -#define R600_VIR_CNTL_0 1 -#define R600_VIR_CNTL_1 2 -#define R600_VIR_CNTL_2 3 -#define R600_VIR_CNTL_3 4 -#define R600_VIR_CNTL_4 5 -#define R600_VIR_CNTL_5 6 -#define R600_VIR_CNTL_6 7 -#define R600_VIR_CNTL_7 8 -#define R600_VIR_CMDSIZE 9 - -#define R600_VIC_CMD_0 0 -#define R600_VIC_CNTL_0 1 -#define R600_VIC_CNTL_1 2 -#define R600_VIC_CMDSIZE 3 - -#define R600_VOF_CMD_0 0 -#define R600_VOF_CNTL_0 1 -#define R600_VOF_CNTL_1 2 -#define R600_VOF_CMDSIZE 3 - -#define R600_PVS_CMD_0 0 -#define R600_PVS_CNTL_1 1 -#define R600_PVS_CNTL_2 2 -#define R600_PVS_CNTL_3 3 -#define R600_PVS_CMDSIZE 4 - -#define R600_GB_MISC_CMD_0 0 -#define R600_GB_MISC_MSPOS_0 1 -#define R600_GB_MISC_MSPOS_1 2 -#define R600_GB_MISC_TILE_CONFIG 3 -#define R600_GB_MISC_SELECT 4 -#define R600_GB_MISC_AA_CONFIG 5 -#define R600_GB_MISC_CMDSIZE 6 - -#define R600_TXE_CMD_0 0 -#define R600_TXE_ENABLE 1 -#define R600_TXE_CMDSIZE 2 - -#define R600_PS_CMD_0 0 -#define R600_PS_POINTSIZE 1 -#define R600_PS_CMDSIZE 2 - -#define R600_ZBS_CMD_0 0 -#define R600_ZBS_T_FACTOR 1 -#define R600_ZBS_T_CONSTANT 2 -#define R600_ZBS_W_FACTOR 3 -#define R600_ZBS_W_CONSTANT 4 -#define R600_ZBS_CMDSIZE 5 - -#define R600_CUL_CMD_0 0 -#define R600_CUL_CULL 1 -#define R600_CUL_CMDSIZE 2 - -#define R600_RC_CMD_0 0 -#define R600_RC_CNTL_0 1 -#define R600_RC_CNTL_1 2 -#define R600_RC_CMDSIZE 3 - -#define R600_RI_CMD_0 0 -#define R600_RI_INTERP_0 1 -#define R600_RI_INTERP_1 2 -#define R600_RI_INTERP_2 3 -#define R600_RI_INTERP_3 4 -#define R600_RI_INTERP_4 5 -#define R600_RI_INTERP_5 6 -#define R600_RI_INTERP_6 7 -#define R600_RI_INTERP_7 8 -#define R600_RI_CMDSIZE 9 - -#define R500_RI_CMDSIZE 17 - -#define R600_RR_CMD_0 0 /* rr is variable size (at least 1) */ -#define R600_RR_INST_0 1 -#define R600_RR_INST_1 2 -#define R600_RR_INST_2 3 -#define R600_RR_INST_3 4 -#define R600_RR_INST_4 5 -#define R600_RR_INST_5 6 -#define R600_RR_INST_6 7 -#define R600_RR_INST_7 8 -#define R600_RR_CMDSIZE 9 - -#define R600_FP_CMD_0 0 -#define R600_FP_CNTL0 1 -#define R600_FP_CNTL1 2 -#define R600_FP_CNTL2 3 -#define R600_FP_CMD_1 4 -#define R600_FP_NODE0 5 -#define R600_FP_NODE1 6 -#define R600_FP_NODE2 7 -#define R600_FP_NODE3 8 -#define R600_FP_CMDSIZE 9 - -#define R500_FP_CMD_0 0 -#define R500_FP_CNTL 1 -#define R500_FP_PIXSIZE 2 -#define R500_FP_CMD_1 3 -#define R500_FP_CODE_ADDR 4 -#define R500_FP_CODE_RANGE 5 -#define R500_FP_CODE_OFFSET 6 -#define R500_FP_CMD_2 7 -#define R500_FP_FC_CNTL 8 -#define R500_FP_CMDSIZE 9 - -#define R600_FPT_CMD_0 0 -#define R600_FPT_INSTR_0 1 -#define R600_FPT_CMDSIZE 65 - -#define R600_FPI_CMD_0 0 -#define R600_FPI_INSTR_0 1 -#define R600_FPI_CMDSIZE 65 -/* R500 has space for 512 instructions - 6 dwords per instruction */ -#define R500_FPI_CMDSIZE (512*6+1) - -#define R600_FPP_CMD_0 0 -#define R600_FPP_PARAM_0 1 -#define R600_FPP_CMDSIZE (32*4+1) -/* R500 has spcae for 256 constants - 4 dwords per constant */ -#define R500_FPP_CMDSIZE (256*4+1) - -#define R600_FOGS_CMD_0 0 -#define R600_FOGS_STATE 1 -#define R600_FOGS_CMDSIZE 2 - -#define R600_FOGC_CMD_0 0 -#define R600_FOGC_R 1 -#define R600_FOGC_G 2 -#define R600_FOGC_B 3 -#define R600_FOGC_CMDSIZE 4 - -#define R600_FOGP_CMD_0 0 -#define R600_FOGP_SCALE 1 -#define R600_FOGP_START 2 -#define R600_FOGP_CMDSIZE 3 - -#define R600_AT_CMD_0 0 -#define R600_AT_ALPHA_TEST 1 -#define R600_AT_UNKNOWN 2 -#define R600_AT_CMDSIZE 3 - -#define R600_BLD_CMD_0 0 -#define R600_BLD_CBLEND 1 -#define R600_BLD_ABLEND 2 -#define R600_BLD_CMDSIZE 3 - -#define R600_CMK_CMD_0 0 -#define R600_CMK_COLORMASK 1 -#define R600_CMK_CMDSIZE 2 - -#define R600_CB_CMD_0 0 -#define R600_CB_OFFSET 1 -#define R600_CB_CMD_1 2 -#define R600_CB_PITCH 3 -#define R600_CB_CMDSIZE 4 - -#define R600_ZS_CMD_0 0 -#define R600_ZS_CNTL_0 1 -#define R600_ZS_CNTL_1 2 -#define R600_ZS_CNTL_2 3 -#define R600_ZS_CMDSIZE 4 - -#define R600_ZB_CMD_0 0 -#define R600_ZB_OFFSET 1 -#define R600_ZB_PITCH 2 -#define R600_ZB_CMDSIZE 3 - -#define R600_VAP_CNTL_FLUSH 0 -#define R600_VAP_CNTL_FLUSH_1 1 -#define R600_VAP_CNTL_CMD 2 -#define R600_VAP_CNTL_INSTR 3 -#define R600_VAP_CNTL_SIZE 4 - -#define R600_VPI_CMD_0 0 -#define R600_VPI_INSTR_0 1 -#define R600_VPI_CMDSIZE 1025 /* 256 16 byte instructions */ - -#define R600_VPP_CMD_0 0 -#define R600_VPP_PARAM_0 1 -#define R600_VPP_CMDSIZE 1025 /* 256 4-component parameters */ - -#define R600_VPUCP_CMD_0 0 -#define R600_VPUCP_X 1 -#define R600_VPUCP_Y 2 -#define R600_VPUCP_Z 3 -#define R600_VPUCP_W 4 -#define R600_VPUCP_CMDSIZE 5 /* 256 4-component parameters */ - -#define R600_VPS_CMD_0 0 -#define R600_VPS_ZERO_0 1 -#define R600_VPS_ZERO_1 2 -#define R600_VPS_POINTSIZE 3 -#define R600_VPS_ZERO_3 4 -#define R600_VPS_CMDSIZE 5 - - /* the layout is common for all fields inside tex */ -#define R600_TEX_CMD_0 0 -#define R600_TEX_VALUE_0 1 -/* We don't really use this, instead specify mtu+1 dynamically -#define R600_TEX_CMDSIZE (MAX_TEXTURE_UNITS+1) -*/ - -/** - * Cache for hardware register state. - */ -struct r600_hw_state { - struct radeon_state_atom vpt; /* viewport (1D98) */ - struct radeon_state_atom vap_cntl; - struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */ - struct radeon_state_atom vof; /* VAP output format register 0x2090 */ - struct radeon_state_atom vte; /* (20B0) */ - struct radeon_state_atom vap_vf_max_vtx_indx; /* Maximum Vertex Indx Clamp (2134) */ - struct radeon_state_atom vap_cntl_status; - struct radeon_state_atom vir[2]; /* vap input route (2150/21E0) */ - struct radeon_state_atom vic; /* vap input control (2180) */ - struct radeon_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */ - struct radeon_state_atom vap_clip_cntl; - struct radeon_state_atom vap_clip; - struct radeon_state_atom vap_pvs_vtx_timeout_reg; /* Vertex timeout register (2288) */ - struct radeon_state_atom pvs; /* pvs_cntl (22D0) */ - struct radeon_state_atom gb_enable; /* (4008) */ - struct radeon_state_atom gb_misc; /* Multisampling position shifts ? (4010) */ - struct radeon_state_atom ga_point_s0; /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */ - struct radeon_state_atom ga_triangle_stipple; /* (4214) */ - struct radeon_state_atom ps; /* pointsize (421C) */ - struct radeon_state_atom ga_point_minmax; /* (4230) */ - struct radeon_state_atom lcntl; /* line control */ - struct radeon_state_atom ga_line_stipple; /* (4260) */ - struct radeon_state_atom shade; - struct radeon_state_atom polygon_mode; - struct radeon_state_atom fogp; /* fog parameters (4294) */ - struct radeon_state_atom ga_soft_reset; /* (429C) */ - struct radeon_state_atom zbias_cntl; - struct radeon_state_atom zbs; /* zbias (42A4) */ - struct radeon_state_atom occlusion_cntl; - struct radeon_state_atom cul; /* cull cntl (42B8) */ - struct radeon_state_atom su_depth_scale; /* (42C0) */ - struct radeon_state_atom rc; /* rs control (4300) */ - struct radeon_state_atom ri; /* rs interpolators (4310) */ - struct radeon_state_atom rr; /* rs route (4330) */ - struct radeon_state_atom sc_hyperz; /* (43A4) */ - struct radeon_state_atom sc_screendoor; /* (43E8) */ - struct radeon_state_atom fp; /* fragment program cntl + nodes (4600) */ - struct radeon_state_atom fpt; /* texi - (4620) */ - struct radeon_state_atom us_out_fmt; /* (46A4) */ - struct radeon_state_atom r500fp; /* r500 fp instructions */ - struct radeon_state_atom r500fp_const; /* r500 fp constants */ - struct radeon_state_atom fpi[4]; /* fp instructions (46C0/47C0/48C0/49C0) */ - struct radeon_state_atom fogs; /* fog state (4BC0) */ - struct radeon_state_atom fogc; /* fog color (4BC8) */ - struct radeon_state_atom at; /* alpha test (4BD4) */ - struct radeon_state_atom fg_depth_src; /* (4BD8) */ - struct radeon_state_atom fpp; /* 0x4C00 and following */ - struct radeon_state_atom rb3d_cctl; /* (4E00) */ - struct radeon_state_atom bld; /* blending (4E04) */ - struct radeon_state_atom cmk; /* colormask (4E0C) */ - struct radeon_state_atom blend_color; /* constant blend color */ - struct radeon_state_atom rop; /* ropcntl */ - struct radeon_state_atom cb; /* colorbuffer (4E28) */ - struct radeon_state_atom rb3d_dither_ctl; /* (4E50) */ - struct radeon_state_atom rb3d_aaresolve_ctl; /* (4E88) */ - struct radeon_state_atom rb3d_discard_src_pixel_lte_threshold; /* (4E88) I saw it only written on RV350 hardware.. */ - struct radeon_state_atom zs; /* zstencil control (4F00) */ - struct radeon_state_atom zstencil_format; - struct radeon_state_atom zb; /* z buffer (4F20) */ - struct radeon_state_atom zb_depthclearvalue; /* (4F28) */ - struct radeon_state_atom unk4F30; /* (4F30) */ - struct radeon_state_atom zb_hiz_offset; /* (4F44) */ - struct radeon_state_atom zb_hiz_pitch; /* (4F54) */ - - struct radeon_state_atom vpi; /* vp instructions */ - struct radeon_state_atom vpp; /* vp parameters */ - struct radeon_state_atom vps; /* vertex point size (?) */ - struct radeon_state_atom vpucp[6]; /* vp user clip plane - 6 */ - /* 8 texture units */ - /* the state is grouped by function and not by - texture unit. This makes single unit updates - really awkward - we are much better off - updating the whole thing at once */ - struct { - struct radeon_state_atom filter; - struct radeon_state_atom filter_1; - struct radeon_state_atom size; - struct radeon_state_atom format; - struct radeon_state_atom pitch; - struct radeon_state_atom offset; - struct radeon_state_atom chroma_key; - struct radeon_state_atom border_color; - } tex; - struct radeon_state_atom txe; /* tex enable (4104) */ - - radeonTexObj *textures[R600_MAX_TEXTURE_UNITS]; -}; - -/** - * State cache - */ - -/* Vertex shader state */ - /* Perhaps more if we store programs in vmem? */ /* drm_r600_cmd_header_t->vpu->count is unsigned char */ #define VSF_MAX_FRAGMENT_LENGTH (255*4) @@ -407,19 +93,6 @@ struct r600_hw_state { #define STATE_R600_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0) #define STATE_R600_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1) -struct r600_vertex_shader_fragment { - int length; - union { - GLuint d[VSF_MAX_FRAGMENT_LENGTH]; - float f[VSF_MAX_FRAGMENT_LENGTH]; - GLuint i[VSF_MAX_FRAGMENT_LENGTH]; - } body; -}; - -struct r600_vertex_shader_state { - struct r600_vertex_shader_fragment program; -}; - extern int hw_tcl_on; #define COLOR_IS_RGBA @@ -427,219 +100,18 @@ extern int hw_tcl_on; #include "tnl_dd/t_dd_vertex.h" #undef TAG -//#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current) -#define CURRENT_VERTEX_SHADER(ctx) (R600_CONTEXT(ctx)->selected_vp) - -/* Should but doesnt work */ -//#define CURRENT_VERTEX_SHADER(ctx) (R600_CONTEXT(ctx)->curr_vp) - -/* r600_vertex_shader_state and r600_vertex_program should probably be merged together someday. - * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly. - */ - -struct r600_vertex_program_key { - GLuint InputsRead; - GLuint OutputsWritten; - GLuint OutputsAdded; -}; - -struct r600_vertex_program { - struct r600_vertex_program *next; - struct r600_vertex_program_key key; - int translated; - - struct r600_vertex_shader_fragment program; - - int pos_end; - int num_temporaries; /* Number of temp vars used by program */ - int wpos_idx; - int inputs[VERT_ATTRIB_MAX]; - int outputs[VERT_RESULT_MAX]; - int native; - int ref_count; - int use_ref_count; -}; - -struct r600_vertex_program_cont { - struct gl_vertex_program mesa_program; /* Must be first */ - struct r600_vertex_shader_fragment params; - struct r600_vertex_program *progs; -}; - #define PFS_MAX_ALU_INST 64 #define PFS_MAX_TEX_INST 64 #define PFS_MAX_TEX_INDIRECT 4 #define PFS_NUM_TEMP_REGS 32 #define PFS_NUM_CONST_REGS 16 -struct r600_pfs_compile_state; - - -/** - * Stores state that influences the compilation of a fragment program. - */ -struct r600_fragment_program_external_state { - struct { - /** - * If the sampler is used as a shadow sampler, - * this field is: - * 0 - GL_LUMINANCE - * 1 - GL_INTENSITY - * 2 - GL_ALPHA - * depending on the depth texture mode. - */ - GLuint depth_texture_mode : 2; - - /** - * If the sampler is used as a shadow sampler, - * this field is (texture_compare_func - GL_NEVER). - * [e.g. if compare function is GL_LEQUAL, this field is 3] - * - * Otherwise, this field is 0. - */ - GLuint texture_compare_func : 3; - } unit[16]; -}; - - -struct r600_fragment_program_node { - int tex_offset; /**< first tex instruction */ - int tex_end; /**< last tex instruction, relative to tex_offset */ - int alu_offset; /**< first ALU instruction */ - int alu_end; /**< last ALU instruction, relative to alu_offset */ - int flags; -}; - -/** - * Stores an R600 fragment program in its compiled-to-hardware form. - */ -struct r600_fragment_program_code { - struct { - int length; /**< total # of texture instructions used */ - GLuint inst[PFS_MAX_TEX_INST]; - } tex; - - struct { - int length; /**< total # of ALU instructions used */ - struct { - GLuint inst0; - GLuint inst1; - GLuint inst2; - GLuint inst3; - } inst[PFS_MAX_ALU_INST]; - } alu; - - struct r600_fragment_program_node node[4]; - int cur_node; - int first_node_has_tex; - - /** - * Remember which program register a given hardware constant - * belongs to. - */ - struct prog_src_register constant[PFS_NUM_CONST_REGS]; - int const_nr; - - int max_temp_idx; -}; - -/** - * Store everything about a fragment program that is needed - * to render with that program. - */ -struct r600_fragment_program { - struct gl_fragment_program mesa_program; - - GLboolean translated; - GLboolean error; - - struct r600_fragment_program_external_state state; - struct r600_fragment_program_code code; - - GLboolean WritesDepth; - GLuint optimization; -}; - -struct r500_pfs_compile_state; - -struct r500_fragment_program_external_state { - struct { - /** - * If the sampler is used as a shadow sampler, - * this field is: - * 0 - GL_LUMINANCE - * 1 - GL_INTENSITY - * 2 - GL_ALPHA - * depending on the depth texture mode. - */ - GLuint depth_texture_mode : 2; - - /** - * If the sampler is used as a shadow sampler, - * this field is (texture_compare_func - GL_NEVER). - * [e.g. if compare function is GL_LEQUAL, this field is 3] - * - * Otherwise, this field is 0. - */ - GLuint texture_compare_func : 3; - } unit[16]; -}; - -struct r500_fragment_program_code { - struct { - GLuint inst0; - GLuint inst1; - GLuint inst2; - GLuint inst3; - GLuint inst4; - GLuint inst5; - } inst[512]; - - int inst_offset; - int inst_end; - - /** - * Remember which program register a given hardware constant - * belongs to. - */ - struct prog_src_register constant[PFS_NUM_CONST_REGS]; - int const_nr; - - int max_temp_idx; -}; - -struct r500_fragment_program { - struct gl_fragment_program mesa_program; - - GLcontext *ctx; - GLboolean translated; - GLboolean error; - - struct r500_fragment_program_external_state state; - struct r500_fragment_program_code code; - - GLboolean writes_depth; - - GLuint optimization; -}; - #define R600_MAX_AOS_ARRAYS 16 #define REG_COORDS 0 #define REG_COLOR0 1 #define REG_TEX0 2 -struct r600_state { - struct r600_texture_state texture; - int sw_tcl_inputs[VERT_ATTRIB_MAX]; - struct r600_vertex_shader_state vertex_shader; - - - DECLARE_RENDERINPUTS(render_inputs_bitset); /* actual render inputs that R600 was configured for. - They are the same as tnl->render_inputs for fixed pipeline */ - -}; - #define R600_FALLBACK_NONE 0 #define R600_FALLBACK_TCL 1 #define R600_FALLBACK_RAST 2 @@ -668,6 +140,71 @@ struct r600_swtcl_info { GLubyte vertex_attr_count; }; +/* to be enabled */ /* DELETE FOLLOWING 2 SRTUCTS */ +struct r600_dma_buffer +{ + int refcount; /* the number of retained regions in buf */ + drmBufPtr buf; + int id; +}; +struct r600_dma_region +{ + struct r600_dma_buffer *buf; + char *address; /* == buf->address */ + int start; + int end; + int ptr; /* offsets from start of buf */ + + int aos_offset; /* address in GART memory */ + int aos_stride; /* distance between elements, in dwords */ + int aos_size; /* number of components (1-4) */ +}; +/* ----------------------- */ + +typedef struct chip_object +{ + void *pvChipObj; + + /* ------------ OUT ------------------- */ + GLboolean (*DestroyChipObj)(void* pvChipObj); + + void (*InitFuncs)(struct dd_function_table *functions); + + void (*InitState)(GLcontext * ctx); + + GLuint (*GetTexObjSize)(void); + + /* ------------ IN ------------------- */ + void (*EmitShader)( GLcontext * ctx, + struct r600_dma_region *rvb, + GLvoid * data, + int sizeinDWORD); + void (*FreeDmaRegion)( GLcontext * ctx, + struct r600_dma_region *region); + void (*EmitVec)(GLcontext * ctx, + struct r600_dma_region *rvb, + GLvoid * data, + int size, + int stride, + int count); + void (*MemUse)(context_t *context, int id); + void (*ReleaseArrays)(GLcontext * ctx); + int (*FlushCmdBuffer)(GLcontext * ctx); + GLboolean (*LoadMemSurf)(context_t *context, + GLuint dst_offset, /* gpu addr */ + GLuint dst_pitch_in_pixel, + GLuint src_width_in_pixel, + GLuint height, + GLuint byte_per_pixel, + unsigned char* pSrc); /* source data */ + GLboolean (*AllocMemSurf)(context_t *context, + void **ppmemBlock, + void **ppheap, + GLuint *prefered_heap, + GLuint totalSize); + + struct tnl_pipeline_stage **stages; +} chip_object; /** * \brief R600 context structure. @@ -675,11 +212,8 @@ struct r600_swtcl_info { struct r600_context { struct radeon_context radeon; /* parent class, must be first */ - struct r600_hw_state hw; - - struct r600_state state; - struct gl_vertex_program *curr_vp; - struct r600_vertex_program *selected_vp; + /* ------ */ + chip_object chipobj; /* Vertex buffers */ @@ -693,18 +227,14 @@ struct r600_context { }; #define R600_CONTEXT(ctx) ((r600ContextPtr)(ctx->DriverCtx)) +#define R700_CONTEXT(ctx) ((context_t *)(ctx->DriverCtx)) +#define GL_CONTEXT(context) ((GLcontext *)(context->radeon.glCtx)) extern void r600DestroyContext(__DRIcontextPrivate * driContextPriv); extern GLboolean r600CreateContext(const __GLcontextModes * glVisual, __DRIcontextPrivate * driContextPriv, void *sharedContextPrivate); -extern void r600SelectVertexShader(r600ContextPtr r600); -extern void r600InitShaderFuncs(struct dd_function_table *functions); -extern int r600VertexProgUpdateParams(GLcontext * ctx, - struct r600_vertex_program_cont *vp, - float *dst); - #define RADEON_D_CAPTURE 0 #define RADEON_D_PLAYBACK 1 #define RADEON_D_PLAYBACK_RAW 2 diff --git a/src/mesa/drivers/dri/r600/r600_emit.c b/src/mesa/drivers/dri/r600/r600_emit.c index 7004f7a2b7..9d43873c4d 100644 --- a/src/mesa/drivers/dri/r600/r600_emit.c +++ b/src/mesa/drivers/dri/r600/r600_emit.c @@ -46,156 +46,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "tnl/t_context.h" #include "r600_context.h" -#include "r600_state.h" #include "r600_emit.h" -#include "r600_ioctl.h" - - -#if SWIZZLE_X != R600_INPUT_ROUTE_SELECT_X || \ - SWIZZLE_Y != R600_INPUT_ROUTE_SELECT_Y || \ - SWIZZLE_Z != R600_INPUT_ROUTE_SELECT_Z || \ - SWIZZLE_W != R600_INPUT_ROUTE_SELECT_W || \ - SWIZZLE_ZERO != R600_INPUT_ROUTE_SELECT_ZERO || \ - SWIZZLE_ONE != R600_INPUT_ROUTE_SELECT_ONE -#error Cannot change these! -#endif - -#define DEBUG_ALL DEBUG_VERTS - -#define DW_SIZE(x) ((inputs[tab[(x)]] << R600_DST_VEC_LOC_SHIFT) | \ - (attribptr[tab[(x)]]->size - 1) << R600_DATA_TYPE_0_SHIFT) - -GLuint r600VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr, - int *inputs, GLint * tab, GLuint nr) -{ - GLuint i, dw; - - /* type, inputs, stop bit, size */ - for (i = 0; i < nr; i += 2) { - /* make sure input is valid, would lockup the gpu */ - assert(inputs[tab[i]] != -1); - dw = (R600_SIGNED | DW_SIZE(i)); - if (i + 1 == nr) { - dw |= R600_LAST_VEC << R600_DATA_TYPE_0_SHIFT; - } else { - assert(inputs[tab[i + 1]] != -1); - dw |= (R600_SIGNED | - DW_SIZE(i + 1)) << R600_DATA_TYPE_1_SHIFT; - if (i + 2 == nr) { - dw |= R600_LAST_VEC << R600_DATA_TYPE_1_SHIFT; - } - } - dst[i >> 1] = dw; - } - - return (nr + 1) >> 1; -} - -static GLuint r600VAPInputRoute1Swizzle(int swizzle[4]) -{ - return (swizzle[0] << R600_SWIZZLE_SELECT_X_SHIFT) | - (swizzle[1] << R600_SWIZZLE_SELECT_Y_SHIFT) | - (swizzle[2] << R600_SWIZZLE_SELECT_Z_SHIFT) | - (swizzle[3] << R600_SWIZZLE_SELECT_W_SHIFT); -} - -GLuint r600VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr) -{ - GLuint i, dw; - - for (i = 0; i < nr; i += 2) { - dw = (r600VAPInputRoute1Swizzle(swizzle[i]) | - ((R600_WRITE_ENA_X | R600_WRITE_ENA_Y | - R600_WRITE_ENA_Z | R600_WRITE_ENA_W) << R600_WRITE_ENA_SHIFT)) << R600_SWIZZLE0_SHIFT; - if (i + 1 < nr) { - dw |= (r600VAPInputRoute1Swizzle(swizzle[i + 1]) | - ((R600_WRITE_ENA_X | R600_WRITE_ENA_Y | - R600_WRITE_ENA_Z | R600_WRITE_ENA_W) << R600_WRITE_ENA_SHIFT)) << R600_SWIZZLE1_SHIFT; - } - dst[i >> 1] = dw; - } - - return (nr + 1) >> 1; -} - -GLuint r600VAPInputCntl0(GLcontext * ctx, GLuint InputsRead) -{ - /* No idea what this value means. I have seen other values written to - * this register... */ - return 0x5555; -} - -GLuint r600VAPInputCntl1(GLcontext * ctx, GLuint InputsRead) -{ - r600ContextPtr rmesa = R600_CONTEXT(ctx); - GLuint i, vic_1 = 0; - - if (InputsRead & (1 << VERT_ATTRIB_POS)) - vic_1 |= R600_INPUT_CNTL_POS; - - if (InputsRead & (1 << VERT_ATTRIB_NORMAL)) - vic_1 |= R600_INPUT_CNTL_NORMAL; - - if (InputsRead & (1 << VERT_ATTRIB_COLOR0)) - vic_1 |= R600_INPUT_CNTL_COLOR; - - rmesa->state.texture.tc_count = 0; - for (i = 0; i < ctx->Const.MaxTextureUnits; i++) - if (InputsRead & (1 << (VERT_ATTRIB_TEX0 + i))) { - rmesa->state.texture.tc_count++; - vic_1 |= R600_INPUT_CNTL_TC0 << i; - } - - return vic_1; -} - -GLuint r600VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten) -{ - GLuint ret = 0; - - if (OutputsWritten & (1 << VERT_RESULT_HPOS)) - ret |= R600_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT; - - if (OutputsWritten & (1 << VERT_RESULT_COL0)) - ret |= R600_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT; - - if (OutputsWritten & (1 << VERT_RESULT_COL1)) - ret |= R600_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT; - - if (OutputsWritten & (1 << VERT_RESULT_BFC0) - || OutputsWritten & (1 << VERT_RESULT_BFC1)) - ret |= - R600_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT | - R600_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT | - R600_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT; - - if (OutputsWritten & (1 << VERT_RESULT_PSIZ)) - ret |= R600_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT; - - return ret; -} - -GLuint r600VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten) -{ - GLuint i, ret = 0, first_free_texcoord = 0; - - for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - if (OutputsWritten & (1 << (VERT_RESULT_TEX0 + i))) { - ret |= (4 << (3 * i)); - ++first_free_texcoord; - } - } - - if (OutputsWritten & (1 << VERT_RESULT_FOGC)) { - if (first_free_texcoord > 8) { - fprintf(stderr, "\tout of free texcoords to write fog coord\n"); - _mesa_exit(-1); - } - ret |= 4 << (3 * first_free_texcoord); - } - - return ret; -} /* Emit vertex data to GART memory * Route inputs to the vertex processor @@ -203,155 +54,14 @@ GLuint r600VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten) */ int r600EmitArrays(GLcontext * ctx) { - r600ContextPtr rmesa = R600_CONTEXT(ctx); - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *vb = &tnl->vb; - GLuint nr; - GLuint count = vb->Count; - GLuint i; - GLuint InputsRead = 0, OutputsWritten = 0; - int *inputs = NULL; - int vir_inputs[VERT_ATTRIB_MAX]; - GLint tab[VERT_ATTRIB_MAX]; - int swizzle[VERT_ATTRIB_MAX][4]; - struct r600_vertex_program *prog = - (struct r600_vertex_program *)CURRENT_VERTEX_SHADER(ctx); - - if (hw_tcl_on) { - inputs = prog->inputs; - InputsRead = prog->key.InputsRead; - OutputsWritten = prog->key.OutputsWritten; - } else { - inputs = rmesa->state.sw_tcl_inputs; - - DECLARE_RENDERINPUTS(render_inputs_bitset); - RENDERINPUTS_COPY(render_inputs_bitset, tnl->render_inputs_bitset); - - vb->AttribPtr[VERT_ATTRIB_POS] = vb->ClipPtr; - - assert(RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_POS)); - assert(RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_NORMAL) == 0); - - if (RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_POS)) { - InputsRead |= 1 << VERT_ATTRIB_POS; - OutputsWritten |= 1 << VERT_RESULT_HPOS; - } - - if (RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_COLOR0)) { - InputsRead |= 1 << VERT_ATTRIB_COLOR0; - OutputsWritten |= 1 << VERT_RESULT_COL0; - } - - if (RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_COLOR1)) { - InputsRead |= 1 << VERT_ATTRIB_COLOR1; - OutputsWritten |= 1 << VERT_RESULT_COL1; - } - - for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - if (RENDERINPUTS_TEST(render_inputs_bitset, _TNL_ATTRIB_TEX(i))) { - InputsRead |= 1 << (VERT_ATTRIB_TEX0 + i); - OutputsWritten |= 1 << (VERT_RESULT_TEX0 + i); - } - } - - for (i = 0, nr = 0; i < VERT_ATTRIB_MAX; i++) { - if (InputsRead & (1 << i)) { - inputs[i] = nr++; - } else { - inputs[i] = -1; - } - } - - /* Fixed, apply to vir0 only */ - memcpy(vir_inputs, inputs, VERT_ATTRIB_MAX * sizeof(int)); - inputs = vir_inputs; - if (InputsRead & VERT_ATTRIB_POS) - inputs[VERT_ATTRIB_POS] = 0; - if (InputsRead & (1 << VERT_ATTRIB_COLOR0)) - inputs[VERT_ATTRIB_COLOR0] = 2; - if (InputsRead & (1 << VERT_ATTRIB_COLOR1)) - inputs[VERT_ATTRIB_COLOR1] = 3; - for (i = VERT_ATTRIB_TEX0; i <= VERT_ATTRIB_TEX7; i++) - if (InputsRead & (1 << i)) - inputs[i] = 6 + (i - VERT_ATTRIB_TEX0); - - RENDERINPUTS_COPY(rmesa->state.render_inputs_bitset, render_inputs_bitset); - } - - assert(InputsRead); - assert(OutputsWritten); - - for (i = 0, nr = 0; i < VERT_ATTRIB_MAX; i++) { - if (InputsRead & (1 << i)) { - tab[nr++] = i; - } - } - - if (nr > R600_MAX_AOS_ARRAYS) { - return R600_FALLBACK_TCL; - } - - for (i = 0; i < nr; i++) { - int ci; - - swizzle[i][0] = SWIZZLE_ZERO; - swizzle[i][1] = SWIZZLE_ZERO; - swizzle[i][2] = SWIZZLE_ZERO; - swizzle[i][3] = SWIZZLE_ONE; - - for (ci = 0; ci < vb->AttribPtr[tab[i]]->size; ci++) { - swizzle[i][ci] = ci; - } - rcommon_emit_vector(ctx, &rmesa->radeon.tcl.aos[i], - vb->AttribPtr[tab[i]]->data, - vb->AttribPtr[tab[i]]->size, - vb->AttribPtr[tab[i]]->stride, count); - } - - /* Setup INPUT_ROUTE. */ - if (rmesa->radeon.radeonScreen->kernel_mm) { - R600_STATECHANGE(rmesa, vir[0]); - rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF; - rmesa->hw.vir[1].cmd[0] &= 0xC000FFFF; - rmesa->hw.vir[0].cmd[0] |= - (r600VAPInputRoute0(&rmesa->hw.vir[0].cmd[R600_VIR_CNTL_0], - vb->AttribPtr, inputs, tab, nr) & 0x3FFF) << 16; - R600_STATECHANGE(rmesa, vir[1]); - rmesa->hw.vir[1].cmd[0] |= - (r600VAPInputRoute1(&rmesa->hw.vir[1].cmd[R600_VIR_CNTL_0], swizzle, - nr) & 0x3FFF) << 16; - } else { - R600_STATECHANGE(rmesa, vir[0]); - ((drm_r300_cmd_header_t *) rmesa->hw.vir[0].cmd)->packet0.count = - r600VAPInputRoute0(&rmesa->hw.vir[0].cmd[R600_VIR_CNTL_0], - vb->AttribPtr, inputs, tab, nr); - R600_STATECHANGE(rmesa, vir[1]); - ((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = - r600VAPInputRoute1(&rmesa->hw.vir[1].cmd[R600_VIR_CNTL_0], swizzle, - nr); - } - /* Setup INPUT_CNTL. */ - R600_STATECHANGE(rmesa, vic); - rmesa->hw.vic.cmd[R600_VIC_CNTL_0] = r600VAPInputCntl0(ctx, InputsRead); - rmesa->hw.vic.cmd[R600_VIC_CNTL_1] = r600VAPInputCntl1(ctx, InputsRead); - - /* Setup OUTPUT_VTX_FMT. */ - R600_STATECHANGE(rmesa, vof); - rmesa->hw.vof.cmd[R600_VOF_CNTL_0] = - r600VAPOutputCntl0(ctx, OutputsWritten); - rmesa->hw.vof.cmd[R600_VOF_CNTL_1] = - r600VAPOutputCntl1(ctx, OutputsWritten); - - rmesa->radeon.tcl.aos_count = nr; - return R600_FALLBACK_NONE; } void r600EmitCacheFlush(r600ContextPtr rmesa) { BATCH_LOCALS(&rmesa->radeon); - +/* BEGIN_BATCH_NO_AUTOSTATE(4); OUT_BATCH_REGVAL(R600_RB3D_DSTCACHE_CTLSTAT, R600_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS | @@ -361,4 +71,5 @@ void r600EmitCacheFlush(r600ContextPtr rmesa) R600_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); END_BATCH(); COMMIT_BATCH(); +*/ } diff --git a/src/mesa/drivers/dri/r600/r600_reg_auto_r6xx.h b/src/mesa/drivers/dri/r600/r600_reg_auto_r6xx.h new file mode 100644 index 0000000000..9d5aa3c7e4 --- /dev/null +++ b/src/mesa/drivers/dri/r600/r600_reg_auto_r6xx.h @@ -0,0 +1,3087 @@ +/* + * RadeonHD R6xx, R7xx Register documentation + * + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2009 Matthias Hopf + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _AUTOREGS +#define _AUTOREGS + +enum { + + VGT_VTX_VECT_EJECT_REG = 0x000088b0, + PRIM_COUNT_mask = 0x3ff << 0, + PRIM_COUNT_shift = 0, + VGT_LAST_COPY_STATE = 0x000088c0, + SRC_STATE_ID_mask = 0x07 << 0, + SRC_STATE_ID_shift = 0, + DST_STATE_ID_mask = 0x07 << 16, + DST_STATE_ID_shift = 16, + VGT_CACHE_INVALIDATION = 0x000088c4, + CACHE_INVALIDATION_mask = 0x03 << 0, + CACHE_INVALIDATION_shift = 0, + VC_ONLY = 0x00, + TC_ONLY = 0x01, + VC_AND_TC = 0x02, + VS_NO_EXTRA_BUFFER_bit = 1 << 5, + VGT_GS_PER_ES = 0x000088c8, + VGT_ES_PER_GS = 0x000088cc, + VGT_GS_VERTEX_REUSE = 0x000088d4, + VERT_REUSE_mask = 0x1f << 0, + VERT_REUSE_shift = 0, + VGT_MC_LAT_CNTL = 0x000088d8, + MC_TIME_STAMP_RES_mask = 0x03 << 0, + MC_TIME_STAMP_RES_shift = 0, + X_0_992_MAX_LATENCY = 0x00, + X_0_496_MAX_LATENCY = 0x01, + X_0_248_MAX_LATENCY = 0x02, + X_0_124_MAX_LATENCY = 0x03, + VGT_GS_PER_VS = 0x000088e8, + GS_PER_VS_mask = 0x0f << 0, + GS_PER_VS_shift = 0, + VGT_CNTL_STATUS = 0x000088f0, + VGT_OUT_INDX_BUSY_bit = 1 << 0, + VGT_OUT_BUSY_bit = 1 << 1, + VGT_PT_BUSY_bit = 1 << 2, + VGT_TE_BUSY_bit = 1 << 3, + VGT_VR_BUSY_bit = 1 << 4, + VGT_GRP_BUSY_bit = 1 << 5, + VGT_DMA_REQ_BUSY_bit = 1 << 6, + VGT_DMA_BUSY_bit = 1 << 7, + VGT_GS_BUSY_bit = 1 << 8, + VGT_BUSY_bit = 1 << 9, + VGT_PRIMITIVE_TYPE = 0x00008958, + VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask = 0x3f << 0, + VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift = 0, + DI_PT_NONE = 0x00, + DI_PT_POINTLIST = 0x01, + DI_PT_LINELIST = 0x02, + DI_PT_LINESTRIP = 0x03, + DI_PT_TRILIST = 0x04, + DI_PT_TRIFAN = 0x05, + DI_PT_TRISTRIP = 0x06, + DI_PT_UNUSED_0 = 0x07, + DI_PT_UNUSED_1 = 0x08, + DI_PT_UNUSED_2 = 0x09, + DI_PT_LINELIST_ADJ = 0x0a, + DI_PT_LINESTRIP_ADJ = 0x0b, + DI_PT_TRILIST_ADJ = 0x0c, + DI_PT_TRISTRIP_ADJ = 0x0d, + DI_PT_UNUSED_3 = 0x0e, + DI_PT_UNUSED_4 = 0x0f, + DI_PT_TRI_WITH_WFLAGS = 0x10, + DI_PT_RECTLIST = 0x11, + DI_PT_LINELOOP = 0x12, + DI_PT_QUADLIST = 0x13, + DI_PT_QUADSTRIP = 0x14, + DI_PT_POLYGON = 0x15, + DI_PT_2D_COPY_RECT_LIST_V0 = 0x16, + DI_PT_2D_COPY_RECT_LIST_V1 = 0x17, + DI_PT_2D_COPY_RECT_LIST_V2 = 0x18, + DI_PT_2D_COPY_RECT_LIST_V3 = 0x19, + DI_PT_2D_FILL_RECT_LIST = 0x1a, + DI_PT_2D_LINE_STRIP = 0x1b, + DI_PT_2D_TRI_STRIP = 0x1c, + VGT_INDEX_TYPE = 0x0000895c, + INDEX_TYPE_mask = 0x03 << 0, + INDEX_TYPE_shift = 0, + DI_INDEX_SIZE_16_BIT = 0x00, + DI_INDEX_SIZE_32_BIT = 0x01, + VGT_STRMOUT_BUFFER_FILLED_SIZE_0 = 0x00008960, + VGT_STRMOUT_BUFFER_FILLED_SIZE_1 = 0x00008964, + VGT_STRMOUT_BUFFER_FILLED_SIZE_2 = 0x00008968, + VGT_STRMOUT_BUFFER_FILLED_SIZE_3 = 0x0000896c, + VGT_NUM_INDICES = 0x00008970, + VGT_NUM_INSTANCES = 0x00008974, + PA_CL_CNTL_STATUS = 0x00008a10, + CL_BUSY_bit = 1 << 31, + PA_CL_ENHANCE = 0x00008a14, + CLIP_VTX_REORDER_ENA_bit = 1 << 0, + NUM_CLIP_SEQ_mask = 0x03 << 1, + NUM_CLIP_SEQ_shift = 1, + CLIPPED_PRIM_SEQ_STALL_bit = 1 << 3, + VE_NAN_PROC_DISABLE_bit = 1 << 4, + PA_SU_CNTL_STATUS = 0x00008a50, + SU_BUSY_bit = 1 << 31, + PA_SC_LINE_STIPPLE_STATE = 0x00008b10, + CURRENT_PTR_mask = 0x0f << 0, + CURRENT_PTR_shift = 0, + CURRENT_COUNT_mask = 0xff << 8, + CURRENT_COUNT_shift = 8, + PA_SC_MULTI_CHIP_CNTL = 0x00008b20, + LOG2_NUM_CHIPS_mask = 0x07 << 0, + LOG2_NUM_CHIPS_shift = 0, + MULTI_CHIP_TILE_SIZE_mask = 0x03 << 3, + MULTI_CHIP_TILE_SIZE_shift = 3, + X_16_X_16_PIXEL_TILE_PER_CHIP = 0x00, + X_32_X_32_PIXEL_TILE_PER_CHIP = 0x01, + X_64_X_64_PIXEL_TILE_PER_CHIP = 0x02, + X_128X128_PIXEL_TILE_PER_CHIP = 0x03, + CHIP_TILE_X_LOC_mask = 0x07 << 5, + CHIP_TILE_X_LOC_shift = 5, + CHIP_TILE_Y_LOC_mask = 0x07 << 8, + CHIP_TILE_Y_LOC_shift = 8, + CHIP_SUPER_TILE_B_bit = 1 << 11, + PA_SC_AA_SAMPLE_LOCS_2S = 0x00008b40, + S0_X_mask = 0x0f << 0, + S0_X_shift = 0, + S0_Y_mask = 0x0f << 4, + S0_Y_shift = 4, + S1_X_mask = 0x0f << 8, + S1_X_shift = 8, + S1_Y_mask = 0x0f << 12, + S1_Y_shift = 12, + PA_SC_AA_SAMPLE_LOCS_4S = 0x00008b44, +/* S0_X_mask = 0x0f << 0, */ +/* S0_X_shift = 0, */ +/* S0_Y_mask = 0x0f << 4, */ +/* S0_Y_shift = 4, */ +/* S1_X_mask = 0x0f << 8, */ +/* S1_X_shift = 8, */ +/* S1_Y_mask = 0x0f << 12, */ +/* S1_Y_shift = 12, */ + S2_X_mask = 0x0f << 16, + S2_X_shift = 16, + S2_Y_mask = 0x0f << 20, + S2_Y_shift = 20, + S3_X_mask = 0x0f << 24, + S3_X_shift = 24, + S3_Y_mask = 0x0f << 28, + S3_Y_shift = 28, + PA_SC_AA_SAMPLE_LOCS_8S_WD0 = 0x00008b48, +/* S0_X_mask = 0x0f << 0, */ +/* S0_X_shift = 0, */ +/* S0_Y_mask = 0x0f << 4, */ +/* S0_Y_shift = 4, */ +/* S1_X_mask = 0x0f << 8, */ +/* S1_X_shift = 8, */ +/* S1_Y_mask = 0x0f << 12, */ +/* S1_Y_shift = 12, */ +/* S2_X_mask = 0x0f << 16, */ +/* S2_X_shift = 16, */ +/* S2_Y_mask = 0x0f << 20, */ +/* S2_Y_shift = 20, */ +/* S3_X_mask = 0x0f << 24, */ +/* S3_X_shift = 24, */ +/* S3_Y_mask = 0x0f << 28, */ +/* S3_Y_shift = 28, */ + PA_SC_AA_SAMPLE_LOCS_8S_WD1 = 0x00008b4c, + S4_X_mask = 0x0f << 0, + S4_X_shift = 0, + S4_Y_mask = 0x0f << 4, + S4_Y_shift = 4, + S5_X_mask = 0x0f << 8, + S5_X_shift = 8, + S5_Y_mask = 0x0f << 12, + S5_Y_shift = 12, + S6_X_mask = 0x0f << 16, + S6_X_shift = 16, + S6_Y_mask = 0x0f << 20, + S6_Y_shift = 20, + S7_X_mask = 0x0f << 24, + S7_X_shift = 24, + S7_Y_mask = 0x0f << 28, + S7_Y_shift = 28, + PA_SC_CNTL_STATUS = 0x00008be0, + MPASS_OVERFLOW_bit = 1 << 30, + PA_SC_ENHANCE = 0x00008bf0, + FORCE_EOV_MAX_CLK_CNT_mask = 0xfff << 0, + FORCE_EOV_MAX_CLK_CNT_shift = 0, + FORCE_EOV_MAX_TILE_CNT_mask = 0xfff << 12, + FORCE_EOV_MAX_TILE_CNT_shift = 12, + SQ_CONFIG = 0x00008c00, + VC_ENABLE_bit = 1 << 0, + EXPORT_SRC_C_bit = 1 << 1, + DX9_CONSTS_bit = 1 << 2, + ALU_INST_PREFER_VECTOR_bit = 1 << 3, + SQ_CONFIG__DX10_CLAMP_bit = 1 << 4, + ALU_PREFER_ONE_WATERFALL_bit = 1 << 5, + ALU_MAX_ONE_WATERFALL_bit = 1 << 6, + CLAUSE_SEQ_PRIO_mask = 0x03 << 8, + CLAUSE_SEQ_PRIO_shift = 8, + SQ_CL_PRIO_RND_ROBIN = 0x00, + SQ_CL_PRIO_MACRO_SEQ = 0x01, + SQ_CL_PRIO_NONE = 0x02, + PS_PRIO_mask = 0x03 << 24, + PS_PRIO_shift = 24, + VS_PRIO_mask = 0x03 << 26, + VS_PRIO_shift = 26, + GS_PRIO_mask = 0x03 << 28, + GS_PRIO_shift = 28, + ES_PRIO_mask = 0x03 << 30, + ES_PRIO_shift = 30, + SQ_GPR_RESOURCE_MGMT_1 = 0x00008c04, + NUM_PS_GPRS_mask = 0xff << 0, + NUM_PS_GPRS_shift = 0, + NUM_VS_GPRS_mask = 0xff << 16, + NUM_VS_GPRS_shift = 16, + NUM_CLAUSE_TEMP_GPRS_mask = 0x0f << 28, + NUM_CLAUSE_TEMP_GPRS_shift = 28, + SQ_GPR_RESOURCE_MGMT_2 = 0x00008c08, + NUM_GS_GPRS_mask = 0xff << 0, + NUM_GS_GPRS_shift = 0, + NUM_ES_GPRS_mask = 0xff << 16, + NUM_ES_GPRS_shift = 16, + SQ_THREAD_RESOURCE_MGMT = 0x00008c0c, + NUM_PS_THREADS_mask = 0xff << 0, + NUM_PS_THREADS_shift = 0, + NUM_VS_THREADS_mask = 0xff << 8, + NUM_VS_THREADS_shift = 8, + NUM_GS_THREADS_mask = 0xff << 16, + NUM_GS_THREADS_shift = 16, + NUM_ES_THREADS_mask = 0xff << 24, + NUM_ES_THREADS_shift = 24, + SQ_STACK_RESOURCE_MGMT_1 = 0x00008c10, + NUM_PS_STACK_ENTRIES_mask = 0xfff << 0, + NUM_PS_STACK_ENTRIES_shift = 0, + NUM_VS_STACK_ENTRIES_mask = 0xfff << 16, + NUM_VS_STACK_ENTRIES_shift = 16, + SQ_STACK_RESOURCE_MGMT_2 = 0x00008c14, + NUM_GS_STACK_ENTRIES_mask = 0xfff << 0, + NUM_GS_STACK_ENTRIES_shift = 0, + NUM_ES_STACK_ENTRIES_mask = 0xfff << 16, + NUM_ES_STACK_ENTRIES_shift = 16, + SQ_ESGS_RING_BASE = 0x00008c40, + SQ_ESGS_RING_SIZE = 0x00008c44, + SQ_GSVS_RING_BASE = 0x00008c48, + SQ_GSVS_RING_SIZE = 0x00008c4c, + SQ_ESTMP_RING_BASE = 0x00008c50, + SQ_ESTMP_RING_SIZE = 0x00008c54, + SQ_GSTMP_RING_BASE = 0x00008c58, + SQ_GSTMP_RING_SIZE = 0x00008c5c, + SQ_VSTMP_RING_BASE = 0x00008c60, + SQ_VSTMP_RING_SIZE = 0x00008c64, + SQ_PSTMP_RING_BASE = 0x00008c68, + SQ_PSTMP_RING_SIZE = 0x00008c6c, + SQ_FBUF_RING_BASE = 0x00008c70, + SQ_FBUF_RING_SIZE = 0x00008c74, + SQ_REDUC_RING_BASE = 0x00008c78, + SQ_REDUC_RING_SIZE = 0x00008c7c, + SQ_ALU_WORD1_OP3 = 0x00008dfc, + SRC2_SEL_mask = 0x1ff << 0, + SRC2_SEL_shift = 0, + SQ_ALU_SRC_0 = 0xf8, + SQ_ALU_SRC_1 = 0xf9, + SQ_ALU_SRC_1_INT = 0xfa, + SQ_ALU_SRC_M_1_INT = 0xfb, + SQ_ALU_SRC_0_5 = 0xfc, + SQ_ALU_SRC_LITERAL = 0xfd, + SQ_ALU_SRC_PV = 0xfe, + SQ_ALU_SRC_PS = 0xff, + SRC2_REL_bit = 1 << 9, + SRC2_CHAN_mask = 0x03 << 10, + SRC2_CHAN_shift = 10, + SQ_CHAN_X = 0x00, + SQ_CHAN_Y = 0x01, + SQ_CHAN_Z = 0x02, + SQ_CHAN_W = 0x03, + SRC2_NEG_bit = 1 << 12, + SQ_ALU_WORD1_OP3__ALU_INST_mask = 0x1f << 13, + SQ_ALU_WORD1_OP3__ALU_INST_shift = 13, + SQ_OP3_INST_MUL_LIT = 0x0c, + SQ_OP3_INST_MUL_LIT_M2 = 0x0d, + SQ_OP3_INST_MUL_LIT_M4 = 0x0e, + SQ_OP3_INST_MUL_LIT_D2 = 0x0f, + SQ_OP3_INST_MULADD = 0x10, + SQ_OP3_INST_MULADD_M2 = 0x11, + SQ_OP3_INST_MULADD_M4 = 0x12, + SQ_OP3_INST_MULADD_D2 = 0x13, + SQ_OP3_INST_MULADD_IEEE = 0x14, + SQ_OP3_INST_MULADD_IEEE_M2 = 0x15, + SQ_OP3_INST_MULADD_IEEE_M4 = 0x16, + SQ_OP3_INST_MULADD_IEEE_D2 = 0x17, + SQ_OP3_INST_CNDE = 0x18, + SQ_OP3_INST_CNDGT = 0x19, + SQ_OP3_INST_CNDGE = 0x1a, + SQ_OP3_INST_CNDE_INT = 0x1c, + SQ_OP3_INST_CNDGT_INT = 0x1d, + SQ_OP3_INST_CNDGE_INT = 0x1e, + SQ_TEX_WORD2 = 0x00008dfc, + OFFSET_X_mask = 0x1f << 0, + OFFSET_X_shift = 0, + OFFSET_Y_mask = 0x1f << 5, + OFFSET_Y_shift = 5, + OFFSET_Z_mask = 0x1f << 10, + OFFSET_Z_shift = 10, + SAMPLER_ID_mask = 0x1f << 15, + SAMPLER_ID_shift = 15, + SQ_TEX_WORD2__SRC_SEL_X_mask = 0x07 << 20, + SQ_TEX_WORD2__SRC_SEL_X_shift = 20, + SQ_SEL_X = 0x00, + SQ_SEL_Y = 0x01, + SQ_SEL_Z = 0x02, + SQ_SEL_W = 0x03, + SQ_SEL_0 = 0x04, + SQ_SEL_1 = 0x05, + SRC_SEL_Y_mask = 0x07 << 23, + SRC_SEL_Y_shift = 23, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ + SRC_SEL_Z_mask = 0x07 << 26, + SRC_SEL_Z_shift = 26, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ + SRC_SEL_W_mask = 0x07 << 29, + SRC_SEL_W_shift = 29, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ + SQ_CF_ALLOC_EXPORT_WORD1 = 0x00008dfc, + BURST_COUNT_mask = 0x0f << 17, + BURST_COUNT_shift = 17, + END_OF_PROGRAM_bit = 1 << 21, + VALID_PIXEL_MODE_bit = 1 << 22, + SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0x7f << 23, + SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_shift = 23, + SQ_CF_INST_MEM_STREAM0 = 0x20, + SQ_CF_INST_MEM_STREAM1 = 0x21, + SQ_CF_INST_MEM_STREAM2 = 0x22, + SQ_CF_INST_MEM_STREAM3 = 0x23, + SQ_CF_INST_MEM_SCRATCH = 0x24, + SQ_CF_INST_MEM_REDUCTION = 0x25, + SQ_CF_INST_MEM_RING = 0x26, + SQ_CF_INST_EXPORT = 0x27, + SQ_CF_INST_EXPORT_DONE = 0x28, + WHOLE_QUAD_MODE_bit = 1 << 30, + BARRIER_bit = 1 << 31, + SQ_CF_ALU_WORD1 = 0x00008dfc, + KCACHE_MODE1_mask = 0x03 << 0, + KCACHE_MODE1_shift = 0, + SQ_CF_KCACHE_NOP = 0x00, + SQ_CF_KCACHE_LOCK_1 = 0x01, + SQ_CF_KCACHE_LOCK_2 = 0x02, + SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, + KCACHE_ADDR0_mask = 0xff << 2, + KCACHE_ADDR0_shift = 2, + KCACHE_ADDR1_mask = 0xff << 10, + KCACHE_ADDR1_shift = 10, + SQ_CF_ALU_WORD1__COUNT_mask = 0x7f << 18, + SQ_CF_ALU_WORD1__COUNT_shift = 18, + SQ_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25, + SQ_CF_ALU_WORD1__CF_INST_mask = 0x0f << 26, + SQ_CF_ALU_WORD1__CF_INST_shift = 26, + SQ_CF_INST_ALU = 0x08, + SQ_CF_INST_ALU_PUSH_BEFORE = 0x09, + SQ_CF_INST_ALU_POP_AFTER = 0x0a, + SQ_CF_INST_ALU_POP2_AFTER = 0x0b, + SQ_CF_INST_ALU_CONTINUE = 0x0d, + SQ_CF_INST_ALU_BREAK = 0x0e, + SQ_CF_INST_ALU_ELSE_AFTER = 0x0f, +/* WHOLE_QUAD_MODE_bit = 1 << 30, */ +/* BARRIER_bit = 1 << 31, */ + SQ_TEX_WORD1 = 0x00008dfc, + SQ_TEX_WORD1__DST_GPR_mask = 0x7f << 0, + SQ_TEX_WORD1__DST_GPR_shift = 0, + SQ_TEX_WORD1__DST_REL_bit = 1 << 7, + SQ_TEX_WORD1__DST_SEL_X_mask = 0x07 << 9, + SQ_TEX_WORD1__DST_SEL_X_shift = 9, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ + SQ_SEL_MASK = 0x07, + SQ_TEX_WORD1__DST_SEL_Y_mask = 0x07 << 12, + SQ_TEX_WORD1__DST_SEL_Y_shift = 12, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + SQ_TEX_WORD1__DST_SEL_Z_mask = 0x07 << 15, + SQ_TEX_WORD1__DST_SEL_Z_shift = 15, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + SQ_TEX_WORD1__DST_SEL_W_mask = 0x07 << 18, + SQ_TEX_WORD1__DST_SEL_W_shift = 18, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + SQ_TEX_WORD1__LOD_BIAS_mask = 0x7f << 21, + SQ_TEX_WORD1__LOD_BIAS_shift = 21, + COORD_TYPE_X_bit = 1 << 28, + COORD_TYPE_Y_bit = 1 << 29, + COORD_TYPE_Z_bit = 1 << 30, + COORD_TYPE_W_bit = 1 << 31, + SQ_VTX_WORD0 = 0x00008dfc, + VTX_INST_mask = 0x1f << 0, + VTX_INST_shift = 0, + SQ_VTX_INST_FETCH = 0x00, + SQ_VTX_INST_SEMANTIC = 0x01, + FETCH_TYPE_mask = 0x03 << 5, + FETCH_TYPE_shift = 5, + SQ_VTX_FETCH_VERTEX_DATA = 0x00, + SQ_VTX_FETCH_INSTANCE_DATA = 0x01, + SQ_VTX_FETCH_NO_INDEX_OFFSET = 0x02, + FETCH_WHOLE_QUAD_bit = 1 << 7, + BUFFER_ID_mask = 0xff << 8, + BUFFER_ID_shift = 8, + SRC_GPR_mask = 0x7f << 16, + SRC_GPR_shift = 16, + SRC_REL_bit = 1 << 23, + SQ_VTX_WORD0__SRC_SEL_X_mask = 0x03 << 24, + SQ_VTX_WORD0__SRC_SEL_X_shift = 24, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ + MEGA_FETCH_COUNT_mask = 0x3f << 26, + MEGA_FETCH_COUNT_shift = 26, + SQ_CF_ALLOC_EXPORT_WORD1_SWIZ = 0x00008dfc, + SEL_X_mask = 0x07 << 0, + SEL_X_shift = 0, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + SEL_Y_mask = 0x07 << 3, + SEL_Y_shift = 3, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + SEL_Z_mask = 0x07 << 6, + SEL_Z_shift = 6, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + SEL_W_mask = 0x07 << 9, + SEL_W_shift = 9, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + SQ_ALU_WORD1 = 0x00008dfc, + ENCODING_mask = 0x07 << 15, + ENCODING_shift = 15, + BANK_SWIZZLE_mask = 0x07 << 18, + BANK_SWIZZLE_shift = 18, + SQ_ALU_VEC_012 = 0x00, + SQ_ALU_VEC_021 = 0x01, + SQ_ALU_VEC_120 = 0x02, + SQ_ALU_VEC_102 = 0x03, + SQ_ALU_VEC_201 = 0x04, + SQ_ALU_VEC_210 = 0x05, + SQ_ALU_WORD1__DST_GPR_mask = 0x7f << 21, + SQ_ALU_WORD1__DST_GPR_shift = 21, + SQ_ALU_WORD1__DST_REL_bit = 1 << 28, + DST_CHAN_mask = 0x03 << 29, + DST_CHAN_shift = 29, + CHAN_X = 0x00, + CHAN_Y = 0x01, + CHAN_Z = 0x02, + CHAN_W = 0x03, + SQ_ALU_WORD1__CLAMP_bit = 1 << 31, + SQ_CF_ALU_WORD0 = 0x00008dfc, + SQ_CF_ALU_WORD0__ADDR_mask = 0x3fffff << 0, + SQ_CF_ALU_WORD0__ADDR_shift = 0, + KCACHE_BANK0_mask = 0x0f << 22, + KCACHE_BANK0_shift = 22, + KCACHE_BANK1_mask = 0x0f << 26, + KCACHE_BANK1_shift = 26, + KCACHE_MODE0_mask = 0x03 << 30, + KCACHE_MODE0_shift = 30, +/* SQ_CF_KCACHE_NOP = 0x00, */ +/* SQ_CF_KCACHE_LOCK_1 = 0x01, */ +/* SQ_CF_KCACHE_LOCK_2 = 0x02, */ +/* SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, */ + SQ_VTX_WORD2 = 0x00008dfc, + SQ_VTX_WORD2__OFFSET_mask = 0xffff << 0, + SQ_VTX_WORD2__OFFSET_shift = 0, + SQ_VTX_WORD2__ENDIAN_SWAP_mask = 0x03 << 16, + SQ_VTX_WORD2__ENDIAN_SWAP_shift = 16, + SQ_ENDIAN_NONE = 0x00, + SQ_ENDIAN_8IN16 = 0x01, + SQ_ENDIAN_8IN32 = 0x02, + CONST_BUF_NO_STRIDE_bit = 1 << 18, + MEGA_FETCH_bit = 1 << 19, + SQ_VTX_WORD2__ALT_CONST_bit = 1 << 20, + SQ_ALU_WORD1_OP2_V2 = 0x00008dfc, + SRC0_ABS_bit = 1 << 0, + SRC1_ABS_bit = 1 << 1, + UPDATE_EXECUTE_MASK_bit = 1 << 2, + UPDATE_PRED_bit = 1 << 3, + WRITE_MASK_bit = 1 << 4, + SQ_ALU_WORD1_OP2_V2__OMOD_mask = 0x03 << 5, + SQ_ALU_WORD1_OP2_V2__OMOD_shift = 5, + SQ_ALU_OMOD_OFF = 0x00, + SQ_ALU_OMOD_M2 = 0x01, + SQ_ALU_OMOD_M4 = 0x02, + SQ_ALU_OMOD_D2 = 0x03, + SQ_ALU_WORD1_OP2_V2__ALU_INST_mask = 0x7ff << 7, + SQ_ALU_WORD1_OP2_V2__ALU_INST_shift = 7, + SQ_OP2_INST_ADD = 0x00, + SQ_OP2_INST_MUL = 0x01, + SQ_OP2_INST_MUL_IEEE = 0x02, + SQ_OP2_INST_MAX = 0x03, + SQ_OP2_INST_MIN = 0x04, + SQ_OP2_INST_MAX_DX10 = 0x05, + SQ_OP2_INST_MIN_DX10 = 0x06, + SQ_OP2_INST_SETE = 0x08, + SQ_OP2_INST_SETGT = 0x09, + SQ_OP2_INST_SETGE = 0x0a, + SQ_OP2_INST_SETNE = 0x0b, + SQ_OP2_INST_SETE_DX10 = 0x0c, + SQ_OP2_INST_SETGT_DX10 = 0x0d, + SQ_OP2_INST_SETGE_DX10 = 0x0e, + SQ_OP2_INST_SETNE_DX10 = 0x0f, + SQ_OP2_INST_FRACT = 0x10, + SQ_OP2_INST_TRUNC = 0x11, + SQ_OP2_INST_CEIL = 0x12, + SQ_OP2_INST_RNDNE = 0x13, + SQ_OP2_INST_FLOOR = 0x14, + SQ_OP2_INST_MOVA = 0x15, + SQ_OP2_INST_MOVA_FLOOR = 0x16, + SQ_OP2_INST_MOVA_INT = 0x18, + SQ_OP2_INST_MOV = 0x19, + SQ_OP2_INST_NOP = 0x1a, + SQ_OP2_INST_PRED_SETGT_UINT = 0x1e, + SQ_OP2_INST_PRED_SETGE_UINT = 0x1f, + SQ_OP2_INST_PRED_SETE = 0x20, + SQ_OP2_INST_PRED_SETGT = 0x21, + SQ_OP2_INST_PRED_SETGE = 0x22, + SQ_OP2_INST_PRED_SETNE = 0x23, + SQ_OP2_INST_PRED_SET_INV = 0x24, + SQ_OP2_INST_PRED_SET_POP = 0x25, + SQ_OP2_INST_PRED_SET_CLR = 0x26, + SQ_OP2_INST_PRED_SET_RESTORE = 0x27, + SQ_OP2_INST_PRED_SETE_PUSH = 0x28, + SQ_OP2_INST_PRED_SETGT_PUSH = 0x29, + SQ_OP2_INST_PRED_SETGE_PUSH = 0x2a, + SQ_OP2_INST_PRED_SETNE_PUSH = 0x2b, + SQ_OP2_INST_KILLE = 0x2c, + SQ_OP2_INST_KILLGT = 0x2d, + SQ_OP2_INST_KILLGE = 0x2e, + SQ_OP2_INST_KILLNE = 0x2f, + SQ_OP2_INST_AND_INT = 0x30, + SQ_OP2_INST_OR_INT = 0x31, + SQ_OP2_INST_XOR_INT = 0x32, + SQ_OP2_INST_NOT_INT = 0x33, + SQ_OP2_INST_ADD_INT = 0x34, + SQ_OP2_INST_SUB_INT = 0x35, + SQ_OP2_INST_MAX_INT = 0x36, + SQ_OP2_INST_MIN_INT = 0x37, + SQ_OP2_INST_MAX_UINT = 0x38, + SQ_OP2_INST_MIN_UINT = 0x39, + SQ_OP2_INST_SETE_INT = 0x3a, + SQ_OP2_INST_SETGT_INT = 0x3b, + SQ_OP2_INST_SETGE_INT = 0x3c, + SQ_OP2_INST_SETNE_INT = 0x3d, + SQ_OP2_INST_SETGT_UINT = 0x3e, + SQ_OP2_INST_SETGE_UINT = 0x3f, + SQ_OP2_INST_KILLGT_UINT = 0x40, + SQ_OP2_INST_KILLGE_UINT = 0x41, + SQ_OP2_INST_PRED_SETE_INT = 0x42, + SQ_OP2_INST_PRED_SETGT_INT = 0x43, + SQ_OP2_INST_PRED_SETGE_INT = 0x44, + SQ_OP2_INST_PRED_SETNE_INT = 0x45, + SQ_OP2_INST_KILLE_INT = 0x46, + SQ_OP2_INST_KILLGT_INT = 0x47, + SQ_OP2_INST_KILLGE_INT = 0x48, + SQ_OP2_INST_KILLNE_INT = 0x49, + SQ_OP2_INST_PRED_SETE_PUSH_INT = 0x4a, + SQ_OP2_INST_PRED_SETGT_PUSH_INT = 0x4b, + SQ_OP2_INST_PRED_SETGE_PUSH_INT = 0x4c, + SQ_OP2_INST_PRED_SETNE_PUSH_INT = 0x4d, + SQ_OP2_INST_PRED_SETLT_PUSH_INT = 0x4e, + SQ_OP2_INST_PRED_SETLE_PUSH_INT = 0x4f, + SQ_OP2_INST_DOT4 = 0x50, + SQ_OP2_INST_DOT4_IEEE = 0x51, + SQ_OP2_INST_CUBE = 0x52, + SQ_OP2_INST_MAX4 = 0x53, + SQ_OP2_INST_MOVA_GPR_INT = 0x60, + SQ_OP2_INST_EXP_IEEE = 0x61, + SQ_OP2_INST_LOG_CLAMPED = 0x62, + SQ_OP2_INST_LOG_IEEE = 0x63, + SQ_OP2_INST_RECIP_CLAMPED = 0x64, + SQ_OP2_INST_RECIP_FF = 0x65, + SQ_OP2_INST_RECIP_IEEE = 0x66, + SQ_OP2_INST_RECIPSQRT_CLAMPED = 0x67, + SQ_OP2_INST_RECIPSQRT_FF = 0x68, + SQ_OP2_INST_RECIPSQRT_IEEE = 0x69, + SQ_OP2_INST_SQRT_IEEE = 0x6a, + SQ_OP2_INST_FLT_TO_INT = 0x6b, + SQ_OP2_INST_INT_TO_FLT = 0x6c, + SQ_OP2_INST_UINT_TO_FLT = 0x6d, + SQ_OP2_INST_SIN = 0x6e, + SQ_OP2_INST_COS = 0x6f, + SQ_OP2_INST_ASHR_INT = 0x70, + SQ_OP2_INST_LSHR_INT = 0x71, + SQ_OP2_INST_LSHL_INT = 0x72, + SQ_OP2_INST_MULLO_INT = 0x73, + SQ_OP2_INST_MULHI_INT = 0x74, + SQ_OP2_INST_MULLO_UINT = 0x75, + SQ_OP2_INST_MULHI_UINT = 0x76, + SQ_OP2_INST_RECIP_INT = 0x77, + SQ_OP2_INST_RECIP_UINT = 0x78, + SQ_OP2_INST_FLT_TO_UINT = 0x79, + SQ_CF_ALLOC_EXPORT_WORD1_BUF = 0x00008dfc, + ARRAY_SIZE_mask = 0xfff << 0, + ARRAY_SIZE_shift = 0, + COMP_MASK_mask = 0x0f << 12, + COMP_MASK_shift = 12, + SQ_CF_WORD0 = 0x00008dfc, + SQ_CF_ALLOC_EXPORT_WORD0 = 0x00008dfc, + ARRAY_BASE_mask = 0x1fff << 0, + ARRAY_BASE_shift = 0, + SQ_CF_ALLOC_EXPORT_WORD0__TYPE_mask = 0x03 << 13, + SQ_CF_ALLOC_EXPORT_WORD0__TYPE_shift = 13, + SQ_EXPORT_PIXEL = 0x00, + SQ_EXPORT_POS = 0x01, + SQ_EXPORT_PARAM = 0x02, + X_UNUSED_FOR_SX_EXPORTS = 0x03, + RW_GPR_mask = 0x7f << 15, + RW_GPR_shift = 15, + RW_REL_bit = 1 << 22, + INDEX_GPR_mask = 0x7f << 23, + INDEX_GPR_shift = 23, + ELEM_SIZE_mask = 0x03 << 30, + ELEM_SIZE_shift = 30, + SQ_VTX_WORD1 = 0x00008dfc, + SQ_VTX_WORD1__DST_SEL_X_mask = 0x07 << 9, + SQ_VTX_WORD1__DST_SEL_X_shift = 9, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + SQ_VTX_WORD1__DST_SEL_Y_mask = 0x07 << 12, + SQ_VTX_WORD1__DST_SEL_Y_shift = 12, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + SQ_VTX_WORD1__DST_SEL_Z_mask = 0x07 << 15, + SQ_VTX_WORD1__DST_SEL_Z_shift = 15, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + SQ_VTX_WORD1__DST_SEL_W_mask = 0x07 << 18, + SQ_VTX_WORD1__DST_SEL_W_shift = 18, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ +/* SQ_SEL_MASK = 0x07, */ + USE_CONST_FIELDS_bit = 1 << 21, + SQ_VTX_WORD1__DATA_FORMAT_mask = 0x3f << 22, + SQ_VTX_WORD1__DATA_FORMAT_shift = 22, + SQ_VTX_WORD1__NUM_FORMAT_ALL_mask = 0x03 << 28, + SQ_VTX_WORD1__NUM_FORMAT_ALL_shift = 28, + SQ_NUM_FORMAT_NORM = 0x00, + SQ_NUM_FORMAT_INT = 0x01, + SQ_NUM_FORMAT_SCALED = 0x02, + SQ_VTX_WORD1__FORMAT_COMP_ALL_bit = 1 << 30, + SQ_VTX_WORD1__SRF_MODE_ALL_bit = 1 << 31, + SQ_ALU_WORD1_OP2 = 0x00008dfc, +/* SRC0_ABS_bit = 1 << 0, */ +/* SRC1_ABS_bit = 1 << 1, */ +/* UPDATE_EXECUTE_MASK_bit = 1 << 2, */ +/* UPDATE_PRED_bit = 1 << 3, */ +/* WRITE_MASK_bit = 1 << 4, */ + FOG_MERGE_bit = 1 << 5, + SQ_ALU_WORD1_OP2__OMOD_mask = 0x03 << 6, + SQ_ALU_WORD1_OP2__OMOD_shift = 6, +/* SQ_ALU_OMOD_OFF = 0x00, */ +/* SQ_ALU_OMOD_M2 = 0x01, */ +/* SQ_ALU_OMOD_M4 = 0x02, */ +/* SQ_ALU_OMOD_D2 = 0x03, */ + SQ_ALU_WORD1_OP2__ALU_INST_mask = 0x3ff << 8, + SQ_ALU_WORD1_OP2__ALU_INST_shift = 8, +/* SQ_OP2_INST_ADD = 0x00, */ +/* SQ_OP2_INST_MUL = 0x01, */ +/* SQ_OP2_INST_MUL_IEEE = 0x02, */ +/* SQ_OP2_INST_MAX = 0x03, */ +/* SQ_OP2_INST_MIN = 0x04, */ +/* SQ_OP2_INST_MAX_DX10 = 0x05, */ +/* SQ_OP2_INST_MIN_DX10 = 0x06, */ +/* SQ_OP2_INST_SETE = 0x08, */ +/* SQ_OP2_INST_SETGT = 0x09, */ +/* SQ_OP2_INST_SETGE = 0x0a, */ +/* SQ_OP2_INST_SETNE = 0x0b, */ +/* SQ_OP2_INST_SETE_DX10 = 0x0c, */ +/* SQ_OP2_INST_SETGT_DX10 = 0x0d, */ +/* SQ_OP2_INST_SETGE_DX10 = 0x0e, */ +/* SQ_OP2_INST_SETNE_DX10 = 0x0f, */ +/* SQ_OP2_INST_FRACT = 0x10, */ +/* SQ_OP2_INST_TRUNC = 0x11, */ +/* SQ_OP2_INST_CEIL = 0x12, */ +/* SQ_OP2_INST_RNDNE = 0x13, */ +/* SQ_OP2_INST_FLOOR = 0x14, */ +/* SQ_OP2_INST_MOVA = 0x15, */ +/* SQ_OP2_INST_MOVA_FLOOR = 0x16, */ +/* SQ_OP2_INST_MOVA_INT = 0x18, */ +/* SQ_OP2_INST_MOV = 0x19, */ +/* SQ_OP2_INST_NOP = 0x1a, */ +/* SQ_OP2_INST_PRED_SETGT_UINT = 0x1e, */ +/* SQ_OP2_INST_PRED_SETGE_UINT = 0x1f, */ +/* SQ_OP2_INST_PRED_SETE = 0x20, */ +/* SQ_OP2_INST_PRED_SETGT = 0x21, */ +/* SQ_OP2_INST_PRED_SETGE = 0x22, */ +/* SQ_OP2_INST_PRED_SETNE = 0x23, */ +/* SQ_OP2_INST_PRED_SET_INV = 0x24, */ +/* SQ_OP2_INST_PRED_SET_POP = 0x25, */ +/* SQ_OP2_INST_PRED_SET_CLR = 0x26, */ +/* SQ_OP2_INST_PRED_SET_RESTORE = 0x27, */ +/* SQ_OP2_INST_PRED_SETE_PUSH = 0x28, */ +/* SQ_OP2_INST_PRED_SETGT_PUSH = 0x29, */ +/* SQ_OP2_INST_PRED_SETGE_PUSH = 0x2a, */ +/* SQ_OP2_INST_PRED_SETNE_PUSH = 0x2b, */ +/* SQ_OP2_INST_KILLE = 0x2c, */ +/* SQ_OP2_INST_KILLGT = 0x2d, */ +/* SQ_OP2_INST_KILLGE = 0x2e, */ +/* SQ_OP2_INST_KILLNE = 0x2f, */ +/* SQ_OP2_INST_AND_INT = 0x30, */ +/* SQ_OP2_INST_OR_INT = 0x31, */ +/* SQ_OP2_INST_XOR_INT = 0x32, */ +/* SQ_OP2_INST_NOT_INT = 0x33, */ +/* SQ_OP2_INST_ADD_INT = 0x34, */ +/* SQ_OP2_INST_SUB_INT = 0x35, */ +/* SQ_OP2_INST_MAX_INT = 0x36, */ +/* SQ_OP2_INST_MIN_INT = 0x37, */ +/* SQ_OP2_INST_MAX_UINT = 0x38, */ +/* SQ_OP2_INST_MIN_UINT = 0x39, */ +/* SQ_OP2_INST_SETE_INT = 0x3a, */ +/* SQ_OP2_INST_SETGT_INT = 0x3b, */ +/* SQ_OP2_INST_SETGE_INT = 0x3c, */ +/* SQ_OP2_INST_SETNE_INT = 0x3d, */ +/* SQ_OP2_INST_SETGT_UINT = 0x3e, */ +/* SQ_OP2_INST_SETGE_UINT = 0x3f, */ +/* SQ_OP2_INST_KILLGT_UINT = 0x40, */ +/* SQ_OP2_INST_KILLGE_UINT = 0x41, */ +/* SQ_OP2_INST_PRED_SETE_INT = 0x42, */ +/* SQ_OP2_INST_PRED_SETGT_INT = 0x43, */ +/* SQ_OP2_INST_PRED_SETGE_INT = 0x44, */ +/* SQ_OP2_INST_PRED_SETNE_INT = 0x45, */ +/* SQ_OP2_INST_KILLE_INT = 0x46, */ +/* SQ_OP2_INST_KILLGT_INT = 0x47, */ +/* SQ_OP2_INST_KILLGE_INT = 0x48, */ +/* SQ_OP2_INST_KILLNE_INT = 0x49, */ +/* SQ_OP2_INST_PRED_SETE_PUSH_INT = 0x4a, */ +/* SQ_OP2_INST_PRED_SETGT_PUSH_INT = 0x4b, */ +/* SQ_OP2_INST_PRED_SETGE_PUSH_INT = 0x4c, */ +/* SQ_OP2_INST_PRED_SETNE_PUSH_INT = 0x4d, */ +/* SQ_OP2_INST_PRED_SETLT_PUSH_INT = 0x4e, */ +/* SQ_OP2_INST_PRED_SETLE_PUSH_INT = 0x4f, */ +/* SQ_OP2_INST_DOT4 = 0x50, */ +/* SQ_OP2_INST_DOT4_IEEE = 0x51, */ +/* SQ_OP2_INST_CUBE = 0x52, */ +/* SQ_OP2_INST_MAX4 = 0x53, */ +/* SQ_OP2_INST_MOVA_GPR_INT = 0x60, */ +/* SQ_OP2_INST_EXP_IEEE = 0x61, */ +/* SQ_OP2_INST_LOG_CLAMPED = 0x62, */ +/* SQ_OP2_INST_LOG_IEEE = 0x63, */ +/* SQ_OP2_INST_RECIP_CLAMPED = 0x64, */ +/* SQ_OP2_INST_RECIP_FF = 0x65, */ +/* SQ_OP2_INST_RECIP_IEEE = 0x66, */ +/* SQ_OP2_INST_RECIPSQRT_CLAMPED = 0x67, */ +/* SQ_OP2_INST_RECIPSQRT_FF = 0x68, */ +/* SQ_OP2_INST_RECIPSQRT_IEEE = 0x69, */ +/* SQ_OP2_INST_SQRT_IEEE = 0x6a, */ +/* SQ_OP2_INST_FLT_TO_INT = 0x6b, */ +/* SQ_OP2_INST_INT_TO_FLT = 0x6c, */ +/* SQ_OP2_INST_UINT_TO_FLT = 0x6d, */ +/* SQ_OP2_INST_SIN = 0x6e, */ +/* SQ_OP2_INST_COS = 0x6f, */ +/* SQ_OP2_INST_ASHR_INT = 0x70, */ +/* SQ_OP2_INST_LSHR_INT = 0x71, */ +/* SQ_OP2_INST_LSHL_INT = 0x72, */ +/* SQ_OP2_INST_MULLO_INT = 0x73, */ +/* SQ_OP2_INST_MULHI_INT = 0x74, */ +/* SQ_OP2_INST_MULLO_UINT = 0x75, */ +/* SQ_OP2_INST_MULHI_UINT = 0x76, */ +/* SQ_OP2_INST_RECIP_INT = 0x77, */ +/* SQ_OP2_INST_RECIP_UINT = 0x78, */ +/* SQ_OP2_INST_FLT_TO_UINT = 0x79, */ + SQ_CF_WORD1 = 0x00008dfc, + POP_COUNT_mask = 0x07 << 0, + POP_COUNT_shift = 0, + CF_CONST_mask = 0x1f << 3, + CF_CONST_shift = 3, + COND_mask = 0x03 << 8, + COND_shift = 8, + SQ_CF_COND_ACTIVE = 0x00, + SQ_CF_COND_FALSE = 0x01, + SQ_CF_COND_BOOL = 0x02, + SQ_CF_COND_NOT_BOOL = 0x03, + SQ_CF_WORD1__COUNT_mask = 0x07 << 10, + SQ_CF_WORD1__COUNT_shift = 10, + CALL_COUNT_mask = 0x3f << 13, + CALL_COUNT_shift = 13, + COUNT_3_bit = 1 << 19, +/* END_OF_PROGRAM_bit = 1 << 21, */ +/* VALID_PIXEL_MODE_bit = 1 << 22, */ + SQ_CF_WORD1__CF_INST_mask = 0x7f << 23, + SQ_CF_WORD1__CF_INST_shift = 23, + SQ_CF_INST_NOP = 0x00, + SQ_CF_INST_TEX = 0x01, + SQ_CF_INST_VTX = 0x02, + SQ_CF_INST_VTX_TC = 0x03, + SQ_CF_INST_LOOP_START = 0x04, + SQ_CF_INST_LOOP_END = 0x05, + SQ_CF_INST_LOOP_START_DX10 = 0x06, + SQ_CF_INST_LOOP_START_NO_AL = 0x07, + SQ_CF_INST_LOOP_CONTINUE = 0x08, + SQ_CF_INST_LOOP_BREAK = 0x09, + SQ_CF_INST_JUMP = 0x0a, + SQ_CF_INST_PUSH = 0x0b, + SQ_CF_INST_PUSH_ELSE = 0x0c, + SQ_CF_INST_ELSE = 0x0d, + SQ_CF_INST_POP = 0x0e, + SQ_CF_INST_POP_JUMP = 0x0f, + SQ_CF_INST_POP_PUSH = 0x10, + SQ_CF_INST_POP_PUSH_ELSE = 0x11, + SQ_CF_INST_CALL = 0x12, + SQ_CF_INST_CALL_FS = 0x13, + SQ_CF_INST_RETURN = 0x14, + SQ_CF_INST_EMIT_VERTEX = 0x15, + SQ_CF_INST_EMIT_CUT_VERTEX = 0x16, + SQ_CF_INST_CUT_VERTEX = 0x17, + SQ_CF_INST_KILL = 0x18, +/* WHOLE_QUAD_MODE_bit = 1 << 30, */ +/* BARRIER_bit = 1 << 31, */ + SQ_VTX_WORD1_SEM = 0x00008dfc, + SEMANTIC_ID_mask = 0xff << 0, + SEMANTIC_ID_shift = 0, + SQ_TEX_WORD0 = 0x00008dfc, + TEX_INST_mask = 0x1f << 0, + TEX_INST_shift = 0, + SQ_TEX_INST_VTX_FETCH = 0x00, + SQ_TEX_INST_VTX_SEMANTIC = 0x01, + SQ_TEX_INST_LD = 0x03, + SQ_TEX_INST_GET_TEXTURE_RESINFO = 0x04, + SQ_TEX_INST_GET_NUMBER_OF_SAMPLES = 0x05, + SQ_TEX_INST_GET_LOD = 0x06, + SQ_TEX_INST_GET_GRADIENTS_H = 0x07, + SQ_TEX_INST_GET_GRADIENTS_V = 0x08, + SQ_TEX_INST_GET_LERP = 0x09, + SQ_TEX_INST_RESERVED_10 = 0x0a, + SQ_TEX_INST_SET_GRADIENTS_H = 0x0b, + SQ_TEX_INST_SET_GRADIENTS_V = 0x0c, + SQ_TEX_INST_PASS = 0x0d, + X_Z_SET_INDEX_FOR_ARRAY_OF_CUBEMAPS = 0x0e, + SQ_TEX_INST_SAMPLE = 0x10, + SQ_TEX_INST_SAMPLE_L = 0x11, + SQ_TEX_INST_SAMPLE_LB = 0x12, + SQ_TEX_INST_SAMPLE_LZ = 0x13, + SQ_TEX_INST_SAMPLE_G = 0x14, + SQ_TEX_INST_SAMPLE_G_L = 0x15, + SQ_TEX_INST_SAMPLE_G_LB = 0x16, + SQ_TEX_INST_SAMPLE_G_LZ = 0x17, + SQ_TEX_INST_SAMPLE_C = 0x18, + SQ_TEX_INST_SAMPLE_C_L = 0x19, + SQ_TEX_INST_SAMPLE_C_LB = 0x1a, + SQ_TEX_INST_SAMPLE_C_LZ = 0x1b, + SQ_TEX_INST_SAMPLE_C_G = 0x1c, + SQ_TEX_INST_SAMPLE_C_G_L = 0x1d, + SQ_TEX_INST_SAMPLE_C_G_LB = 0x1e, + SQ_TEX_INST_SAMPLE_C_G_LZ = 0x1f, + BC_FRAC_MODE_bit = 1 << 5, +/* FETCH_WHOLE_QUAD_bit = 1 << 7, */ + RESOURCE_ID_mask = 0xff << 8, + RESOURCE_ID_shift = 8, +/* SRC_GPR_mask = 0x7f << 16, */ +/* SRC_GPR_shift = 16, */ +/* SRC_REL_bit = 1 << 23, */ + SQ_TEX_WORD0__ALT_CONST_bit = 1 << 24, + SQ_VTX_WORD1_GPR = 0x00008dfc, + SQ_VTX_WORD1_GPR__DST_GPR_mask = 0x7f << 0, + SQ_VTX_WORD1_GPR__DST_GPR_shift = 0, + SQ_VTX_WORD1_GPR__DST_REL_bit = 1 << 7, + SQ_ALU_WORD0 = 0x00008dfc, + SRC0_SEL_mask = 0x1ff << 0, + SRC0_SEL_shift = 0, +/* SQ_ALU_SRC_0 = 0xf8, */ +/* SQ_ALU_SRC_1 = 0xf9, */ +/* SQ_ALU_SRC_1_INT = 0xfa, */ +/* SQ_ALU_SRC_M_1_INT = 0xfb, */ +/* SQ_ALU_SRC_0_5 = 0xfc, */ +/* SQ_ALU_SRC_LITERAL = 0xfd, */ +/* SQ_ALU_SRC_PV = 0xfe, */ +/* SQ_ALU_SRC_PS = 0xff, */ + SRC0_REL_bit = 1 << 9, + SRC0_CHAN_mask = 0x03 << 10, + SRC0_CHAN_shift = 10, +/* SQ_CHAN_X = 0x00, */ +/* SQ_CHAN_Y = 0x01, */ +/* SQ_CHAN_Z = 0x02, */ +/* SQ_CHAN_W = 0x03, */ + SRC0_NEG_bit = 1 << 12, + SRC1_SEL_mask = 0x1ff << 13, + SRC1_SEL_shift = 13, +/* SQ_ALU_SRC_0 = 0xf8, */ +/* SQ_ALU_SRC_1 = 0xf9, */ +/* SQ_ALU_SRC_1_INT = 0xfa, */ +/* SQ_ALU_SRC_M_1_INT = 0xfb, */ +/* SQ_ALU_SRC_0_5 = 0xfc, */ +/* SQ_ALU_SRC_LITERAL = 0xfd, */ +/* SQ_ALU_SRC_PV = 0xfe, */ +/* SQ_ALU_SRC_PS = 0xff, */ + SRC1_REL_bit = 1 << 22, + SRC1_CHAN_mask = 0x03 << 23, + SRC1_CHAN_shift = 23, +/* SQ_CHAN_X = 0x00, */ +/* SQ_CHAN_Y = 0x01, */ +/* SQ_CHAN_Z = 0x02, */ +/* SQ_CHAN_W = 0x03, */ + SRC1_NEG_bit = 1 << 25, + INDEX_MODE_mask = 0x07 << 26, + INDEX_MODE_shift = 26, + SQ_INDEX_AR_X = 0x00, + SQ_INDEX_AR_Y = 0x01, + SQ_INDEX_AR_Z = 0x02, + SQ_INDEX_AR_W = 0x03, + SQ_INDEX_LOOP = 0x04, + PRED_SEL_mask = 0x03 << 29, + PRED_SEL_shift = 29, + SQ_PRED_SEL_OFF = 0x00, + SQ_PRED_SEL_ZERO = 0x02, + SQ_PRED_SEL_ONE = 0x03, + LAST_bit = 1 << 31, + SX_EXPORT_BUFFER_SIZES = 0x0000900c, + COLOR_BUFFER_SIZE_mask = 0xff << 0, + COLOR_BUFFER_SIZE_shift = 0, + POSITION_BUFFER_SIZE_mask = 0xff << 8, + POSITION_BUFFER_SIZE_shift = 8, + SMX_BUFFER_SIZE_mask = 0xff << 16, + SMX_BUFFER_SIZE_shift = 16, + SX_MEMORY_EXPORT_BASE = 0x00009010, + SX_MEMORY_EXPORT_SIZE = 0x00009014, + SPI_CONFIG_CNTL = 0x00009100, + GPR_WRITE_PRIORITY_mask = 0x1f << 0, + GPR_WRITE_PRIORITY_shift = 0, + X_PRIORITY_ORDER = 0x00, + X_PRIORITY_ORDER_VS = 0x01, + DISABLE_INTERP_1_bit = 1 << 5, + DEBUG_THREAD_TYPE_SEL_mask = 0x03 << 6, + DEBUG_THREAD_TYPE_SEL_shift = 6, + DEBUG_GROUP_SEL_mask = 0x1f << 8, + DEBUG_GROUP_SEL_shift = 8, + DEBUG_GRBM_OVERRIDE_bit = 1 << 13, + SPI_CONFIG_CNTL_1 = 0x0000913c, + VTX_DONE_DELAY_mask = 0x0f << 0, + VTX_DONE_DELAY_shift = 0, + X_DELAY_10_CLKS = 0x00, + X_DELAY_11_CLKS = 0x01, + X_DELAY_12_CLKS = 0x02, + X_DELAY_13_CLKS = 0x03, + X_DELAY_14_CLKS = 0x04, + X_DELAY_15_CLKS = 0x05, + X_DELAY_16_CLKS = 0x06, + X_DELAY_17_CLKS = 0x07, + X_DELAY_2_CLKS = 0x08, + X_DELAY_3_CLKS = 0x09, + X_DELAY_4_CLKS = 0x0a, + X_DELAY_5_CLKS = 0x0b, + X_DELAY_6_CLKS = 0x0c, + X_DELAY_7_CLKS = 0x0d, + X_DELAY_8_CLKS = 0x0e, + X_DELAY_9_CLKS = 0x0f, + INTERP_ONE_PRIM_PER_ROW_bit = 1 << 4, + TD_FILTER4 = 0x00009400, + WEIGHT_1_mask = 0x7ff << 0, + WEIGHT_1_shift = 0, + WEIGHT_0_mask = 0x7ff << 11, + WEIGHT_0_shift = 11, + WEIGHT_PAIR_bit = 1 << 22, + PHASE_mask = 0x0f << 23, + PHASE_shift = 23, + DIRECTION_bit = 1 << 27, + TD_FILTER4_1 = 0x00009404, + TD_FILTER4_1_num = 35, +/* WEIGHT_1_mask = 0x7ff << 0, */ +/* WEIGHT_1_shift = 0, */ +/* WEIGHT_0_mask = 0x7ff << 11, */ +/* WEIGHT_0_shift = 11, */ + TD_CNTL = 0x00009490, + SYNC_PHASE_SH_mask = 0x03 << 0, + SYNC_PHASE_SH_shift = 0, + SYNC_PHASE_VC_SMX_mask = 0x03 << 4, + SYNC_PHASE_VC_SMX_shift = 4, + TD0_CNTL = 0x00009494, + TD0_CNTL_num = 4, + ID_OVERRIDE_mask = 0x03 << 28, + ID_OVERRIDE_shift = 28, + TD0_STATUS = 0x000094a4, + TD0_STATUS_num = 4, + BUSY_bit = 1 << 31, + TA_CNTL = 0x00009504, + GRADIENT_CREDIT_mask = 0x1f << 0, + GRADIENT_CREDIT_shift = 0, + WALKER_CREDIT_mask = 0x1f << 8, + WALKER_CREDIT_shift = 8, + ALIGNER_CREDIT_mask = 0x1f << 16, + ALIGNER_CREDIT_shift = 16, + TD_FIFO_CREDIT_mask = 0x3ff << 22, + TD_FIFO_CREDIT_shift = 22, + TA_CNTL_AUX = 0x00009508, + DISABLE_CUBE_WRAP_bit = 1 << 0, + SYNC_GRADIENT_bit = 1 << 24, + SYNC_WALKER_bit = 1 << 25, + SYNC_ALIGNER_bit = 1 << 26, + BILINEAR_PRECISION_bit = 1 << 31, + TA0_CNTL = 0x00009510, +/* ID_OVERRIDE_mask = 0x03 << 28, */ +/* ID_OVERRIDE_shift = 28, */ + TA1_CNTL = 0x00009514, +/* ID_OVERRIDE_mask = 0x03 << 28, */ +/* ID_OVERRIDE_shift = 28, */ + TA2_CNTL = 0x00009518, +/* ID_OVERRIDE_mask = 0x03 << 28, */ +/* ID_OVERRIDE_shift = 28, */ + TA3_CNTL = 0x0000951c, +/* ID_OVERRIDE_mask = 0x03 << 28, */ +/* ID_OVERRIDE_shift = 28, */ + TA0_STATUS = 0x00009520, + FG_PFIFO_EMPTYB_bit = 1 << 12, + FG_LFIFO_EMPTYB_bit = 1 << 13, + FG_SFIFO_EMPTYB_bit = 1 << 14, + FL_PFIFO_EMPTYB_bit = 1 << 16, + FL_LFIFO_EMPTYB_bit = 1 << 17, + FL_SFIFO_EMPTYB_bit = 1 << 18, + FA_PFIFO_EMPTYB_bit = 1 << 20, + FA_LFIFO_EMPTYB_bit = 1 << 21, + FA_SFIFO_EMPTYB_bit = 1 << 22, + IN_BUSY_bit = 1 << 24, + FG_BUSY_bit = 1 << 25, + FL_BUSY_bit = 1 << 27, + TA_BUSY_bit = 1 << 28, + FA_BUSY_bit = 1 << 29, + AL_BUSY_bit = 1 << 30, +/* BUSY_bit = 1 << 31, */ + TA1_STATUS = 0x00009524, +/* FG_PFIFO_EMPTYB_bit = 1 << 12, */ +/* FG_LFIFO_EMPTYB_bit = 1 << 13, */ +/* FG_SFIFO_EMPTYB_bit = 1 << 14, */ +/* FL_PFIFO_EMPTYB_bit = 1 << 16, */ +/* FL_LFIFO_EMPTYB_bit = 1 << 17, */ +/* FL_SFIFO_EMPTYB_bit = 1 << 18, */ +/* FA_PFIFO_EMPTYB_bit = 1 << 20, */ +/* FA_LFIFO_EMPTYB_bit = 1 << 21, */ +/* FA_SFIFO_EMPTYB_bit = 1 << 22, */ +/* IN_BUSY_bit = 1 << 24, */ +/* FG_BUSY_bit = 1 << 25, */ +/* FL_BUSY_bit = 1 << 27, */ +/* TA_BUSY_bit = 1 << 28, */ +/* FA_BUSY_bit = 1 << 29, */ +/* AL_BUSY_bit = 1 << 30, */ +/* BUSY_bit = 1 << 31, */ + TA2_STATUS = 0x00009528, +/* FG_PFIFO_EMPTYB_bit = 1 << 12, */ +/* FG_LFIFO_EMPTYB_bit = 1 << 13, */ +/* FG_SFIFO_EMPTYB_bit = 1 << 14, */ +/* FL_PFIFO_EMPTYB_bit = 1 << 16, */ +/* FL_LFIFO_EMPTYB_bit = 1 << 17, */ +/* FL_SFIFO_EMPTYB_bit = 1 << 18, */ +/* FA_PFIFO_EMPTYB_bit = 1 << 20, */ +/* FA_LFIFO_EMPTYB_bit = 1 << 21, */ +/* FA_SFIFO_EMPTYB_bit = 1 << 22, */ +/* IN_BUSY_bit = 1 << 24, */ +/* FG_BUSY_bit = 1 << 25, */ +/* FL_BUSY_bit = 1 << 27, */ +/* TA_BUSY_bit = 1 << 28, */ +/* FA_BUSY_bit = 1 << 29, */ +/* AL_BUSY_bit = 1 << 30, */ +/* BUSY_bit = 1 << 31, */ + TA3_STATUS = 0x0000952c, +/* FG_PFIFO_EMPTYB_bit = 1 << 12, */ +/* FG_LFIFO_EMPTYB_bit = 1 << 13, */ +/* FG_SFIFO_EMPTYB_bit = 1 << 14, */ +/* FL_PFIFO_EMPTYB_bit = 1 << 16, */ +/* FL_LFIFO_EMPTYB_bit = 1 << 17, */ +/* FL_SFIFO_EMPTYB_bit = 1 << 18, */ +/* FA_PFIFO_EMPTYB_bit = 1 << 20, */ +/* FA_LFIFO_EMPTYB_bit = 1 << 21, */ +/* FA_SFIFO_EMPTYB_bit = 1 << 22, */ +/* IN_BUSY_bit = 1 << 24, */ +/* FG_BUSY_bit = 1 << 25, */ +/* FL_BUSY_bit = 1 << 27, */ +/* TA_BUSY_bit = 1 << 28, */ +/* FA_BUSY_bit = 1 << 29, */ +/* AL_BUSY_bit = 1 << 30, */ +/* BUSY_bit = 1 << 31, */ + TC_STATUS = 0x00009600, + TC_BUSY_bit = 1 << 0, + TC_INVALIDATE = 0x00009604, + START_bit = 1 << 0, + TC_CNTL = 0x00009608, + FORCE_HIT_bit = 1 << 0, + FORCE_MISS_bit = 1 << 1, + L2_SIZE_mask = 0x0f << 5, + L2_SIZE_shift = 5, + _256K = 0x00, + _224K = 0x01, + _192K = 0x02, + _160K = 0x03, + _128K = 0x04, + _96K = 0x05, + _64K = 0x06, + _32K = 0x07, + L2_DISABLE_LATE_HIT_bit = 1 << 9, + DISABLE_VERT_PERF_bit = 1 << 10, + DISABLE_INVAL_BUSY_bit = 1 << 11, + DISABLE_INVAL_SAME_SURFACE_bit = 1 << 12, + PARTITION_MODE_mask = 0x03 << 13, + PARTITION_MODE_shift = 13, + X_VERTEX = 0x00, + MISS_ARB_MODE_bit = 1 << 15, + HIT_ARB_MODE_bit = 1 << 16, + DISABLE_WRITE_DELAY_bit = 1 << 17, + HIT_FIFO_DEPTH_bit = 1 << 18, + VC_CNTL = 0x00009700, + L2_INVALIDATE_bit = 1 << 0, + RESERVED_bit = 1 << 1, + CC_FORCE_MISS_bit = 1 << 2, + MI_CHAN_SEL_mask = 0x03 << 3, + MI_CHAN_SEL_shift = 3, + X_MC0_USES_CH_0_1 = 0x00, + X_MC0_USES_CH_0_3 = 0x01, + X_VC_MC0_IS_ACTIVE = 0x02, + X_VC_MC1_IS_DISABLED = 0x03, + MI_STEER_DISABLE_bit = 1 << 5, + MI_CREDIT_CTR_mask = 0x0f << 6, + MI_CREDIT_CTR_shift = 6, + MI_CREDIT_WE_bit = 1 << 10, + MI_REQ_STALL_THLD_mask = 0x07 << 11, + MI_REQ_STALL_THLD_shift = 11, + X_LATENCY_EXCEEDS_399_CLOCKS = 0x00, + X_LATENCY_EXCEEDS_415_CLOCKS = 0x01, + X_LATENCY_EXCEEDS_431_CLOCKS = 0x02, + X_LATENCY_EXCEEDS_447_CLOCKS = 0x03, + X_LATENCY_EXCEEDS_463_CLOCKS = 0x04, + X_LATENCY_EXCEEDS_479_CLOCKS = 0x05, + X_LATENCY_EXCEEDS_495_CLOCKS = 0x06, + X_LATENCY_EXCEEDS_511_CLOCKS = 0x07, + VC_CNTL__MI_TIMESTAMP_RES_mask = 0x1f << 14, + VC_CNTL__MI_TIMESTAMP_RES_shift = 14, + X_1X_SYSTEM_CLOCK = 0x00, + X_2X_SYSTEM_CLOCK = 0x01, + X_4X_SYSTEM_CLOCK = 0x02, + X_8X_SYSTEM_CLOCK = 0x03, + X_16X_SYSTEM_CLOCK = 0x04, + X_32X_SYSTEM_CLOCK = 0x05, + X_64X_SYSTEM_CLOCK = 0x06, + X_128X_SYSTEM_CLOCK = 0x07, + X_256X_SYSTEM_CLOCK = 0x08, + X_512X_SYSTEM_CLOCK = 0x09, + X_1024X_SYSTEM_CLOCK = 0x0a, + X_2048X_SYSTEM_CLOCK = 0x0b, + X_4092X_SYSTEM_CLOCK = 0x0c, + X_8192X_SYSTEM_CLOCK = 0x0d, + X_16384X_SYSTEM_CLOCK = 0x0e, + X_32768X_SYSTEM_CLOCK = 0x0f, + VC_CNTL_STATUS = 0x00009704, + RP_BUSY_bit = 1 << 0, + RG_BUSY_bit = 1 << 1, + VC_BUSY_bit = 1 << 2, + CLAMP_DETECT_bit = 1 << 3, + VC_CONFIG = 0x00009718, + WRITE_DIS_bit = 1 << 0, + GPR_DATA_PHASE_ADJ_mask = 0x07 << 1, + GPR_DATA_PHASE_ADJ_shift = 1, + X_LATENCY_BASE_0_CYCLES = 0x00, + X_LATENCY_BASE_1_CYCLES = 0x01, + X_LATENCY_BASE_2_CYCLES = 0x02, + X_LATENCY_BASE_3_CYCLES = 0x03, + TD_SIMD_SYNC_ADJ_mask = 0x07 << 4, + TD_SIMD_SYNC_ADJ_shift = 4, + X_0_CYCLES_DELAY = 0x00, + X_1_CYCLES_DELAY = 0x01, + X_2_CYCLES_DELAY = 0x02, + X_3_CYCLES_DELAY = 0x03, + X_4_CYCLES_DELAY = 0x04, + X_5_CYCLES_DELAY = 0x05, + X_6_CYCLES_DELAY = 0x06, + X_7_CYCLES_DELAY = 0x07, + SMX_DC_CTL0 = 0x0000a020, + WR_GATHER_STREAM0_bit = 1 << 0, + WR_GATHER_STREAM1_bit = 1 << 1, + WR_GATHER_STREAM2_bit = 1 << 2, + WR_GATHER_STREAM3_bit = 1 << 3, + WR_GATHER_SCRATCH_bit = 1 << 4, + WR_GATHER_REDUC_BUF_bit = 1 << 5, + WR_GATHER_RING_BUF_bit = 1 << 6, + WR_GATHER_F_BUF_bit = 1 << 7, + DISABLE_CACHES_bit = 1 << 8, + AUTO_FLUSH_INVAL_EN_bit = 1 << 10, + AUTO_FLUSH_EN_bit = 1 << 11, + AUTO_FLUSH_CNT_mask = 0xffff << 12, + AUTO_FLUSH_CNT_shift = 12, + MC_RD_STALL_FACTOR_mask = 0x03 << 28, + MC_RD_STALL_FACTOR_shift = 28, + MC_WR_STALL_FACTOR_mask = 0x03 << 30, + MC_WR_STALL_FACTOR_shift = 30, + SMX_DC_CTL1 = 0x0000a024, + OP_FIFO_SKID_mask = 0x7f << 0, + OP_FIFO_SKID_shift = 0, + CACHE_LINE_SIZE_bit = 1 << 8, + MULTI_FLUSH_MODE_bit = 1 << 9, + MULTI_FLUSH_REQ_ABORT_IDX_FIFO_SKID_mask = 0x0f << 10, + MULTI_FLUSH_REQ_ABORT_IDX_FIFO_SKID_shift = 10, + DISABLE_WR_GATHER_RD_HIT_FORCE_EVICT_bit = 1 << 16, + DISABLE_WR_GATHER_RD_HIT_COMP_VLDS_CHECK_bit = 1 << 17, + DISABLE_FLUSH_ES_ALSO_INVALS_bit = 1 << 18, + DISABLE_FLUSH_GS_ALSO_INVALS_bit = 1 << 19, + SMX_DC_CTL2 = 0x0000a028, + INVALIDATE_CACHES_bit = 1 << 0, + CACHES_INVALID_bit = 1 << 1, + CACHES_DIRTY_bit = 1 << 2, + FLUSH_ALL_bit = 1 << 4, + FLUSH_GS_THREADS_bit = 1 << 8, + FLUSH_ES_THREADS_bit = 1 << 9, + SMX_DC_MC_INTF_CTL = 0x0000a02c, + MC_RD_REQ_CRED_mask = 0xff << 0, + MC_RD_REQ_CRED_shift = 0, + MC_WR_REQ_CRED_mask = 0xff << 16, + MC_WR_REQ_CRED_shift = 16, + TD_PS_SAMPLER0_BORDER_RED = 0x0000a400, + TD_PS_SAMPLER0_BORDER_RED_num = 18, + TD_PS_SAMPLER0_BORDER_RED_offset = 16, + TD_PS_SAMPLER0_BORDER_GREEN = 0x0000a404, + TD_PS_SAMPLER0_BORDER_GREEN_num = 18, + TD_PS_SAMPLER0_BORDER_GREEN_offset = 16, + TD_PS_SAMPLER0_BORDER_BLUE = 0x0000a408, + TD_PS_SAMPLER0_BORDER_BLUE_num = 18, + TD_PS_SAMPLER0_BORDER_BLUE_offset = 16, + TD_PS_SAMPLER0_BORDER_ALPHA = 0x0000a40c, + TD_PS_SAMPLER0_BORDER_ALPHA_num = 18, + TD_PS_SAMPLER0_BORDER_ALPHA_offset = 16, + TD_VS_SAMPLER0_BORDER_RED = 0x0000a600, + TD_VS_SAMPLER0_BORDER_RED_num = 18, + TD_VS_SAMPLER0_BORDER_RED_offset = 16, + TD_VS_SAMPLER0_BORDER_GREEN = 0x0000a604, + TD_VS_SAMPLER0_BORDER_GREEN_num = 18, + TD_VS_SAMPLER0_BORDER_GREEN_offset = 16, + TD_VS_SAMPLER0_BORDER_BLUE = 0x0000a608, + TD_VS_SAMPLER0_BORDER_BLUE_num = 18, + TD_VS_SAMPLER0_BORDER_BLUE_offset = 16, + TD_VS_SAMPLER0_BORDER_ALPHA = 0x0000a60c, + TD_VS_SAMPLER0_BORDER_ALPHA_num = 18, + TD_VS_SAMPLER0_BORDER_ALPHA_offset = 16, + TD_GS_SAMPLER0_BORDER_RED = 0x0000a800, + TD_GS_SAMPLER0_BORDER_RED_num = 18, + TD_GS_SAMPLER0_BORDER_RED_offset = 16, + TD_GS_SAMPLER0_BORDER_GREEN = 0x0000a804, + TD_GS_SAMPLER0_BORDER_GREEN_num = 18, + TD_GS_SAMPLER0_BORDER_GREEN_offset = 16, + TD_GS_SAMPLER0_BORDER_BLUE = 0x0000a808, + TD_GS_SAMPLER0_BORDER_BLUE_num = 18, + TD_GS_SAMPLER0_BORDER_BLUE_offset = 16, + TD_GS_SAMPLER0_BORDER_ALPHA = 0x0000a80c, + TD_GS_SAMPLER0_BORDER_ALPHA_num = 18, + TD_GS_SAMPLER0_BORDER_ALPHA_offset = 16, + TD_PS_SAMPLER0_CLEARTYPE_KERNEL = 0x0000aa00, + TD_PS_SAMPLER0_CLEARTYPE_KERNEL_num = 18, + TD_PS_SAMPLER0_CLEARTYPE_KERNEL__WIDTH_mask = 0x07 << 0, + TD_PS_SAMPLER0_CLEARTYPE_KERNEL__WIDTH_shift = 0, + TD_PS_SAMPLER0_CLEARTYPE_KERNEL__HEIGHT_mask = 0x07 << 3, + TD_PS_SAMPLER0_CLEARTYPE_KERNEL__HEIGHT_shift = 3, + DB_DEPTH_SIZE = 0x00028000, + PITCH_TILE_MAX_mask = 0x3ff << 0, + PITCH_TILE_MAX_shift = 0, + SLICE_TILE_MAX_mask = 0xfffff << 10, + SLICE_TILE_MAX_shift = 10, + DB_DEPTH_VIEW = 0x00028004, + SLICE_START_mask = 0x7ff << 0, + SLICE_START_shift = 0, + SLICE_MAX_mask = 0x7ff << 13, + SLICE_MAX_shift = 13, + DB_DEPTH_BASE = 0x0002800c, + DB_DEPTH_INFO = 0x00028010, + DB_DEPTH_INFO__FORMAT_mask = 0x07 << 0, + DB_DEPTH_INFO__FORMAT_shift = 0, + DEPTH_INVALID = 0x00, + DEPTH_16 = 0x01, + DEPTH_X8_24 = 0x02, + DEPTH_8_24 = 0x03, + DEPTH_X8_24_FLOAT = 0x04, + DEPTH_8_24_FLOAT = 0x05, + DEPTH_32_FLOAT = 0x06, + DEPTH_X24_8_32_FLOAT = 0x07, + DB_DEPTH_INFO__READ_SIZE_bit = 1 << 3, + DB_DEPTH_INFO__ARRAY_MODE_mask = 0x0f << 15, + DB_DEPTH_INFO__ARRAY_MODE_shift = 15, + ARRAY_2D_TILED_THIN1 = 0x04, + TILE_SURFACE_ENABLE_bit = 1 << 25, + TILE_COMPACT_bit = 1 << 26, + ZRANGE_PRECISION_bit = 1 << 31, + DB_HTILE_DATA_BASE = 0x00028014, + DB_STENCIL_CLEAR = 0x00028028, + DB_STENCIL_CLEAR__CLEAR_mask = 0xff << 0, + DB_STENCIL_CLEAR__CLEAR_shift = 0, + MIN_mask = 0xff << 16, + MIN_shift = 16, + DB_DEPTH_CLEAR = 0x0002802c, + PA_SC_SCREEN_SCISSOR_TL = 0x00028030, + PA_SC_SCREEN_SCISSOR_TL__TL_X_mask = 0x7fff << 0, + PA_SC_SCREEN_SCISSOR_TL__TL_X_shift = 0, + PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask = 0x7fff << 16, + PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift = 16, + PA_SC_SCREEN_SCISSOR_BR = 0x00028034, + PA_SC_SCREEN_SCISSOR_BR__BR_X_mask = 0x7fff << 0, + PA_SC_SCREEN_SCISSOR_BR__BR_X_shift = 0, + PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask = 0x7fff << 16, + PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift = 16, + CB_COLOR0_BASE = 0x00028040, + CB_COLOR0_BASE_num = 8, + CB_COLOR0_SIZE = 0x00028060, + CB_COLOR0_SIZE_num = 8, +/* PITCH_TILE_MAX_mask = 0x3ff << 0, */ +/* PITCH_TILE_MAX_shift = 0, */ +/* SLICE_TILE_MAX_mask = 0xfffff << 10, */ +/* SLICE_TILE_MAX_shift = 10, */ + CB_COLOR0_VIEW = 0x00028080, + CB_COLOR0_VIEW_num = 8, +/* SLICE_START_mask = 0x7ff << 0, */ +/* SLICE_START_shift = 0, */ +/* SLICE_MAX_mask = 0x7ff << 13, */ +/* SLICE_MAX_shift = 13, */ + CB_COLOR0_INFO = 0x000280a0, + CB_COLOR0_INFO_num = 8, + ENDIAN_mask = 0x03 << 0, + ENDIAN_shift = 0, + ENDIAN_NONE = 0x00, + ENDIAN_8IN16 = 0x01, + ENDIAN_8IN32 = 0x02, + ENDIAN_8IN64 = 0x03, + CB_COLOR0_INFO__FORMAT_mask = 0x3f << 2, + CB_COLOR0_INFO__FORMAT_shift = 2, + COLOR_INVALID = 0x00, + COLOR_8 = 0x01, + COLOR_4_4 = 0x02, + COLOR_3_3_2 = 0x03, + COLOR_16 = 0x05, + COLOR_16_FLOAT = 0x06, + COLOR_8_8 = 0x07, + COLOR_5_6_5 = 0x08, + COLOR_6_5_5 = 0x09, + COLOR_1_5_5_5 = 0x0a, + COLOR_4_4_4_4 = 0x0b, + COLOR_5_5_5_1 = 0x0c, + COLOR_32 = 0x0d, + COLOR_32_FLOAT = 0x0e, + COLOR_16_16 = 0x0f, + COLOR_16_16_FLOAT = 0x10, + COLOR_8_24 = 0x11, + COLOR_8_24_FLOAT = 0x12, + COLOR_24_8 = 0x13, + COLOR_24_8_FLOAT = 0x14, + COLOR_10_11_11 = 0x15, + COLOR_10_11_11_FLOAT = 0x16, + COLOR_11_11_10 = 0x17, + COLOR_11_11_10_FLOAT = 0x18, + COLOR_2_10_10_10 = 0x19, + COLOR_8_8_8_8 = 0x1a, + COLOR_10_10_10_2 = 0x1b, + COLOR_X24_8_32_FLOAT = 0x1c, + COLOR_32_32 = 0x1d, + COLOR_32_32_FLOAT = 0x1e, + COLOR_16_16_16_16 = 0x1f, + COLOR_16_16_16_16_FLOAT = 0x20, + COLOR_32_32_32_32 = 0x22, + COLOR_32_32_32_32_FLOAT = 0x23, + CB_COLOR0_INFO__ARRAY_MODE_mask = 0x0f << 8, + CB_COLOR0_INFO__ARRAY_MODE_shift = 8, + ARRAY_LINEAR_GENERAL = 0x00, + ARRAY_LINEAR_ALIGNED = 0x01, +/* ARRAY_2D_TILED_THIN1 = 0x04, */ + NUMBER_TYPE_mask = 0x07 << 12, + NUMBER_TYPE_shift = 12, + NUMBER_UNORM = 0x00, + NUMBER_SNORM = 0x01, + NUMBER_USCALED = 0x02, + NUMBER_SSCALED = 0x03, + NUMBER_UINT = 0x04, + NUMBER_SINT = 0x05, + NUMBER_SRGB = 0x06, + NUMBER_FLOAT = 0x07, + CB_COLOR0_INFO__READ_SIZE_bit = 1 << 15, + COMP_SWAP_mask = 0x03 << 16, + COMP_SWAP_shift = 16, + SWAP_STD = 0x00, + SWAP_ALT = 0x01, + SWAP_STD_REV = 0x02, + SWAP_ALT_REV = 0x03, + CB_COLOR0_INFO__TILE_MODE_mask = 0x03 << 18, + CB_COLOR0_INFO__TILE_MODE_shift = 18, + TILE_DISABLE = 0x00, + TILE_CLEAR_ENABLE = 0x01, + TILE_FRAG_ENABLE = 0x02, + BLEND_CLAMP_bit = 1 << 20, + CLEAR_COLOR_bit = 1 << 21, + BLEND_BYPASS_bit = 1 << 22, + BLEND_FLOAT32_bit = 1 << 23, + SIMPLE_FLOAT_bit = 1 << 24, + CB_COLOR0_INFO__ROUND_MODE_bit = 1 << 25, +/* TILE_COMPACT_bit = 1 << 26, */ + SOURCE_FORMAT_bit = 1 << 27, + CB_COLOR0_TILE = 0x000280c0, + CB_COLOR0_TILE_num = 8, + CB_COLOR0_FRAG = 0x000280e0, + CB_COLOR0_FRAG_num = 8, + CB_COLOR0_MASK = 0x00028100, + CB_COLOR0_MASK_num = 8, + CMASK_BLOCK_MAX_mask = 0xfff << 0, + CMASK_BLOCK_MAX_shift = 0, + FMASK_TILE_MAX_mask = 0xfffff << 12, + FMASK_TILE_MAX_shift = 12, + CB_CLEAR_RED = 0x00028120, + CB_CLEAR_GREEN = 0x00028124, + CB_CLEAR_BLUE = 0x00028128, + CB_CLEAR_ALPHA = 0x0002812c, + SQ_ALU_CONST_BUFFER_SIZE_PS_0 = 0x00028140, + SQ_ALU_CONST_BUFFER_SIZE_PS_0_num = 16, + SQ_ALU_CONST_BUFFER_SIZE_PS_0__DATA_mask = 0x1ff << 0, + SQ_ALU_CONST_BUFFER_SIZE_PS_0__DATA_shift = 0, + SQ_ALU_CONST_BUFFER_SIZE_VS_0 = 0x00028180, + SQ_ALU_CONST_BUFFER_SIZE_VS_0_num = 16, + SQ_ALU_CONST_BUFFER_SIZE_VS_0__DATA_mask = 0x1ff << 0, + SQ_ALU_CONST_BUFFER_SIZE_VS_0__DATA_shift = 0, + SQ_ALU_CONST_BUFFER_SIZE_GS_0 = 0x000281c0, + SQ_ALU_CONST_BUFFER_SIZE_GS_0_num = 16, + SQ_ALU_CONST_BUFFER_SIZE_GS_0__DATA_mask = 0x1ff << 0, + SQ_ALU_CONST_BUFFER_SIZE_GS_0__DATA_shift = 0, + PA_SC_WINDOW_OFFSET = 0x00028200, + WINDOW_X_OFFSET_mask = 0x7fff << 0, + WINDOW_X_OFFSET_shift = 0, + WINDOW_Y_OFFSET_mask = 0x7fff << 16, + WINDOW_Y_OFFSET_shift = 16, + PA_SC_WINDOW_SCISSOR_TL = 0x00028204, + PA_SC_WINDOW_SCISSOR_TL__TL_X_mask = 0x3fff << 0, + PA_SC_WINDOW_SCISSOR_TL__TL_X_shift = 0, + PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask = 0x3fff << 16, + PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift = 16, + WINDOW_OFFSET_DISABLE_bit = 1 << 31, + PA_SC_WINDOW_SCISSOR_BR = 0x00028208, + PA_SC_WINDOW_SCISSOR_BR__BR_X_mask = 0x3fff << 0, + PA_SC_WINDOW_SCISSOR_BR__BR_X_shift = 0, + PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask = 0x3fff << 16, + PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift = 16, + PA_SC_CLIPRECT_RULE = 0x0002820c, + CLIP_RULE_mask = 0xffff << 0, + CLIP_RULE_shift = 0, + PA_SC_CLIPRECT_0_TL = 0x00028210, + PA_SC_CLIPRECT_0_TL_num = 4, + PA_SC_CLIPRECT_0_TL_offset = 8, + PA_SC_CLIPRECT_0_TL__TL_X_mask = 0x3fff << 0, + PA_SC_CLIPRECT_0_TL__TL_X_shift = 0, + PA_SC_CLIPRECT_0_TL__TL_Y_mask = 0x3fff << 16, + PA_SC_CLIPRECT_0_TL__TL_Y_shift = 16, + PA_SC_CLIPRECT_0_BR = 0x00028214, + PA_SC_CLIPRECT_0_BR_num = 4, + PA_SC_CLIPRECT_0_BR_offset = 8, + PA_SC_CLIPRECT_0_BR__BR_X_mask = 0x3fff << 0, + PA_SC_CLIPRECT_0_BR__BR_X_shift = 0, + PA_SC_CLIPRECT_0_BR__BR_Y_mask = 0x3fff << 16, + PA_SC_CLIPRECT_0_BR__BR_Y_shift = 16, + CB_TARGET_MASK = 0x00028238, + TARGET0_ENABLE_mask = 0x0f << 0, + TARGET0_ENABLE_shift = 0, + TARGET1_ENABLE_mask = 0x0f << 4, + TARGET1_ENABLE_shift = 4, + TARGET2_ENABLE_mask = 0x0f << 8, + TARGET2_ENABLE_shift = 8, + TARGET3_ENABLE_mask = 0x0f << 12, + TARGET3_ENABLE_shift = 12, + TARGET4_ENABLE_mask = 0x0f << 16, + TARGET4_ENABLE_shift = 16, + TARGET5_ENABLE_mask = 0x0f << 20, + TARGET5_ENABLE_shift = 20, + TARGET6_ENABLE_mask = 0x0f << 24, + TARGET6_ENABLE_shift = 24, + TARGET7_ENABLE_mask = 0x0f << 28, + TARGET7_ENABLE_shift = 28, + CB_SHADER_MASK = 0x0002823c, + OUTPUT0_ENABLE_mask = 0x0f << 0, + OUTPUT0_ENABLE_shift = 0, + OUTPUT1_ENABLE_mask = 0x0f << 4, + OUTPUT1_ENABLE_shift = 4, + OUTPUT2_ENABLE_mask = 0x0f << 8, + OUTPUT2_ENABLE_shift = 8, + OUTPUT3_ENABLE_mask = 0x0f << 12, + OUTPUT3_ENABLE_shift = 12, + OUTPUT4_ENABLE_mask = 0x0f << 16, + OUTPUT4_ENABLE_shift = 16, + OUTPUT5_ENABLE_mask = 0x0f << 20, + OUTPUT5_ENABLE_shift = 20, + OUTPUT6_ENABLE_mask = 0x0f << 24, + OUTPUT6_ENABLE_shift = 24, + OUTPUT7_ENABLE_mask = 0x0f << 28, + OUTPUT7_ENABLE_shift = 28, + PA_SC_GENERIC_SCISSOR_TL = 0x00028240, + PA_SC_GENERIC_SCISSOR_TL__TL_X_mask = 0x3fff << 0, + PA_SC_GENERIC_SCISSOR_TL__TL_X_shift = 0, + PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask = 0x3fff << 16, + PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift = 16, +/* WINDOW_OFFSET_DISABLE_bit = 1 << 31, */ + PA_SC_GENERIC_SCISSOR_BR = 0x00028244, + PA_SC_GENERIC_SCISSOR_BR__BR_X_mask = 0x3fff << 0, + PA_SC_GENERIC_SCISSOR_BR__BR_X_shift = 0, + PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask = 0x3fff << 16, + PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift = 16, + PA_SC_VPORT_SCISSOR_0_TL = 0x00028250, + PA_SC_VPORT_SCISSOR_0_TL_num = 16, + PA_SC_VPORT_SCISSOR_0_TL_offset = 8, + PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask = 0x3fff << 0, + PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift = 0, + PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask = 0x3fff << 16, + PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift = 16, +/* WINDOW_OFFSET_DISABLE_bit = 1 << 31, */ + PA_SC_VPORT_SCISSOR_0_BR = 0x00028254, + PA_SC_VPORT_SCISSOR_0_BR_num = 16, + PA_SC_VPORT_SCISSOR_0_BR_offset = 8, + PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask = 0x3fff << 0, + PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift = 0, + PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask = 0x3fff << 16, + PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift = 16, + PA_SC_VPORT_ZMIN_0 = 0x000282d0, + PA_SC_VPORT_ZMIN_0_num = 16, + PA_SC_VPORT_ZMIN_0_offset = 8, + PA_SC_VPORT_ZMAX_0 = 0x000282d4, + PA_SC_VPORT_ZMAX_0_num = 16, + PA_SC_VPORT_ZMAX_0_offset = 8, + SX_MISC = 0x00028350, + MULTIPASS_bit = 1 << 0, + SQ_VTX_SEMANTIC_0 = 0x00028380, + SQ_VTX_SEMANTIC_0_num = 32, +/* SEMANTIC_ID_mask = 0xff << 0, */ +/* SEMANTIC_ID_shift = 0, */ + VGT_MAX_VTX_INDX = 0x00028400, + VGT_MIN_VTX_INDX = 0x00028404, + VGT_INDX_OFFSET = 0x00028408, + VGT_MULTI_PRIM_IB_RESET_INDX = 0x0002840c, + SX_ALPHA_TEST_CONTROL = 0x00028410, + ALPHA_FUNC_mask = 0x07 << 0, + ALPHA_FUNC_shift = 0, + REF_NEVER = 0x00, + REF_LESS = 0x01, + REF_EQUAL = 0x02, + REF_LEQUAL = 0x03, + REF_GREATER = 0x04, + REF_NOTEQUAL = 0x05, + REF_GEQUAL = 0x06, + REF_ALWAYS = 0x07, + ALPHA_TEST_ENABLE_bit = 1 << 3, + ALPHA_TEST_BYPASS_bit = 1 << 8, + CB_BLEND_RED = 0x00028414, + CB_BLEND_GREEN = 0x00028418, + CB_BLEND_BLUE = 0x0002841c, + CB_BLEND_ALPHA = 0x00028420, + CB_FOG_RED = 0x00028424, + CB_FOG_GREEN = 0x00028428, + CB_FOG_BLUE = 0x0002842c, + DB_STENCILREFMASK = 0x00028430, + STENCILREF_mask = 0xff << 0, + STENCILREF_shift = 0, + STENCILMASK_mask = 0xff << 8, + STENCILMASK_shift = 8, + STENCILWRITEMASK_mask = 0xff << 16, + STENCILWRITEMASK_shift = 16, + DB_STENCILREFMASK_BF = 0x00028434, + STENCILREF_BF_mask = 0xff << 0, + STENCILREF_BF_shift = 0, + STENCILMASK_BF_mask = 0xff << 8, + STENCILMASK_BF_shift = 8, + STENCILWRITEMASK_BF_mask = 0xff << 16, + STENCILWRITEMASK_BF_shift = 16, + SX_ALPHA_REF = 0x00028438, + PA_CL_VPORT_XSCALE_0 = 0x0002843c, + PA_CL_VPORT_XSCALE_0_num = 16, + PA_CL_VPORT_XSCALE_0_offset = 24, + PA_CL_VPORT_XOFFSET_0 = 0x00028440, + PA_CL_VPORT_XOFFSET_0_num = 16, + PA_CL_VPORT_XOFFSET_0_offset = 24, + PA_CL_VPORT_YSCALE_0 = 0x00028444, + PA_CL_VPORT_YSCALE_0_num = 16, + PA_CL_VPORT_YSCALE_0_offset = 24, + PA_CL_VPORT_YOFFSET_0 = 0x00028448, + PA_CL_VPORT_YOFFSET_0_num = 16, + PA_CL_VPORT_YOFFSET_0_offset = 24, + PA_CL_VPORT_ZSCALE_0 = 0x0002844c, + PA_CL_VPORT_ZSCALE_0_num = 16, + PA_CL_VPORT_ZSCALE_0_offset = 24, + PA_CL_VPORT_ZOFFSET_0 = 0x00028450, + PA_CL_VPORT_ZOFFSET_0_num = 16, + PA_CL_VPORT_ZOFFSET_0_offset = 24, + SPI_VS_OUT_ID_0 = 0x00028614, + SPI_VS_OUT_ID_0_num = 10, + SEMANTIC_0_mask = 0xff << 0, + SEMANTIC_0_shift = 0, + SEMANTIC_1_mask = 0xff << 8, + SEMANTIC_1_shift = 8, + SEMANTIC_2_mask = 0xff << 16, + SEMANTIC_2_shift = 16, + SEMANTIC_3_mask = 0xff << 24, + SEMANTIC_3_shift = 24, + SPI_PS_INPUT_CNTL_0 = 0x00028644, + SPI_PS_INPUT_CNTL_0_num = 32, + SEMANTIC_mask = 0xff << 0, + SEMANTIC_shift = 0, + DEFAULT_VAL_mask = 0x03 << 8, + DEFAULT_VAL_shift = 8, + X_0_0F = 0x00, + FLAT_SHADE_bit = 1 << 10, + SEL_CENTROID_bit = 1 << 11, + SEL_LINEAR_bit = 1 << 12, + CYL_WRAP_mask = 0x0f << 13, + CYL_WRAP_shift = 13, + PT_SPRITE_TEX_bit = 1 << 17, + SEL_SAMPLE_bit = 1 << 18, + SPI_VS_OUT_CONFIG = 0x000286c4, + VS_PER_COMPONENT_bit = 1 << 0, + VS_EXPORT_COUNT_mask = 0x1f << 1, + VS_EXPORT_COUNT_shift = 1, + VS_EXPORTS_FOG_bit = 1 << 8, + VS_OUT_FOG_VEC_ADDR_mask = 0x1f << 9, + VS_OUT_FOG_VEC_ADDR_shift = 9, + SPI_PS_IN_CONTROL_0 = 0x000286cc, + NUM_INTERP_mask = 0x3f << 0, + NUM_INTERP_shift = 0, + POSITION_ENA_bit = 1 << 8, + POSITION_CENTROID_bit = 1 << 9, + POSITION_ADDR_mask = 0x1f << 10, + POSITION_ADDR_shift = 10, + PARAM_GEN_mask = 0x0f << 15, + PARAM_GEN_shift = 15, + PARAM_GEN_ADDR_mask = 0x7f << 19, + PARAM_GEN_ADDR_shift = 19, + BARYC_SAMPLE_CNTL_mask = 0x03 << 26, + BARYC_SAMPLE_CNTL_shift = 26, + CENTROIDS_ONLY = 0x00, + CENTERS_ONLY = 0x01, + CENTROIDS_AND_CENTERS = 0x02, + UNDEF = 0x03, + PERSP_GRADIENT_ENA_bit = 1 << 28, + LINEAR_GRADIENT_ENA_bit = 1 << 29, + POSITION_SAMPLE_bit = 1 << 30, + BARYC_AT_SAMPLE_ENA_bit = 1 << 31, + SPI_PS_IN_CONTROL_1 = 0x000286d0, + GEN_INDEX_PIX_bit = 1 << 0, + GEN_INDEX_PIX_ADDR_mask = 0x7f << 1, + GEN_INDEX_PIX_ADDR_shift = 1, + FRONT_FACE_ENA_bit = 1 << 8, + FRONT_FACE_CHAN_mask = 0x03 << 9, + FRONT_FACE_CHAN_shift = 9, + FRONT_FACE_ALL_BITS_bit = 1 << 11, + FRONT_FACE_ADDR_mask = 0x1f << 12, + FRONT_FACE_ADDR_shift = 12, + FOG_ADDR_mask = 0x7f << 17, + FOG_ADDR_shift = 17, + FIXED_PT_POSITION_ENA_bit = 1 << 24, + FIXED_PT_POSITION_ADDR_mask = 0x1f << 25, + FIXED_PT_POSITION_ADDR_shift = 25, + SPI_INTERP_CONTROL_0 = 0x000286d4, + FLAT_SHADE_ENA_bit = 1 << 0, + PNT_SPRITE_ENA_bit = 1 << 1, + PNT_SPRITE_OVRD_X_mask = 0x07 << 2, + PNT_SPRITE_OVRD_X_shift = 2, + SPI_PNT_SPRITE_SEL_0 = 0x00, + SPI_PNT_SPRITE_SEL_1 = 0x01, + SPI_PNT_SPRITE_SEL_S = 0x02, + SPI_PNT_SPRITE_SEL_T = 0x03, + SPI_PNT_SPRITE_SEL_NONE = 0x04, + PNT_SPRITE_OVRD_Y_mask = 0x07 << 5, + PNT_SPRITE_OVRD_Y_shift = 5, +/* SPI_PNT_SPRITE_SEL_0 = 0x00, */ +/* SPI_PNT_SPRITE_SEL_1 = 0x01, */ +/* SPI_PNT_SPRITE_SEL_S = 0x02, */ +/* SPI_PNT_SPRITE_SEL_T = 0x03, */ +/* SPI_PNT_SPRITE_SEL_NONE = 0x04, */ + PNT_SPRITE_OVRD_Z_mask = 0x07 << 8, + PNT_SPRITE_OVRD_Z_shift = 8, +/* SPI_PNT_SPRITE_SEL_0 = 0x00, */ +/* SPI_PNT_SPRITE_SEL_1 = 0x01, */ +/* SPI_PNT_SPRITE_SEL_S = 0x02, */ +/* SPI_PNT_SPRITE_SEL_T = 0x03, */ +/* SPI_PNT_SPRITE_SEL_NONE = 0x04, */ + PNT_SPRITE_OVRD_W_mask = 0x07 << 11, + PNT_SPRITE_OVRD_W_shift = 11, +/* SPI_PNT_SPRITE_SEL_0 = 0x00, */ +/* SPI_PNT_SPRITE_SEL_1 = 0x01, */ +/* SPI_PNT_SPRITE_SEL_S = 0x02, */ +/* SPI_PNT_SPRITE_SEL_T = 0x03, */ +/* SPI_PNT_SPRITE_SEL_NONE = 0x04, */ + PNT_SPRITE_TOP_1_bit = 1 << 14, + SPI_INPUT_Z = 0x000286d8, + PROVIDE_Z_TO_SPI_bit = 1 << 0, + SPI_FOG_CNTL = 0x000286dc, + PASS_FOG_THROUGH_PS_bit = 1 << 0, + PIXEL_FOG_FUNC_mask = 0x03 << 1, + PIXEL_FOG_FUNC_shift = 1, + SPI_FOG_NONE = 0x00, + SPI_FOG_EXP = 0x01, + SPI_FOG_EXP2 = 0x02, + SPI_FOG_LINEAR = 0x03, + PIXEL_FOG_SRC_SEL_bit = 1 << 3, + VS_FOG_CLAMP_DISABLE_bit = 1 << 4, + SPI_FOG_FUNC_SCALE = 0x000286e0, + SPI_FOG_FUNC_BIAS = 0x000286e4, + CB_BLEND0_CONTROL = 0x00028780, + CB_BLEND0_CONTROL_num = 8, + COLOR_SRCBLEND_mask = 0x1f << 0, + COLOR_SRCBLEND_shift = 0, + COLOR_COMB_FCN_mask = 0x07 << 5, + COLOR_COMB_FCN_shift = 5, + COLOR_DESTBLEND_mask = 0x1f << 8, + COLOR_DESTBLEND_shift = 8, + OPACITY_WEIGHT_bit = 1 << 13, + ALPHA_SRCBLEND_mask = 0x1f << 16, + ALPHA_SRCBLEND_shift = 16, + ALPHA_COMB_FCN_mask = 0x07 << 21, + ALPHA_COMB_FCN_shift = 21, + ALPHA_DESTBLEND_mask = 0x1f << 24, + ALPHA_DESTBLEND_shift = 24, + SEPARATE_ALPHA_BLEND_bit = 1 << 29, + VGT_DMA_BASE_HI = 0x000287e4, + VGT_DMA_BASE_HI__BASE_ADDR_mask = 0xff << 0, + VGT_DMA_BASE_HI__BASE_ADDR_shift = 0, + VGT_DMA_BASE = 0x000287e8, + VGT_DRAW_INITIATOR = 0x000287f0, + SOURCE_SELECT_mask = 0x03 << 0, + SOURCE_SELECT_shift = 0, + DI_SRC_SEL_DMA = 0x00, + DI_SRC_SEL_IMMEDIATE = 0x01, + DI_SRC_SEL_AUTO_INDEX = 0x02, + DI_SRC_SEL_RESERVED = 0x03, + MAJOR_MODE_mask = 0x03 << 2, + MAJOR_MODE_shift = 2, + DI_MAJOR_MODE_0 = 0x00, + DI_MAJOR_MODE_1 = 0x01, + SPRITE_EN_bit = 1 << 4, + NOT_EOP_bit = 1 << 5, + USE_OPAQUE_bit = 1 << 6, + VGT_IMMED_DATA = 0x000287f4, + VGT_EVENT_ADDRESS_REG = 0x000287f8, + ADDRESS_LOW_mask = 0xfffffff << 0, + ADDRESS_LOW_shift = 0, + DB_DEPTH_CONTROL = 0x00028800, + STENCIL_ENABLE_bit = 1 << 0, + Z_ENABLE_bit = 1 << 1, + Z_WRITE_ENABLE_bit = 1 << 2, + ZFUNC_mask = 0x07 << 4, + ZFUNC_shift = 4, + FRAG_NEVER = 0x00, + FRAG_LESS = 0x01, + FRAG_EQUAL = 0x02, + FRAG_LEQUAL = 0x03, + FRAG_GREATER = 0x04, + FRAG_NOTEQUAL = 0x05, + FRAG_GEQUAL = 0x06, + FRAG_ALWAYS = 0x07, + BACKFACE_ENABLE_bit = 1 << 7, + STENCILFUNC_mask = 0x07 << 8, + STENCILFUNC_shift = 8, +/* REF_NEVER = 0x00, */ +/* REF_LESS = 0x01, */ +/* REF_EQUAL = 0x02, */ +/* REF_LEQUAL = 0x03, */ +/* REF_GREATER = 0x04, */ +/* REF_NOTEQUAL = 0x05, */ +/* REF_GEQUAL = 0x06, */ +/* REF_ALWAYS = 0x07, */ + STENCILFAIL_mask = 0x07 << 11, + STENCILFAIL_shift = 11, + STENCIL_KEEP = 0x00, + STENCIL_ZERO = 0x01, + STENCIL_REPLACE = 0x02, + STENCIL_INCR_CLAMP = 0x03, + STENCIL_DECR_CLAMP = 0x04, + STENCIL_INVERT = 0x05, + STENCIL_INCR_WRAP = 0x06, + STENCIL_DECR_WRAP = 0x07, + STENCILZPASS_mask = 0x07 << 14, + STENCILZPASS_shift = 14, +/* STENCIL_KEEP = 0x00, */ +/* STENCIL_ZERO = 0x01, */ +/* STENCIL_REPLACE = 0x02, */ +/* STENCIL_INCR_CLAMP = 0x03, */ +/* STENCIL_DECR_CLAMP = 0x04, */ +/* STENCIL_INVERT = 0x05, */ +/* STENCIL_INCR_WRAP = 0x06, */ +/* STENCIL_DECR_WRAP = 0x07, */ + STENCILZFAIL_mask = 0x07 << 17, + STENCILZFAIL_shift = 17, +/* STENCIL_KEEP = 0x00, */ +/* STENCIL_ZERO = 0x01, */ +/* STENCIL_REPLACE = 0x02, */ +/* STENCIL_INCR_CLAMP = 0x03, */ +/* STENCIL_DECR_CLAMP = 0x04, */ +/* STENCIL_INVERT = 0x05, */ +/* STENCIL_INCR_WRAP = 0x06, */ +/* STENCIL_DECR_WRAP = 0x07, */ + STENCILFUNC_BF_mask = 0x07 << 20, + STENCILFUNC_BF_shift = 20, +/* REF_NEVER = 0x00, */ +/* REF_LESS = 0x01, */ +/* REF_EQUAL = 0x02, */ +/* REF_LEQUAL = 0x03, */ +/* REF_GREATER = 0x04, */ +/* REF_NOTEQUAL = 0x05, */ +/* REF_GEQUAL = 0x06, */ +/* REF_ALWAYS = 0x07, */ + STENCILFAIL_BF_mask = 0x07 << 23, + STENCILFAIL_BF_shift = 23, +/* STENCIL_KEEP = 0x00, */ +/* STENCIL_ZERO = 0x01, */ +/* STENCIL_REPLACE = 0x02, */ +/* STENCIL_INCR_CLAMP = 0x03, */ +/* STENCIL_DECR_CLAMP = 0x04, */ +/* STENCIL_INVERT = 0x05, */ +/* STENCIL_INCR_WRAP = 0x06, */ +/* STENCIL_DECR_WRAP = 0x07, */ + STENCILZPASS_BF_mask = 0x07 << 26, + STENCILZPASS_BF_shift = 26, +/* STENCIL_KEEP = 0x00, */ +/* STENCIL_ZERO = 0x01, */ +/* STENCIL_REPLACE = 0x02, */ +/* STENCIL_INCR_CLAMP = 0x03, */ +/* STENCIL_DECR_CLAMP = 0x04, */ +/* STENCIL_INVERT = 0x05, */ +/* STENCIL_INCR_WRAP = 0x06, */ +/* STENCIL_DECR_WRAP = 0x07, */ + STENCILZFAIL_BF_mask = 0x07 << 29, + STENCILZFAIL_BF_shift = 29, +/* STENCIL_KEEP = 0x00, */ +/* STENCIL_ZERO = 0x01, */ +/* STENCIL_REPLACE = 0x02, */ +/* STENCIL_INCR_CLAMP = 0x03, */ +/* STENCIL_DECR_CLAMP = 0x04, */ +/* STENCIL_INVERT = 0x05, */ +/* STENCIL_INCR_WRAP = 0x06, */ +/* STENCIL_DECR_WRAP = 0x07, */ + CB_BLEND_CONTROL = 0x00028804, +/* COLOR_SRCBLEND_mask = 0x1f << 0, */ +/* COLOR_SRCBLEND_shift = 0, */ + BLEND_ZERO = 0x00, + BLEND_ONE = 0x01, + BLEND_SRC_COLOR = 0x02, + BLEND_ONE_MINUS_SRC_COLOR = 0x03, + BLEND_SRC_ALPHA = 0x04, + BLEND_ONE_MINUS_SRC_ALPHA = 0x05, + BLEND_DST_ALPHA = 0x06, + BLEND_ONE_MINUS_DST_ALPHA = 0x07, + BLEND_DST_COLOR = 0x08, + BLEND_ONE_MINUS_DST_COLOR = 0x09, + BLEND_SRC_ALPHA_SATURATE = 0x0a, + BLEND_BOTH_SRC_ALPHA = 0x0b, + BLEND_BOTH_INV_SRC_ALPHA = 0x0c, + BLEND_CONSTANT_COLOR = 0x0d, + BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, + BLEND_SRC1_COLOR = 0x0f, + BLEND_INV_SRC1_COLOR = 0x10, + BLEND_SRC1_ALPHA = 0x11, + BLEND_INV_SRC1_ALPHA = 0x12, + BLEND_CONSTANT_ALPHA = 0x13, + BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, +/* COLOR_COMB_FCN_mask = 0x07 << 5, */ +/* COLOR_COMB_FCN_shift = 5, */ + COMB_DST_PLUS_SRC = 0x00, + COMB_SRC_MINUS_DST = 0x01, + COMB_MIN_DST_SRC = 0x02, + COMB_MAX_DST_SRC = 0x03, + COMB_DST_MINUS_SRC = 0x04, +/* COLOR_DESTBLEND_mask = 0x1f << 8, */ +/* COLOR_DESTBLEND_shift = 8, */ +/* BLEND_ZERO = 0x00, */ +/* BLEND_ONE = 0x01, */ +/* BLEND_SRC_COLOR = 0x02, */ +/* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */ +/* BLEND_SRC_ALPHA = 0x04, */ +/* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */ +/* BLEND_DST_ALPHA = 0x06, */ +/* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */ +/* BLEND_DST_COLOR = 0x08, */ +/* BLEND_ONE_MINUS_DST_COLOR = 0x09, */ +/* BLEND_SRC_ALPHA_SATURATE = 0x0a, */ +/* BLEND_BOTH_SRC_ALPHA = 0x0b, */ +/* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */ +/* BLEND_CONSTANT_COLOR = 0x0d, */ +/* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */ +/* BLEND_SRC1_COLOR = 0x0f, */ +/* BLEND_INV_SRC1_COLOR = 0x10, */ +/* BLEND_SRC1_ALPHA = 0x11, */ +/* BLEND_INV_SRC1_ALPHA = 0x12, */ +/* BLEND_CONSTANT_ALPHA = 0x13, */ +/* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */ +/* OPACITY_WEIGHT_bit = 1 << 13, */ +/* ALPHA_SRCBLEND_mask = 0x1f << 16, */ +/* ALPHA_SRCBLEND_shift = 16, */ +/* BLEND_ZERO = 0x00, */ +/* BLEND_ONE = 0x01, */ +/* BLEND_SRC_COLOR = 0x02, */ +/* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */ +/* BLEND_SRC_ALPHA = 0x04, */ +/* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */ +/* BLEND_DST_ALPHA = 0x06, */ +/* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */ +/* BLEND_DST_COLOR = 0x08, */ +/* BLEND_ONE_MINUS_DST_COLOR = 0x09, */ +/* BLEND_SRC_ALPHA_SATURATE = 0x0a, */ +/* BLEND_BOTH_SRC_ALPHA = 0x0b, */ +/* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */ +/* BLEND_CONSTANT_COLOR = 0x0d, */ +/* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */ +/* BLEND_SRC1_COLOR = 0x0f, */ +/* BLEND_INV_SRC1_COLOR = 0x10, */ +/* BLEND_SRC1_ALPHA = 0x11, */ +/* BLEND_INV_SRC1_ALPHA = 0x12, */ +/* BLEND_CONSTANT_ALPHA = 0x13, */ +/* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */ +/* ALPHA_COMB_FCN_mask = 0x07 << 21, */ +/* ALPHA_COMB_FCN_shift = 21, */ +/* COMB_DST_PLUS_SRC = 0x00, */ +/* COMB_SRC_MINUS_DST = 0x01, */ +/* COMB_MIN_DST_SRC = 0x02, */ +/* COMB_MAX_DST_SRC = 0x03, */ +/* COMB_DST_MINUS_SRC = 0x04, */ +/* ALPHA_DESTBLEND_mask = 0x1f << 24, */ +/* ALPHA_DESTBLEND_shift = 24, */ +/* BLEND_ZERO = 0x00, */ +/* BLEND_ONE = 0x01, */ +/* BLEND_SRC_COLOR = 0x02, */ +/* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */ +/* BLEND_SRC_ALPHA = 0x04, */ +/* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */ +/* BLEND_DST_ALPHA = 0x06, */ +/* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */ +/* BLEND_DST_COLOR = 0x08, */ +/* BLEND_ONE_MINUS_DST_COLOR = 0x09, */ +/* BLEND_SRC_ALPHA_SATURATE = 0x0a, */ +/* BLEND_BOTH_SRC_ALPHA = 0x0b, */ +/* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */ +/* BLEND_CONSTANT_COLOR = 0x0d, */ +/* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */ +/* BLEND_SRC1_COLOR = 0x0f, */ +/* BLEND_INV_SRC1_COLOR = 0x10, */ +/* BLEND_SRC1_ALPHA = 0x11, */ +/* BLEND_INV_SRC1_ALPHA = 0x12, */ +/* BLEND_CONSTANT_ALPHA = 0x13, */ +/* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */ +/* SEPARATE_ALPHA_BLEND_bit = 1 << 29, */ + CB_COLOR_CONTROL = 0x00028808, + FOG_ENABLE_bit = 1 << 0, + MULTIWRITE_ENABLE_bit = 1 << 1, + DITHER_ENABLE_bit = 1 << 2, + DEGAMMA_ENABLE_bit = 1 << 3, + SPECIAL_OP_mask = 0x07 << 4, + SPECIAL_OP_shift = 4, + SPECIAL_NORMAL = 0x00, + SPECIAL_DISABLE = 0x01, + SPECIAL_FAST_CLEAR = 0x02, + SPECIAL_FORCE_CLEAR = 0x03, + SPECIAL_EXPAND_COLOR = 0x04, + SPECIAL_EXPAND_TEXTURE = 0x05, + SPECIAL_EXPAND_SAMPLES = 0x06, + SPECIAL_RESOLVE_BOX = 0x07, + PER_MRT_BLEND_bit = 1 << 7, + TARGET_BLEND_ENABLE_mask = 0xff << 8, + TARGET_BLEND_ENABLE_shift = 8, + ROP3_mask = 0xff << 16, + ROP3_shift = 16, + DB_SHADER_CONTROL = 0x0002880c, + Z_EXPORT_ENABLE_bit = 1 << 0, + STENCIL_REF_EXPORT_ENABLE_bit = 1 << 1, + Z_ORDER_mask = 0x03 << 4, + Z_ORDER_shift = 4, + LATE_Z = 0x00, + EARLY_Z_THEN_LATE_Z = 0x01, + RE_Z = 0x02, + EARLY_Z_THEN_RE_Z = 0x03, + KILL_ENABLE_bit = 1 << 6, + COVERAGE_TO_MASK_ENABLE_bit = 1 << 7, + MASK_EXPORT_ENABLE_bit = 1 << 8, + DUAL_EXPORT_ENABLE_bit = 1 << 9, + EXEC_ON_HIER_FAIL_bit = 1 << 10, + EXEC_ON_NOOP_bit = 1 << 11, + PA_CL_CLIP_CNTL = 0x00028810, + UCP_ENA_0_bit = 1 << 0, + UCP_ENA_1_bit = 1 << 1, + UCP_ENA_2_bit = 1 << 2, + UCP_ENA_3_bit = 1 << 3, + UCP_ENA_4_bit = 1 << 4, + UCP_ENA_5_bit = 1 << 5, + PS_UCP_Y_SCALE_NEG_bit = 1 << 13, + PS_UCP_MODE_mask = 0x03 << 14, + PS_UCP_MODE_shift = 14, + CLIP_DISABLE_bit = 1 << 16, + UCP_CULL_ONLY_ENA_bit = 1 << 17, + BOUNDARY_EDGE_FLAG_ENA_bit = 1 << 18, + DX_CLIP_SPACE_DEF_bit = 1 << 19, + DIS_CLIP_ERR_DETECT_bit = 1 << 20, + VTX_KILL_OR_bit = 1 << 21, + DX_LINEAR_ATTR_CLIP_ENA_bit = 1 << 24, + VTE_VPORT_PROVOKE_DISABLE_bit = 1 << 25, + ZCLIP_NEAR_DISABLE_bit = 1 << 26, + ZCLIP_FAR_DISABLE_bit = 1 << 27, + PA_SU_SC_MODE_CNTL = 0x00028814, + CULL_FRONT_bit = 1 << 0, + CULL_BACK_bit = 1 << 1, + FACE_bit = 1 << 2, + POLY_MODE_mask = 0x03 << 3, + POLY_MODE_shift = 3, + X_DISABLE_POLY_MODE = 0x00, + X_DUAL_MODE = 0x01, + POLYMODE_FRONT_PTYPE_mask = 0x07 << 5, + POLYMODE_FRONT_PTYPE_shift = 5, + X_DRAW_POINTS = 0x00, + X_DRAW_LINES = 0x01, + X_DRAW_TRIANGLES = 0x02, + POLYMODE_BACK_PTYPE_mask = 0x07 << 8, + POLYMODE_BACK_PTYPE_shift = 8, +/* X_DRAW_POINTS = 0x00, */ +/* X_DRAW_LINES = 0x01, */ +/* X_DRAW_TRIANGLES = 0x02, */ + POLY_OFFSET_FRONT_ENABLE_bit = 1 << 11, + POLY_OFFSET_BACK_ENABLE_bit = 1 << 12, + POLY_OFFSET_PARA_ENABLE_bit = 1 << 13, + VTX_WINDOW_OFFSET_ENABLE_bit = 1 << 16, + PROVOKING_VTX_LAST_bit = 1 << 19, + PERSP_CORR_DIS_bit = 1 << 20, + MULTI_PRIM_IB_ENA_bit = 1 << 21, + PA_CL_VTE_CNTL = 0x00028818, + VPORT_X_SCALE_ENA_bit = 1 << 0, + VPORT_X_OFFSET_ENA_bit = 1 << 1, + VPORT_Y_SCALE_ENA_bit = 1 << 2, + VPORT_Y_OFFSET_ENA_bit = 1 << 3, + VPORT_Z_SCALE_ENA_bit = 1 << 4, + VPORT_Z_OFFSET_ENA_bit = 1 << 5, + VTX_XY_FMT_bit = 1 << 8, + VTX_Z_FMT_bit = 1 << 9, + VTX_W0_FMT_bit = 1 << 10, + PERFCOUNTER_REF_bit = 1 << 11, + PA_CL_VS_OUT_CNTL = 0x0002881c, + CLIP_DIST_ENA_0_bit = 1 << 0, + CLIP_DIST_ENA_1_bit = 1 << 1, + CLIP_DIST_ENA_2_bit = 1 << 2, + CLIP_DIST_ENA_3_bit = 1 << 3, + CLIP_DIST_ENA_4_bit = 1 << 4, + CLIP_DIST_ENA_5_bit = 1 << 5, + CLIP_DIST_ENA_6_bit = 1 << 6, + CLIP_DIST_ENA_7_bit = 1 << 7, + CULL_DIST_ENA_0_bit = 1 << 8, + CULL_DIST_ENA_1_bit = 1 << 9, + CULL_DIST_ENA_2_bit = 1 << 10, + CULL_DIST_ENA_3_bit = 1 << 11, + CULL_DIST_ENA_4_bit = 1 << 12, + CULL_DIST_ENA_5_bit = 1 << 13, + CULL_DIST_ENA_6_bit = 1 << 14, + CULL_DIST_ENA_7_bit = 1 << 15, + USE_VTX_POINT_SIZE_bit = 1 << 16, + USE_VTX_EDGE_FLAG_bit = 1 << 17, + USE_VTX_RENDER_TARGET_INDX_bit = 1 << 18, + USE_VTX_VIEWPORT_INDX_bit = 1 << 19, + USE_VTX_KILL_FLAG_bit = 1 << 20, + VS_OUT_MISC_VEC_ENA_bit = 1 << 21, + VS_OUT_CCDIST0_VEC_ENA_bit = 1 << 22, + VS_OUT_CCDIST1_VEC_ENA_bit = 1 << 23, + PA_CL_NANINF_CNTL = 0x00028820, + VTE_XY_INF_DISCARD_bit = 1 << 0, + VTE_Z_INF_DISCARD_bit = 1 << 1, + VTE_W_INF_DISCARD_bit = 1 << 2, + VTE_0XNANINF_IS_0_bit = 1 << 3, + VTE_XY_NAN_RETAIN_bit = 1 << 4, + VTE_Z_NAN_RETAIN_bit = 1 << 5, + VTE_W_NAN_RETAIN_bit = 1 << 6, + VTE_W_RECIP_NAN_IS_0_bit = 1 << 7, + VS_XY_NAN_TO_INF_bit = 1 << 8, + VS_XY_INF_RETAIN_bit = 1 << 9, + VS_Z_NAN_TO_INF_bit = 1 << 10, + VS_Z_INF_RETAIN_bit = 1 << 11, + VS_W_NAN_TO_INF_bit = 1 << 12, + VS_W_INF_RETAIN_bit = 1 << 13, + VS_CLIP_DIST_INF_DISCARD_bit = 1 << 14, + VTE_NO_OUTPUT_NEG_0_bit = 1 << 20, + SQ_PGM_START_PS = 0x00028840, + SQ_PGM_RESOURCES_PS = 0x00028850, + NUM_GPRS_mask = 0xff << 0, + NUM_GPRS_shift = 0, + STACK_SIZE_mask = 0xff << 8, + STACK_SIZE_shift = 8, + SQ_PGM_RESOURCES_PS__DX10_CLAMP_bit = 1 << 21, + FETCH_CACHE_LINES_mask = 0x07 << 24, + FETCH_CACHE_LINES_shift = 24, + UNCACHED_FIRST_INST_bit = 1 << 28, + CLAMP_CONSTS_bit = 1 << 31, + SQ_PGM_EXPORTS_PS = 0x00028854, + EXPORT_MODE_mask = 0x1f << 0, + EXPORT_MODE_shift = 0, + SQ_PGM_START_VS = 0x00028858, + SQ_PGM_RESOURCES_VS = 0x00028868, +/* NUM_GPRS_mask = 0xff << 0, */ +/* NUM_GPRS_shift = 0, */ +/* STACK_SIZE_mask = 0xff << 8, */ +/* STACK_SIZE_shift = 8, */ + SQ_PGM_RESOURCES_VS__DX10_CLAMP_bit = 1 << 21, +/* FETCH_CACHE_LINES_mask = 0x07 << 24, */ +/* FETCH_CACHE_LINES_shift = 24, */ +/* UNCACHED_FIRST_INST_bit = 1 << 28, */ + SQ_PGM_START_GS = 0x0002886c, + SQ_PGM_RESOURCES_GS = 0x0002887c, +/* NUM_GPRS_mask = 0xff << 0, */ +/* NUM_GPRS_shift = 0, */ +/* STACK_SIZE_mask = 0xff << 8, */ +/* STACK_SIZE_shift = 8, */ + SQ_PGM_RESOURCES_GS__DX10_CLAMP_bit = 1 << 21, +/* FETCH_CACHE_LINES_mask = 0x07 << 24, */ +/* FETCH_CACHE_LINES_shift = 24, */ +/* UNCACHED_FIRST_INST_bit = 1 << 28, */ + SQ_PGM_START_ES = 0x00028880, + SQ_PGM_RESOURCES_ES = 0x00028890, +/* NUM_GPRS_mask = 0xff << 0, */ +/* NUM_GPRS_shift = 0, */ +/* STACK_SIZE_mask = 0xff << 8, */ +/* STACK_SIZE_shift = 8, */ + SQ_PGM_RESOURCES_ES__DX10_CLAMP_bit = 1 << 21, +/* FETCH_CACHE_LINES_mask = 0x07 << 24, */ +/* FETCH_CACHE_LINES_shift = 24, */ +/* UNCACHED_FIRST_INST_bit = 1 << 28, */ + SQ_PGM_START_FS = 0x00028894, + SQ_PGM_RESOURCES_FS = 0x000288a4, +/* NUM_GPRS_mask = 0xff << 0, */ +/* NUM_GPRS_shift = 0, */ +/* STACK_SIZE_mask = 0xff << 8, */ +/* STACK_SIZE_shift = 8, */ + SQ_PGM_RESOURCES_FS__DX10_CLAMP_bit = 1 << 21, + SQ_ESGS_RING_ITEMSIZE = 0x000288a8, + ITEMSIZE_mask = 0x7fff << 0, + ITEMSIZE_shift = 0, + SQ_GSVS_RING_ITEMSIZE = 0x000288ac, +/* ITEMSIZE_mask = 0x7fff << 0, */ +/* ITEMSIZE_shift = 0, */ + SQ_ESTMP_RING_ITEMSIZE = 0x000288b0, +/* ITEMSIZE_mask = 0x7fff << 0, */ +/* ITEMSIZE_shift = 0, */ + SQ_GSTMP_RING_ITEMSIZE = 0x000288b4, +/* ITEMSIZE_mask = 0x7fff << 0, */ +/* ITEMSIZE_shift = 0, */ + SQ_VSTMP_RING_ITEMSIZE = 0x000288b8, +/* ITEMSIZE_mask = 0x7fff << 0, */ +/* ITEMSIZE_shift = 0, */ + SQ_PSTMP_RING_ITEMSIZE = 0x000288bc, +/* ITEMSIZE_mask = 0x7fff << 0, */ +/* ITEMSIZE_shift = 0, */ + SQ_FBUF_RING_ITEMSIZE = 0x000288c0, +/* ITEMSIZE_mask = 0x7fff << 0, */ +/* ITEMSIZE_shift = 0, */ + SQ_REDUC_RING_ITEMSIZE = 0x000288c4, +/* ITEMSIZE_mask = 0x7fff << 0, */ +/* ITEMSIZE_shift = 0, */ + SQ_GS_VERT_ITEMSIZE = 0x000288c8, +/* ITEMSIZE_mask = 0x7fff << 0, */ +/* ITEMSIZE_shift = 0, */ + SQ_PGM_CF_OFFSET_PS = 0x000288cc, + PGM_CF_OFFSET_mask = 0xfffff << 0, + PGM_CF_OFFSET_shift = 0, + SQ_PGM_CF_OFFSET_VS = 0x000288d0, +/* PGM_CF_OFFSET_mask = 0xfffff << 0, */ +/* PGM_CF_OFFSET_shift = 0, */ + SQ_PGM_CF_OFFSET_GS = 0x000288d4, +/* PGM_CF_OFFSET_mask = 0xfffff << 0, */ +/* PGM_CF_OFFSET_shift = 0, */ + SQ_PGM_CF_OFFSET_ES = 0x000288d8, +/* PGM_CF_OFFSET_mask = 0xfffff << 0, */ +/* PGM_CF_OFFSET_shift = 0, */ + SQ_PGM_CF_OFFSET_FS = 0x000288dc, +/* PGM_CF_OFFSET_mask = 0xfffff << 0, */ +/* PGM_CF_OFFSET_shift = 0, */ + SQ_VTX_SEMANTIC_CLEAR = 0x000288e0, + SQ_ALU_CONST_CACHE_PS_0 = 0x00028940, + SQ_ALU_CONST_CACHE_PS_0_num = 16, + SQ_ALU_CONST_CACHE_VS_0 = 0x00028980, + SQ_ALU_CONST_CACHE_VS_0_num = 16, + SQ_ALU_CONST_CACHE_GS_0 = 0x000289c0, + SQ_ALU_CONST_CACHE_GS_0_num = 16, + PA_SU_POINT_SIZE = 0x00028a00, + PA_SU_POINT_SIZE__HEIGHT_mask = 0xffff << 0, + PA_SU_POINT_SIZE__HEIGHT_shift = 0, + PA_SU_POINT_SIZE__WIDTH_mask = 0xffff << 16, + PA_SU_POINT_SIZE__WIDTH_shift = 16, + PA_SU_POINT_MINMAX = 0x00028a04, + MIN_SIZE_mask = 0xffff << 0, + MIN_SIZE_shift = 0, + MAX_SIZE_mask = 0xffff << 16, + MAX_SIZE_shift = 16, + PA_SU_LINE_CNTL = 0x00028a08, + PA_SU_LINE_CNTL__WIDTH_mask = 0xffff << 0, + PA_SU_LINE_CNTL__WIDTH_shift = 0, + PA_SC_LINE_STIPPLE = 0x00028a0c, + LINE_PATTERN_mask = 0xffff << 0, + LINE_PATTERN_shift = 0, + REPEAT_COUNT_mask = 0xff << 16, + REPEAT_COUNT_shift = 16, + PATTERN_BIT_ORDER_bit = 1 << 28, + AUTO_RESET_CNTL_mask = 0x03 << 29, + AUTO_RESET_CNTL_shift = 29, + VGT_OUTPUT_PATH_CNTL = 0x00028a10, + PATH_SELECT_mask = 0x03 << 0, + PATH_SELECT_shift = 0, + VGT_OUTPATH_VTX_REUSE = 0x00, + VGT_OUTPATH_TESS_EN = 0x01, + VGT_OUTPATH_PASSTHRU = 0x02, + VGT_OUTPATH_GS_BLOCK = 0x03, + VGT_HOS_CNTL = 0x00028a14, + TESS_MODE_mask = 0x03 << 0, + TESS_MODE_shift = 0, + VGT_HOS_MAX_TESS_LEVEL = 0x00028a18, + VGT_HOS_MIN_TESS_LEVEL = 0x00028a1c, + VGT_HOS_REUSE_DEPTH = 0x00028a20, + REUSE_DEPTH_mask = 0xff << 0, + REUSE_DEPTH_shift = 0, + VGT_GROUP_PRIM_TYPE = 0x00028a24, + VGT_GROUP_PRIM_TYPE__PRIM_TYPE_mask = 0x1f << 0, + VGT_GROUP_PRIM_TYPE__PRIM_TYPE_shift = 0, + VGT_GRP_3D_POINT = 0x00, + VGT_GRP_3D_LINE = 0x01, + VGT_GRP_3D_TRI = 0x02, + VGT_GRP_3D_RECT = 0x03, + VGT_GRP_3D_QUAD = 0x04, + VGT_GRP_2D_COPY_RECT_V0 = 0x05, + VGT_GRP_2D_COPY_RECT_V1 = 0x06, + VGT_GRP_2D_COPY_RECT_V2 = 0x07, + VGT_GRP_2D_COPY_RECT_V3 = 0x08, + VGT_GRP_2D_FILL_RECT = 0x09, + VGT_GRP_2D_LINE = 0x0a, + VGT_GRP_2D_TRI = 0x0b, + VGT_GRP_PRIM_INDEX_LINE = 0x0c, + VGT_GRP_PRIM_INDEX_TRI = 0x0d, + VGT_GRP_PRIM_INDEX_QUAD = 0x0e, + VGT_GRP_3D_LINE_ADJ = 0x0f, + VGT_GRP_3D_TRI_ADJ = 0x10, + RETAIN_ORDER_bit = 1 << 14, + RETAIN_QUADS_bit = 1 << 15, + PRIM_ORDER_mask = 0x07 << 16, + PRIM_ORDER_shift = 16, + VGT_GRP_LIST = 0x00, + VGT_GRP_STRIP = 0x01, + VGT_GRP_FAN = 0x02, + VGT_GRP_LOOP = 0x03, + VGT_GRP_POLYGON = 0x04, + VGT_GROUP_FIRST_DECR = 0x00028a28, + FIRST_DECR_mask = 0x0f << 0, + FIRST_DECR_shift = 0, + VGT_GROUP_DECR = 0x00028a2c, + DECR_mask = 0x0f << 0, + DECR_shift = 0, + VGT_GROUP_VECT_0_CNTL = 0x00028a30, + COMP_X_EN_bit = 1 << 0, + COMP_Y_EN_bit = 1 << 1, + COMP_Z_EN_bit = 1 << 2, + COMP_W_EN_bit = 1 << 3, + VGT_GROUP_VECT_0_CNTL__STRIDE_mask = 0xff << 8, + VGT_GROUP_VECT_0_CNTL__STRIDE_shift = 8, + SHIFT_mask = 0xff << 16, + SHIFT_shift = 16, + VGT_GROUP_VECT_1_CNTL = 0x00028a34, +/* COMP_X_EN_bit = 1 << 0, */ +/* COMP_Y_EN_bit = 1 << 1, */ +/* COMP_Z_EN_bit = 1 << 2, */ +/* COMP_W_EN_bit = 1 << 3, */ + VGT_GROUP_VECT_1_CNTL__STRIDE_mask = 0xff << 8, + VGT_GROUP_VECT_1_CNTL__STRIDE_shift = 8, +/* SHIFT_mask = 0xff << 16, */ +/* SHIFT_shift = 16, */ + VGT_GROUP_VECT_0_FMT_CNTL = 0x00028a38, + X_CONV_mask = 0x0f << 0, + X_CONV_shift = 0, + VGT_GRP_INDEX_16 = 0x00, + VGT_GRP_INDEX_32 = 0x01, + VGT_GRP_UINT_16 = 0x02, + VGT_GRP_UINT_32 = 0x03, + VGT_GRP_SINT_16 = 0x04, + VGT_GRP_SINT_32 = 0x05, + VGT_GRP_FLOAT_32 = 0x06, + VGT_GRP_AUTO_PRIM = 0x07, + VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, + X_OFFSET_mask = 0x0f << 4, + X_OFFSET_shift = 4, + Y_CONV_mask = 0x0f << 8, + Y_CONV_shift = 8, +/* VGT_GRP_INDEX_16 = 0x00, */ +/* VGT_GRP_INDEX_32 = 0x01, */ +/* VGT_GRP_UINT_16 = 0x02, */ +/* VGT_GRP_UINT_32 = 0x03, */ +/* VGT_GRP_SINT_16 = 0x04, */ +/* VGT_GRP_SINT_32 = 0x05, */ +/* VGT_GRP_FLOAT_32 = 0x06, */ +/* VGT_GRP_AUTO_PRIM = 0x07, */ +/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ + Y_OFFSET_mask = 0x0f << 12, + Y_OFFSET_shift = 12, + Z_CONV_mask = 0x0f << 16, + Z_CONV_shift = 16, +/* VGT_GRP_INDEX_16 = 0x00, */ +/* VGT_GRP_INDEX_32 = 0x01, */ +/* VGT_GRP_UINT_16 = 0x02, */ +/* VGT_GRP_UINT_32 = 0x03, */ +/* VGT_GRP_SINT_16 = 0x04, */ +/* VGT_GRP_SINT_32 = 0x05, */ +/* VGT_GRP_FLOAT_32 = 0x06, */ +/* VGT_GRP_AUTO_PRIM = 0x07, */ +/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ + Z_OFFSET_mask = 0x0f << 20, + Z_OFFSET_shift = 20, + W_CONV_mask = 0x0f << 24, + W_CONV_shift = 24, +/* VGT_GRP_INDEX_16 = 0x00, */ +/* VGT_GRP_INDEX_32 = 0x01, */ +/* VGT_GRP_UINT_16 = 0x02, */ +/* VGT_GRP_UINT_32 = 0x03, */ +/* VGT_GRP_SINT_16 = 0x04, */ +/* VGT_GRP_SINT_32 = 0x05, */ +/* VGT_GRP_FLOAT_32 = 0x06, */ +/* VGT_GRP_AUTO_PRIM = 0x07, */ +/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ + W_OFFSET_mask = 0x0f << 28, + W_OFFSET_shift = 28, + VGT_GROUP_VECT_1_FMT_CNTL = 0x00028a3c, +/* X_CONV_mask = 0x0f << 0, */ +/* X_CONV_shift = 0, */ +/* VGT_GRP_INDEX_16 = 0x00, */ +/* VGT_GRP_INDEX_32 = 0x01, */ +/* VGT_GRP_UINT_16 = 0x02, */ +/* VGT_GRP_UINT_32 = 0x03, */ +/* VGT_GRP_SINT_16 = 0x04, */ +/* VGT_GRP_SINT_32 = 0x05, */ +/* VGT_GRP_FLOAT_32 = 0x06, */ +/* VGT_GRP_AUTO_PRIM = 0x07, */ +/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ +/* X_OFFSET_mask = 0x0f << 4, */ +/* X_OFFSET_shift = 4, */ +/* Y_CONV_mask = 0x0f << 8, */ +/* Y_CONV_shift = 8, */ +/* VGT_GRP_INDEX_16 = 0x00, */ +/* VGT_GRP_INDEX_32 = 0x01, */ +/* VGT_GRP_UINT_16 = 0x02, */ +/* VGT_GRP_UINT_32 = 0x03, */ +/* VGT_GRP_SINT_16 = 0x04, */ +/* VGT_GRP_SINT_32 = 0x05, */ +/* VGT_GRP_FLOAT_32 = 0x06, */ +/* VGT_GRP_AUTO_PRIM = 0x07, */ +/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ +/* Y_OFFSET_mask = 0x0f << 12, */ +/* Y_OFFSET_shift = 12, */ +/* Z_CONV_mask = 0x0f << 16, */ +/* Z_CONV_shift = 16, */ +/* VGT_GRP_INDEX_16 = 0x00, */ +/* VGT_GRP_INDEX_32 = 0x01, */ +/* VGT_GRP_UINT_16 = 0x02, */ +/* VGT_GRP_UINT_32 = 0x03, */ +/* VGT_GRP_SINT_16 = 0x04, */ +/* VGT_GRP_SINT_32 = 0x05, */ +/* VGT_GRP_FLOAT_32 = 0x06, */ +/* VGT_GRP_AUTO_PRIM = 0x07, */ +/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ +/* Z_OFFSET_mask = 0x0f << 20, */ +/* Z_OFFSET_shift = 20, */ +/* W_CONV_mask = 0x0f << 24, */ +/* W_CONV_shift = 24, */ +/* VGT_GRP_INDEX_16 = 0x00, */ +/* VGT_GRP_INDEX_32 = 0x01, */ +/* VGT_GRP_UINT_16 = 0x02, */ +/* VGT_GRP_UINT_32 = 0x03, */ +/* VGT_GRP_SINT_16 = 0x04, */ +/* VGT_GRP_SINT_32 = 0x05, */ +/* VGT_GRP_FLOAT_32 = 0x06, */ +/* VGT_GRP_AUTO_PRIM = 0x07, */ +/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ +/* W_OFFSET_mask = 0x0f << 28, */ +/* W_OFFSET_shift = 28, */ + VGT_GS_MODE = 0x00028a40, + MODE_mask = 0x03 << 0, + MODE_shift = 0, + GS_OFF = 0x00, + GS_SCENARIO_A = 0x01, + GS_SCENARIO_B = 0x02, + GS_SCENARIO_G = 0x03, + ES_PASSTHRU_bit = 1 << 2, + CUT_MODE_mask = 0x03 << 3, + CUT_MODE_shift = 3, + GS_CUT_1024 = 0x00, + GS_CUT_512 = 0x01, + GS_CUT_256 = 0x02, + GS_CUT_128 = 0x03, + PA_SC_MPASS_PS_CNTL = 0x00028a48, + MPASS_PIX_VEC_PER_PASS_mask = 0xfffff << 0, + MPASS_PIX_VEC_PER_PASS_shift = 0, + MPASS_PS_ENA_bit = 1 << 31, + PA_SC_MODE_CNTL = 0x00028a4c, + MSAA_ENABLE_bit = 1 << 0, + CLIPRECT_ENABLE_bit = 1 << 1, + LINE_STIPPLE_ENABLE_bit = 1 << 2, + MULTI_CHIP_PRIM_DISCARD_ENAB_bit = 1 << 3, + WALK_ORDER_ENABLE_bit = 1 << 4, + HALVE_DETAIL_SAMPLE_PERF_bit = 1 << 5, + WALK_SIZE_bit = 1 << 6, + WALK_ALIGNMENT_bit = 1 << 7, + WALK_ALIGN8_PRIM_FITS_ST_bit = 1 << 8, + TILE_COVER_NO_SCISSOR_bit = 1 << 9, + KILL_PIX_POST_HI_Z_bit = 1 << 10, + KILL_PIX_POST_DETAIL_MASK_bit = 1 << 11, + MULTI_CHIP_SUPERTILE_ENABLE_bit = 1 << 12, + TILE_COVER_DISABLE_bit = 1 << 13, + FORCE_EOV_CNTDWN_ENABLE_bit = 1 << 14, + FORCE_EOV_TILE_ENABLE_bit = 1 << 15, + FORCE_EOV_REZ_ENABLE_bit = 1 << 16, + PS_ITER_SAMPLE_bit = 1 << 17, + VGT_ENHANCE = 0x00028a50, + VGT_ENHANCE__MI_TIMESTAMP_RES_mask = 0x03 << 0, + VGT_ENHANCE__MI_TIMESTAMP_RES_shift = 0, + X_0_992_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_32 = 0x00, + X_0_496_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_16 = 0x01, + X_0_248_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_8 = 0x02, + X_0_124_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_4 = 0x03, + MISC_mask = 0x3fffffff << 2, + MISC_shift = 2, + VGT_GS_OUT_PRIM_TYPE = 0x00028a6c, + OUTPRIM_TYPE_mask = 0x3f << 0, + OUTPRIM_TYPE_shift = 0, + POINTLIST = 0x00, + LINESTRIP = 0x01, + TRISTRIP = 0x02, + VGT_DMA_SIZE = 0x00028a74, + VGT_DMA_INDEX_TYPE = 0x00028a7c, +/* INDEX_TYPE_mask = 0x03 << 0, */ +/* INDEX_TYPE_shift = 0, */ + VGT_INDEX_16 = 0x00, + VGT_INDEX_32 = 0x01, + SWAP_MODE_mask = 0x03 << 2, + SWAP_MODE_shift = 2, + VGT_DMA_SWAP_NONE = 0x00, + VGT_DMA_SWAP_16_BIT = 0x01, + VGT_DMA_SWAP_32_BIT = 0x02, + VGT_DMA_SWAP_WORD = 0x03, + VGT_PRIMITIVEID_EN = 0x00028a84, + PRIMITIVEID_EN_bit = 1 << 0, + VGT_DMA_NUM_INSTANCES = 0x00028a88, + VGT_EVENT_INITIATOR = 0x00028a90, + EVENT_TYPE_mask = 0x3f << 0, + EVENT_TYPE_shift = 0, + CACHE_FLUSH_TS = 0x04, + CONTEXT_DONE = 0x05, + CACHE_FLUSH = 0x06, + VIZQUERY_START = 0x07, + VIZQUERY_END = 0x08, + SC_WAIT_WC = 0x09, + MPASS_PS_CP_REFETCH = 0x0a, + MPASS_PS_RST_START = 0x0b, + MPASS_PS_INCR_START = 0x0c, + RST_PIX_CNT = 0x0d, + RST_VTX_CNT = 0x0e, + VS_PARTIAL_FLUSH = 0x0f, + PS_PARTIAL_FLUSH = 0x10, + CACHE_FLUSH_AND_INV_TS_EVENT = 0x14, + ZPASS_DONE = 0x15, + CACHE_FLUSH_AND_INV_EVENT = 0x16, + PERFCOUNTER_START = 0x17, + PERFCOUNTER_STOP = 0x18, + PIPELINESTAT_START = 0x19, + PIPELINESTAT_STOP = 0x1a, + PERFCOUNTER_SAMPLE = 0x1b, + FLUSH_ES_OUTPUT = 0x1c, + FLUSH_GS_OUTPUT = 0x1d, + SAMPLE_PIPELINESTAT = 0x1e, + SO_VGTSTREAMOUT_FLUSH = 0x1f, + SAMPLE_STREAMOUTSTATS = 0x20, + RESET_VTX_CNT = 0x21, + BLOCK_CONTEXT_DONE = 0x22, + CR_CONTEXT_DONE = 0x23, + VGT_FLUSH = 0x24, + CR_DONE_TS = 0x25, + SQ_NON_EVENT = 0x26, + SC_SEND_DB_VPZ = 0x27, + BOTTOM_OF_PIPE_TS = 0x28, + DB_CACHE_FLUSH_AND_INV = 0x2a, + ADDRESS_HI_mask = 0xff << 19, + ADDRESS_HI_shift = 19, + EXTENDED_EVENT_bit = 1 << 27, + VGT_MULTI_PRIM_IB_RESET_EN = 0x00028a94, + RESET_EN_bit = 1 << 0, + VGT_INSTANCE_STEP_RATE_0 = 0x00028aa0, + VGT_INSTANCE_STEP_RATE_1 = 0x00028aa4, + VGT_STRMOUT_EN = 0x00028ab0, + STREAMOUT_bit = 1 << 0, + VGT_REUSE_OFF = 0x00028ab4, + REUSE_OFF_bit = 1 << 0, + VGT_VTX_CNT_EN = 0x00028ab8, + VTX_CNT_EN_bit = 1 << 0, + VGT_STRMOUT_BUFFER_SIZE_0 = 0x00028ad0, + VGT_STRMOUT_VTX_STRIDE_0 = 0x00028ad4, + VGT_STRMOUT_VTX_STRIDE_0__STRIDE_mask = 0x3ff << 0, + VGT_STRMOUT_VTX_STRIDE_0__STRIDE_shift = 0, + VGT_STRMOUT_BUFFER_BASE_0 = 0x00028ad8, + VGT_STRMOUT_BUFFER_OFFSET_0 = 0x00028adc, + VGT_STRMOUT_BUFFER_SIZE_1 = 0x00028ae0, + VGT_STRMOUT_VTX_STRIDE_1 = 0x00028ae4, + VGT_STRMOUT_VTX_STRIDE_1__STRIDE_mask = 0x3ff << 0, + VGT_STRMOUT_VTX_STRIDE_1__STRIDE_shift = 0, + VGT_STRMOUT_BUFFER_BASE_1 = 0x00028ae8, + VGT_STRMOUT_BUFFER_OFFSET_1 = 0x00028aec, + VGT_STRMOUT_BUFFER_SIZE_2 = 0x00028af0, + VGT_STRMOUT_VTX_STRIDE_2 = 0x00028af4, + VGT_STRMOUT_VTX_STRIDE_2__STRIDE_mask = 0x3ff << 0, + VGT_STRMOUT_VTX_STRIDE_2__STRIDE_shift = 0, + VGT_STRMOUT_BUFFER_BASE_2 = 0x00028af8, + VGT_STRMOUT_BUFFER_OFFSET_2 = 0x00028afc, + VGT_STRMOUT_BUFFER_SIZE_3 = 0x00028b00, + VGT_STRMOUT_VTX_STRIDE_3 = 0x00028b04, + VGT_STRMOUT_VTX_STRIDE_3__STRIDE_mask = 0x3ff << 0, + VGT_STRMOUT_VTX_STRIDE_3__STRIDE_shift = 0, + VGT_STRMOUT_BUFFER_BASE_3 = 0x00028b08, + VGT_STRMOUT_BUFFER_OFFSET_3 = 0x00028b0c, + VGT_STRMOUT_BASE_OFFSET_0 = 0x00028b10, + VGT_STRMOUT_BASE_OFFSET_1 = 0x00028b14, + VGT_STRMOUT_BASE_OFFSET_2 = 0x00028b18, + VGT_STRMOUT_BASE_OFFSET_3 = 0x00028b1c, + VGT_STRMOUT_BUFFER_EN = 0x00028b20, + BUFFER_0_EN_bit = 1 << 0, + BUFFER_1_EN_bit = 1 << 1, + BUFFER_2_EN_bit = 1 << 2, + BUFFER_3_EN_bit = 1 << 3, + VGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x00028b28, + VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x00028b2c, + VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x00028b30, + VGT_STRMOUT_BASE_OFFSET_HI_0 = 0x00028b44, + VGT_STRMOUT_BASE_OFFSET_HI_0__BASE_OFFSET_mask = 0x3f << 0, + VGT_STRMOUT_BASE_OFFSET_HI_0__BASE_OFFSET_shift = 0, + VGT_STRMOUT_BASE_OFFSET_HI_1 = 0x00028b48, + VGT_STRMOUT_BASE_OFFSET_HI_1__BASE_OFFSET_mask = 0x3f << 0, + VGT_STRMOUT_BASE_OFFSET_HI_1__BASE_OFFSET_shift = 0, + VGT_STRMOUT_BASE_OFFSET_HI_2 = 0x00028b4c, + VGT_STRMOUT_BASE_OFFSET_HI_2__BASE_OFFSET_mask = 0x3f << 0, + VGT_STRMOUT_BASE_OFFSET_HI_2__BASE_OFFSET_shift = 0, + VGT_STRMOUT_BASE_OFFSET_HI_3 = 0x00028b50, + VGT_STRMOUT_BASE_OFFSET_HI_3__BASE_OFFSET_mask = 0x3f << 0, + VGT_STRMOUT_BASE_OFFSET_HI_3__BASE_OFFSET_shift = 0, + PA_SC_LINE_CNTL = 0x00028c00, + BRES_CNTL_mask = 0xff << 0, + BRES_CNTL_shift = 0, + USE_BRES_CNTL_bit = 1 << 8, + EXPAND_LINE_WIDTH_bit = 1 << 9, + LAST_PIXEL_bit = 1 << 10, + PA_SC_AA_CONFIG = 0x00028c04, + MSAA_NUM_SAMPLES_mask = 0x03 << 0, + MSAA_NUM_SAMPLES_shift = 0, + AA_MASK_CENTROID_DTMN_bit = 1 << 4, + MAX_SAMPLE_DIST_mask = 0x0f << 13, + MAX_SAMPLE_DIST_shift = 13, + PA_SU_VTX_CNTL = 0x00028c08, + PIX_CENTER_bit = 1 << 0, + PA_SU_VTX_CNTL__ROUND_MODE_mask = 0x03 << 1, + PA_SU_VTX_CNTL__ROUND_MODE_shift = 1, + X_TRUNCATE = 0x00, + X_ROUND = 0x01, + X_ROUND_TO_EVEN = 0x02, + X_ROUND_TO_ODD = 0x03, + QUANT_MODE_mask = 0x07 << 3, + QUANT_MODE_shift = 3, + X_1_16TH = 0x00, + X_1_8TH = 0x01, + X_1_4TH = 0x02, + X_1_2 = 0x03, + X_1 = 0x04, + X_1_256TH = 0x05, + PA_CL_GB_VERT_CLIP_ADJ = 0x00028c0c, + PA_CL_GB_VERT_DISC_ADJ = 0x00028c10, + PA_CL_GB_HORZ_CLIP_ADJ = 0x00028c14, + PA_CL_GB_HORZ_DISC_ADJ = 0x00028c18, + PA_SC_AA_SAMPLE_LOCS_MCTX = 0x00028c1c, +/* S0_X_mask = 0x0f << 0, */ +/* S0_X_shift = 0, */ +/* S0_Y_mask = 0x0f << 4, */ +/* S0_Y_shift = 4, */ +/* S1_X_mask = 0x0f << 8, */ +/* S1_X_shift = 8, */ +/* S1_Y_mask = 0x0f << 12, */ +/* S1_Y_shift = 12, */ +/* S2_X_mask = 0x0f << 16, */ +/* S2_X_shift = 16, */ +/* S2_Y_mask = 0x0f << 20, */ +/* S2_Y_shift = 20, */ +/* S3_X_mask = 0x0f << 24, */ +/* S3_X_shift = 24, */ +/* S3_Y_mask = 0x0f << 28, */ +/* S3_Y_shift = 28, */ + PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX = 0x00028c20, +/* S4_X_mask = 0x0f << 0, */ +/* S4_X_shift = 0, */ +/* S4_Y_mask = 0x0f << 4, */ +/* S4_Y_shift = 4, */ +/* S5_X_mask = 0x0f << 8, */ +/* S5_X_shift = 8, */ +/* S5_Y_mask = 0x0f << 12, */ +/* S5_Y_shift = 12, */ +/* S6_X_mask = 0x0f << 16, */ +/* S6_X_shift = 16, */ +/* S6_Y_mask = 0x0f << 20, */ +/* S6_Y_shift = 20, */ +/* S7_X_mask = 0x0f << 24, */ +/* S7_X_shift = 24, */ +/* S7_Y_mask = 0x0f << 28, */ +/* S7_Y_shift = 28, */ + CB_CLRCMP_CONTROL = 0x00028c30, + CLRCMP_FCN_SRC_mask = 0x07 << 0, + CLRCMP_FCN_SRC_shift = 0, + CLRCMP_DRAW_ALWAYS = 0x00, + CLRCMP_DRAW_NEVER = 0x01, + CLRCMP_DRAW_ON_NEQ = 0x04, + CLRCMP_DRAW_ON_EQ = 0x05, + CLRCMP_FCN_DST_mask = 0x07 << 8, + CLRCMP_FCN_DST_shift = 8, +/* CLRCMP_DRAW_ALWAYS = 0x00, */ +/* CLRCMP_DRAW_NEVER = 0x01, */ +/* CLRCMP_DRAW_ON_NEQ = 0x04, */ +/* CLRCMP_DRAW_ON_EQ = 0x05, */ + CLRCMP_FCN_SEL_mask = 0x03 << 24, + CLRCMP_FCN_SEL_shift = 24, + CLRCMP_SEL_DST = 0x00, + CLRCMP_SEL_SRC = 0x01, + CLRCMP_SEL_AND = 0x02, + CB_CLRCMP_SRC = 0x00028c34, + CB_CLRCMP_DST = 0x00028c38, + CB_CLRCMP_MSK = 0x00028c3c, + PA_SC_AA_MASK = 0x00028c48, + VGT_VERTEX_REUSE_BLOCK_CNTL = 0x00028c58, + VTX_REUSE_DEPTH_mask = 0xff << 0, + VTX_REUSE_DEPTH_shift = 0, + VGT_OUT_DEALLOC_CNTL = 0x00028c5c, + DEALLOC_DIST_mask = 0x7f << 0, + DEALLOC_DIST_shift = 0, + DB_RENDER_CONTROL = 0x00028d0c, + DEPTH_CLEAR_ENABLE_bit = 1 << 0, + STENCIL_CLEAR_ENABLE_bit = 1 << 1, + DEPTH_COPY_bit = 1 << 2, + STENCIL_COPY_bit = 1 << 3, + RESUMMARIZE_ENABLE_bit = 1 << 4, + STENCIL_COMPRESS_DISABLE_bit = 1 << 5, + DEPTH_COMPRESS_DISABLE_bit = 1 << 6, + COPY_CENTROID_bit = 1 << 7, + COPY_SAMPLE_mask = 0x07 << 8, + COPY_SAMPLE_shift = 8, + ZPASS_INCREMENT_DISABLE_bit = 1 << 11, + DB_RENDER_OVERRIDE = 0x00028d10, + FORCE_HIZ_ENABLE_mask = 0x03 << 0, + FORCE_HIZ_ENABLE_shift = 0, + FORCE_OFF = 0x00, + FORCE_ENABLE = 0x01, + FORCE_DISABLE = 0x02, + FORCE_RESERVED = 0x03, + FORCE_HIS_ENABLE0_mask = 0x03 << 2, + FORCE_HIS_ENABLE0_shift = 2, +/* FORCE_OFF = 0x00, */ +/* FORCE_ENABLE = 0x01, */ +/* FORCE_DISABLE = 0x02, */ +/* FORCE_RESERVED = 0x03, */ + FORCE_HIS_ENABLE1_mask = 0x03 << 4, + FORCE_HIS_ENABLE1_shift = 4, +/* FORCE_OFF = 0x00, */ +/* FORCE_ENABLE = 0x01, */ +/* FORCE_DISABLE = 0x02, */ +/* FORCE_RESERVED = 0x03, */ + FORCE_SHADER_Z_ORDER_bit = 1 << 6, + FAST_Z_DISABLE_bit = 1 << 7, + FAST_STENCIL_DISABLE_bit = 1 << 8, + NOOP_CULL_DISABLE_bit = 1 << 9, + FORCE_COLOR_KILL_bit = 1 << 10, + FORCE_Z_READ_bit = 1 << 11, + FORCE_STENCIL_READ_bit = 1 << 12, + FORCE_FULL_Z_RANGE_mask = 0x03 << 13, + FORCE_FULL_Z_RANGE_shift = 13, +/* FORCE_OFF = 0x00, */ +/* FORCE_ENABLE = 0x01, */ +/* FORCE_DISABLE = 0x02, */ +/* FORCE_RESERVED = 0x03, */ + FORCE_QC_SMASK_CONFLICT_bit = 1 << 15, + DISABLE_VIEWPORT_CLAMP_bit = 1 << 16, + IGNORE_SC_ZRANGE_bit = 1 << 17, + DB_HTILE_SURFACE = 0x00028d24, + HTILE_WIDTH_bit = 1 << 0, + HTILE_HEIGHT_bit = 1 << 1, + LINEAR_bit = 1 << 2, + FULL_CACHE_bit = 1 << 3, + HTILE_USES_PRELOAD_WIN_bit = 1 << 4, + PRELOAD_bit = 1 << 5, + PREFETCH_WIDTH_mask = 0x3f << 6, + PREFETCH_WIDTH_shift = 6, + PREFETCH_HEIGHT_mask = 0x3f << 12, + PREFETCH_HEIGHT_shift = 12, + DB_SRESULTS_COMPARE_STATE1 = 0x00028d2c, + COMPAREFUNC1_mask = 0x07 << 0, + COMPAREFUNC1_shift = 0, +/* REF_NEVER = 0x00, */ +/* REF_LESS = 0x01, */ +/* REF_EQUAL = 0x02, */ +/* REF_LEQUAL = 0x03, */ +/* REF_GREATER = 0x04, */ +/* REF_NOTEQUAL = 0x05, */ +/* REF_GEQUAL = 0x06, */ +/* REF_ALWAYS = 0x07, */ + COMPAREVALUE1_mask = 0xff << 4, + COMPAREVALUE1_shift = 4, + COMPAREMASK1_mask = 0xff << 12, + COMPAREMASK1_shift = 12, + ENABLE1_bit = 1 << 24, + DB_PRELOAD_CONTROL = 0x00028d30, + START_X_mask = 0xff << 0, + START_X_shift = 0, + START_Y_mask = 0xff << 8, + START_Y_shift = 8, + MAX_X_mask = 0xff << 16, + MAX_X_shift = 16, + MAX_Y_mask = 0xff << 24, + MAX_Y_shift = 24, + DB_PREFETCH_LIMIT = 0x00028d34, + DEPTH_HEIGHT_TILE_MAX_mask = 0x3ff << 0, + DEPTH_HEIGHT_TILE_MAX_shift = 0, + PA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x00028df8, + POLY_OFFSET_NEG_NUM_DB_BITS_mask = 0xff << 0, + POLY_OFFSET_NEG_NUM_DB_BITS_shift = 0, + POLY_OFFSET_DB_IS_FLOAT_FMT_bit = 1 << 8, + PA_SU_POLY_OFFSET_CLAMP = 0x00028dfc, + PA_SU_POLY_OFFSET_FRONT_SCALE = 0x00028e00, + PA_SU_POLY_OFFSET_FRONT_OFFSET = 0x00028e04, + PA_SU_POLY_OFFSET_BACK_SCALE = 0x00028e08, + PA_SU_POLY_OFFSET_BACK_OFFSET = 0x00028e0c, + PA_CL_POINT_X_RAD = 0x00028e10, + PA_CL_POINT_Y_RAD = 0x00028e14, + PA_CL_POINT_SIZE = 0x00028e18, + PA_CL_POINT_CULL_RAD = 0x00028e1c, + PA_CL_UCP_0_X = 0x00028e20, + PA_CL_UCP_0_X_num = 6, + PA_CL_UCP_0_X_offset = 16, + PA_CL_UCP_0_Y = 0x00028e24, + PA_CL_UCP_0_Y_num = 6, + PA_CL_UCP_0_Y_offset = 16, + PA_CL_UCP_0_Z = 0x00028e28, + PA_CL_UCP_0_Z_num = 6, + PA_CL_UCP_0_Z_offset = 16, + SQ_ALU_CONSTANT0_0 = 0x00030000, + SQ_ALU_CONSTANT1_0 = 0x00030004, + SQ_ALU_CONSTANT2_0 = 0x00030008, + SQ_ALU_CONSTANT3_0 = 0x0003000c, + SQ_VTX_CONSTANT_WORD0_0 = 0x00038000, + SQ_TEX_RESOURCE_WORD0_0 = 0x00038000, + DIM_mask = 0x07 << 0, + DIM_shift = 0, + SQ_TEX_DIM_1D = 0x00, + SQ_TEX_DIM_2D = 0x01, + SQ_TEX_DIM_3D = 0x02, + SQ_TEX_DIM_CUBEMAP = 0x03, + SQ_TEX_DIM_1D_ARRAY = 0x04, + SQ_TEX_DIM_2D_ARRAY = 0x05, + SQ_TEX_DIM_2D_MSAA = 0x06, + SQ_TEX_DIM_2D_ARRAY_MSAA = 0x07, + SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask = 0x0f << 3, + SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift = 3, + TILE_TYPE_bit = 1 << 7, + PITCH_mask = 0x7ff << 8, + PITCH_shift = 8, + TEX_WIDTH_mask = 0x1fff << 19, + TEX_WIDTH_shift = 19, + SQ_VTX_CONSTANT_WORD1_0 = 0x00038004, + SQ_TEX_RESOURCE_WORD1_0 = 0x00038004, + TEX_HEIGHT_mask = 0x1fff << 0, + TEX_HEIGHT_shift = 0, + TEX_DEPTH_mask = 0x1fff << 13, + TEX_DEPTH_shift = 13, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask = 0x3f << 26, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift = 26, + SQ_VTX_CONSTANT_WORD2_0 = 0x00038008, + BASE_ADDRESS_HI_mask = 0xff << 0, + BASE_ADDRESS_HI_shift = 0, + SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask = 0x7ff << 8, + SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift = 8, + SQ_VTX_CONSTANT_WORD2_0__CLAMP_X_bit = 1 << 19, + SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, + SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift = 20, + SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask = 0x03 << 26, + SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift = 26, +/* SQ_NUM_FORMAT_NORM = 0x00, */ +/* SQ_NUM_FORMAT_INT = 0x01, */ +/* SQ_NUM_FORMAT_SCALED = 0x02, */ + SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit = 1 << 28, + SQ_VTX_CONSTANT_WORD2_0__SRF_MODE_ALL_bit = 1 << 29, + SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_mask = 0x03 << 30, + SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift = 30, +/* SQ_ENDIAN_NONE = 0x00, */ +/* SQ_ENDIAN_8IN16 = 0x01, */ +/* SQ_ENDIAN_8IN32 = 0x02, */ + SQ_TEX_RESOURCE_WORD2_0 = 0x00038008, + SQ_VTX_CONSTANT_WORD3_0 = 0x0003800c, + MEM_REQUEST_SIZE_mask = 0x03 << 0, + MEM_REQUEST_SIZE_shift = 0, + SQ_TEX_RESOURCE_WORD3_0 = 0x0003800c, + SQ_TEX_RESOURCE_WORD4_0 = 0x00038010, + FORMAT_COMP_X_mask = 0x03 << 0, + FORMAT_COMP_X_shift = 0, + SQ_FORMAT_COMP_UNSIGNED = 0x00, + SQ_FORMAT_COMP_SIGNED = 0x01, + SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, + FORMAT_COMP_Y_mask = 0x03 << 2, + FORMAT_COMP_Y_shift = 2, +/* SQ_FORMAT_COMP_UNSIGNED = 0x00, */ +/* SQ_FORMAT_COMP_SIGNED = 0x01, */ +/* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */ + FORMAT_COMP_Z_mask = 0x03 << 4, + FORMAT_COMP_Z_shift = 4, +/* SQ_FORMAT_COMP_UNSIGNED = 0x00, */ +/* SQ_FORMAT_COMP_SIGNED = 0x01, */ +/* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */ + FORMAT_COMP_W_mask = 0x03 << 6, + FORMAT_COMP_W_shift = 6, +/* SQ_FORMAT_COMP_UNSIGNED = 0x00, */ +/* SQ_FORMAT_COMP_SIGNED = 0x01, */ +/* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */ + SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_mask = 0x03 << 8, + SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift = 8, +/* SQ_NUM_FORMAT_NORM = 0x00, */ +/* SQ_NUM_FORMAT_INT = 0x01, */ +/* SQ_NUM_FORMAT_SCALED = 0x02, */ + SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit = 1 << 10, + SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit = 1 << 11, + SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_mask = 0x03 << 12, + SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift = 12, +/* SQ_ENDIAN_NONE = 0x00, */ +/* SQ_ENDIAN_8IN16 = 0x01, */ +/* SQ_ENDIAN_8IN32 = 0x02, */ + REQUEST_SIZE_mask = 0x03 << 14, + REQUEST_SIZE_shift = 14, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask = 0x07 << 16, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift = 16, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask = 0x07 << 19, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift = 19, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask = 0x07 << 22, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift = 22, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask = 0x07 << 25, + SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift = 25, +/* SQ_SEL_X = 0x00, */ +/* SQ_SEL_Y = 0x01, */ +/* SQ_SEL_Z = 0x02, */ +/* SQ_SEL_W = 0x03, */ +/* SQ_SEL_0 = 0x04, */ +/* SQ_SEL_1 = 0x05, */ + BASE_LEVEL_mask = 0x0f << 28, + BASE_LEVEL_shift = 28, + SQ_TEX_RESOURCE_WORD5_0 = 0x00038014, + LAST_LEVEL_mask = 0x0f << 0, + LAST_LEVEL_shift = 0, + BASE_ARRAY_mask = 0x1fff << 4, + BASE_ARRAY_shift = 4, + LAST_ARRAY_mask = 0x1fff << 17, + LAST_ARRAY_shift = 17, + SQ_TEX_RESOURCE_WORD6_0 = 0x00038018, + MPEG_CLAMP_mask = 0x03 << 0, + MPEG_CLAMP_shift = 0, + SQ_TEX_MPEG_CLAMP_OFF = 0x00, + SQ_TEX_MPEG_9 = 0x01, + SQ_TEX_MPEG_10 = 0x02, + PERF_MODULATION_mask = 0x07 << 5, + PERF_MODULATION_shift = 5, + INTERLACED_bit = 1 << 8, + SQ_TEX_RESOURCE_WORD6_0__TYPE_mask = 0x03 << 30, + SQ_TEX_RESOURCE_WORD6_0__TYPE_shift = 30, + SQ_TEX_VTX_INVALID_TEXTURE = 0x00, + SQ_TEX_VTX_INVALID_BUFFER = 0x01, + SQ_TEX_VTX_VALID_TEXTURE = 0x02, + SQ_TEX_VTX_VALID_BUFFER = 0x03, + SQ_VTX_CONSTANT_WORD6_0 = 0x00038018, + SQ_VTX_CONSTANT_WORD6_0__TYPE_mask = 0x03 << 30, + SQ_VTX_CONSTANT_WORD6_0__TYPE_shift = 30, +/* SQ_TEX_VTX_INVALID_TEXTURE = 0x00, */ +/* SQ_TEX_VTX_INVALID_BUFFER = 0x01, */ +/* SQ_TEX_VTX_VALID_TEXTURE = 0x02, */ +/* SQ_TEX_VTX_VALID_BUFFER = 0x03, */ + SQ_TEX_SAMPLER_WORD0_0 = 0x0003c000, + SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask = 0x07 << 0, + SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift = 0, + SQ_TEX_WRAP = 0x00, + SQ_TEX_MIRROR = 0x01, + SQ_TEX_CLAMP_LAST_TEXEL = 0x02, + SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, + SQ_TEX_CLAMP_HALF_BORDER = 0x04, + SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, + SQ_TEX_CLAMP_BORDER = 0x06, + SQ_TEX_MIRROR_ONCE_BORDER = 0x07, + CLAMP_Y_mask = 0x07 << 3, + CLAMP_Y_shift = 3, +/* SQ_TEX_WRAP = 0x00, */ +/* SQ_TEX_MIRROR = 0x01, */ +/* SQ_TEX_CLAMP_LAST_TEXEL = 0x02, */ +/* SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, */ +/* SQ_TEX_CLAMP_HALF_BORDER = 0x04, */ +/* SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, */ +/* SQ_TEX_CLAMP_BORDER = 0x06, */ +/* SQ_TEX_MIRROR_ONCE_BORDER = 0x07, */ + CLAMP_Z_mask = 0x07 << 6, + CLAMP_Z_shift = 6, +/* SQ_TEX_WRAP = 0x00, */ +/* SQ_TEX_MIRROR = 0x01, */ +/* SQ_TEX_CLAMP_LAST_TEXEL = 0x02, */ +/* SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, */ +/* SQ_TEX_CLAMP_HALF_BORDER = 0x04, */ +/* SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, */ +/* SQ_TEX_CLAMP_BORDER = 0x06, */ +/* SQ_TEX_MIRROR_ONCE_BORDER = 0x07, */ + XY_MAG_FILTER_mask = 0x07 << 9, + XY_MAG_FILTER_shift = 9, + SQ_TEX_XY_FILTER_POINT = 0x00, + SQ_TEX_XY_FILTER_BILINEAR = 0x01, + SQ_TEX_XY_FILTER_BICUBIC = 0x02, + XY_MIN_FILTER_mask = 0x07 << 12, + XY_MIN_FILTER_shift = 12, +/* SQ_TEX_XY_FILTER_POINT = 0x00, */ +/* SQ_TEX_XY_FILTER_BILINEAR = 0x01, */ +/* SQ_TEX_XY_FILTER_BICUBIC = 0x02, */ + Z_FILTER_mask = 0x03 << 15, + Z_FILTER_shift = 15, + SQ_TEX_Z_FILTER_NONE = 0x00, + SQ_TEX_Z_FILTER_POINT = 0x01, + SQ_TEX_Z_FILTER_LINEAR = 0x02, + MIP_FILTER_mask = 0x03 << 17, + MIP_FILTER_shift = 17, +/* SQ_TEX_Z_FILTER_NONE = 0x00, */ +/* SQ_TEX_Z_FILTER_POINT = 0x01, */ +/* SQ_TEX_Z_FILTER_LINEAR = 0x02, */ + BORDER_COLOR_TYPE_mask = 0x03 << 22, + BORDER_COLOR_TYPE_shift = 22, + SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00, + SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x01, + SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x02, + SQ_TEX_BORDER_COLOR_REGISTER = 0x03, + POINT_SAMPLING_CLAMP_bit = 1 << 24, + TEX_ARRAY_OVERRIDE_bit = 1 << 25, + DEPTH_COMPARE_FUNCTION_mask = 0x07 << 26, + DEPTH_COMPARE_FUNCTION_shift = 26, + SQ_TEX_DEPTH_COMPARE_NEVER = 0x00, + SQ_TEX_DEPTH_COMPARE_LESS = 0x01, + SQ_TEX_DEPTH_COMPARE_EQUAL = 0x02, + SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x03, + SQ_TEX_DEPTH_COMPARE_GREATER = 0x04, + SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x05, + SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x06, + SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x07, + CHROMA_KEY_mask = 0x03 << 29, + CHROMA_KEY_shift = 29, + SQ_TEX_CHROMA_KEY_DISABLED = 0x00, + SQ_TEX_CHROMA_KEY_KILL = 0x01, + SQ_TEX_CHROMA_KEY_BLEND = 0x02, + LOD_USES_MINOR_AXIS_bit = 1 << 31, + SQ_TEX_SAMPLER_WORD1_0 = 0x0003c004, + MIN_LOD_mask = 0x3ff << 0, + MIN_LOD_shift = 0, + MAX_LOD_mask = 0x3ff << 10, + MAX_LOD_shift = 10, + SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS_mask = 0xfff << 20, + SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS_shift = 20, + SQ_TEX_SAMPLER_WORD2_0 = 0x0003c008, + LOD_BIAS_SEC_mask = 0xfff << 0, + LOD_BIAS_SEC_shift = 0, + MC_COORD_TRUNCATE_bit = 1 << 12, + SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA_bit = 1 << 13, + HIGH_PRECISION_FILTER_bit = 1 << 14, + PERF_MIP_mask = 0x07 << 15, + PERF_MIP_shift = 15, + PERF_Z_mask = 0x03 << 18, + PERF_Z_shift = 18, + FETCH_4_bit = 1 << 26, + SAMPLE_IS_PCF_bit = 1 << 27, + SQ_TEX_SAMPLER_WORD2_0__TYPE_bit = 1 << 31, + SQ_VTX_BASE_VTX_LOC = 0x0003cff0, + SQ_VTX_START_INST_LOC = 0x0003cff4, + SQ_LOOP_CONST_DX10_0 = 0x0003e200, + SQ_LOOP_CONST_0 = 0x0003e200, + SQ_LOOP_CONST_0__COUNT_mask = 0xfff << 0, + SQ_LOOP_CONST_0__COUNT_shift = 0, + INIT_mask = 0xfff << 12, + INIT_shift = 12, + INC_mask = 0xff << 24, + INC_shift = 24, + SQ_BOOL_CONST_0 = 0x0003e380, + SQ_BOOL_CONST_0_num = 3, + +} ; + +#endif /* _AUTOREGS */ + diff --git a/src/mesa/drivers/dri/r600/r600_reg_r6xx.h b/src/mesa/drivers/dri/r600/r600_reg_r6xx.h new file mode 100644 index 0000000000..f7702c46de --- /dev/null +++ b/src/mesa/drivers/dri/r600/r600_reg_r6xx.h @@ -0,0 +1,492 @@ +/* + * RadeonHD R6xx, R7xx Register documentation + * + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2009 Matthias Hopf + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _R600_REG_R6xx_H_ +#define _R600_REG_R6xx_H_ + +/* + * Registers for R6xx chips that are not documented yet + */ + +enum { + + MM_INDEX = 0x0000, + MM_DATA = 0x0004, + + SRBM_STATUS = 0x0e50, + RLC_RQ_PENDING_bit = 1 << 3, + RCU_RQ_PENDING_bit = 1 << 4, + GRBM_RQ_PENDING_bit = 1 << 5, + HI_RQ_PENDING_bit = 1 << 6, + IO_EXTERN_SIGNAL_bit = 1 << 7, + VMC_BUSY_bit = 1 << 8, + MCB_BUSY_bit = 1 << 9, + MCDZ_BUSY_bit = 1 << 10, + MCDY_BUSY_bit = 1 << 11, + MCDX_BUSY_bit = 1 << 12, + MCDW_BUSY_bit = 1 << 13, + SEM_BUSY_bit = 1 << 14, + SRBM_STATUS__RLC_BUSY_bit = 1 << 15, + PDMA_BUSY_bit = 1 << 16, + IH_BUSY_bit = 1 << 17, + CSC_BUSY_bit = 1 << 20, + CMC7_BUSY_bit = 1 << 21, + CMC6_BUSY_bit = 1 << 22, + CMC5_BUSY_bit = 1 << 23, + CMC4_BUSY_bit = 1 << 24, + CMC3_BUSY_bit = 1 << 25, + CMC2_BUSY_bit = 1 << 26, + CMC1_BUSY_bit = 1 << 27, + CMC0_BUSY_bit = 1 << 28, + BIF_BUSY_bit = 1 << 29, + IDCT_BUSY_bit = 1 << 30, + + SRBM_READ_ERROR = 0x0e98, + READ_ADDRESS_mask = 0xffff << 2, + READ_ADDRESS_shift = 2, + READ_REQUESTER_HI_bit = 1 << 24, + READ_REQUESTER_GRBM_bit = 1 << 25, + READ_REQUESTER_RCU_bit = 1 << 26, + READ_REQUESTER_RLC_bit = 1 << 27, + READ_ERROR_bit = 1 << 31, + + SRBM_INT_STATUS = 0x0ea4, + RDERR_INT_STAT_bit = 1 << 0, + GFX_CNTX_SWITCH_INT_STAT_bit = 1 << 1, + SRBM_INT_ACK = 0x0ea8, + RDERR_INT_ACK_bit = 1 << 0, + GFX_CNTX_SWITCH_INT_ACK_bit = 1 << 1, + + R6XX_MC_VM_FB_LOCATION = 0x2180, + + VENDOR_DEVICE_ID = 0x4000, + + D1GRPH_PRIMARY_SURFACE_ADDRESS = 0x6110, + D1GRPH_PITCH = 0x6120, + D1GRPH_Y_END = 0x6138, + + GRBM_STATUS = 0x8010, + CMDFIFO_AVAIL_mask = 0x1f << 0, + CMDFIFO_AVAIL_shift = 0, + SRBM_RQ_PENDING_bit = 1 << 5, + CP_RQ_PENDING_bit = 1 << 6, + CF_RQ_PENDING_bit = 1 << 7, + PF_RQ_PENDING_bit = 1 << 8, + GRBM_EE_BUSY_bit = 1 << 10, + GRBM_STATUS__VC_BUSY_bit = 1 << 11, + DB03_CLEAN_bit = 1 << 12, + CB03_CLEAN_bit = 1 << 13, + VGT_BUSY_NO_DMA_bit = 1 << 16, + GRBM_STATUS__VGT_BUSY_bit = 1 << 17, + TA03_BUSY_bit = 1 << 18, + GRBM_STATUS__TC_BUSY_bit = 1 << 19, + SX_BUSY_bit = 1 << 20, + SH_BUSY_bit = 1 << 21, + SPI03_BUSY_bit = 1 << 22, + SMX_BUSY_bit = 1 << 23, + SC_BUSY_bit = 1 << 24, + PA_BUSY_bit = 1 << 25, + DB03_BUSY_bit = 1 << 26, + CR_BUSY_bit = 1 << 27, + CP_COHERENCY_BUSY_bit = 1 << 28, + GRBM_STATUS__CP_BUSY_bit = 1 << 29, + CB03_BUSY_bit = 1 << 30, + GUI_ACTIVE_bit = 1 << 31, + GRBM_STATUS2 = 0x8014, + CR_CLEAN_bit = 1 << 0, + SMX_CLEAN_bit = 1 << 1, + SPI0_BUSY_bit = 1 << 8, + SPI1_BUSY_bit = 1 << 9, + SPI2_BUSY_bit = 1 << 10, + SPI3_BUSY_bit = 1 << 11, + TA0_BUSY_bit = 1 << 12, + TA1_BUSY_bit = 1 << 13, + TA2_BUSY_bit = 1 << 14, + TA3_BUSY_bit = 1 << 15, + DB0_BUSY_bit = 1 << 16, + DB1_BUSY_bit = 1 << 17, + DB2_BUSY_bit = 1 << 18, + DB3_BUSY_bit = 1 << 19, + CB0_BUSY_bit = 1 << 20, + CB1_BUSY_bit = 1 << 21, + CB2_BUSY_bit = 1 << 22, + CB3_BUSY_bit = 1 << 23, + GRBM_SOFT_RESET = 0x8020, + SOFT_RESET_CP_bit = 1 << 0, + SOFT_RESET_CB_bit = 1 << 1, + SOFT_RESET_CR_bit = 1 << 2, + SOFT_RESET_DB_bit = 1 << 3, + SOFT_RESET_PA_bit = 1 << 5, + SOFT_RESET_SC_bit = 1 << 6, + SOFT_RESET_SMX_bit = 1 << 7, + SOFT_RESET_SPI_bit = 1 << 8, + SOFT_RESET_SH_bit = 1 << 9, + SOFT_RESET_SX_bit = 1 << 10, + SOFT_RESET_TC_bit = 1 << 11, + SOFT_RESET_TA_bit = 1 << 12, + SOFT_RESET_VC_bit = 1 << 13, + SOFT_RESET_VGT_bit = 1 << 14, + SOFT_RESET_GRBM_GCA_bit = 1 << 15, + + WAIT_UNTIL = 0x8040, + WAIT_CP_DMA_IDLE_bit = 1 << 8, + WAIT_CMDFIFO_bit = 1 << 10, + WAIT_2D_IDLE_bit = 1 << 14, + WAIT_3D_IDLE_bit = 1 << 15, + WAIT_2D_IDLECLEAN_bit = 1 << 16, + WAIT_3D_IDLECLEAN_bit = 1 << 17, + WAIT_EXTERN_SIG_bit = 1 << 19, + CMDFIFO_ENTRIES_mask = 0x1f << 20, + CMDFIFO_ENTRIES_shift = 20, + + GRBM_READ_ERROR = 0x8058, +/* READ_ADDRESS_mask = 0xffff << 2, */ +/* READ_ADDRESS_shift = 2, */ + READ_REQUESTER_SRBM_bit = 1 << 28, + READ_REQUESTER_CP_bit = 1 << 29, + READ_REQUESTER_WU_POLL_bit = 1 << 30, +/* READ_ERROR_bit = 1 << 31, */ + + SCRATCH_REG0 = 0x8500, + SCRATCH_REG1 = 0x8504, + SCRATCH_REG2 = 0x8508, + SCRATCH_REG3 = 0x850c, + SCRATCH_REG4 = 0x8510, + SCRATCH_REG5 = 0x8514, + SCRATCH_REG6 = 0x8518, + SCRATCH_REG7 = 0x851c, + SCRATCH_UMSK = 0x8540, + SCRATCH_ADDR = 0x8544, + + CP_COHER_CNTL = 0x85f0, + DEST_BASE_0_ENA_bit = 1 << 0, + DEST_BASE_1_ENA_bit = 1 << 1, + SO0_DEST_BASE_ENA_bit = 1 << 2, + SO1_DEST_BASE_ENA_bit = 1 << 3, + SO2_DEST_BASE_ENA_bit = 1 << 4, + SO3_DEST_BASE_ENA_bit = 1 << 5, + CB0_DEST_BASE_ENA_bit = 1 << 6, + CB1_DEST_BASE_ENA_bit = 1 << 7, + CB2_DEST_BASE_ENA_bit = 1 << 8, + CB3_DEST_BASE_ENA_bit = 1 << 9, + CB4_DEST_BASE_ENA_bit = 1 << 10, + CB5_DEST_BASE_ENA_bit = 1 << 11, + CB6_DEST_BASE_ENA_bit = 1 << 12, + CB7_DEST_BASE_ENA_bit = 1 << 13, + DB_DEST_BASE_ENA_bit = 1 << 14, + CR_DEST_BASE_ENA_bit = 1 << 15, + TC_ACTION_ENA_bit = 1 << 23, + VC_ACTION_ENA_bit = 1 << 24, + CB_ACTION_ENA_bit = 1 << 25, + DB_ACTION_ENA_bit = 1 << 26, + SH_ACTION_ENA_bit = 1 << 27, + SMX_ACTION_ENA_bit = 1 << 28, + CR0_ACTION_ENA_bit = 1 << 29, + CR1_ACTION_ENA_bit = 1 << 30, + CR2_ACTION_ENA_bit = 1 << 31, + CP_COHER_SIZE = 0x85f4, + CP_COHER_BASE = 0x85f8, + CP_COHER_STATUS = 0x85fc, + MATCHING_GFX_CNTX_mask = 0xff << 0, + MATCHING_GFX_CNTX_shift = 0, + MATCHING_CR_CNTX_mask = 0xffff << 8, + MATCHING_CR_CNTX_shift = 8, + STATUS_bit = 1 << 31, + + CP_STALLED_STAT1 = 0x8674, + RBIU_TO_DMA_NOT_RDY_TO_RCV_bit = 1 << 0, + RBIU_TO_IBS_NOT_RDY_TO_RCV_bit = 1 << 1, + RBIU_TO_SEM_NOT_RDY_TO_RCV_bit = 1 << 2, + RBIU_TO_2DREGS_NOT_RDY_TO_RCV_bit = 1 << 3, + RBIU_TO_MEMWR_NOT_RDY_TO_RCV_bit = 1 << 4, + RBIU_TO_MEMRD_NOT_RDY_TO_RCV_bit = 1 << 5, + RBIU_TO_EOPD_NOT_RDY_TO_RCV_bit = 1 << 6, + RBIU_TO_RECT_NOT_RDY_TO_RCV_bit = 1 << 7, + RBIU_TO_STRMO_NOT_RDY_TO_RCV_bit = 1 << 8, + RBIU_TO_PSTAT_NOT_RDY_TO_RCV_bit = 1 << 9, + MIU_WAITING_ON_RDREQ_FREE_bit = 1 << 16, + MIU_WAITING_ON_WRREQ_FREE_bit = 1 << 17, + MIU_NEEDS_AVAIL_WRREQ_PHASE_bit = 1 << 18, + RCIU_WAITING_ON_GRBM_FREE_bit = 1 << 24, + RCIU_WAITING_ON_VGT_FREE_bit = 1 << 25, + RCIU_STALLED_ON_ME_READ_bit = 1 << 26, + RCIU_STALLED_ON_DMA_READ_bit = 1 << 27, + RCIU_HALTED_BY_REG_VIOLATION_bit = 1 << 28, + CP_STALLED_STAT2 = 0x8678, + PFP_TO_CSF_NOT_RDY_TO_RCV_bit = 1 << 0, + PFP_TO_MEQ_NOT_RDY_TO_RCV_bit = 1 << 1, + PFP_TO_VGT_NOT_RDY_TO_RCV_bit = 1 << 2, + PFP_HALTED_BY_INSTR_VIOLATION_bit = 1 << 3, + MULTIPASS_IB_PENDING_IN_PFP_bit = 1 << 4, + ME_BRUSH_WC_NOT_RDY_TO_RCV_bit = 1 << 8, + ME_STALLED_ON_BRUSH_LOGIC_bit = 1 << 9, + CR_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 10, + GFX_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 11, + ME_RCIU_NOT_RDY_TO_RCV_bit = 1 << 12, + ME_TO_CONST_NOT_RDY_TO_RCV_bit = 1 << 13, + ME_WAITING_DATA_FROM_PFP_bit = 1 << 14, + ME_WAITING_ON_PARTIAL_FLUSH_bit = 1 << 15, + RECT_FIFO_NEEDS_CR_RECT_DONE_bit = 1 << 16, + RECT_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 17, + EOPD_FIFO_NEEDS_SC_EOP_DONE_bit = 1 << 18, + EOPD_FIFO_NEEDS_SMX_EOP_DONE_bit = 1 << 19, + EOPD_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 20, + EOPD_FIFO_NEEDS_SIGNAL_SEM_bit = 1 << 21, + SO_NUMPRIM_FIFO_NEEDS_SOADDR_bit = 1 << 22, + SO_NUMPRIM_FIFO_NEEDS_NUMPRIM_bit = 1 << 23, + PIPE_STATS_FIFO_NEEDS_SAMPLE_bit = 1 << 24, + SURF_SYNC_NEEDS_IDLE_CNTXS_bit = 1 << 30, + SURF_SYNC_NEEDS_ALL_CLEAN_bit = 1 << 31, + CP_BUSY_STAT = 0x867c, + REG_BUS_FIFO_BUSY_bit = 1 << 0, + RING_FETCHING_DATA_bit = 1 << 1, + INDR1_FETCHING_DATA_bit = 1 << 2, + INDR2_FETCHING_DATA_bit = 1 << 3, + STATE_FETCHING_DATA_bit = 1 << 4, + PRED_FETCHING_DATA_bit = 1 << 5, + COHER_CNTR_NEQ_ZERO_bit = 1 << 6, + PFP_PARSING_PACKETS_bit = 1 << 7, + ME_PARSING_PACKETS_bit = 1 << 8, + RCIU_PFP_BUSY_bit = 1 << 9, + RCIU_ME_BUSY_bit = 1 << 10, + OUTSTANDING_READ_TAGS_bit = 1 << 11, + SEM_CMDFIFO_NOT_EMPTY_bit = 1 << 12, + SEM_FAILED_AND_HOLDING_bit = 1 << 13, + SEM_POLLING_FOR_PASS_bit = 1 << 14, + _3D_BUSY_bit = 1 << 15, + _2D_BUSY_bit = 1 << 16, + CP_STAT = 0x8680, + CSF_RING_BUSY_bit = 1 << 0, + CSF_WPTR_POLL_BUSY_bit = 1 << 1, + CSF_INDIRECT1_BUSY_bit = 1 << 2, + CSF_INDIRECT2_BUSY_bit = 1 << 3, + CSF_STATE_BUSY_bit = 1 << 4, + CSF_PREDICATE_BUSY_bit = 1 << 5, + CSF_BUSY_bit = 1 << 6, + MIU_RDREQ_BUSY_bit = 1 << 7, + MIU_WRREQ_BUSY_bit = 1 << 8, + ROQ_RING_BUSY_bit = 1 << 9, + ROQ_INDIRECT1_BUSY_bit = 1 << 10, + ROQ_INDIRECT2_BUSY_bit = 1 << 11, + ROQ_STATE_BUSY_bit = 1 << 12, + ROQ_PREDICATE_BUSY_bit = 1 << 13, + ROQ_ALIGN_BUSY_bit = 1 << 14, + PFP_BUSY_bit = 1 << 15, + MEQ_BUSY_bit = 1 << 16, + ME_BUSY_bit = 1 << 17, + QUERY_BUSY_bit = 1 << 18, + SEMAPHORE_BUSY_bit = 1 << 19, + INTERRUPT_BUSY_bit = 1 << 20, + SURFACE_SYNC_BUSY_bit = 1 << 21, + DMA_BUSY_bit = 1 << 22, + RCIU_BUSY_bit = 1 << 23, + CP_STAT__CP_BUSY_bit = 1 << 31, + + CP_ME_CNTL = 0x86d8, + ME_STATMUX_mask = 0xff << 0, + ME_STATMUX_shift = 0, + ME_HALT_bit = 1 << 28, + CP_ME_STATUS = 0x86dc, + + CP_RB_RPTR = 0x8700, + RB_RPTR_mask = 0xfffff << 0, + RB_RPTR_shift = 0, + CP_RB_WPTR_DELAY = 0x8704, + PRE_WRITE_TIMER_mask = 0xfffffff << 0, + PRE_WRITE_TIMER_shift = 0, + PRE_WRITE_LIMIT_mask = 0x0f << 28, + PRE_WRITE_LIMIT_shift = 28, + + CP_ROQ_RB_STAT = 0x8780, + ROQ_RPTR_PRIMARY_mask = 0x3ff << 0, + ROQ_RPTR_PRIMARY_shift = 0, + ROQ_WPTR_PRIMARY_mask = 0x3ff << 16, + ROQ_WPTR_PRIMARY_shift = 16, + CP_ROQ_IB1_STAT = 0x8784, + ROQ_RPTR_INDIRECT1_mask = 0x3ff << 0, + ROQ_RPTR_INDIRECT1_shift = 0, + ROQ_WPTR_INDIRECT1_mask = 0x3ff << 16, + ROQ_WPTR_INDIRECT1_shift = 16, + CP_ROQ_IB2_STAT = 0x8788, + ROQ_RPTR_INDIRECT2_mask = 0x3ff << 0, + ROQ_RPTR_INDIRECT2_shift = 0, + ROQ_WPTR_INDIRECT2_mask = 0x3ff << 16, + ROQ_WPTR_INDIRECT2_shift = 16, + + CP_MEQ_STAT = 0x8794, + MEQ_RPTR_mask = 0x3ff << 0, + MEQ_RPTR_shift = 0, + MEQ_WPTR_mask = 0x3ff << 16, + MEQ_WPTR_shift = 16, + + CC_GC_SHADER_PIPE_CONFIG = 0x8950, + INACTIVE_QD_PIPES_mask = 0xff << 8, + INACTIVE_QD_PIPES_shift = 8, + R6XX_MAX_QD_PIPES = 8, + INACTIVE_SIMDS_mask = 0xff << 16, + INACTIVE_SIMDS_shift = 16, + R6XX_MAX_SIMDS = 8, + GC_USER_SHADER_PIPE_CONFIG = 0x8954, + + VC_ENHANCE = 0x9714, + DB_DEBUG = 0x9830, + PREZ_MUST_WAIT_FOR_POSTZ_DONE = 1 << 31, + + DB_WATERMARKS = 0x00009838, + DEPTH_FREE_mask = 0x1f << 0, + DEPTH_FREE_shift = 0, + DEPTH_FLUSH_mask = 0x3f << 5, + DEPTH_FLUSH_shift = 5, + FORCE_SUMMARIZE_mask = 0x0f << 11, + FORCE_SUMMARIZE_shift = 11, + DEPTH_PENDING_FREE_mask = 0x1f << 15, + DEPTH_PENDING_FREE_shift = 15, + DEPTH_CACHELINE_FREE_mask = 0x1f << 20, + DEPTH_CACHELINE_FREE_shift = 20, + EARLY_Z_PANIC_DISABLE_bit = 1 << 25, + LATE_Z_PANIC_DISABLE_bit = 1 << 26, + RE_Z_PANIC_DISABLE_bit = 1 << 27, + DB_EXTRA_DEBUG_mask = 0x0f << 28, + DB_EXTRA_DEBUG_shift = 28, + + CP_RB_BASE = 0xc100, + CP_RB_CNTL = 0xc104, + RB_BUFSZ_mask = 0x3f << 0, + CP_RB_WPTR = 0xc114, + RB_WPTR_mask = 0xfffff << 0, + RB_WPTR_shift = 0, + CP_RB_RPTR_WR = 0xc108, + RB_RPTR_WR_mask = 0xfffff << 0, + RB_RPTR_WR_shift = 0, + + CP_INT_STATUS = 0xc128, + DISABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 0, + ENABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 1, + SEM_SIGNAL_INT_STAT_bit = 1 << 18, + CNTX_BUSY_INT_STAT_bit = 1 << 19, + CNTX_EMPTY_INT_STAT_bit = 1 << 20, + WAITMEM_SEM_INT_STAT_bit = 1 << 21, + PRIV_INSTR_INT_STAT_bit = 1 << 22, + PRIV_REG_INT_STAT_bit = 1 << 23, + OPCODE_ERROR_INT_STAT_bit = 1 << 24, + SCRATCH_INT_STAT_bit = 1 << 25, + TIME_STAMP_INT_STAT_bit = 1 << 26, + RESERVED_BIT_ERROR_INT_STAT_bit = 1 << 27, + DMA_INT_STAT_bit = 1 << 28, + IB2_INT_STAT_bit = 1 << 29, + IB1_INT_STAT_bit = 1 << 30, + RB_INT_STAT_bit = 1 << 31, + +// SX_ALPHA_TEST_CONTROL = 0x00028410, + ALPHA_FUNC__REF_NEVER = 0, + ALPHA_FUNC__REF_ALWAYS = 7, +// DB_SHADER_CONTROL = 0x0002880c, + Z_ORDER__EARLY_Z_THEN_LATE_Z = 2, +// PA_SU_SC_MODE_CNTL = 0x00028814, +// POLY_MODE_mask = 0x03 << 3, + POLY_MODE__TRIANGLES = 0, POLY_MODE__DUAL_MODE, +// POLYMODE_FRONT_PTYPE_mask = 0x07 << 5, + POLYMODE_PTYPE__POINTS = 0, POLYMODE_PTYPE__LINES, POLYMODE_PTYPE__TRIANGLES, + PA_SC_AA_SAMPLE_LOCS_8S_WD1_M = 0x00028c20, + DB_SRESULTS_COMPARE_STATE0 = 0x00028d28, /* See autoregs: DB_SRESULTS_COMPARE_STATE1 */ +// DB_SRESULTS_COMPARE_STATE1 = 0x00028d2c, + DB_ALPHA_TO_MASK = 0x00028d44, + ALPHA_TO_MASK_ENABLE = 1 << 0, + ALPHA_TO_MASK_OFFSET0_mask = 0x03 << 8, + ALPHA_TO_MASK_OFFSET0_shift = 8, + ALPHA_TO_MASK_OFFSET1_mask = 0x03 << 8, + ALPHA_TO_MASK_OFFSET1_shift = 10, + ALPHA_TO_MASK_OFFSET2_mask = 0x03 << 8, + ALPHA_TO_MASK_OFFSET2_shift = 12, + ALPHA_TO_MASK_OFFSET3_mask = 0x03 << 8, + ALPHA_TO_MASK_OFFSET3_shift = 14, + +// SQ_VTX_CONSTANT_WORD2_0 = 0x00038008, +// SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, + FMT_INVALID=0, FMT_8, FMT_4_4, FMT_3_3_2, + FMT_16=5, FMT_16_FLOAT, FMT_8_8, + FMT_5_6_5, FMT_6_5_5, FMT_1_5_5_5, FMT_4_4_4_4, + FMT_5_5_5_1, FMT_32, FMT_32_FLOAT, FMT_16_16, + FMT_16_16_FLOAT=16, FMT_8_24, FMT_8_24_FLOAT, FMT_24_8, + FMT_24_8_FLOAT, FMT_10_11_11, FMT_10_11_11_FLOAT, FMT_11_11_10, + FMT_11_11_10_FLOAT, FMT_2_10_10_10, FMT_8_8_8_8, FMT_10_10_10_2, + FMT_X24_8_32_FLOAT, FMT_32_32, FMT_32_32_FLOAT, FMT_16_16_16_16, + FMT_16_16_16_16_FLOAT=32, FMT_32_32_32_32=34, FMT_32_32_32_32_FLOAT, + FMT_1 = 37, FMT_GB_GR=39, + FMT_BG_RG, FMT_32_AS_8, FMT_32_AS_8_8, FMT_5_9_9_9_SHAREDEXP, + FMT_8_8_8, FMT_16_16_16, FMT_16_16_16_FLOAT, FMT_32_32_32, + FMT_32_32_32_FLOAT=48, + +// High level register file lengths + SQ_ALU_CONSTANT = SQ_ALU_CONSTANT0_0, /* 256 PS, 256 VS */ + SQ_ALU_CONSTANT_ps_num = 256, + SQ_ALU_CONSTANT_vs_num = 256, + SQ_ALU_CONSTANT_all_num = 512, + SQ_ALU_CONSTANT_offset = 16, + SQ_ALU_CONSTANT_ps = 0, + SQ_ALU_CONSTANT_vs = SQ_ALU_CONSTANT_ps + SQ_ALU_CONSTANT_ps_num, + SQ_TEX_RESOURCE = SQ_TEX_RESOURCE_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */ + SQ_TEX_RESOURCE_ps_num = 160, + SQ_TEX_RESOURCE_vs_num = 160, + SQ_TEX_RESOURCE_fs_num = 16, + SQ_TEX_RESOURCE_gs_num = 160, + SQ_TEX_RESOURCE_all_num = 496, + SQ_TEX_RESOURCE_offset = 28, + SQ_TEX_RESOURCE_ps = 0, + SQ_TEX_RESOURCE_vs = SQ_TEX_RESOURCE_ps + SQ_TEX_RESOURCE_ps_num, + SQ_TEX_RESOURCE_fs = SQ_TEX_RESOURCE_vs + SQ_TEX_RESOURCE_vs_num, + SQ_TEX_RESOURCE_gs = SQ_TEX_RESOURCE_fs + SQ_TEX_RESOURCE_fs_num, + SQ_VTX_RESOURCE = SQ_VTX_CONSTANT_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */ + SQ_VTX_RESOURCE_ps_num = 160, + SQ_VTX_RESOURCE_vs_num = 160, + SQ_VTX_RESOURCE_fs_num = 16, + SQ_VTX_RESOURCE_gs_num = 160, + SQ_VTX_RESOURCE_all_num = 496, + SQ_VTX_RESOURCE_offset = 28, + SQ_VTX_RESOURCE_ps = 0, + SQ_VTX_RESOURCE_vs = SQ_VTX_RESOURCE_ps + SQ_VTX_RESOURCE_ps_num, + SQ_VTX_RESOURCE_fs = SQ_VTX_RESOURCE_vs + SQ_VTX_RESOURCE_vs_num, + SQ_VTX_RESOURCE_gs = SQ_VTX_RESOURCE_fs + SQ_VTX_RESOURCE_fs_num, + SQ_TEX_SAMPLER_WORD = SQ_TEX_SAMPLER_WORD0_0, /* 18 per PS, VS, GS */ + SQ_TEX_SAMPLER_WORD_ps_num = 18, + SQ_TEX_SAMPLER_WORD_vs_num = 18, + SQ_TEX_SAMPLER_WORD_gs_num = 18, + SQ_TEX_SAMPLER_WORD_all_num = 54, + SQ_TEX_SAMPLER_WORD_offset = 12, + SQ_TEX_SAMPLER_WORD_ps = 0, + SQ_TEX_SAMPLER_WORD_vs = SQ_TEX_SAMPLER_WORD_ps + SQ_TEX_SAMPLER_WORD_ps_num, + SQ_TEX_SAMPLER_WORD_gs = SQ_TEX_SAMPLER_WORD_vs + SQ_TEX_SAMPLER_WORD_vs_num, + SQ_LOOP_CONST = SQ_LOOP_CONST_0, /* 32 per PS, VS, GS */ + SQ_LOOP_CONST_ps_num = 32, + SQ_LOOP_CONST_vs_num = 32, + SQ_LOOP_CONST_gs_num = 32, + SQ_LOOP_CONST_all_num = 96, + SQ_LOOP_CONST_offset = 4, + SQ_LOOP_CONST_ps = 0, + SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num, + SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num, +} ; + + +#endif diff --git a/src/mesa/drivers/dri/r600/r600_reg_r7xx.h b/src/mesa/drivers/dri/r600/r600_reg_r7xx.h new file mode 100644 index 0000000000..e5c01c861a --- /dev/null +++ b/src/mesa/drivers/dri/r600/r600_reg_r7xx.h @@ -0,0 +1,149 @@ +/* + * RadeonHD R6xx, R7xx Register documentation + * + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2009 Matthias Hopf + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _R600_REG_R7xx_H_ +#define _R600_REG_R7xx_H_ + +/* + * Register update for R7xx chips + */ + +enum { + + R7XX_MC_VM_FB_LOCATION = 0x00002024, + +// GRBM_STATUS = 0x00008010, + R7XX_TA_BUSY_bit = 1 << 14, + + R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ = 0x00008d8c, + RING0_OFFSET_mask = 0xff << 0, + RING0_OFFSET_shift = 0, + ISOLATE_ES_ENABLE_bit = 1 << 12, + ISOLATE_GS_ENABLE_bit = 1 << 13, + VS_PC_LIMIT_ENABLE_bit = 1 << 14, + +// SQ_ALU_WORD0 = 0x00008dfc, +// SRC0_SEL_mask = 0x1ff << 0, +// SRC1_SEL_mask = 0x1ff << 13, + R7xx_SQ_ALU_SRC_1_DBL_L = 0xf4, + R7xx_SQ_ALU_SRC_1_DBL_M = 0xf5, + R7xx_SQ_ALU_SRC_0_5_DBL_L = 0xf6, + R7xx_SQ_ALU_SRC_0_5_DBL_M = 0xf7, +// INDEX_MODE_mask = 0x07 << 26, + R7xx_SQ_INDEX_GLOBAL = 0x05, + R7xx_SQ_INDEX_GLOBAL_AR_X = 0x06, + R6xx_SQ_ALU_WORD1_OP2 = 0x00008dfc, + R7xx_SQ_ALU_WORD1_OP2_V2 = 0x00008dfc, + R6xx_FOG_MERGE_bit = 1 << 5, + R6xx_OMOD_mask = 0x03 << 6, + R7xx_OMOD_mask = 0x03 << 5, + R6xx_OMOD_shift = 6, + R7xx_OMOD_shift = 5, + R6xx_SQ_ALU_WORD1_OP2__ALU_INST_mask = 0x3ff << 8, + R7xx_SQ_ALU_WORD1_OP2_V2__ALU_INST_mask = 0x7ff << 7, + R6xx_SQ_ALU_WORD1_OP2__ALU_INST_shift = 8, + R7xx_SQ_ALU_WORD1_OP2_V2__ALU_INST_shift = 7, + R7xx_SQ_OP2_INST_FREXP_64 = 0x07, + R7xx_SQ_OP2_INST_ADD_64 = 0x17, + R7xx_SQ_OP2_INST_MUL_64 = 0x1b, + R7xx_SQ_OP2_INST_FLT64_TO_FLT32 = 0x1c, + R7xx_SQ_OP2_INST_FLT32_TO_FLT64 = 0x1d, + R7xx_SQ_OP2_INST_LDEXP_64 = 0x7a, + R7xx_SQ_OP2_INST_FRACT_64 = 0x7b, + R7xx_SQ_OP2_INST_PRED_SETGT_64 = 0x7c, + R7xx_SQ_OP2_INST_PRED_SETE_64 = 0x7d, + R7xx_SQ_OP2_INST_PRED_SETGE_64 = 0x7e, +// SQ_ALU_WORD1_OP3 = 0x00008dfc, +// SRC2_SEL_mask = 0x1ff << 0, +// R7xx_SQ_ALU_SRC_1_DBL_L = 0xf4, +// R7xx_SQ_ALU_SRC_1_DBL_M = 0xf5, +// R7xx_SQ_ALU_SRC_0_5_DBL_L = 0xf6, +// R7xx_SQ_ALU_SRC_0_5_DBL_M = 0xf7, +// SQ_ALU_WORD1_OP3__ALU_INST_mask = 0x1f << 13, + R7xx_SQ_OP3_INST_MULADD_64 = 0x08, + R7xx_SQ_OP3_INST_MULADD_64_M2 = 0x09, + R7xx_SQ_OP3_INST_MULADD_64_M4 = 0x0a, + R7xx_SQ_OP3_INST_MULADD_64_D2 = 0x0b, +// SQ_CF_ALU_WORD1 = 0x00008dfc, + R6xx_USES_WATERFALL_bit = 1 << 25, + R7xx_SQ_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25, +// SQ_CF_ALLOC_EXPORT_WORD0 = 0x00008dfc, +// ARRAY_BASE_mask = 0x1fff << 0, +// TYPE_mask = 0x03 << 13, +// SQ_EXPORT_PARAM = 0x02, +// X_UNUSED_FOR_SX_EXPORTS = 0x03, +// ELEM_SIZE_mask = 0x03 << 30, +// SQ_CF_ALLOC_EXPORT_WORD1 = 0x00008dfc, +// SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0x7f << 23, + R7xx_SQ_CF_INST_MEM_EXPORT = 0x3a, +// SQ_CF_WORD1 = 0x00008dfc, +// SQ_CF_WORD1__COUNT_mask = 0x07 << 10, + R7xx_COUNT_3_bit = 1 << 19, +// SQ_CF_WORD1__CF_INST_mask = 0x7f << 23, + R7xx_SQ_CF_INST_END_PROGRAM = 0x19, + R7xx_SQ_CF_INST_WAIT_ACK = 0x1a, + R7xx_SQ_CF_INST_TEX_ACK = 0x1b, + R7xx_SQ_CF_INST_VTX_ACK = 0x1c, + R7xx_SQ_CF_INST_VTX_TC_ACK = 0x1d, +// SQ_VTX_WORD0 = 0x00008dfc, +// VTX_INST_mask = 0x1f << 0, + R7xx_SQ_VTX_INST_MEM = 0x02, +// SQ_VTX_WORD2 = 0x00008dfc, + R7xx_SQ_VTX_WORD2__ALT_CONST_bit = 1 << 20, + +// SQ_TEX_WORD0 = 0x00008dfc, +// TEX_INST_mask = 0x1f << 0, + R7xx_X_MEMORY_READ = 0x02, + R7xx_SQ_TEX_INST_KEEP_GRADIENTS = 0x0a, + R7xx_X_FETCH4_LOAD4_INSTRUCTION_FOR_DX10_1 = 0x0f, + R7xx_SQ_TEX_WORD0__ALT_CONST_bit = 1 << 24, + + R7xx_PA_SC_EDGERULE = 0x00028230, + R7xx_SPI_THREAD_GROUPING = 0x000286c8, + PS_GROUPING_mask = 0x1f << 0, + PS_GROUPING_shift = 0, + VS_GROUPING_mask = 0x1f << 8, + VS_GROUPING_shift = 8, + GS_GROUPING_mask = 0x1f << 16, + GS_GROUPING_shift = 16, + ES_GROUPING_mask = 0x1f << 24, + ES_GROUPING_shift = 24, + R7xx_CB_SHADER_CONTROL = 0x000287a0, + RT0_ENABLE_bit = 1 << 0, + RT1_ENABLE_bit = 1 << 1, + RT2_ENABLE_bit = 1 << 2, + RT3_ENABLE_bit = 1 << 3, + RT4_ENABLE_bit = 1 << 4, + RT5_ENABLE_bit = 1 << 5, + RT6_ENABLE_bit = 1 << 6, + RT7_ENABLE_bit = 1 << 7, +// DB_ALPHA_TO_MASK = 0x00028d44, + R7xx_OFFSET_ROUND_bit = 1 << 16, +// SQ_TEX_SAMPLER_MISC_0 = 0x0003d03c, + R7xx_TRUNCATE_COORD_bit = 1 << 9, + R7xx_DISABLE_CUBE_WRAP_bit = 1 << 10, + +} ; + +#endif /* _R600_REG_R7xx_H_ */ diff --git a/src/mesa/drivers/dri/r600/r600_swtcl.c b/src/mesa/drivers/dri/r600/r600_swtcl.c index fdb6f78754..4d134070d6 100644 --- a/src/mesa/drivers/dri/r600/r600_swtcl.c +++ b/src/mesa/drivers/dri/r600/r600_swtcl.c @@ -36,7 +36,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r600_swtcl.h" #include "r600_emit.h" -#include "r600_tex.h" #define EMIT_ATTR( ATTR, STYLE ) \ do { \ @@ -65,104 +64,12 @@ do { \ static void r600SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsWritten) { - r600ContextPtr rmesa = R600_CONTEXT( ctx ); - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *VB = &tnl->vb; - struct vertex_attribute *attrs = rmesa->swtcl.vert_attrs; - int vte = 0; - int i, j, reg_count; - uint32_t *vir0 = &rmesa->hw.vir[0].cmd[1]; - uint32_t *vir1 = &rmesa->hw.vir[1].cmd[1]; - - for (i = 0; i < R600_VIR_CMDSIZE-1; ++i) - vir0[i] = vir1[i] = 0; - - for (i = 0, j = 0; i < rmesa->radeon.swtcl.vertex_attr_count; ++i) { - int tmp, data_format; - switch (attrs[i].format) { - case EMIT_1F: - data_format = R600_DATA_TYPE_FLOAT_1; - break; - case EMIT_2F: - data_format = R600_DATA_TYPE_FLOAT_2; - break; - case EMIT_3F: - data_format = R600_DATA_TYPE_FLOAT_3; - break; - case EMIT_4F: - data_format = R600_DATA_TYPE_FLOAT_4; - break; - case EMIT_4UB_4F_RGBA: - case EMIT_4UB_4F_ABGR: - data_format = R600_DATA_TYPE_BYTE | R600_NORMALIZE; - break; - default: - fprintf(stderr, "%s: Invalid data format type", __FUNCTION__); - _mesa_exit(-1); - break; - } - - tmp = data_format | (attrs[i].dst_loc << R600_DST_VEC_LOC_SHIFT); - if (i % 2 == 0) { - vir0[j] = tmp << R600_DATA_TYPE_0_SHIFT; - vir1[j] = attrs[i].swizzle | (attrs[i].write_mask << R600_WRITE_ENA_SHIFT); - } else { - vir0[j] |= tmp << R600_DATA_TYPE_1_SHIFT; - vir1[j] |= (attrs[i].swizzle | (attrs[i].write_mask << R600_WRITE_ENA_SHIFT)) << R600_SWIZZLE1_SHIFT; - ++j; - } - } - - reg_count = (rmesa->radeon.swtcl.vertex_attr_count + 1) >> 1; - if (rmesa->radeon.swtcl.vertex_attr_count % 2 != 0) { - vir0[reg_count-1] |= R600_LAST_VEC << R600_DATA_TYPE_0_SHIFT; - } else { - vir0[reg_count-1] |= R600_LAST_VEC << R600_DATA_TYPE_1_SHIFT; - } - - R600_STATECHANGE(rmesa, vir[0]); - R600_STATECHANGE(rmesa, vir[1]); - R600_STATECHANGE(rmesa, vof); - R600_STATECHANGE(rmesa, vte); - R600_STATECHANGE(rmesa, vic); - - if (rmesa->radeon.radeonScreen->kernel_mm) { - rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF; - rmesa->hw.vir[1].cmd[0] &= 0xC000FFFF; - rmesa->hw.vir[0].cmd[0] |= (reg_count & 0x3FFF) << 16; - rmesa->hw.vir[1].cmd[0] |= (reg_count & 0x3FFF) << 16; - } else { - ((drm_r300_cmd_header_t *) rmesa->hw.vir[0].cmd)->packet0.count = reg_count; - ((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = reg_count; - } - - rmesa->hw.vic.cmd[R600_VIC_CNTL_0] = r600VAPInputCntl0(ctx, InputsRead); - rmesa->hw.vic.cmd[R600_VIC_CNTL_1] = r600VAPInputCntl1(ctx, InputsRead); - rmesa->hw.vof.cmd[R600_VOF_CNTL_0] = r600VAPOutputCntl0(ctx, OutputsWritten); - rmesa->hw.vof.cmd[R600_VOF_CNTL_1] = r600VAPOutputCntl1(ctx, OutputsWritten); - - vte = rmesa->hw.vte.cmd[1]; - vte &= ~(R600_VTX_XY_FMT | R600_VTX_Z_FMT | R600_VTX_W0_FMT); - /* Important: - */ - if ( VB->NdcPtr != NULL ) { - VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr; - vte |= R600_VTX_XY_FMT | R600_VTX_Z_FMT; - } - else { - VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr; - vte |= R600_VTX_W0_FMT; - } - - assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL ); - - rmesa->hw.vte.cmd[1] = vte; - rmesa->hw.vte.cmd[2] = rmesa->radeon.swtcl.vertex_size; } static void r600SetVertexFormat( GLcontext *ctx ) { +#if 0 /* to be enabled */ r600ContextPtr rmesa = R600_CONTEXT( ctx ); TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *VB = &tnl->vb; @@ -318,6 +225,7 @@ static void r600SetVertexFormat( GLcontext *ctx ) rmesa->radeon.swtcl.vertex_size /= 4; RENDERINPUTS_COPY(rmesa->state.render_inputs_bitset, tnl->render_inputs_bitset); +#endif /* to be enabled */ } @@ -584,6 +492,7 @@ static void r600ChooseRenderState( GLcontext *ctx ) static void r600RenderStart(GLcontext *ctx) { +#if 0 /* to be enabled */ r600ContextPtr rmesa = R600_CONTEXT( ctx ); r600ChooseRenderState(ctx); @@ -600,6 +509,7 @@ static void r600RenderStart(GLcontext *ctx) if (rmesa->radeon.dma.flush != NULL) { rmesa->radeon.dma.flush(ctx); } +#endif /* to be enabled */ } static void r600RenderFinish(GLcontext *ctx) @@ -608,12 +518,14 @@ static void r600RenderFinish(GLcontext *ctx) static void r600RasterPrimitive( GLcontext *ctx, GLuint hwprim ) { +#if 0 /* to be enabled */ r600ContextPtr rmesa = R600_CONTEXT(ctx); if (rmesa->radeon.swtcl.hw_primitive != hwprim) { R600_NEWPRIM( rmesa ); rmesa->radeon.swtcl.hw_primitive = hwprim; } +#endif /* to be enabled */ } static void r600RenderPrimitive(GLcontext *ctx, GLenum prim) @@ -673,6 +585,7 @@ void r600DestroySwtcl(GLcontext *ctx) static void r600EmitVertexAOS(r600ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset) { +#if 0 /* to be enabled */ BATCH_LOCALS(&rmesa->radeon); if (RADEON_DEBUG & DEBUG_VERTS) @@ -685,10 +598,12 @@ static void r600EmitVertexAOS(r600ContextPtr rmesa, GLuint vertex_size, struct r OUT_BATCH(vertex_size | (vertex_size << 8)); OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0); END_BATCH(); +#endif /* to be enabled */ } static void r600EmitVbufPrim(r600ContextPtr rmesa, GLuint primitive, GLuint vertex_nr) { +#if 0 /* to be enabled */ BATCH_LOCALS(&rmesa->radeon); int type, num_verts; @@ -699,10 +614,12 @@ static void r600EmitVbufPrim(r600ContextPtr rmesa, GLuint primitive, GLuint vert OUT_BATCH_PACKET3(R600_PACKET3_3D_DRAW_VBUF_2, 0); OUT_BATCH(R600_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type); END_BATCH(); +#endif /* to be enabled */ } void r600_swtcl_flush(GLcontext *ctx, uint32_t current_offset) { +#if 0 /* to be enabled */ r600ContextPtr rmesa = R600_CONTEXT(ctx); rcommonEnsureCmdBufSpace(&rmesa->radeon, @@ -719,4 +636,5 @@ void r600_swtcl_flush(GLcontext *ctx, uint32_t current_offset) rmesa->radeon.swtcl.numverts); r600EmitCacheFlush(rmesa); COMMIT_BATCH(); +#endif /* to be enabled */ } diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c new file mode 100644 index 0000000000..5ceb3fdd9b --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -0,0 +1,4068 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + */ + +#include +#include +#include +#include +#include + +#include "main/mtypes.h" +#include "main/imports.h" + +#include "r600_context.h" +#include "r700_chip.h" +#include "r700_debug.h" + +#include "r700_assembler.h" + +BITS addrmode_PVSDST(PVSDST * pPVSDST) +{ + return pPVSDST->addrmode0 | ((BITS)pPVSDST->addrmode1 << 1); +} + +void setaddrmode_PVSDST(PVSDST * pPVSDST, BITS addrmode) +{ + pPVSDST->addrmode0 = addrmode & 1; + pPVSDST->addrmode1 = (addrmode >> 1) & 1; +} + +void nomask_PVSDST(PVSDST * pPVSDST) +{ + pPVSDST->writex = pPVSDST->writey = pPVSDST->writez = pPVSDST->writew = 1; +} + +BITS addrmode_PVSSRC(PVSSRC* pPVSSRC) +{ + return pPVSSRC->addrmode0 | ((BITS)pPVSSRC->addrmode1 << 1); +} + +void setaddrmode_PVSSRC(PVSSRC* pPVSSRC, BITS addrmode) +{ + pPVSSRC->addrmode0 = addrmode & 1; + pPVSSRC->addrmode1 = (addrmode >> 1) & 1; +} + + +void setswizzle_PVSSRC(PVSSRC* pPVSSRC, BITS swz) +{ + pPVSSRC->swizzlex = + pPVSSRC->swizzley = + pPVSSRC->swizzlez = + pPVSSRC->swizzlew = swz; +} + +void noswizzle_PVSSRC(PVSSRC* pPVSSRC) +{ + pPVSSRC->swizzlex = SQ_SEL_X; + pPVSSRC->swizzley = SQ_SEL_Y; + pPVSSRC->swizzlez = SQ_SEL_Z; + pPVSSRC->swizzlew = SQ_SEL_W; +} + +void +swizzleagain_PVSSRC(PVSSRC * pPVSSRC, BITS x, BITS y, BITS z, BITS w) +{ + switch (x) + { + case SQ_SEL_X: x = pPVSSRC->swizzlex; + break; + case SQ_SEL_Y: x = pPVSSRC->swizzley; + break; + case SQ_SEL_Z: x = pPVSSRC->swizzlez; + break; + case SQ_SEL_W: x = pPVSSRC->swizzlew; + break; + default:; + } + + switch (y) + { + case SQ_SEL_X: y = pPVSSRC->swizzlex; + break; + case SQ_SEL_Y: y = pPVSSRC->swizzley; + break; + case SQ_SEL_Z: y = pPVSSRC->swizzlez; + break; + case SQ_SEL_W: y = pPVSSRC->swizzlew; + break; + default:; + } + + switch (z) + { + case SQ_SEL_X: z = pPVSSRC->swizzlex; + break; + case SQ_SEL_Y: z = pPVSSRC->swizzley; + break; + case SQ_SEL_Z: z = pPVSSRC->swizzlez; + break; + case SQ_SEL_W: z = pPVSSRC->swizzlew; + break; + default:; + } + + switch (w) + { + case SQ_SEL_X: w = pPVSSRC->swizzlex; + break; + case SQ_SEL_Y: w = pPVSSRC->swizzley; + break; + case SQ_SEL_Z: w = pPVSSRC->swizzlez; + break; + case SQ_SEL_W: w = pPVSSRC->swizzlew; + break; + default:; + } + + pPVSSRC->swizzlex = x; + pPVSSRC->swizzley = y; + pPVSSRC->swizzlez = z; + pPVSSRC->swizzlew = w; +} + +void neg_PVSSRC(PVSSRC* pPVSSRC) +{ + pPVSSRC->negx = 1; + pPVSSRC->negy = 1; + pPVSSRC->negz = 1; + pPVSSRC->negw = 1; +} + +void noneg_PVSSRC(PVSSRC* pPVSSRC) +{ + pPVSSRC->negx = 0; + pPVSSRC->negy = 0; + pPVSSRC->negz = 0; + pPVSSRC->negw = 0; +} + +// negate argument (for SUB instead of ADD and alike) +void flipneg_PVSSRC(PVSSRC* pPVSSRC) +{ + pPVSSRC->negx = !pPVSSRC->negx; + pPVSSRC->negy = !pPVSSRC->negy; + pPVSSRC->negz = !pPVSSRC->negz; + pPVSSRC->negw = !pPVSSRC->negw; +} + +void zerocomp_PVSSRC(PVSSRC* pPVSSRC, int c) +{ + switch (c) + { + case 0: pPVSSRC->swizzlex = SQ_SEL_0; pPVSSRC->negx = 0; break; + case 1: pPVSSRC->swizzley = SQ_SEL_0; pPVSSRC->negy = 0; break; + case 2: pPVSSRC->swizzlez = SQ_SEL_0; pPVSSRC->negz = 0; break; + case 3: pPVSSRC->swizzlew = SQ_SEL_0; pPVSSRC->negw = 0; break; + default:; + } +} + +void onecomp_PVSSRC(PVSSRC* pPVSSRC, int c) +{ + switch (c) + { + case 0: pPVSSRC->swizzlex = SQ_SEL_1; pPVSSRC->negx = 0; break; + case 1: pPVSSRC->swizzley = SQ_SEL_1; pPVSSRC->negy = 0; break; + case 2: pPVSSRC->swizzlez = SQ_SEL_1; pPVSSRC->negz = 0; break; + case 3: pPVSSRC->swizzlew = SQ_SEL_1; pPVSSRC->negw = 0; break; + default:; + } +} + +BITS is_misc_component_exported(VAP_OUT_VTX_FMT_0* pOutVTXFmt0) +{ + return (pOutVTXFmt0->point_size | + pOutVTXFmt0->edge_flag | + pOutVTXFmt0->rta_index | + pOutVTXFmt0->kill_flag | + pOutVTXFmt0->viewport_index); +} + +BITS is_depth_component_exported(OUT_FRAGMENT_FMT_0* pFPOutFmt) +{ + return (pFPOutFmt->depth | + pFPOutFmt->stencil_ref | + pFPOutFmt->mask | + pFPOutFmt->coverage_to_mask); +} + +GLboolean is_reduction_opcode(PVSDWORD* dest) +{ + if (dest->dst.op3 == 0) + { + if ( (dest->dst.opcode == SQ_OP2_INST_DOT4 || dest->dst.opcode == SQ_OP2_INST_DOT4_IEEE) ) + { + return GL_TRUE; + } + } + return GL_FALSE; +} + +GLuint GetSurfaceFormat(GLenum eType, GLuint nChannels, GLuint * pClient_size) +{ + GLuint format = FMT_INVALID; + GLuint uiElemSize = 0; + + switch (eType) + { + case GL_BYTE: + case GL_UNSIGNED_BYTE: + uiElemSize = 1; + switch(nChannels) + { + case 1: + format = FMT_8; break; + case 2: + format = FMT_8_8; break; + case 3: + format = FMT_8_8_8; break; + case 4: + format = FMT_8_8_8_8; break; + default: + break; + } + break; + + case GL_UNSIGNED_SHORT: + case GL_SHORT: + uiElemSize = 2; + switch(nChannels) + { + case 1: + format = FMT_16; break; + case 2: + format = FMT_16_16; break; + case 3: + format = FMT_16_16_16; break; + case 4: + format = FMT_16_16_16_16; break; + default: + break; + } + break; + + case GL_UNSIGNED_INT: + case GL_INT: + uiElemSize = 4; + switch(nChannels) + { + case 1: + format = FMT_32; break; + case 2: + format = FMT_32_32; break; + case 3: + format = FMT_32_32_32; break; + case 4: + format = FMT_32_32_32_32; break; + default: + break; + } + break; + + case GL_FLOAT: + uiElemSize = 4; + switch(nChannels) + { + case 1: + format = FMT_32_FLOAT; break; + case 2: + format = FMT_32_32_FLOAT; break; + case 3: + format = FMT_32_32_32_FLOAT; break; + case 4: + format = FMT_32_32_32_32_FLOAT; break; + default: + break; + } + break; + case GL_DOUBLE: + uiElemSize = 8; + switch(nChannels) + { + case 1: + format = FMT_32_FLOAT; break; + case 2: + format = FMT_32_32_FLOAT; break; + case 3: + format = FMT_32_32_32_FLOAT; break; + case 4: + format = FMT_32_32_32_32_FLOAT; break; + default: + break; + } + break; + default: + ; + //GL_ASSERT_NO_CASE(); + } + + if(NULL != pClient_size) + { + *pClient_size = uiElemSize * nChannels; + } + + return(format); +} + +unsigned int r700GetNumOperands(r700_AssemblerBase* pAsm) +{ + if(pAsm->D.dst.op3) + { + return 3; + } + + switch (pAsm->D.dst.opcode) + { + case SQ_OP2_INST_ADD: + case SQ_OP2_INST_MUL: + case SQ_OP2_INST_MAX: + case SQ_OP2_INST_MIN: + //case SQ_OP2_INST_MAX_DX10: + //case SQ_OP2_INST_MIN_DX10: + case SQ_OP2_INST_SETGT: + case SQ_OP2_INST_SETGE: + case SQ_OP2_INST_PRED_SETE: + case SQ_OP2_INST_PRED_SETGT: + case SQ_OP2_INST_PRED_SETGE: + case SQ_OP2_INST_PRED_SETNE: + case SQ_OP2_INST_DOT4: + case SQ_OP2_INST_DOT4_IEEE: + return 2; + + case SQ_OP2_INST_MOV: + case SQ_OP2_INST_FRACT: + case SQ_OP2_INST_FLOOR: + case SQ_OP2_INST_KILLGT: + case SQ_OP2_INST_EXP_IEEE: + case SQ_OP2_INST_LOG_CLAMPED: + case SQ_OP2_INST_LOG_IEEE: + case SQ_OP2_INST_RECIP_IEEE: + case SQ_OP2_INST_RECIPSQRT_IEEE: + case SQ_OP2_INST_FLT_TO_INT: + case SQ_OP2_INST_SIN: + case SQ_OP2_INST_COS: + return 1; + + default: r700_error(TODO_ASM_NEEDIMPINST, + "Need instruction operand number. \n");; + }; + + return 3; +} + +int Init_r700_AssemblerBase(SHADER_PIPE_TYPE spt, r700_AssemblerBase* pAsm, R700_Shader* pShader) +{ + GLuint i; + + Init_R700_Shader(pShader); + pAsm->pR700Shader = pShader; + pAsm->currentShaderType = spt; + + pAsm->cf_last_export_ptr = NULL; + + pAsm->cf_current_export_clause_ptr = NULL; + pAsm->cf_current_alu_clause_ptr = NULL; + pAsm->cf_current_tex_clause_ptr = NULL; + pAsm->cf_current_vtx_clause_ptr = NULL; + pAsm->cf_current_cf_clause_ptr = NULL; + + // No clause has been created yet + pAsm->cf_current_clause_type = CF_EMPTY_CLAUSE; + + pAsm->number_of_colorandz_exports = 0; + pAsm->number_of_exports = 0; + pAsm->number_of_export_opcodes = 0; + + + pAsm->D.bits = 0; + pAsm->S[0].bits = 0; + pAsm->S[1].bits = 0; + pAsm->S[2].bits = 0; + + pAsm->uLastPosUpdate = 0; + + *(BITS *) &pAsm->fp_stOutFmt0 = 0; + + pAsm->uIIns = 0; + pAsm->uOIns = 0; + pAsm->number_used_registers = 0; + pAsm->uUsedConsts = 256; + + + // Fragment programs + pAsm->uBoolConsts = 0; + pAsm->uIntConsts = 0; + pAsm->uInsts = 0; + pAsm->uConsts = 0; + + pAsm->FCSP = 0; + pAsm->fc_stack[0].type = FC_NONE; + + pAsm->branch_depth = 0; + pAsm->max_branch_depth = 0; + + pAsm->aArgSubst[0] = + pAsm->aArgSubst[1] = + pAsm->aArgSubst[2] = + pAsm->aArgSubst[3] = (-1); + + pAsm->uOutputs = 0; + + for (i=0; icolor_export_register_number[i] = (-1); + } + + + pAsm->depth_export_register_number = (-1); + pAsm->stencil_export_register_number = (-1); + pAsm->coverage_to_mask_export_register_number = (-1); + pAsm->mask_export_register_number = (-1); + + pAsm->starting_export_register_number = 0; + pAsm->starting_vfetch_register_number = 0; + pAsm->starting_temp_register_number = 0; + pAsm->uFirstHelpReg = 0; + + + pAsm->input_position_is_used = GL_FALSE; + pAsm->input_normal_is_used = GL_FALSE; + + + for (i=0; iinput_color_is_used[ i ] = GL_FALSE; + } + + for (i=0; iinput_texture_unit_is_used[ i ] = GL_FALSE; + } + + for (i=0; ivfetch_instruction_ptr_array[ i ] = NULL; + } + + pAsm->number_of_inputs = 0; + + return 0; +} + +GLboolean IsTex(gl_inst_opcode Opcode) +{ + if( (OPCODE_TEX==Opcode) || (OPCODE_TXP==Opcode) || (OPCODE_TXB==Opcode) ) + { + return GL_TRUE; + } + return GL_FALSE; +} + +GLboolean IsAlu(gl_inst_opcode Opcode) +{ + //TODO : more for fc and ex for higher spec. + if( IsTex(Opcode) ) + { + return GL_FALSE; + } + return GL_TRUE; +} + +int check_current_clause(r700_AssemblerBase* pAsm, + CF_CLAUSE_TYPE new_clause_type) +{ + if (pAsm->cf_current_clause_type != new_clause_type) + { //Close last open clause + switch (pAsm->cf_current_clause_type) + { + case CF_ALU_CLAUSE: + if ( pAsm->cf_current_alu_clause_ptr != NULL) + { + pAsm->cf_current_alu_clause_ptr = NULL; + } + break; + case CF_VTX_CLAUSE: + if ( pAsm->cf_current_vtx_clause_ptr != NULL) + { + pAsm->cf_current_vtx_clause_ptr = NULL; + } + break; + case CF_TEX_CLAUSE: + if ( pAsm->cf_current_tex_clause_ptr != NULL) + { + pAsm->cf_current_tex_clause_ptr = NULL; + } + break; + case CF_EXPORT_CLAUSE: + if ( pAsm->cf_current_export_clause_ptr != NULL) + { + pAsm->cf_current_export_clause_ptr = NULL; + } + break; + case CF_OTHER_CLAUSE: + if ( pAsm->cf_current_cf_clause_ptr != NULL) + { + pAsm->cf_current_cf_clause_ptr = NULL; + } + break; + case CF_EMPTY_CLAUSE: + break; + default: + r700_error(ERROR_ASM_VTX_CLAUSE, + "Unknown CF_CLAUSE_TYPE (%d) in check_current_clause. \n", (int) new_clause_type); + return GL_FALSE; + } + + pAsm->cf_current_clause_type = CF_EMPTY_CLAUSE; + + // Create new clause + switch (new_clause_type) + { + case CF_ALU_CLAUSE: + pAsm->cf_current_clause_type = CF_ALU_CLAUSE; + break; + case CF_VTX_CLAUSE: + pAsm->cf_current_clause_type = CF_VTX_CLAUSE; + break; + case CF_TEX_CLAUSE: + pAsm->cf_current_clause_type = CF_TEX_CLAUSE; + break; + case CF_EXPORT_CLAUSE: + { + R700ControlFlowSXClause* pR700ControlFlowSXClause + = (R700ControlFlowSXClause*) CALLOC_STRUCT(R700ControlFlowSXClause); + + // Add new export instruction to control flow program + if (pR700ControlFlowSXClause != 0) + { + pAsm->cf_current_export_clause_ptr = pR700ControlFlowSXClause; + Init_R700ControlFlowSXClause(pR700ControlFlowSXClause); + AddCFInstruction( pAsm->pR700Shader, + (R700ControlFlowInstruction *)pR700ControlFlowSXClause ); + } + else + { + r700_error(ERROR_ASM_ALLOCEXPORTCF, + "Error allocating new EXPORT CF instruction in check_current_clause. \n"); + return GL_FALSE; + } + pAsm->cf_current_clause_type = CF_EXPORT_CLAUSE; + } + break; + case CF_EMPTY_CLAUSE: + break; + case CF_OTHER_CLAUSE: + pAsm->cf_current_clause_type = CF_OTHER_CLAUSE; + break; + default: + r700_error(ERROR_ASM_UNKOWNCLAUSE, + "Unknown CF_CLAUSE_TYPE (%d) in check_current_clause. \n", (int) new_clause_type); + return GL_FALSE; + } + } + + return GL_TRUE; +} + +GLboolean add_vfetch_instruction(r700_AssemblerBase* pAsm, + R700VertexInstruction* vertex_instruction_ptr) +{ + if( GL_FALSE == check_current_clause(pAsm, CF_VTX_CLAUSE) ) + { + return GL_FALSE; + } + + if( pAsm->cf_current_vtx_clause_ptr == NULL || + ( (pAsm->cf_current_vtx_clause_ptr != NULL) && + (pAsm->cf_current_vtx_clause_ptr->m_Word1.f.count >= GetCFMaxInstructions(pAsm->cf_current_vtx_clause_ptr->m_ShaderInstType)-1) + ) ) + { + // Create new Vfetch control flow instruction for this new clause + pAsm->cf_current_vtx_clause_ptr = (R700ControlFlowGenericClause*) CALLOC_STRUCT(R700ControlFlowGenericClause); + + if (pAsm->cf_current_vtx_clause_ptr != NULL) + { + Init_R700ControlFlowGenericClause(pAsm->cf_current_vtx_clause_ptr); + AddCFInstruction( pAsm->pR700Shader, + (R700ControlFlowInstruction *)pAsm->cf_current_vtx_clause_ptr ); + } + else + { + r700_error(ERROR_ASM_ALLOCVTXCF, "Could not allocate a new VFetch CF instruction."); + return GL_FALSE; + } + + pAsm->cf_current_vtx_clause_ptr->m_Word1.f.pop_count = 0x0; + pAsm->cf_current_vtx_clause_ptr->m_Word1.f.cf_const = 0x0; + pAsm->cf_current_vtx_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE; + pAsm->cf_current_vtx_clause_ptr->m_Word1.f.count = 0x0; + pAsm->cf_current_vtx_clause_ptr->m_Word1.f.end_of_program = 0x0; + pAsm->cf_current_vtx_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0; + pAsm->cf_current_vtx_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_VTX; + pAsm->cf_current_vtx_clause_ptr->m_Word1.f.whole_quad_mode = 0x0; + pAsm->cf_current_vtx_clause_ptr->m_Word1.f.barrier = 0x1; + + LinkVertexInstruction(pAsm->cf_current_vtx_clause_ptr, vertex_instruction_ptr ); + } + else + { + pAsm->cf_current_vtx_clause_ptr->m_Word1.f.count++; + } + + AddVTXInstruction(pAsm->pR700Shader, vertex_instruction_ptr); + + return GL_TRUE; +} + +GLboolean add_tex_instruction(r700_AssemblerBase* pAsm, + R700TextureInstruction* tex_instruction_ptr) +{ + if ( GL_FALSE == check_current_clause(pAsm, CF_TEX_CLAUSE) ) + { + return GL_FALSE; + } + + if ( pAsm->cf_current_tex_clause_ptr == NULL || + ( (pAsm->cf_current_tex_clause_ptr != NULL) && + (pAsm->cf_current_tex_clause_ptr->m_Word1.f.count >= GetCFMaxInstructions(pAsm->cf_current_tex_clause_ptr->m_ShaderInstType)-1) + ) ) + { + // new tex cf instruction for this new clause + pAsm->cf_current_tex_clause_ptr = (R700ControlFlowGenericClause*) CALLOC_STRUCT(R700ControlFlowGenericClause); + + if (pAsm->cf_current_tex_clause_ptr != NULL) + { + Init_R700ControlFlowGenericClause(pAsm->cf_current_tex_clause_ptr); + AddCFInstruction( pAsm->pR700Shader, + (R700ControlFlowInstruction *)pAsm->cf_current_tex_clause_ptr ); + } + else + { + r700_error(ERROR_ASM_ALLOCTEXCF, "Could not allocate a new TEX CF instruction."); + return GL_FALSE; + } + + pAsm->cf_current_tex_clause_ptr->m_Word1.f.pop_count = 0x0; + pAsm->cf_current_tex_clause_ptr->m_Word1.f.cf_const = 0x0; + pAsm->cf_current_tex_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE; + + pAsm->cf_current_tex_clause_ptr->m_Word1.f.end_of_program = 0x0; + pAsm->cf_current_tex_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0; + pAsm->cf_current_tex_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_TEX; + pAsm->cf_current_tex_clause_ptr->m_Word1.f.whole_quad_mode = 0x0; + pAsm->cf_current_tex_clause_ptr->m_Word1.f.barrier = 0x0; //0x1; + } + else + { + pAsm->cf_current_tex_clause_ptr->m_Word1.f.count++; + } + + // If this clause constains any TEX instruction that is dependent on a previous instruction, + // set the barrier bit + if( pAsm->pInstDeps[pAsm->uiCurInst].nDstDep > (-1) ) + { + pAsm->cf_current_tex_clause_ptr->m_Word1.f.barrier = 0x1; + } + + if(NULL == pAsm->cf_current_tex_clause_ptr->m_pLinkedTEXInstruction) + { + pAsm->cf_current_tex_clause_ptr->m_pLinkedTEXInstruction = tex_instruction_ptr; + tex_instruction_ptr->m_pLinkedGenericClause = pAsm->cf_current_tex_clause_ptr; + } + + AddTEXInstruction(pAsm->pR700Shader, tex_instruction_ptr); + + return GL_TRUE; +} + +GLboolean assemble_vfetch_instruction(r700_AssemblerBase* pAsm, + GLuint gl_client_id, + GLuint destination_register, + GLuint number_of_elements, + GLenum dataElementType, + VTX_FETCH_METHOD* pFetchMethod) +{ + GLuint client_size_inbyte; + GLuint data_format; + GLuint mega_fetch_count; + GLuint is_mega_fetch_flag; + + R700VertexGenericFetch* vfetch_instruction_ptr; + R700VertexGenericFetch* assembled_vfetch_instruction_ptr = pAsm->vfetch_instruction_ptr_array[ gl_client_id ]; + + if (assembled_vfetch_instruction_ptr == NULL) + { + vfetch_instruction_ptr = (R700VertexGenericFetch*) CALLOC_STRUCT(R700VertexGenericFetch); + if (vfetch_instruction_ptr == NULL) + { + return GL_FALSE; + } + Init_R700VertexGenericFetch(vfetch_instruction_ptr); + } + else + { + vfetch_instruction_ptr = assembled_vfetch_instruction_ptr; + } + + data_format = GetSurfaceFormat(dataElementType, number_of_elements, &client_size_inbyte); + + if(GL_TRUE == pFetchMethod->bEnableMini) //More conditions here + { + //TODO : mini fetch + } + else + { + mega_fetch_count = MEGA_FETCH_BYTES - 1; + is_mega_fetch_flag = 0x1; + pFetchMethod->mega_fetch_remainder = MEGA_FETCH_BYTES - client_size_inbyte; + } + + vfetch_instruction_ptr->m_Word0.f.vtx_inst = SQ_VTX_INST_FETCH; + vfetch_instruction_ptr->m_Word0.f.fetch_type = SQ_VTX_FETCH_VERTEX_DATA; + vfetch_instruction_ptr->m_Word0.f.fetch_whole_quad = 0x0; + + vfetch_instruction_ptr->m_Word0.f.buffer_id = gl_client_id; + vfetch_instruction_ptr->m_Word0.f.src_gpr = 0x0; + vfetch_instruction_ptr->m_Word0.f.src_rel = SQ_ABSOLUTE; + vfetch_instruction_ptr->m_Word0.f.src_sel_x = SQ_SEL_X; + vfetch_instruction_ptr->m_Word0.f.mega_fetch_count = mega_fetch_count; + + vfetch_instruction_ptr->m_Word1.f.dst_sel_x = (number_of_elements < 1) ? SQ_SEL_0 : SQ_SEL_X; + vfetch_instruction_ptr->m_Word1.f.dst_sel_y = (number_of_elements < 2) ? SQ_SEL_0 : SQ_SEL_Y; + vfetch_instruction_ptr->m_Word1.f.dst_sel_z = (number_of_elements < 3) ? SQ_SEL_0 : SQ_SEL_Z; + vfetch_instruction_ptr->m_Word1.f.dst_sel_w = (number_of_elements < 4) ? SQ_SEL_1 : SQ_SEL_W; + + vfetch_instruction_ptr->m_Word1.f.use_const_fields = 1; + + // Destination register + vfetch_instruction_ptr->m_Word1_GPR.f.dst_gpr = destination_register; + vfetch_instruction_ptr->m_Word1_GPR.f.dst_rel = SQ_ABSOLUTE; + + vfetch_instruction_ptr->m_Word2.f.offset = 0; + vfetch_instruction_ptr->m_Word2.f.const_buf_no_stride = 0x0; + + vfetch_instruction_ptr->m_Word2.f.mega_fetch = is_mega_fetch_flag; + + if (assembled_vfetch_instruction_ptr == NULL) + { + if ( GL_FALSE == add_vfetch_instruction(pAsm, (R700VertexInstruction *)vfetch_instruction_ptr) ) + { + return GL_FALSE; + } + + if (pAsm->vfetch_instruction_ptr_array[ gl_client_id ] != NULL) + { + return GL_FALSE; + } + else + { + pAsm->vfetch_instruction_ptr_array[ gl_client_id ] = vfetch_instruction_ptr; + } + } + + return GL_TRUE; +} + +GLuint gethelpr(r700_AssemblerBase* pAsm) +{ + GLuint r = pAsm->uHelpReg; + pAsm->uHelpReg++; + if (pAsm->uHelpReg > pAsm->number_used_registers) + { + pAsm->number_used_registers = pAsm->uHelpReg; + } + return r; +} +void resethelpr(r700_AssemblerBase* pAsm) +{ + pAsm->uHelpReg = pAsm->uFirstHelpReg; +} + +void checkop_init(r700_AssemblerBase* pAsm) +{ + resethelpr(pAsm); + pAsm->aArgSubst[0] = + pAsm->aArgSubst[1] = + pAsm->aArgSubst[2] = + pAsm->aArgSubst[3] = -1; +} + +GLboolean mov_temp(r700_AssemblerBase* pAsm, int src) +{ + GLuint tmp = gethelpr(pAsm); + + //mov src to temp helper gpr. + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + + nomask_PVSDST(&(pAsm->D.dst)); + + if( GL_FALSE == assemble_src(pAsm, src, 0) ) + { + return GL_FALSE; + } + + noswizzle_PVSSRC(&(pAsm->S[0].src)); + noneg_PVSSRC(&(pAsm->S[0].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + pAsm->aArgSubst[1 + src] = tmp; + + return GL_TRUE; +} + +GLboolean checkop1(r700_AssemblerBase* pAsm) +{ + checkop_init(pAsm); + return GL_TRUE; +} + +GLboolean checkop2(r700_AssemblerBase* pAsm) +{ + GLboolean bSrcConst[2]; + struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); + + checkop_init(pAsm); + + if( (pILInst->SrcReg[0].File == PROGRAM_CONSTANT) || + (pILInst->SrcReg[0].File == PROGRAM_LOCAL_PARAM) || + (pILInst->SrcReg[0].File == PROGRAM_ENV_PARAM) || + (pILInst->SrcReg[0].File == PROGRAM_STATE_VAR) ) + { + bSrcConst[0] = GL_TRUE; + } + else + { + bSrcConst[0] = GL_FALSE; + } + if( (pILInst->SrcReg[1].File == PROGRAM_CONSTANT) || + (pILInst->SrcReg[1].File == PROGRAM_LOCAL_PARAM) || + (pILInst->SrcReg[1].File == PROGRAM_ENV_PARAM) || + (pILInst->SrcReg[1].File == PROGRAM_STATE_VAR) ) + { + bSrcConst[1] = GL_TRUE; + } + else + { + bSrcConst[1] = GL_FALSE; + } + + if( (bSrcConst[0] == GL_TRUE) && (bSrcConst[1] == GL_TRUE) ) + { + if(pILInst->SrcReg[0].Index != pILInst->SrcReg[1].Index) + { + if( GL_FALSE == mov_temp(pAsm, 1) ) + { + return GL_FALSE; + } + } + } + + return GL_TRUE; +} + +GLboolean checkop3(r700_AssemblerBase* pAsm) +{ + GLboolean bSrcConst[3]; + struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); + + checkop_init(pAsm); + + if( (pILInst->SrcReg[0].File == PROGRAM_CONSTANT) || + (pILInst->SrcReg[0].File == PROGRAM_LOCAL_PARAM) || + (pILInst->SrcReg[0].File == PROGRAM_ENV_PARAM) || + (pILInst->SrcReg[0].File == PROGRAM_STATE_VAR) ) + { + bSrcConst[0] = GL_TRUE; + } + else + { + bSrcConst[0] = GL_FALSE; + } + if( (pILInst->SrcReg[1].File == PROGRAM_CONSTANT) || + (pILInst->SrcReg[1].File == PROGRAM_LOCAL_PARAM) || + (pILInst->SrcReg[1].File == PROGRAM_ENV_PARAM) || + (pILInst->SrcReg[1].File == PROGRAM_STATE_VAR) ) + { + bSrcConst[1] = GL_TRUE; + } + else + { + bSrcConst[1] = GL_FALSE; + } + if( (pILInst->SrcReg[2].File == PROGRAM_CONSTANT) || + (pILInst->SrcReg[2].File == PROGRAM_LOCAL_PARAM) || + (pILInst->SrcReg[2].File == PROGRAM_ENV_PARAM) || + (pILInst->SrcReg[2].File == PROGRAM_STATE_VAR) ) + { + bSrcConst[2] = GL_TRUE; + } + else + { + bSrcConst[2] = GL_FALSE; + } + + if( (GL_TRUE == bSrcConst[0]) && + (GL_TRUE == bSrcConst[1]) && + (GL_TRUE == bSrcConst[2]) ) + { + if( GL_FALSE == mov_temp(pAsm, 1) ) + { + return GL_FALSE; + } + if( GL_FALSE == mov_temp(pAsm, 2) ) + { + return GL_FALSE; + } + + return GL_TRUE; + } + else if( (GL_TRUE == bSrcConst[0]) && + (GL_TRUE == bSrcConst[1]) ) + { + if(pILInst->SrcReg[0].Index != pILInst->SrcReg[1].Index) + { + if( GL_FALSE == mov_temp(pAsm, 1) ) + { + return 1; + } + } + + return GL_TRUE; + } + else if ( (GL_TRUE == bSrcConst[0]) && + (GL_TRUE == bSrcConst[2]) ) + { + if(pILInst->SrcReg[0].Index != pILInst->SrcReg[2].Index) + { + if( GL_FALSE == mov_temp(pAsm, 2) ) + { + return GL_FALSE; + } + } + + return GL_TRUE; + } + else if( (GL_TRUE == bSrcConst[1]) && + (GL_TRUE == bSrcConst[2]) ) + { + if(pILInst->SrcReg[1].Index != pILInst->SrcReg[2].Index) + { + if( GL_FALSE == mov_temp(pAsm, 2) ) + { + return GL_FALSE; + } + } + + return GL_TRUE; + } + + return GL_TRUE; +} + +GLboolean assemble_src(r700_AssemblerBase *pAsm, + int src, + int fld) +{ + struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); + + if (fld == -1) + { + fld = src; + } + + if(pAsm->aArgSubst[1+src] >= 0) + { + setaddrmode_PVSSRC(&(pAsm->S[fld].src), ADDR_ABSOLUTE); + pAsm->S[fld].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[fld].src.reg = pAsm->aArgSubst[1+src]; + } + else + { + switch (pILInst->SrcReg[src].File) + { + case PROGRAM_TEMPORARY: + setaddrmode_PVSSRC(&(pAsm->S[fld].src), ADDR_ABSOLUTE); + pAsm->S[fld].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[fld].src.reg = pILInst->SrcReg[src].Index + pAsm->starting_temp_register_number; + break; + case PROGRAM_CONSTANT: + case PROGRAM_LOCAL_PARAM: + case PROGRAM_ENV_PARAM: + case PROGRAM_STATE_VAR: + if (1 == pILInst->SrcReg[src].RelAddr) + { + setaddrmode_PVSSRC(&(pAsm->S[fld].src), ADDR_RELATIVE_A0); + } + else + { + setaddrmode_PVSSRC(&(pAsm->S[fld].src), ADDR_ABSOLUTE); + } + + pAsm->S[fld].src.rtype = SRC_REG_CONSTANT; + pAsm->S[fld].src.reg = pILInst->SrcReg[src].Index; + break; + case PROGRAM_INPUT: + setaddrmode_PVSSRC(&(pAsm->S[fld].src), ADDR_ABSOLUTE); + pAsm->S[fld].src.rtype = SRC_REG_INPUT; + switch (pAsm->currentShaderType) + { + case SPT_FP: + pAsm->S[fld].src.reg = pAsm->uiFP_AttributeMap[pILInst->SrcReg[src].Index]; + break; + case SPT_VP: + pAsm->S[fld].src.reg = pAsm->ucVP_AttributeMap[pILInst->SrcReg[src].Index]; + break; + } + break; + default: + r700_error(ERROR_ASM_SRCARGUMENT, "Invalid source argument type"); + return GL_FALSE; + } + } + + pAsm->S[fld].src.swizzlex = pILInst->SrcReg[src].Swizzle & 0x7; + pAsm->S[fld].src.swizzley = (pILInst->SrcReg[src].Swizzle >> 3) & 0x7; + pAsm->S[fld].src.swizzlez = (pILInst->SrcReg[src].Swizzle >> 6) & 0x7; + pAsm->S[fld].src.swizzlew = (pILInst->SrcReg[src].Swizzle >> 9) & 0x7; + + pAsm->S[fld].src.negx = pILInst->SrcReg[src].NegateBase & 0x1; + pAsm->S[fld].src.negy = (pILInst->SrcReg[src].NegateBase >> 1) & 0x1; + pAsm->S[fld].src.negz = (pILInst->SrcReg[src].NegateBase >> 2) & 0x1; + pAsm->S[fld].src.negw = (pILInst->SrcReg[src].NegateBase >> 3) & 0x1; + + return GL_TRUE; +} + +GLboolean assemble_dst(r700_AssemblerBase *pAsm) +{ + struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); + switch (pILInst->DstReg.File) + { + case PROGRAM_TEMPORARY: + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = pILInst->DstReg.Index + pAsm->starting_temp_register_number; + break; + case PROGRAM_ADDRESS: + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_A0; + pAsm->D.dst.reg = 0; + break; + case PROGRAM_OUTPUT: + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_OUT; + switch (pAsm->currentShaderType) + { + case SPT_FP: + pAsm->D.dst.reg = pAsm->uiFP_OutputMap[pILInst->DstReg.Index]; + break; + case SPT_VP: + pAsm->D.dst.reg = pAsm->ucVP_OutputMap[pILInst->DstReg.Index]; + break; + } + break; + default: + r700_error(ERROR_ASM_DSTARGUMENT, "Invalid destination output argument type"); + return GL_FALSE; + } + + pAsm->D.dst.writex = pILInst->DstReg.WriteMask & 0x1; + pAsm->D.dst.writey = (pILInst->DstReg.WriteMask >> 1) & 0x1; + pAsm->D.dst.writez = (pILInst->DstReg.WriteMask >> 2) & 0x1; + pAsm->D.dst.writew = (pILInst->DstReg.WriteMask >> 3) & 0x1; + + return GL_TRUE; +} + +GLboolean tex_dst(r700_AssemblerBase *pAsm) +{ + struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); + + if(PROGRAM_TEMPORARY == pILInst->DstReg.File) + { + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = pAsm->pILInst[pAsm->uiCurInst].DstReg.Index + pAsm->starting_temp_register_number; + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + } + else if(PROGRAM_OUTPUT == pILInst->DstReg.File) + { + pAsm->D.dst.rtype = DST_REG_OUT; + switch (pAsm->currentShaderType) + { + case SPT_FP: + pAsm->D.dst.reg = pAsm->uiFP_OutputMap[pILInst->DstReg.Index]; + break; + case SPT_VP: + pAsm->D.dst.reg = pAsm->ucVP_OutputMap[pILInst->DstReg.Index]; + break; + } + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + } + else + { + r700_error(ERROR_ASM_DSTARGUMENT, "Invalid destination output argument type"); + return GL_FALSE; + } + + pAsm->D.dst.writex = pILInst->DstReg.WriteMask & 0x1; + pAsm->D.dst.writey = (pILInst->DstReg.WriteMask >> 1) & 0x1; + pAsm->D.dst.writez = (pILInst->DstReg.WriteMask >> 2) & 0x1; + pAsm->D.dst.writew = (pILInst->DstReg.WriteMask >> 3) & 0x1; + + return GL_TRUE; +} + +GLboolean tex_src(r700_AssemblerBase *pAsm) +{ + struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); + + GLboolean bValidTexCoord = GL_FALSE; + + switch (pILInst->SrcReg[0].File) + { + case PROGRAM_TEMPORARY: + bValidTexCoord = GL_TRUE; + + pAsm->S[0].src.reg = pILInst->SrcReg[0].Index + pAsm->starting_temp_register_number; + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + + break; + case PROGRAM_INPUT: + switch (pILInst->SrcReg[0].Index) + { + case FRAG_ATTRIB_COL0: + case FRAG_ATTRIB_COL1: + case FRAG_ATTRIB_TEX0: + case FRAG_ATTRIB_TEX1: + case FRAG_ATTRIB_TEX2: + case FRAG_ATTRIB_TEX3: + case FRAG_ATTRIB_TEX4: + case FRAG_ATTRIB_TEX5: + case FRAG_ATTRIB_TEX6: + case FRAG_ATTRIB_TEX7: + bValidTexCoord = GL_TRUE; + + pAsm->S[0].src.reg = pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index]; + pAsm->S[0].src.rtype = SRC_REG_INPUT; + } + break; + } + + if(GL_TRUE == bValidTexCoord) + { + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + } + else + { + r700_error(ERROR_ASM_BADTEXSRC, "Invalid source texcoord for TEX instruction"); + return GL_FALSE; + } + + pAsm->S[0].src.swizzlex = pILInst->SrcReg[0].Swizzle & 0x7; + pAsm->S[0].src.swizzley = (pILInst->SrcReg[0].Swizzle >> 3) & 0x7; + pAsm->S[0].src.swizzlez = (pILInst->SrcReg[0].Swizzle >> 6) & 0x7; + pAsm->S[0].src.swizzlew = (pILInst->SrcReg[0].Swizzle >> 9) & 0x7; + + pAsm->S[0].src.negx = pILInst->SrcReg[0].NegateBase & 0x1; + pAsm->S[0].src.negy = (pILInst->SrcReg[0].NegateBase >> 1) & 0x1; + pAsm->S[0].src.negz = (pILInst->SrcReg[0].NegateBase >> 2) & 0x1; + pAsm->S[0].src.negw = (pILInst->SrcReg[0].NegateBase >> 3) & 0x1; + + return GL_TRUE; +} + +GLboolean assemble_tex_instruction(r700_AssemblerBase *pAsm) +{ + PVSSRC * texture_coordinate_source; + PVSSRC * texture_unit_source; + + R700TextureInstruction* tex_instruction_ptr = (R700TextureInstruction*) CALLOC_STRUCT(R700TextureInstruction); + if (tex_instruction_ptr == NULL) + { + return GL_FALSE; + } + Init_R700TextureInstruction(tex_instruction_ptr); + + texture_coordinate_source = &(pAsm->S[0].src); + texture_unit_source = &(pAsm->S[1].src); + + tex_instruction_ptr->m_Word0.f.tex_inst = pAsm->D.dst.opcode; + tex_instruction_ptr->m_Word0.f.bc_frac_mode = 0x0; + tex_instruction_ptr->m_Word0.f.fetch_whole_quad = 0x0; + + tex_instruction_ptr->m_Word0.f.resource_id = texture_unit_source->reg; + + tex_instruction_ptr->m_Word1.f.lod_bias = 0x0; + tex_instruction_ptr->m_Word1.f.coord_type_x = SQ_TEX_NORMALIZED; + tex_instruction_ptr->m_Word1.f.coord_type_y = SQ_TEX_NORMALIZED; + tex_instruction_ptr->m_Word1.f.coord_type_z = SQ_TEX_NORMALIZED; + tex_instruction_ptr->m_Word1.f.coord_type_w = SQ_TEX_NORMALIZED; + + tex_instruction_ptr->m_Word2.f.offset_x = 0x0; + tex_instruction_ptr->m_Word2.f.offset_y = 0x0; + tex_instruction_ptr->m_Word2.f.offset_z = 0x0; + + tex_instruction_ptr->m_Word2.f.sampler_id = texture_unit_source->reg; + + // dst + if ( (pAsm->D.dst.rtype == DST_REG_TEMPORARY) || + (pAsm->D.dst.rtype == DST_REG_OUT) ) + { + tex_instruction_ptr->m_Word0.f.src_gpr = texture_coordinate_source->reg; + tex_instruction_ptr->m_Word0.f.src_rel = SQ_ABSOLUTE; + + tex_instruction_ptr->m_Word1.f.dst_gpr = pAsm->D.dst.reg; + tex_instruction_ptr->m_Word1.f.dst_rel = SQ_ABSOLUTE; + + tex_instruction_ptr->m_Word1.f.dst_sel_x = (pAsm->D.dst.writex ? texture_unit_source->swizzlex : SQ_SEL_MASK); + tex_instruction_ptr->m_Word1.f.dst_sel_y = (pAsm->D.dst.writey ? texture_unit_source->swizzley : SQ_SEL_MASK); + tex_instruction_ptr->m_Word1.f.dst_sel_z = (pAsm->D.dst.writez ? texture_unit_source->swizzlez : SQ_SEL_MASK); + tex_instruction_ptr->m_Word1.f.dst_sel_w = (pAsm->D.dst.writew ? texture_unit_source->swizzlew : SQ_SEL_MASK); + + + tex_instruction_ptr->m_Word2.f.src_sel_x = texture_coordinate_source->swizzlex; + tex_instruction_ptr->m_Word2.f.src_sel_y = texture_coordinate_source->swizzley; + tex_instruction_ptr->m_Word2.f.src_sel_z = texture_coordinate_source->swizzlez; + tex_instruction_ptr->m_Word2.f.src_sel_w = texture_coordinate_source->swizzlew; + } + else + { + r700_error(ERROR_ASM_TEXDSTBADTYPE, "Only temp destination registers supported for TEX dest regs."); + return GL_FALSE; + } + + if( GL_FALSE == add_tex_instruction(pAsm, tex_instruction_ptr) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +void initialize(r700_AssemblerBase *pAsm) +{ + GLuint cycle, component; + + for (cycle=0; cyclehw_gpr[cycle][component] = (-1); + } + } + for (component=0; componenthw_cfile_addr[component] = (-1); + pAsm->hw_cfile_chan[component] = (-1); + } +} + +GLboolean assemble_alu_src(R700ALUInstruction* alu_instruction_ptr, + int source_index, + PVSSRC* pSource, + BITS scalar_channel_index) +{ + BITS src_sel; + BITS src_rel; + BITS src_chan; + BITS src_neg; + + //-------------------------------------------------------------------------- + // Source for operands src0, src1. + // Values [0,127] correspond to GPR[0..127]. + // Values [256,511] correspond to cfile constants c[0..255]. + + //-------------------------------------------------------------------------- + // Other special values are shown in the list below. + + // 248 SQ_ALU_SRC_0: special constant 0.0. + // 249 SQ_ALU_SRC_1: special constant 1.0 float. + + // 250 SQ_ALU_SRC_1_INT: special constant 1 integer. + // 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer. + + // 252 SQ_ALU_SRC_0_5: special constant 0.5 float. + // 253 SQ_ALU_SRC_LITERAL: literal constant. + + // 254 SQ_ALU_SRC_PV: previous vector result. + // 255 SQ_ALU_SRC_PS: previous scalar result. + //-------------------------------------------------------------------------- + + BITS channel_swizzle; + switch (scalar_channel_index) + { + case 0: channel_swizzle = pSource->swizzlex; break; + case 1: channel_swizzle = pSource->swizzley; break; + case 2: channel_swizzle = pSource->swizzlez; break; + case 3: channel_swizzle = pSource->swizzlew; break; + default: channel_swizzle = SQ_SEL_MASK; break; + } + + if(channel_swizzle == SQ_SEL_0) + { + src_sel = SQ_ALU_SRC_0; + } + else if (channel_swizzle == SQ_SEL_1) + { + src_sel = SQ_ALU_SRC_1; + } + else + { + if ( (pSource->rtype == SRC_REG_TEMPORARY) || + (pSource->rtype == SRC_REG_INPUT) + ) + { + src_sel = pSource->reg; + } + else if (pSource->rtype == SRC_REG_CONSTANT) + { + src_sel = pSource->reg + CFILE_REGISTER_OFFSET; + } + else + { + r700_error(ERROR_ASM_ALUSRCBADTYPE, "Source (%d) register type (%d) not one of TEMP, INPUT, or CONSTANT.", + source_index, pSource->rtype); + return GL_FALSE; + } + } + + if( ADDR_ABSOLUTE == addrmode_PVSSRC(pSource) ) + { + src_rel = SQ_ABSOLUTE; + } + else + { + src_rel = SQ_RELATIVE; + } + + switch (channel_swizzle) + { + case SQ_SEL_X: + src_chan = SQ_CHAN_X; + break; + case SQ_SEL_Y: + src_chan = SQ_CHAN_Y; + break; + case SQ_SEL_Z: + src_chan = SQ_CHAN_Z; + break; + case SQ_SEL_W: + src_chan = SQ_CHAN_W; + break; + case SQ_SEL_0: + case SQ_SEL_1: + // Does not matter since src_sel controls + src_chan = SQ_CHAN_X; + break; + default: + r700_error(ERROR_ASM_ALUSRCSELECT, "Unknown source select value (%d) in assemble_alu_src()."); + return GL_FALSE; + break; + } + + switch (scalar_channel_index) + { + case 0: src_neg = pSource->negx; break; + case 1: src_neg = pSource->negy; break; + case 2: src_neg = pSource->negz; break; + case 3: src_neg = pSource->negw; break; + default: src_neg = 0; break; + } + + switch (source_index) + { + case 0: + alu_instruction_ptr->m_Word0.f.src0_sel = src_sel; + alu_instruction_ptr->m_Word0.f.src0_rel = src_rel; + alu_instruction_ptr->m_Word0.f.src0_chan = src_chan; + alu_instruction_ptr->m_Word0.f.src0_neg = src_neg; + break; + case 1: + alu_instruction_ptr->m_Word0.f.src1_sel = src_sel; + alu_instruction_ptr->m_Word0.f.src1_rel = src_rel; + alu_instruction_ptr->m_Word0.f.src1_chan = src_chan; + alu_instruction_ptr->m_Word0.f.src1_neg = src_neg; + break; + case 2: + alu_instruction_ptr->m_Word1_OP3.f.src2_sel = src_sel; + alu_instruction_ptr->m_Word1_OP3.f.src2_rel = src_rel; + alu_instruction_ptr->m_Word1_OP3.f.src2_chan = src_chan; + alu_instruction_ptr->m_Word1_OP3.f.src2_neg = src_neg; + break; + default: + r700_error(ERROR_ASM_ALUSRCNUMBER, "Only three sources allowed in ALU opcodes."); + return GL_FALSE; + break; + } + + return GL_TRUE; +} + +GLboolean add_alu_instruction(r700_AssemblerBase* pAsm, + R700ALUInstruction* alu_instruction_ptr, + GLuint contiguous_slots_needed) +{ + if( GL_FALSE == check_current_clause(pAsm, CF_ALU_CLAUSE) ) + { + return GL_FALSE; + } + + if ( pAsm->cf_current_alu_clause_ptr == NULL || + ( (pAsm->cf_current_alu_clause_ptr != NULL) && + (pAsm->cf_current_alu_clause_ptr->m_Word1.f.count >= (GetCFMaxInstructions(pAsm->cf_current_alu_clause_ptr->m_ShaderInstType)-contiguous_slots_needed-1) ) + ) ) + { + + //new cf inst for this clause + pAsm->cf_current_alu_clause_ptr = (R700ControlFlowALUClause*) CALLOC_STRUCT(R700ControlFlowALUClause); + + // link the new cf to cf segment + if(NULL != pAsm->cf_current_alu_clause_ptr) + { + Init_R700ControlFlowALUClause(pAsm->cf_current_alu_clause_ptr); + AddCFInstruction( pAsm->pR700Shader, + (R700ControlFlowInstruction *)pAsm->cf_current_alu_clause_ptr ); + } + else + { + r700_error(ERROR_ASM_ALLOCALUCF, "Could not allocate a new ALU CF instruction."); + return GL_FALSE; + } + + pAsm->cf_current_alu_clause_ptr->m_Word0.f.kcache_bank0 = 0x0; + pAsm->cf_current_alu_clause_ptr->m_Word0.f.kcache_bank1 = 0x0; + pAsm->cf_current_alu_clause_ptr->m_Word0.f.kcache_mode0 = SQ_CF_KCACHE_NOP; + + pAsm->cf_current_alu_clause_ptr->m_Word1.f.kcache_mode1 = SQ_CF_KCACHE_NOP; + pAsm->cf_current_alu_clause_ptr->m_Word1.f.kcache_addr0 = 0x0; + pAsm->cf_current_alu_clause_ptr->m_Word1.f.kcache_addr1 = 0x0; + + //cf_current_alu_clause_ptr->m_Word1.f.count = number_of_scalar_operations - 1; + pAsm->cf_current_alu_clause_ptr->m_Word1.f.count = 0x0; + pAsm->cf_current_alu_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_ALU; + + pAsm->cf_current_alu_clause_ptr->m_Word1.f.whole_quad_mode = 0x0; + + pAsm->cf_current_alu_clause_ptr->m_Word1.f.barrier = 0x1; + } + else + { + pAsm->cf_current_alu_clause_ptr->m_Word1.f.count++; + } + + // If this clause constains any instruction that is forward dependent on a TEX instruction, + // set the whole_quad_mode for this clause + if ( pAsm->pInstDeps[pAsm->uiCurInst].nDstDep > (-1) ) + { + pAsm->cf_current_alu_clause_ptr->m_Word1.f.whole_quad_mode = 0x1; + } + + if (pAsm->cf_current_alu_clause_ptr->m_Word1.f.count >= (GetCFMaxInstructions(pAsm->cf_current_alu_clause_ptr->m_ShaderInstType)-1) ) + { + alu_instruction_ptr->m_Word0.f.last = 1; + } + + if(NULL == pAsm->cf_current_alu_clause_ptr->m_pLinkedALUInstruction) + { + pAsm->cf_current_alu_clause_ptr->m_pLinkedALUInstruction = alu_instruction_ptr; + alu_instruction_ptr->m_pLinkedALUClause = pAsm->cf_current_alu_clause_ptr; + } + + AddALUInstruction(pAsm->pR700Shader, alu_instruction_ptr); + + return GL_TRUE; +} + +void get_src_properties(R700ALUInstruction* alu_instruction_ptr, + int source_index, + BITS* psrc_sel, + BITS* psrc_rel, + BITS* psrc_chan, + BITS* psrc_neg) +{ + switch (source_index) + { + case 0: + *psrc_sel = alu_instruction_ptr->m_Word0.f.src0_sel ; + *psrc_rel = alu_instruction_ptr->m_Word0.f.src0_rel ; + *psrc_chan = alu_instruction_ptr->m_Word0.f.src0_chan; + *psrc_neg = alu_instruction_ptr->m_Word0.f.src0_neg ; + break; + + case 1: + *psrc_sel = alu_instruction_ptr->m_Word0.f.src1_sel ; + *psrc_rel = alu_instruction_ptr->m_Word0.f.src1_rel ; + *psrc_chan = alu_instruction_ptr->m_Word0.f.src1_chan; + *psrc_neg = alu_instruction_ptr->m_Word0.f.src1_neg ; + break; + + case 2: + *psrc_sel = alu_instruction_ptr->m_Word1_OP3.f.src2_sel; + *psrc_rel = alu_instruction_ptr->m_Word1_OP3.f.src2_rel; + *psrc_chan = alu_instruction_ptr->m_Word1_OP3.f.src2_chan; + *psrc_neg = alu_instruction_ptr->m_Word1_OP3.f.src2_neg; + break; + } +} + +int is_cfile(BITS sel) +{ + if (sel > 255 && sel < 512) + { + return 1; + } + return 0; +} + +int is_const(BITS sel) +{ + if (is_cfile(sel)) + { + return 1; + } + else if(sel >= SQ_ALU_SRC_0 && sel <= SQ_ALU_SRC_LITERAL) + { + return 1; + } + return 0; +} + +int is_gpr(BITS sel) +{ + if (sel >= 0 && sel < 128) + { + return 1; + } + return 0; +} + +const GLuint BANK_SWIZZLE_VEC[8] = {SQ_ALU_VEC_210, //000 + SQ_ALU_VEC_120, //001 + SQ_ALU_VEC_102, //010 + + SQ_ALU_VEC_201, //011 + SQ_ALU_VEC_012, //100 + SQ_ALU_VEC_021, //101 + + SQ_ALU_VEC_012, //110 + SQ_ALU_VEC_012}; //111 + +const GLuint BANK_SWIZZLE_SCL[8] = {SQ_ALU_SCL_210, //000 + SQ_ALU_SCL_122, //001 + SQ_ALU_SCL_122, //010 + + SQ_ALU_SCL_221, //011 + SQ_ALU_SCL_212, //100 + SQ_ALU_SCL_122, //101 + + SQ_ALU_SCL_122, //110 + SQ_ALU_SCL_122}; //111 + +GLboolean reserve_cfile(r700_AssemblerBase* pAsm, + GLuint sel, + GLuint chan) +{ + int res_match = (-1); + int res_empty = (-1); + + GLint res; + + for (res=3; res>=0; res--) + { + if(pAsm->hw_cfile_addr[ res] < 0) + { + res_empty = res; + } + else if( (pAsm->hw_cfile_addr[res] == (int)sel) + && + (pAsm->hw_cfile_chan[ res ] == (int) chan) ) + { + res_match = res; + } + } + + if(res_match >= 0) + { + // Read for this scalar component already reserved, nothing to do here. + ; + } + else if(res_empty >= 0) + { + pAsm->hw_cfile_addr[ res_empty ] = sel; + pAsm->hw_cfile_chan[ res_empty ] = chan; + } + else + { + r700_error(ERROR_ASM_CONSTCHANNEL, "All cfile read ports are used, cannot reference C$sel, channel $chan."); + return GL_FALSE; + } + return GL_TRUE; +} + +GLboolean reserve_gpr(r700_AssemblerBase* pAsm, GLuint sel, GLuint chan, GLuint cycle) +{ + if(pAsm->hw_gpr[cycle][chan] < 0) + { + pAsm->hw_gpr[cycle][chan] = sel; + } + else if(pAsm->hw_gpr[cycle][chan] != (int)sel) + { + r700_error(ERROR_ASM_BADGPRRESERVE, "Another scalar operation has already used GPR read port for given channel"); + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean cycle_for_scalar_bank_swizzle(const int swiz, const int sel, GLuint* pCycle) +{ + switch (swiz) + { + case SQ_ALU_SCL_210: + { + int table[3] = {2, 1, 0}; + *pCycle = table[sel]; + return GL_TRUE; + } + break; + case SQ_ALU_SCL_122: + { + int table[3] = {1, 2, 2}; + *pCycle = table[sel]; + return GL_TRUE; + } + break; + case SQ_ALU_SCL_212: + { + int table[3] = {2, 1, 2}; + *pCycle = table[sel]; + return GL_TRUE; + } + break; + case SQ_ALU_SCL_221: + { + int table[3] = {2, 2, 1}; + *pCycle = table[sel]; + return GL_TRUE; + } + break; + default: + r700_error(ERROR_ASM_BADSCALARBZ, "Bad Scalar bank swizzle value"); + break; + } + + return GL_FALSE; +} + +GLboolean cycle_for_vector_bank_swizzle(const int swiz, const int sel, GLuint* pCycle) +{ + switch (swiz) + { + case SQ_ALU_VEC_012: + { + int table[3] = {0, 1, 2}; + *pCycle = table[sel]; + } + break; + case SQ_ALU_VEC_021: + { + int table[3] = {0, 2, 1}; + *pCycle = table[sel]; + } + break; + case SQ_ALU_VEC_120: + { + int table[3] = {1, 2, 0}; + *pCycle = table[sel]; + } + break; + case SQ_ALU_VEC_102: + { + int table[3] = {1, 0, 2}; + *pCycle = table[sel]; + } + break; + case SQ_ALU_VEC_201: + { + int table[3] = {2, 0, 1}; + *pCycle = table[sel]; + } + break; + case SQ_ALU_VEC_210: + { + int table[3] = {2, 1, 0}; + *pCycle = table[sel]; + } + break; + default: + r700_error(ERROR_ASM_BADVECTORBZ, "Bad Vec bank swizzle value"); + return GL_FALSE; + break; + } + + return GL_TRUE; +} + +GLboolean check_scalar(r700_AssemblerBase* pAsm, + R700ALUInstruction* alu_instruction_ptr) +{ + GLuint cycle; + GLuint bank_swizzle; + GLuint const_count = 0; + + BITS sel; + BITS chan; + BITS rel; + BITS neg; + + GLuint src; + + BITS src_sel [3] = {0,0,0}; + BITS src_chan[3] = {0,0,0}; + BITS src_rel [3] = {0,0,0}; + BITS src_neg [3] = {0,0,0}; + + GLuint swizzle_key; + + GLuint number_of_operands = r700GetNumOperands(pAsm); + + for (src=0; srcm_Word1.f.bank_swizzle = BANK_SWIZZLE_SCL[ swizzle_key ]; + + for (src=0; srcm_Word1.f.bank_swizzle; + + if( GL_FALSE == cycle_for_scalar_bank_swizzle(bank_swizzle, src, &cycle) ) + { + return GL_FALSE; + } + + if(cycle < const_count) + { + if( GL_FALSE == reserve_gpr(pAsm, sel, chan, cycle) ) + { + return GL_FALSE; + } + } + } + } + + return GL_TRUE; +} + +GLboolean check_vector(r700_AssemblerBase* pAsm, + R700ALUInstruction* alu_instruction_ptr) +{ + GLuint cycle; + GLuint bank_swizzle; + GLuint const_count = 0; + + GLuint src; + + BITS sel; + BITS chan; + BITS rel; + BITS neg; + + BITS src_sel [3] = {0,0,0}; + BITS src_chan[3] = {0,0,0}; + BITS src_rel [3] = {0,0,0}; + BITS src_neg [3] = {0,0,0}; + + GLuint swizzle_key; + + GLuint number_of_operands = r700GetNumOperands(pAsm); + + for (src=0; srcm_Word1.f.bank_swizzle = BANK_SWIZZLE_VEC[swizzle_key]; + + for (src=0; srcm_Word1.f.bank_swizzle; + + if( is_gpr(sel) ) + { + if( GL_FALSE == cycle_for_vector_bank_swizzle(bank_swizzle, src, &cycle) ) + { + return GL_FALSE; + } + + if ( (src == 1) && + (sel == src_sel[0]) && + (chan == src_chan[0]) ) + { + } + else + { + if( GL_FALSE == reserve_gpr(pAsm, sel, chan, cycle) ) + { + return GL_FALSE; + } + } + } + else if( is_const(sel) ) + { + const_count++; + + if( is_cfile(sel) ) + { + if( GL_FALSE == reserve_cfile(pAsm, sel, chan) ) + { + return GL_FALSE; + } + } + } + } + + return GL_TRUE; +} + +GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) +{ + GLuint number_of_scalar_operations; + GLboolean is_single_scalar_operation; + GLuint scalar_channel_index; + + PVSSRC * pcurrent_source; + int current_source_index; + GLuint contiguous_slots_needed; + + GLuint uNumSrc = r700GetNumOperands(pAsm); + GLuint channel_swizzle, j; + GLuint chan_counter[4] = {0, 0, 0, 0}; + PVSSRC * pSource[3]; + GLboolean bSplitInst = GL_FALSE; + + if (1 == pAsm->D.dst.math) + { + is_single_scalar_operation = GL_TRUE; + number_of_scalar_operations = 1; + } + else + { + is_single_scalar_operation = GL_FALSE; + number_of_scalar_operations = 4; + + /* check read port, only very preliminary algorithm, not count in + src0/1 same comp case and prev slot repeat case; also not count relative + addressing. TODO: improve performance. */ + for(j=0; jS[j].src); + } + for(scalar_channel_index=0; scalar_channel_index<4; scalar_channel_index++) + { + for(j=0; jswizzlex; break; + case 1: channel_swizzle = pSource[j]->swizzley; break; + case 2: channel_swizzle = pSource[j]->swizzlez; break; + case 3: channel_swizzle = pSource[j]->swizzlew; break; + default: channel_swizzle = SQ_SEL_MASK; break; + } + if ( ((pSource[j]->rtype == SRC_REG_TEMPORARY) || + (pSource[j]->rtype == SRC_REG_INPUT)) + && (channel_swizzle <= SQ_SEL_W) ) + { + chan_counter[channel_swizzle]++; + } + } + } + if( (chan_counter[SQ_SEL_X] > 3) + || (chan_counter[SQ_SEL_Y] > 3) + || (chan_counter[SQ_SEL_Z] > 3) + || (chan_counter[SQ_SEL_W] > 3) ) /* each chan bank has only 3 ports. */ + { + bSplitInst = GL_TRUE; + } + } + + contiguous_slots_needed = 0; + + if(GL_TRUE == is_reduction_opcode(&(pAsm->D)) ) + { + contiguous_slots_needed = 4; + } + + initialize(pAsm); + + for (scalar_channel_index=0; + scalar_channel_index < number_of_scalar_operations; + scalar_channel_index++) + { + R700ALUInstruction* alu_instruction_ptr = (R700ALUInstruction*) CALLOC_STRUCT(R700ALUInstruction); + if (alu_instruction_ptr == NULL) + { + return GL_FALSE; + } + Init_R700ALUInstruction(alu_instruction_ptr); + + //src 0 + current_source_index = 0; + pcurrent_source = &(pAsm->S[0].src); + + if (GL_FALSE == assemble_alu_src(alu_instruction_ptr, + current_source_index, + pcurrent_source, + scalar_channel_index) ) + { + return GL_FALSE; + } + + if (pAsm->D.dst.math == 0) + { + // Process source 1 + current_source_index = 1; + pcurrent_source = &(pAsm->S[current_source_index].src); + + if (GL_FALSE == assemble_alu_src(alu_instruction_ptr, + current_source_index, + pcurrent_source, + scalar_channel_index) ) + { + return GL_FALSE; + } + } + + //other bits + alu_instruction_ptr->m_Word0.f.index_mode = SQ_INDEX_LOOP; + + if( (is_single_scalar_operation == GL_TRUE) + || (GL_TRUE == bSplitInst) ) + { + alu_instruction_ptr->m_Word0.f.last = 1; + } + else + { + alu_instruction_ptr->m_Word0.f.last = (scalar_channel_index == 3) ? 1 : 0; + } + + alu_instruction_ptr->m_Word0.f.pred_sel = 0x0; + alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0x0; + alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0x0; + + // dst + if( (pAsm->D.dst.rtype == DST_REG_TEMPORARY) || + (pAsm->D.dst.rtype == DST_REG_OUT) ) + { + alu_instruction_ptr->m_Word1.f.dst_gpr = pAsm->D.dst.reg; + } + else + { + r700_error(ERROR_ASM_ALUDSTBADTYPE, "Only temp destination registers supported for ALU dest regs."); + return GL_FALSE; + } + + alu_instruction_ptr->m_Word1.f.dst_rel = SQ_ABSOLUTE; //D.rtype + + if ( is_single_scalar_operation == GL_TRUE ) + { + // Override scalar_channel_index since only one scalar value will be written + if(pAsm->D.dst.writex) + { + scalar_channel_index = 0; + } + else if(pAsm->D.dst.writey) + { + scalar_channel_index = 1; + } + else if(pAsm->D.dst.writez) + { + scalar_channel_index = 2; + } + else if(pAsm->D.dst.writew) + { + scalar_channel_index = 3; + } + } + + alu_instruction_ptr->m_Word1.f.dst_chan = scalar_channel_index; + + alu_instruction_ptr->m_Word1.f.clamp = pAsm->pILInst[pAsm->uiCurInst].SaturateMode; + + if (pAsm->D.dst.op3) + { + //op3 + + alu_instruction_ptr->m_Word1_OP3.f.alu_inst = pAsm->D.dst.opcode; + + //There's 3rd src for op3 + current_source_index = 2; + pcurrent_source = &(pAsm->S[current_source_index].src); + + if ( GL_FALSE == assemble_alu_src(alu_instruction_ptr, + current_source_index, + pcurrent_source, + scalar_channel_index) ) + { + return GL_FALSE; + } + } + else + { + //op2 + if (pAsm->bR6xx) + { + alu_instruction_ptr->m_Word1_OP2.f6.alu_inst = pAsm->D.dst.opcode; + + alu_instruction_ptr->m_Word1_OP2.f6.src0_abs = 0x0; + alu_instruction_ptr->m_Word1_OP2.f6.src1_abs = 0x0; + + //alu_instruction_ptr->m_Word1_OP2.f6.update_execute_mask = 0x0; + //alu_instruction_ptr->m_Word1_OP2.f6.update_pred = 0x0; + switch (scalar_channel_index) + { + case 0: + alu_instruction_ptr->m_Word1_OP2.f6.write_mask = pAsm->D.dst.writex; + break; + case 1: + alu_instruction_ptr->m_Word1_OP2.f6.write_mask = pAsm->D.dst.writey; + break; + case 2: + alu_instruction_ptr->m_Word1_OP2.f6.write_mask = pAsm->D.dst.writez; + break; + case 3: + alu_instruction_ptr->m_Word1_OP2.f6.write_mask = pAsm->D.dst.writew; + break; + default: + alu_instruction_ptr->m_Word1_OP2.f6.write_mask = SQ_SEL_MASK; + break; + } + alu_instruction_ptr->m_Word1_OP2.f6.omod = SQ_ALU_OMOD_OFF; + } + else + { + alu_instruction_ptr->m_Word1_OP2.f.alu_inst = pAsm->D.dst.opcode; + + alu_instruction_ptr->m_Word1_OP2.f.src0_abs = 0x0; + alu_instruction_ptr->m_Word1_OP2.f.src1_abs = 0x0; + + //alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0x0; + //alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0x0; + switch (scalar_channel_index) + { + case 0: + alu_instruction_ptr->m_Word1_OP2.f.write_mask = pAsm->D.dst.writex; + break; + case 1: + alu_instruction_ptr->m_Word1_OP2.f.write_mask = pAsm->D.dst.writey; + break; + case 2: + alu_instruction_ptr->m_Word1_OP2.f.write_mask = pAsm->D.dst.writez; + break; + case 3: + alu_instruction_ptr->m_Word1_OP2.f.write_mask = pAsm->D.dst.writew; + break; + default: + alu_instruction_ptr->m_Word1_OP2.f.write_mask = SQ_SEL_MASK; + break; + } + alu_instruction_ptr->m_Word1_OP2.f.omod = SQ_ALU_OMOD_OFF; + } + } + + if(GL_FALSE == add_alu_instruction(pAsm, alu_instruction_ptr, contiguous_slots_needed) ) + { + return GL_FALSE; + } + + /* + * Judge the type of current instruction, is it vector or scalar + * instruction. + */ + if (is_single_scalar_operation) + { + if(GL_FALSE == check_scalar(pAsm, alu_instruction_ptr) ) + { + return GL_FALSE; + } + } + else + { + if(GL_FALSE == check_vector(pAsm, alu_instruction_ptr) ) + { + return 1; + } + } + + contiguous_slots_needed = 0; + } + + return GL_TRUE; +} + +GLboolean next_ins(r700_AssemblerBase *pAsm) +{ + struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); + + if( GL_TRUE == IsTex(pILInst->Opcode) ) + { + if( GL_FALSE == assemble_tex_instruction(pAsm) ) + { + r700_error(ERROR_ASM_TEXINSTRUCTION, "Error assembling TEX instruction"); + return GL_FALSE; + } + } + else + { //ALU + if( GL_FALSE == assemble_alu_instruction(pAsm) ) + { + r700_error(ERROR_ASM_TEXINSTRUCTION, "Error assembling ALU instruction"); + return GL_FALSE; + } + } + + if(pAsm->D.dst.rtype == DST_REG_OUT) + { + if(pAsm->D.dst.op3) + { + // There is no mask for OP3 instructions, so all channels are written + pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number] = 0xF; + } + else + { + pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number] + |= (unsigned char)pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask; + } + } + + //reset for next inst. + pAsm->D.bits = 0; + pAsm->S[0].bits = 0; + pAsm->S[1].bits = 0; + pAsm->S[2].bits = 0; + + return GL_TRUE; +} + +GLboolean assemble_math_function(r700_AssemblerBase* pAsm, BITS opcode) +{ + BITS tmp; + + checkop1(pAsm); + + tmp = gethelpr(pAsm); + + // opcode tmp.x, a.x + // MOV dst, tmp.x + + pAsm->D.dst.opcode = opcode; + pAsm->D.dst.math = 1; + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + pAsm->D.dst.writex = 1; + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if ( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + // Now replicate result to all necessary channels in destination + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = DST_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp; + + setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X); + noneg_PVSSRC(&(pAsm->S[0].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_ABS(r700_AssemblerBase *pAsm) +{ + checkop1(pAsm); + + pAsm->D.dst.opcode = SQ_OP2_INST_MAX; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + pAsm->S[1].bits = pAsm->S[0].bits; + flipneg_PVSSRC(&(pAsm->S[1].src)); + + if ( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_ADD(r700_AssemblerBase *pAsm) +{ + if( GL_FALSE == checkop2(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP2_INST_ADD; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 1, -1) ) + { + return GL_FALSE; + } + + if(pAsm->pILInst[pAsm->uiCurInst].Opcode == OPCODE_SUB) + { + flipneg_PVSSRC(&(pAsm->S[1].src)); + } + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_BAD(char *opcode_str) +{ + r700_error(TODO_ASM_NEEDIMPINST, "Not yet implemented instruction (%s)", opcode_str); + return GL_FALSE; +} + +GLboolean assemble_CMP(r700_AssemblerBase *pAsm) +{ + int tmp; + + if( GL_FALSE == checkop3(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP3_INST_CNDGE; + pAsm->D.dst.op3 = 1; + + tmp = (-1); + + if(0xF != pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask) + { + //OP3 has no support for write mask + tmp = gethelpr(pAsm); + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + + nomask_PVSDST(&(pAsm->D.dst)); + } + else + { + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + } + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 2, 1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 1, 2) ) + { + return GL_FALSE; + } + + if ( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + if (0xF != pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask) + { + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + + //tmp for source + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp; + + noneg_PVSSRC(&(pAsm->S[0].src)); + noswizzle_PVSSRC(&(pAsm->S[0].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + } + + return GL_TRUE; +} + +GLboolean assemble_COS(r700_AssemblerBase *pAsm) +{ + return assemble_math_function(pAsm, SQ_OP2_INST_COS); +} + +GLboolean assemble_DOT(r700_AssemblerBase *pAsm) +{ + if( GL_FALSE == checkop2(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP2_INST_DOT4; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 1, -1) ) + { + return GL_FALSE; + } + + if(OPCODE_DP3 == pAsm->pILInst[pAsm->uiCurInst].Opcode) + { + zerocomp_PVSSRC(&(pAsm->S[0].src), 3); + zerocomp_PVSSRC(&(pAsm->S[1].src), 3); + } + else if(pAsm->pILInst[pAsm->uiCurInst].Opcode == OPCODE_DPH) + { + onecomp_PVSSRC(&(pAsm->S[1].src), 3); + } + + if ( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_DST(r700_AssemblerBase *pAsm) +{ + if( GL_FALSE == checkop2(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP2_INST_MUL; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 1, -1) ) + { + return GL_FALSE; + } + + onecomp_PVSSRC(&(pAsm->S[0].src), 0); + onecomp_PVSSRC(&(pAsm->S[0].src), 3); + + onecomp_PVSSRC(&(pAsm->S[1].src), 0); + onecomp_PVSSRC(&(pAsm->S[1].src), 2); + + if ( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_EX2(r700_AssemblerBase *pAsm) +{ + return assemble_math_function(pAsm, SQ_OP2_INST_EXP_IEEE); +} + +GLboolean assemble_FLR(r700_AssemblerBase *pAsm) +{ + checkop1(pAsm); + + pAsm->D.dst.opcode = SQ_OP2_INST_FLOOR; + + if ( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + if ( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if ( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_FLR_INT(r700_AssemblerBase *pAsm) +{ + return assemble_math_function(pAsm, SQ_OP2_INST_FLT_TO_INT); +} + +GLboolean assemble_FRC(r700_AssemblerBase *pAsm) +{ + checkop1(pAsm); + + pAsm->D.dst.opcode = SQ_OP2_INST_FRACT; + + if ( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + if ( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if ( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_KIL(r700_AssemblerBase *pAsm) +{ + checkop1(pAsm); + + pAsm->D.dst.opcode = SQ_OP2_INST_KILLGT; + + if ( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.writex = 0; + pAsm->D.dst.writey = 0; + pAsm->D.dst.writez = 0; + pAsm->D.dst.writew = 0; + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = 0; + + setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_0); + noneg_PVSSRC(&(pAsm->S[0].src)); + + pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; + + if(PROGRAM_TEMPORARY == pAsm->pILInst[pAsm->uiCurInst].DstReg.File) + { + pAsm->S[1].src.reg = pAsm->pILInst[pAsm->uiCurInst].DstReg.Index + pAsm->starting_temp_register_number; + } + else + { //PROGRAM_OUTPUT + pAsm->S[1].src.reg = pAsm->uiFP_OutputMap[pAsm->pILInst[pAsm->uiCurInst].DstReg.Index]; + } + + setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); + noswizzle_PVSSRC(&(pAsm->S[1].src)); + + if ( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + pAsm->pR700Shader->killIsUsed = GL_TRUE; + + return GL_TRUE; +} + +GLboolean assemble_LG2(r700_AssemblerBase *pAsm) +{ + return assemble_math_function(pAsm, SQ_OP2_INST_LOG_IEEE); +} + +GLboolean assemble_LRP(r700_AssemblerBase *pAsm) +{ + BITS tmp; + + if( GL_FALSE == checkop3(pAsm) ) + { + return GL_FALSE; + } + + tmp = gethelpr(pAsm); + + pAsm->D.dst.opcode = SQ_OP2_INST_ADD; + + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + nomask_PVSDST(&(pAsm->D.dst)); + + + if( GL_FALSE == assemble_src(pAsm, 1, 0) ) + { + return GL_FALSE; + } + + if ( GL_FALSE == assemble_src(pAsm, 2, 1) ) + { + return GL_FALSE; + } + + neg_PVSSRC(&(pAsm->S[1].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP3_INST_MULADD; + pAsm->D.dst.op3 = 1; + + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + nomask_PVSDST(&(pAsm->D.dst)); + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp; + noswizzle_PVSSRC(&(pAsm->S[0].src)); + + + if( GL_FALSE == assemble_src(pAsm, 0, 1) ) + { + return GL_FALSE; + } + if( GL_FALSE == assemble_src(pAsm, 2, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp; + noswizzle_PVSSRC(&(pAsm->S[0].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_MAD(struct r700_AssemblerBase *pAsm) +{ + int tmp, ii; + GLboolean bReplaceDst = GL_FALSE; + struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); + + if( GL_FALSE == checkop3(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP3_INST_MULADD; + pAsm->D.dst.op3 = 1; + + tmp = (-1); + + if(PROGRAM_TEMPORARY == pILInst->DstReg.File) + { /* TODO : more investigation on MAD src and dst using same register */ + for(ii=0; ii<3; ii++) + { + if( (PROGRAM_TEMPORARY == pILInst->SrcReg[ii].File) + && (pILInst->DstReg.Index == pILInst->SrcReg[ii].Index) ) + { + bReplaceDst = GL_TRUE; + break; + } + } + } + if(0xF != pILInst->DstReg.WriteMask) + { /* OP3 has no support for write mask */ + bReplaceDst = GL_TRUE; + } + + if(GL_TRUE == bReplaceDst) + { + tmp = gethelpr(pAsm); + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + + nomask_PVSDST(&(pAsm->D.dst)); + } + else + { + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + } + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 1, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 2, -1) ) + { + return GL_FALSE; + } + + if ( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + if (GL_TRUE == bReplaceDst) + { + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + + //tmp for source + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp; + + noneg_PVSSRC(&(pAsm->S[0].src)); + noswizzle_PVSSRC(&(pAsm->S[0].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + } + + return GL_TRUE; +} + +/* LIT dst, src */ +GLboolean assemble_LIT(r700_AssemblerBase *pAsm) +{ + unsigned int dstReg; + unsigned int dstType; + unsigned int srcReg; + unsigned int srcType; + checkop1(pAsm); + int tmp = gethelpr(pAsm); + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + dstReg = pAsm->D.dst.reg; + dstType = pAsm->D.dst.rtype; + srcReg = pAsm->S[0].src.reg; + srcType = pAsm->S[0].src.rtype; + + /* dst.xw, <- 1.0 */ + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + pAsm->D.dst.rtype = dstType; + pAsm->D.dst.reg = dstReg; + pAsm->D.dst.writex = 1; + pAsm->D.dst.writey = 0; + pAsm->D.dst.writez = 0; + pAsm->D.dst.writew = 1; + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp; + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + noneg_PVSSRC(&(pAsm->S[0].src)); + pAsm->S[0].src.swizzlex = SQ_SEL_1; + pAsm->S[0].src.swizzley = SQ_SEL_1; + pAsm->S[0].src.swizzlez = SQ_SEL_1; + pAsm->S[0].src.swizzlew = SQ_SEL_1; + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + /* dst.y = max(src.x, 0.0) */ + pAsm->D.dst.opcode = SQ_OP2_INST_MAX; + pAsm->D.dst.rtype = dstType; + pAsm->D.dst.reg = dstReg; + pAsm->D.dst.writex = 0; + pAsm->D.dst.writey = 1; + pAsm->D.dst.writez = 0; + pAsm->D.dst.writew = 0; + pAsm->S[0].src.rtype = srcType; + pAsm->S[0].src.reg = srcReg; + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + noneg_PVSSRC(&(pAsm->S[0].src)); + pAsm->S[0].src.swizzlex = SQ_SEL_X; + pAsm->S[0].src.swizzley = SQ_SEL_X; + pAsm->S[0].src.swizzlez = SQ_SEL_X; + pAsm->S[0].src.swizzlew = SQ_SEL_X; + pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[1].src.reg = tmp; + setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); + noneg_PVSSRC(&(pAsm->S[1].src)); + pAsm->S[1].src.swizzlex = SQ_SEL_0; + pAsm->S[1].src.swizzley = SQ_SEL_0; + pAsm->S[1].src.swizzlez = SQ_SEL_0; + pAsm->S[1].src.swizzlew = SQ_SEL_0; + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + /* dst.w = log(src.y) */ + pAsm->D.dst.opcode = SQ_OP2_INST_LOG_CLAMPED; + pAsm->D.dst.math = 1; + pAsm->D.dst.rtype = dstType; + pAsm->D.dst.reg = dstReg; + pAsm->D.dst.writex = 0; + pAsm->D.dst.writey = 0; + pAsm->D.dst.writez = 0; + pAsm->D.dst.writew = 1; + pAsm->S[0].src.rtype = srcType; + pAsm->S[0].src.reg = srcReg; + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + noneg_PVSSRC(&(pAsm->S[0].src)); + pAsm->S[0].src.swizzlex = SQ_SEL_Y; + pAsm->S[0].src.swizzley = SQ_SEL_Y; + pAsm->S[0].src.swizzlez = SQ_SEL_Y; + pAsm->S[0].src.swizzlew = SQ_SEL_Y; + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + /* tmp.x = amd MUL_LIT(src.w, dst.w, src.x ) */ + pAsm->D.dst.opcode = SQ_OP3_INST_MUL_LIT; + pAsm->D.dst.op3 = 1; + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + pAsm->D.dst.writex = 1; + pAsm->D.dst.writey = 0; + pAsm->D.dst.writez = 0; + pAsm->D.dst.writew = 0; + + pAsm->S[0].src.rtype = srcType; + pAsm->S[0].src.reg = srcReg; + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + noneg_PVSSRC(&(pAsm->S[0].src)); + pAsm->S[0].src.swizzlex = SQ_SEL_W; + pAsm->S[0].src.swizzley = SQ_SEL_W; + pAsm->S[0].src.swizzlez = SQ_SEL_W; + pAsm->S[0].src.swizzlew = SQ_SEL_W; + + pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[1].src.reg = dstReg; + setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); + noneg_PVSSRC(&(pAsm->S[1].src)); + pAsm->S[1].src.swizzlex = SQ_SEL_W; + pAsm->S[1].src.swizzley = SQ_SEL_W; + pAsm->S[1].src.swizzlez = SQ_SEL_W; + pAsm->S[1].src.swizzlew = SQ_SEL_W; + + pAsm->S[2].src.rtype = srcType; + pAsm->S[2].src.reg = srcReg; + setaddrmode_PVSSRC(&(pAsm->S[2].src), ADDR_ABSOLUTE); + noneg_PVSSRC(&(pAsm->S[2].src)); + pAsm->S[2].src.swizzlex = SQ_SEL_X; + pAsm->S[2].src.swizzley = SQ_SEL_X; + pAsm->S[2].src.swizzlez = SQ_SEL_X; + pAsm->S[2].src.swizzlew = SQ_SEL_X; + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + /* dst.z = exp(tmp.x) */ + pAsm->D.dst.opcode = SQ_OP2_INST_EXP_IEEE; + pAsm->D.dst.math = 1; + pAsm->D.dst.rtype = dstType; + pAsm->D.dst.reg = dstReg; + pAsm->D.dst.writex = 0; + pAsm->D.dst.writey = 0; + pAsm->D.dst.writez = 1; + pAsm->D.dst.writew = 0; + + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp; + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + noneg_PVSSRC(&(pAsm->S[0].src)); + pAsm->S[0].src.swizzlex = SQ_SEL_X; + pAsm->S[0].src.swizzley = SQ_SEL_X; + pAsm->S[0].src.swizzlez = SQ_SEL_X; + pAsm->S[0].src.swizzlew = SQ_SEL_X; + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_MAX(r700_AssemblerBase *pAsm) +{ + if( GL_FALSE == checkop2(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP2_INST_MAX; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 1, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_MIN(r700_AssemblerBase *pAsm) +{ + if( GL_FALSE == checkop2(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP2_INST_MIN; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 1, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_MOV(r700_AssemblerBase *pAsm) +{ + checkop1(pAsm); + + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + + if (GL_FALSE == assemble_dst(pAsm)) + { + return GL_FALSE; + } + + if (GL_FALSE == assemble_src(pAsm, 0, -1)) + { + return GL_FALSE; + } + + if ( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_MUL(r700_AssemblerBase *pAsm) +{ + if( GL_FALSE == checkop2(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP2_INST_MUL; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 1, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_POW(r700_AssemblerBase *pAsm) +{ + BITS tmp; + + checkop1(pAsm); + + tmp = gethelpr(pAsm); + + // LG2 tmp.x, a.swizzle + pAsm->D.dst.opcode = SQ_OP2_INST_LOG_IEEE; + pAsm->D.dst.math = 1; + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + nomask_PVSDST(&(pAsm->D.dst)); + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + // MUL tmp.x, tmp.x, b.swizzle + pAsm->D.dst.opcode = SQ_OP2_INST_MUL; + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + nomask_PVSDST(&(pAsm->D.dst)); + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp; + setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X); + noneg_PVSSRC(&(pAsm->S[0].src)); + + if( GL_FALSE == assemble_src(pAsm, 1, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + // EX2 dst.mask, tmp.x + // EX2 tmp.x, tmp.x + pAsm->D.dst.opcode = SQ_OP2_INST_EXP_IEEE; + pAsm->D.dst.math = 1; + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + nomask_PVSDST(&(pAsm->D.dst)); + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp; + setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X); + noneg_PVSSRC(&(pAsm->S[0].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + // Now replicate result to all necessary channels in destination + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = DST_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp; + + setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X); + noneg_PVSSRC(&(pAsm->S[0].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_RCP(r700_AssemblerBase *pAsm) +{ + return assemble_math_function(pAsm, SQ_OP2_INST_RECIP_IEEE); +} + +GLboolean assemble_RSQ(r700_AssemblerBase *pAsm) +{ + return assemble_math_function(pAsm, SQ_OP2_INST_RECIPSQRT_IEEE); +} + +GLboolean assemble_SIN(r700_AssemblerBase *pAsm) +{ + return assemble_math_function(pAsm, SQ_OP2_INST_SIN); +} + +GLboolean assemble_SCS(r700_AssemblerBase *pAsm) +{ + BITS tmp; + + checkop1(pAsm); + + tmp = gethelpr(pAsm); + + // COS tmp.x, a.x + pAsm->D.dst.opcode = SQ_OP2_INST_COS; + pAsm->D.dst.math = 1; + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + pAsm->D.dst.writex = 1; + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if ( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + // SIN tmp.y, a.x + pAsm->D.dst.opcode = SQ_OP2_INST_SIN; + pAsm->D.dst.math = 1; + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + pAsm->D.dst.writey = 1; + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + // MOV dst.mask, tmp + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = DST_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp; + + noswizzle_PVSSRC(&(pAsm->S[0].src)); + pAsm->S[0].src.swizzlez = SQ_SEL_0; + pAsm->S[0].src.swizzlew = SQ_SEL_0; + + if ( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_SGE(r700_AssemblerBase *pAsm) +{ + if( GL_FALSE == checkop2(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP2_INST_SETGE; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 1, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_SLT(r700_AssemblerBase *pAsm) +{ + if( GL_FALSE == checkop2(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP2_INST_SETGT; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 0, 1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 1, 0) ) + { + return GL_FALSE; + } + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_STP(r700_AssemblerBase *pAsm) +{ + return GL_TRUE; +} + +GLboolean assemble_TEX(r700_AssemblerBase *pAsm) +{ + GLboolean src_const; + + switch (pAsm->pILInst[pAsm->uiCurInst].SrcReg[0].File) + { + case PROGRAM_CONSTANT: + case PROGRAM_LOCAL_PARAM: + case PROGRAM_ENV_PARAM: + case PROGRAM_STATE_VAR: + src_const = GL_TRUE; + case PROGRAM_TEMPORARY: + case PROGRAM_INPUT: + src_const = GL_FALSE; + } + + if (GL_TRUE == src_const) + { + r700_error(TODO_ASM_CONSTTEXADDR, "TODO: Texture coordinates from a constant register not supported."); + return GL_FALSE; + } + + switch (pAsm->pILInst[pAsm->uiCurInst].Opcode) + { + case OPCODE_TEX: + pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE; + break; + case OPCODE_TXB: + r700_error(TODO_ASM_TXB, "do not support TXB yet"); + return GL_FALSE; + break; + case OPCODE_TXP: + /* TODO : tex proj version : divid first 3 components by 4th */ + pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE; + break; + default: + r700_error(ERROR_ASM_BADTEXINST, "Internal error: bad texture op (not TEX)"); + return GL_FALSE; + break; + } + + // Set src1 to tex unit id + pAsm->S[1].src.reg = pAsm->pILInst[pAsm->uiCurInst].TexSrcUnit; + pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; + + //No sw info from mesa compiler, so hard code here. + pAsm->S[1].src.swizzlex = SQ_SEL_X; + pAsm->S[1].src.swizzley = SQ_SEL_Y; + pAsm->S[1].src.swizzlez = SQ_SEL_Z; + pAsm->S[1].src.swizzlew = SQ_SEL_W; + + if( GL_FALSE == tex_dst(pAsm) ) + { + return GL_FALSE; + } + + if( GL_FALSE == tex_src(pAsm) ) + { + return GL_FALSE; + } + + if ( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_XPD(r700_AssemblerBase *pAsm) +{ + BITS tmp; + + if( GL_FALSE == checkop2(pAsm) ) + { + return GL_FALSE; + } + + tmp = gethelpr(pAsm); + + pAsm->D.dst.opcode = SQ_OP2_INST_MUL; + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + nomask_PVSDST(&(pAsm->D.dst)); + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 1, -1) ) + { + return GL_FALSE; + } + + swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_Z, SQ_SEL_X, SQ_SEL_Y, SQ_SEL_0); + swizzleagain_PVSSRC(&(pAsm->S[1].src), SQ_SEL_Y, SQ_SEL_Z, SQ_SEL_X, SQ_SEL_0); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP3_INST_MULADD; + pAsm->D.dst.op3 = 1; + + if(0xF != pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask) + { + tmp = gethelpr(pAsm); + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + + nomask_PVSDST(&(pAsm->D.dst)); + } + else + { + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + } + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 1, -1) ) + { + return GL_FALSE; + } + + swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_Y, SQ_SEL_Z, SQ_SEL_X, SQ_SEL_0); + swizzleagain_PVSSRC(&(pAsm->S[1].src), SQ_SEL_Z, SQ_SEL_X, SQ_SEL_Y, SQ_SEL_0); + + // result1 + (neg) result0 + setaddrmode_PVSSRC(&(pAsm->S[2].src),ADDR_ABSOLUTE); + pAsm->S[2].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[2].src.reg = tmp; + + neg_PVSSRC(&(pAsm->S[2].src)); + noswizzle_PVSSRC(&(pAsm->S[2].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + + if(0xF != pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask) + { + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + + // Use tmp as source + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp; + + noneg_PVSSRC(&(pAsm->S[0].src)); + noswizzle_PVSSRC(&(pAsm->S[0].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + } + + return GL_TRUE; +} + +GLboolean assemble_EXPORT(r700_AssemblerBase *pAsm) +{ + return GL_TRUE; +} + +GLboolean assemble_IF(r700_AssemblerBase *pAsm) +{ + return GL_TRUE; +} + +GLboolean assemble_ENDIF(r700_AssemblerBase *pAsm) +{ + return GL_TRUE; +} + +GLboolean AssembleInstr(GLuint uiNumberInsts, + struct prog_instruction *pILInst, + r700_AssemblerBase *pR700AsmCode) +{ + GLuint i; + + pR700AsmCode->pILInst = pILInst; + for(i=0; iuiCurInst = i; + + switch (pILInst[i].Opcode) + { + case OPCODE_ABS: + if ( GL_FALSE == assemble_ABS(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_ADD: + case OPCODE_SUB: + if ( GL_FALSE == assemble_ADD(pR700AsmCode) ) + return GL_FALSE; + break; + + case OPCODE_ARL: + r700_error(TODO_ASM_NEEDIMPINST, "Not yet implemented instruction OPCODE_ARL "); + //if ( GL_FALSE == assemble_BAD("ARL") ) + return GL_FALSE; + break; + case OPCODE_ARR: + r700_error(TODO_ASM_NEEDIMPINST, "Not yet implemented instruction OPCODE_ARR "); + //if ( GL_FALSE == assemble_BAD("ARR") ) + return GL_FALSE; + break; + + case OPCODE_CMP: + if ( GL_FALSE == assemble_CMP(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_COS: + if ( GL_FALSE == assemble_COS(pR700AsmCode) ) + return GL_FALSE; + break; + + case OPCODE_DP3: + case OPCODE_DP4: + case OPCODE_DPH: + if ( GL_FALSE == assemble_DOT(pR700AsmCode) ) + return GL_FALSE; + break; + + case OPCODE_DST: + if ( GL_FALSE == assemble_DST(pR700AsmCode) ) + return GL_FALSE; + break; + + case OPCODE_EX2: + if ( GL_FALSE == assemble_EX2(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_EXP: + r700_error(TODO_ASM_NEEDIMPINST, "Not yet implemented instruction OPCODE_EXP "); + //if ( GL_FALSE == assemble_BAD("EXP") ) + return GL_FALSE; + break; // approx of EX2 + + case OPCODE_FLR: + if ( GL_FALSE == assemble_FLR(pR700AsmCode) ) + return GL_FALSE; + break; + //case OP_FLR_INT: + // if ( GL_FALSE == assemble_FLR_INT() ) + // return GL_FALSE; + // break; + + case OPCODE_FRC: + if ( GL_FALSE == assemble_FRC(pR700AsmCode) ) + return GL_FALSE; + break; + + case OPCODE_KIL: + if ( GL_FALSE == assemble_KIL(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_LG2: + if ( GL_FALSE == assemble_LG2(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_LIT: + if ( GL_FALSE == assemble_LIT(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_LRP: + if ( GL_FALSE == assemble_LRP(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_LOG: + r700_error(TODO_ASM_NEEDIMPINST, "Not yet implemented instruction OPCODE_LOG "); + //if ( GL_FALSE == assemble_BAD("LOG") ) + return GL_FALSE; + break; // approx of LG2 + + case OPCODE_MAD: + if ( GL_FALSE == assemble_MAD(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_MAX: + if ( GL_FALSE == assemble_MAX(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_MIN: + if ( GL_FALSE == assemble_MIN(pR700AsmCode) ) + return GL_FALSE; + break; + + case OPCODE_MOV: + if ( GL_FALSE == assemble_MOV(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_MUL: + if ( GL_FALSE == assemble_MUL(pR700AsmCode) ) + return GL_FALSE; + break; + + case OPCODE_POW: + if ( GL_FALSE == assemble_POW(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_RCP: + if ( GL_FALSE == assemble_RCP(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_RSQ: + if ( GL_FALSE == assemble_RSQ(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_SIN: + if ( GL_FALSE == assemble_SIN(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_SCS: + if ( GL_FALSE == assemble_SCS(pR700AsmCode) ) + return GL_FALSE; + break; + + case OPCODE_SGE: + if ( GL_FALSE == assemble_SGE(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_SLT: + if ( GL_FALSE == assemble_SLT(pR700AsmCode) ) + return GL_FALSE; + break; + + //case OP_STP: + // if ( GL_FALSE == assemble_STP(pR700AsmCode) ) + // return GL_FALSE; + // break; + + case OPCODE_SWZ: + if ( GL_FALSE == assemble_MOV(pR700AsmCode) ) + { + return GL_FALSE; + } + else + { + if( (i+1)pInstDeps[i+1].nDstDep = i+1; //=1? + } + } + } + } + break; + + case OPCODE_TEX: + case OPCODE_TXB: + case OPCODE_TXP: + if ( GL_FALSE == assemble_TEX(pR700AsmCode) ) + return GL_FALSE; + break; + + case OPCODE_XPD: + if ( GL_FALSE == assemble_XPD(pR700AsmCode) ) + return GL_FALSE; + break; + + case OPCODE_IF : + if ( GL_FALSE == assemble_IF(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_ELSE : + r700_error(TODO_ASM_NEEDIMPINST, "Not yet implemented instruction OPCODE_ELSE "); + //if ( GL_FALSE == assemble_BAD("ELSE") ) + return GL_FALSE; + break; + case OPCODE_ENDIF: + if ( GL_FALSE == assemble_ENDIF(pR700AsmCode) ) + return GL_FALSE; + break; + + //case OPCODE_EXPORT: + // if ( GL_FALSE == assemble_EXPORT() ) + // return GL_FALSE; + // break; + + case OPCODE_END: + //pR700AsmCode->uiCurInst = i; + //This is to remaind that if in later exoort there is depth/stencil + //export, we need a mov to re-arrange DST channel, where using a + //psuedo inst, we will use this end inst to do it. + return GL_TRUE; + + default: + r700_error(ERROR_ASM_UNKNOWNILINST, "internal: unknown instruction"); + return GL_FALSE; + } + } + + return GL_TRUE; +} + +GLboolean Process_Export(r700_AssemblerBase* pAsm, + GLuint type, + GLuint export_starting_index, + GLuint export_count, + GLuint starting_register_number, + GLboolean is_depth_export) +{ + unsigned char ucWriteMask; + + check_current_clause(pAsm, CF_EMPTY_CLAUSE); + check_current_clause(pAsm, CF_EXPORT_CLAUSE); //alloc the cf_current_export_clause_ptr + + pAsm->cf_current_export_clause_ptr->m_Word0.f.type = type; + + switch (type) + { + case SQ_EXPORT_PIXEL: + if(GL_TRUE == is_depth_export) + { + pAsm->cf_current_export_clause_ptr->m_Word0.f.array_base = SQ_CF_PIXEL_Z; + } + else + { + pAsm->cf_current_export_clause_ptr->m_Word0.f.array_base = SQ_CF_PIXEL_MRT0 + export_starting_index; + } + break; + + case SQ_EXPORT_POS: + pAsm->cf_current_export_clause_ptr->m_Word0.f.array_base = SQ_CF_POS_0 + export_starting_index; + break; + + case SQ_EXPORT_PARAM: + pAsm->cf_current_export_clause_ptr->m_Word0.f.array_base = 0x0 + export_starting_index; + break; + + default: + r700_error(ERROR_ASM_BADEXPORTTYPE, "Unknown export type: %d", type); + return GL_FALSE; + break; + } + + pAsm->cf_current_export_clause_ptr->m_Word0.f.rw_gpr = starting_register_number; + + pAsm->cf_current_export_clause_ptr->m_Word0.f.rw_rel = SQ_ABSOLUTE; + pAsm->cf_current_export_clause_ptr->m_Word0.f.index_gpr = 0x0; + pAsm->cf_current_export_clause_ptr->m_Word0.f.elem_size = 0x3; + + pAsm->cf_current_export_clause_ptr->m_Word1.f.burst_count = (export_count - 1); + pAsm->cf_current_export_clause_ptr->m_Word1.f.end_of_program = 0x0; + pAsm->cf_current_export_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0; + pAsm->cf_current_export_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_EXPORT; // _DONE + pAsm->cf_current_export_clause_ptr->m_Word1.f.whole_quad_mode = 0x0; + pAsm->cf_current_export_clause_ptr->m_Word1.f.barrier = 0x1; + + if (export_count == 1) + { + ucWriteMask = pAsm->pucOutMask[starting_register_number - pAsm->starting_export_register_number]; + + if( (ucWriteMask & 0x1) != 0) + { + pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_x = SQ_SEL_X; + } + else + { + pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_x = SQ_SEL_MASK; + } + if( ((ucWriteMask>>1) & 0x1) != 0) + { + pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_y = SQ_SEL_Y; + } + else + { + pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_y = SQ_SEL_MASK; + } + if( ((ucWriteMask>>2) & 0x1) != 0) + { + pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_z = SQ_SEL_Z; + } + else + { + pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_z = SQ_SEL_MASK; + } + if( ((ucWriteMask>>3) & 0x1) != 0) + { + pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_w = SQ_SEL_W; + } + else + { + pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_w = SQ_SEL_MASK; + } + } + else + { + // This should only be used if all components for all registers have been written + pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_x = SQ_SEL_X; + pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_y = SQ_SEL_Y; + pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_z = SQ_SEL_Z; + pAsm->cf_current_export_clause_ptr->m_Word1_SWIZ.f.sel_w = SQ_SEL_W; + } + + pAsm->cf_last_export_ptr = pAsm->cf_current_export_clause_ptr; + + return GL_TRUE; +} + +GLboolean Move_Depth_Exports_To_Correct_Channels(r700_AssemblerBase *pAsm, BITS depth_channel_select) +{ + gl_inst_opcode Opcode_save = pAsm->pILInst[pAsm->uiCurInst].Opcode; //Should be OPCODE_END + pAsm->pILInst[pAsm->uiCurInst].Opcode = OPCODE_MOV; + + // MOV depth_export_register.hw_depth_channel, depth_export_register.depth_channel_select + + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = pAsm->depth_export_register_number; + + pAsm->D.dst.writex = 1; // depth goes in R channel for HW + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = DST_REG_TEMPORARY; + pAsm->S[0].src.reg = pAsm->depth_export_register_number; + + setswizzle_PVSSRC(&(pAsm->S[0].src), depth_channel_select); + + noneg_PVSSRC(&(pAsm->S[0].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + pAsm->pILInst[pAsm->uiCurInst].Opcode = Opcode_save; + + return GL_TRUE; +} + +GLboolean Process_Fragment_Exports(r700_AssemblerBase *pR700AsmCode, + GLbitfield OutputsWritten) +{ + unsigned int unBit; + + if(pR700AsmCode->depth_export_register_number >= 0) + { + if( GL_FALSE == Move_Depth_Exports_To_Correct_Channels(pR700AsmCode, SQ_SEL_Z) ) // depth + { + return GL_FALSE; + } + } + + unBit = 1 << FRAG_RESULT_COLOR; + if(OutputsWritten & unBit) + { + if( GL_FALSE == Process_Export(pR700AsmCode, + SQ_EXPORT_PIXEL, + 0, + 1, + pR700AsmCode->uiFP_OutputMap[FRAG_RESULT_COLOR], + GL_FALSE) ) + { + return GL_FALSE; + } + } + unBit = 1 << FRAG_RESULT_DEPTH; + if(OutputsWritten & unBit) + { + if( GL_FALSE == Process_Export(pR700AsmCode, + SQ_EXPORT_PIXEL, + 0, + 1, + pR700AsmCode->uiFP_OutputMap[FRAG_RESULT_DEPTH], + GL_TRUE)) + { + return GL_FALSE; + } + } + + if(pR700AsmCode->cf_last_export_ptr != NULL) + { + pR700AsmCode->cf_last_export_ptr->m_Word1.f.cf_inst = SQ_CF_INST_EXPORT_DONE; + pR700AsmCode->cf_last_export_ptr->m_Word1.f.end_of_program = 0x1; + } + + return GL_TRUE; +} + +GLboolean Process_Vertex_Exports(r700_AssemblerBase *pR700AsmCode, + GLbitfield OutputsWritten) +{ + unsigned int unBit; + unsigned int i; + + GLuint export_starting_index = 0; + GLuint export_count = pR700AsmCode->number_of_exports; + + unBit = 1 << VERT_RESULT_HPOS; + if(OutputsWritten & unBit) + { + if( GL_FALSE == Process_Export(pR700AsmCode, + SQ_EXPORT_POS, + export_starting_index, + 1, + pR700AsmCode->ucVP_OutputMap[VERT_RESULT_HPOS], + GL_FALSE) ) + { + return GL_FALSE; + } + + export_count--; + + pR700AsmCode->cf_last_export_ptr->m_Word1.f.cf_inst = SQ_CF_INST_EXPORT_DONE; + } + + pR700AsmCode->number_of_exports = export_count; + + unBit = 1 << VERT_RESULT_COL0; + if(OutputsWritten & unBit) + { + if( GL_FALSE == Process_Export(pR700AsmCode, + SQ_EXPORT_PARAM, + export_starting_index, + 1, + pR700AsmCode->ucVP_OutputMap[VERT_RESULT_COL0], + GL_FALSE) ) + { + return GL_FALSE; + } + + export_starting_index++; + } + + unBit = 1 << VERT_RESULT_COL1; + if(OutputsWritten & unBit) + { + if( GL_FALSE == Process_Export(pR700AsmCode, + SQ_EXPORT_PARAM, + export_starting_index, + 1, + pR700AsmCode->ucVP_OutputMap[VERT_RESULT_COL1], + GL_FALSE) ) + { + return GL_FALSE; + } + + export_starting_index++; + } + + for(i=0; i<8; i++) + { + unBit = 1 << (VERT_RESULT_TEX0 + i); + if(OutputsWritten & unBit) + { + if( GL_FALSE == Process_Export(pR700AsmCode, + SQ_EXPORT_PARAM, + export_starting_index, + 1, + pR700AsmCode->ucVP_OutputMap[VERT_RESULT_TEX0 + i], + GL_FALSE) ) + { + return GL_FALSE; + } + + export_starting_index++; + } + } + + // At least one param should be exported + if (export_count) + { + pR700AsmCode->cf_last_export_ptr->m_Word1.f.cf_inst = SQ_CF_INST_EXPORT_DONE; + } + else + { + if( GL_FALSE == Process_Export(pR700AsmCode, + SQ_EXPORT_PARAM, + 0, + 1, + 0, + GL_FALSE) ) + { + return GL_FALSE; + } + + pR700AsmCode->cf_last_export_ptr->m_Word1_SWIZ.f.sel_x = SQ_SEL_0; + pR700AsmCode->cf_last_export_ptr->m_Word1_SWIZ.f.sel_y = SQ_SEL_0; + pR700AsmCode->cf_last_export_ptr->m_Word1_SWIZ.f.sel_z = SQ_SEL_0; + pR700AsmCode->cf_last_export_ptr->m_Word1_SWIZ.f.sel_w = SQ_SEL_1; + pR700AsmCode->cf_last_export_ptr->m_Word1.f.cf_inst = SQ_CF_INST_EXPORT_DONE; + } + + pR700AsmCode->cf_last_export_ptr->m_Word1.f.end_of_program = 0x1; + + return GL_TRUE; +} + +GLboolean Clean_Up_Assembler(r700_AssemblerBase *pR700AsmCode) +{ + FREE(pR700AsmCode->pucOutMask); + FREE(pR700AsmCode->pInstDeps); + return GL_TRUE; +} + diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h new file mode 100644 index 0000000000..e9b21b802e --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -0,0 +1,512 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + */ + +#ifndef _R700_ASSEMBLER_H_ +#define _R700_ASSEMBLER_H_ + +#include "main/mtypes.h" +#include "shader/prog_instruction.h" + +#include "r700_chip.h" +#include "r700_shaderinst.h" +#include "r700_shader.h" + +typedef enum SHADER_PIPE_TYPE +{ + SPT_VP = 0, + SPT_FP = 1 +} SHADER_PIPE_TYPE; + +typedef enum ConstantCycles +{ + NUMBER_OF_CYCLES = 3, + NUMBER_OF_COMPONENTS = 4 +} ConstantCycles; + +typedef enum HARDWARE_LIMIT_VALUES +{ + TEMPORARY_REGISTER_OFFSET = SQ_ALU_SRC_GPR_BASE, + MAX_TEMPORARY_REGISTERS = SQ_ALU_SRC_GPR_SIZE, + MAX_CONSTANT_REGISTERS = SQ_ALU_SRC_CFILE_SIZE, + CFILE_REGISTER_OFFSET = SQ_ALU_SRC_CFILE_BASE, + NUMBER_OF_INPUT_COLORS = 2, + NUMBER_OF_OUTPUT_COLORS = 8, + NUMBER_OF_TEXTURE_UNITS = 16, + MEGA_FETCH_BYTES = 32 +} HARDWARE_LIMIT_VALUES; + +typedef enum AddressMode +{ + ADDR_ABSOLUTE = 0, + ADDR_RELATIVE_A0 = 1, + ADDR_RELATIVE_FLI_0 = 2, + NUMBER_OF_ADDR_MOD = 3 +} AddressMode; + +typedef enum SrcRegisterType +{ + SRC_REG_TEMPORARY = 0, + SRC_REG_INPUT = 1, + SRC_REG_CONSTANT = 2, + SRC_REG_ALT_TEMPORARY = 3, + NUMBER_OF_SRC_REG_TYPE = 4 +} SrcRegisterType; + +typedef enum DstRegisterType +{ + DST_REG_TEMPORARY = 0, + DST_REG_A0 = 1, + DST_REG_OUT = 2, + DST_REG_OUT_X_REPL = 3, + DST_REG_ALT_TEMPORARY = 4, + DST_REG_INPUT = 5, + NUMBER_OF_DST_REG_TYPE = 6 +} DstRegisterType; + +typedef unsigned int BITS; + +typedef struct PVSDSTtag +{ + BITS opcode:8; //(:6) //@@@ really should be 10 bits for OP2 + BITS math:1; + BITS predicated:1; //10 //8 + BITS pred_inv :1; //11 //8 + + BITS rtype:3; + BITS reg:10; //24 //20 + + BITS writex:1; + BITS writey:1; + BITS writez:1; + BITS writew:1; //28 + + BITS op3:1; // 29 Represents *_OP3_* ALU opcode + + BITS dualop:1; // 30 //26 + + BITS addrmode0:1; //31 //29 + BITS addrmode1:1; //32 +} PVSDST; + +typedef struct PVSSRCtag +{ + BITS rtype:4; + BITS addrmode0:1; + BITS reg:10; //15 (8) + BITS swizzlex:3; + BITS swizzley:3; + BITS swizzlez:3; + BITS swizzlew:3; //27 + + BITS negx:1; + BITS negy:1; + BITS negz:1; + BITS negw:1; //31 + //BITS addrsel:2; + BITS addrmode1:1; //32 +} PVSSRC; + +typedef struct PVSMATHtag +{ + BITS rtype:4; + BITS spare:1; + BITS reg:8; + BITS swizzlex:3; + BITS swizzley:3; + BITS dstoff:2; // 2 bits of dest offset into alt ram + BITS opcode:4; + BITS negx:1; + BITS negy:1; + BITS dstcomp:2; // select dest component + BITS spare2:3; +} PVSMATH; + +typedef union PVSDWORDtag +{ + BITS bits; + PVSDST dst; + PVSSRC src; + PVSMATH math; + float f; +} PVSDWORD; + +typedef struct VAP_OUT_VTX_FMT_0tag +{ + BITS pos:1; // 0 + BITS misc:1; + BITS clip_dist0:1; + BITS clip_dist1:1; + BITS pos_param:1; // 4 + + BITS color0:1; // 5 + BITS color1:1; + BITS color2:1; + BITS color3:1; + BITS color4:1; + BITS color5:1; + BITS color6:1; + BITS color7:1; + + BITS normal:1; + + BITS depth:1; // 14 + + BITS point_size:1; // 15 + BITS edge_flag:1; + BITS rta_index:1; // shares same channel as kill_flag + BITS kill_flag:1; + BITS viewport_index:1; // 19 + + BITS resvd1:12; // 20 +} VAP_OUT_VTX_FMT_0; + +typedef struct VAP_OUT_VTX_FMT_1tag +{ + BITS tex0comp:3; + BITS tex1comp:3; + BITS tex2comp:3; + BITS tex3comp:3; + BITS tex4comp:3; + BITS tex5comp:3; + BITS tex6comp:3; + BITS tex7comp:3; + + BITS resvd:8; +} VAP_OUT_VTX_FMT_1; + +typedef struct VAP_OUT_VTX_FMT_2tag +{ + BITS tex8comp :3; + BITS tex9comp :3; + BITS tex10comp:3; + BITS tex11comp:3; + BITS tex12comp:3; + BITS tex13comp:3; + BITS tex14comp:3; + BITS tex15comp:3; + + BITS resvd:8; +} VAP_OUT_VTX_FMT_2; + +typedef struct OUT_FRAGMENT_FMT_0tag +{ + BITS color0:1; + BITS color1:1; + BITS color2:1; + BITS color3:1; + BITS color4:1; + BITS color5:1; + BITS color6:1; + BITS color7:1; + + BITS depth:1; + BITS stencil_ref:1; + BITS coverage_to_mask:1; + BITS mask:1; + + BITS resvd1:20; +} OUT_FRAGMENT_FMT_0; + +typedef enum CF_CLAUSE_TYPE +{ + CF_EXPORT_CLAUSE, + CF_ALU_CLAUSE, + CF_TEX_CLAUSE, + CF_VTX_CLAUSE, + CF_OTHER_CLAUSE, + CF_EMPTY_CLAUSE, + NUMBER_CF_CLAUSE_TYPES +} CF_CLAUSE_TYPE; + +enum +{ + MAX_BOOL_CONSTANTS = 32, + MAX_INT_CONSTANTS = 32, + MAX_FLOAT_CONSTANTS = 256, + + FC_NONE = 0, + FC_IF = 1, + FC_LOOP = 2, + FC_REP = 3, + + COND_NONE = 0, + COND_BOOL = 1, + COND_PRED = 2, + COND_ALU = 3, + + SAFEDIST_TEX = 6, ///< safe distance for using result of texture lookup in alu or another tex lookup + SAFEDIST_ALU = 6 ///< the same for alu->fc +}; + +typedef struct FC_LEVEL +{ + unsigned int first; ///< first fc instruction on level (if, rep, loop) + unsigned int* mid; ///< middle instructions - else or all breaks on this level + unsigned int midLen; + unsigned int type; + unsigned int cond; + unsigned int inv; + unsigned int bpush; ///< 1 if first instruction does branch stack push + int id; ///< id of bool or int variable +} FC_LEVEL; + +typedef struct VTX_FETCH_METHOD +{ + GLboolean bEnableMini; + GLuint mega_fetch_remainder; +} VTX_FETCH_METHOD; + +typedef struct r700_AssemblerBase +{ + R700ControlFlowSXClause* cf_last_export_ptr; + R700ControlFlowSXClause* cf_current_export_clause_ptr; + R700ControlFlowALUClause* cf_current_alu_clause_ptr; + R700ControlFlowGenericClause* cf_current_tex_clause_ptr; + R700ControlFlowGenericClause* cf_current_vtx_clause_ptr; + R700ControlFlowGenericClause* cf_current_cf_clause_ptr; + + //Result shader + R700_Shader * pR700Shader; + + // No clause has been created yet + CF_CLAUSE_TYPE cf_current_clause_type; + + GLuint number_of_exports; + GLuint number_of_colorandz_exports; + GLuint number_of_export_opcodes; + + PVSDWORD D; + PVSDWORD S[3]; + + unsigned int uLastPosUpdate; + + OUT_FRAGMENT_FMT_0 fp_stOutFmt0; + + unsigned int uIIns; + unsigned int uOIns; + unsigned int number_used_registers; + unsigned int uUsedConsts; + + // Fragment programs + unsigned int uiFP_AttributeMap[FRAG_ATTRIB_MAX]; + unsigned int uiFP_OutputMap[FRAG_RESULT_MAX]; + unsigned int uBoolConsts; + unsigned int uIntConsts; + unsigned int uInsts; + unsigned int uConsts; + + // Vertex programs + unsigned char ucVP_AttributeMap[VERT_ATTRIB_MAX]; + unsigned char ucVP_OutputMap[VERT_RESULT_MAX]; + + unsigned char * pucOutMask; + + //----------------------------------------------------------------------------------- + // flow control members + //----------------------------------------------------------------------------------- + unsigned int FCSP; + FC_LEVEL fc_stack[32]; + + unsigned int branch_depth; + unsigned int max_branch_depth; + + //----------------------------------------------------------------------------------- + // ArgSubst used in Assemble_Source() function + //----------------------------------------------------------------------------------- + int aArgSubst[4]; + + GLint hw_gpr[ NUMBER_OF_CYCLES ][ NUMBER_OF_COMPONENTS ]; + GLint hw_cfile_addr[ NUMBER_OF_COMPONENTS ]; + GLint hw_cfile_chan[ NUMBER_OF_COMPONENTS ]; + + GLuint uOutputs; + + GLint color_export_register_number[NUMBER_OF_OUTPUT_COLORS]; + GLint depth_export_register_number; + + GLint stencil_export_register_number; + GLint coverage_to_mask_export_register_number; + GLint mask_export_register_number; + + GLuint starting_export_register_number; + GLuint starting_vfetch_register_number; + GLuint starting_temp_register_number; + GLuint uHelpReg; + GLuint uFirstHelpReg; + + GLboolean input_position_is_used; + GLboolean input_normal_is_used; + + GLboolean input_color_is_used[NUMBER_OF_INPUT_COLORS]; + + GLboolean input_texture_unit_is_used[NUMBER_OF_TEXTURE_UNITS]; + + R700VertexGenericFetch* vfetch_instruction_ptr_array[VERT_ATTRIB_MAX]; + + GLuint number_of_inputs; + + InstDeps *pInstDeps; + + SHADER_PIPE_TYPE currentShaderType; + struct prog_instruction * pILInst; + GLuint uiCurInst; + GLboolean bR6xx; +} r700_AssemblerBase; + +//Internal use +BITS addrmode_PVSDST(PVSDST * pPVSDST); +void setaddrmode_PVSDST(PVSDST * pPVSDST, BITS addrmode); +void nomask_PVSDST(PVSDST * pPVSDST); +BITS addrmode_PVSSRC(PVSSRC* pPVSSRC); +void setaddrmode_PVSSRC(PVSSRC* pPVSSRC, BITS addrmode); +void setswizzle_PVSSRC(PVSSRC* pPVSSRC, BITS swz); +void noswizzle_PVSSRC(PVSSRC* pPVSSRC); +void swizzleagain_PVSSRC(PVSSRC * pPVSSRC, BITS x, BITS y, BITS z, BITS w); +void neg_PVSSRC(PVSSRC* pPVSSRC); +void noneg_PVSSRC(PVSSRC* pPVSSRC); +void flipneg_PVSSRC(PVSSRC* pPVSSRC); +void zerocomp_PVSSRC(PVSSRC* pPVSSRC, int c); +void onecomp_PVSSRC(PVSSRC* pPVSSRC, int c); +BITS is_misc_component_exported(VAP_OUT_VTX_FMT_0* pOutVTXFmt0); +BITS is_depth_component_exported(OUT_FRAGMENT_FMT_0* pFPOutFmt) ; +GLboolean is_reduction_opcode(PVSDWORD * dest); +GLuint GetSurfaceFormat(GLenum eType, GLuint nChannels, GLuint * pClient_size); + +unsigned int r700GetNumOperands(r700_AssemblerBase* pAsm); + +GLboolean IsTex(gl_inst_opcode Opcode); +GLboolean IsAlu(gl_inst_opcode Opcode); +int check_current_clause(r700_AssemblerBase* pAsm, + CF_CLAUSE_TYPE new_clause_type); +GLboolean add_vfetch_instruction(r700_AssemblerBase* pAsm, + R700VertexInstruction* vertex_instruction_ptr); +GLboolean add_tex_instruction(r700_AssemblerBase* pAsm, + R700TextureInstruction* tex_instruction_ptr); +GLboolean assemble_vfetch_instruction(r700_AssemblerBase* pAsm, + GLuint gl_client_id, + GLuint destination_register, + GLuint number_of_elements, + GLenum dataElementType, + VTX_FETCH_METHOD* pFetchMethod); +GLuint gethelpr(r700_AssemblerBase* pAsm); +void resethelpr(r700_AssemblerBase* pAsm); +void checkop_init(r700_AssemblerBase* pAsm); +GLboolean mov_temp(r700_AssemblerBase* pAsm, int src); +GLboolean checkop1(r700_AssemblerBase* pAsm); +GLboolean checkop2(r700_AssemblerBase* pAsm); +GLboolean checkop3(r700_AssemblerBase* pAsm); +GLboolean assemble_src(r700_AssemblerBase *pAsm, + int src, + int fld); +GLboolean assemble_dst(r700_AssemblerBase *pAsm); +GLboolean tex_dst(r700_AssemblerBase *pAsm); +GLboolean tex_src(r700_AssemblerBase *pAsm); +GLboolean assemble_tex_instruction(r700_AssemblerBase *pAsm); +void initialize(r700_AssemblerBase *pAsm); +GLboolean assemble_alu_src(R700ALUInstruction* alu_instruction_ptr, + int source_index, + PVSSRC* pSource, + BITS scalar_channel_index); +GLboolean add_alu_instruction(r700_AssemblerBase* pAsm, + R700ALUInstruction* alu_instruction_ptr, + GLuint contiguous_slots_needed); +void get_src_properties(R700ALUInstruction* alu_instruction_ptr, + int source_index, + BITS* psrc_sel, + BITS* psrc_rel, + BITS* psrc_chan, + BITS* psrc_neg); +int is_cfile(BITS sel); +int is_const(BITS sel); +int is_gpr(BITS sel); +GLboolean reserve_cfile(r700_AssemblerBase* pAsm, + GLuint sel, + GLuint chan); +GLboolean reserve_gpr(r700_AssemblerBase* pAsm, GLuint sel, GLuint chan, GLuint cycle); +GLboolean cycle_for_scalar_bank_swizzle(const int swiz, const int sel, GLuint* pCycle); +GLboolean cycle_for_vector_bank_swizzle(const int swiz, const int sel, GLuint* pCycle); +GLboolean check_scalar(r700_AssemblerBase* pAsm, + R700ALUInstruction* alu_instruction_ptr); +GLboolean check_vector(r700_AssemblerBase* pAsm, + R700ALUInstruction* alu_instruction_ptr); +GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm); +GLboolean next_ins(r700_AssemblerBase *pAsm); +GLboolean assemble_math_function(r700_AssemblerBase* pAsm, BITS opcode); +GLboolean assemble_ABS(r700_AssemblerBase *pAsm); +GLboolean assemble_ADD(r700_AssemblerBase *pAsm); +GLboolean assemble_BAD(char *opcode_str); +GLboolean assemble_CMP(r700_AssemblerBase *pAsm); +GLboolean assemble_COS(r700_AssemblerBase *pAsm); +GLboolean assemble_DOT(r700_AssemblerBase *pAsm); +GLboolean assemble_DST(r700_AssemblerBase *pAsm); +GLboolean assemble_EX2(r700_AssemblerBase *pAsm); +GLboolean assemble_FLR(r700_AssemblerBase *pAsm); +GLboolean assemble_FLR_INT(r700_AssemblerBase *pAsm); +GLboolean assemble_FRC(r700_AssemblerBase *pAsm); +GLboolean assemble_KIL(r700_AssemblerBase *pAsm); +GLboolean assemble_LG2(r700_AssemblerBase *pAsm); +GLboolean assemble_LRP(r700_AssemblerBase *pAsm); +GLboolean assemble_MAD(r700_AssemblerBase *pAsm); +GLboolean assemble_LIT(r700_AssemblerBase *pAsm); +GLboolean assemble_MAX(r700_AssemblerBase *pAsm); +GLboolean assemble_MIN(r700_AssemblerBase *pAsm); +GLboolean assemble_MOV(r700_AssemblerBase *pAsm); +GLboolean assemble_MUL(r700_AssemblerBase *pAsm); +GLboolean assemble_POW(r700_AssemblerBase *pAsm); +GLboolean assemble_RCP(r700_AssemblerBase *pAsm); +GLboolean assemble_RSQ(r700_AssemblerBase *pAsm); +GLboolean assemble_SIN(r700_AssemblerBase *pAsm); +GLboolean assemble_SCS(r700_AssemblerBase *pAsm); +GLboolean assemble_SGE(r700_AssemblerBase *pAsm); +GLboolean assemble_SLT(r700_AssemblerBase *pAsm); +GLboolean assemble_STP(r700_AssemblerBase *pAsm); +GLboolean assemble_TEX(r700_AssemblerBase *pAsm); +GLboolean assemble_XPD(r700_AssemblerBase *pAsm); +GLboolean assemble_EXPORT(r700_AssemblerBase *pAsm); +GLboolean assemble_IF(r700_AssemblerBase *pAsm); +GLboolean assemble_ENDIF(r700_AssemblerBase *pAsm); + +GLboolean Process_Export(r700_AssemblerBase* pAsm, + GLuint type, + GLuint export_starting_index, + GLuint export_count, + GLuint starting_register_number, + GLboolean is_depth_export); +GLboolean Move_Depth_Exports_To_Correct_Channels(r700_AssemblerBase *pAsm, + BITS depth_channel_select); + + +//Interface +GLboolean AssembleInstr(GLuint uiNumberInsts, + struct prog_instruction *pILInst, + r700_AssemblerBase *pR700AsmCode); +GLboolean Process_Fragment_Exports(r700_AssemblerBase *pR700AsmCode, GLbitfield OutputsWritten); +GLboolean Process_Vertex_Exports(r700_AssemblerBase *pR700AsmCode, GLbitfield OutputsWritten); + +int Init_r700_AssemblerBase(SHADER_PIPE_TYPE spt, r700_AssemblerBase* pAsm, R700_Shader* pShader); +GLboolean Clean_Up_Assembler(r700_AssemblerBase *pR700AsmCode); + +#endif //_R700_ASSEMBLER_H_ diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c new file mode 100644 index 0000000000..d0371cdda0 --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -0,0 +1,420 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + * CooperYuan , + */ + +#include "main/imports.h" +#include "main/glheader.h" + +#include "r600_context.h" + +#include "r700_chip.h" +#include "r700_state.h" +#include "r700_tex.h" +#include "r700_oglprog.h" +#include "r700_ioctl.h" +/* to be enable +#include "r700_emit.h" +*/ + +extern const struct tnl_pipeline_stage *r700_pipeline[]; + +static GLboolean r700DestroyChipObj(void* pvChipObj) +{ + R700_CHIP_CONTEXT *r700; + + if(NULL == pvChipObj) + { + return GL_TRUE; + } + + r700 = (R700_CHIP_CONTEXT *)pvChipObj; + + FREE(r700->pStateList); + + FREE(r700); + + return GL_TRUE; +} + +static void r700InitFuncs(struct dd_function_table *functions) +{ + r700InitStateFuncs(functions); + r700InitTextureFuncs(functions); + r700InitShaderFuncs(functions); + r700InitIoctlFuncs(functions); +} + +#define LINK_STATES(reg) \ +do \ +{ \ + pStateListWork->puiValue = (unsigned int*)&(r700->reg); \ + pStateListWork->unOffset = mm##reg - ASIC_CONTEXT_BASE_INDEX; \ + pStateListWork->pNext = pStateListWork + 1; \ + pStateListWork++; \ +}while(0) + +GLboolean r700InitChipObject(context_t *context) +{ + ContextState * pStateListWork; + + R700_CHIP_CONTEXT *r700 = CALLOC( sizeof(R700_CHIP_CONTEXT) ); + + context->chipobj.pvChipObj = (void*)r700; + + context->chipobj.DestroyChipObj = r700DestroyChipObj; + + context->chipobj.GetTexObjSize = r700GetTexObjSize; + + context->chipobj.stages = r700_pipeline; + + context->chipobj.InitFuncs = r700InitFuncs; + + context->chipobj.InitState = r700InitState; + + /* init state list */ + r700->pStateList = (ContextState*) MALLOC (sizeof(ContextState)*sizeof(R700_CHIP_CONTEXT)/sizeof(unsigned int)); + pStateListWork = r700->pStateList; + + LINK_STATES(DB_DEPTH_SIZE); + LINK_STATES(DB_DEPTH_VIEW); + + LINK_STATES(DB_DEPTH_BASE); + LINK_STATES(DB_DEPTH_INFO); + LINK_STATES(DB_HTILE_DATA_BASE); + + LINK_STATES(DB_STENCIL_CLEAR); + LINK_STATES(DB_DEPTH_CLEAR); + + LINK_STATES(PA_SC_SCREEN_SCISSOR_TL); + LINK_STATES(PA_SC_SCREEN_SCISSOR_BR); + + LINK_STATES(CB_COLOR0_BASE); + + LINK_STATES(CB_COLOR0_SIZE); + + LINK_STATES(CB_COLOR0_VIEW); + + LINK_STATES(CB_COLOR0_INFO); + LINK_STATES(CB_COLOR1_INFO); + LINK_STATES(CB_COLOR2_INFO); + LINK_STATES(CB_COLOR3_INFO); + LINK_STATES(CB_COLOR4_INFO); + LINK_STATES(CB_COLOR5_INFO); + LINK_STATES(CB_COLOR6_INFO); + LINK_STATES(CB_COLOR7_INFO); + + LINK_STATES(CB_COLOR0_TILE); + + LINK_STATES(CB_COLOR0_FRAG); + + LINK_STATES(CB_COLOR0_MASK); + + LINK_STATES(PA_SC_WINDOW_OFFSET); + LINK_STATES(PA_SC_WINDOW_SCISSOR_TL); + LINK_STATES(PA_SC_WINDOW_SCISSOR_BR); + LINK_STATES(PA_SC_CLIPRECT_RULE); + LINK_STATES(PA_SC_CLIPRECT_0_TL); + LINK_STATES(PA_SC_CLIPRECT_0_BR); + LINK_STATES(PA_SC_CLIPRECT_1_TL); + LINK_STATES(PA_SC_CLIPRECT_1_BR); + LINK_STATES(PA_SC_CLIPRECT_2_TL); + LINK_STATES(PA_SC_CLIPRECT_2_BR); + LINK_STATES(PA_SC_CLIPRECT_3_TL); + LINK_STATES(PA_SC_CLIPRECT_3_BR); + + LINK_STATES(PA_SC_EDGERULE); + + LINK_STATES(CB_TARGET_MASK); + LINK_STATES(CB_SHADER_MASK); + LINK_STATES(PA_SC_GENERIC_SCISSOR_TL); + LINK_STATES(PA_SC_GENERIC_SCISSOR_BR); + + LINK_STATES(PA_SC_VPORT_SCISSOR_0_TL); + LINK_STATES(PA_SC_VPORT_SCISSOR_0_BR); + LINK_STATES(PA_SC_VPORT_SCISSOR_1_TL); + LINK_STATES(PA_SC_VPORT_SCISSOR_1_BR); + + LINK_STATES(PA_SC_VPORT_ZMIN_0); + LINK_STATES(PA_SC_VPORT_ZMAX_0); + + LINK_STATES(SX_MISC); + + LINK_STATES(SQ_VTX_SEMANTIC_0); + LINK_STATES(SQ_VTX_SEMANTIC_1); + LINK_STATES(SQ_VTX_SEMANTIC_2); + LINK_STATES(SQ_VTX_SEMANTIC_3); + LINK_STATES(SQ_VTX_SEMANTIC_4); + LINK_STATES(SQ_VTX_SEMANTIC_5); + LINK_STATES(SQ_VTX_SEMANTIC_6); + LINK_STATES(SQ_VTX_SEMANTIC_7); + LINK_STATES(SQ_VTX_SEMANTIC_8); + LINK_STATES(SQ_VTX_SEMANTIC_9); + LINK_STATES(SQ_VTX_SEMANTIC_10); + LINK_STATES(SQ_VTX_SEMANTIC_11); + LINK_STATES(SQ_VTX_SEMANTIC_12); + LINK_STATES(SQ_VTX_SEMANTIC_13); + LINK_STATES(SQ_VTX_SEMANTIC_14); + LINK_STATES(SQ_VTX_SEMANTIC_15); + LINK_STATES(SQ_VTX_SEMANTIC_16); + LINK_STATES(SQ_VTX_SEMANTIC_17); + LINK_STATES(SQ_VTX_SEMANTIC_18); + LINK_STATES(SQ_VTX_SEMANTIC_19); + LINK_STATES(SQ_VTX_SEMANTIC_20); + LINK_STATES(SQ_VTX_SEMANTIC_21); + LINK_STATES(SQ_VTX_SEMANTIC_22); + LINK_STATES(SQ_VTX_SEMANTIC_23); + LINK_STATES(SQ_VTX_SEMANTIC_24); + LINK_STATES(SQ_VTX_SEMANTIC_25); + LINK_STATES(SQ_VTX_SEMANTIC_26); + LINK_STATES(SQ_VTX_SEMANTIC_27); + LINK_STATES(SQ_VTX_SEMANTIC_28); + LINK_STATES(SQ_VTX_SEMANTIC_29); + LINK_STATES(SQ_VTX_SEMANTIC_30); + LINK_STATES(SQ_VTX_SEMANTIC_31); + + LINK_STATES(VGT_MAX_VTX_INDX); + LINK_STATES(VGT_MIN_VTX_INDX); + LINK_STATES(VGT_INDX_OFFSET); + LINK_STATES(VGT_MULTI_PRIM_IB_RESET_INDX); + LINK_STATES(SX_ALPHA_TEST_CONTROL); + + LINK_STATES(CB_BLEND_RED); + LINK_STATES(CB_BLEND_GREEN); + LINK_STATES(CB_BLEND_BLUE); + LINK_STATES(CB_BLEND_ALPHA); + + LINK_STATES(PA_CL_VPORT_XSCALE); + LINK_STATES(PA_CL_VPORT_XOFFSET); + LINK_STATES(PA_CL_VPORT_YSCALE); + LINK_STATES(PA_CL_VPORT_YOFFSET); + LINK_STATES(PA_CL_VPORT_ZSCALE); + LINK_STATES(PA_CL_VPORT_ZOFFSET); + + LINK_STATES(SPI_VS_OUT_ID_0); + LINK_STATES(SPI_VS_OUT_ID_1); + LINK_STATES(SPI_VS_OUT_ID_2); + LINK_STATES(SPI_VS_OUT_ID_3); + LINK_STATES(SPI_VS_OUT_ID_4); + LINK_STATES(SPI_VS_OUT_ID_5); + LINK_STATES(SPI_VS_OUT_ID_6); + LINK_STATES(SPI_VS_OUT_ID_7); + LINK_STATES(SPI_VS_OUT_ID_8); + LINK_STATES(SPI_VS_OUT_ID_9); + + LINK_STATES(SPI_PS_INPUT_CNTL_0); + LINK_STATES(SPI_PS_INPUT_CNTL_1); + LINK_STATES(SPI_PS_INPUT_CNTL_2); + LINK_STATES(SPI_PS_INPUT_CNTL_3); + LINK_STATES(SPI_PS_INPUT_CNTL_4); + LINK_STATES(SPI_PS_INPUT_CNTL_5); + LINK_STATES(SPI_PS_INPUT_CNTL_6); + LINK_STATES(SPI_PS_INPUT_CNTL_7); + LINK_STATES(SPI_PS_INPUT_CNTL_8); + LINK_STATES(SPI_PS_INPUT_CNTL_9); + LINK_STATES(SPI_PS_INPUT_CNTL_10); + LINK_STATES(SPI_PS_INPUT_CNTL_11); + LINK_STATES(SPI_PS_INPUT_CNTL_12); + LINK_STATES(SPI_PS_INPUT_CNTL_13); + LINK_STATES(SPI_PS_INPUT_CNTL_14); + LINK_STATES(SPI_PS_INPUT_CNTL_15); + LINK_STATES(SPI_PS_INPUT_CNTL_16); + LINK_STATES(SPI_PS_INPUT_CNTL_17); + LINK_STATES(SPI_PS_INPUT_CNTL_18); + LINK_STATES(SPI_PS_INPUT_CNTL_19); + LINK_STATES(SPI_PS_INPUT_CNTL_20); + LINK_STATES(SPI_PS_INPUT_CNTL_21); + LINK_STATES(SPI_PS_INPUT_CNTL_22); + LINK_STATES(SPI_PS_INPUT_CNTL_23); + LINK_STATES(SPI_PS_INPUT_CNTL_24); + LINK_STATES(SPI_PS_INPUT_CNTL_25); + LINK_STATES(SPI_PS_INPUT_CNTL_26); + LINK_STATES(SPI_PS_INPUT_CNTL_27); + LINK_STATES(SPI_PS_INPUT_CNTL_28); + LINK_STATES(SPI_PS_INPUT_CNTL_29); + LINK_STATES(SPI_PS_INPUT_CNTL_30); + LINK_STATES(SPI_PS_INPUT_CNTL_31); + LINK_STATES(SPI_VS_OUT_CONFIG); + LINK_STATES(SPI_THREAD_GROUPING); + LINK_STATES(SPI_PS_IN_CONTROL_0); + LINK_STATES(SPI_PS_IN_CONTROL_1); + + LINK_STATES(SPI_INPUT_Z); + LINK_STATES(SPI_FOG_CNTL); + + LINK_STATES(CB_BLEND0_CONTROL); + + LINK_STATES(CB_SHADER_CONTROL); + + /*LINK_STATES(VGT_DRAW_INITIATOR); */ + + LINK_STATES(DB_DEPTH_CONTROL); + + LINK_STATES(CB_COLOR_CONTROL); + LINK_STATES(DB_SHADER_CONTROL); + LINK_STATES(PA_CL_CLIP_CNTL); + LINK_STATES(PA_SU_SC_MODE_CNTL); + LINK_STATES(PA_CL_VTE_CNTL); + LINK_STATES(PA_CL_VS_OUT_CNTL); + LINK_STATES(PA_CL_NANINF_CNTL); + + LINK_STATES(SQ_PGM_START_PS); + LINK_STATES(SQ_PGM_RESOURCES_PS); + LINK_STATES(SQ_PGM_EXPORTS_PS); + LINK_STATES(SQ_PGM_START_VS); + LINK_STATES(SQ_PGM_RESOURCES_VS); + LINK_STATES(SQ_PGM_START_GS); + LINK_STATES(SQ_PGM_RESOURCES_GS); + LINK_STATES(SQ_PGM_START_ES); + LINK_STATES(SQ_PGM_RESOURCES_ES); + LINK_STATES(SQ_PGM_START_FS); + LINK_STATES(SQ_PGM_RESOURCES_FS); + LINK_STATES(SQ_ESGS_RING_ITEMSIZE); + LINK_STATES(SQ_GSVS_RING_ITEMSIZE); + LINK_STATES(SQ_ESTMP_RING_ITEMSIZE); + LINK_STATES(SQ_GSTMP_RING_ITEMSIZE); + LINK_STATES(SQ_VSTMP_RING_ITEMSIZE); + LINK_STATES(SQ_PSTMP_RING_ITEMSIZE); + LINK_STATES(SQ_FBUF_RING_ITEMSIZE); + LINK_STATES(SQ_REDUC_RING_ITEMSIZE); + LINK_STATES(SQ_GS_VERT_ITEMSIZE); + LINK_STATES(SQ_PGM_CF_OFFSET_PS); + LINK_STATES(SQ_PGM_CF_OFFSET_VS); + LINK_STATES(SQ_PGM_CF_OFFSET_GS); + LINK_STATES(SQ_PGM_CF_OFFSET_ES); + LINK_STATES(SQ_PGM_CF_OFFSET_FS); + + LINK_STATES(PA_SU_POINT_SIZE); + LINK_STATES(PA_SU_POINT_MINMAX); + LINK_STATES(PA_SU_LINE_CNTL); + LINK_STATES(PA_SC_LINE_STIPPLE); + LINK_STATES(VGT_OUTPUT_PATH_CNTL); + + LINK_STATES(VGT_GS_MODE); + + LINK_STATES(PA_SC_MPASS_PS_CNTL); + LINK_STATES(PA_SC_MODE_CNTL); + + LINK_STATES(VGT_PRIMITIVEID_EN); + LINK_STATES(VGT_DMA_NUM_INSTANCES); + + LINK_STATES(VGT_MULTI_PRIM_IB_RESET_EN); + + LINK_STATES(VGT_INSTANCE_STEP_RATE_0); + LINK_STATES(VGT_INSTANCE_STEP_RATE_1); + + LINK_STATES(VGT_STRMOUT_EN); + LINK_STATES(VGT_REUSE_OFF); + + LINK_STATES(PA_SC_LINE_CNTL); + LINK_STATES(PA_SC_AA_CONFIG); + LINK_STATES(PA_SU_VTX_CNTL); + LINK_STATES(PA_CL_GB_VERT_CLIP_ADJ); + LINK_STATES(PA_CL_GB_VERT_DISC_ADJ); + LINK_STATES(PA_CL_GB_HORZ_CLIP_ADJ); + LINK_STATES(PA_CL_GB_HORZ_DISC_ADJ); + LINK_STATES(PA_SC_AA_SAMPLE_LOCS_MCTX); + LINK_STATES(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX); + + LINK_STATES(CB_CLRCMP_CONTROL); + LINK_STATES(CB_CLRCMP_SRC); + LINK_STATES(CB_CLRCMP_DST); + LINK_STATES(CB_CLRCMP_MSK); + + LINK_STATES(PA_SC_AA_MASK); + + LINK_STATES(VGT_VERTEX_REUSE_BLOCK_CNTL); + LINK_STATES(VGT_OUT_DEALLOC_CNTL); + + LINK_STATES(DB_RENDER_CONTROL); + LINK_STATES(DB_RENDER_OVERRIDE); + + LINK_STATES(DB_HTILE_SURFACE); + + LINK_STATES(DB_ALPHA_TO_MASK); + + LINK_STATES(PA_SU_POLY_OFFSET_DB_FMT_CNTL); + LINK_STATES(PA_SU_POLY_OFFSET_CLAMP); + LINK_STATES(PA_SU_POLY_OFFSET_FRONT_SCALE); + LINK_STATES(PA_SU_POLY_OFFSET_FRONT_OFFSET); + LINK_STATES(PA_SU_POLY_OFFSET_BACK_SCALE); + + pStateListWork->puiValue = (unsigned int*)&(r700->PA_SU_POLY_OFFSET_BACK_OFFSET); + pStateListWork->unOffset = mmPA_SU_POLY_OFFSET_BACK_OFFSET - ASIC_CONTEXT_BASE_INDEX; + pStateListWork->pNext = NULL; /* END OF STATE LIST */ + + /* TODO : may need order sorting in case someone break the order of states in R700_CHIP_CONTEXT. */ + + return GL_TRUE; +} + +GLboolean r700SendContextStates(context_t *context) +{ +#if 0 //to be enable + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + + ContextState * pState = r700->pStateList; + ContextState * pInit; + unsigned int toSend; + unsigned int ui; + + while(NULL != pState) + { + toSend = 1; + + pInit = pState; + + while(NULL != pState->pNext) + { + if( (pState->pNext->unOffset - pState->unOffset) > 1 ) + { + break; + } + else + { + pState = pState->pNext; + toSend++; + } + }; + + pState = pState->pNext; + + R700_CMDBUF_CHECK_SPACE(toSend + 2); + R700EP3(context, IT_SET_CONTEXT_REG, toSend); + R700E32(context, pInit->unOffset); + + for(ui=0; uipuiValue)); + pInit = pInit->pNext; + }; + }; +#endif //to be enable + return GL_TRUE; +} + + + + diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h new file mode 100644 index 0000000000..f08190027c --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_chip.h @@ -0,0 +1,458 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + */ + +#ifndef _R700_CHIP_H_ +#define _R700_CHIP_H_ + +#include "r600_context.h" + +#include "r600_reg.h" +#include "r600_reg_auto_r6xx.h" +#include "r600_reg_r6xx.h" +#include "r600_reg_r7xx.h" + +#include "r700_chipoffset.h" + +#define SETfield(x, val, shift, mask) ( (x) = ((x) & ~(mask)) | ((val) << (shift)) ) /* u32All */ +#define CLEARfield(x, mask) ( (x) &= ~(mask) ) +#define SETbit(x, bit) ( (x) |= (bit) ) +#define CLEARbit(x, bit) ( (x) &= ~(bit) ) + +#define R700_TEXTURE_NUMBERUNITS 16 + +/* Enum not show in r600_*.h */ + +#define FETCH_RESOURCE_STRIDE 7 + +#define ASIC_CONFIG_BASE_INDEX 0x2000 +#define ASIC_CONTEXT_BASE_INDEX 0xA000 +#define ASIC_CTL_CONST_BASE_INDEX 0xF3FC + +enum +{ + SQ_ABSOLUTE = 0x00000000, + SQ_RELATIVE = 0x00000001, +}; + +enum +{ + SQ_ALU_SCL_210 = 0x00000000, + SQ_ALU_SCL_122 = 0x00000001, + SQ_ALU_SCL_212 = 0x00000002, + SQ_ALU_SCL_221 = 0x00000003, +}; + +enum +{ + SQ_TEX_UNNORMALIZED = 0x00000000, + SQ_TEX_NORMALIZED = 0x00000001, +}; + +enum +{ + SQ_CF_PIXEL_MRT0 = 0x00000000, + SQ_CF_PIXEL_MRT1 = 0x00000001, + SQ_CF_PIXEL_MRT2 = 0x00000002, + SQ_CF_PIXEL_MRT3 = 0x00000003, + SQ_CF_PIXEL_MRT4 = 0x00000004, + SQ_CF_PIXEL_MRT5 = 0x00000005, + SQ_CF_PIXEL_MRT6 = 0x00000006, + SQ_CF_PIXEL_MRT7 = 0x00000007, + SQ_CF_PIXEL_Z = 0x0000003d, +}; + +typedef enum ENUM_SQ_CF_ARRAY_BASE_POS { +SQ_CF_POS_0 = 0x0000003c, +SQ_CF_POS_1 = 0x0000003d, +SQ_CF_POS_2 = 0x0000003e, +SQ_CF_POS_3 = 0x0000003f, +} ENUM_SQ_CF_ARRAY_BASE_POS; + +enum +{ + PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit = 23, +}; + +enum +{ + TEX_XYFilter_Point = 0x00000000, + TEX_XYFilter_Linear = 0x00000001, + TEX_XYFilter_Cubic = 0x00000002, + TEX_XYFilter_Cleartype = 0x00000003, + + TEX_MipFilter_None = 0x00000000, + TEX_MipFilter_Point = 0x00000001, + TEX_MipFilter_Linear = 0x00000002, +}; + +enum +{ + SQ_EXPORT_WRITE = 0x00000000, + SQ_EXPORT_WRITE_IND = 0x00000001, + SQ_EXPORT_WRITE_ACK = 0x00000002, + SQ_EXPORT_WRITE_IND_ACK = 0x00000003, +}; + +/* --------------------------------- */ + +enum +{ + R700_PM4_PACKET0_NOP = 0x00000000, + R700_PM4_PACKET1_NOP = 0x40000000, + R700_PM4_PACKET2_NOP = 0x80000000, + R700_PM4_PACKET3_NOP = 0xC0000000, +}; + +#define PM4_OPCODE_SET_INDEX_TYPE (R700_PM4_PACKET3_NOP | (IT_INDEX_TYPE << 8)) + +#define PM4_OPCODE_DRAW_INDEX_AUTO (R700_PM4_PACKET3_NOP | (IT_DRAW_INDEX_AUTO << 8)) +#define PM4_OPCODE_DRAW_INDEX_IMMD (R700_PM4_PACKET3_NOP | (IT_DRAW_INDEX_IMMD << 8)) +#define PM4_OPCODE_WAIT_REG_MEM (R700_PM4_PACKET3_NOP | (IT_WAIT_REG_MEM << 8)) +#define PM4_OPCODE_SET_CONTEXT_REG (R700_PM4_PACKET3_NOP | (IT_SET_CONTEXT_REG << 8)) +#define PM4_OPCODE_SET_CONFIG_REG (R700_PM4_PACKET3_NOP | (IT_SET_CONFIG_REG << 8)) +#define PM4_OPCODE_SET_ALU_CONST (R700_PM4_PACKET3_NOP | (IT_SET_ALU_CONST << 8)) +#define PM4_OPCODE_SET_RESOURCE (R700_PM4_PACKET3_NOP | (IT_SET_RESOURCE << 8)) +#define PM4_OPCODE_SET_SAMPLER (R700_PM4_PACKET3_NOP | (IT_SET_SAMPLER << 8)) +#define PM4_OPCODE_CONTEXT_CONTROL (R700_PM4_PACKET3_NOP | (IT_CONTEXT_CONTROL << 8)) + +union UINT_FLOAT +{ + unsigned int u32All; + float f32All; +}; + +typedef struct _TEXTURE_STATE_STRUCT +{ + union UINT_FLOAT SQ_TEX_RESOURCE0; + union UINT_FLOAT SQ_TEX_RESOURCE1; + union UINT_FLOAT SQ_TEX_RESOURCE2; + union UINT_FLOAT SQ_TEX_RESOURCE3; + union UINT_FLOAT SQ_TEX_RESOURCE4; + union UINT_FLOAT SQ_TEX_RESOURCE5; + union UINT_FLOAT SQ_TEX_RESOURCE6; + GLboolean enabled; +} TEXTURE_STATE_STRUCT; + +typedef struct _SAMPLER_STATE_STRUCT +{ + union UINT_FLOAT SQ_TEX_SAMPLER0; + union UINT_FLOAT SQ_TEX_SAMPLER1; + union UINT_FLOAT SQ_TEX_SAMPLER2; + GLboolean enabled; +} SAMPLER_STATE_STRUCT; + +typedef struct _R700_TEXTURE_STATES +{ + TEXTURE_STATE_STRUCT *textures[R700_TEXTURE_NUMBERUNITS]; + SAMPLER_STATE_STRUCT *samplers[R700_TEXTURE_NUMBERUNITS]; +} R700_TEXTURE_STATES; + +typedef struct ContextState +{ + unsigned int * puiValue; + unsigned int unOffset; + struct ContextState * pNext; +} ContextState; + +typedef struct _R700_CHIP_CONTEXT +{ + union UINT_FLOAT DB_DEPTH_SIZE ; /* 0xA000 */ + union UINT_FLOAT DB_DEPTH_VIEW ; /* 0xA001 */ + + union UINT_FLOAT DB_DEPTH_BASE ; /* 0xA003 */ + union UINT_FLOAT DB_DEPTH_INFO ; /* 0xA004 */ + union UINT_FLOAT DB_HTILE_DATA_BASE ; /* 0xA005 */ + + union UINT_FLOAT DB_STENCIL_CLEAR ; /* 0xA00A */ + union UINT_FLOAT DB_DEPTH_CLEAR ; /* 0xA00B */ + + union UINT_FLOAT PA_SC_SCREEN_SCISSOR_TL ; /* 0xA00C */ + union UINT_FLOAT PA_SC_SCREEN_SCISSOR_BR ; /* 0xA00D */ + + union UINT_FLOAT CB_COLOR0_BASE ; /* 0xA010 */ + + union UINT_FLOAT CB_COLOR0_SIZE ; /* 0xA018 */ + + union UINT_FLOAT CB_COLOR0_VIEW ; /* 0xA020 */ + + union UINT_FLOAT CB_COLOR0_INFO ; /* 0xA028 */ + union UINT_FLOAT CB_COLOR1_INFO ; /* 0xA029 */ + union UINT_FLOAT CB_COLOR2_INFO ; /* 0xA02A */ + union UINT_FLOAT CB_COLOR3_INFO ; /* 0xA02B */ + union UINT_FLOAT CB_COLOR4_INFO ; /* 0xA02C */ + union UINT_FLOAT CB_COLOR5_INFO ; /* 0xA02D */ + union UINT_FLOAT CB_COLOR6_INFO ; /* 0xA02E */ + union UINT_FLOAT CB_COLOR7_INFO ; /* 0xA02F */ + + union UINT_FLOAT CB_COLOR0_TILE ; /* 0xA030 */ + + union UINT_FLOAT CB_COLOR0_FRAG ; /* 0xA038 */ + + union UINT_FLOAT CB_COLOR0_MASK ; /* 0xA040 */ + + union UINT_FLOAT PA_SC_WINDOW_OFFSET ; /* 0xA080 */ + union UINT_FLOAT PA_SC_WINDOW_SCISSOR_TL ; /* 0xA081 */ + union UINT_FLOAT PA_SC_WINDOW_SCISSOR_BR ; /* 0xA082 */ + union UINT_FLOAT PA_SC_CLIPRECT_RULE ; /* 0xA083 */ + union UINT_FLOAT PA_SC_CLIPRECT_0_TL ; /* 0xA084 */ + union UINT_FLOAT PA_SC_CLIPRECT_0_BR ; /* 0xA085 */ + union UINT_FLOAT PA_SC_CLIPRECT_1_TL ; /* 0xA086 */ + union UINT_FLOAT PA_SC_CLIPRECT_1_BR ; /* 0xA087 */ + union UINT_FLOAT PA_SC_CLIPRECT_2_TL ; /* 0xA088 */ + union UINT_FLOAT PA_SC_CLIPRECT_2_BR ; /* 0xA089 */ + union UINT_FLOAT PA_SC_CLIPRECT_3_TL ; /* 0xA08A */ + union UINT_FLOAT PA_SC_CLIPRECT_3_BR ; /* 0xA08B */ + + union UINT_FLOAT PA_SC_EDGERULE ; /* 0xA08C */ + + union UINT_FLOAT CB_TARGET_MASK ; /* 0xA08E */ + union UINT_FLOAT CB_SHADER_MASK ; /* 0xA08F */ + union UINT_FLOAT PA_SC_GENERIC_SCISSOR_TL ; /* 0xA090 */ + union UINT_FLOAT PA_SC_GENERIC_SCISSOR_BR ; /* 0xA091 */ + + union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_TL ; /* 0xA094 */ + union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_BR ; /* 0xA095 */ + union UINT_FLOAT PA_SC_VPORT_SCISSOR_1_TL ; /* 0xA096 */ + union UINT_FLOAT PA_SC_VPORT_SCISSOR_1_BR ; /* 0xA097 */ + + union UINT_FLOAT PA_SC_VPORT_ZMIN_0 ; /* 0xA0B4 */ + union UINT_FLOAT PA_SC_VPORT_ZMAX_0 ; /* 0xA0B5 */ + + union UINT_FLOAT SX_MISC ; /* 0xA0D4 */ + + union UINT_FLOAT SQ_VTX_SEMANTIC_0 ; /* 0xA0E0 */ + union UINT_FLOAT SQ_VTX_SEMANTIC_1 ; /* 0xA0E1 */ + union UINT_FLOAT SQ_VTX_SEMANTIC_2 ; /* 0xA0E2 */ + union UINT_FLOAT SQ_VTX_SEMANTIC_3 ; /* 0xA0E3 */ + union UINT_FLOAT SQ_VTX_SEMANTIC_4 ; /* 0xA0E4 */ + union UINT_FLOAT SQ_VTX_SEMANTIC_5 ; /* 0xA0E5 */ + union UINT_FLOAT SQ_VTX_SEMANTIC_6 ; /* 0xA0E6 */ + union UINT_FLOAT SQ_VTX_SEMANTIC_7 ; /* 0xA0E7 */ + union UINT_FLOAT SQ_VTX_SEMANTIC_8 ; /* 0xA0E8 */ + union UINT_FLOAT SQ_VTX_SEMANTIC_9 ; /* 0xA0E9 */ + union UINT_FLOAT SQ_VTX_SEMANTIC_10 ; /* 0xA0EA */ + union UINT_FLOAT SQ_VTX_SEMANTIC_11 ; /* 0xA0EB */ + union UINT_FLOAT SQ_VTX_SEMANTIC_12 ; /* 0xA0EC */ + union UINT_FLOAT SQ_VTX_SEMANTIC_13 ; /* 0xA0ED */ + union UINT_FLOAT SQ_VTX_SEMANTIC_14 ; /* 0xA0EE */ + union UINT_FLOAT SQ_VTX_SEMANTIC_15 ; /* 0xA0EF */ + union UINT_FLOAT SQ_VTX_SEMANTIC_16 ; /* 0xA0F0 */ + union UINT_FLOAT SQ_VTX_SEMANTIC_17 ; /* 0xA0F1 */ + union UINT_FLOAT SQ_VTX_SEMANTIC_18 ; /* 0xA0F2 */ + union UINT_FLOAT SQ_VTX_SEMANTIC_19 ; /* 0xA0F3 */ + union UINT_FLOAT SQ_VTX_SEMANTIC_20 ; /* 0xA0F4 */ + union UINT_FLOAT SQ_VTX_SEMANTIC_21 ; /* 0xA0F5 */ + union UINT_FLOAT SQ_VTX_SEMANTIC_22 ; /* 0xA0F6 */ + union UINT_FLOAT SQ_VTX_SEMANTIC_23 ; /* 0xA0F7 */ + union UINT_FLOAT SQ_VTX_SEMANTIC_24 ; /* 0xA0F8 */ + union UINT_FLOAT SQ_VTX_SEMANTIC_25 ; /* 0xA0F9 */ + union UINT_FLOAT SQ_VTX_SEMANTIC_26 ; /* 0xA0FA */ + union UINT_FLOAT SQ_VTX_SEMANTIC_27 ; /* 0xA0FB */ + union UINT_FLOAT SQ_VTX_SEMANTIC_28 ; /* 0xA0FC */ + union UINT_FLOAT SQ_VTX_SEMANTIC_29 ; /* 0xA0FD */ + union UINT_FLOAT SQ_VTX_SEMANTIC_30 ; /* 0xA0FE */ + union UINT_FLOAT SQ_VTX_SEMANTIC_31 ; /* 0xA0FF */ + + union UINT_FLOAT VGT_MAX_VTX_INDX ; /* 0xA100 */ + union UINT_FLOAT VGT_MIN_VTX_INDX ; /* 0xA101 */ + union UINT_FLOAT VGT_INDX_OFFSET ; /* 0xA102 */ + union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_INDX; /* 0xA103 */ + union UINT_FLOAT SX_ALPHA_TEST_CONTROL ; /* 0xA104 */ + + union UINT_FLOAT CB_BLEND_RED ; /* 0xA105 */ + union UINT_FLOAT CB_BLEND_GREEN ; /* 0xA106 */ + union UINT_FLOAT CB_BLEND_BLUE ; /* 0xA107 */ + union UINT_FLOAT CB_BLEND_ALPHA ; /* 0xA108 */ + + union UINT_FLOAT PA_CL_VPORT_XSCALE ; /* 0xA10F */ + union UINT_FLOAT PA_CL_VPORT_XOFFSET ; /* 0xA110 */ + union UINT_FLOAT PA_CL_VPORT_YSCALE ; /* 0xA111 */ + union UINT_FLOAT PA_CL_VPORT_YOFFSET ; /* 0xA112 */ + union UINT_FLOAT PA_CL_VPORT_ZSCALE ; /* 0xA113 */ + union UINT_FLOAT PA_CL_VPORT_ZOFFSET ; /* 0xA114 */ + + union UINT_FLOAT SPI_VS_OUT_ID_0 ; /* 0xA185 */ + union UINT_FLOAT SPI_VS_OUT_ID_1 ; /* 0xA186 */ + union UINT_FLOAT SPI_VS_OUT_ID_2 ; /* 0xA187 */ + union UINT_FLOAT SPI_VS_OUT_ID_3 ; /* 0xA188 */ + union UINT_FLOAT SPI_VS_OUT_ID_4 ; /* 0xA189 */ + union UINT_FLOAT SPI_VS_OUT_ID_5 ; /* 0xA18A */ + union UINT_FLOAT SPI_VS_OUT_ID_6 ; /* 0xA18B */ + union UINT_FLOAT SPI_VS_OUT_ID_7 ; /* 0xA18C */ + union UINT_FLOAT SPI_VS_OUT_ID_8 ; /* 0xA18D */ + union UINT_FLOAT SPI_VS_OUT_ID_9 ; /* 0xA18E */ + + union UINT_FLOAT SPI_PS_INPUT_CNTL_0 ; /* 0xA191 */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_1 ; /* 0xA192 */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_2 ; /* 0xA193 */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_3 ; /* 0xA194 */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_4 ; /* 0xA195 */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_5 ; /* 0xA196 */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_6 ; /* 0xA197 */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_7 ; /* 0xA198 */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_8 ; /* 0xA199 */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_9 ; /* 0xA19A */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_10 ; /* 0xA19B */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_11 ; /* 0xA19C */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_12 ; /* 0xA19D */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_13 ; /* 0xA19E */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_14 ; /* 0xA19F */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_15 ; /* 0xA1A0 */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_16 ; /* 0xA1A1 */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_17 ; /* 0xA1A2 */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_18 ; /* 0xA1A3 */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_19 ; /* 0xA1A4 */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_20 ; /* 0xA1A5 */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_21 ; /* 0xA1A6 */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_22 ; /* 0xA1A7 */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_23 ; /* 0xA1A8 */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_24 ; /* 0xA1A9 */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_25 ; /* 0xA1AA */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_26 ; /* 0xA1AB */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_27 ; /* 0xA1AC */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_28 ; /* 0xA1AD */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_29 ; /* 0xA1AE */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_30 ; /* 0xA1AF */ + union UINT_FLOAT SPI_PS_INPUT_CNTL_31 ; /* 0xA1B0 */ + union UINT_FLOAT SPI_VS_OUT_CONFIG ; /* 0xA1B1 */ + union UINT_FLOAT SPI_THREAD_GROUPING ; /* 0xA1B2 */ + union UINT_FLOAT SPI_PS_IN_CONTROL_0 ; /* 0xA1B3 */ + union UINT_FLOAT SPI_PS_IN_CONTROL_1 ; /* 0xA1B4 */ + + union UINT_FLOAT SPI_INPUT_Z ; /* 0xA1B6 */ + union UINT_FLOAT SPI_FOG_CNTL ; /* 0xA1B7 */ + + union UINT_FLOAT CB_BLEND0_CONTROL ; /* 0xA1E0 */ + + union UINT_FLOAT CB_SHADER_CONTROL ; /* 0xA1E8 */ + + /*union UINT_FLOAT VGT_DRAW_INITIATOR*/ ; /* 0xA1FC */ + + union UINT_FLOAT DB_DEPTH_CONTROL ; /* 0xA200 */ + + union UINT_FLOAT CB_COLOR_CONTROL ; /* 0xA202 */ + union UINT_FLOAT DB_SHADER_CONTROL ; /* 0xA203 */ + union UINT_FLOAT PA_CL_CLIP_CNTL ; /* 0xA204 */ + union UINT_FLOAT PA_SU_SC_MODE_CNTL ; /* 0xA205 */ + union UINT_FLOAT PA_CL_VTE_CNTL ; /* 0xA206 */ + union UINT_FLOAT PA_CL_VS_OUT_CNTL ; /* 0xA207 */ + union UINT_FLOAT PA_CL_NANINF_CNTL ; /* 0xA208 */ + + union UINT_FLOAT SQ_PGM_START_PS ; /* 0xA210 */ + union UINT_FLOAT SQ_PGM_RESOURCES_PS ; /* 0xA214 */ + union UINT_FLOAT SQ_PGM_EXPORTS_PS ; /* 0xA215 */ + union UINT_FLOAT SQ_PGM_START_VS ; /* 0xA216 */ + union UINT_FLOAT SQ_PGM_RESOURCES_VS ; /* 0xA21A */ + union UINT_FLOAT SQ_PGM_START_GS ; /* 0xA21B */ + union UINT_FLOAT SQ_PGM_RESOURCES_GS ; /* 0xA21F */ + union UINT_FLOAT SQ_PGM_START_ES ; /* 0xA220 */ + union UINT_FLOAT SQ_PGM_RESOURCES_ES ; /* 0xA224 */ + union UINT_FLOAT SQ_PGM_START_FS ; /* 0xA225 */ + union UINT_FLOAT SQ_PGM_RESOURCES_FS ; /* 0xA229 */ + union UINT_FLOAT SQ_ESGS_RING_ITEMSIZE ; /* 0xA22A */ + union UINT_FLOAT SQ_GSVS_RING_ITEMSIZE ; /* 0xA22B */ + union UINT_FLOAT SQ_ESTMP_RING_ITEMSIZE ; /* 0xA22C */ + union UINT_FLOAT SQ_GSTMP_RING_ITEMSIZE ; /* 0xA22D */ + union UINT_FLOAT SQ_VSTMP_RING_ITEMSIZE ; /* 0xA22E */ + union UINT_FLOAT SQ_PSTMP_RING_ITEMSIZE ; /* 0xA22F */ + union UINT_FLOAT SQ_FBUF_RING_ITEMSIZE ; /* 0xA230 */ + union UINT_FLOAT SQ_REDUC_RING_ITEMSIZE ; /* 0xA231 */ + union UINT_FLOAT SQ_GS_VERT_ITEMSIZE ; /* 0xA232 */ + union UINT_FLOAT SQ_PGM_CF_OFFSET_PS ; /* 0xA233 */ + union UINT_FLOAT SQ_PGM_CF_OFFSET_VS ; /* 0xA234 */ + union UINT_FLOAT SQ_PGM_CF_OFFSET_GS ; /* 0xA235 */ + union UINT_FLOAT SQ_PGM_CF_OFFSET_ES ; /* 0xA236 */ + union UINT_FLOAT SQ_PGM_CF_OFFSET_FS ; /* 0xA237 */ + + union UINT_FLOAT PA_SU_POINT_SIZE ; /* 0xA280 */ + union UINT_FLOAT PA_SU_POINT_MINMAX ; /* 0xA281 */ + union UINT_FLOAT PA_SU_LINE_CNTL ; /* 0xA282 */ + union UINT_FLOAT PA_SC_LINE_STIPPLE ; /* 0xA283 */ + union UINT_FLOAT VGT_OUTPUT_PATH_CNTL ; /* 0xA284 */ + + union UINT_FLOAT VGT_GS_MODE ; /* 0xA290 */ + + union UINT_FLOAT PA_SC_MPASS_PS_CNTL ; /* 0xA292 */ + union UINT_FLOAT PA_SC_MODE_CNTL ; /* 0xA293 */ + + union UINT_FLOAT VGT_PRIMITIVEID_EN ; /* 0xA2A1 */ + union UINT_FLOAT VGT_DMA_NUM_INSTANCES ; /* 0xA2A2 */ + + union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_EN; /* 0xA2A5 */ + + union UINT_FLOAT VGT_INSTANCE_STEP_RATE_0 ; /* 0xA2A8 */ + union UINT_FLOAT VGT_INSTANCE_STEP_RATE_1 ; /* 0xA2A9 */ + + union UINT_FLOAT VGT_STRMOUT_EN ; /* 0xA2AC */ + union UINT_FLOAT VGT_REUSE_OFF ; /* 0xA2AD */ + + union UINT_FLOAT PA_SC_LINE_CNTL ; /* 0xA300 */ + union UINT_FLOAT PA_SC_AA_CONFIG ; /* 0xA301 */ + union UINT_FLOAT PA_SU_VTX_CNTL ; /* 0xA302 */ + union UINT_FLOAT PA_CL_GB_VERT_CLIP_ADJ ; /* 0xA303 */ + union UINT_FLOAT PA_CL_GB_VERT_DISC_ADJ ; /* 0xA304 */ + union UINT_FLOAT PA_CL_GB_HORZ_CLIP_ADJ ; /* 0xA305 */ + union UINT_FLOAT PA_CL_GB_HORZ_DISC_ADJ ; /* 0xA306 */ + union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_MCTX ; /* 0xA307 */ + union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX; /* 0xA308 */ + + union UINT_FLOAT CB_CLRCMP_CONTROL ; /* 0xA30C */ + union UINT_FLOAT CB_CLRCMP_SRC ; /* 0xA30D */ + union UINT_FLOAT CB_CLRCMP_DST ; /* 0xA30E */ + union UINT_FLOAT CB_CLRCMP_MSK ; /* 0xA30F */ + + union UINT_FLOAT PA_SC_AA_MASK ; /* 0xA312 */ + + union UINT_FLOAT VGT_VERTEX_REUSE_BLOCK_CNTL; /* 0xA316 */ + union UINT_FLOAT VGT_OUT_DEALLOC_CNTL ; /* 0xA317 */ + + union UINT_FLOAT DB_RENDER_CONTROL ; /* 0xA343 */ + union UINT_FLOAT DB_RENDER_OVERRIDE ; /* 0xA344 */ + + union UINT_FLOAT DB_HTILE_SURFACE ; /* 0xA349 */ + + union UINT_FLOAT DB_ALPHA_TO_MASK ; /* 0xA351 */ + + union UINT_FLOAT PA_SU_POLY_OFFSET_DB_FMT_CNTL; /* 0xA37E */ + union UINT_FLOAT PA_SU_POLY_OFFSET_CLAMP ; /* 0xA37F */ + union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_SCALE; /* 0xA380 */ + union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_OFFSET; /* 0xA381 */ + union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_SCALE; /* 0xA382 */ + union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_OFFSET; /* 0xA383 */ + + ContextState * pStateList; + + R700_TEXTURE_STATES texture_states; + +} R700_CHIP_CONTEXT; + +#define R700_CONTEXT_STATES(context) ((R700_CHIP_CONTEXT *)(context->chipobj.pvChipObj)) + +extern GLboolean r700InitChipObject(context_t *context); +extern GLboolean r700SendContextStates(context_t *context); + +#endif /* _R700_CHIP_H_ */ + diff --git a/src/mesa/drivers/dri/r600/r700_chipoffset.h b/src/mesa/drivers/dri/r600/r700_chipoffset.h new file mode 100644 index 0000000000..9050b9a715 --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_chipoffset.h @@ -0,0 +1,684 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + * CooperYuan , + */ + +#ifndef _R700_CHIPOFFSET_H_ +#define _R700_CHIPOFFSET_H_ + +#define mmWAIT_UNTIL 0x2010 +#define mmSCRATCH_REG0 0x2140 +#define mmGUI_SCRATCH_REG0 0x2140 +#define mmSCRATCH_REG1 0x2141 +#define mmGUI_SCRATCH_REG1 0x2141 +#define mmSCRATCH_REG2 0x2142 +#define mmGUI_SCRATCH_REG2 0x2142 +#define mmSCRATCH_REG3 0x2143 +#define mmGUI_SCRATCH_REG3 0x2143 +#define mmSCRATCH_REG4 0x2144 +#define mmGUI_SCRATCH_REG4 0x2144 +#define mmSCRATCH_REG5 0x2145 +#define mmGUI_SCRATCH_REG5 0x2145 +#define mmSCRATCH_REG6 0x2146 +#define mmGUI_SCRATCH_REG6 0x2146 +#define mmSCRATCH_REG7 0x2147 +#define mmGUI_SCRATCH_REG7 0x2147 + +#define mmCP_COHER_CNTL 0x217C +#define mmCP_COHER_SIZE 0x217D +#define mmCP_COHER_BASE 0x217E +#define mmCP_COHER_STATUS 0x217F + +#define mmPA_CL_VPORT_XSCALE 0xA10F +#define mmPA_CL_VPORT_XOFFSET 0xA110 +#define mmPA_CL_VPORT_YSCALE 0xA111 +#define mmPA_CL_VPORT_YOFFSET 0xA112 +#define mmPA_CL_VPORT_ZSCALE 0xA113 +#define mmPA_CL_VPORT_ZOFFSET 0xA114 +#define mmPA_CL_VPORT_XSCALE_1 0xA115 +#define mmPA_CL_VPORT_XSCALE_2 0xA11B +#define mmPA_CL_VPORT_XSCALE_3 0xA121 +#define mmPA_CL_VPORT_XSCALE_4 0xA127 +#define mmPA_CL_VPORT_XSCALE_5 0xA12D +#define mmPA_CL_VPORT_XSCALE_6 0xA133 +#define mmPA_CL_VPORT_XSCALE_7 0xA139 +#define mmPA_CL_VPORT_XSCALE_8 0xA13F +#define mmPA_CL_VPORT_XSCALE_9 0xA145 +#define mmPA_CL_VPORT_XSCALE_10 0xA14B +#define mmPA_CL_VPORT_XSCALE_11 0xA151 +#define mmPA_CL_VPORT_XSCALE_12 0xA157 +#define mmPA_CL_VPORT_XSCALE_13 0xA15D +#define mmPA_CL_VPORT_XSCALE_14 0xA163 +#define mmPA_CL_VPORT_XSCALE_15 0xA169 +#define mmPA_CL_VPORT_XOFFSET_1 0xA116 +#define mmPA_CL_VPORT_XOFFSET_2 0xA11C +#define mmPA_CL_VPORT_XOFFSET_3 0xA122 +#define mmPA_CL_VPORT_XOFFSET_4 0xA128 +#define mmPA_CL_VPORT_XOFFSET_5 0xA12E +#define mmPA_CL_VPORT_XOFFSET_6 0xA134 +#define mmPA_CL_VPORT_XOFFSET_7 0xA13A +#define mmPA_CL_VPORT_XOFFSET_8 0xA140 +#define mmPA_CL_VPORT_XOFFSET_9 0xA146 +#define mmPA_CL_VPORT_XOFFSET_10 0xA14C +#define mmPA_CL_VPORT_XOFFSET_11 0xA152 +#define mmPA_CL_VPORT_XOFFSET_12 0xA158 +#define mmPA_CL_VPORT_XOFFSET_13 0xA15E +#define mmPA_CL_VPORT_XOFFSET_14 0xA164 +#define mmPA_CL_VPORT_XOFFSET_15 0xA16A +#define mmPA_CL_VPORT_YSCALE_1 0xA117 +#define mmPA_CL_VPORT_YSCALE_2 0xA11D +#define mmPA_CL_VPORT_YSCALE_3 0xA123 +#define mmPA_CL_VPORT_YSCALE_4 0xA129 +#define mmPA_CL_VPORT_YSCALE_5 0xA12F +#define mmPA_CL_VPORT_YSCALE_6 0xA135 +#define mmPA_CL_VPORT_YSCALE_7 0xA13B +#define mmPA_CL_VPORT_YSCALE_8 0xA141 +#define mmPA_CL_VPORT_YSCALE_9 0xA147 +#define mmPA_CL_VPORT_YSCALE_10 0xA14D +#define mmPA_CL_VPORT_YSCALE_11 0xA153 +#define mmPA_CL_VPORT_YSCALE_12 0xA159 +#define mmPA_CL_VPORT_YSCALE_13 0xA15F +#define mmPA_CL_VPORT_YSCALE_14 0xA165 +#define mmPA_CL_VPORT_YSCALE_15 0xA16B +#define mmPA_CL_VPORT_YOFFSET_1 0xA118 +#define mmPA_CL_VPORT_YOFFSET_2 0xA11E +#define mmPA_CL_VPORT_YOFFSET_3 0xA124 +#define mmPA_CL_VPORT_YOFFSET_4 0xA12A +#define mmPA_CL_VPORT_YOFFSET_5 0xA130 +#define mmPA_CL_VPORT_YOFFSET_6 0xA136 +#define mmPA_CL_VPORT_YOFFSET_7 0xA13C +#define mmPA_CL_VPORT_YOFFSET_8 0xA142 +#define mmPA_CL_VPORT_YOFFSET_9 0xA148 +#define mmPA_CL_VPORT_YOFFSET_10 0xA14E +#define mmPA_CL_VPORT_YOFFSET_11 0xA154 +#define mmPA_CL_VPORT_YOFFSET_12 0xA15A +#define mmPA_CL_VPORT_YOFFSET_13 0xA160 +#define mmPA_CL_VPORT_YOFFSET_14 0xA166 +#define mmPA_CL_VPORT_YOFFSET_15 0xA16C +#define mmPA_CL_VPORT_ZSCALE_1 0xA119 +#define mmPA_CL_VPORT_ZSCALE_2 0xA11F +#define mmPA_CL_VPORT_ZSCALE_3 0xA125 +#define mmPA_CL_VPORT_ZSCALE_4 0xA12B +#define mmPA_CL_VPORT_ZSCALE_5 0xA131 +#define mmPA_CL_VPORT_ZSCALE_6 0xA137 +#define mmPA_CL_VPORT_ZSCALE_7 0xA13D +#define mmPA_CL_VPORT_ZSCALE_8 0xA143 +#define mmPA_CL_VPORT_ZSCALE_9 0xA149 +#define mmPA_CL_VPORT_ZSCALE_10 0xA14F +#define mmPA_CL_VPORT_ZSCALE_11 0xA155 +#define mmPA_CL_VPORT_ZSCALE_12 0xA15B +#define mmPA_CL_VPORT_ZSCALE_13 0xA161 +#define mmPA_CL_VPORT_ZSCALE_14 0xA167 +#define mmPA_CL_VPORT_ZSCALE_15 0xA16D +#define mmPA_CL_VPORT_ZOFFSET_1 0xA11A +#define mmPA_CL_VPORT_ZOFFSET_2 0xA120 +#define mmPA_CL_VPORT_ZOFFSET_3 0xA126 +#define mmPA_CL_VPORT_ZOFFSET_4 0xA12C +#define mmPA_CL_VPORT_ZOFFSET_5 0xA132 +#define mmPA_CL_VPORT_ZOFFSET_6 0xA138 +#define mmPA_CL_VPORT_ZOFFSET_7 0xA13E +#define mmPA_CL_VPORT_ZOFFSET_8 0xA144 +#define mmPA_CL_VPORT_ZOFFSET_9 0xA14A +#define mmPA_CL_VPORT_ZOFFSET_10 0xA150 +#define mmPA_CL_VPORT_ZOFFSET_11 0xA156 +#define mmPA_CL_VPORT_ZOFFSET_12 0xA15C +#define mmPA_CL_VPORT_ZOFFSET_13 0xA162 +#define mmPA_CL_VPORT_ZOFFSET_14 0xA168 +#define mmPA_CL_VPORT_ZOFFSET_15 0xA16E +#define mmPA_CL_VTE_CNTL 0xA206 +#define mmPA_CL_VS_OUT_CNTL 0xA207 +#define mmPA_CL_NANINF_CNTL 0xA208 +#define mmPA_CL_CLIP_CNTL 0xA204 +#define mmPA_CL_GB_VERT_CLIP_ADJ 0xA303 +#define mmPA_CL_GB_VERT_DISC_ADJ 0xA304 +#define mmPA_CL_GB_HORZ_CLIP_ADJ 0xA305 +#define mmPA_CL_GB_HORZ_DISC_ADJ 0xA306 +#define mmPA_CL_UCP_0_X 0xA388 +#define mmPA_CL_UCP_0_Y 0xA389 +#define mmPA_CL_UCP_0_Z 0xA38A +#define mmPA_CL_UCP_0_W 0xA38B +#define mmPA_CL_UCP_1_X 0xA38C +#define mmPA_CL_UCP_1_Y 0xA38D +#define mmPA_CL_UCP_1_Z 0xA38E +#define mmPA_CL_UCP_1_W 0xA38F +#define mmPA_CL_UCP_2_X 0xA390 +#define mmPA_CL_UCP_2_Y 0xA391 +#define mmPA_CL_UCP_2_Z 0xA392 +#define mmPA_CL_UCP_2_W 0xA393 +#define mmPA_CL_UCP_3_X 0xA394 +#define mmPA_CL_UCP_3_Y 0xA395 +#define mmPA_CL_UCP_3_Z 0xA396 +#define mmPA_CL_UCP_3_W 0xA397 +#define mmPA_CL_UCP_4_X 0xA398 +#define mmPA_CL_UCP_4_Y 0xA399 +#define mmPA_CL_UCP_4_Z 0xA39A +#define mmPA_CL_UCP_4_W 0xA39B +#define mmPA_CL_UCP_5_X 0xA39C +#define mmPA_CL_UCP_5_Y 0xA39D +#define mmPA_CL_UCP_5_Z 0xA39E +#define mmPA_CL_UCP_5_W 0xA39F +#define mmPA_CL_POINT_X_RAD 0xA384 +#define mmPA_CL_POINT_Y_RAD 0xA385 +#define mmPA_CL_POINT_SIZE 0xA386 +#define mmPA_CL_POINT_CULL_RAD 0xA387 + +#define mmPA_SU_VTX_CNTL 0xA302 +#define mmPA_SU_POINT_SIZE 0xA280 +#define mmPA_SU_POINT_MINMAX 0xA281 +#define mmPA_SU_LINE_CNTL 0xA282 +#define mmPA_SU_SC_MODE_CNTL 0xA205 +#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0xA37E +#define mmPA_SU_POLY_OFFSET_CLAMP 0xA37F +#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0xA380 +#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0xA381 +#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0xA382 +#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0xA383 + +#define mmPA_SC_WINDOW_OFFSET 0xA080 +#define mmPA_SC_AA_CONFIG 0xA301 +#define mmPA_SC_AA_MASK 0xA312 +#define mmPA_SC_AA_SAMPLE_LOCS_MCTX 0xA307 +#define mmPA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX 0xA308 +#define mmPA_SC_LINE_STIPPLE 0xA283 +#define mmPA_SC_LINE_CNTL 0xA300 +#define mmPA_SC_SCREEN_SCISSOR_TL 0xA00C +#define mmPA_SC_SCREEN_SCISSOR_BR 0xA00D +#define mmPA_SC_WINDOW_SCISSOR_TL 0xA081 +#define mmPA_SC_WINDOW_SCISSOR_BR 0xA082 +#define mmPA_SC_CLIPRECT_RULE 0xA083 +#define mmPA_SC_CLIPRECT_0_TL 0xA084 +#define mmPA_SC_CLIPRECT_0_BR 0xA085 +#define mmPA_SC_CLIPRECT_1_TL 0xA086 +#define mmPA_SC_CLIPRECT_1_BR 0xA087 +#define mmPA_SC_CLIPRECT_2_TL 0xA088 +#define mmPA_SC_CLIPRECT_2_BR 0xA089 +#define mmPA_SC_CLIPRECT_3_TL 0xA08A +#define mmPA_SC_CLIPRECT_3_BR 0xA08B +#define mmPA_SC_EDGERULE 0xA08C +#define mmPA_SC_GENERIC_SCISSOR_TL 0xA090 +#define mmPA_SC_GENERIC_SCISSOR_BR 0xA091 +#define mmPA_SC_VPORT_SCISSOR_0_TL 0xA094 +#define mmPA_SC_VPORT_SCISSOR_1_TL 0xA096 +#define mmPA_SC_VPORT_SCISSOR_2_TL 0xA098 +#define mmPA_SC_VPORT_SCISSOR_3_TL 0xA09A +#define mmPA_SC_VPORT_SCISSOR_4_TL 0xA09C +#define mmPA_SC_VPORT_SCISSOR_5_TL 0xA09E +#define mmPA_SC_VPORT_SCISSOR_6_TL 0xA0A0 +#define mmPA_SC_VPORT_SCISSOR_7_TL 0xA0A2 +#define mmPA_SC_VPORT_SCISSOR_8_TL 0xA0A4 +#define mmPA_SC_VPORT_SCISSOR_9_TL 0xA0A6 +#define mmPA_SC_VPORT_SCISSOR_10_TL 0xA0A8 +#define mmPA_SC_VPORT_SCISSOR_11_TL 0xA0AA +#define mmPA_SC_VPORT_SCISSOR_12_TL 0xA0AC +#define mmPA_SC_VPORT_SCISSOR_13_TL 0xA0AE +#define mmPA_SC_VPORT_SCISSOR_14_TL 0xA0B0 +#define mmPA_SC_VPORT_SCISSOR_15_TL 0xA0B2 +#define mmPA_SC_VPORT_SCISSOR_0_BR 0xA095 +#define mmPA_SC_VPORT_SCISSOR_1_BR 0xA097 +#define mmPA_SC_VPORT_SCISSOR_2_BR 0xA099 +#define mmPA_SC_VPORT_SCISSOR_3_BR 0xA09B +#define mmPA_SC_VPORT_SCISSOR_4_BR 0xA09D +#define mmPA_SC_VPORT_SCISSOR_5_BR 0xA09F +#define mmPA_SC_VPORT_SCISSOR_6_BR 0xA0A1 +#define mmPA_SC_VPORT_SCISSOR_7_BR 0xA0A3 +#define mmPA_SC_VPORT_SCISSOR_8_BR 0xA0A5 +#define mmPA_SC_VPORT_SCISSOR_9_BR 0xA0A7 +#define mmPA_SC_VPORT_SCISSOR_10_BR 0xA0A9 +#define mmPA_SC_VPORT_SCISSOR_11_BR 0xA0AB +#define mmPA_SC_VPORT_SCISSOR_12_BR 0xA0AD +#define mmPA_SC_VPORT_SCISSOR_13_BR 0xA0AF +#define mmPA_SC_VPORT_SCISSOR_14_BR 0xA0B1 +#define mmPA_SC_VPORT_SCISSOR_15_BR 0xA0B3 +#define mmPA_SC_VPORT_ZMIN_0 0xA0B4 +#define mmPA_SC_VPORT_ZMIN_1 0xA0B6 +#define mmPA_SC_VPORT_ZMIN_2 0xA0B8 +#define mmPA_SC_VPORT_ZMIN_3 0xA0BA +#define mmPA_SC_VPORT_ZMIN_4 0xA0BC +#define mmPA_SC_VPORT_ZMIN_5 0xA0BE +#define mmPA_SC_VPORT_ZMIN_6 0xA0C0 +#define mmPA_SC_VPORT_ZMIN_7 0xA0C2 +#define mmPA_SC_VPORT_ZMIN_8 0xA0C4 +#define mmPA_SC_VPORT_ZMIN_9 0xA0C6 +#define mmPA_SC_VPORT_ZMIN_10 0xA0C8 +#define mmPA_SC_VPORT_ZMIN_11 0xA0CA +#define mmPA_SC_VPORT_ZMIN_12 0xA0CC +#define mmPA_SC_VPORT_ZMIN_13 0xA0CE +#define mmPA_SC_VPORT_ZMIN_14 0xA0D0 +#define mmPA_SC_VPORT_ZMIN_15 0xA0D2 +#define mmPA_SC_VPORT_ZMAX_0 0xA0B5 +#define mmPA_SC_VPORT_ZMAX_1 0xA0B7 +#define mmPA_SC_VPORT_ZMAX_2 0xA0B9 +#define mmPA_SC_VPORT_ZMAX_3 0xA0BB +#define mmPA_SC_VPORT_ZMAX_4 0xA0BD +#define mmPA_SC_VPORT_ZMAX_5 0xA0BF +#define mmPA_SC_VPORT_ZMAX_6 0xA0C1 +#define mmPA_SC_VPORT_ZMAX_7 0xA0C3 +#define mmPA_SC_VPORT_ZMAX_8 0xA0C5 +#define mmPA_SC_VPORT_ZMAX_9 0xA0C7 +#define mmPA_SC_VPORT_ZMAX_10 0xA0C9 +#define mmPA_SC_VPORT_ZMAX_11 0xA0CB +#define mmPA_SC_VPORT_ZMAX_12 0xA0CD +#define mmPA_SC_VPORT_ZMAX_13 0xA0CF +#define mmPA_SC_VPORT_ZMAX_14 0xA0D1 +#define mmPA_SC_VPORT_ZMAX_15 0xA0D3 +#define mmPA_SC_MODE_CNTL 0xA293 +#define mmPA_SC_MPASS_PS_CNTL 0xA292 + +#define mmVGT_DRAW_INITIATOR 0xA1FC +#define mmVGT_EVENT_INITIATOR 0xA2A4 +#define mmVGT_EVENT_ADDRESS_REG 0xA1FE +#define mmVGT_DMA_BASE_HI 0xA1F9 +#define mmVGT_DMA_BASE 0xA1FA +#define mmVGT_DMA_INDEX_TYPE 0xA29F +#define mmVGT_DMA_NUM_INSTANCES 0xA2A2 +#define mmVGT_DMA_SIZE 0xA29D + +#define mmVGT_IMMED_DATA 0xA1FD +#define mmVGT_INDEX_TYPE 0x2257 +#define mmVGT_NUM_INDICES 0x225C +#define mmVGT_NUM_INSTANCES 0x225D +#define mmVGT_PRIMITIVE_TYPE 0x2256 +#define mmVGT_PRIMITIVEID_EN 0xA2A1 +#define mmVGT_VTX_CNT_EN 0xA2AE +#define mmVGT_REUSE_OFF 0xA2AD +#define mmVGT_INSTANCE_STEP_RATE_0 0xA2A8 +#define mmVGT_INSTANCE_STEP_RATE_1 0xA2A9 +#define mmVGT_MAX_VTX_INDX 0xA100 +#define mmVGT_MIN_VTX_INDX 0xA101 +#define mmVGT_INDX_OFFSET 0xA102 +#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0xA316 +#define mmVGT_OUT_DEALLOC_CNTL 0xA317 +#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0xA103 +#define mmVGT_MULTI_PRIM_IB_RESET_EN 0xA2A5 +#define mmVGT_ENHANCE 0xA294 +#define mmVGT_OUTPUT_PATH_CNTL 0xA284 +#define mmVGT_HOS_CNTL 0xA285 +#define mmVGT_HOS_MAX_TESS_LEVEL 0xA286 +#define mmVGT_HOS_MIN_TESS_LEVEL 0xA287 +#define mmVGT_HOS_REUSE_DEPTH 0xA288 +#define mmVGT_GROUP_PRIM_TYPE 0xA289 +#define mmVGT_GROUP_FIRST_DECR 0xA28A +#define mmVGT_GROUP_DECR 0xA28B +#define mmVGT_GROUP_VECT_0_CNTL 0xA28C +#define mmVGT_GROUP_VECT_1_CNTL 0xA28D +#define mmVGT_GROUP_VECT_0_FMT_CNTL 0xA28E +#define mmVGT_GROUP_VECT_1_FMT_CNTL 0xA28F +#define mmVGT_GS_MODE 0xA290 +#define mmVGT_GS_OUT_PRIM_TYPE 0xA29B + +#define mmVGT_STRMOUT_EN 0xA2AC +#define mmVGT_STRMOUT_BUFFER_SIZE_0 0xA2B4 +#define mmVGT_STRMOUT_BUFFER_SIZE_1 0xA2B8 +#define mmVGT_STRMOUT_BUFFER_SIZE_2 0xA2BC +#define mmVGT_STRMOUT_BUFFER_SIZE_3 0xA2C0 +#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0xA2B7 +#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0xA2BB +#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0xA2BF +#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0xA2C3 +#define mmVGT_STRMOUT_VTX_STRIDE_0 0xA2B5 +#define mmVGT_STRMOUT_VTX_STRIDE_1 0xA2B9 +#define mmVGT_STRMOUT_VTX_STRIDE_2 0xA2BD +#define mmVGT_STRMOUT_VTX_STRIDE_3 0xA2C1 +#define mmVGT_STRMOUT_BUFFER_BASE_0 0xA2B6 +#define mmVGT_STRMOUT_BUFFER_BASE_1 0xA2BA +#define mmVGT_STRMOUT_BUFFER_BASE_2 0xA2BE +#define mmVGT_STRMOUT_BUFFER_BASE_3 0xA2C2 +#define mmVGT_STRMOUT_BUFFER_EN 0xA2C8 +#define mmVGT_STRMOUT_BASE_OFFSET_0 0xA2C4 +#define mmVGT_STRMOUT_BASE_OFFSET_1 0xA2C5 +#define mmVGT_STRMOUT_BASE_OFFSET_2 0xA2C6 +#define mmVGT_STRMOUT_BASE_OFFSET_3 0xA2C7 +#define mmVGT_STRMOUT_BASE_OFFSET_HI_0 0xA2D1 +#define mmVGT_STRMOUT_BASE_OFFSET_HI_1 0xA2D2 +#define mmVGT_STRMOUT_BASE_OFFSET_HI_2 0xA2D3 +#define mmVGT_STRMOUT_BASE_OFFSET_HI_3 0xA2D4 +#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0xA2CA +#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0xA2CB +#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0xA2CC + +#define mmSQ_PGM_START_PS 0xA210 +#define mmSQ_PGM_CF_OFFSET_PS 0xA233 +#define mmSQ_PGM_RESOURCES_PS 0xA214 +#define mmSQ_PGM_EXPORTS_PS 0xA215 +#define mmSQ_PGM_START_VS 0xA216 +#define mmSQ_PGM_CF_OFFSET_VS 0xA234 +#define mmSQ_PGM_RESOURCES_VS 0xA21A +#define mmSQ_PGM_START_GS 0xA21B +#define mmSQ_PGM_CF_OFFSET_GS 0xA235 +#define mmSQ_PGM_RESOURCES_GS 0xA21F +#define mmSQ_PGM_START_ES 0xA220 +#define mmSQ_PGM_CF_OFFSET_ES 0xA236 +#define mmSQ_PGM_RESOURCES_ES 0xA224 +#define mmSQ_PGM_START_FS 0xA225 +#define mmSQ_PGM_CF_OFFSET_FS 0xA237 +#define mmSQ_PGM_RESOURCES_FS 0xA229 +#define mmSQ_ESGS_RING_ITEMSIZE 0xA22A +#define mmSQ_GSVS_RING_ITEMSIZE 0xA22B +#define mmSQ_ESTMP_RING_ITEMSIZE 0xA22C +#define mmSQ_GSTMP_RING_ITEMSIZE 0xA22D +#define mmSQ_VSTMP_RING_ITEMSIZE 0xA22E +#define mmSQ_PSTMP_RING_ITEMSIZE 0xA22F +#define mmSQ_FBUF_RING_ITEMSIZE 0xA230 +#define mmSQ_REDUC_RING_ITEMSIZE 0xA231 +#define mmSQ_GS_VERT_ITEMSIZE 0xA232 +#define mmSQ_VTX_SEMANTIC_CLEAR 0xA238 + +#define mmSQ_VTX_SEMANTIC_0 0xA0E0 +#define mmSQ_VTX_SEMANTIC_1 0xA0E1 +#define mmSQ_VTX_SEMANTIC_2 0xA0E2 +#define mmSQ_VTX_SEMANTIC_3 0xA0E3 +#define mmSQ_VTX_SEMANTIC_4 0xA0E4 +#define mmSQ_VTX_SEMANTIC_5 0xA0E5 +#define mmSQ_VTX_SEMANTIC_6 0xA0E6 +#define mmSQ_VTX_SEMANTIC_7 0xA0E7 +#define mmSQ_VTX_SEMANTIC_8 0xA0E8 +#define mmSQ_VTX_SEMANTIC_9 0xA0E9 +#define mmSQ_VTX_SEMANTIC_10 0xA0EA +#define mmSQ_VTX_SEMANTIC_11 0xA0EB +#define mmSQ_VTX_SEMANTIC_12 0xA0EC +#define mmSQ_VTX_SEMANTIC_13 0xA0ED +#define mmSQ_VTX_SEMANTIC_14 0xA0EE +#define mmSQ_VTX_SEMANTIC_15 0xA0EF +#define mmSQ_VTX_SEMANTIC_16 0xA0F0 +#define mmSQ_VTX_SEMANTIC_17 0xA0F1 +#define mmSQ_VTX_SEMANTIC_18 0xA0F2 +#define mmSQ_VTX_SEMANTIC_19 0xA0F3 +#define mmSQ_VTX_SEMANTIC_20 0xA0F4 +#define mmSQ_VTX_SEMANTIC_21 0xA0F5 +#define mmSQ_VTX_SEMANTIC_22 0xA0F6 +#define mmSQ_VTX_SEMANTIC_23 0xA0F7 +#define mmSQ_VTX_SEMANTIC_24 0xA0F8 +#define mmSQ_VTX_SEMANTIC_25 0xA0F9 +#define mmSQ_VTX_SEMANTIC_26 0xA0FA +#define mmSQ_VTX_SEMANTIC_27 0xA0FB +#define mmSQ_VTX_SEMANTIC_28 0xA0FC +#define mmSQ_VTX_SEMANTIC_29 0xA0FD +#define mmSQ_VTX_SEMANTIC_30 0xA0FE +#define mmSQ_VTX_SEMANTIC_31 0xA0FF + +#define mmSQ_ALU_CONST_CACHE_PS_0 0xA250 +#define mmSQ_ALU_CONST_CACHE_PS_1 0xA251 +#define mmSQ_ALU_CONST_CACHE_PS_2 0xA252 +#define mmSQ_ALU_CONST_CACHE_PS_3 0xA253 +#define mmSQ_ALU_CONST_CACHE_PS_4 0xA254 +#define mmSQ_ALU_CONST_CACHE_PS_5 0xA255 +#define mmSQ_ALU_CONST_CACHE_PS_6 0xA256 +#define mmSQ_ALU_CONST_CACHE_PS_7 0xA257 +#define mmSQ_ALU_CONST_CACHE_PS_8 0xA258 +#define mmSQ_ALU_CONST_CACHE_PS_9 0xA259 +#define mmSQ_ALU_CONST_CACHE_PS_10 0xA25A +#define mmSQ_ALU_CONST_CACHE_PS_11 0xA25B +#define mmSQ_ALU_CONST_CACHE_PS_12 0xA25C +#define mmSQ_ALU_CONST_CACHE_PS_13 0xA25D +#define mmSQ_ALU_CONST_CACHE_PS_14 0xA25E +#define mmSQ_ALU_CONST_CACHE_PS_15 0xA25F +#define mmSQ_ALU_CONST_CACHE_VS_0 0xA260 +#define mmSQ_ALU_CONST_CACHE_VS_1 0xA261 +#define mmSQ_ALU_CONST_CACHE_VS_2 0xA262 +#define mmSQ_ALU_CONST_CACHE_VS_3 0xA263 +#define mmSQ_ALU_CONST_CACHE_VS_4 0xA264 +#define mmSQ_ALU_CONST_CACHE_VS_5 0xA265 +#define mmSQ_ALU_CONST_CACHE_VS_6 0xA266 +#define mmSQ_ALU_CONST_CACHE_VS_7 0xA267 +#define mmSQ_ALU_CONST_CACHE_VS_8 0xA268 +#define mmSQ_ALU_CONST_CACHE_VS_9 0xA269 +#define mmSQ_ALU_CONST_CACHE_VS_10 0xA26A +#define mmSQ_ALU_CONST_CACHE_VS_11 0xA26B +#define mmSQ_ALU_CONST_CACHE_VS_12 0xA26C +#define mmSQ_ALU_CONST_CACHE_VS_13 0xA26D +#define mmSQ_ALU_CONST_CACHE_VS_14 0xA26E +#define mmSQ_ALU_CONST_CACHE_VS_15 0xA26F +#define mmSQ_ALU_CONST_CACHE_GS_0 0xA270 +#define mmSQ_ALU_CONST_CACHE_GS_1 0xA271 +#define mmSQ_ALU_CONST_CACHE_GS_2 0xA272 +#define mmSQ_ALU_CONST_CACHE_GS_3 0xA273 +#define mmSQ_ALU_CONST_CACHE_GS_4 0xA274 +#define mmSQ_ALU_CONST_CACHE_GS_5 0xA275 +#define mmSQ_ALU_CONST_CACHE_GS_6 0xA276 +#define mmSQ_ALU_CONST_CACHE_GS_7 0xA277 +#define mmSQ_ALU_CONST_CACHE_GS_8 0xA278 +#define mmSQ_ALU_CONST_CACHE_GS_9 0xA279 +#define mmSQ_ALU_CONST_CACHE_GS_10 0xA27A +#define mmSQ_ALU_CONST_CACHE_GS_11 0xA27B +#define mmSQ_ALU_CONST_CACHE_GS_12 0xA27C +#define mmSQ_ALU_CONST_CACHE_GS_13 0xA27D +#define mmSQ_ALU_CONST_CACHE_GS_14 0xA27E +#define mmSQ_ALU_CONST_CACHE_GS_15 0xA27F +#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_0 0xA050 +#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_1 0xA051 +#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_2 0xA052 +#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_3 0xA053 +#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_4 0xA054 +#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_5 0xA055 +#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_6 0xA056 +#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_7 0xA057 +#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_8 0xA058 +#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_9 0xA059 +#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_10 0xA05A +#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_11 0xA05B +#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_12 0xA05C +#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_13 0xA05D +#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_14 0xA05E +#define mmSQ_ALU_CONST_BUFFER_SIZE_PS_15 0xA05F +#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_0 0xA060 +#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_1 0xA061 +#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_2 0xA062 +#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_3 0xA063 +#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_4 0xA064 +#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_5 0xA065 +#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_6 0xA066 +#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_7 0xA067 +#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_8 0xA068 +#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_9 0xA069 +#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_10 0xA06A +#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_11 0xA06B +#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_12 0xA06C +#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_13 0xA06D +#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_14 0xA06E +#define mmSQ_ALU_CONST_BUFFER_SIZE_VS_15 0xA06F +#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_0 0xA070 +#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_1 0xA071 +#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_2 0xA072 +#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_3 0xA073 +#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_4 0xA074 +#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_5 0xA075 +#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_6 0xA076 +#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_7 0xA077 +#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_8 0xA078 +#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_9 0xA079 +#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_10 0xA07A +#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_11 0xA07B +#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_12 0xA07C +#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_13 0xA07D +#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_14 0xA07E +#define mmSQ_ALU_CONST_BUFFER_SIZE_GS_15 0xA07F + +#define mmSPI_VS_OUT_ID_0 0xA185 +#define mmSPI_VS_OUT_ID_1 0xA186 +#define mmSPI_VS_OUT_ID_2 0xA187 +#define mmSPI_VS_OUT_ID_3 0xA188 +#define mmSPI_VS_OUT_ID_4 0xA189 +#define mmSPI_VS_OUT_ID_5 0xA18A +#define mmSPI_VS_OUT_ID_6 0xA18B +#define mmSPI_VS_OUT_ID_7 0xA18C +#define mmSPI_VS_OUT_ID_8 0xA18D +#define mmSPI_VS_OUT_ID_9 0xA18E +#define mmSPI_PS_INPUT_CNTL_0 0xA191 +#define mmSPI_PS_INPUT_CNTL_1 0xA192 +#define mmSPI_PS_INPUT_CNTL_2 0xA193 +#define mmSPI_PS_INPUT_CNTL_3 0xA194 +#define mmSPI_PS_INPUT_CNTL_4 0xA195 +#define mmSPI_PS_INPUT_CNTL_5 0xA196 +#define mmSPI_PS_INPUT_CNTL_6 0xA197 +#define mmSPI_PS_INPUT_CNTL_7 0xA198 +#define mmSPI_PS_INPUT_CNTL_8 0xA199 +#define mmSPI_PS_INPUT_CNTL_9 0xA19A +#define mmSPI_PS_INPUT_CNTL_10 0xA19B +#define mmSPI_PS_INPUT_CNTL_11 0xA19C +#define mmSPI_PS_INPUT_CNTL_12 0xA19D +#define mmSPI_PS_INPUT_CNTL_13 0xA19E +#define mmSPI_PS_INPUT_CNTL_14 0xA19F +#define mmSPI_PS_INPUT_CNTL_15 0xA1A0 +#define mmSPI_PS_INPUT_CNTL_16 0xA1A1 +#define mmSPI_PS_INPUT_CNTL_17 0xA1A2 +#define mmSPI_PS_INPUT_CNTL_18 0xA1A3 +#define mmSPI_PS_INPUT_CNTL_19 0xA1A4 +#define mmSPI_PS_INPUT_CNTL_20 0xA1A5 +#define mmSPI_PS_INPUT_CNTL_21 0xA1A6 +#define mmSPI_PS_INPUT_CNTL_22 0xA1A7 +#define mmSPI_PS_INPUT_CNTL_23 0xA1A8 +#define mmSPI_PS_INPUT_CNTL_24 0xA1A9 +#define mmSPI_PS_INPUT_CNTL_25 0xA1AA +#define mmSPI_PS_INPUT_CNTL_26 0xA1AB +#define mmSPI_PS_INPUT_CNTL_27 0xA1AC +#define mmSPI_PS_INPUT_CNTL_28 0xA1AD +#define mmSPI_PS_INPUT_CNTL_29 0xA1AE +#define mmSPI_PS_INPUT_CNTL_30 0xA1AF +#define mmSPI_PS_INPUT_CNTL_31 0xA1B0 +#define mmSPI_VS_OUT_CONFIG 0xA1B1 +#define mmSPI_THREAD_GROUPING 0xA1B2 +#define mmSPI_PS_IN_CONTROL_0 0xA1B3 +#define mmSPI_PS_IN_CONTROL_1 0xA1B4 +#define mmSPI_INTERP_CONTROL_0 0xA1B5 +#define mmSPI_INPUT_Z 0xA1B6 +#define mmSPI_FOG_CNTL 0xA1B7 +#define mmSPI_FOG_FUNC_SCALE 0xA1B8 +#define mmSPI_FOG_FUNC_BIAS 0xA1B9 + +#define mmSX_MISC 0xA0D4 + +#define mmSX_ALPHA_TEST_CONTROL 0xA104 +#define mmSX_ALPHA_REF 0xA10E + +#define mmDB_DEPTH_BASE 0xA003 +#define mmDB_DEPTH_INFO 0xA004 +#define mmDB_HTILE_DATA_BASE 0xA005 +#define mmDB_DEPTH_SIZE 0xA000 +#define mmDB_DEPTH_VIEW 0xA001 +#define mmDB_RENDER_CONTROL 0xA343 +#define mmDB_RENDER_OVERRIDE 0xA344 +#define mmDB_SHADER_CONTROL 0xA203 +#define mmDB_STENCIL_CLEAR 0xA00A +#define mmDB_DEPTH_CLEAR 0xA00B +#define mmDB_HTILE_SURFACE 0xA349 +#define mmDB_PRELOAD_CONTROL 0xA34C +#define mmDB_PREFETCH_LIMIT 0xA34D +#define mmDB_STENCILREFMASK 0xA10C +#define mmDB_STENCILREFMASK_BF 0xA10D +#define mmDB_SRESULTS_COMPARE_STATE0 0xA34A +#define mmDB_SRESULTS_COMPARE_STATE1 0xA34B +#define mmDB_DEPTH_CONTROL 0xA200 +#define mmDB_ALPHA_TO_MASK 0xA351 + +#define mmCB_BLEND_RED 0xA105 +#define mmCB_BLEND_GREEN 0xA106 +#define mmCB_BLEND_BLUE 0xA107 +#define mmCB_BLEND_ALPHA 0xA108 +#define mmCB_FOG_RED_R6XX 0xA109 +#define mmCB_FOG_GREEN_R6XX 0xA10A +#define mmCB_FOG_BLUE_R6XX 0xA10B +#define mmCB_BLEND_CONTROL 0xA201 +#define mmCB_COLOR_CONTROL 0xA202 +#define mmCB_BLEND0_CONTROL 0xA1E0 +#define mmCB_BLEND1_CONTROL 0xA1E1 +#define mmCB_BLEND2_CONTROL 0xA1E2 +#define mmCB_BLEND3_CONTROL 0xA1E3 +#define mmCB_BLEND4_CONTROL 0xA1E4 +#define mmCB_BLEND5_CONTROL 0xA1E5 +#define mmCB_BLEND6_CONTROL 0xA1E6 +#define mmCB_BLEND7_CONTROL 0xA1E7 +#define mmCB_CLRCMP_CONTROL 0xA30C +#define mmCB_CLRCMP_SRC 0xA30D +#define mmCB_CLRCMP_DST 0xA30E +#define mmCB_CLRCMP_MSK 0xA30F +#define mmCB_COLOR0_BASE 0xA010 +#define mmCB_COLOR1_BASE 0xA011 +#define mmCB_COLOR2_BASE 0xA012 +#define mmCB_COLOR3_BASE 0xA013 +#define mmCB_COLOR4_BASE 0xA014 +#define mmCB_COLOR5_BASE 0xA015 +#define mmCB_COLOR6_BASE 0xA016 +#define mmCB_COLOR7_BASE 0xA017 +#define mmCB_COLOR0_SIZE 0xA018 +#define mmCB_COLOR1_SIZE 0xA019 +#define mmCB_COLOR2_SIZE 0xA01A +#define mmCB_COLOR3_SIZE 0xA01B +#define mmCB_COLOR4_SIZE 0xA01C +#define mmCB_COLOR5_SIZE 0xA01D +#define mmCB_COLOR6_SIZE 0xA01E +#define mmCB_COLOR7_SIZE 0xA01F +#define mmCB_COLOR0_VIEW 0xA020 +#define mmCB_COLOR1_VIEW 0xA021 +#define mmCB_COLOR2_VIEW 0xA022 +#define mmCB_COLOR3_VIEW 0xA023 +#define mmCB_COLOR4_VIEW 0xA024 +#define mmCB_COLOR5_VIEW 0xA025 +#define mmCB_COLOR6_VIEW 0xA026 +#define mmCB_COLOR7_VIEW 0xA027 +#define mmCB_COLOR0_INFO 0xA028 +#define mmCB_COLOR1_INFO 0xA029 +#define mmCB_COLOR2_INFO 0xA02A +#define mmCB_COLOR3_INFO 0xA02B +#define mmCB_COLOR4_INFO 0xA02C +#define mmCB_COLOR5_INFO 0xA02D +#define mmCB_COLOR6_INFO 0xA02E +#define mmCB_COLOR7_INFO 0xA02F +#define mmCB_COLOR0_TILE 0xA030 +#define mmCB_COLOR1_TILE 0xA031 +#define mmCB_COLOR2_TILE 0xA032 +#define mmCB_COLOR3_TILE 0xA033 +#define mmCB_COLOR4_TILE 0xA034 +#define mmCB_COLOR5_TILE 0xA035 +#define mmCB_COLOR6_TILE 0xA036 +#define mmCB_COLOR7_TILE 0xA037 +#define mmCB_COLOR0_FRAG 0xA038 +#define mmCB_COLOR1_FRAG 0xA039 +#define mmCB_COLOR2_FRAG 0xA03A +#define mmCB_COLOR3_FRAG 0xA03B +#define mmCB_COLOR4_FRAG 0xA03C +#define mmCB_COLOR5_FRAG 0xA03D +#define mmCB_COLOR6_FRAG 0xA03E +#define mmCB_COLOR7_FRAG 0xA03F +#define mmCB_COLOR0_MASK 0xA040 +#define mmCB_COLOR1_MASK 0xA041 +#define mmCB_COLOR2_MASK 0xA042 +#define mmCB_COLOR3_MASK 0xA043 +#define mmCB_COLOR4_MASK 0xA044 +#define mmCB_COLOR5_MASK 0xA045 +#define mmCB_COLOR6_MASK 0xA046 +#define mmCB_COLOR7_MASK 0xA047 +#define mmCB_CLEAR_RED_R6XX 0xA048 +#define mmCB_CLEAR_GREEN_R6XX 0xA049 +#define mmCB_CLEAR_BLUE_R6XX 0xA04A +#define mmCB_CLEAR_ALPHA_R6XX 0xA04B +#define mmCB_TARGET_MASK 0xA08E +#define mmCB_SHADER_MASK 0xA08F +#define mmCB_SHADER_CONTROL 0xA1E8 + +#define mmSQ_VTX_BASE_VTX_LOC 0xF3FC +#define mmSQ_VTX_START_INST_LOC 0xF3FD + +#endif /* _R700_CHIPOFFSET_H_ */ + diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c new file mode 100644 index 0000000000..5725360dac --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_clear.c @@ -0,0 +1,267 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + * CooperYuan , + */ + +#include "main/glheader.h" +#include "main/context.h" +#include "main/macros.h" +#include "main/imports.h" +#include "main/mtypes.h" +#include "main/enums.h" + +#include "r600_context.h" +#include "r700_chip.h" + +#if 0 /* to be enabled */ +#include "r700_shaderinst.h" +#include "r700_emit.h" +#endif /* to be enabled */ + +extern void r700InitState (GLcontext * ctx); + +#if 0 /* to be enabled */ +extern void r700SetupVTXConstans(GLcontext * ctx, + unsigned int nStreamID, + unsigned int aos_offset, + unsigned int size, /* number of elements in vector */ + unsigned int stride, + unsigned int count); +extern GLboolean r700SendContextStates(context_t *context); +extern GLboolean r700SyncSurf(context_t *context); +#endif /* to be enabled */ + +static GLboolean r700ClearFast(context_t *context, GLbitfield mask) +{ + /* TODO, fast clear need implementation */ + return GL_FALSE; +} + +static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) +{ + GLcontext *ctx = GL_CONTEXT(context); + +#if 0 /* to be enabled */ + R700_CHIP_CONTEXT r700Saved; + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + struct r600_dma_region aos_vs; + struct r600_dma_region aos_fs; + struct r600_dma_region aos_vb; + aos_vs.buf = NULL; + aos_fs.buf = NULL; + aos_vb.buf = NULL; + + + unsigned int ui; + GLfloat fTemp; + GLfloat fVb[] = { 1.0f, 1.0f, 1.0f, 1.0f, + -1.0f, -1.0f, 1.0f, 1.0f, + 1.0f, -1.0f, 1.0f, 1.0f, + 1.0f, 1.0f, 1.0f, 1.0f, + -1.0f, 1.0f, 1.0f, 1.0f, + -1.0f, -1.0f, 1.0f, 1.0f}; /* TODO : Z set here */ + unsigned int uVs[] = { 0xC, 0x81000000, 0x4, 0xA01C0000, + 0xC001203C, 0x94000688, 0xC001C000, 0x94200688, + 0x10000001, 0x540C90, 0x10000401, 0x20540C90, + 0x10000801, 0x40540C90, 0x90000C01, 0x60400C90, + 0x10000100, 0x600C90, 0x10000500, 0x20600C90, + 0x10000900, 0x40600C90, 0x90000D00, 0x60680C90, + 0x7C000000, 0x2D1001, 0x80000, 0xBEADEAF }; + unsigned int uFs[] = { 0x2, 0xA00C0000, 0xC0008000, 0x94200688, + 0x10000000, 0x340C90, 0x10000400, 0x20340C90, + 0x10000800, 0x40340C90, 0x90000C00, 0x60200C90}; + + if (context->screen->chip.type <= CHIP_TYPE_RV670) + { + uVs[9] = 0x541910; + uVs[11] = 0x20541910; + uVs[13] = 0x40541910; + uVs[15] = 0x60401910; + uVs[17] = 0x601910; + uVs[19] = 0x20601910; + uVs[21] = 0x40601910; + uVs[23] = 0x60681910; + uFs[5] = 0x341910; + uFs[7] = 0x20341910; + uFs[9] = 0x40341910; + uFs[11] = 0x60201910; + } + + r700SyncSurf(context); + + /* Save current chip object. */ + memcpy(&r700Saved, r700, sizeof(R700_CHIP_CONTEXT)); + + r700InitState(ctx); + + r700->CB_COLOR0_BASE.u32All = context->target.rt.gpu >> 8; + + /* Turn off perspective divid. */ + SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit); + SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit); + SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit); + + if( (mask & BUFFER_BIT_FRONT_LEFT) || (mask & BUFFER_BIT_BACK_LEFT) ) + { /* Enable render target output. */ + SETfield(r700->CB_TARGET_MASK.u32All, 0xF, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask); + } + else + { /* Disable render target output. */ + CLEARfield(r700->CB_TARGET_MASK.u32All, TARGET0_ENABLE_mask); /* TODO : OGL need 4 rt. */ + } + if (mask & BUFFER_BIT_DEPTH) + { + /* Set correct Z to clear. */ + SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit); + SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit); + SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS, ZFUNC_shift, ZFUNC_mask); + fTemp = ctx->Depth.Clear; + for(ui=2; ui<24;) + { + fVb[ui] = fTemp; + ui += 4; + } + } + else + { + /* Disable Z write. */ + CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit); + CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit); + } + + /* Setup vb */ + R700_CMDBUF_CHECK_SPACE(6); + R700EP3 (context, IT_SET_CTL_CONST, 1); + R700E32 (context, mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); + R700E32 (context, 0); + R700EP3 (context, IT_SET_CTL_CONST, 1); + R700E32 (context, mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX); + R700E32 (context, 0); + (context->chipobj.EmitVec)(ctx, &aos_vb, (GLvoid *)fVb, 4, 16, 6); + r700SetupVTXConstans(ctx, VERT_ATTRIB_POS, (unsigned int)aos_vb.aos_offset, 4, 16, 6); + + /* Setup shaders, copied from dump */ + r700->SQ_PGM_RESOURCES_PS.u32All = 0; + r700->SQ_PGM_RESOURCES_VS.u32All = 0; + SETbit(r700->SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); + SETbit(r700->SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); + /* vs */ + (context->chipobj.EmitShader)(ctx, &aos_vs, (GLvoid *)(&uVs[0]), 28); + r700->SQ_PGM_START_VS.u32All = (aos_vs.aos_offset >> 8) & 0x00FFFFFF; + r700->SQ_PGM_RESOURCES_VS.u32All = 0x00800004; + /* vs const */ /* TODO : Set color here */ + R700_CMDBUF_CHECK_SPACE(4 + 2); + R700EP3 (context, IT_SET_ALU_CONST, 4); + R700E32 (context, SQ_ALU_CONSTANT_VS_OFFSET * 4); + R700E32 (context, *((unsigned int*)&(ctx->Color.ClearColor[0]))); + R700E32 (context, *((unsigned int*)&(ctx->Color.ClearColor[1]))); + R700E32 (context, *((unsigned int*)&(ctx->Color.ClearColor[2]))); + R700E32 (context, *((unsigned int*)&(ctx->Color.ClearColor[3]))); + + r700->SPI_VS_OUT_CONFIG.u32All = 0x00000000; + r700->SPI_PS_IN_CONTROL_0.u32All = 0x20000001; + /* ps */ + (context->chipobj.EmitShader)(ctx, &aos_fs, (GLvoid *)(&uFs[0]), 12); + r700->SQ_PGM_START_PS.u32All = (aos_fs.aos_offset >> 8) & 0x00FFFFFF; + r700->SQ_PGM_RESOURCES_PS.u32All = 0x00800002; + r700->SQ_PGM_EXPORTS_PS.u32All = 0x00000002; + r700->DB_SHADER_CONTROL.u32All = 0x00000200; + + r700->CB_SHADER_CONTROL.u32All = 0x00000001; + + /* set a valid base address to make the command checker happy */ + r700->SQ_PGM_START_FS.u32All = (aos_fs.aos_offset >> 8) & 0x00FFFFFF; + r700->SQ_PGM_START_ES.u32All = (aos_fs.aos_offset >> 8) & 0x00FFFFFF; + r700->SQ_PGM_START_GS.u32All = (aos_fs.aos_offset >> 8) & 0x00FFFFFF; + + /* Now, send the states */ + r700SendContextStates(context); + + /* Draw */ + GLuint numEntires, j; + GLuint numIndices = 6; + unsigned int VGT_DRAW_INITIATOR = 0; + unsigned int VGT_INDEX_TYPE = 0; + unsigned int VGT_PRIMITIVE_TYPE = 0; + unsigned int VGT_NUM_INDICES = 0; + + numEntires = 2 /* VGT_INDEX_TYPE */ + + 3 /* VGT_PRIMITIVE_TYPE */ + + numIndices + 3; /* DRAW_INDEX_IMMD */ + + R700_CMDBUF_CHECK_SPACE(numEntires); + + SETfield(VGT_INDEX_TYPE, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask); + + R700EP3(context, IT_INDEX_TYPE, 0); + R700E32(context, VGT_INDEX_TYPE); + + VGT_NUM_INDICES = numIndices; + + SETfield(VGT_PRIMITIVE_TYPE, DI_PT_TRILIST, VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask); + R700EP3(context, IT_SET_CONFIG_REG, 1); + R700E32(context, mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); + R700E32(context, VGT_PRIMITIVE_TYPE); + + SETfield(VGT_DRAW_INITIATOR, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask); + SETfield(VGT_DRAW_INITIATOR, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask); + + R700EP3(context, IT_DRAW_INDEX_IMMD, (numIndices + 1)); + R700E32(context, VGT_NUM_INDICES); + R700E32(context, VGT_DRAW_INITIATOR); + + for (j=0; jchipobj.FlushCmdBuffer)(context); + + /* TODO : keep these in context, don't load and release every time. */ + (context->chipobj.FreeDmaRegion)(context, &aos_vs); + (context->chipobj.FreeDmaRegion)(context, &aos_fs); + (context->chipobj.FreeDmaRegion)(context, &aos_vb); + + /* Restore chip object. */ + memcpy(r700, &r700Saved, sizeof(R700_CHIP_CONTEXT)); + +#endif /* to be enabled */ + + return GL_TRUE; +} + +void r700Clear(GLcontext * ctx, GLbitfield mask) +{ + context_t *context = R700_CONTEXT(ctx); + + if( GL_TRUE == r700ClearFast(context, mask) ) + { + return; + } + + r700ClearWithDraw(context, mask); +} + + diff --git a/src/mesa/drivers/dri/r600/r700_clear.h b/src/mesa/drivers/dri/r600/r700_clear.h new file mode 100644 index 0000000000..bed1d3a90e --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_clear.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + * CooperYuan , + */ + +#ifndef __r700_CLEAR_H__ +#define __r700_CLEAR_H__ + +extern void r700Clear(GLcontext * ctx, GLbitfield mask); + +#endif /* __r700_CLEAR_H__ */ diff --git a/src/mesa/drivers/dri/r600/r700_debug.c b/src/mesa/drivers/dri/r600/r700_debug.c new file mode 100644 index 0000000000..9e6ad4a696 --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_debug.c @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + * CooperYuan , + */ + +#include +#include +#include +#include + +#include "main/glheader.h" + +#include "r700_debug.h" +#include "r600_context.h" + +void NormalizeLogErrorCode(int nError) +{ + //TODO +} + +void r700_error(int nLocalError, char* fmt, ...) +{ + va_list args; + + NormalizeLogErrorCode(nLocalError); + + va_start(args, fmt); + fprintf(stderr, fmt, args); + va_end(args); +} + +void DumpHwBinary(int type, void *addr, int size) +{ + int i; + unsigned int *pHw = (unsigned int *)addr; + switch (type) + { + case DUMP_PIXEL_SHADER: + DEBUGF("Pixel Shader\n"); + break; + case DUMP_VERTEX_SHADER: + DEBUGF("Vertex Shader\n"); + break; + case DUMP_FETCH_SHADER: + DEBUGF("Fetch Shader\n"); + break; + } + + for (i = 0; i < size; i++) + { + DEBUGP("0x%08x,\t", *pHw); + if (i%4 == 3) + DEBUGP("\n", *pHw); + pHw++; + + } +} + diff --git a/src/mesa/drivers/dri/r600/r700_debug.h b/src/mesa/drivers/dri/r600/r700_debug.h new file mode 100644 index 0000000000..e810e6da08 --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_debug.h @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + * CooperYuan , + */ + +#ifndef _R700_DEBUG_H_ +#define _R700_DEBUG_H_ + +enum R700_ERROR +{ + ERROR_ASM_VTX_CLAUSE = 0x1000, + ERROR_ASM_UNKOWNCLAUSE = 0x1001, + ERROR_ASM_ALLOCEXPORTCF = 0x1002, + ERROR_ASM_ALLOCVTXCF = 0x1003, + ERROR_ASM_ALLOCTEXCF = 0x1004, + ERROR_ASM_ALLOCALUCF = 0x1005, + ERROR_ASM_UNKNOWNILINST = 0x1006, + ERROR_ASM_SRCARGUMENT = 0x1007, + ERROR_ASM_DSTARGUMENT = 0x1008, + ERROR_ASM_TEXINSTRUCTION = 0x1009, + ERROR_ASM_ALUINSTRUCTION = 0x100A, + ERROR_ASM_INSTDSTTRACK = 0x100B, + ERROR_ASM_TEXDSTBADTYPE = 0x100C, + ERROR_ASM_ALUSRCBADTYPE = 0x100D, + ERROR_ASM_ALUSRCSELECT = 0x100E, + ERROR_ASM_ALUSRCNUMBER = 0x100F, + ERROR_ASM_ALUDSTBADTYPE = 0x1010, + ERROR_ASM_CONSTCHANNEL = 0x1011, + ERROR_ASM_BADSCALARBZ = 0x1012, + ERROR_ASM_BADGPRRESERVE = 0x1013, + ERROR_ASM_BADVECTORBZ = 0x1014, + ERROR_ASM_BADTEXINST = 0x1015, + ERROR_ASM_BADTEXSRC = 0x1016, + ERROR_ASM_BADEXPORTTYPE = 0x1017, + + + TODO_ASM_CONSTTEXADDR = 0x8000, + TODO_ASM_NEEDIMPINST = 0x8001, + TODO_ASM_TXB = 0x8002, + TODO_ASM_TXP = 0x8003 +}; + +enum R700_DUMP_TYPE +{ + DUMP_VERTEX_SHADER = 0x1, + DUMP_PIXEL_SHADER = 0x2, + DUMP_FETCH_SHADER = 0x4, +}; + +#define DEBUGF printf +#define DEBUGP printf + +void NormalizeLogErrorCode(int nError); +/*NormalizeLogErrorCode(nLocalError); */ +void r700_error(int nLocalError, char *fmt, ...); +extern void DumpHwBinary(int, void *, int); + +#ifdef STANDALONE_COMPILER +#ifdef __cplusplus +extern "C" +{ +#endif //__cplusplus + +void LogString(char* szStr); + +#ifdef __cplusplus +} +#endif //__cplusplus +#endif /*STANDALONE_COMPILER*/ + +#endif /*_R700_DEBUG_H_*/ diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c new file mode 100644 index 0000000000..2b813828a5 --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -0,0 +1,365 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + * CooperYuan , + */ + +#include +#include +#include +#include +#include + +#include "main/imports.h" +#include "shader/prog_parameter.h" +#include "shader/prog_statevars.h" + +#include "r600_context.h" + +#include "r700_chip.h" +#include "r700_fragprog.h" + +/* to be enabled */ +#if 0 +#include "r700_emit.h" +#endif + +#include "r700_debug.h" + +//TODO : Validate FP input with VP output. +void Map_Fragment_Program(r700_AssemblerBase *pAsm, + struct gl_fragment_program *mesa_fp) +{ + unsigned int unBit; + unsigned int i; + GLuint ui; + + pAsm->number_used_registers = 0; + +//Input mapping : mesa_fp->Base.InputsRead set the flag, set in + //The flags parsed in parse_attrib_binding. FRAG_ATTRIB_COLx, FRAG_ATTRIB_TEXx, ... + //MUST match order in Map_Vertex_Output + unBit = 1 << FRAG_ATTRIB_COL0; + if(mesa_fp->Base.InputsRead & unBit) + { + pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL0] = pAsm->number_used_registers++; + } + + unBit = 1 << FRAG_ATTRIB_COL1; + if(mesa_fp->Base.InputsRead & unBit) + { + pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1] = pAsm->number_used_registers++; + } + + for(i=0; i<8; i++) + { + unBit = 1 << (FRAG_ATTRIB_TEX0 + i); + if(mesa_fp->Base.InputsRead & unBit) + { + pAsm->uiFP_AttributeMap[FRAG_ATTRIB_TEX0 + i] = pAsm->number_used_registers++; + } + } + +/* Map temporary registers (GPRs) */ + pAsm->starting_temp_register_number = pAsm->number_used_registers; + + if(mesa_fp->Base.NumNativeTemporaries >= mesa_fp->Base.NumTemporaries) + { + pAsm->number_used_registers += mesa_fp->Base.NumNativeTemporaries; + } + else + { + pAsm->number_used_registers += mesa_fp->Base.NumTemporaries; + } + +/* Output mapping */ + pAsm->number_of_exports = 0; + pAsm->number_of_colorandz_exports = 0; /* don't include stencil and mask out. */ + pAsm->starting_export_register_number = pAsm->number_used_registers; + unBit = 1 << FRAG_RESULT_COLOR; + if(mesa_fp->Base.OutputsWritten & unBit) + { + pAsm->uiFP_OutputMap[FRAG_RESULT_COLOR] = pAsm->number_used_registers++; + pAsm->number_of_exports++; + pAsm->number_of_colorandz_exports++; + } + unBit = 1 << FRAG_RESULT_DEPTH; + if(mesa_fp->Base.OutputsWritten & unBit) + { + pAsm->depth_export_register_number = pAsm->number_used_registers; + pAsm->uiFP_OutputMap[FRAG_RESULT_DEPTH] = pAsm->number_used_registers++; + pAsm->number_of_exports++; + pAsm->number_of_colorandz_exports++; + } + + pAsm->pucOutMask = (unsigned char*) MALLOC(pAsm->number_of_exports); + for(ui=0; uinumber_of_exports; ui++) + { + pAsm->pucOutMask[ui] = 0x0; + } + + pAsm->uFirstHelpReg = pAsm->number_used_registers; +} + +GLboolean Find_Instruction_Dependencies_fp(struct r700_fragment_program *fp, + struct gl_fragment_program *mesa_fp) +{ + GLuint i, j; + GLint * puiTEMPwrites; + struct prog_instruction * pILInst; + InstDeps *pInstDeps; + struct prog_instruction * texcoord_DepInst; + GLint nDepInstID; + + puiTEMPwrites = (GLint*) MALLOC(sizeof(GLuint)*mesa_fp->Base.NumTemporaries); + for(i=0; iBase.NumTemporaries; i++) + { + puiTEMPwrites[i] = -1; + } + + pInstDeps = (InstDeps*)MALLOC(sizeof(InstDeps)*mesa_fp->Base.NumInstructions); + + for(i=0; iBase.NumInstructions; i++) + { + pInstDeps[i].nDstDep = -1; + pILInst = &(mesa_fp->Base.Instructions[i]); + + //Dst + if(pILInst->DstReg.File == PROGRAM_TEMPORARY) + { + //Set lastwrite for the temp + puiTEMPwrites[pILInst->DstReg.Index] = i; + } + + //Src + for(j=0; j<3; j++) + { + if(pILInst->SrcReg[j].File == PROGRAM_TEMPORARY) + { + //Set dep. + pInstDeps[i].nSrcDeps[j] = puiTEMPwrites[pILInst->SrcReg[j].Index]; + } + else + { + pInstDeps[i].nSrcDeps[j] = -1; + } + } + } + + fp->r700AsmCode.pInstDeps = pInstDeps; + + FREE(puiTEMPwrites); + + //Find dep for tex inst + for(i=0; iBase.NumInstructions; i++) + { + pILInst = &(mesa_fp->Base.Instructions[i]); + + if(GL_TRUE == IsTex(pILInst->Opcode)) + { //src0 is the tex coord register, src1 is texunit, src2 is textype + nDepInstID = pInstDeps[i].nSrcDeps[0]; + if(nDepInstID >= 0) + { + texcoord_DepInst = &(mesa_fp->Base.Instructions[nDepInstID]); + if(GL_TRUE == IsAlu(texcoord_DepInst->Opcode) ) + { + pInstDeps[nDepInstID].nDstDep = i; + pInstDeps[i].nDstDep = i; + } + else if(GL_TRUE == IsTex(texcoord_DepInst->Opcode) ) + { + pInstDeps[i].nDstDep = i; + } + else + { //... other deps? + } + } + } + } + + return GL_TRUE; +} + +GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp, + struct gl_fragment_program *mesa_fp) +{ + GLuint number_of_colors_exported; + GLboolean z_enabled = GL_FALSE; + GLuint unBit; + + //Init_Program + Init_r700_AssemblerBase( SPT_FP, &(fp->r700AsmCode), &(fp->r700Shader) ); + Map_Fragment_Program(&(fp->r700AsmCode), mesa_fp); + + if( GL_FALSE == Find_Instruction_Dependencies_fp(fp, mesa_fp) ) + { + return GL_FALSE; + } + + if( GL_FALSE == AssembleInstr(mesa_fp->Base.NumInstructions, + &(mesa_fp->Base.Instructions[0]), + &(fp->r700AsmCode)) ) + { + return GL_FALSE; + } + + if(GL_FALSE == Process_Fragment_Exports(&(fp->r700AsmCode), mesa_fp->Base.OutputsWritten) ) + { + return GL_FALSE; + } + + fp->r700Shader.nRegs = (fp->r700AsmCode.number_used_registers == 0) ? 0 + : (fp->r700AsmCode.number_used_registers - 1); + + fp->r700Shader.nParamExports = fp->r700AsmCode.number_of_exports; + + number_of_colors_exported = fp->r700AsmCode.number_of_colorandz_exports; + + unBit = 1 << FRAG_RESULT_DEPTH; + if(mesa_fp->Base.OutputsWritten & unBit) + { + z_enabled = GL_TRUE; + number_of_colors_exported--; + } + + fp->r700Shader.exportMode = number_of_colors_exported << 1 | z_enabled; + + fp->translated = GL_TRUE; + + return GL_TRUE; +} + +GLboolean r700SetupFragmentProgram(GLcontext * ctx) +{ + context_t *context = R700_CONTEXT(ctx); + + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + + struct r700_fragment_program *fp = (struct r700_fragment_program *) + (ctx->FragmentProgram._Current); + + struct gl_program_parameter_list *paramList; + unsigned int unNumParamData; + unsigned int ui; + + unsigned int unNumOfReg; + + if(GL_FALSE == fp->loaded) + { + if(fp->r700Shader.bNeedsAssembly == GL_TRUE) + { + Assemble( &(fp->r700Shader) ); + } +/* to be enabled */ +#if 0 + /* Load fp to gpu */ + (context->chipobj.EmitShader)(ctx, + &(fp->shadercode), + (GLvoid *)(fp->r700Shader.pProgram), + fp->r700Shader.uShaderBinaryDWORDSize); +#endif + fp->loaded = GL_TRUE; + } + + DumpHwBinary(DUMP_PIXEL_SHADER, (GLvoid *)(fp->r700Shader.pProgram), + fp->r700Shader.uShaderBinaryDWORDSize); + + /* TODO : enable this after MemUse fixed *= + (context->chipobj.MemUse)(context, fp->shadercode.buf->id); + */ +/* to be enabled */ +#if 0 + r700->SQ_PGM_START_PS.u32All = (fp->shadercode.aos_offset >> 8) & 0x00FFFFFF; +#endif + + unNumOfReg = fp->r700Shader.nRegs + 1; + + ui = (r700->SPI_PS_IN_CONTROL_0.u32All & NUM_INTERP_mask) / (1 << NUM_INTERP_shift); + + ui = ui ? unNumOfReg : ui; + + SETfield(r700->SQ_PGM_RESOURCES_PS.u32All, ui, NUM_GPRS_shift, NUM_GPRS_mask); + + CLEARbit(r700->SQ_PGM_RESOURCES_PS.u32All, UNCACHED_FIRST_INST_bit); + + if(fp->r700Shader.uStackSize) /* we don't use branch for now, it should be zero. */ + { + SETfield(r700->SQ_PGM_RESOURCES_PS.u32All, fp->r700Shader.uStackSize, + STACK_SIZE_shift, STACK_SIZE_mask); + } + + SETfield(r700->SQ_PGM_EXPORTS_PS.u32All, fp->r700Shader.exportMode, + EXPORT_MODE_shift, EXPORT_MODE_mask); + + if(fp->r700Shader.killIsUsed) + { + SETbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit); + } + else + { + CLEARbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit); + } + + if(fp->r700Shader.depthIsExported) + { + SETbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit); + } + else + { + CLEARbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit); + } + + /* sent out shader constants. */ + + paramList = fp->mesa_program.Base.Parameters; + + if(NULL != paramList) + { + _mesa_load_state_parameters(ctx, paramList); +/* to be enabled */ +#if 0 + unNumParamData = paramList->NumParameters * 4; + R700_CMDBUF_CHECK_SPACE(2 + unNumParamData); + + R700EP3(context, IT_SET_ALU_CONST, unNumParamData); + /* assembler map const from very beginning. */ + R700E32(context, SQ_ALU_CONSTANT_PS_OFFSET * 4); + + unNumParamData = paramList->NumParameters; + + for(ui=0; uiParameterValues[ui][0]))); + R700E32(context, *((unsigned int*)&(paramList->ParameterValues[ui][1]))); + R700E32(context, *((unsigned int*)&(paramList->ParameterValues[ui][2]))); + R700E32(context, *((unsigned int*)&(paramList->ParameterValues[ui][3]))); + } +#endif + } + + return GL_TRUE; +} + + + diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.h b/src/mesa/drivers/dri/r600/r700_fragprog.h index c19ad181e4..649ee4822d 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.h +++ b/src/mesa/drivers/dri/r600/r700_fragprog.h @@ -1,62 +1,63 @@ /* - * Copyright (C) 2005 Ben Skeggs. + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. * - * All Rights Reserved. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* * Authors: - * Ben Skeggs - * Jerome Glisse + * Richard Li , */ -#ifndef __R700_FRAGPROG_H_ -#define __R700_FRAGPROG_H_ -#include "main/glheader.h" -#include "main/macros.h" -#include "main/enums.h" -#include "shader/prog_parameter.h" -#include "shader/prog_print.h" -#include "shader/program.h" -#include "shader/prog_instruction.h" +#ifndef _R700_FRAGPROG_H_ +#define _R700_FRAGPROG_H_ #include "r600_context.h" -#include "r600_state.h" -#include "radeon_program.h" +#include "r700_assembler.h" + +struct r700_fragment_program +{ + struct gl_fragment_program mesa_program; -struct r500_fragment_program; + r700_AssemblerBase r700AsmCode; + R700_Shader r700Shader; -extern void r500TranslateFragmentShader(r600ContextPtr r600, - struct r500_fragment_program *fp); + GLboolean translated; + GLboolean loaded; + GLboolean error; +/* to be enabled */ +#if 0 + struct r600_dma_region shadercode; +#endif -struct r500_fragment_program_compiler { - r600ContextPtr r600; - struct r500_fragment_program *fp; - struct r500_fragment_program_code *code; - struct gl_program *program; + GLboolean WritesDepth; + GLuint optimization; }; -extern GLboolean r500FragmentProgramEmit(struct r500_fragment_program_compiler *compiler); +/* Internal */ +void Map_Fragment_Program(r700_AssemblerBase *pAsm, + struct gl_fragment_program *mesa_fp); +GLboolean Find_Instruction_Dependencies_fp(struct r700_fragment_program *fp, + struct gl_fragment_program *mesa_fp); -#endif +/* Interface */ +extern GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp, + struct gl_fragment_program *mesa_vp); +extern GLboolean r700SetupFragmentProgram(GLcontext * ctx); + +#endif /*_R700_FRAGPROG_H_*/ diff --git a/src/mesa/drivers/dri/r600/r700_ioctl.c b/src/mesa/drivers/dri/r600/r700_ioctl.c new file mode 100644 index 0000000000..0541dc76e4 --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_ioctl.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + */ + +#include +#include + +#include "main/glheader.h" +#include "main/imports.h" +#include "main/macros.h" +#include "main/context.h" +#include "swrast/swrast.h" + +#include "radeon_common.h" +#include "radeon_lock.h" +#include "r600_context.h" + +#include "r700_ioctl.h" +#include "r700_clear.h" + +void r700InitIoctlFuncs(struct dd_function_table *functions) +{ + functions->Clear = r700Clear; + functions->Finish = radeonFinish; + functions->Flush = radeonFlush; +} diff --git a/src/mesa/drivers/dri/r600/r700_ioctl.h b/src/mesa/drivers/dri/r600/r700_ioctl.h new file mode 100644 index 0000000000..414dc3e23e --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_ioctl.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + */ + +#ifndef __R700_IOCTL_H__ +#define __R700_IOCTL_H__ + +#include "r600_context.h" +#include "radeon_drm.h" + +extern void r700InitIoctlFuncs(struct dd_function_table *functions); + +#endif /* __R700_IOCTL_H__ */ diff --git a/src/mesa/drivers/dri/r600/r700_oglprog.c b/src/mesa/drivers/dri/r600/r700_oglprog.c new file mode 100644 index 0000000000..ee6377632b --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_oglprog.c @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + */ + +#include + +#include "main/glheader.h" +#include "main/imports.h" + +#include "shader/program.h" +#include "tnl/tnl.h" + +#include "r600_context.h" + +#include "r700_chip.h" +#include "r700_oglprog.h" + +#if 0 /* to be enabled */ +#include "r700_fragprog.h" +#include "r700_vertprog.h" +#endif /* to be enabled */ + +static struct gl_program *r700NewProgram(GLcontext * ctx, + GLenum target, + GLuint id) +{ + struct gl_program *pProgram = NULL; +#if 0 /* to be enabled */ + struct r700_vertex_program *vp; + struct r700_fragment_program *fp; + + switch (target) + { + case GL_VERTEX_STATE_PROGRAM_NV: + case GL_VERTEX_PROGRAM_ARB: + vp = CALLOC_STRUCT(r700_vertex_program); + pProgram = _mesa_init_vertex_program(ctx, + &vp->mesa_program, + target, + id); + vp->translated = GL_FALSE; + vp->loaded = GL_FALSE; + vp->shadercode.buf = NULL; + break; + case GL_FRAGMENT_PROGRAM_NV: + case GL_FRAGMENT_PROGRAM_ARB: + fp = CALLOC_STRUCT(r700_fragment_program); + pProgram = _mesa_init_fragment_program(ctx, + &fp->mesa_program, + target, + id); + fp->translated = GL_FALSE; + fp->loaded = GL_FALSE; + fp->shadercode.buf = NULL; + break; + default: + _mesa_problem(ctx, "Bad target in r700NewProgram"); + } +#endif /* to be enabled */ + return pProgram; +} + +static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) +{ +#if 0 /* to be enabled */ + struct r700_vertex_program * vp; + struct r700_fragment_program * fp; + context_t *context = R700_CONTEXT(ctx); + + switch (prog->Target) + { + case GL_VERTEX_STATE_PROGRAM_NV: + case GL_VERTEX_PROGRAM_ARB: + vp = (struct r700_vertex_program*)prog; + /* Release DMA region */ + (context->chipobj.FreeDmaRegion)(context, &(vp->shadercode)); + /* Clean up */ + Clean_Up_Assembler(&(vp->r700AsmCode)); + Clean_Up_Shader(&(vp->r700Shader)); + break; + case GL_FRAGMENT_PROGRAM_NV: + case GL_FRAGMENT_PROGRAM_ARB: + fp = (struct r700_fragment_program*)prog; + /* Release DMA region */ + (context->chipobj.FreeDmaRegion)(context, &(fp->shadercode)); + /* Clean up */ + Clean_Up_Assembler(&(fp->r700AsmCode)); + Clean_Up_Shader(&(fp->r700Shader)); + break; + default: + _mesa_problem(ctx, "Bad target in r700NewProgram"); + } + + _mesa_delete_program(ctx, prog); +#endif /* to be enabled */ +} + +static void +r700ProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog) +{ + +} + +static GLboolean r700IsProgramNative(GLcontext * ctx, GLenum target, struct gl_program *prog) +{ + + return GL_TRUE; +} + +void r700InitShaderFuncs(struct dd_function_table *functions) +{ + functions->NewProgram = r700NewProgram; + functions->DeleteProgram = r700DeleteProgram; + functions->ProgramStringNotify = r700ProgramStringNotify; + functions->IsProgramNative = r700IsProgramNative; +} diff --git a/src/mesa/drivers/dri/r600/r700_oglprog.h b/src/mesa/drivers/dri/r600/r700_oglprog.h new file mode 100644 index 0000000000..fe2e9d1974 --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_oglprog.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + * CooperYuan , + */ + +#ifndef _R700_OGLPROG_H_ +#define _R700_OGLPROG_H_ +#include "r600_context.h" + +extern void r700InitShaderFuncs(struct dd_function_table *functions); + +#endif /*_R700_OGLPROG_H_*/ diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c new file mode 100644 index 0000000000..fce99ada54 --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -0,0 +1,462 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + * CooperYuan , + */ + +#include "main/glheader.h" +#include "main/state.h" +#include "main/imports.h" +#include "main/enums.h" +#include "main/macros.h" +#include "main/context.h" +#include "main/dd.h" +#include "main/simple_list.h" +#include "main/api_arrayelt.h" +#include "swrast/swrast.h" +#include "swrast_setup/swrast_setup.h" +#include "vbo/vbo.h" + +#include "tnl/tnl.h" +#include "tnl/t_vp_build.h" +#include "tnl/t_context.h" +#include "tnl/t_vertex.h" +#include "tnl/t_pipeline.h" + +#include "r600_context.h" + +#include "r700_chip.h" + +/* to be enable +#include "r700_vertprog.h" +#include "r700_fragprog.h" +#include "r700_state.h" +#include "r700_tex.h" +#include "r700_emit.h" +*/ + +#if 0 // to be enable +void r700WaitForIdle(context_t *context) +{ + R700EP3 (context, IT_SET_CONFIG_REG, 1); + R700E32 (context, mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); + R700E32 (context, 1 << 15); +} + +void r700WaitForIdleClean(context_t *context) +{ + R700EP3 (context, IT_EVENT_WRITE, 0); + R700E32 (context, 0x16); + + R700EP3 (context, IT_SET_CONFIG_REG, 1); + R700E32 (context, mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); + R700E32 (context, 1 << 17); +} + +static void r700Start3D(context_t *context) +{ + if (context->screen->chip.type <= CHIP_TYPE_RV670) + { + R700EP3 (context, IT_START_3D_CMDBUF, 1); + R700E32 (context, 0); + } + + R700EP3 (context, IT_CONTEXT_CONTROL, 1); + R700E32 (context, 0x80000000); + R700E32 (context, 0x80000000); + r700WaitForIdleClean(context); +} + + +static int r700SetupStreams(GLcontext * ctx) +{ + context_t *context = R700_CONTEXT(ctx); + + struct r700_vertex_program *vpc + = (struct r700_vertex_program *)ctx->VertexProgram._Current; + + TNLcontext *tnl = TNL_CONTEXT(ctx); + struct vertex_buffer *vb = &tnl->vb; + + unsigned int unBit; + unsigned int i; + + R700_CMDBUF_CHECK_SPACE(6); + R700EP3 (context, IT_SET_CTL_CONST, 1); + R700E32 (context, mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); + R700E32 (context, 0); + + R700EP3 (context, IT_SET_CTL_CONST, 1); + R700E32 (context, mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX); + R700E32 (context, 0); + + context->aos_count = 0; + for(i=0; imesa_program.Base.InputsRead & unBit) + { + (context->chipobj.EmitVec)(ctx, + &(context->aos[context->aos_count]), + vb->AttribPtr[i]->data, + vb->AttribPtr[i]->size, + vb->AttribPtr[i]->stride, + vb->Count); + + context->aos[context->aos_count].aos_size = vb->AttribPtr[i]->size; + + /* currently aos are packed */ + r700SetupVTXConstans(ctx, + i, + (unsigned int)context->aos[context->aos_count].aos_offset, + (unsigned int)vb->AttribPtr[i]->size, + (unsigned int)(vb->AttribPtr[i]->size * 4), + (unsigned int)vb->Count); + /* TODO : enable this after MemUse fixed *= + (context->chipobj.MemUse)(context, context->aos[context->aos_count].buf->id); + */ + + context->aos_count++; + } + } + for(i=context->aos_count; iaos[i].buf = NULL; + } + + return R600_FALLBACK_NONE; +} + +static GLboolean r700SetupShaders(GLcontext * ctx) +{ + context_t *context = R700_CONTEXT(ctx); + + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + + GLuint exportCount; + + r700->SQ_PGM_RESOURCES_PS.u32All = 0; + r700->SQ_PGM_RESOURCES_VS.u32All = 0; + + SETbit(r700->SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); + SETbit(r700->SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); + + r700SetupVertexProgram(ctx); + + r700SetupFragmentProgram(ctx); + + exportCount = (r700->SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift); + r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1; + + return GL_TRUE; +} + +GLboolean r700SendTextureState(context_t *context) +{ + unsigned int i; + + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + + for(i=0; itexture_states.textures[i] != 0) + { + R700_CMDBUF_CHECK_SPACE(9); + R700EP3 (context, IT_SET_RESOURCE, 7); + R700E32 (context, i * 7); + R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE0.u32All); + R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE1.u32All); + R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE2.u32All); + R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE3.u32All); + R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE4.u32All); + R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE5.u32All); + R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE6.u32All); + } + + if(r700->texture_states.samplers[i] != 0) + { + R700_CMDBUF_CHECK_SPACE(5); + R700EP3 (context, IT_SET_SAMPLER, 3); + R700E32 (context, i * 3); // Base at 0x7000 + R700E32 (context, r700->texture_states.samplers[i]->SQ_TEX_SAMPLER0.u32All); + R700E32 (context, r700->texture_states.samplers[i]->SQ_TEX_SAMPLER1.u32All); + R700E32 (context, r700->texture_states.samplers[i]->SQ_TEX_SAMPLER2.u32All); + } + } + + return GL_TRUE; +} + +GLboolean r700SyncSurf(context_t *context) +{ + /* TODO : too heavy? */ + unsigned int CP_COHER_CNTL = 0; + + CP_COHER_CNTL |= TC_ACTION_ENA_bit + |VC_ACTION_ENA_bit + |CB_ACTION_ENA_bit + |DB_ACTION_ENA_bit + |SH_ACTION_ENA_bit + |SMX_ACTION_ENA_bit; + + + R700_CMDBUF_CHECK_SPACE(5); + R700EP3(context, IT_SURFACE_SYNC, 3); + R700E32(context, CP_COHER_CNTL); + R700E32(context, 0xFFFFFFFF); + R700E32(context, 0x00000000); + R700E32(context, 10); + + return GL_TRUE; +} + +static void r700SetRenderTarget(context_t *context) +{ + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + + r700->CB_COLOR0_BASE.u32All = context->target.rt.gpu >> 8; +} + +unsigned int r700PrimitiveType(int prim) +{ + switch (prim & PRIM_MODE_MASK) + { + case GL_POINTS: + return DI_PT_POINTLIST; + break; + case GL_LINES: + return DI_PT_LINELIST; + break; + case GL_LINE_STRIP: + return DI_PT_LINESTRIP; + break; + case GL_LINE_LOOP: + return DI_PT_LINELOOP; + break; + case GL_TRIANGLES: + return DI_PT_TRILIST; + break; + case GL_TRIANGLE_STRIP: + return DI_PT_TRISTRIP; + break; + case GL_TRIANGLE_FAN: + return DI_PT_TRIFAN; + break; + case GL_QUADS: + return DI_PT_QUADLIST; + break; + case GL_QUAD_STRIP: + return DI_PT_QUADSTRIP; + break; + case GL_POLYGON: + return DI_PT_POLYGON; + break; + default: + assert(0); + return -1; + break; + } +} + +#endif // to be enable + +static GLboolean r700RunRender(GLcontext * ctx, + struct tnl_pipeline_stage *stage) +{ +#if 0 // to be enable + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + unsigned int i, j; + TNLcontext *tnl = TNL_CONTEXT(ctx); + struct vertex_buffer *vb = &tnl->vb; + + struct r700_fragment_program *fp = (struct r700_fragment_program *) + (ctx->FragmentProgram._Current); + if (context->screen->chip.type <= CHIP_TYPE_RV670) + { + fp->r700AsmCode.bR6xx = 1; + } + + r700Start3D(context); /* TODO : this is too much. */ + + r700SyncSurf(context); /* TODO : make it light. */ + + r700UpdateShaders(ctx); + + r700SetRenderTarget(context); + + if(r700SetupStreams(ctx)) + { + return GL_TRUE; + } + + r700UpdateTextureState(context); + r700SendTextureState(context); + + if(GL_FALSE == fp->translated) + { + if( GL_FALSE == r700TranslateFragmentShader(fp, &(fp->mesa_program)) ) + { + return GL_TRUE; + } + } + + r700SetupShaders(ctx); + + /* set a valid base address to make the command checker happy */ + r700->SQ_PGM_START_FS.u32All = r700->SQ_PGM_START_PS.u32All; + r700->SQ_PGM_START_ES.u32All = r700->SQ_PGM_START_PS.u32All; + r700->SQ_PGM_START_GS.u32All = r700->SQ_PGM_START_PS.u32All; + + r700SendContextStates(context); + + /* richard test code */ + for (i = 0; i < vb->PrimitiveCount; i++) + { + GLuint prim = _tnl_translate_prim(&vb->Primitive[i]); + GLuint start = vb->Primitive[i].start; + GLuint end = vb->Primitive[i].start + vb->Primitive[i].count; + GLuint numIndices = vb->Primitive[i].count; + GLuint numEntires; + //r300RunRenderPrimitive(rmesa, ctx, start, end, prim); + + unsigned int VGT_DRAW_INITIATOR = 0; + unsigned int VGT_INDEX_TYPE = 0; + unsigned int VGT_PRIMITIVE_TYPE = 0; + unsigned int VGT_NUM_INDICES = 0; + + numEntires = 2 /* VGT_INDEX_TYPE */ + + 3 /* VGT_PRIMITIVE_TYPE */ + + numIndices + 3 /* DRAW_INDEX_IMMD */ + + 2; /* test stamp */ + + R700_CMDBUF_CHECK_SPACE(numEntires); + + VGT_INDEX_TYPE |= DI_INDEX_SIZE_32_BIT << INDEX_TYPE_shift; + + R700EP3(context, IT_INDEX_TYPE, 0); + R700E32(context, VGT_INDEX_TYPE); + + VGT_NUM_INDICES = numIndices; + + VGT_PRIMITIVE_TYPE |= r700PrimitiveType(prim) << VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift; + R700EP3(context, IT_SET_CONFIG_REG, 1); + R700E32(context, mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); + R700E32(context, VGT_PRIMITIVE_TYPE); + + VGT_DRAW_INITIATOR |= DI_SRC_SEL_IMMEDIATE << SOURCE_SELECT_shift; + VGT_DRAW_INITIATOR |= DI_MAJOR_MODE_0 << MAJOR_MODE_shift; + + R700EP3(context, IT_DRAW_INDEX_IMMD, (numIndices + 1)); + R700E32(context, VGT_NUM_INDICES); + R700E32(context, VGT_DRAW_INITIATOR); + + for (j=0; jchipobj.FlushCmdBuffer)(context); + + /* free aos => TODO : cache mgr */ + for (i = 0; i < context->aos_count; i++) + { + (context->chipobj.FreeDmaRegion)(context, &(context->aos[i])); + } +#endif // to be enable + return GL_FALSE; +} + +static GLboolean r700RunNonTCLRender(GLcontext * ctx, + struct tnl_pipeline_stage *stage) /* -------------------- */ +{ + GLboolean bRet = GL_TRUE; + + return bRet; +} + +static GLboolean r700RunTCLRender(GLcontext * ctx, /*----------------------*/ + struct tnl_pipeline_stage *stage) +{ + GLboolean bRet = GL_FALSE; + +#if 0 // to be enable + context_t *context = R700_CONTEXT(ctx); + + r700UpdateShaders(ctx); +#endif // to be enable + + bRet = r700RunRender(ctx, stage); + + return bRet; + //GL_FALSE will stop to do other pipe stage in _tnl_run_pipeline + //The render here DOES finish the whole pipe, so GL_FALSE should be returned for success. +} + +const struct tnl_pipeline_stage _r700_render_stage = { + "r700 Hardware Rasterization", + NULL, + NULL, + NULL, + NULL, + r700RunNonTCLRender +}; + +const struct tnl_pipeline_stage _r700_tcl_stage = { + "r700 Hardware Transform, Clipping and Lighting", + NULL, + NULL, + NULL, + NULL, + r700RunTCLRender +}; + +const struct tnl_pipeline_stage *r700_pipeline[] = +{ + &_r700_tcl_stage, + &_tnl_vertex_transform_stage, + &_tnl_normal_transform_stage, + &_tnl_lighting_stage, + &_tnl_fog_coordinate_stage, + &_tnl_texgen_stage, + &_tnl_texture_transform_stage, + &_tnl_vertex_program_stage, + + &_r700_render_stage, + &_tnl_render_stage, + 0, +}; + + diff --git a/src/mesa/drivers/dri/r600/r700_shader.c b/src/mesa/drivers/dri/r600/r700_shader.c new file mode 100644 index 0000000000..446f9f959b --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_shader.c @@ -0,0 +1,528 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + */ + +#include +#include +#include +#include +#include + +#include "main/imports.h" + +#include "main/glheader.h" + +#include "r600_context.h" +#include "r700_chip.h" +#include "r700_debug.h" + +#include "r700_shader.h" + +void r700ShaderInit(GLcontext * ctx) +{ +} + +void AddInstToList(TypedShaderList * plstCFInstructions, R700ShaderInstruction * pInst) +{ + if(NULL == plstCFInstructions->pTail) + { //first + plstCFInstructions->pHead = pInst; + plstCFInstructions->pTail = pInst; + } + else + { + plstCFInstructions->pTail->pNextInst = pInst; + plstCFInstructions->pTail = pInst; + } + pInst->pNextInst = NULL; + + plstCFInstructions->uNumOfNode++; +} + +void Init_R700_Shader(R700_Shader * pShader) +{ + pShader->Type = R700_SHADER_INVALID; + pShader->pProgram = NULL; + pShader->bBinaryShader = GL_FALSE; + pShader->bFetchShaderRequired = GL_FALSE; + pShader->bNeedsAssembly = GL_FALSE; + pShader->bLinksDirty = GL_TRUE; + pShader->uShaderBinaryDWORDSize = 0; + pShader->nRegs = 0; + pShader->nParamExports = 0; + pShader->nMemExports = 0; + pShader->resource = 0; + + pShader->exportMode = 0; + pShader->depthIsImported = GL_FALSE; + + pShader->positionVectorIsExported = GL_FALSE; + pShader->miscVectorIsExported = GL_FALSE; + pShader->renderTargetArrayIndexIsExported = GL_FALSE; + pShader->ccDist0VectorIsExported = GL_FALSE; + pShader->ccDist1VectorIsExported = GL_FALSE; + + + pShader->depthIsExported = GL_FALSE; + pShader->stencilRefIsExported = GL_FALSE; + pShader->coverageToMaskIsExported = GL_FALSE; + pShader->maskIsExported = GL_FALSE; + pShader->killIsUsed = GL_FALSE; + + pShader->uCFOffset = 0; + pShader->uStackSize = 0; + pShader->uMaxCallDepth = 0; + + pShader->bSurfAllocated = GL_FALSE; + + pShader->lstCFInstructions.pHead=NULL; + pShader->lstCFInstructions.pTail=NULL; + pShader->lstCFInstructions.uNumOfNode=0; + pShader->lstALUInstructions.pHead=NULL; + pShader->lstALUInstructions.pTail=NULL; + pShader->lstALUInstructions.uNumOfNode=0; + pShader->lstTEXInstructions.pHead=NULL; + pShader->lstTEXInstructions.pTail=NULL; + pShader->lstTEXInstructions.uNumOfNode=0; + pShader->lstVTXInstructions.pHead=NULL; + pShader->lstVTXInstructions.pTail=NULL; + pShader->lstVTXInstructions.uNumOfNode=0; +} + +void AddCFInstruction(R700_Shader *pShader, R700ControlFlowInstruction *pCFInst) +{ + R700ControlFlowSXClause* pSXClause; + R700ControlFlowSMXClause* pSMXClause; + + pCFInst->m_uIndex = pShader->lstCFInstructions.uNumOfNode; + AddInstToList(&(pShader->lstCFInstructions), + (R700ShaderInstruction*)pCFInst); + pShader->uShaderBinaryDWORDSize += GetInstructionSize(pCFInst->m_ShaderInstType); + + pSXClause = NULL; + pSMXClause = NULL; + switch (pCFInst->m_ShaderInstType) + { + case SIT_CF_ALL_EXP_SX: + pSXClause = (R700ControlFlowSXClause*)pCFInst; + break; + case SIT_CF_ALL_EXP_SMX: + pSMXClause = (R700ControlFlowSMXClause*)pCFInst; + break; + default: + break; + }; + + if((pSXClause != NULL) && (pSXClause->m_Word0.f.type == SQ_EXPORT_PARAM)) + { + pShader->nParamExports += pSXClause->m_Word1.f.burst_count + 1; + } + else if ((pSMXClause != NULL) && (pSMXClause->m_Word1.f.cf_inst == SQ_CF_INST_MEM_RING) && + (pSMXClause->m_Word0.f.type == SQ_EXPORT_WRITE || pSMXClause->m_Word0.f.type == SQ_EXPORT_WRITE_IND)) + { + pShader->nMemExports += pSMXClause->m_Word1.f.burst_count + 1; + } + + pShader->bLinksDirty = GL_TRUE; + pShader->bNeedsAssembly = GL_TRUE; + + pCFInst->useCount++; +} + +void AddVTXInstruction(R700_Shader *pShader, R700VertexInstruction *pVTXInst) +{ + pVTXInst->m_uIndex = pShader->lstVTXInstructions.uNumOfNode; + AddInstToList(&(pShader->lstVTXInstructions), + (R700ShaderInstruction*)pVTXInst); + pShader->uShaderBinaryDWORDSize += GetInstructionSize(pVTXInst->m_ShaderInstType); + + if(pVTXInst->m_ShaderInstType == SIT_VTX_GENERIC) + { + R700VertexGenericFetch* pVTXGenericClause = (R700VertexGenericFetch*)pVTXInst; + pShader->nRegs = (pShader->nRegs < pVTXGenericClause->m_Word1_GPR.f.dst_gpr) ? pVTXGenericClause->m_Word1_GPR.f.dst_gpr : pShader->nRegs; + } + + pShader->bLinksDirty = GL_TRUE; + pShader->bNeedsAssembly = GL_TRUE; + + pVTXInst->useCount++; +} + +void AddTEXInstruction(R700_Shader *pShader, R700TextureInstruction *pTEXInst) +{ + pTEXInst->m_uIndex = pShader->lstTEXInstructions.uNumOfNode; + AddInstToList(&(pShader->lstTEXInstructions), + (R700ShaderInstruction*)pTEXInst); + pShader->uShaderBinaryDWORDSize += GetInstructionSize(pTEXInst->m_ShaderInstType); + + pShader->nRegs = (pShader->nRegs < pTEXInst->m_Word1.f.dst_gpr) ? pTEXInst->m_Word1.f.dst_gpr : pShader->nRegs; + + pShader->bLinksDirty = GL_TRUE; + pShader->bNeedsAssembly = GL_TRUE; + + pTEXInst->useCount++; +} + +void AddALUInstruction(R700_Shader *pShader, R700ALUInstruction *pALUInst) +{ + pALUInst->m_uIndex = pShader->lstALUInstructions.uNumOfNode; + AddInstToList(&(pShader->lstALUInstructions), + (R700ShaderInstruction*)pALUInst); + pShader->uShaderBinaryDWORDSize += GetInstructionSize(pALUInst->m_ShaderInstType); + + pShader->nRegs = (pShader->nRegs < pALUInst->m_Word1.f.dst_gpr) ? pALUInst->m_Word1.f.dst_gpr : pShader->nRegs; + + pShader->bLinksDirty = GL_TRUE; + pShader->bNeedsAssembly = GL_TRUE; + + pALUInst->useCount++; +} + +void ResolveLinks(R700_Shader *pShader) +{ + GLuint uiSize; + R700ShaderInstruction *pInst; + R700ALUInstruction *pALUinst; + R700TextureInstruction *pTEXinst; + R700VertexInstruction *pVTXinst; + + GLuint vtxOffset; + + GLuint cfOffset = 0x0; + + GLuint aluOffset = cfOffset + pShader->lstCFInstructions.uNumOfNode * GetInstructionSize(SIT_CF); + + GLuint texOffset = aluOffset; // + m_lstALUInstructions.size() * R700ALUInstruction::SIZE, + + pInst = pShader->lstALUInstructions.pHead; + while(NULL != pInst) + { + texOffset += GetInstructionSize(pInst->m_ShaderInstType); + + pInst = pInst->pNextInst; + }; + + vtxOffset = texOffset + pShader->lstTEXInstructions.uNumOfNode * GetInstructionSize(SIT_TEX); + + if ( ((pShader->lstTEXInstructions.uNumOfNode > 0) && (texOffset % 4 != 0)) || + ((pShader->lstVTXInstructions.uNumOfNode > 0) && (vtxOffset % 4 != 0)) ) + { + pALUinst = (R700ALUInstruction*) CALLOC_STRUCT(R700ALUInstruction); + Init_R700ALUInstruction(pALUinst); + AddALUInstruction(pShader, pALUinst); + texOffset += GetInstructionSize(SIT_ALU); + vtxOffset += GetInstructionSize(SIT_ALU); + } + + pInst = pShader->lstALUInstructions.pHead; + uiSize = 0; + while(NULL != pInst) + { + pALUinst = (R700ALUInstruction*)pInst; + + if(pALUinst->m_pLinkedALUClause != NULL) + { + // This address is quad-word aligned + pALUinst->m_pLinkedALUClause->m_Word0.f.addr = (aluOffset + uiSize) >> 1; + } + + uiSize += GetInstructionSize(pALUinst->m_ShaderInstType); + + pInst = pInst->pNextInst; + }; + + pInst = pShader->lstTEXInstructions.pHead; + uiSize = 0; + while(NULL != pInst) + { + pTEXinst = (R700TextureInstruction*)pInst; + + if (pTEXinst->m_pLinkedGenericClause != NULL) + { + pTEXinst->m_pLinkedGenericClause->m_Word0.f.addr = (texOffset + uiSize) >> 1; + } + + uiSize += GetInstructionSize(pTEXinst->m_ShaderInstType); + + pInst = pInst->pNextInst; + }; + + pInst = pShader->lstVTXInstructions.pHead; + uiSize = 0; + while(NULL != pInst) + { + pVTXinst = (R700VertexInstruction*)pInst; + + if (pVTXinst->m_pLinkedGenericClause != NULL) + { + pVTXinst->m_pLinkedGenericClause->m_Word0.f.addr = (vtxOffset + uiSize) >> 1; + } + + uiSize += GetInstructionSize(pVTXinst->m_ShaderInstType); + + pInst = pInst->pNextInst; + }; + + pShader->bLinksDirty = GL_FALSE; +} + +void Assemble(R700_Shader *pShader) +{ + GLuint i; + GLuint *pShaderBinary; + GLuint size_of_program; + GLuint *pCurrPos; + + GLuint end_of_cf_instructions; + GLuint number_of_alu_dwords; + + R700ShaderInstruction *pInst; + + if(GL_TRUE == pShader->bBinaryShader) + { + return; + } + + if(pShader->bLinksDirty == GL_TRUE) + { + ResolveLinks(pShader); + } + + size_of_program = pShader->uShaderBinaryDWORDSize; + + pShaderBinary = (GLuint*) MALLOC(sizeof(GLuint)*size_of_program); + + pCurrPos = pShaderBinary; + + for (i = 0; i < size_of_program; i++) + { + pShaderBinary[i] = 0; + } + + pInst = pShader->lstCFInstructions.pHead; + while(NULL != pInst) + { + switch (pInst->m_ShaderInstType) + { + case SIT_CF_GENERIC: + { + R700ControlFlowGenericClause* pCFgeneric = (R700ControlFlowGenericClause*)pInst; + *pCurrPos++ = pCFgeneric->m_Word0.val; + *pCurrPos++ = pCFgeneric->m_Word1.val; + } + break; + case SIT_CF_ALU: + { + R700ControlFlowALUClause* pCFalu = (R700ControlFlowALUClause*)pInst; + *pCurrPos++ = pCFalu->m_Word0.val; + *pCurrPos++ = pCFalu->m_Word1.val; + } + break; + case SIT_CF_ALL_EXP_SX: + { + R700ControlFlowSXClause* pCFsx = (R700ControlFlowSXClause*)pInst; + *pCurrPos++ = pCFsx->m_Word0.val; + *pCurrPos++ = (pCFsx->m_Word1.val | pCFsx->m_Word1_SWIZ.val); + } + break; + case SIT_CF_ALL_EXP_SMX: + { + R700ControlFlowSMXClause* pCFsmx = (R700ControlFlowSMXClause*)pInst; + *pCurrPos++ = pCFsmx->m_Word0.val; + *pCurrPos++ = (pCFsmx->m_Word1.val | pCFsmx->m_Word1_BUF.val); + } + break; + default: + break; + } + + pInst = pInst->pNextInst; + }; + + number_of_alu_dwords = 0; + pInst = pShader->lstALUInstructions.pHead; + while(NULL != pInst) + { + switch (pInst->m_ShaderInstType) + { + case SIT_ALU: + { + R700ALUInstruction* pALU = (R700ALUInstruction*)pInst; + + *pCurrPos++ = pALU->m_Word0.val; + *pCurrPos++ = (pALU->m_Word1.val | pALU->m_Word1_OP2.val | pALU->m_Word1_OP3.val); + + number_of_alu_dwords += 2; + } + break; + case SIT_ALU_HALF_LIT: + { + R700ALUInstructionHalfLiteral* pALUhalf = (R700ALUInstructionHalfLiteral*)pInst; + + *pCurrPos++ = pALUhalf->m_Word0.val; + *pCurrPos++ = (pALUhalf->m_Word1.val | pALUhalf->m_Word1_OP2.val | pALUhalf->m_Word1_OP3.val); + *pCurrPos++ = *((GLuint*)&(pALUhalf->m_fLiteralX)); + *pCurrPos++ = *((GLuint*)&(pALUhalf->m_fLiteralY)); + + number_of_alu_dwords += 4; + } + break; + case SIT_ALU_FALL_LIT: + { + R700ALUInstructionFullLiteral* pALUfull = (R700ALUInstructionFullLiteral*)pInst; + + *pCurrPos++ = pALUfull->m_Word0.val; + *pCurrPos++ = (pALUfull->m_Word1.val | pALUfull->m_Word1_OP2.val | pALUfull->m_Word1_OP3.val); + + *pCurrPos++ = *((GLuint*)&(pALUfull->m_fLiteralX)); + *pCurrPos++ = *((GLuint*)&(pALUfull->m_fLiteralY)); + *pCurrPos++ = *((GLuint*)&(pALUfull->m_fLiteralZ)); + *pCurrPos++ = *((GLuint*)&(pALUfull->m_fLiteralW)); + + number_of_alu_dwords += 6; + } + break; + default: + break; + } + + pInst = pInst->pNextInst; + }; + + pInst = pShader->lstTEXInstructions.pHead; + while(NULL != pInst) + { + R700TextureInstruction* pTEX = (R700TextureInstruction*)pInst; + + *pCurrPos++ = pTEX->m_Word0.val; + *pCurrPos++ = pTEX->m_Word1.val; + *pCurrPos++ = pTEX->m_Word2.val; + *pCurrPos++ = 0x0beadeaf; + + pInst = pInst->pNextInst; + }; + + pInst = pShader->lstVTXInstructions.pHead; + while(NULL != pInst) + { + switch (pInst->m_ShaderInstType) + { + case SIT_VTX_SEM: // + { + R700VertexSemanticFetch* pVTXsem = (R700VertexSemanticFetch*)pInst; + + *pCurrPos++ = pVTXsem->m_Word0.val; + *pCurrPos++ = (pVTXsem->m_Word1.val | pVTXsem->m_Word1_SEM.val); + *pCurrPos++ = pVTXsem->m_Word2.val; + *pCurrPos++ = 0x0beadeaf; + } + break; + case SIT_VTX_GENERIC: // + { + R700VertexGenericFetch* pVTXgeneric = (R700VertexGenericFetch*)pInst; + + *pCurrPos++ = pVTXgeneric->m_Word0.val; + *pCurrPos++ = (pVTXgeneric->m_Word1.val | pVTXgeneric->m_Word1_GPR.val); + *pCurrPos++ = pVTXgeneric->m_Word2.val; + *pCurrPos++ = 0x0beadeaf; + } + break; + default: + break; + } + + pInst = pInst->pNextInst; + }; + + if(NULL != pShader->pProgram) + { + FREE(pShader->pProgram); + } + pShader->pProgram = (GLubyte*)pShaderBinary; + + end_of_cf_instructions = pShader->uCFOffset + pShader->lstCFInstructions.uNumOfNode * GetInstructionSize(SIT_CF); + + pShader->uEndOfCF = end_of_cf_instructions >> 1; + + pShader->uEndOfALU = (end_of_cf_instructions + number_of_alu_dwords) >> 1; + + pShader->uEndOfFetch = (pShader->uCFOffset + pShader->uShaderBinaryDWORDSize) >> 1; + + pShader->bNeedsAssembly = GL_FALSE; +} + +void LoadProgram(R700_Shader *pShader) //context +{ +} + +void UpdateShaderRegisters(R700_Shader *pShader) //context +{ +} + +void DeleteInstructions(R700_Shader *pShader) +{ +} + +void DebugPrint(void) +{ +} + +void Clean_Up_Shader(R700_Shader *pShader) +{ + FREE(pShader->pProgram); + + R700ShaderInstruction *pInst; + R700ShaderInstruction *pInstToFree; + + pInst = pShader->lstCFInstructions.pHead; + while(NULL != pInst) + { + pInstToFree = pInst; + pInst = pInst->pNextInst; + FREE(pInstToFree); + }; + pInst = pShader->lstALUInstructions.pHead; + while(NULL != pInst) + { + pInstToFree = pInst; + pInst = pInst->pNextInst; + FREE(pInstToFree); + }; + pInst = pShader->lstTEXInstructions.pHead; + while(NULL != pInst) + { + pInstToFree = pInst; + pInst = pInst->pNextInst; + FREE(pInstToFree); + }; + pInst = pShader->lstVTXInstructions.pHead; + while(NULL != pInst) + { + pInstToFree = pInst; + pInst = pInst->pNextInst; + FREE(pInstToFree); + }; +} + diff --git a/src/mesa/drivers/dri/r600/r700_shader.h b/src/mesa/drivers/dri/r600/r700_shader.h new file mode 100644 index 0000000000..bfd01e1a93 --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_shader.h @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + */ + + +#ifndef __R700_SHADER_H__ +#define __R700_SHADER_H__ + +#include "main/mtypes.h" + +#include "r700_shaderinst.h" + + +void r700ShaderInit(GLcontext * ctx); + +typedef enum R700ShaderType +{ + R700_SHADER_FS = 0x0, + R700_SHADER_ES = 0x1, + R700_SHADER_GS = 0x2, + R700_SHADER_VS = 0x3, + R700_SHADER_PS = 0x4, + R700_SHADER_INVALID = 0x5, +} R700ShaderType; + +typedef struct TypedShaderList +{ + R700ShaderInstruction * pHead; + R700ShaderInstruction * pTail; + GLuint uNumOfNode; +} TypedShaderList; + +typedef struct RealRegister +{ + GLuint uAddr; + GLuint uValue; +} RealRegister; + +typedef struct InstDeps +{ + GLint nDstDep; + GLint nSrcDeps[3]; +} InstDeps; + +typedef struct R700_Shader +{ + R700ShaderType Type; + + GLubyte* pProgram; + + GLboolean bBinaryShader; + GLboolean bFetchShaderRequired; + GLboolean bNeedsAssembly; + GLboolean bLinksDirty; + + GLuint uShaderBinaryDWORDSize; // in DWORDS + GLuint nRegs; + GLuint nParamExports; // VS_ EXPORT_COUNT (1 based, the actual register is 0 based!) + GLuint nMemExports; + GLuint resource; // VS and PS _RESOURCE + GLuint exportMode; // VS and PS _EXPORT_MODE + + GLboolean depthIsImported; + + // Vertex program exports + GLboolean positionVectorIsExported; + + GLboolean miscVectorIsExported; + GLboolean renderTargetArrayIndexIsExported; + + GLboolean ccDist0VectorIsExported; + GLboolean ccDist1VectorIsExported; + + // Pixel program exports + GLboolean depthIsExported; + GLboolean stencilRefIsExported; + GLboolean coverageToMaskIsExported; + GLboolean maskIsExported; + + GLboolean killIsUsed; + + GLuint uStartAddr; + GLuint uCFOffset; + GLuint uEndOfCF; + GLuint uEndOfALU; + GLuint uEndOfFetch; + GLuint uStackSize; + GLuint uMaxCallDepth; + + TypedShaderList lstCFInstructions; + TypedShaderList lstALUInstructions; + TypedShaderList lstTEXInstructions; + TypedShaderList lstVTXInstructions; + + RealRegister RegStartAddr; + RealRegister RegCFOffset; + RealRegister RegEndCF; + RealRegister RegEndALU; + RealRegister egEndFetcg; + + // -------- constants + GLfloat ConstantArray[SQ_ALU_CONSTANT_PS_COUNT * 4]; + + GLboolean bSurfAllocated; +} R700_Shader; + +//Internal +void AddInstToList(TypedShaderList * plstCFInstructions, R700ShaderInstruction * pInst); +void ResolveLinks(R700_Shader *pShader); +void Assemble(R700_Shader *pShader); + + +//Interface +void Init_R700_Shader(R700_Shader * pShader); +void AddCFInstruction(R700_Shader *pShader, R700ControlFlowInstruction *pCFInst); +void AddVTXInstruction(R700_Shader *pShader, R700VertexInstruction *pVTXInst); +void AddTEXInstruction(R700_Shader *pShader, R700TextureInstruction *pTEXInst); +void AddALUInstruction(R700_Shader *pShader, R700ALUInstruction *pALUInst); + +void LoadProgram(R700_Shader *pShader); +void UpdateShaderRegisters(R700_Shader *pShader); +void DeleteInstructions(R700_Shader *pShader); +void DebugPrint(void); + +void Clean_Up_Shader(R700_Shader *pShader); + +#endif /*__R700_SHADER_H__*/ + diff --git a/src/mesa/drivers/dri/r600/r700_shaderinst.c b/src/mesa/drivers/dri/r600/r700_shaderinst.c new file mode 100644 index 0000000000..c1bffee91f --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_shaderinst.c @@ -0,0 +1,224 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + */ + + +#include "main/mtypes.h" + +#include "r700_debug.h" +#include "r700_shaderinst.h" + +void Init_R700ControlFlowGenericClause(R700ControlFlowGenericClause* pInst) +{ + pInst->m_Word0.val = 0x00000000; + pInst->m_Word1.val = 0x00000000; + + pInst->m_pLinkedVTXInstruction = 0; + pInst->m_pLinkedTEXInstruction = 0; + + pInst->useCount = 0; + + pInst->m_ShaderInstType = SIT_CF_GENERIC; +} + +void Init_R700ControlFlowALUClause(R700ControlFlowALUClause* pInst) +{ + pInst->m_Word0.val = 0x00000000; + pInst->m_Word1.val = 0x00000000; + + pInst->m_pLinkedALUInstruction = 0; + + pInst->useCount = 0; + + pInst->m_ShaderInstType = SIT_CF_ALU; +} + +void Init_R700ControlFlowSXClause(R700ControlFlowSXClause* pInst) +{ + pInst->m_Word0.val = 0x00000000; + pInst->m_Word1.val = 0x00000000; + pInst->m_Word1_SWIZ.val = 0x00000000; + + pInst->useCount = 0; + + pInst->m_ShaderInstType = SIT_CF_ALL_EXP_SX; +} + +void Init_R700ControlFlowSMXClause(R700ControlFlowSMXClause* pInst) +{ + pInst->m_Word0.val = 0x00000000; + pInst->m_Word1.val = 0x00000000; + pInst->m_Word1_BUF.val = 0x00000000; + + pInst->useCount = 0; + + pInst->m_ShaderInstType = SIT_CF_ALL_EXP_SMX; +} + +void Init_R700ALUInstruction(R700ALUInstruction* pInst) +{ + pInst->m_Word0.val = 0x00000000; + pInst->m_Word1.val = 0x00000000; + pInst->m_Word1_OP2.val = 0x00000000; + pInst->m_Word1_OP3.val = 0x00000000; + + pInst->m_pLinkedALUClause = 0; + + pInst->useCount = 0; + + pInst->m_ShaderInstType = SIT_ALU; +} + +void Init_R700ALUInstructionHalfLiteral(R700ALUInstructionHalfLiteral* pInst, GLfloat x, GLfloat y) +{ + pInst->m_Word0.val = 0x00000000; + pInst->m_Word1.val = 0x00000000; + pInst->m_Word1_OP2.val = 0x00000000; + pInst->m_Word1_OP3.val = 0x00000000; + + pInst->m_pLinkedALUClause = 0; + + pInst->m_fLiteralX = x; + pInst->m_fLiteralY = y; + + pInst->useCount = 0; + + pInst->m_ShaderInstType = SIT_ALU_HALF_LIT; +} + +void Init_R700ALUInstructionFullLiteral(R700ALUInstructionFullLiteral* pInst, GLfloat x, GLfloat y, GLfloat z, GLfloat w) +{ + pInst->m_Word0.val = 0x00000000; + pInst->m_Word1.val = 0x00000000; + pInst->m_Word1_OP2.val = 0x00000000; + pInst->m_Word1_OP3.val = 0x00000000; + + pInst->m_pLinkedALUClause = 0; + + pInst->m_fLiteralX = x; + pInst->m_fLiteralY = y; + pInst->m_fLiteralZ = z; + pInst->m_fLiteralW = w; + + pInst->useCount = 0; + + pInst->m_ShaderInstType = SIT_ALU_FALL_LIT; +} + +void Init_R700TextureInstruction(R700TextureInstruction* pInst) +{ + pInst->m_Word0.val = 0x00000000; + pInst->m_Word1.val = 0x00000000; + pInst->m_Word2.val = 0x00000000; + + pInst->m_pLinkedGenericClause = 0; + + pInst->useCount = 0; + + pInst->m_ShaderInstType = SIT_TEX; +} + +void Init_R700VertexSemanticFetch(R700VertexSemanticFetch* pInst) +{ + pInst->m_Word0.val = 0x00000000; + pInst->m_Word1.val = 0x00000000; + pInst->m_Word1_SEM.val = 0x00000000; + pInst->m_Word2.val = 0x00000000; + + pInst->m_pLinkedGenericClause = 0; + + pInst->useCount = 0; + + pInst->m_ShaderInstType = SIT_VTX_SEM; +} + +void Init_R700VertexGenericFetch(R700VertexGenericFetch* pInst) +{ + pInst->m_Word0.val = 0x00000000; + pInst->m_Word1.val = 0x00000000; + pInst->m_Word1_GPR.val = 0x00000000; + pInst->m_Word2.val = 0x00000000; + + pInst->m_pLinkedGenericClause = 0; + + pInst->useCount = 0; + + pInst->m_ShaderInstType = SIT_VTX_GENERIC; +} + +unsigned int GetInstructionSize(ShaderInstType instType) +{ + switch(instType) + { + case SIT_ALU_HALF_LIT: + case SIT_TEX: + case SIT_VTX: + case SIT_VTX_GENERIC: + case SIT_VTX_SEM: + return 4; + case SIT_ALU_FALL_LIT: + return 6; + default: + break; + } + + return 2; +} + +unsigned int GetCFMaxInstructions(ShaderInstType instType) +{ + switch (instType) + { + case SIT_CF_ALL_EXP: + case SIT_CF_ALL_EXP_SX: + case SIT_CF_ALL_EXP_SMX: + return 0x10; + case SIT_CF_GENERIC: + return 0x8; //For tex and vtx + case SIT_CF_ALU: + return 0x80; + default: + break; + } + return 0x10; +} + +GLboolean LinkVertexInstruction(R700ControlFlowGenericClause *pCFGeneric, + R700VertexInstruction *pVTXInstruction) +{ + if (pCFGeneric->m_pLinkedTEXInstruction != 0) + { + r700_error(ERROR_ASM_VTX_CLAUSE, "This instruction is already linked to a texture instruction"); + return GL_FALSE; + } + + pCFGeneric->m_pLinkedVTXInstruction = pVTXInstruction; + pVTXInstruction->m_pLinkedGenericClause = pCFGeneric; + + return GL_TRUE; +} + + + diff --git a/src/mesa/drivers/dri/r600/r700_shaderinst.h b/src/mesa/drivers/dri/r600/r700_shaderinst.h new file mode 100644 index 0000000000..2829cca0a3 --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_shaderinst.h @@ -0,0 +1,321 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + */ + + +#ifndef _R700_SHADERINST_H_ +#define _R700_SHADERINST_H_ + +#include "main/glheader.h" + +#include "defaultendian.h" +#include "sq_micro_reg.h" + +#define SQ_ALU_CONSTANT_PS_OFFSET 0x00000000 +#define SQ_ALU_CONSTANT_PS_COUNT 0x00000100 +#define SQ_ALU_CONSTANT_VS_OFFSET 0x00000100 +#define SQ_ALU_CONSTANT_VS_COUNT 0x00000100 +#define SQ_FETCH_RESOURCE_PS_OFFSET 0x00000000 +#define SQ_FETCH_RESOURCE_PS_COUNT 0x000000a0 +#define SQ_FETCH_RESOURCE_VS_OFFSET 0x000000a0 +#define SQ_FETCH_RESOURCE_VS_COUNT 0x000000b0 + +#define SHADERINST_TYPEMASK_CF 0x10 +#define SHADERINST_TYPEMASK_ALU 0x20 +#define SHADERINST_TYPEMASK_TEX 0x40 +#define SHADERINST_TYPEMASK_VTX 0x80 + +typedef enum ShaderInstType +{ + SIT_CF = 0x10, /*SIZE = 0x2*/ + SIT_CF_ALL_EXP = 0x14, /*SIZE = 0x2, MAX_INSTRUCTIONS = 0x10;*/ + SIT_CF_ALL_EXP_SX = 0x15, /*SIZE = 0x2, MAX_INSTRUCTIONS = 0x10;*/ + SIT_CF_ALL_EXP_SMX= 0x16, /*SIZE = 0x2, MAX_INSTRUCTIONS = 0x10;*/ + SIT_CF_GENERIC = 0x18, /*SIZE = 0x2, MAX_INSTRUCTIONS = 0x8; //For tex and vtx*/ + SIT_CF_ALU = 0x19, /*SIZE = 0x2, MAX_INSTRUCTIONS = 0x80;*/ + SIT_ALU = 0x20, /*SIZE = 0x2,*/ + SIT_ALU_HALF_LIT = 0x21, /*SIZE = 0x4,*/ + SIT_ALU_FALL_LIT = 0x22, /*SIZE = 0x6,*/ + SIT_TEX = 0x40, /*SIZE = 0x4,*/ + SIT_VTX = 0x80, /*SIZE = 0x4, MEGA_FETCH_BYTES = 0x20*/ + SIT_VTX_GENERIC = 0x81, /*SIZE = 0x4, MEGA_FETCH_BYTES = 0x20*/ + SIT_VTX_SEM = 0x82 /*SIZE = 0x4, MEGA_FETCH_BYTES = 0x20*/ +} ShaderInstType; + +typedef struct R700ShaderInstruction +{ + ShaderInstType m_ShaderInstType; + struct R700ShaderInstruction *pNextInst; + GLuint m_uIndex; + GLuint useCount; +} R700ShaderInstruction; + +// ------------------ CF insts --------------------------- + +typedef R700ShaderInstruction R700ControlFlowInstruction; + +typedef struct R700ControlFlowAllocExportClause +{ + ShaderInstType m_ShaderInstType; + R700ShaderInstruction * pNextInst; + GLuint m_uIndex; + GLuint useCount; + + sq_cf_alloc_export_word0_u m_Word0; + sq_cf_alloc_export_word1_u m_Word1; +} R700ControlFlowAllocExportClause; + +typedef struct R700ControlFlowSXClause +{ + ShaderInstType m_ShaderInstType; + R700ShaderInstruction * pNextInst; + //R700ControlFlowAllocExportClause + //R700ControlFlowInstruction + //R700ShaderInstruction + GLuint m_uIndex; + GLuint useCount; + //--------------------- + //--------------------------- + sq_cf_alloc_export_word0_u m_Word0; + sq_cf_alloc_export_word1_u m_Word1; + //------------------------------------- + + sq_cf_alloc_export_word1_swiz_u m_Word1_SWIZ; +} R700ControlFlowSXClause; + +typedef struct R700ControlFlowSMXClause +{ + ShaderInstType m_ShaderInstType; + R700ShaderInstruction * pNextInst; + //R700ControlFlowAllocExportClause + //R700ControlFlowInstruction + //R700ShaderInstruction + GLuint m_uIndex; + GLuint useCount; + //--------------------- + //--------------------------- + sq_cf_alloc_export_word0_u m_Word0; + sq_cf_alloc_export_word1_u m_Word1; + //------------------------------- + + sq_cf_alloc_export_word1_buf_u m_Word1_BUF; +} R700ControlFlowSMXClause; + +typedef struct R700ControlFlowGenericClause +{ + ShaderInstType m_ShaderInstType; + R700ShaderInstruction * pNextInst; + //R700ControlFlowInstruction + //R700ShaderInstruction + GLuint m_uIndex; + GLuint useCount; + //--------------------- + //--------------------- + + sq_cf_word0_u m_Word0; + sq_cf_word1_u m_Word1; + + struct R700VertexInstruction *m_pLinkedVTXInstruction; + struct R700TextureInstruction *m_pLinkedTEXInstruction; +} R700ControlFlowGenericClause; + +typedef struct R700ControlFlowALUClause +{ + ShaderInstType m_ShaderInstType; + R700ShaderInstruction * pNextInst; + //R700ControlFlowInstruction + //R700ShaderInstruction + GLuint m_uIndex; + GLuint useCount; + //--------------------- + //--------------------- + + sq_cf_alu_word0_u m_Word0; + sq_cf_alu_word1_u m_Word1; + + struct R700ALUInstruction *m_pLinkedALUInstruction; +} R700ControlFlowALUClause; + +// ------------------- End of CF Inst ------------------------ + +// ------------------- ALU Inst ------------------------------ +typedef struct R700ALUInstruction +{ + ShaderInstType m_ShaderInstType; + R700ShaderInstruction * pNextInst; + //R700ShaderInstruction + GLuint m_uIndex; + GLuint useCount; + //--------------------- + + sq_alu_word0_u m_Word0; + sq_alu_word1_u m_Word1; + sq_alu_word1_op2_v2_u m_Word1_OP2; + sq_alu_word1_op3_u m_Word1_OP3; + + struct R700ControlFlowALUClause *m_pLinkedALUClause; +} R700ALUInstruction; + +typedef struct R700ALUInstructionHalfLiteral +{ + ShaderInstType m_ShaderInstType; + R700ShaderInstruction * pNextInst; + //R700ALUInstruction + //R700ShaderInstruction + GLuint m_uIndex; + GLuint useCount; + //--------------------- + + sq_alu_word0_u m_Word0; + sq_alu_word1_u m_Word1; + sq_alu_word1_op2_v2_u m_Word1_OP2; + sq_alu_word1_op3_u m_Word1_OP3; + + struct R700ControlFlowALUClause *m_pLinkedALUClause; + //------------------- + + GLfloat m_fLiteralX, + m_fLiteralY; +} R700ALUInstructionHalfLiteral; + +typedef struct R700ALUInstructionFullLiteral +{ + ShaderInstType m_ShaderInstType; + R700ShaderInstruction * pNextInst; + //R700ALUInstruction + //R700ShaderInstruction + GLuint m_uIndex; + GLuint useCount; + //--------------------- + + sq_alu_word0_u m_Word0; + sq_alu_word1_u m_Word1; + sq_alu_word1_op2_v2_u m_Word1_OP2; + sq_alu_word1_op3_u m_Word1_OP3; + + struct R700ControlFlowALUClause *m_pLinkedALUClause; + //------------------- + + GLfloat m_fLiteralX, + m_fLiteralY, + m_fLiteralZ, + m_fLiteralW; +} R700ALUInstructionFullLiteral; +// ------------------- End of ALU Inst ----------------------- + +// ------------------- Textuer/Vertex Instruction -------------------- + +typedef struct R700TextureInstruction +{ + ShaderInstType m_ShaderInstType; + R700ShaderInstruction * pNextInst; + //R700ShaderInstruction + GLuint m_uIndex; + GLuint useCount; + //--------------------- + + sq_tex_word0_u m_Word0; + sq_tex_word1_u m_Word1; + sq_tex_word2_u m_Word2; + + struct R700ControlFlowGenericClause *m_pLinkedGenericClause; +} R700TextureInstruction; + +typedef struct R700VertexInstruction +{ + ShaderInstType m_ShaderInstType; + R700ShaderInstruction * pNextInst; + //R700ShaderInstruction + GLuint m_uIndex; + GLuint useCount; + //--------------------- + + sq_vtx_word0_u m_Word0; + sq_vtx_word1_u m_Word1; + sq_vtx_word2_u m_Word2; + + struct R700ControlFlowGenericClause *m_pLinkedGenericClause; +} R700VertexInstruction; +// +typedef struct R700VertexSemanticFetch +{ + ShaderInstType m_ShaderInstType; + R700ShaderInstruction * pNextInst; + //R700VertexInstruction + //R700ShaderInstruction + GLuint m_uIndex; + GLuint useCount; + //--------------------- + + sq_vtx_word0_u m_Word0; + sq_vtx_word1_u m_Word1; + sq_vtx_word2_u m_Word2; + + struct R700ControlFlowGenericClause *m_pLinkedGenericClause; + //--------------------------- + + sq_vtx_word1_sem_u m_Word1_SEM; +} R700VertexSemanticFetch; +// +typedef struct R700VertexGenericFetch +{ + ShaderInstType m_ShaderInstType; + R700ShaderInstruction * pNextInst; + //R700VertexInstruction + //R700ShaderInstruction + GLuint m_uIndex; + GLuint useCount; + //--------------------- + + sq_vtx_word0_u m_Word0; + sq_vtx_word1_u m_Word1; + sq_vtx_word2_u m_Word2; + + struct R700ControlFlowGenericClause *m_pLinkedGenericClause; + //--------------------------- + + sq_vtx_word1_gpr_u m_Word1_GPR; +} R700VertexGenericFetch; + +// ------------------- End of Texture Vertex Instruction -------------------- + +void Init_R700ControlFlowGenericClause(R700ControlFlowGenericClause* pInst); +void Init_R700ControlFlowALUClause(R700ControlFlowALUClause* pInst); +void Init_R700ControlFlowSXClause(R700ControlFlowSXClause* pInst); +void Init_R700ControlFlowSMXClause(R700ControlFlowSMXClause* pInst); +void Init_R700ALUInstruction(R700ALUInstruction* pInst); +void Init_R700ALUInstructionHalfLiteral(R700ALUInstructionHalfLiteral* pInst, GLfloat x, GLfloat y); +void Init_R700ALUInstructionFullLiteral(R700ALUInstructionFullLiteral* pInst, GLfloat x, GLfloat y, GLfloat z, GLfloat w); +void Init_R700TextureInstruction(R700TextureInstruction* pInst); +void Init_R700VertexSemanticFetch(R700VertexSemanticFetch* pInst); +void Init_R700VertexGenericFetch(R700VertexGenericFetch* pInst); + +unsigned int GetInstructionSize(ShaderInstType instType); +unsigned int GetCFMaxInstructions(ShaderInstType instType); + +GLboolean LinkVertexInstruction(R700ControlFlowGenericClause *pCFGeneric, + R700VertexInstruction *pVTXInstruction); + +#endif //_R700_SHADERINST_H_ diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c new file mode 100644 index 0000000000..4341f33665 --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -0,0 +1,925 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + */ + +#include "main/glheader.h" +#include "main/mtypes.h" +#include "main/state.h" +#include "main/imports.h" +#include "main/enums.h" +#include "main/macros.h" +#include "main/dd.h" +#include "main/simple_list.h" + +#include "tnl/tnl.h" +#include "tnl/t_pipeline.h" +#include "tnl/t_vp_build.h" +#include "swrast/swrast.h" +#include "swrast_setup/swrast_setup.h" +#include "main/api_arrayelt.h" +#include "main/state.h" +#include "main/framebuffer.h" + +#include "shader/prog_parameter.h" +#include "shader/prog_statevars.h" +#include "vbo/vbo.h" +#include "main/texformat.h" + +#include "r600_context.h" + +#include "r700_chip.h" +#include "r700_state.h" + +#if 0 /* to be enabled */ +#include "r700_fragprog.h" +#include "r700_vertprog.h" +#endif /* to be enabled */ + +void r700SetDefaultStates(context_t *context) //-------------------- +{ + +} + +void r700UpdateShaders (GLcontext * ctx) //---------------------------------- +{ + context_t *context = R700_CONTEXT(ctx); + + GLvector4f dummy_attrib[_TNL_ATTRIB_MAX]; + GLvector4f *temp_attrib[_TNL_ATTRIB_MAX]; +#if 0 /* to be enabled */ + struct r700_vertex_program *vp; + int i; + + if (context->NewGLState) + { + context->NewGLState = 0; + + for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) + { + /* mat states from state var not array for sw */ + dummy_attrib[i].stride = 0; + + temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i]; + TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]); + } + + _tnl_UpdateFixedFunctionProgram(ctx); + + for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) + { + TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i]; + } + + r700SelectVertexShader(ctx); + vp = (struct r700_vertex_program *)ctx->VertexProgram._Current; + + if (vp->translated == GL_FALSE) + { + // TODO + //fprintf(stderr, "Failing back to sw-tcl\n"); + //hw_tcl_on = future_hw_tcl_on = 0; + //r300ResetHwState(rmesa); + // + r700UpdateStateParameters(ctx, _NEW_PROGRAM); + return; + } + } + + r700UpdateStateParameters(ctx, _NEW_PROGRAM); +#endif /* to be enabled */ +} + +/* + * To correctly position primitives: + */ +void r700UpdateViewportOffset(GLcontext * ctx) //------------------ +{ +} + +/** + * Tell the card where to render (offset, pitch). + * Effected by glDrawBuffer, etc + */ +void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //--------------------- +{ +#if 0 /* to be enabled */ + context_t *context = R700_CONTEXT(ctx); + + switch (ctx->DrawBuffer->_ColorDrawBufferIndexes[0]) + { + case BUFFER_FRONT_LEFT: + context->target.rt = context->screen->frontBuffer; + break; + case BUFFER_BACK_LEFT: + context->target.rt = context->screen->backBuffer; + break; + default: + memset (&context->target.rt, sizeof(context->target.rt), 0); + } +#endif /* to be enabled */ +} + +static void r700FetchStateParameter(GLcontext * ctx, + const gl_state_index state[STATE_LENGTH], + GLfloat * value) +{ + context_t *context = R700_CONTEXT(ctx); + + /* TODO */ +} + +void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //-------------------- +{ +#if 0 /* to be enabled */ + struct r700_fragment_program *fp; + struct gl_program_parameter_list *paramList; + GLuint i; + + if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM))) + return; + + fp = (struct r700_fragment_program *)ctx->FragmentProgram._Current; + if (!fp) + { + return; + } + + paramList = fp->mesa_program.Base.Parameters; + + if (!paramList) + { + return; + } + + for (i = 0; i < paramList->NumParameters; i++) + { + if (paramList->Parameters[i].Type == PROGRAM_STATE_VAR) + { + r700FetchStateParameter(ctx, + paramList->Parameters[i]. + StateIndexes, + paramList->ParameterValues[i]); + } + } +#endif /* to be enabled */ +} + +/** + * Called by Mesa after an internal state update. + */ +static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //------------------- +{ +#if 0 /* to be enabled */ + context_t *context = R700_CONTEXT(ctx); + + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + + _swrast_InvalidateState(ctx, new_state); + _swsetup_InvalidateState(ctx, new_state); + _vbo_InvalidateState(ctx, new_state); + _tnl_InvalidateState(ctx, new_state); + _ae_invalidate_state(ctx, new_state); + + if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) + { + r700UpdateDrawBuffer(ctx); + } + + r700UpdateStateParameters(ctx, new_state); + + if(GL_TRUE == context->bEnablePerspective) + { + /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */ + CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit); + CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit); + + SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit); + + CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit); + SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit); + } + else + { + /* For orthogonal case. */ + SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit); + SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit); + + SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit); + + SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit); + CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit); + } + + context->NewGLState |= new_state; +#endif /* to be enabled */ +} + +static void r700SetDepthState(GLcontext * ctx) +{ + context_t *context = R700_CONTEXT(ctx); + + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + + if (ctx->Depth.Test) + { + SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit); + if (ctx->Depth.Mask) + { + SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit); + } + else + { + CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit); + } + + switch (ctx->Depth.Func) + { + case GL_NEVER: + SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER, + ZFUNC_shift, ZFUNC_mask); + break; + case GL_LESS: + SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS, + ZFUNC_shift, ZFUNC_mask); + break; + case GL_EQUAL: + SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL, + ZFUNC_shift, ZFUNC_mask); + break; + case GL_LEQUAL: + SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL, + ZFUNC_shift, ZFUNC_mask); + break; + case GL_GREATER: + SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER, + ZFUNC_shift, ZFUNC_mask); + break; + case GL_NOTEQUAL: + SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL, + ZFUNC_shift, ZFUNC_mask); + break; + case GL_GEQUAL: + SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL, + ZFUNC_shift, ZFUNC_mask); + break; + case GL_ALWAYS: + SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS, + ZFUNC_shift, ZFUNC_mask); + break; + default: + SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS, + ZFUNC_shift, ZFUNC_mask); + break; + } + } + else + { + CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit); + CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit); + } +} + +static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //--------------- +{ +} + + +static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //---------------- +{ +} + +static void r700BlendEquationSeparate(GLcontext * ctx, + GLenum modeRGB, GLenum modeA) //----------------- +{ +} + +static void r700BlendFuncSeparate(GLcontext * ctx, + GLenum sfactorRGB, GLenum dfactorRGB, + GLenum sfactorA, GLenum dfactorA) //------------------------ +{ +} + +static void r700UpdateCulling(GLcontext * ctx) +{ + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(R700_CONTEXT(ctx)->chipobj.pvChipObj); + + CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); + CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit); + CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit); + + if (ctx->Polygon.CullFlag) + { + switch (ctx->Polygon.CullFaceMode) + { + case GL_FRONT: + SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit); + CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit); + break; + case GL_BACK: + CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit); + SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit); + break; + case GL_FRONT_AND_BACK: + SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit); + SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit); + break; + default: + CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit); + CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit); + break; + } + } + + switch (ctx->Polygon.FrontFace) + { + case GL_CW: + SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); + break; + case GL_CCW: + CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); + break; + default: + CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */ + break; + } +} + +static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------ +{ + switch (cap) + { + case GL_TEXTURE_1D: + case GL_TEXTURE_2D: + case GL_TEXTURE_3D: + break; + case GL_FOG: + break; + case GL_ALPHA_TEST: + break; + case GL_COLOR_LOGIC_OP: + case GL_BLEND: + break; + case GL_CLIP_PLANE0: + case GL_CLIP_PLANE1: + case GL_CLIP_PLANE2: + case GL_CLIP_PLANE3: + case GL_CLIP_PLANE4: + case GL_CLIP_PLANE5: + break; + case GL_DEPTH_TEST: + r700SetDepthState(ctx); + break; + case GL_STENCIL_TEST: + break; + case GL_CULL_FACE: + r700UpdateCulling(ctx); + break; + case GL_POLYGON_OFFSET_POINT: + case GL_POLYGON_OFFSET_LINE: + case GL_POLYGON_OFFSET_FILL: + break; + default: + break; + } +} + +/** + * Handle glColorMask() + */ +static void r700ColorMask(GLcontext * ctx, + GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------ +{ +} + +/** + * Change the depth testing function. + * + * \note Mesa already filters redundant calls to this function. + */ +static void r700DepthFunc(GLcontext * ctx, GLenum func) //-------------------- +{ + r700SetDepthState(ctx); +} + +/** + * Enable/Disable depth writing. + * + * \note Mesa already filters redundant calls to this function. + */ +static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------ +{ + r700SetDepthState(ctx); +} + +/** + * Change the culling mode. + * + * \note Mesa already filters redundant calls to this function. + */ +static void r700CullFace(GLcontext * ctx, GLenum mode) //----------------- +{ + r700UpdateCulling(ctx); +} + +/* ============================================================= + * Fog + */ +static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //-------------- +{ +} + +/** + * Change the polygon orientation. + * + * \note Mesa already filters redundant calls to this function. + */ +static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------ +{ + r700UpdateCulling(ctx); +} + +static void r700ShadeModel(GLcontext * ctx, GLenum mode) //-------------------- +{ +} + +static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------- +{ +} + +static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face, + GLenum func, GLint ref, GLuint mask) //--------------------- +{ +} + + +static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //-------------- +{ +} + +static void r700StencilOpSeparate(GLcontext * ctx, GLenum face, + GLenum fail, GLenum zfail, GLenum zpass) //-------------------- +{ +} + +#define SUBPIXEL_X 0.125 +#define SUBPIXEL_Y 0.125 + +static void r700Viewport(GLcontext * ctx, + GLint x, + GLint y, + GLsizei width, + GLsizei height) //-------------------- +{ +#if 0 /* to be enabled */ + context_t *context = R700_CONTEXT(ctx); + + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + + context->vport_x = x; + context->vport_y = y; + context->vport_width = width; + context->vport_height= height; + + __DRIdrawablePrivate *dPriv = context->currentDraw; + + GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; + GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; + + const GLfloat *v = ctx->Viewport._WindowMap.m; + + GLfloat sx, tx, sy, ty, sz, tz; + GLfloat scale; + + switch (ctx->Visual.depthBits) + { + case 16: + scale = 1.0 / (GLfloat) 0xffff; + break; + case 24: + scale = 1.0 / (GLfloat) 0xffffff; + break; + default: + fprintf(stderr, "Error: Unsupported depth %d... exiting\n", + ctx->Visual.depthBits); + _mesa_exit(-1); + } + + sx = v[MAT_SX]; + tx = v[MAT_TX] + xoffset + SUBPIXEL_X; + sy = -v[MAT_SY]; + ty = (-v[MAT_TY]) + yoffset + SUBPIXEL_Y; + sz = v[MAT_SZ] * scale; + tz = v[MAT_TZ] * scale; + + /* TODO : Need DMA flush as well. */ + + if(context->cmdbuf.count_used > 0) + { + (context->chipobj.FlushCmdBuffer)(context); + } + + r700->PA_CL_VPORT_XSCALE.u32All = *((unsigned int*)(&sx)); + r700->PA_CL_VPORT_XOFFSET.u32All = *((unsigned int*)(&tx)); + + r700->PA_CL_VPORT_YSCALE.u32All = *((unsigned int*)(&sy)); + r700->PA_CL_VPORT_YOFFSET.u32All = *((unsigned int*)(&ty)); + + r700->PA_CL_VPORT_ZSCALE.u32All = *((unsigned int*)(&sz)); + r700->PA_CL_VPORT_ZOFFSET.u32All = *((unsigned int*)(&tz)); +#endif /* to be enabled */ +} + + +static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //------------- +{ +} + +static void r700PointSize(GLcontext * ctx, GLfloat size) //------------------- +{ +} + +static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //--------------- +{ +} + +static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //-------------- +{ +} + + +static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------ +{ +} + +static void r700RenderMode(GLcontext * ctx, GLenum mode) //--------------------- +{ +} + +static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) //----------------- +{ +} + +static void r700Scissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h) //--------------- +{ + if (ctx->Scissor.Enabled) + { + /* We don't pipeline cliprect changes */ + /* r700Flush(ctx); */ + + //__DRIdrawablePrivate *dPriv = radeon->dri.drawable; + //int x1 = dPriv->x + ctx->Scissor.X; + //int y1 = dPriv->y + dPriv->h - (ctx->Scissor.Y + ctx->Scissor.Height); + + //radeon->state.scissor.rect.x1 = x1; + //radeon->state.scissor.rect.y1 = y1; + //radeon->state.scissor.rect.x2 = x1 + ctx->Scissor.Width; + //radeon->state.scissor.rect.y2 = y1 + ctx->Scissor.Height; + /* radeonRecalcScissorRects(radeon); */ + } +} + + +/** + * Calculate initial hardware state and register state functions. + * Assumes that the command buffer and state atoms have been + * initialized already. + */ +void r700InitState(GLcontext * ctx) //------------------- +{ +#if 0 /* to be enabled */ + context_t *context = R700_CONTEXT(ctx); + + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + + if(context->ctx->Visual.doubleBufferMode && context->sarea->pfCurrentPage == 0) + { + context->target.rt = context->screen->backBuffer; + } + else + { + context->target.rt = context->screen->frontBuffer; + } + + SETfield(r700->CB_TARGET_MASK.u32All, 0xF, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask); + SETfield(r700->CB_SHADER_MASK.u32All, 0xF, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask); + + /* screen */ + r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0; + SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, context->screen->width, + PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask); + SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, context->screen->height, + PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask); + + /* window */ + SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit); + SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, context->currentDraw->x, + PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask); + SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, context->currentDraw->y, + PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask); + + SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, context->currentDraw->x + context->currentDraw->w, + PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask); + SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, context->currentDraw->y + context->currentDraw->h, + PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask); + + /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */ + r700->PA_SC_CLIPRECT_RULE.u32All = 0x0000FFFF; + + SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, context->currentDraw->x, + PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask); + SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, context->currentDraw->y, + PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask); + SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, context->currentDraw->x + context->currentDraw->w, + PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask); + SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, context->currentDraw->y + context->currentDraw->h, + PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask); + + r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All; + r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All; + r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All; + r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All; + r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All; + r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All; + + /* more....2d clip */ + SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit); + SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, context->currentDraw->x, + PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask); + SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, context->currentDraw->y, + PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask); + SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, context->currentDraw->x + context->currentDraw->w, + PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask); + SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, context->currentDraw->y + context->currentDraw->h, + PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask); + + SETbit(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit); + SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, context->currentDraw->x, + PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask); + SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, context->currentDraw->y, + PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask); + SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, context->currentDraw->x + context->currentDraw->w, + PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask); + SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, context->currentDraw->y + context->currentDraw->h, + PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask); + + SETbit(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, WINDOW_OFFSET_DISABLE_bit); + SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, context->currentDraw->x, + PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask); + SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, context->currentDraw->y, + PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask); + SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, context->currentDraw->x + context->currentDraw->w, + PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask); + SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, context->currentDraw->y + context->currentDraw->h, + PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask); + + /* setup viewport */ + r700Viewport(ctx, + 0, + 0, + context->currentDraw->w, + context->currentDraw->h); + + /* Turn off vgt reuse */ + r700->VGT_REUSE_OFF.u32All = 0; + SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit); + + /* Specify offsetting and clamp values for vertices */ + r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF; + r700->VGT_MIN_VTX_INDX.u32All = 0; + r700->VGT_INDX_OFFSET.u32All = 0; + + /* Specify the number of instances */ + r700->VGT_DMA_NUM_INSTANCES.u32All = 1; + + /* not alpha blend */ + CLEARfield(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_FUNC_mask); + CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit); + + /* defualt shader connections. */ + r700->SPI_VS_OUT_ID_0.u32All = 0x03020100; + r700->SPI_VS_OUT_ID_1.u32All = 0x07060504; + + r700->SPI_PS_INPUT_CNTL_0.u32All = 0x00000800; + r700->SPI_PS_INPUT_CNTL_1.u32All = 0x00000801; + r700->SPI_PS_INPUT_CNTL_2.u32All = 0x00000802; + + SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask); + CLEARbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit); + CLEARfield(r700->CB_BLEND0_CONTROL.u32All, COLOR_SRCBLEND_mask); /* no dst blend */ + CLEARfield(r700->CB_BLEND0_CONTROL.u32All, ALPHA_SRCBLEND_mask); /* no dst blend */ + + r700->DB_SHADER_CONTROL.u32All = 0; + SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit); + + /* Set up the culling control register */ + SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES, + POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask); + SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES, + POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask); + + /* Do scale XY and Z by 1/W0. */ + context->bEnablePerspective = GL_TRUE; + CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit); + CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit); + SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit); + + /* Enable viewport scaling for all three axis */ + SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit); + SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit); + SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit); + SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit); + SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit); + SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit); + + /* Set up point sizes and min/max values */ + SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8, + PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask); + SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8, + PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask); + CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask); + SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask); + + /* Set up line control */ + SETfield(r700->PA_SU_LINE_CNTL.u32All, 0x8, + PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask); + + r700->PA_SC_LINE_CNTL.u32All = 0; + CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit); + SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit); + + /* Set up vertex control */ + r700->PA_SU_VTX_CNTL.u32All = 0; + CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask); + SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit); + SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN, + PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask); + + /* to 1.0 = no guard band */ + r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */ + r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000; + r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000; + r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000; + + /* Disble color compares */ + SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS, + CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask); + SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS, + CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask); + SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC, + CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask); + + /* Zero out source */ + r700->CB_CLRCMP_SRC.u32All = 0x00000000; + + /* Put a compare color in for error checking */ + r700->CB_CLRCMP_DST.u32All = 0x000000FF; + + /* Set up color compare mask */ + r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF; + + /* Enable all samples for multi-sample anti-aliasing */ + r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF; + /* Turn off AA */ + r700->PA_SC_AA_CONFIG.u32All = 0; + + SETfield(r700->VGT_OUT_DEALLOC_CNTL.u32All, 16, DEALLOC_DIST_shift, DEALLOC_DIST_mask); + SETfield(r700->VGT_VERTEX_REUSE_BLOCK_CNTL.u32All, 14, VTX_REUSE_DEPTH_shift, VTX_REUSE_DEPTH_mask); + + r700->SX_MISC.u32All = 0; + + /* depth buf */ + r700->DB_DEPTH_SIZE.u32All = 0; + SETfield(r700->DB_DEPTH_SIZE.u32All, (context->screen->depthBuffer.pitch/8)-1, + PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); + SETfield(r700->DB_DEPTH_SIZE.u32All, ( (context->screen->depthBuffer.size / context->screen->cpp)/64 )-1, + SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */ + r700->DB_DEPTH_BASE.u32All = context->screen->depthBuffer.gpu >> 8; + r700->DB_DEPTH_INFO.u32All = 0; + if(4 == context->screen->cpp) /* TODO : in scrren create, gives z its own format alloc. */ + { + switch (ctx->Visual.depthBits) + { + case 16: + case 24: + SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24, + DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask); + break; + default: + fprintf(stderr, "Error: Unsupported depth %d... exiting\n", + ctx->Visual.depthBits); + _mesa_exit(-1); + } + } + else + { + SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16, + DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask); + } + SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1, + DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask); + /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */ + r700->DB_DEPTH_CONTROL.u32All = 0; + r700->DB_DEPTH_CLEAR.u32All = 0x3F800000; + r700->DB_DEPTH_VIEW.u32All = 0; + r700->DB_RENDER_CONTROL.u32All = 0; + r700->DB_RENDER_OVERRIDE.u32All = 0; + SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask); + SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask); + SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask); + + /* color buffer */ + SETfield(r700->CB_COLOR0_SIZE.u32All, (context->screen->frontBuffer.pitch/8)-1, + PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); + SETfield(r700->CB_COLOR0_SIZE.u32All, ( (context->screen->frontBuffer.size / context->screen->cpp)/64 )-1, + SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); + r700->CB_COLOR0_BASE.u32All = context->screen->frontBuffer.gpu >> 8; + SETfield(r700->CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask); + SETfield(r700->CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL, + CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask); + if(4 == context->screen->cpp) + { + SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_8_8_8_8, + CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask); + SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask); + } + else + { + SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_5_6_5, + CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask); + SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT_REV, + COMP_SWAP_shift, COMP_SWAP_mask); + } + SETbit(r700->CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit); + SETbit(r700->CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit); + SETfield(r700->CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask); + r700->CB_COLOR0_VIEW.u32All = 0; + r700->CB_COLOR0_TILE.u32All = 0; + r700->CB_COLOR0_FRAG.u32All = 0; + r700->CB_COLOR0_MASK.u32All = 0; + + r700->PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000; +#endif /* to be enabled */ +} + +void r700InitStateFuncs(struct dd_function_table *functions) //----------------- +{ + functions->UpdateState = r700InvalidateState; + functions->AlphaFunc = r700AlphaFunc; + functions->BlendColor = r700BlendColor; + functions->BlendEquationSeparate = r700BlendEquationSeparate; + functions->BlendFuncSeparate = r700BlendFuncSeparate; + functions->Enable = r700Enable; + functions->ColorMask = r700ColorMask; + functions->DepthFunc = r700DepthFunc; + functions->DepthMask = r700DepthMask; + functions->CullFace = r700CullFace; + functions->Fogfv = r700Fogfv; + functions->FrontFace = r700FrontFace; + functions->ShadeModel = r700ShadeModel; + + /* ARB_point_parameters */ + functions->PointParameterfv = r700PointParameter; + + /* Stencil related */ + functions->StencilFuncSeparate = r700StencilFuncSeparate; + functions->StencilMaskSeparate = r700StencilMaskSeparate; + functions->StencilOpSeparate = r700StencilOpSeparate; + + /* Viewport related */ + functions->Viewport = r700Viewport; + functions->DepthRange = r700DepthRange; + functions->PointSize = r700PointSize; + functions->LineWidth = r700LineWidth; + + functions->PolygonOffset = r700PolygonOffset; + functions->PolygonMode = r700PolygonMode; + + functions->RenderMode = r700RenderMode; + + functions->ClipPlane = r700ClipPlane; + + functions->Scissor = r700Scissor; +} + diff --git a/src/mesa/drivers/dri/r600/r700_state.h b/src/mesa/drivers/dri/r600/r700_state.h new file mode 100644 index 0000000000..b9542f4dd2 --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_state.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + */ + +#ifndef _R700_STATE_H +#define _R700_STATE_H + +#include "main/mtypes.h" + +#include "r600_context.h" + +#include "r700_chip.h" + +extern void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state); +extern void r700UpdateShaders (GLcontext * ctx); + +extern void r700UpdateViewportOffset(GLcontext * ctx); +extern void r700UpdateDrawBuffer (GLcontext * ctx); + +extern void r700InitState (GLcontext * ctx); +extern void r700InitStateFuncs (struct dd_function_table *functions); + +extern void r700SetDefaultStates(context_t * context); + +#endif /* _R600_SCREEN_H */ diff --git a/src/mesa/drivers/dri/r600/r700_tex.c b/src/mesa/drivers/dri/r600/r700_tex.c new file mode 100644 index 0000000000..75300d2c5f --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_tex.c @@ -0,0 +1,1555 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + */ + +#include "main/glheader.h" +#include "main/imports.h" +#include "main/colormac.h" +#include "main/context.h" +#include "main/simple_list.h" +#include "main/texformat.h" +#include "main/texstore.h" +#include "texmem.h" +#include "main/teximage.h" +#include "main/texobj.h" +#include "main/macros.h" +#include "xmlpool.h" + +#include "radeon_common.h" + +#include "r600_context.h" +#include "r700_chip.h" + +#if 0 /* to be enabled */ +#include "r700_state.h" +#endif /* to be enabled */ + +#include "r700_tex.h" + +GLuint r700GetTexObjSize(void) +{ + return sizeof(r700TexObj); +} + +/* to be enable */ +void r700SetTexBuffer(__DRIcontext *pDRICtx, GLint target, + __DRIdrawable *dPriv) +{ +} + +/* to be enable */ +void r700SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, + GLint format, __DRIdrawable *dPriv) +{ +} + +/* to be enable */ +void r700SetTexOffset(__DRIcontext *pDRICtx, GLint texname, + unsigned long long offset, GLint depth, + GLuint pitch) +{ +} + +#if 0 /* to be enabled */ +static GLboolean r700GetTexFormat(struct gl_texture_object *tObj, GLuint mesa_format) +{ + r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; + + t->texture_state.SQ_TEX_RESOURCE4.u32All &= ~( SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask + |SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask + |SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask + |SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask ); + + switch (mesa_format) /* This is mesa format. */ + { + case MESA_FORMAT_RGBA8888: + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + + break; + case MESA_FORMAT_RGBA8888_REV: + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + + break; + case MESA_FORMAT_ARGB8888: + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ARGB8888_REV: + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + + case MESA_FORMAT_RGB888: + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGB565: + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_5_6_5, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGB565_REV: + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_5_6_5, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ARGB4444: + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_4_4_4_4, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ARGB4444_REV: + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_4_4_4_4, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ARGB1555: + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_1_5_5_5, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ARGB1555_REV: + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_1_5_5_5, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_AL88: + case MESA_FORMAT_AL88_REV: /* TODO : Check this. */ + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGB332: + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_3_3_2, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_A8: /* ZERO, ZERO, ZERO, X */ + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_L8: /* X, X, X, ONE */ + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_I8: /* X, X, X, X */ + case MESA_FORMAT_CI8: + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + /* YUV422 TODO conversion */ /* X, Y, Z, ONE, G8R8_G8B8 */ + /* + case MESA_FORMAT_YCBCR: + t->texture_state.SQ_TEX_RESOURCE1.bitfields.DATA_FORMAT = ; + break; + */ + /* VUY422 TODO conversion */ /* X, Y, Z, ONE, G8R8_G8B8 */ + /* + case MESA_FORMAT_YCBCR_REV: + t->texture_state.SQ_TEX_RESOURCE1.bitfields.DATA_FORMAT = ; + break; + */ + case MESA_FORMAT_RGB_DXT1: /* not supported yet */ + + break; + case MESA_FORMAT_RGBA_DXT1: /* not supported yet */ + + break; + case MESA_FORMAT_RGBA_DXT3: /* not supported yet */ + + break; + case MESA_FORMAT_RGBA_DXT5: /* not supported yet */ + + break; + case MESA_FORMAT_RGBA_FLOAT32: + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_32_32_32_32_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGBA_FLOAT16: + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_16_16_16_16_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGB_FLOAT32: /* X, Y, Z, ONE */ + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_32_32_32_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGB_FLOAT16: + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_16_16_16_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ALPHA_FLOAT32: /* ZERO, ZERO, ZERO, X */ + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_32_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ALPHA_FLOAT16: /* ZERO, ZERO, ZERO, X */ + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_16_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_LUMINANCE_FLOAT32: /* X, X, X, ONE */ + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_32_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_LUMINANCE_FLOAT16: /* X, X, X, ONE */ + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_16_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32: + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_32_32_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16: + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_16_16_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */ + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_32_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */ + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_16_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_Z16: + case MESA_FORMAT_Z24_S8: + case MESA_FORMAT_Z32: + switch (mesa_format) + { + case MESA_FORMAT_Z16: + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_16, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + break; + case MESA_FORMAT_Z24_S8: + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_24_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + break; + case MESA_FORMAT_Z32: + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_32, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + }; + switch (tObj->DepthMode) + { + case GL_LUMINANCE: /* X, X, X, ONE */ + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case GL_INTENSITY: /* X, X, X, X */ + + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case GL_ALPHA: /* ZERO, ZERO, ZERO, X */ + t->texture_state.SQ_TEX_RESOURCE4.u32All |= + (SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + default: + return GL_FALSE; + } + break; + default: + /* Not supported format */ + return GL_FALSE; + }; + + return GL_TRUE; +} + +static void compute_tex_image_offset( + struct gl_texture_object *tObj, + GLuint face, + GLint level, + GLint* curOffset) +{ + r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; + const struct gl_texture_image* texImage; + GLuint blitWidth = R700_BLIT_WIDTH_BYTES; + GLuint texelBytes; + GLuint size; + GLuint pitch; + + texImage = tObj->Image[0][level + t->base.firstLevel]; + if (!texImage) + { + return; + } + + texelBytes = texImage->TexFormat->TexelBytes; + + pitch = (texImage->Width + R700_TEXEL_PITCH_ALIGNMENT_MASK) & ~R700_TEXEL_PITCH_ALIGNMENT_MASK; + + /* find image size in bytes */ + if (texImage->IsCompressed) + { + /* not supported yet */ + } + else if (tObj->Target == GL_TEXTURE_RECTANGLE_NV) + { + if( (ARRAY_LINEAR_ALIGNED << SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift) + == (t->texture_state.SQ_TEX_RESOURCE0.u32All & SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask) ) + { + pitch = (texImage->Width * texelBytes + 255) & ~255; + } + else + { + if(0 == level) + { + pitch = (pitch * texelBytes + 63) & ~63; + } + else + { + pitch = texImage->Width * texelBytes; + } + } + size = pitch * texImage->Height; + blitWidth = 64 / texelBytes; + pitch /= texelBytes; + } + else + { + if( (ARRAY_LINEAR_ALIGNED << SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift) + == (t->texture_state.SQ_TEX_RESOURCE0.u32All & SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask) ) + { + pitch = (texImage->Width * texelBytes + 255) & ~255; + } + else + { + if(0 == level) + { + pitch = (pitch * texelBytes + 31) & ~31; + } + else + { + pitch = texImage->Width * texelBytes; + } + } + size = pitch * texImage->Height * texImage->Depth; + blitWidth = MAX2(texImage->Width, 64 / texelBytes); + pitch /= texelBytes; + } + assert(size > 0); + + if( (0 == level) || (1 == level) ) /* 0 for BASE_ADDRESS, 1 for MIP_ADDRESS */ + { + *curOffset = (*curOffset + R700_TEXTURE_ALIGNMENT_MASK) & ~R700_TEXTURE_ALIGNMENT_MASK; + } + + if (texelBytes) + { + /* fix x and y coords up later together with offset */ + t->texel_pitch[face][level] = pitch; + t->level_offset[face][level] = *curOffset; + t->byte_per_texel = texelBytes; + t->src_width_in_pexel[face][level] = texImage->Width; + t->src_hight_in_pexel[face][level] = texImage->Height; + } + else + { + /* Do it like one byte texel. */ + pitch = (size + R700_TEXEL_PITCH_ALIGNMENT_MASK) & ~R700_TEXEL_PITCH_ALIGNMENT_MASK; + t->texel_pitch[face][level] = pitch; + t->level_offset[face][level] = *curOffset; + t->byte_per_texel = 1; + t->src_width_in_pexel[face][level] = size; + t->src_hight_in_pexel[face][level] = 1; + } + + *curOffset += size; +} +#endif /* to be enabled */ + +void r700DestroyTexObj(context_t context, r700TexObjPtr t) +{ + /* TODO : nuke r700 chip texture and sampler pointer. */ + //int i; + + //for (i = 0; i < rmesa->ctx->Const.MaxTextureUnits; i++) + //{ + //if (rmesa->state.texture.unit[i].texobj == t) { + // rmesa->state.texture.unit[i].texobj = NULL; + //} + //} +} + +#if 0 /* to be enabled */ +static void r700SetTexImages(context_t *context, struct gl_texture_object *tObj) +{ + r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; + const struct gl_texture_image *baseImage = tObj->Image[0][tObj->BaseLevel]; + GLint curOffset; + GLint i, texelBytes; + GLint numLevels; + GLint log2Width, log2Height, log2Depth; + GLuint uTexelPitch; + + if (!t->image_override) + { + if(GL_FALSE == r700GetTexFormat(tObj, baseImage->TexFormat->MesaFormat) ) + { + _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__); + return; + } + } + + texelBytes = baseImage->TexFormat->TexelBytes; + + switch (tObj->Target) + { + case GL_TEXTURE_1D: + SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, SQ_TEX_DIM_1D, DIM_shift, DIM_mask); + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, 0, TEX_DEPTH_shift, TEX_DEPTH_mask); + break; + case GL_TEXTURE_2D: + case GL_TEXTURE_RECTANGLE_NV: + SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, SQ_TEX_DIM_2D, DIM_shift, DIM_mask); + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, 0, TEX_DEPTH_shift, TEX_DEPTH_mask); + break; + case GL_TEXTURE_3D: + SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, SQ_TEX_DIM_3D, DIM_shift, DIM_mask); + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, tObj->Image[0][t->base.firstLevel]->Depth - 1, + TEX_DEPTH_shift, TEX_DEPTH_mask); + break; + case GL_TEXTURE_CUBE_MAP: + SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, SQ_TEX_DIM_CUBEMAP, DIM_shift, DIM_mask); + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, 0, TEX_DEPTH_shift, TEX_DEPTH_mask); + break; + default: + _mesa_problem(NULL, "unexpected texture target type in %s", __FUNCTION__); + return; + } + + /* Compute which mipmap levels we really want to send to the hardware. + */ + driCalculateTextureFirstLastLevel((driTextureObject *) t); + log2Width = tObj->Image[0][t->base.firstLevel]->WidthLog2; + log2Height = tObj->Image[0][t->base.firstLevel]->HeightLog2; + log2Depth = tObj->Image[0][t->base.firstLevel]->DepthLog2; + + numLevels = t->base.lastLevel - t->base.firstLevel + 1; + + assert(numLevels <= RADEON_MAX_TEXTURE_LEVELS); + + /* Calculate mipmap offsets and dimensions for blitting (uploading) + * The idea is that we lay out the mipmap levels within a block of + * memory organized as a rectangle of width BLIT_WIDTH_BYTES. + */ + t->tile_bits = 0; + + curOffset = 0; + + if (tObj->Target == GL_TEXTURE_CUBE_MAP) + { + ASSERT(log2Width == log2Height); + + for(i = 0; i < numLevels; i++) + { + /* i is hw level */ + GLuint face; + for(face = 0; face < 6; face++) + { + compute_tex_image_offset(tObj, face, i, &curOffset); + } + } + } + else + { + for (i = 0; i < numLevels; i++) + { + /* i is hw level */ + compute_tex_image_offset(tObj, 0, i, &curOffset); + } + } + + /* Align the total size of texture memory block. + */ + t->base.totalSize = (curOffset + R700_TEXTURE_ALIGNMENT_MASK) & ~R700_TEXTURE_ALIGNMENT_MASK; + + t->pitch = 0; + + /* TODO : baseImage->IsCompressed, tObj->Target == GL_TEXTURE_RECTANGLE_NV */ + + uTexelPitch = (tObj->Image[0][t->base.firstLevel]->Width + R700_TEXEL_PITCH_ALIGNMENT_MASK) + & ~R700_TEXEL_PITCH_ALIGNMENT_MASK; + + SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, (uTexelPitch/8)-1, PITCH_shift, PITCH_mask); + SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, tObj->Image[0][t->base.firstLevel]->Width - 1, + TEX_WIDTH_shift, TEX_WIDTH_mask); + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, tObj->Image[0][t->base.firstLevel]->Height - 1, + TEX_HEIGHT_shift, TEX_HEIGHT_mask); +} + +static void r700UploadSubImage(context_t *context, + r700TexObjPtr t, + GLint hwlevel, /* relative level to first real level. */ + GLint x, + GLint y, + GLuint face) +{ + struct gl_texture_image *texImage = NULL; + GLuint offset; + GLint imageWidth, imageHeight; + GLint ret; + const int level = hwlevel + t->base.firstLevel; + + unsigned char *pSrc; + + ASSERT(face < 6); + + /* Ensure we have a valid texture to upload */ + if ((hwlevel < 0) || (hwlevel >= RADEON_MAX_TEXTURE_LEVELS)) + { + _mesa_problem(NULL, "bad texture level in %s", __FUNCTION__); + return; + } + + texImage = t->base.tObj->Image[face][level]; + + if (!texImage) + { + return; + } + if (!texImage->Data) + { + return; + } + + if (t->base.tObj->Target == GL_TEXTURE_RECTANGLE_NV) + { + /* TODO : + assert(level == 0); + assert(hwlevel == 0); + + r300UploadRectSubImage(rmesa, t, texImage, x, y, width, height); + */ + return; + } + else if (texImage->IsClientData) + { + /* TODO : + r300UploadGARTClientSubImage(rmesa, t, texImage, hwlevel, x, y, + width, height); + */ + return; + } + + imageWidth = texImage->Width; + imageHeight = texImage->Height; + + /* use hwlevel for hwsurf. */ + offset = t->bufAddr + t->level_offset[face][hwlevel]; + + pSrc = (unsigned char*)(texImage->Data); + + (context->chipobj.LoadMemSurf)(context, + offset, /* gpu addr */ + t->texel_pitch[face][hwlevel], /* dst_pitch_in_pixel */ + t->src_width_in_pexel[face][hwlevel], /*src_width_in_pixel */ + t->src_hight_in_pexel[face][hwlevel], /* height */ + t->byte_per_texel, /* byte_per_pixel */ + pSrc); /* source data */ +} + +int r700UploadTexImages(GLcontext * ctx, struct gl_texture_object *tObj, GLuint face) +{ + context_t *context = R700_CONTEXT(ctx); + r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; + + int heap; + const int numLevels = t->base.lastLevel - t->base.firstLevel + 1; + + if (t->image_override) + { + return 0; + } + + if (t->base.totalSize == 0) + { + return 0; + } + /* TODO */ + /*LOCK_HARDWARE(&rmesa->radeon);*/ + + if (t->base.memBlock == NULL) + { + heap = RADEON_LOCAL_TEX_HEAP; + if( GL_FALSE == (context->chipobj.AllocMemSurf)(context, + &(t->base.memBlock), + &(t->base.heap), + &heap, /* prefered_heap, also return the actual heap used. */ + t->base.totalSize) ) + { + /* TODO */ + /* UNLOCK_HARDWARE(&rmesa->radeon); */ + return -1; + } + + /* Set the base offset of the texture image */ + t->bufAddr = context->screen->texOffset[heap] + t->base.memBlock->ofs; + t->offset = t->bufAddr; + + /* + if (!(t->base.tObj->Image[0][0]->IsClientData)) + { + t->offset |= t->tile_bits; + } + */ + } + + /* Let the world know we've used this memory recently. + */ + driUpdateTextureLRU((driTextureObject *) t); + + /* TODO */ + /* UNLOCK_HARDWARE(&rmesa->radeon); */ + + /* Upload any images that are new */ + if (t->my_dirty_images[face]) + { + int i; + for(i = 0; i < numLevels; i++) + { + if( (t->my_dirty_images[face] & (1 << (i + t->base.firstLevel))) !=0) + { + r700UploadSubImage(context, + t, + i, /* i is hw level */ + 0, + 0, + face); + } + } + t->base.dirty_images[face] = 0; + t->my_dirty_images[face] = 0; + } + + /* TODO : 3D, CUBE */ + t->texture_state.SQ_TEX_RESOURCE2.u32All = t->bufAddr / 256; + if( (t->base.lastLevel - t->base.firstLevel) > 0 ) + { + t->texture_state.SQ_TEX_RESOURCE3.u32All = (t->bufAddr + t->level_offset[0][1]) / 256; /* MIP_ADDRESS */ + + SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, t->base.firstLevel, BASE_LEVEL_shift, BASE_LEVEL_mask); + SETfield(t->texture_state.SQ_TEX_RESOURCE5.u32All, t->base.lastLevel, LAST_LEVEL_shift, LAST_LEVEL_mask); + } + + return 0; +} + +static GLboolean r700EnableTexture2D(GLcontext * ctx, int unit) +{ + context_t *context = R700_CONTEXT(ctx); + struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; + struct gl_texture_object *tObj = texUnit->_Current; + r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; + + ASSERT(tObj->Target == GL_TEXTURE_2D || tObj->Target == GL_TEXTURE_1D); + + if (t->base.dirty_images[0]) + { + r700SetTexImages(context, tObj); + r700UploadTexImages(ctx, tObj, 0); + if (!t->base.memBlock && !t->image_override) + { + return GL_FALSE; + } + } + return GL_TRUE; +} + +/* try to find a format which will only need a memcopy */ +static const struct gl_texture_format *r700Choose8888TexFormat(GLenum srcFormat, + GLenum srcType) +{ + struct gl_texture_format * gtfRet; + + const GLuint ui = 1; + const GLubyte littleEndian = *((const GLubyte *)&ui); + + if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8) || + (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && !littleEndian) || + (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || + (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && littleEndian)) + { + gtfRet = &_mesa_texformat_rgba8888; + } + else if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || + (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && littleEndian) || + (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8) || + (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && !littleEndian)) + { + gtfRet = &_mesa_texformat_rgba8888_rev; + } + else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && !littleEndian) || + srcType == GL_UNSIGNED_INT_8_8_8_8)) + { + gtfRet = &_mesa_texformat_argb8888_rev; + } + else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && littleEndian) || + srcType == GL_UNSIGNED_INT_8_8_8_8_REV)) + { + gtfRet = &_mesa_texformat_argb8888; + } + else + { + gtfRet = _dri_texformat_argb8888; + } + + return gtfRet; +} + +#endif /* to be enabled */ + +static r700TexObjPtr r700AllocTexObj(struct gl_texture_object *texObj) +{ + r700TexObjPtr t; + + t = CALLOC_STRUCT(r700_tex_obj); + texObj->DriverData = t; + if (t != NULL) + { +#if 0 /* to be enabled */ + /* Initialize non-image-dependent parts of the state: + */ + t->base.tObj = texObj; + t->border_fallback = GL_FALSE; + + make_empty_list(&t->base); + + /* Init text object to default states. */ + t->texture_state.SQ_TEX_RESOURCE0.u32All = 0; + SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, SQ_TEX_DIM_2D, DIM_shift, DIM_mask); + SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, ARRAY_LINEAR_GENERAL, + SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift, SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask); + CLEARbit(t->texture_state.SQ_TEX_RESOURCE0.u32All, TILE_TYPE_bit); + + t->texture_state.SQ_TEX_RESOURCE1.u32All = 0; + SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->texture_state.SQ_TEX_RESOURCE2.u32All = 0; + t->texture_state.SQ_TEX_RESOURCE3.u32All = 0; + + t->texture_state.SQ_TEX_RESOURCE4.u32All = 0; + SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_FORMAT_COMP_UNSIGNED, + FORMAT_COMP_X_shift, FORMAT_COMP_X_mask); + SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_FORMAT_COMP_UNSIGNED, + FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask); + SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_FORMAT_COMP_UNSIGNED, + FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask); + SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_FORMAT_COMP_UNSIGNED, + FORMAT_COMP_W_shift, FORMAT_COMP_W_mask); + SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_NUM_FORMAT_NORM, + SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift, SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_mask); + CLEARbit(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit); + CLEARbit(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit); + SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_ENDIAN_NONE, + SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift, SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_mask); + SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, 1, REQUEST_SIZE_shift, REQUEST_SIZE_mask); + t->texture_state.SQ_TEX_RESOURCE4.u32All |= SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift + |SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift + |SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift + |SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift; + SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, 0, BASE_LEVEL_shift, BASE_LEVEL_mask); /* mip-maps */ + + t->texture_state.SQ_TEX_RESOURCE5.u32All = 0; + + t->texture_state.SQ_TEX_RESOURCE6.u32All = 0; + + SETfield(t->texture_state.SQ_TEX_RESOURCE6.u32All, SQ_TEX_VTX_VALID_TEXTURE, + SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask); + + /* Initialize sampler registers */ + t->sampler_state.SQ_TEX_SAMPLER0.u32All = 0; + t->sampler_state.SQ_TEX_SAMPLER0.u32All |= + SQ_TEX_WRAP << SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift + |SQ_TEX_WRAP << CLAMP_Y_shift + |SQ_TEX_WRAP << CLAMP_Z_shift + |SQ_TEX_XY_FILTER_POINT << XY_MAG_FILTER_shift + |SQ_TEX_XY_FILTER_POINT << XY_MIN_FILTER_shift + |SQ_TEX_Z_FILTER_NONE << Z_FILTER_shift + |SQ_TEX_Z_FILTER_NONE << MIP_FILTER_shift + |SQ_TEX_BORDER_COLOR_TRANS_BLACK << BORDER_COLOR_TYPE_shift; + + t->sampler_state.SQ_TEX_SAMPLER1.u32All = 0x7FF << MAX_LOD_shift; + + t->sampler_state.SQ_TEX_SAMPLER2.u32All = 0; + SETbit(t->sampler_state.SQ_TEX_SAMPLER2.u32All, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit); +#endif /* to be enabled */ + } + + return t; +} + +static GLboolean +r700ValidateClientStorage(GLcontext * ctx, GLenum target, + GLint internalFormat, + GLint srcWidth, GLint srcHeight, + GLenum format, GLenum type, const void *pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + if (!ctx->Unpack.ClientStorage) + { + return 0; + } + + if (ctx->_ImageTransferState || + texImage->IsCompressed || texObj->GenerateMipmap) + { + return 0; + } + + /* This list is incomplete, may be different on ppc??? + */ + switch (internalFormat) + { + case GL_RGBA: + if (format == GL_BGRA && type == GL_UNSIGNED_INT_8_8_8_8_REV) + { + texImage->TexFormat = _dri_texformat_argb8888; + } + else + { + return 0; + } + break; + + case GL_RGB: + if (format == GL_RGB && type == GL_UNSIGNED_SHORT_5_6_5) + { + texImage->TexFormat = _dri_texformat_rgb565; + } + else + { + return 0; + } + break; + + case GL_YCBCR_MESA: + if (format == GL_YCBCR_MESA && + type == GL_UNSIGNED_SHORT_8_8_REV_APPLE) + { + texImage->TexFormat = &_mesa_texformat_ycbcr_rev; + } + else if( format == GL_YCBCR_MESA && + (type == GL_UNSIGNED_SHORT_8_8_APPLE || type == GL_UNSIGNED_BYTE)) + { + texImage->TexFormat = &_mesa_texformat_ycbcr; + } + else + { + return 0; + } + break; + + default: + return 0; + } + + /* Could deal with these packing issues, but currently don't: + */ + if (packing->SkipPixels || + packing->SkipRows || packing->SwapBytes || packing->LsbFirst) + { + return 0; + } + + GLint srcRowStride = _mesa_image_row_stride(packing, srcWidth, format, type); + + /* Have validated that _mesa_transfer_teximage would be a straight + * memcpy at this point. NOTE: future calls to TexSubImage will + * overwrite the client data. This is explicitly mentioned in the + * extension spec. + */ + texImage->Data = (void *)pixels; + texImage->IsClientData = GL_TRUE; + texImage->RowStride = srcRowStride / texImage->TexFormat->TexelBytes; + + return 1; +} + +static void r700TexImage1D(GLcontext * ctx, GLenum target, GLint level, + GLint internalFormat, + GLint width, GLint border, + GLenum format, GLenum type, const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ +} + +static void r700TexImage2D(GLcontext * ctx, GLenum target, GLint level, + GLint internalFormat, + GLint width, GLint height, GLint border, + GLenum format, GLenum type, const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ +#if 0 /* to be enabled */ + r700TexObjPtr r700t = (r700TexObjPtr) texObj->DriverData; + + driTextureObject *t = (driTextureObject *) texObj->DriverData; + GLuint face; + + /* which cube face or ordinary 2D image */ + switch (target) + { + case GL_TEXTURE_CUBE_MAP_POSITIVE_X: + case GL_TEXTURE_CUBE_MAP_NEGATIVE_X: + case GL_TEXTURE_CUBE_MAP_POSITIVE_Y: + case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y: + case GL_TEXTURE_CUBE_MAP_POSITIVE_Z: + case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z: + face = (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X; + ASSERT(face < 6); + break; + default: + face = 0; + } + + if (t != NULL) + { + driSwapOutTextureObject(t); + } + else + { + t = (driTextureObject *) r700AllocTexObj(texObj); + if (!t) + { + _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage2D"); + return; + } + } + + texImage->IsClientData = GL_FALSE; + + if (r700ValidateClientStorage(ctx, target, + internalFormat, + width, height, + format, type, pixels, + packing, texObj, texImage)) + { + /* client maintained surface */ + } + else + { + /* Normal path: copy (to cached memory) and eventually upload + * via another copy to GART memory and then a blit... Could + * eliminate one copy by going straight to (permanent) GART. + * + * Note, this will call r700ChooseTextureFormat. + */ + _mesa_store_teximage2d(ctx, target, level, internalFormat, + width, height, border, format, type, + pixels, &ctx->Unpack, texObj, texImage); + + t->dirty_images[face] |= (1 << level); + + /* mesa dirty_images is not correct, so use own one for now, review it later. */ + r700t->my_dirty_images[face] |= (1 << level); + } +#endif /* to be enabled */ +} + +static void r700TexImage3D(GLcontext * ctx, GLenum target, GLint level, + GLint internalFormat, + GLint width, GLint height, GLint depth, + GLint border, + GLenum format, GLenum type, const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ +} + +static void r700TexSubImage1D(GLcontext * ctx, GLenum target, GLint level, + GLint xoffset, + GLsizei width, + GLenum format, GLenum type, + const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ + +} + +static void r700TexSubImage2D(GLcontext * ctx, GLenum target, GLint level, + GLint xoffset, GLint yoffset, + GLsizei width, GLsizei height, + GLenum format, GLenum type, + const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ +} + +static void r700TexSubImage3D(GLcontext * ctx, GLenum target, GLint level, + GLint xoffset, GLint yoffset, GLint zoffset, + GLsizei width, GLsizei height, GLsizei depth, + GLenum format, GLenum type, + const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ +} + +/** + * Allocate a new texture object. + * Called via ctx->Driver.NewTextureObject. + * Note: this function will be called during context creation to + * allocate the default texture objects. + * Note: we could use containment here to 'derive' the driver-specific + * texture object from the core mesa gl_texture_object. Not done at this time. + */ +static struct gl_texture_object *r700NewTextureObject(GLcontext * ctx, + GLuint name, + GLenum target) +{ + context_t *context = R700_CONTEXT(ctx); + + struct gl_texture_object *obj; + + obj = _mesa_new_texture_object(ctx, name, target); + if (!obj) + { + return NULL; + } + + //obj->MaxAnisotropy = context->initialMaxAnisotropy; + + r700AllocTexObj(obj); + + return obj; +} + +static void r700BindTexture(GLcontext * ctx, GLenum target, + struct gl_texture_object *texObj) +{ + if ((target == GL_TEXTURE_1D) + || (target == GL_TEXTURE_2D) + || (target == GL_TEXTURE_3D) + || (target == GL_TEXTURE_CUBE_MAP) + || (target == GL_TEXTURE_RECTANGLE_NV)) + { + assert(texObj->DriverData != NULL); + } +} + +static void r700DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) +{ +} + +#if 0 /* to be enabled */ +static void r700SetTexMinFilter(r700TexObjPtr t, GLenum minf) +{ + switch (minf) + { + case GL_NEAREST: + + SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Point, + XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); + + SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_MipFilter_None, + MIP_FILTER_shift, MIP_FILTER_mask); + break; + case GL_LINEAR: + + SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Linear, + XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); + + SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_MipFilter_None, + MIP_FILTER_shift, MIP_FILTER_mask); + break; + case GL_NEAREST_MIPMAP_NEAREST: + + SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Point, + XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); + + SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_MipFilter_Point, + MIP_FILTER_shift, MIP_FILTER_mask); + break; + case GL_LINEAR_MIPMAP_NEAREST: + + SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Linear, + XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); + + SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_MipFilter_Point, + MIP_FILTER_shift, MIP_FILTER_mask); + break; + case GL_NEAREST_MIPMAP_LINEAR: + + SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Point, + XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); + + SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_MipFilter_Linear, + MIP_FILTER_shift, MIP_FILTER_mask); + break; + case GL_LINEAR_MIPMAP_LINEAR: + + SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Linear, + XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); + + SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_MipFilter_Linear, + MIP_FILTER_shift, MIP_FILTER_mask); + break; + default: + /* no case */ + break; + } +} + +static void r700SetTexMagFilter(r700TexObjPtr t, GLenum magf) +{ + switch(magf) + { + case GL_NEAREST: + + SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Point, + XY_MAG_FILTER_shift, XY_MAG_FILTER_mask); + + break; + case GL_LINEAR: + + SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Linear, + XY_MAG_FILTER_shift, XY_MAG_FILTER_mask); + + break; + default: + break; + } +} + +static unsigned int r700GetWrapMode(GLenum wrapmode) +{ + switch(wrapmode) + { + case GL_REPEAT: + return SQ_TEX_WRAP; + case GL_CLAMP: + return SQ_TEX_CLAMP_HALF_BORDER; + case GL_CLAMP_TO_EDGE: + return SQ_TEX_CLAMP_LAST_TEXEL; + case GL_CLAMP_TO_BORDER: + return SQ_TEX_CLAMP_BORDER; + case GL_MIRRORED_REPEAT: + return SQ_TEX_MIRROR_ONCE_HALF_BORDER; + case GL_MIRROR_CLAMP_EXT: + return SQ_TEX_MIRROR; + case GL_MIRROR_CLAMP_TO_EDGE_EXT: + return SQ_TEX_MIRROR_ONCE_BORDER; + case GL_MIRROR_CLAMP_TO_BORDER_EXT: + return SQ_TEX_MIRROR_ONCE_LAST_TEXEL; + default: + _mesa_problem(NULL, "bad wrap mode in %s", __FUNCTION__); + return 0; + } +} +#endif /* to be enabled */ + +static void r700TexParameter(GLcontext * ctx, GLenum target, + struct gl_texture_object *texObj, + GLenum pname, const GLfloat * params) +{ + r700TexObjPtr t = (r700TexObjPtr) texObj->DriverData; +#if 0 /* to be enabled */ + switch (pname) + { + case GL_TEXTURE_MIN_FILTER: + r700SetTexMinFilter(t, texObj->MinFilter); + break; + case GL_TEXTURE_MAG_FILTER: + r700SetTexMagFilter(t, texObj->MagFilter); + break; + case GL_TEXTURE_MAX_ANISOTROPY_EXT: + + r700SetTexMinFilter(t, texObj->MinFilter); + r700SetTexMagFilter(t, texObj->MagFilter); + + break; + + case GL_TEXTURE_WRAP_S: + SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, r700GetWrapMode(texObj->WrapS), + SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift, SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask); + break; + case GL_TEXTURE_WRAP_T: + SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, r700GetWrapMode(texObj->WrapT), + CLAMP_Y_shift, CLAMP_Y_mask); + break; + case GL_TEXTURE_WRAP_R: + SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, r700GetWrapMode(texObj->WrapR), + CLAMP_Z_shift, CLAMP_Z_mask); + break; + + case GL_TEXTURE_BORDER_COLOR: + /* TODO : set border color regs before rendering. */ + SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, SQ_TEX_BORDER_COLOR_REGISTER, + BORDER_COLOR_TYPE_shift, BORDER_COLOR_TYPE_mask); + break; + + case GL_TEXTURE_BASE_LEVEL: + case GL_TEXTURE_MAX_LEVEL: + case GL_TEXTURE_MIN_LOD: + case GL_TEXTURE_MAX_LOD: + /* TODO : we do support this, add it later. */ + driSwapOutTextureObject((driTextureObject *) t); + break; + + case GL_DEPTH_TEXTURE_MODE: + if (!texObj->Image[0][texObj->BaseLevel]) + { + return; + } + if (texObj->Image[0][texObj->BaseLevel]->TexFormat->BaseFormat + == GL_DEPTH_COMPONENT) + { + /* TODO : r700SetDepthTexMode(texObj); */ + break; + } + else + { + /* If not depth texture, just return. */ + return; + } + + default: + return; + } +#endif /* to be enabled */ +} + +static void r700CompressedTexImage2D(GLcontext * ctx, GLenum target, + GLint level, GLint internalFormat, + GLint width, GLint height, GLint border, + GLsizei imageSize, const GLvoid * data, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ +} + +static void r700CompressedTexSubImage2D(GLcontext * ctx, GLenum target, + GLint level, GLint xoffset, + GLint yoffset, GLsizei width, + GLsizei height, GLenum format, + GLsizei imageSize, const GLvoid * data, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage) +{ +} + +static GLboolean r700UpdateTextureUnit(GLcontext * ctx, int unit) +{ + return GL_TRUE; +} + +static GLboolean r700EnableTextureRect(GLcontext * ctx, int unit) +{ + return GL_TRUE; +} + +static GLboolean r700EnableTexture3D(GLcontext * ctx, int unit) +{ + return GL_TRUE; +} + +static GLboolean r700EnableTextureCube(GLcontext * ctx, int unit) +{ + return GL_TRUE; +} + +static GLboolean r700UpdateTexture(GLcontext * ctx, int unit) +{ +#if 0 /* to be enabled */ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + + struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; + struct gl_texture_object *tObj = texUnit->_Current; + r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; + + if( r700->texture_states.textures[unit] != &(t->texture_state) ) + { + if(NULL != r700->texture_states.textures[unit]) + { /* there is an old one. */ + } + + r700->texture_states.textures[unit] = &(t->texture_state); + r700->texture_states.samplers[unit] = &(t->sampler_state); + driUpdateTextureLRU((driTextureObject *) t); /* XXX: should be locked! */ + } +#endif /* to be enabled */ + + return GL_TRUE; +} + +void r700UpdateTextureState(context_t * context) +{ +#if 0 /* to be enabled */ + GLboolean bRet; + GLuint unit; + GLcontext * ctx = context->ctx; + struct gl_texture_unit *texUnit; + + for (unit = 0; unit < 8; unit++) + { + texUnit = &ctx->Texture.Unit[unit]; + + if (texUnit->_ReallyEnabled & (TEXTURE_RECT_BIT)) + { + bRet = (r700EnableTextureRect(ctx, unit) && + r700UpdateTexture(ctx, unit)); + } + else if (texUnit->_ReallyEnabled & (TEXTURE_1D_BIT | TEXTURE_2D_BIT)) + { + bRet = (r700EnableTexture2D(ctx, unit) && + r700UpdateTexture(ctx, unit)); + } + else if (texUnit->_ReallyEnabled & (TEXTURE_3D_BIT)) + { + bRet = (r700EnableTexture3D(ctx, unit) && + r700UpdateTexture(ctx, unit)); + } + else if (texUnit->_ReallyEnabled & (TEXTURE_CUBE_BIT)) + { + bRet = (r700EnableTextureCube(ctx, unit) && + r700UpdateTexture(ctx, unit)); + } + else if (texUnit->_ReallyEnabled) + { + bRet = GL_FALSE; + } + else + { + bRet = GL_TRUE; + } + + if (!bRet) + { + _mesa_warning(ctx, "failed to update texture state for unit %d.\n", unit); + } + } +#endif /* to be enabled */ +} + +void r700InitTextureFuncs(struct dd_function_table *functions) +{ + /* Note: we only plug in the functions we implement in the driver + * since _mesa_init_driver_functions() was already called. + */ + functions->ChooseTextureFormat = radeonChooseTextureFormat_mesa; + functions->TexImage1D = r700TexImage1D; + functions->TexImage2D = r700TexImage2D; + functions->TexImage3D = r700TexImage3D; + functions->TexSubImage1D = r700TexSubImage1D; + functions->TexSubImage2D = r700TexSubImage2D; + functions->TexSubImage3D = r700TexSubImage3D; + functions->NewTextureObject = r700NewTextureObject; + functions->BindTexture = r700BindTexture; + functions->DeleteTexture = r700DeleteTexture; + functions->IsTextureResident = driIsTextureResident; + + functions->TexParameter = r700TexParameter; + + functions->CompressedTexImage2D = r700CompressedTexImage2D; + functions->CompressedTexSubImage2D = r700CompressedTexSubImage2D; + + driInitTextureFormats(); +} + + diff --git a/src/mesa/drivers/dri/r600/r700_tex.h b/src/mesa/drivers/dri/r600/r700_tex.h new file mode 100644 index 0000000000..13290578a1 --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_tex.h @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + */ + +#ifndef __r700_TEX_H__ +#define __r700_TEX_H__ + +#include "texmem.h" + +#include "r700_chip.h" + +/* TODO : review this after texture load code. */ +#define R700_BLIT_WIDTH_BYTES 1024 +/* The BASE_ADDRESS and MIP_ADDRESS fields are 256-byte-aligned */ +#define R700_TEXTURE_ALIGNMENT_MASK 0x255 +/* Texel pitch is 8 alignment. */ +#define R700_TEXEL_PITCH_ALIGNMENT_MASK 0x7 + +#define R700_MAX_TEXTURE_UNITS 8 /* TODO : should be 16, lets make it work, review later */ + +typedef struct r700_tex_obj r700TexObj, *r700TexObjPtr; + +/* Texture object in locally shared texture space. + */ +struct r700_tex_obj +{ + driTextureObject base; + + /* r300 tex obj */ + GLuint bufAddr; + GLboolean image_override; + GLuint pitch; + GLuint filter; + GLuint filter_1; + GLuint pitch_reg; + GLuint size; + GLuint format; + GLuint offset; + GLuint unknown4; + GLuint unknown5; + GLboolean border_fallback; + GLuint tile_bits; + + /* r700 texture states */ + TEXTURE_STATE_STRUCT texture_state; + SAMPLER_STATE_STRUCT sampler_state; + + GLuint texel_pitch[6][RADEON_MAX_TEXTURE_LEVELS]; + GLuint level_offset[6][RADEON_MAX_TEXTURE_LEVELS]; + GLuint byte_per_texel; + GLuint src_width_in_pexel[6][RADEON_MAX_TEXTURE_LEVELS]; + GLuint src_hight_in_pexel[6][RADEON_MAX_TEXTURE_LEVELS]; + + GLuint my_dirty_images[6]; /* TODO : review */ +}; + +extern void r700SetTexBuffer(__DRIcontext *pDRICtx, GLint target, + __DRIdrawable *dPriv); + +extern void r700SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, + GLint format, __DRIdrawable *dPriv); + +extern void r700SetTexOffset(__DRIcontext *pDRICtx, GLint texname, + unsigned long long offset, GLint depth, + GLuint pitch); + +extern GLuint r700GetTexObjSize(void); +extern void r700UpdateTextureState(context_t * context); + +extern void r700SetTexOffset(__DRIcontext *pDRICtx, + GLint texname, + unsigned long long offset, + GLint depth, + GLuint pitch); + +extern void r700DestroyTexObj(context_t rmesa, r700TexObjPtr t); + +extern void r700InitTextureFuncs(struct dd_function_table *functions); + +#endif /* __r700_TEX_H__ */ diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c new file mode 100644 index 0000000000..22a12a00d1 --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -0,0 +1,466 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + */ + + +#include +#include +#include +#include +#include + +#include "main/imports.h" +#include "main/mtypes.h" + +#include "tnl/t_context.h" +#include "shader/prog_parameter.h" +#include "shader/prog_statevars.h" + +#include "r600_context.h" + +#include "r700_chip.h" +#include "r700_debug.h" +#include "r700_vertprog.h" + +#if 0 /* to be enabled */ +#include "r700_emit.h" +#endif + +unsigned int Map_Vertex_Output(r700_AssemblerBase *pAsm, + struct gl_vertex_program *mesa_vp, + unsigned int unStart) +{ + unsigned int i; + unsigned int unBit; + unsigned int unTotal = unStart; + + //!!!!!!! THE ORDER MATCH FS INPUT + + unBit = 1 << VERT_RESULT_HPOS; + if(mesa_vp->Base.OutputsWritten & unBit) + { + pAsm->ucVP_OutputMap[VERT_RESULT_HPOS] = unTotal++; + } + + unBit = 1 << VERT_RESULT_COL0; + if(mesa_vp->Base.OutputsWritten & unBit) + { + pAsm->ucVP_OutputMap[VERT_RESULT_COL0] = unTotal++; + } + + unBit = 1 << VERT_RESULT_COL1; + if(mesa_vp->Base.OutputsWritten & unBit) + { + pAsm->ucVP_OutputMap[VERT_RESULT_COL1] = unTotal++; + } + + //TODO : dealing back face. + //unBit = 1 << VERT_RESULT_BFC0; + //if(mesa_vp->Base.OutputsWritten & unBit) + //{ + // pAsm->ucVP_OutputMap[VERT_RESULT_COL0] = unTotal++; + //} + + //unBit = 1 << VERT_RESULT_BFC1; + //if(mesa_vp->Base.OutputsWritten & unBit) + //{ + // pAsm->ucVP_OutputMap[VERT_RESULT_COL1] = unTotal++; + //} + + //TODO : dealing fog. + //unBit = 1 << VERT_RESULT_FOGC; + //if(mesa_vp->Base.OutputsWritten & unBit) + //{ + // pAsm->ucVP_OutputMap[VERT_RESULT_FOGC] = unTotal++; + //} + + //TODO : dealing point size. + //unBit = 1 << VERT_RESULT_PSIZ; + //if(mesa_vp->Base.OutputsWritten & unBit) + //{ + // pAsm->ucVP_OutputMap[VERT_RESULT_PSIZ] = unTotal++; + //} + + for(i=0; i<8; i++) + { + unBit = 1 << (VERT_RESULT_TEX0 + i); + if(mesa_vp->Base.OutputsWritten & unBit) + { + pAsm->ucVP_OutputMap[VERT_RESULT_TEX0 + i] = unTotal++; + } + } + + return (unTotal - unStart); +} + +unsigned int Map_Vertex_Input(r700_AssemblerBase *pAsm, + struct gl_vertex_program *mesa_vp, + unsigned int unStart) +{ + int i; + unsigned int unBit; + unsigned int unTotal = unStart; + for(i=0; iBase.InputsRead & unBit) + { + pAsm->ucVP_AttributeMap[i] = unTotal++; + } + } + return (unTotal - unStart); +} + +GLboolean Process_Vertex_Program_Vfetch_Instructions( + struct r700_vertex_program *vp, + struct gl_vertex_program *mesa_vp) +{ + int i; + unsigned int unBit; + VTX_FETCH_METHOD vtxFetchMethod; + vtxFetchMethod.bEnableMini = GL_FALSE; + vtxFetchMethod.mega_fetch_remainder = 0; + + for(i=0; iBase.InputsRead & unBit) + { + assemble_vfetch_instruction(&vp->r700AsmCode, + i, + vp->r700AsmCode.ucVP_AttributeMap[i], + vp->aos_desc[i].size, + vp->aos_desc[i].type, + &vtxFetchMethod); + } + } + + return GL_TRUE; +} + +void Map_Vertex_Program(struct r700_vertex_program *vp, + struct gl_vertex_program *mesa_vp) +{ + GLuint ui; + r700_AssemblerBase *pAsm = &(vp->r700AsmCode); + unsigned int num_inputs; + + // R0 will always be used for index into vertex buffer + pAsm->number_used_registers = 1; + pAsm->starting_vfetch_register_number = pAsm->number_used_registers; + + // Map Inputs: Add 1 to mapping since R0 is used for index + num_inputs = Map_Vertex_Input(pAsm, mesa_vp, pAsm->number_used_registers); + pAsm->number_used_registers += num_inputs; + + // Create VFETCH instructions for inputs + if (GL_TRUE != Process_Vertex_Program_Vfetch_Instructions(vp, mesa_vp) ) + { + r700_error(ERROR_ASM_VTX_CLAUSE, "Calling Process_Vertex_Program_Vfetch_Instructions return error. \n"); + return; //error + } + + // Map Outputs + pAsm->number_of_exports = Map_Vertex_Output(pAsm, mesa_vp, pAsm->number_used_registers); + + pAsm->starting_export_register_number = pAsm->number_used_registers; + + pAsm->number_used_registers += pAsm->number_of_exports; + + pAsm->pucOutMask = (unsigned char*) MALLOC(pAsm->number_of_exports); + + for(ui=0; uinumber_of_exports; ui++) + { + pAsm->pucOutMask[ui] = 0x0; + } + + /* Map temporary registers (GPRs) */ + pAsm->starting_temp_register_number = pAsm->number_used_registers; + + if(mesa_vp->Base.NumNativeTemporaries >= mesa_vp->Base.NumTemporaries) + { /* arb uses NumNativeTemporaries */ + pAsm->number_used_registers += mesa_vp->Base.NumNativeTemporaries; + } + else + { /* fix func t_vp uses NumTemporaries */ + pAsm->number_used_registers += mesa_vp->Base.NumTemporaries; + } + + pAsm->uFirstHelpReg = pAsm->number_used_registers; +} + +GLboolean Find_Instruction_Dependencies_vp(struct r700_vertex_program *vp, + struct gl_vertex_program *mesa_vp) +{ + GLuint i, j; + GLint * puiTEMPwrites; + struct prog_instruction *pILInst; + InstDeps *pInstDeps; + + puiTEMPwrites = (GLint*) MALLOC(sizeof(GLuint)*mesa_vp->Base.NumTemporaries); + for(i=0; iBase.NumTemporaries; i++) + { + puiTEMPwrites[i] = -1; + } + + pInstDeps = (InstDeps*)MALLOC(sizeof(InstDeps)*mesa_vp->Base.NumInstructions); + + for(i=0; iBase.NumInstructions; i++) + { + pInstDeps[i].nDstDep = -1; + pILInst = &(mesa_vp->Base.Instructions[i]); + + //Dst + if(pILInst->DstReg.File == PROGRAM_TEMPORARY) + { + //Set lastwrite for the temp + puiTEMPwrites[pILInst->DstReg.Index] = i; + } + + //Src + for(j=0; j<3; j++) + { + if(pILInst->SrcReg[j].File == PROGRAM_TEMPORARY) + { + //Set dep. + pInstDeps[i].nSrcDeps[j] = puiTEMPwrites[pILInst->SrcReg[j].Index]; + } + else + { + pInstDeps[i].nSrcDeps[j] = -1; + } + } + } + + vp->r700AsmCode.pInstDeps = pInstDeps; + + FREE(puiTEMPwrites); + + return GL_TRUE; +} + +GLboolean r700TranslateVertexShader(struct r700_vertex_program *vp, + struct gl_vertex_program *mesa_vp) +{ + //Init_Program + Init_r700_AssemblerBase(SPT_VP, &(vp->r700AsmCode), &(vp->r700Shader) ); + Map_Vertex_Program( vp, mesa_vp ); + + if(GL_FALSE == Find_Instruction_Dependencies_vp(vp, mesa_vp)) + { + return GL_FALSE; + } + + if(GL_FALSE == AssembleInstr(mesa_vp->Base.NumInstructions, + &(mesa_vp->Base.Instructions[0]), + &(vp->r700AsmCode)) ) + { + return GL_FALSE; + } + + if(GL_FALSE == Process_Vertex_Exports(&(vp->r700AsmCode), mesa_vp->Base.OutputsWritten) ) + { + return GL_FALSE; + } + + vp->r700Shader.nRegs = (vp->r700AsmCode.number_used_registers == 0) ? 0 + : (vp->r700AsmCode.number_used_registers - 1); + + vp->r700Shader.nParamExports = vp->r700AsmCode.number_of_exports; + + vp->translated = GL_TRUE; + + return GL_TRUE; +} + +void r700SelectVertexShader(GLcontext *ctx) +{ +#if 0 /* to be enabled */ + context_t *context = R700_CONTEXT(ctx); + struct r700_vertex_program *vpc + = (struct r700_vertex_program *)ctx->VertexProgram._Current; + if (context->screen->chip.type <= CHIP_TYPE_RV670) + { + vpc->r700AsmCode.bR6xx = 1; + } + + TNLcontext *tnl = TNL_CONTEXT(ctx); + struct vertex_buffer *vb = &tnl->vb; + + unsigned int unBit; + unsigned int i; + for(i=0; imesa_program.Base.InputsRead & unBit) /* ctx->Array.ArrayObj->xxxxxxx */ + { + vpc->aos_desc[i].size = vb->AttribPtr[i]->size; + vpc->aos_desc[i].stride = vb->AttribPtr[i]->size * sizeof(GL_FLOAT);/* when emit array, data is packed. vb->AttribPtr[i]->stride;*/ + vpc->aos_desc[i].type = GL_FLOAT; + } + } + + if(GL_FALSE == vpc->translated) + { + r700TranslateVertexShader(vpc, + &(vpc->mesa_program) ); + } +#endif /* to be enabled */ +} + +void r700SetupVTXConstans(GLcontext * ctx, + unsigned int nStreamID, + unsigned int aos_offset, + unsigned int size, /* number of elements in vector */ + unsigned int stride, + unsigned int count) /* number of vectors in stream */ +{ + context_t *context = R700_CONTEXT(ctx); + uint32_t *dest; + + unsigned int uSQ_VTX_CONSTANT_WORD0_0; + unsigned int uSQ_VTX_CONSTANT_WORD1_0; + unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0; + unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0; + unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0; + + uSQ_VTX_CONSTANT_WORD0_0 = aos_offset; + uSQ_VTX_CONSTANT_WORD1_0 = count * stride - 1; + + uSQ_VTX_CONSTANT_WORD2_0 |= 0 << BASE_ADDRESS_HI_shift /* TODO */ + |stride << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift + |GetSurfaceFormat(GL_FLOAT, size, NULL) << SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift /* TODO : trace back api for initial data type, not only GL_FLOAT */ + |SQ_NUM_FORMAT_SCALED << SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift + |SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit; + + uSQ_VTX_CONSTANT_WORD3_0 |= 1 << MEM_REQUEST_SIZE_shift; + + uSQ_VTX_CONSTANT_WORD6_0 |= SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift; +#if 0 /* to be enabled */ + R700_CMDBUF_CHECK_SPACE(9); + R700EP3 (context, IT_SET_RESOURCE, 7); + R700E32 (context, (nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE); + + R700E32 (context, uSQ_VTX_CONSTANT_WORD0_0); + R700E32 (context, uSQ_VTX_CONSTANT_WORD1_0); + R700E32 (context, uSQ_VTX_CONSTANT_WORD2_0); + R700E32 (context, uSQ_VTX_CONSTANT_WORD3_0); + R700E32 (context, 0); + R700E32 (context, 0); + R700E32 (context, uSQ_VTX_CONSTANT_WORD6_0); +#endif /* to be enabled */ +} + +GLboolean r700SetupVertexProgram(GLcontext * ctx) +{ + context_t *context = R700_CONTEXT(ctx); + + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + + struct r700_vertex_program *vp + = (struct r700_vertex_program *)ctx->VertexProgram._Current; + + struct gl_program_parameter_list *paramList; + unsigned int unNumParamData; + + unsigned int ui; + + if(GL_FALSE == vp->loaded) + { + if(vp->r700Shader.bNeedsAssembly == GL_TRUE) + { + Assemble( &(vp->r700Shader) ); + } + + /* Load vp to gpu */ + (context->chipobj.EmitShader)(ctx, + &(vp->shadercode), + (GLvoid *)(vp->r700Shader.pProgram), + vp->r700Shader.uShaderBinaryDWORDSize); + + vp->loaded = GL_TRUE; + } + + DumpHwBinary(DUMP_VERTEX_SHADER, (GLvoid *)(vp->r700Shader.pProgram), + vp->r700Shader.uShaderBinaryDWORDSize); + + /* TODO : enable this after MemUse fixed *= + (context->chipobj.MemUse)(context, vp->shadercode.buf->id); + */ + + r700->SQ_PGM_START_VS.u32All = (vp->shadercode.aos_offset >> 8) & 0x00FFFFFF; + + SETfield(r700->SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.nRegs + 1, + NUM_GPRS_shift, NUM_GPRS_mask); + + if(vp->r700Shader.uStackSize) /* we don't use branch for now, it should be zero. */ + { + SETfield(r700->SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.uStackSize, + STACK_SIZE_shift, STACK_SIZE_mask); + } + + SETfield(r700->SPI_VS_OUT_CONFIG.u32All, vp->r700Shader.nParamExports - 1, + VS_EXPORT_COUNT_shift, VS_EXPORT_COUNT_mask); + SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, vp->r700Shader.nParamExports, + NUM_INTERP_shift, NUM_INTERP_mask); + + /* + SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit); + CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit); + */ + + /* sent out shader constants. */ + + paramList = vp->mesa_program.Base.Parameters; + + if(NULL != paramList) + { + _mesa_load_state_parameters(ctx, paramList); +#if 0 /* to be enabled */ + unNumParamData = paramList->NumParameters * 4; + + R700_CMDBUF_CHECK_SPACE(unNumParamData + 2); + R700EP3 (context, IT_SET_ALU_CONST, unNumParamData); + /* assembler map const from very beginning. */ + R700E32 (context, SQ_ALU_CONSTANT_VS_OFFSET * 4); + + unNumParamData = paramList->NumParameters; + + for(ui=0; uiParameterValues[ui][0]))); + R700E32 (context, *((unsigned int*)&(paramList->ParameterValues[ui][1]))); + R700E32 (context, *((unsigned int*)&(paramList->ParameterValues[ui][2]))); + R700E32 (context, *((unsigned int*)&(paramList->ParameterValues[ui][3]))); + } +#endif /* to be enabled */ + } + + return GL_TRUE; +} + + + + diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.h b/src/mesa/drivers/dri/r600/r700_vertprog.h new file mode 100644 index 0000000000..0822335c10 --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_vertprog.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + */ + + +#ifndef _R700_VERTPROG_H_ +#define _R700_VERTPROG_H_ + +#include "main/glheader.h" +#include "main/mtypes.h" + +#include "r700_shader.h" +#include "r700_assembler.h" + +typedef struct ArrayDesc //TEMP +{ + GLint size; //number of data element + GLenum type; //data element type + GLsizei stride; +} ArrayDesc; + +struct r700_vertex_program +{ + struct gl_vertex_program mesa_program; /* Must be first */ + + struct r700_vertex_program *next; + + r700_AssemblerBase r700AsmCode; + R700_Shader r700Shader; + + GLboolean translated; + GLboolean loaded; + + /* ... */ + + struct r600_dma_region shadercode; + ArrayDesc aos_desc[VERT_ATTRIB_MAX]; +}; + +//Internal +unsigned int Map_Vertex_Output(r700_AssemblerBase *pAsm, + struct gl_vertex_program *mesa_vp, + unsigned int unStart); +unsigned int Map_Vertex_Input(r700_AssemblerBase *pAsm, + struct gl_vertex_program *mesa_vp, + unsigned int unStart); +GLboolean Process_Vertex_Program_Vfetch_Instructions( + struct r700_vertex_program *vp, + struct gl_vertex_program *mesa_vp); +void Map_Vertex_Program(struct r700_vertex_program *vp, + struct gl_vertex_program *mesa_vp); +GLboolean Find_Instruction_Dependencies_vp(struct r700_vertex_program *vp, + struct gl_vertex_program *mesa_vp); + +/* Interface */ +extern GLboolean r700TranslateVertexShader(struct r700_vertex_program *vp, + struct gl_vertex_program *mesa_vp); + +extern void r700SelectVertexShader(GLcontext *ctx); + +extern GLboolean r700SetupVertexProgram(GLcontext * ctx); + +extern void r700SetupVTXConstans(GLcontext * ctx, + unsigned int nStreamID, + unsigned int aos_offset, + unsigned int size, /* number of elements in vector */ + unsigned int stride, + unsigned int Count); /* number of vectors in stream */ + +#endif /* _R700_VERTPROG_H_ */ diff --git a/src/mesa/drivers/dri/r600/sq_micro_reg.h b/src/mesa/drivers/dri/r600/sq_micro_reg.h new file mode 100644 index 0000000000..bfd21cef62 --- /dev/null +++ b/src/mesa/drivers/dri/r600/sq_micro_reg.h @@ -0,0 +1,2008 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Contacts: + * Richard Li , + */ + +#if !defined (_SQ_MICRO_REG_H) +#define _SQ_MICRO_REG_H + +#if defined(LITTLEENDIAN_CPU) +#elif defined(BIGENDIAN_CPU) +#else +#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined" +#endif + +/* + * SQ_ALU_SRC_GPR_BASE value + */ + +#define SQ_ALU_SRC_GPR_BASE 0x00000000 + +/* + * SQ_ALU_SRC_GPR_SIZE value + */ + +#define SQ_ALU_SRC_GPR_SIZE 0x00000080 + +/* + * SQ_ALU_SRC_KCACHE0_BASE value + */ + +#define SQ_ALU_SRC_KCACHE0_BASE 0x00000080 + +/* + * SQ_ALU_SRC_KCACHE0_SIZE value + */ + +#define SQ_ALU_SRC_KCACHE0_SIZE 0x00000020 + +/* + * SQ_ALU_SRC_KCACHE1_BASE value + */ + +#define SQ_ALU_SRC_KCACHE1_BASE 0x000000a0 + +/* + * SQ_ALU_SRC_KCACHE1_SIZE value + */ + +#define SQ_ALU_SRC_KCACHE1_SIZE 0x00000020 + +/* + * SQ_ALU_SRC_CFILE_BASE value + */ + +#define SQ_ALU_SRC_CFILE_BASE 0x00000100 + +/* + * SQ_ALU_SRC_CFILE_SIZE value + */ + +#define SQ_ALU_SRC_CFILE_SIZE 0x00000100 + +/* + * SQ_SP_OP_REDUC_BEGIN value + */ + +#define SQ_SP_OP_REDUC_BEGIN 0x00000050 + +/* + * SQ_SP_OP_REDUC_END value + */ + +#define SQ_SP_OP_REDUC_END 0x00000053 + +/* + * SQ_SP_OP_TRANS_BEGIN value + */ + +#define SQ_SP_OP_TRANS_BEGIN 0x00000060 + +/* + * SQ_SP_OP_TRANS_END value + */ + +#define SQ_SP_OP_TRANS_END 0x0000007f + +/* + * SQ_CF_WORD0 struct + */ + +#define SQ_CF_WORD0_ADDR_SIZE 32 + +#define SQ_CF_WORD0_ADDR_SHIFT 0 + +#define SQ_CF_WORD0_ADDR_MASK 0xffffffff + +#define SQ_CF_WORD0_MASK \ + (SQ_CF_WORD0_ADDR_MASK) + +#define SQ_CF_WORD0_DEFAULT 0xcdcdcdcd + +#define SQ_CF_WORD0_GET_ADDR(sq_cf_word0) \ + ((sq_cf_word0 & SQ_CF_WORD0_ADDR_MASK) >> SQ_CF_WORD0_ADDR_SHIFT) + +#define SQ_CF_WORD0_SET_ADDR(sq_cf_word0_reg, addr) \ + sq_cf_word0_reg = (sq_cf_word0_reg & ~SQ_CF_WORD0_ADDR_MASK) | (addr << SQ_CF_WORD0_ADDR_SHIFT) + +#if defined(LITTLEENDIAN_CPU) + + typedef struct _sq_cf_word0_t { + unsigned int addr : SQ_CF_WORD0_ADDR_SIZE; + } sq_cf_word0_t; + +#elif defined(BIGENDIAN_CPU) + + typedef struct _sq_cf_word0_t { + unsigned int addr : SQ_CF_WORD0_ADDR_SIZE; + } sq_cf_word0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_word0_t f; +} sq_cf_word0_u; + + +/* + * SQ_CF_WORD1 struct + */ + +#define SQ_CF_WORD1_POP_COUNT_SIZE 3 +#define SQ_CF_WORD1_CF_CONST_SIZE 5 +#define SQ_CF_WORD1_COND_SIZE 2 +#define SQ_CF_WORD1_COUNT_SIZE 3 +#define SQ_CF_WORD1_CALL_COUNT_SIZE 6 +#define SQ_CF_WORD1_COUNT_3_SIZE 1 +#define SQ_CF_WORD1_END_OF_PROGRAM_SIZE 1 +#define SQ_CF_WORD1_VALID_PIXEL_MODE_SIZE 1 +#define SQ_CF_WORD1_CF_INST_SIZE 7 +#define SQ_CF_WORD1_WHOLE_QUAD_MODE_SIZE 1 +#define SQ_CF_WORD1_BARRIER_SIZE 1 + +#define SQ_CF_WORD1_POP_COUNT_SHIFT 0 +#define SQ_CF_WORD1_CF_CONST_SHIFT 3 +#define SQ_CF_WORD1_COND_SHIFT 8 +#define SQ_CF_WORD1_COUNT_SHIFT 10 +#define SQ_CF_WORD1_CALL_COUNT_SHIFT 13 +#define SQ_CF_WORD1_COUNT_3_SHIFT 19 +#define SQ_CF_WORD1_END_OF_PROGRAM_SHIFT 21 +#define SQ_CF_WORD1_VALID_PIXEL_MODE_SHIFT 22 +#define SQ_CF_WORD1_CF_INST_SHIFT 23 +#define SQ_CF_WORD1_WHOLE_QUAD_MODE_SHIFT 30 +#define SQ_CF_WORD1_BARRIER_SHIFT 31 + +#define SQ_CF_WORD1_POP_COUNT_MASK 0x00000007 +#define SQ_CF_WORD1_CF_CONST_MASK 0x000000f8 +#define SQ_CF_WORD1_COND_MASK 0x00000300 +#define SQ_CF_WORD1_COUNT_MASK 0x00001c00 +#define SQ_CF_WORD1_CALL_COUNT_MASK 0x0007e000 +#define SQ_CF_WORD1_COUNT_3_MASK 0x00080000 +#define SQ_CF_WORD1_END_OF_PROGRAM_MASK 0x00200000 +#define SQ_CF_WORD1_VALID_PIXEL_MODE_MASK 0x00400000 +#define SQ_CF_WORD1_CF_INST_MASK 0x3f800000 +#define SQ_CF_WORD1_WHOLE_QUAD_MODE_MASK 0x40000000 +#define SQ_CF_WORD1_BARRIER_MASK 0x80000000 + +#define SQ_CF_WORD1_MASK \ + (SQ_CF_WORD1_POP_COUNT_MASK | \ + SQ_CF_WORD1_CF_CONST_MASK | \ + SQ_CF_WORD1_COND_MASK | \ + SQ_CF_WORD1_COUNT_MASK | \ + SQ_CF_WORD1_CALL_COUNT_MASK | \ + SQ_CF_WORD1_COUNT_3_MASK | \ + SQ_CF_WORD1_END_OF_PROGRAM_MASK | \ + SQ_CF_WORD1_VALID_PIXEL_MODE_MASK | \ + SQ_CF_WORD1_CF_INST_MASK | \ + SQ_CF_WORD1_WHOLE_QUAD_MODE_MASK | \ + SQ_CF_WORD1_BARRIER_MASK) + +#define SQ_CF_WORD1_DEFAULT 0xcdcdcdcd + +#define SQ_CF_WORD1_GET_POP_COUNT(sq_cf_word1) \ + ((sq_cf_word1 & SQ_CF_WORD1_POP_COUNT_MASK) >> SQ_CF_WORD1_POP_COUNT_SHIFT) +#define SQ_CF_WORD1_GET_CF_CONST(sq_cf_word1) \ + ((sq_cf_word1 & SQ_CF_WORD1_CF_CONST_MASK) >> SQ_CF_WORD1_CF_CONST_SHIFT) +#define SQ_CF_WORD1_GET_COND(sq_cf_word1) \ + ((sq_cf_word1 & SQ_CF_WORD1_COND_MASK) >> SQ_CF_WORD1_COND_SHIFT) +#define SQ_CF_WORD1_GET_COUNT(sq_cf_word1) \ + ((sq_cf_word1 & SQ_CF_WORD1_COUNT_MASK) >> SQ_CF_WORD1_COUNT_SHIFT) +#define SQ_CF_WORD1_GET_CALL_COUNT(sq_cf_word1) \ + ((sq_cf_word1 & SQ_CF_WORD1_CALL_COUNT_MASK) >> SQ_CF_WORD1_CALL_COUNT_SHIFT) +#define SQ_CF_WORD1_GET_COUNT_3(sq_cf_word1) \ + ((sq_cf_word1 & SQ_CF_WORD1_COUNT_3_MASK) >> SQ_CF_WORD1_COUNT_3_SHIFT) +#define SQ_CF_WORD1_GET_END_OF_PROGRAM(sq_cf_word1) \ + ((sq_cf_word1 & SQ_CF_WORD1_END_OF_PROGRAM_MASK) >> SQ_CF_WORD1_END_OF_PROGRAM_SHIFT) +#define SQ_CF_WORD1_GET_VALID_PIXEL_MODE(sq_cf_word1) \ + ((sq_cf_word1 & SQ_CF_WORD1_VALID_PIXEL_MODE_MASK) >> SQ_CF_WORD1_VALID_PIXEL_MODE_SHIFT) +#define SQ_CF_WORD1_GET_CF_INST(sq_cf_word1) \ + ((sq_cf_word1 & SQ_CF_WORD1_CF_INST_MASK) >> SQ_CF_WORD1_CF_INST_SHIFT) +#define SQ_CF_WORD1_GET_WHOLE_QUAD_MODE(sq_cf_word1) \ + ((sq_cf_word1 & SQ_CF_WORD1_WHOLE_QUAD_MODE_MASK) >> SQ_CF_WORD1_WHOLE_QUAD_MODE_SHIFT) +#define SQ_CF_WORD1_GET_BARRIER(sq_cf_word1) \ + ((sq_cf_word1 & SQ_CF_WORD1_BARRIER_MASK) >> SQ_CF_WORD1_BARRIER_SHIFT) + +#define SQ_CF_WORD1_SET_POP_COUNT(sq_cf_word1_reg, pop_count) \ + sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_POP_COUNT_MASK) | (pop_count << SQ_CF_WORD1_POP_COUNT_SHIFT) +#define SQ_CF_WORD1_SET_CF_CONST(sq_cf_word1_reg, cf_const) \ + sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_CF_CONST_MASK) | (cf_const << SQ_CF_WORD1_CF_CONST_SHIFT) +#define SQ_CF_WORD1_SET_COND(sq_cf_word1_reg, cond) \ + sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_COND_MASK) | (cond << SQ_CF_WORD1_COND_SHIFT) +#define SQ_CF_WORD1_SET_COUNT(sq_cf_word1_reg, count) \ + sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_COUNT_MASK) | (count << SQ_CF_WORD1_COUNT_SHIFT) +#define SQ_CF_WORD1_SET_CALL_COUNT(sq_cf_word1_reg, call_count) \ + sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_CALL_COUNT_MASK) | (call_count << SQ_CF_WORD1_CALL_COUNT_SHIFT) +#define SQ_CF_WORD1_SET_COUNT_3(sq_cf_word1_reg, count_3) \ + sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_COUNT_3_MASK) | (count_3 << SQ_CF_WORD1_COUNT_3_SHIFT) +#define SQ_CF_WORD1_SET_END_OF_PROGRAM(sq_cf_word1_reg, end_of_program) \ + sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_END_OF_PROGRAM_MASK) | (end_of_program << SQ_CF_WORD1_END_OF_PROGRAM_SHIFT) +#define SQ_CF_WORD1_SET_VALID_PIXEL_MODE(sq_cf_word1_reg, valid_pixel_mode) \ + sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_VALID_PIXEL_MODE_MASK) | (valid_pixel_mode << SQ_CF_WORD1_VALID_PIXEL_MODE_SHIFT) +#define SQ_CF_WORD1_SET_CF_INST(sq_cf_word1_reg, cf_inst) \ + sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_CF_INST_MASK) | (cf_inst << SQ_CF_WORD1_CF_INST_SHIFT) +#define SQ_CF_WORD1_SET_WHOLE_QUAD_MODE(sq_cf_word1_reg, whole_quad_mode) \ + sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_WHOLE_QUAD_MODE_MASK) | (whole_quad_mode << SQ_CF_WORD1_WHOLE_QUAD_MODE_SHIFT) +#define SQ_CF_WORD1_SET_BARRIER(sq_cf_word1_reg, barrier) \ + sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_BARRIER_MASK) | (barrier << SQ_CF_WORD1_BARRIER_SHIFT) + +#if defined(LITTLEENDIAN_CPU) + + typedef struct _sq_cf_word1_t { + unsigned int pop_count : SQ_CF_WORD1_POP_COUNT_SIZE; + unsigned int cf_const : SQ_CF_WORD1_CF_CONST_SIZE; + unsigned int cond : SQ_CF_WORD1_COND_SIZE; + unsigned int count : SQ_CF_WORD1_COUNT_SIZE; + unsigned int call_count : SQ_CF_WORD1_CALL_COUNT_SIZE; + unsigned int count_3 : SQ_CF_WORD1_COUNT_3_SIZE; + unsigned int : 1; + unsigned int end_of_program : SQ_CF_WORD1_END_OF_PROGRAM_SIZE; + unsigned int valid_pixel_mode : SQ_CF_WORD1_VALID_PIXEL_MODE_SIZE; + unsigned int cf_inst : SQ_CF_WORD1_CF_INST_SIZE; + unsigned int whole_quad_mode : SQ_CF_WORD1_WHOLE_QUAD_MODE_SIZE; + unsigned int barrier : SQ_CF_WORD1_BARRIER_SIZE; + } sq_cf_word1_t; + +#elif defined(BIGENDIAN_CPU) + + typedef struct _sq_cf_word1_t { + unsigned int barrier : SQ_CF_WORD1_BARRIER_SIZE; + unsigned int whole_quad_mode : SQ_CF_WORD1_WHOLE_QUAD_MODE_SIZE; + unsigned int cf_inst : SQ_CF_WORD1_CF_INST_SIZE; + unsigned int valid_pixel_mode : SQ_CF_WORD1_VALID_PIXEL_MODE_SIZE; + unsigned int end_of_program : SQ_CF_WORD1_END_OF_PROGRAM_SIZE; + unsigned int : 1; + unsigned int count_3 : SQ_CF_WORD1_COUNT_3_SIZE; + unsigned int call_count : SQ_CF_WORD1_CALL_COUNT_SIZE; + unsigned int count : SQ_CF_WORD1_COUNT_SIZE; + unsigned int cond : SQ_CF_WORD1_COND_SIZE; + unsigned int cf_const : SQ_CF_WORD1_CF_CONST_SIZE; + unsigned int pop_count : SQ_CF_WORD1_POP_COUNT_SIZE; + } sq_cf_word1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_word1_t f; +} sq_cf_word1_u; + + +/* + * SQ_CF_ALU_WORD0 struct + */ + +#define SQ_CF_ALU_WORD0_ADDR_SIZE 22 +#define SQ_CF_ALU_WORD0_KCACHE_BANK0_SIZE 4 +#define SQ_CF_ALU_WORD0_KCACHE_BANK1_SIZE 4 +#define SQ_CF_ALU_WORD0_KCACHE_MODE0_SIZE 2 + +#define SQ_CF_ALU_WORD0_ADDR_SHIFT 0 +#define SQ_CF_ALU_WORD0_KCACHE_BANK0_SHIFT 22 +#define SQ_CF_ALU_WORD0_KCACHE_BANK1_SHIFT 26 +#define SQ_CF_ALU_WORD0_KCACHE_MODE0_SHIFT 30 + +#define SQ_CF_ALU_WORD0_ADDR_MASK 0x003fffff +#define SQ_CF_ALU_WORD0_KCACHE_BANK0_MASK 0x03c00000 +#define SQ_CF_ALU_WORD0_KCACHE_BANK1_MASK 0x3c000000 +#define SQ_CF_ALU_WORD0_KCACHE_MODE0_MASK 0xc0000000 + +#define SQ_CF_ALU_WORD0_MASK \ + (SQ_CF_ALU_WORD0_ADDR_MASK | \ + SQ_CF_ALU_WORD0_KCACHE_BANK0_MASK | \ + SQ_CF_ALU_WORD0_KCACHE_BANK1_MASK | \ + SQ_CF_ALU_WORD0_KCACHE_MODE0_MASK) + +#define SQ_CF_ALU_WORD0_DEFAULT 0xcdcdcdcd + +#define SQ_CF_ALU_WORD0_GET_ADDR(sq_cf_alu_word0) \ + ((sq_cf_alu_word0 & SQ_CF_ALU_WORD0_ADDR_MASK) >> SQ_CF_ALU_WORD0_ADDR_SHIFT) +#define SQ_CF_ALU_WORD0_GET_KCACHE_BANK0(sq_cf_alu_word0) \ + ((sq_cf_alu_word0 & SQ_CF_ALU_WORD0_KCACHE_BANK0_MASK) >> SQ_CF_ALU_WORD0_KCACHE_BANK0_SHIFT) +#define SQ_CF_ALU_WORD0_GET_KCACHE_BANK1(sq_cf_alu_word0) \ + ((sq_cf_alu_word0 & SQ_CF_ALU_WORD0_KCACHE_BANK1_MASK) >> SQ_CF_ALU_WORD0_KCACHE_BANK1_SHIFT) +#define SQ_CF_ALU_WORD0_GET_KCACHE_MODE0(sq_cf_alu_word0) \ + ((sq_cf_alu_word0 & SQ_CF_ALU_WORD0_KCACHE_MODE0_MASK) >> SQ_CF_ALU_WORD0_KCACHE_MODE0_SHIFT) + +#define SQ_CF_ALU_WORD0_SET_ADDR(sq_cf_alu_word0_reg, addr) \ + sq_cf_alu_word0_reg = (sq_cf_alu_word0_reg & ~SQ_CF_ALU_WORD0_ADDR_MASK) | (addr << SQ_CF_ALU_WORD0_ADDR_SHIFT) +#define SQ_CF_ALU_WORD0_SET_KCACHE_BANK0(sq_cf_alu_word0_reg, kcache_bank0) \ + sq_cf_alu_word0_reg = (sq_cf_alu_word0_reg & ~SQ_CF_ALU_WORD0_KCACHE_BANK0_MASK) | (kcache_bank0 << SQ_CF_ALU_WORD0_KCACHE_BANK0_SHIFT) +#define SQ_CF_ALU_WORD0_SET_KCACHE_BANK1(sq_cf_alu_word0_reg, kcache_bank1) \ + sq_cf_alu_word0_reg = (sq_cf_alu_word0_reg & ~SQ_CF_ALU_WORD0_KCACHE_BANK1_MASK) | (kcache_bank1 << SQ_CF_ALU_WORD0_KCACHE_BANK1_SHIFT) +#define SQ_CF_ALU_WORD0_SET_KCACHE_MODE0(sq_cf_alu_word0_reg, kcache_mode0) \ + sq_cf_alu_word0_reg = (sq_cf_alu_word0_reg & ~SQ_CF_ALU_WORD0_KCACHE_MODE0_MASK) | (kcache_mode0 << SQ_CF_ALU_WORD0_KCACHE_MODE0_SHIFT) + +#if defined(LITTLEENDIAN_CPU) + + typedef struct _sq_cf_alu_word0_t { + unsigned int addr : SQ_CF_ALU_WORD0_ADDR_SIZE; + unsigned int kcache_bank0 : SQ_CF_ALU_WORD0_KCACHE_BANK0_SIZE; + unsigned int kcache_bank1 : SQ_CF_ALU_WORD0_KCACHE_BANK1_SIZE; + unsigned int kcache_mode0 : SQ_CF_ALU_WORD0_KCACHE_MODE0_SIZE; + } sq_cf_alu_word0_t; + +#elif defined(BIGENDIAN_CPU) + + typedef struct _sq_cf_alu_word0_t { + unsigned int kcache_mode0 : SQ_CF_ALU_WORD0_KCACHE_MODE0_SIZE; + unsigned int kcache_bank1 : SQ_CF_ALU_WORD0_KCACHE_BANK1_SIZE; + unsigned int kcache_bank0 : SQ_CF_ALU_WORD0_KCACHE_BANK0_SIZE; + unsigned int addr : SQ_CF_ALU_WORD0_ADDR_SIZE; + } sq_cf_alu_word0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_alu_word0_t f; +} sq_cf_alu_word0_u; + + +/* + * SQ_CF_ALU_WORD1 struct + */ + +#define SQ_CF_ALU_WORD1_KCACHE_MODE1_SIZE 2 +#define SQ_CF_ALU_WORD1_KCACHE_ADDR0_SIZE 8 +#define SQ_CF_ALU_WORD1_KCACHE_ADDR1_SIZE 8 +#define SQ_CF_ALU_WORD1_COUNT_SIZE 7 +#define SQ_CF_ALU_WORD1_ALT_CONST_SIZE 1 +#define SQ_CF_ALU_WORD1_CF_INST_SIZE 4 +#define SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_SIZE 1 +#define SQ_CF_ALU_WORD1_BARRIER_SIZE 1 + +#define SQ_CF_ALU_WORD1_KCACHE_MODE1_SHIFT 0 +#define SQ_CF_ALU_WORD1_KCACHE_ADDR0_SHIFT 2 +#define SQ_CF_ALU_WORD1_KCACHE_ADDR1_SHIFT 10 +#define SQ_CF_ALU_WORD1_COUNT_SHIFT 18 +#define SQ_CF_ALU_WORD1_ALT_CONST_SHIFT 25 +#define SQ_CF_ALU_WORD1_CF_INST_SHIFT 26 +#define SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_SHIFT 30 +#define SQ_CF_ALU_WORD1_BARRIER_SHIFT 31 + +#define SQ_CF_ALU_WORD1_KCACHE_MODE1_MASK 0x00000003 +#define SQ_CF_ALU_WORD1_KCACHE_ADDR0_MASK 0x000003fc +#define SQ_CF_ALU_WORD1_KCACHE_ADDR1_MASK 0x0003fc00 +#define SQ_CF_ALU_WORD1_COUNT_MASK 0x01fc0000 +#define SQ_CF_ALU_WORD1_ALT_CONST_MASK 0x02000000 +#define SQ_CF_ALU_WORD1_CF_INST_MASK 0x3c000000 +#define SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_MASK 0x40000000 +#define SQ_CF_ALU_WORD1_BARRIER_MASK 0x80000000 + +#define SQ_CF_ALU_WORD1_MASK \ + (SQ_CF_ALU_WORD1_KCACHE_MODE1_MASK | \ + SQ_CF_ALU_WORD1_KCACHE_ADDR0_MASK | \ + SQ_CF_ALU_WORD1_KCACHE_ADDR1_MASK | \ + SQ_CF_ALU_WORD1_COUNT_MASK | \ + SQ_CF_ALU_WORD1_ALT_CONST_MASK | \ + SQ_CF_ALU_WORD1_CF_INST_MASK | \ + SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_MASK | \ + SQ_CF_ALU_WORD1_BARRIER_MASK) + +#define SQ_CF_ALU_WORD1_DEFAULT 0xcdcdcdcd + +#define SQ_CF_ALU_WORD1_GET_KCACHE_MODE1(sq_cf_alu_word1) \ + ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_KCACHE_MODE1_MASK) >> SQ_CF_ALU_WORD1_KCACHE_MODE1_SHIFT) +#define SQ_CF_ALU_WORD1_GET_KCACHE_ADDR0(sq_cf_alu_word1) \ + ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_KCACHE_ADDR0_MASK) >> SQ_CF_ALU_WORD1_KCACHE_ADDR0_SHIFT) +#define SQ_CF_ALU_WORD1_GET_KCACHE_ADDR1(sq_cf_alu_word1) \ + ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_KCACHE_ADDR1_MASK) >> SQ_CF_ALU_WORD1_KCACHE_ADDR1_SHIFT) +#define SQ_CF_ALU_WORD1_GET_COUNT(sq_cf_alu_word1) \ + ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_COUNT_MASK) >> SQ_CF_ALU_WORD1_COUNT_SHIFT) +#define SQ_CF_ALU_WORD1_GET_ALT_CONST(sq_cf_alu_word1) \ + ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_ALT_CONST_MASK) >> SQ_CF_ALU_WORD1_ALT_CONST_SHIFT) +#define SQ_CF_ALU_WORD1_GET_CF_INST(sq_cf_alu_word1) \ + ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_CF_INST_MASK) >> SQ_CF_ALU_WORD1_CF_INST_SHIFT) +#define SQ_CF_ALU_WORD1_GET_WHOLE_QUAD_MODE(sq_cf_alu_word1) \ + ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_MASK) >> SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_SHIFT) +#define SQ_CF_ALU_WORD1_GET_BARRIER(sq_cf_alu_word1) \ + ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_BARRIER_MASK) >> SQ_CF_ALU_WORD1_BARRIER_SHIFT) + +#define SQ_CF_ALU_WORD1_SET_KCACHE_MODE1(sq_cf_alu_word1_reg, kcache_mode1) \ + sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_KCACHE_MODE1_MASK) | (kcache_mode1 << SQ_CF_ALU_WORD1_KCACHE_MODE1_SHIFT) +#define SQ_CF_ALU_WORD1_SET_KCACHE_ADDR0(sq_cf_alu_word1_reg, kcache_addr0) \ + sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_KCACHE_ADDR0_MASK) | (kcache_addr0 << SQ_CF_ALU_WORD1_KCACHE_ADDR0_SHIFT) +#define SQ_CF_ALU_WORD1_SET_KCACHE_ADDR1(sq_cf_alu_word1_reg, kcache_addr1) \ + sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_KCACHE_ADDR1_MASK) | (kcache_addr1 << SQ_CF_ALU_WORD1_KCACHE_ADDR1_SHIFT) +#define SQ_CF_ALU_WORD1_SET_COUNT(sq_cf_alu_word1_reg, count) \ + sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_COUNT_MASK) | (count << SQ_CF_ALU_WORD1_COUNT_SHIFT) +#define SQ_CF_ALU_WORD1_SET_ALT_CONST(sq_cf_alu_word1_reg, alt_const) \ + sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_ALT_CONST_MASK) | (alt_const << SQ_CF_ALU_WORD1_ALT_CONST_SHIFT) +#define SQ_CF_ALU_WORD1_SET_CF_INST(sq_cf_alu_word1_reg, cf_inst) \ + sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_CF_INST_MASK) | (cf_inst << SQ_CF_ALU_WORD1_CF_INST_SHIFT) +#define SQ_CF_ALU_WORD1_SET_WHOLE_QUAD_MODE(sq_cf_alu_word1_reg, whole_quad_mode) \ + sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_MASK) | (whole_quad_mode << SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_SHIFT) +#define SQ_CF_ALU_WORD1_SET_BARRIER(sq_cf_alu_word1_reg, barrier) \ + sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_BARRIER_MASK) | (barrier << SQ_CF_ALU_WORD1_BARRIER_SHIFT) + +#if defined(LITTLEENDIAN_CPU) + + typedef struct _sq_cf_alu_word1_t { + unsigned int kcache_mode1 : SQ_CF_ALU_WORD1_KCACHE_MODE1_SIZE; + unsigned int kcache_addr0 : SQ_CF_ALU_WORD1_KCACHE_ADDR0_SIZE; + unsigned int kcache_addr1 : SQ_CF_ALU_WORD1_KCACHE_ADDR1_SIZE; + unsigned int count : SQ_CF_ALU_WORD1_COUNT_SIZE; + unsigned int alt_const : SQ_CF_ALU_WORD1_ALT_CONST_SIZE; + unsigned int cf_inst : SQ_CF_ALU_WORD1_CF_INST_SIZE; + unsigned int whole_quad_mode : SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_SIZE; + unsigned int barrier : SQ_CF_ALU_WORD1_BARRIER_SIZE; + } sq_cf_alu_word1_t; + +#elif defined(BIGENDIAN_CPU) + + typedef struct _sq_cf_alu_word1_t { + unsigned int barrier : SQ_CF_ALU_WORD1_BARRIER_SIZE; + unsigned int whole_quad_mode : SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_SIZE; + unsigned int cf_inst : SQ_CF_ALU_WORD1_CF_INST_SIZE; + unsigned int alt_const : SQ_CF_ALU_WORD1_ALT_CONST_SIZE; + unsigned int count : SQ_CF_ALU_WORD1_COUNT_SIZE; + unsigned int kcache_addr1 : SQ_CF_ALU_WORD1_KCACHE_ADDR1_SIZE; + unsigned int kcache_addr0 : SQ_CF_ALU_WORD1_KCACHE_ADDR0_SIZE; + unsigned int kcache_mode1 : SQ_CF_ALU_WORD1_KCACHE_MODE1_SIZE; + } sq_cf_alu_word1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_alu_word1_t f; +} sq_cf_alu_word1_u; + + +/* + * SQ_CF_ALLOC_EXPORT_WORD0 struct + */ + +#define SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_SIZE 13 +#define SQ_CF_ALLOC_EXPORT_WORD0_TYPE_SIZE 2 +#define SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_SIZE 7 +#define SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_SIZE 1 +#define SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_SIZE 7 +#define SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_SIZE 2 + +#define SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_SHIFT 0 +#define SQ_CF_ALLOC_EXPORT_WORD0_TYPE_SHIFT 13 +#define SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_SHIFT 15 +#define SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_SHIFT 22 +#define SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_SHIFT 23 +#define SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_SHIFT 30 + +#define SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_MASK 0x00001fff +#define SQ_CF_ALLOC_EXPORT_WORD0_TYPE_MASK 0x00006000 +#define SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_MASK 0x003f8000 +#define SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_MASK 0x00400000 +#define SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_MASK 0x3f800000 +#define SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_MASK 0xc0000000 + +#define SQ_CF_ALLOC_EXPORT_WORD0_MASK \ + (SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_MASK | \ + SQ_CF_ALLOC_EXPORT_WORD0_TYPE_MASK | \ + SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_MASK | \ + SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_MASK | \ + SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_MASK | \ + SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_MASK) + +#define SQ_CF_ALLOC_EXPORT_WORD0_DEFAULT 0xcdcdcdcd + +#define SQ_CF_ALLOC_EXPORT_WORD0_GET_ARRAY_BASE(sq_cf_alloc_export_word0) \ + ((sq_cf_alloc_export_word0 & SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_MASK) >> SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD0_GET_TYPE(sq_cf_alloc_export_word0) \ + ((sq_cf_alloc_export_word0 & SQ_CF_ALLOC_EXPORT_WORD0_TYPE_MASK) >> SQ_CF_ALLOC_EXPORT_WORD0_TYPE_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD0_GET_RW_GPR(sq_cf_alloc_export_word0) \ + ((sq_cf_alloc_export_word0 & SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_MASK) >> SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD0_GET_RW_REL(sq_cf_alloc_export_word0) \ + ((sq_cf_alloc_export_word0 & SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_MASK) >> SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD0_GET_INDEX_GPR(sq_cf_alloc_export_word0) \ + ((sq_cf_alloc_export_word0 & SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_MASK) >> SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD0_GET_ELEM_SIZE(sq_cf_alloc_export_word0) \ + ((sq_cf_alloc_export_word0 & SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_MASK) >> SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_SHIFT) + +#define SQ_CF_ALLOC_EXPORT_WORD0_SET_ARRAY_BASE(sq_cf_alloc_export_word0_reg, array_base) \ + sq_cf_alloc_export_word0_reg = (sq_cf_alloc_export_word0_reg & ~SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_MASK) | (array_base << SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD0_SET_TYPE(sq_cf_alloc_export_word0_reg, type) \ + sq_cf_alloc_export_word0_reg = (sq_cf_alloc_export_word0_reg & ~SQ_CF_ALLOC_EXPORT_WORD0_TYPE_MASK) | (type << SQ_CF_ALLOC_EXPORT_WORD0_TYPE_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD0_SET_RW_GPR(sq_cf_alloc_export_word0_reg, rw_gpr) \ + sq_cf_alloc_export_word0_reg = (sq_cf_alloc_export_word0_reg & ~SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_MASK) | (rw_gpr << SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD0_SET_RW_REL(sq_cf_alloc_export_word0_reg, rw_rel) \ + sq_cf_alloc_export_word0_reg = (sq_cf_alloc_export_word0_reg & ~SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_MASK) | (rw_rel << SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD0_SET_INDEX_GPR(sq_cf_alloc_export_word0_reg, index_gpr) \ + sq_cf_alloc_export_word0_reg = (sq_cf_alloc_export_word0_reg & ~SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_MASK) | (index_gpr << SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD0_SET_ELEM_SIZE(sq_cf_alloc_export_word0_reg, elem_size) \ + sq_cf_alloc_export_word0_reg = (sq_cf_alloc_export_word0_reg & ~SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_MASK) | (elem_size << SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_SHIFT) + +#if defined(LITTLEENDIAN_CPU) + + typedef struct _sq_cf_alloc_export_word0_t { + unsigned int array_base : SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_SIZE; + unsigned int type : SQ_CF_ALLOC_EXPORT_WORD0_TYPE_SIZE; + unsigned int rw_gpr : SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_SIZE; + unsigned int rw_rel : SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_SIZE; + unsigned int index_gpr : SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_SIZE; + unsigned int elem_size : SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_SIZE; + } sq_cf_alloc_export_word0_t; + +#elif defined(BIGENDIAN_CPU) + + typedef struct _sq_cf_alloc_export_word0_t { + unsigned int elem_size : SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_SIZE; + unsigned int index_gpr : SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_SIZE; + unsigned int rw_rel : SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_SIZE; + unsigned int rw_gpr : SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_SIZE; + unsigned int type : SQ_CF_ALLOC_EXPORT_WORD0_TYPE_SIZE; + unsigned int array_base : SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_SIZE; + } sq_cf_alloc_export_word0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_alloc_export_word0_t f; +} sq_cf_alloc_export_word0_u; + + +/* + * SQ_CF_ALLOC_EXPORT_WORD1 struct + */ + +#define SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_SIZE 4 +#define SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_SIZE 1 +#define SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_SIZE 1 +#define SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_SIZE 7 +#define SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_SIZE 1 +#define SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_SIZE 1 + +#define SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_SHIFT 17 +#define SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_SHIFT 21 +#define SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_SHIFT 22 +#define SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_SHIFT 23 +#define SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_SHIFT 30 +#define SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_SHIFT 31 + +#define SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_MASK 0x001e0000 +#define SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_MASK 0x00200000 +#define SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_MASK 0x00400000 +#define SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_MASK 0x3f800000 +#define SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_MASK 0x40000000 +#define SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_MASK 0x80000000 + +#define SQ_CF_ALLOC_EXPORT_WORD1_MASK \ + (SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_MASK | \ + SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_MASK | \ + SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_MASK | \ + SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_MASK | \ + SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_MASK | \ + SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_MASK) + +#define SQ_CF_ALLOC_EXPORT_WORD1_DEFAULT 0xcdcc0000 + +#define SQ_CF_ALLOC_EXPORT_WORD1_GET_BURST_COUNT(sq_cf_alloc_export_word1) \ + ((sq_cf_alloc_export_word1 & SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD1_GET_END_OF_PROGRAM(sq_cf_alloc_export_word1) \ + ((sq_cf_alloc_export_word1 & SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD1_GET_VALID_PIXEL_MODE(sq_cf_alloc_export_word1) \ + ((sq_cf_alloc_export_word1 & SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD1_GET_CF_INST(sq_cf_alloc_export_word1) \ + ((sq_cf_alloc_export_word1 & SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD1_GET_WHOLE_QUAD_MODE(sq_cf_alloc_export_word1) \ + ((sq_cf_alloc_export_word1 & SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD1_GET_BARRIER(sq_cf_alloc_export_word1) \ + ((sq_cf_alloc_export_word1 & SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_SHIFT) + +#define SQ_CF_ALLOC_EXPORT_WORD1_SET_BURST_COUNT(sq_cf_alloc_export_word1_reg, burst_count) \ + sq_cf_alloc_export_word1_reg = (sq_cf_alloc_export_word1_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_MASK) | (burst_count << SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD1_SET_END_OF_PROGRAM(sq_cf_alloc_export_word1_reg, end_of_program) \ + sq_cf_alloc_export_word1_reg = (sq_cf_alloc_export_word1_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_MASK) | (end_of_program << SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD1_SET_VALID_PIXEL_MODE(sq_cf_alloc_export_word1_reg, valid_pixel_mode) \ + sq_cf_alloc_export_word1_reg = (sq_cf_alloc_export_word1_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_MASK) | (valid_pixel_mode << SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD1_SET_CF_INST(sq_cf_alloc_export_word1_reg, cf_inst) \ + sq_cf_alloc_export_word1_reg = (sq_cf_alloc_export_word1_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_MASK) | (cf_inst << SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD1_SET_WHOLE_QUAD_MODE(sq_cf_alloc_export_word1_reg, whole_quad_mode) \ + sq_cf_alloc_export_word1_reg = (sq_cf_alloc_export_word1_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_MASK) | (whole_quad_mode << SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD1_SET_BARRIER(sq_cf_alloc_export_word1_reg, barrier) \ + sq_cf_alloc_export_word1_reg = (sq_cf_alloc_export_word1_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_MASK) | (barrier << SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_SHIFT) + +#if defined(LITTLEENDIAN_CPU) + + typedef struct _sq_cf_alloc_export_word1_t { + unsigned int : 17; + unsigned int burst_count : SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_SIZE; + unsigned int end_of_program : SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_SIZE; + unsigned int valid_pixel_mode : SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_SIZE; + unsigned int cf_inst : SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_SIZE; + unsigned int whole_quad_mode : SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_SIZE; + unsigned int barrier : SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_SIZE; + } sq_cf_alloc_export_word1_t; + +#elif defined(BIGENDIAN_CPU) + + typedef struct _sq_cf_alloc_export_word1_t { + unsigned int barrier : SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_SIZE; + unsigned int whole_quad_mode : SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_SIZE; + unsigned int cf_inst : SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_SIZE; + unsigned int valid_pixel_mode : SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_SIZE; + unsigned int end_of_program : SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_SIZE; + unsigned int burst_count : SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_SIZE; + unsigned int : 17; + } sq_cf_alloc_export_word1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_alloc_export_word1_t f; +} sq_cf_alloc_export_word1_u; + + +/* + * SQ_CF_ALLOC_EXPORT_WORD1_BUF struct + */ + +#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_SIZE 12 +#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_SIZE 4 + +#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_SHIFT 0 +#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_SHIFT 12 + +#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_MASK 0x00000fff +#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_MASK 0x0000f000 + +#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_MASK \ + (SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_MASK | \ + SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_MASK) + +#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_DEFAULT 0x0000cdcd + +#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_GET_ARRAY_SIZE(sq_cf_alloc_export_word1_buf) \ + ((sq_cf_alloc_export_word1_buf & SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_GET_COMP_MASK(sq_cf_alloc_export_word1_buf) \ + ((sq_cf_alloc_export_word1_buf & SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_SHIFT) + +#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_SET_ARRAY_SIZE(sq_cf_alloc_export_word1_buf_reg, array_size) \ + sq_cf_alloc_export_word1_buf_reg = (sq_cf_alloc_export_word1_buf_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_MASK) | (array_size << SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD1_BUF_SET_COMP_MASK(sq_cf_alloc_export_word1_buf_reg, comp_mask) \ + sq_cf_alloc_export_word1_buf_reg = (sq_cf_alloc_export_word1_buf_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_MASK) | (comp_mask << SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_SHIFT) + +#if defined(LITTLEENDIAN_CPU) + + typedef struct _sq_cf_alloc_export_word1_buf_t { + unsigned int array_size : SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_SIZE; + unsigned int comp_mask : SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_SIZE; + unsigned int : 16; + } sq_cf_alloc_export_word1_buf_t; + +#elif defined(BIGENDIAN_CPU) + + typedef struct _sq_cf_alloc_export_word1_buf_t { + unsigned int : 16; + unsigned int comp_mask : SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_SIZE; + unsigned int array_size : SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_SIZE; + } sq_cf_alloc_export_word1_buf_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_alloc_export_word1_buf_t f; +} sq_cf_alloc_export_word1_buf_u; + + +/* + * SQ_CF_ALLOC_EXPORT_WORD1_SWIZ struct + */ + +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_SIZE 3 +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_SIZE 3 +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_SIZE 3 +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_SIZE 3 + +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_SHIFT 0 +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_SHIFT 3 +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_SHIFT 6 +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_SHIFT 9 + +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_MASK 0x00000007 +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_MASK 0x00000038 +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_MASK 0x000001c0 +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_MASK 0x00000e00 + +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_MASK \ + (SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_MASK | \ + SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_MASK | \ + SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_MASK | \ + SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_MASK) + +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_DEFAULT 0x00000dcd + +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_GET_SEL_X(sq_cf_alloc_export_word1_swiz) \ + ((sq_cf_alloc_export_word1_swiz & SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_GET_SEL_Y(sq_cf_alloc_export_word1_swiz) \ + ((sq_cf_alloc_export_word1_swiz & SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_GET_SEL_Z(sq_cf_alloc_export_word1_swiz) \ + ((sq_cf_alloc_export_word1_swiz & SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_GET_SEL_W(sq_cf_alloc_export_word1_swiz) \ + ((sq_cf_alloc_export_word1_swiz & SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_SHIFT) + +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SET_SEL_X(sq_cf_alloc_export_word1_swiz_reg, sel_x) \ + sq_cf_alloc_export_word1_swiz_reg = (sq_cf_alloc_export_word1_swiz_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_MASK) | (sel_x << SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SET_SEL_Y(sq_cf_alloc_export_word1_swiz_reg, sel_y) \ + sq_cf_alloc_export_word1_swiz_reg = (sq_cf_alloc_export_word1_swiz_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_MASK) | (sel_y << SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SET_SEL_Z(sq_cf_alloc_export_word1_swiz_reg, sel_z) \ + sq_cf_alloc_export_word1_swiz_reg = (sq_cf_alloc_export_word1_swiz_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_MASK) | (sel_z << SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_SHIFT) +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SET_SEL_W(sq_cf_alloc_export_word1_swiz_reg, sel_w) \ + sq_cf_alloc_export_word1_swiz_reg = (sq_cf_alloc_export_word1_swiz_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_MASK) | (sel_w << SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_SHIFT) + +#if defined(LITTLEENDIAN_CPU) + + typedef struct _sq_cf_alloc_export_word1_swiz_t { + unsigned int sel_x : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_SIZE; + unsigned int sel_y : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_SIZE; + unsigned int sel_z : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_SIZE; + unsigned int sel_w : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_SIZE; + unsigned int : 20; + } sq_cf_alloc_export_word1_swiz_t; + +#elif defined(BIGENDIAN_CPU) + + typedef struct _sq_cf_alloc_export_word1_swiz_t { + unsigned int : 20; + unsigned int sel_w : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_SIZE; + unsigned int sel_z : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_SIZE; + unsigned int sel_y : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_SIZE; + unsigned int sel_x : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_SIZE; + } sq_cf_alloc_export_word1_swiz_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_alloc_export_word1_swiz_t f; +} sq_cf_alloc_export_word1_swiz_u; + + +/* + * SQ_ALU_WORD0 struct + */ + +#define SQ_ALU_WORD0_SRC0_SEL_SIZE 9 +#define SQ_ALU_WORD0_SRC0_REL_SIZE 1 +#define SQ_ALU_WORD0_SRC0_CHAN_SIZE 2 +#define SQ_ALU_WORD0_SRC0_NEG_SIZE 1 +#define SQ_ALU_WORD0_SRC1_SEL_SIZE 9 +#define SQ_ALU_WORD0_SRC1_REL_SIZE 1 +#define SQ_ALU_WORD0_SRC1_CHAN_SIZE 2 +#define SQ_ALU_WORD0_SRC1_NEG_SIZE 1 +#define SQ_ALU_WORD0_INDEX_MODE_SIZE 3 +#define SQ_ALU_WORD0_PRED_SEL_SIZE 2 +#define SQ_ALU_WORD0_LAST_SIZE 1 + +#define SQ_ALU_WORD0_SRC0_SEL_SHIFT 0 +#define SQ_ALU_WORD0_SRC0_REL_SHIFT 9 +#define SQ_ALU_WORD0_SRC0_CHAN_SHIFT 10 +#define SQ_ALU_WORD0_SRC0_NEG_SHIFT 12 +#define SQ_ALU_WORD0_SRC1_SEL_SHIFT 13 +#define SQ_ALU_WORD0_SRC1_REL_SHIFT 22 +#define SQ_ALU_WORD0_SRC1_CHAN_SHIFT 23 +#define SQ_ALU_WORD0_SRC1_NEG_SHIFT 25 +#define SQ_ALU_WORD0_INDEX_MODE_SHIFT 26 +#define SQ_ALU_WORD0_PRED_SEL_SHIFT 29 +#define SQ_ALU_WORD0_LAST_SHIFT 31 + +#define SQ_ALU_WORD0_SRC0_SEL_MASK 0x000001ff +#define SQ_ALU_WORD0_SRC0_REL_MASK 0x00000200 +#define SQ_ALU_WORD0_SRC0_CHAN_MASK 0x00000c00 +#define SQ_ALU_WORD0_SRC0_NEG_MASK 0x00001000 +#define SQ_ALU_WORD0_SRC1_SEL_MASK 0x003fe000 +#define SQ_ALU_WORD0_SRC1_REL_MASK 0x00400000 +#define SQ_ALU_WORD0_SRC1_CHAN_MASK 0x01800000 +#define SQ_ALU_WORD0_SRC1_NEG_MASK 0x02000000 +#define SQ_ALU_WORD0_INDEX_MODE_MASK 0x1c000000 +#define SQ_ALU_WORD0_PRED_SEL_MASK 0x60000000 +#define SQ_ALU_WORD0_LAST_MASK 0x80000000 + +#define SQ_ALU_WORD0_MASK \ + (SQ_ALU_WORD0_SRC0_SEL_MASK | \ + SQ_ALU_WORD0_SRC0_REL_MASK | \ + SQ_ALU_WORD0_SRC0_CHAN_MASK | \ + SQ_ALU_WORD0_SRC0_NEG_MASK | \ + SQ_ALU_WORD0_SRC1_SEL_MASK | \ + SQ_ALU_WORD0_SRC1_REL_MASK | \ + SQ_ALU_WORD0_SRC1_CHAN_MASK | \ + SQ_ALU_WORD0_SRC1_NEG_MASK | \ + SQ_ALU_WORD0_INDEX_MODE_MASK | \ + SQ_ALU_WORD0_PRED_SEL_MASK | \ + SQ_ALU_WORD0_LAST_MASK) + +#define SQ_ALU_WORD0_DEFAULT 0xcdcdcdcd + +#define SQ_ALU_WORD0_GET_SRC0_SEL(sq_alu_word0) \ + ((sq_alu_word0 & SQ_ALU_WORD0_SRC0_SEL_MASK) >> SQ_ALU_WORD0_SRC0_SEL_SHIFT) +#define SQ_ALU_WORD0_GET_SRC0_REL(sq_alu_word0) \ + ((sq_alu_word0 & SQ_ALU_WORD0_SRC0_REL_MASK) >> SQ_ALU_WORD0_SRC0_REL_SHIFT) +#define SQ_ALU_WORD0_GET_SRC0_CHAN(sq_alu_word0) \ + ((sq_alu_word0 & SQ_ALU_WORD0_SRC0_CHAN_MASK) >> SQ_ALU_WORD0_SRC0_CHAN_SHIFT) +#define SQ_ALU_WORD0_GET_SRC0_NEG(sq_alu_word0) \ + ((sq_alu_word0 & SQ_ALU_WORD0_SRC0_NEG_MASK) >> SQ_ALU_WORD0_SRC0_NEG_SHIFT) +#define SQ_ALU_WORD0_GET_SRC1_SEL(sq_alu_word0) \ + ((sq_alu_word0 & SQ_ALU_WORD0_SRC1_SEL_MASK) >> SQ_ALU_WORD0_SRC1_SEL_SHIFT) +#define SQ_ALU_WORD0_GET_SRC1_REL(sq_alu_word0) \ + ((sq_alu_word0 & SQ_ALU_WORD0_SRC1_REL_MASK) >> SQ_ALU_WORD0_SRC1_REL_SHIFT) +#define SQ_ALU_WORD0_GET_SRC1_CHAN(sq_alu_word0) \ + ((sq_alu_word0 & SQ_ALU_WORD0_SRC1_CHAN_MASK) >> SQ_ALU_WORD0_SRC1_CHAN_SHIFT) +#define SQ_ALU_WORD0_GET_SRC1_NEG(sq_alu_word0) \ + ((sq_alu_word0 & SQ_ALU_WORD0_SRC1_NEG_MASK) >> SQ_ALU_WORD0_SRC1_NEG_SHIFT) +#define SQ_ALU_WORD0_GET_INDEX_MODE(sq_alu_word0) \ + ((sq_alu_word0 & SQ_ALU_WORD0_INDEX_MODE_MASK) >> SQ_ALU_WORD0_INDEX_MODE_SHIFT) +#define SQ_ALU_WORD0_GET_PRED_SEL(sq_alu_word0) \ + ((sq_alu_word0 & SQ_ALU_WORD0_PRED_SEL_MASK) >> SQ_ALU_WORD0_PRED_SEL_SHIFT) +#define SQ_ALU_WORD0_GET_LAST(sq_alu_word0) \ + ((sq_alu_word0 & SQ_ALU_WORD0_LAST_MASK) >> SQ_ALU_WORD0_LAST_SHIFT) + +#define SQ_ALU_WORD0_SET_SRC0_SEL(sq_alu_word0_reg, src0_sel) \ + sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC0_SEL_MASK) | (src0_sel << SQ_ALU_WORD0_SRC0_SEL_SHIFT) +#define SQ_ALU_WORD0_SET_SRC0_REL(sq_alu_word0_reg, src0_rel) \ + sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC0_REL_MASK) | (src0_rel << SQ_ALU_WORD0_SRC0_REL_SHIFT) +#define SQ_ALU_WORD0_SET_SRC0_CHAN(sq_alu_word0_reg, src0_chan) \ + sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC0_CHAN_MASK) | (src0_chan << SQ_ALU_WORD0_SRC0_CHAN_SHIFT) +#define SQ_ALU_WORD0_SET_SRC0_NEG(sq_alu_word0_reg, src0_neg) \ + sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC0_NEG_MASK) | (src0_neg << SQ_ALU_WORD0_SRC0_NEG_SHIFT) +#define SQ_ALU_WORD0_SET_SRC1_SEL(sq_alu_word0_reg, src1_sel) \ + sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC1_SEL_MASK) | (src1_sel << SQ_ALU_WORD0_SRC1_SEL_SHIFT) +#define SQ_ALU_WORD0_SET_SRC1_REL(sq_alu_word0_reg, src1_rel) \ + sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC1_REL_MASK) | (src1_rel << SQ_ALU_WORD0_SRC1_REL_SHIFT) +#define SQ_ALU_WORD0_SET_SRC1_CHAN(sq_alu_word0_reg, src1_chan) \ + sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC1_CHAN_MASK) | (src1_chan << SQ_ALU_WORD0_SRC1_CHAN_SHIFT) +#define SQ_ALU_WORD0_SET_SRC1_NEG(sq_alu_word0_reg, src1_neg) \ + sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC1_NEG_MASK) | (src1_neg << SQ_ALU_WORD0_SRC1_NEG_SHIFT) +#define SQ_ALU_WORD0_SET_INDEX_MODE(sq_alu_word0_reg, index_mode) \ + sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_INDEX_MODE_MASK) | (index_mode << SQ_ALU_WORD0_INDEX_MODE_SHIFT) +#define SQ_ALU_WORD0_SET_PRED_SEL(sq_alu_word0_reg, pred_sel) \ + sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_PRED_SEL_MASK) | (pred_sel << SQ_ALU_WORD0_PRED_SEL_SHIFT) +#define SQ_ALU_WORD0_SET_LAST(sq_alu_word0_reg, last) \ + sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_LAST_MASK) | (last << SQ_ALU_WORD0_LAST_SHIFT) + +#if defined(LITTLEENDIAN_CPU) + + typedef struct _sq_alu_word0_t { + unsigned int src0_sel : SQ_ALU_WORD0_SRC0_SEL_SIZE; + unsigned int src0_rel : SQ_ALU_WORD0_SRC0_REL_SIZE; + unsigned int src0_chan : SQ_ALU_WORD0_SRC0_CHAN_SIZE; + unsigned int src0_neg : SQ_ALU_WORD0_SRC0_NEG_SIZE; + unsigned int src1_sel : SQ_ALU_WORD0_SRC1_SEL_SIZE; + unsigned int src1_rel : SQ_ALU_WORD0_SRC1_REL_SIZE; + unsigned int src1_chan : SQ_ALU_WORD0_SRC1_CHAN_SIZE; + unsigned int src1_neg : SQ_ALU_WORD0_SRC1_NEG_SIZE; + unsigned int index_mode : SQ_ALU_WORD0_INDEX_MODE_SIZE; + unsigned int pred_sel : SQ_ALU_WORD0_PRED_SEL_SIZE; + unsigned int last : SQ_ALU_WORD0_LAST_SIZE; + } sq_alu_word0_t; + +#elif defined(BIGENDIAN_CPU) + + typedef struct _sq_alu_word0_t { + unsigned int last : SQ_ALU_WORD0_LAST_SIZE; + unsigned int pred_sel : SQ_ALU_WORD0_PRED_SEL_SIZE; + unsigned int index_mode : SQ_ALU_WORD0_INDEX_MODE_SIZE; + unsigned int src1_neg : SQ_ALU_WORD0_SRC1_NEG_SIZE; + unsigned int src1_chan : SQ_ALU_WORD0_SRC1_CHAN_SIZE; + unsigned int src1_rel : SQ_ALU_WORD0_SRC1_REL_SIZE; + unsigned int src1_sel : SQ_ALU_WORD0_SRC1_SEL_SIZE; + unsigned int src0_neg : SQ_ALU_WORD0_SRC0_NEG_SIZE; + unsigned int src0_chan : SQ_ALU_WORD0_SRC0_CHAN_SIZE; + unsigned int src0_rel : SQ_ALU_WORD0_SRC0_REL_SIZE; + unsigned int src0_sel : SQ_ALU_WORD0_SRC0_SEL_SIZE; + } sq_alu_word0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_alu_word0_t f; +} sq_alu_word0_u; + + +/* + * SQ_ALU_WORD1 struct + */ + +#define SQ_ALU_WORD1_ENCODING_SIZE 3 +#define SQ_ALU_WORD1_BANK_SWIZZLE_SIZE 3 +#define SQ_ALU_WORD1_DST_GPR_SIZE 7 +#define SQ_ALU_WORD1_DST_REL_SIZE 1 +#define SQ_ALU_WORD1_DST_CHAN_SIZE 2 +#define SQ_ALU_WORD1_CLAMP_SIZE 1 + +#define SQ_ALU_WORD1_ENCODING_SHIFT 15 +#define SQ_ALU_WORD1_BANK_SWIZZLE_SHIFT 18 +#define SQ_ALU_WORD1_DST_GPR_SHIFT 21 +#define SQ_ALU_WORD1_DST_REL_SHIFT 28 +#define SQ_ALU_WORD1_DST_CHAN_SHIFT 29 +#define SQ_ALU_WORD1_CLAMP_SHIFT 31 + +#define SQ_ALU_WORD1_ENCODING_MASK 0x00038000 +#define SQ_ALU_WORD1_BANK_SWIZZLE_MASK 0x001c0000 +#define SQ_ALU_WORD1_DST_GPR_MASK 0x0fe00000 +#define SQ_ALU_WORD1_DST_REL_MASK 0x10000000 +#define SQ_ALU_WORD1_DST_CHAN_MASK 0x60000000 +#define SQ_ALU_WORD1_CLAMP_MASK 0x80000000 + +#define SQ_ALU_WORD1_MASK \ + (SQ_ALU_WORD1_ENCODING_MASK | \ + SQ_ALU_WORD1_BANK_SWIZZLE_MASK | \ + SQ_ALU_WORD1_DST_GPR_MASK | \ + SQ_ALU_WORD1_DST_REL_MASK | \ + SQ_ALU_WORD1_DST_CHAN_MASK | \ + SQ_ALU_WORD1_CLAMP_MASK) + +#define SQ_ALU_WORD1_DEFAULT 0xcdcd8000 + +#define SQ_ALU_WORD1_GET_ENCODING(sq_alu_word1) \ + ((sq_alu_word1 & SQ_ALU_WORD1_ENCODING_MASK) >> SQ_ALU_WORD1_ENCODING_SHIFT) +#define SQ_ALU_WORD1_GET_BANK_SWIZZLE(sq_alu_word1) \ + ((sq_alu_word1 & SQ_ALU_WORD1_BANK_SWIZZLE_MASK) >> SQ_ALU_WORD1_BANK_SWIZZLE_SHIFT) +#define SQ_ALU_WORD1_GET_DST_GPR(sq_alu_word1) \ + ((sq_alu_word1 & SQ_ALU_WORD1_DST_GPR_MASK) >> SQ_ALU_WORD1_DST_GPR_SHIFT) +#define SQ_ALU_WORD1_GET_DST_REL(sq_alu_word1) \ + ((sq_alu_word1 & SQ_ALU_WORD1_DST_REL_MASK) >> SQ_ALU_WORD1_DST_REL_SHIFT) +#define SQ_ALU_WORD1_GET_DST_CHAN(sq_alu_word1) \ + ((sq_alu_word1 & SQ_ALU_WORD1_DST_CHAN_MASK) >> SQ_ALU_WORD1_DST_CHAN_SHIFT) +#define SQ_ALU_WORD1_GET_CLAMP(sq_alu_word1) \ + ((sq_alu_word1 & SQ_ALU_WORD1_CLAMP_MASK) >> SQ_ALU_WORD1_CLAMP_SHIFT) + +#define SQ_ALU_WORD1_SET_ENCODING(sq_alu_word1_reg, encoding) \ + sq_alu_word1_reg = (sq_alu_word1_reg & ~SQ_ALU_WORD1_ENCODING_MASK) | (encoding << SQ_ALU_WORD1_ENCODING_SHIFT) +#define SQ_ALU_WORD1_SET_BANK_SWIZZLE(sq_alu_word1_reg, bank_swizzle) \ + sq_alu_word1_reg = (sq_alu_word1_reg & ~SQ_ALU_WORD1_BANK_SWIZZLE_MASK) | (bank_swizzle << SQ_ALU_WORD1_BANK_SWIZZLE_SHIFT) +#define SQ_ALU_WORD1_SET_DST_GPR(sq_alu_word1_reg, dst_gpr) \ + sq_alu_word1_reg = (sq_alu_word1_reg & ~SQ_ALU_WORD1_DST_GPR_MASK) | (dst_gpr << SQ_ALU_WORD1_DST_GPR_SHIFT) +#define SQ_ALU_WORD1_SET_DST_REL(sq_alu_word1_reg, dst_rel) \ + sq_alu_word1_reg = (sq_alu_word1_reg & ~SQ_ALU_WORD1_DST_REL_MASK) | (dst_rel << SQ_ALU_WORD1_DST_REL_SHIFT) +#define SQ_ALU_WORD1_SET_DST_CHAN(sq_alu_word1_reg, dst_chan) \ + sq_alu_word1_reg = (sq_alu_word1_reg & ~SQ_ALU_WORD1_DST_CHAN_MASK) | (dst_chan << SQ_ALU_WORD1_DST_CHAN_SHIFT) +#define SQ_ALU_WORD1_SET_CLAMP(sq_alu_word1_reg, clamp) \ + sq_alu_word1_reg = (sq_alu_word1_reg & ~SQ_ALU_WORD1_CLAMP_MASK) | (clamp << SQ_ALU_WORD1_CLAMP_SHIFT) + +#if defined(LITTLEENDIAN_CPU) + + typedef struct _sq_alu_word1_t { + unsigned int : 15; + unsigned int encoding : SQ_ALU_WORD1_ENCODING_SIZE; + unsigned int bank_swizzle : SQ_ALU_WORD1_BANK_SWIZZLE_SIZE; + unsigned int dst_gpr : SQ_ALU_WORD1_DST_GPR_SIZE; + unsigned int dst_rel : SQ_ALU_WORD1_DST_REL_SIZE; + unsigned int dst_chan : SQ_ALU_WORD1_DST_CHAN_SIZE; + unsigned int clamp : SQ_ALU_WORD1_CLAMP_SIZE; + } sq_alu_word1_t; + +#elif defined(BIGENDIAN_CPU) + + typedef struct _sq_alu_word1_t { + unsigned int clamp : SQ_ALU_WORD1_CLAMP_SIZE; + unsigned int dst_chan : SQ_ALU_WORD1_DST_CHAN_SIZE; + unsigned int dst_rel : SQ_ALU_WORD1_DST_REL_SIZE; + unsigned int dst_gpr : SQ_ALU_WORD1_DST_GPR_SIZE; + unsigned int bank_swizzle : SQ_ALU_WORD1_BANK_SWIZZLE_SIZE; + unsigned int encoding : SQ_ALU_WORD1_ENCODING_SIZE; + unsigned int : 15; + } sq_alu_word1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_alu_word1_t f; +} sq_alu_word1_u; + + +/* + * SQ_ALU_WORD1_OP2_V2 struct + */ + +#define SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SIZE 1 +#define SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SIZE 1 +#define SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SIZE 1 +#define SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SIZE 1 +#define SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SIZE 1 +#define SQ_ALU_WORD1_OP2_V2_OMOD_SIZE 2 +#define SQ_ALU_WORD1_OP2_V2_ALU_INST_SIZE 11 + +#define SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SHIFT 0 +#define SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SHIFT 1 +#define SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SHIFT 2 +#define SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SHIFT 3 +#define SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SHIFT 4 +#define SQ_ALU_WORD1_OP2_V2_OMOD_SHIFT 5 +#define SQ_ALU_WORD1_OP2_V2_ALU_INST_SHIFT 7 + +#define SQ_ALU_WORD1_OP2_V2_SRC0_ABS_MASK 0x00000001 +#define SQ_ALU_WORD1_OP2_V2_SRC1_ABS_MASK 0x00000002 +#define SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_MASK 0x00000004 +#define SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_MASK 0x00000008 +#define SQ_ALU_WORD1_OP2_V2_WRITE_MASK_MASK 0x00000010 +#define SQ_ALU_WORD1_OP2_V2_OMOD_MASK 0x00000060 +#define SQ_ALU_WORD1_OP2_V2_ALU_INST_MASK 0x0003ff80 + +#define SQ_ALU_WORD1_OP2_V2_MASK \ + (SQ_ALU_WORD1_OP2_V2_SRC0_ABS_MASK | \ + SQ_ALU_WORD1_OP2_V2_SRC1_ABS_MASK | \ + SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_MASK | \ + SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_MASK | \ + SQ_ALU_WORD1_OP2_V2_WRITE_MASK_MASK | \ + SQ_ALU_WORD1_OP2_V2_OMOD_MASK | \ + SQ_ALU_WORD1_OP2_V2_ALU_INST_MASK) + +#define SQ_ALU_WORD1_OP2_V2_DEFAULT 0x0001cdcd + +#define SQ_ALU_WORD1_OP2_V2_GET_SRC0_ABS(sq_alu_word1_op2_v2) \ + ((sq_alu_word1_op2_v2 & SQ_ALU_WORD1_OP2_V2_SRC0_ABS_MASK) >> SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SHIFT) +#define SQ_ALU_WORD1_OP2_V2_GET_SRC1_ABS(sq_alu_word1_op2_v2) \ + ((sq_alu_word1_op2_v2 & SQ_ALU_WORD1_OP2_V2_SRC1_ABS_MASK) >> SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SHIFT) +#define SQ_ALU_WORD1_OP2_V2_GET_UPDATE_EXECUTE_MASK(sq_alu_word1_op2_v2) \ + ((sq_alu_word1_op2_v2 & SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_MASK) >> SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SHIFT) +#define SQ_ALU_WORD1_OP2_V2_GET_UPDATE_PRED(sq_alu_word1_op2_v2) \ + ((sq_alu_word1_op2_v2 & SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_MASK) >> SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SHIFT) +#define SQ_ALU_WORD1_OP2_V2_GET_WRITE_MASK(sq_alu_word1_op2_v2) \ + ((sq_alu_word1_op2_v2 & SQ_ALU_WORD1_OP2_V2_WRITE_MASK_MASK) >> SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SHIFT) +#define SQ_ALU_WORD1_OP2_V2_GET_OMOD(sq_alu_word1_op2_v2) \ + ((sq_alu_word1_op2_v2 & SQ_ALU_WORD1_OP2_V2_OMOD_MASK) >> SQ_ALU_WORD1_OP2_V2_OMOD_SHIFT) +#define SQ_ALU_WORD1_OP2_V2_GET_ALU_INST(sq_alu_word1_op2_v2) \ + ((sq_alu_word1_op2_v2 & SQ_ALU_WORD1_OP2_V2_ALU_INST_MASK) >> SQ_ALU_WORD1_OP2_V2_ALU_INST_SHIFT) + +#define SQ_ALU_WORD1_OP2_V2_SET_SRC0_ABS(sq_alu_word1_op2_v2_reg, src0_abs) \ + sq_alu_word1_op2_v2_reg = (sq_alu_word1_op2_v2_reg & ~SQ_ALU_WORD1_OP2_V2_SRC0_ABS_MASK) | (src0_abs << SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SHIFT) +#define SQ_ALU_WORD1_OP2_V2_SET_SRC1_ABS(sq_alu_word1_op2_v2_reg, src1_abs) \ + sq_alu_word1_op2_v2_reg = (sq_alu_word1_op2_v2_reg & ~SQ_ALU_WORD1_OP2_V2_SRC1_ABS_MASK) | (src1_abs << SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SHIFT) +#define SQ_ALU_WORD1_OP2_V2_SET_UPDATE_EXECUTE_MASK(sq_alu_word1_op2_v2_reg, update_execute_mask) \ + sq_alu_word1_op2_v2_reg = (sq_alu_word1_op2_v2_reg & ~SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_MASK) | (update_execute_mask << SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SHIFT) +#define SQ_ALU_WORD1_OP2_V2_SET_UPDATE_PRED(sq_alu_word1_op2_v2_reg, update_pred) \ + sq_alu_word1_op2_v2_reg = (sq_alu_word1_op2_v2_reg & ~SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_MASK) | (update_pred << SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SHIFT) +#define SQ_ALU_WORD1_OP2_V2_SET_WRITE_MASK(sq_alu_word1_op2_v2_reg, write_mask) \ + sq_alu_word1_op2_v2_reg = (sq_alu_word1_op2_v2_reg & ~SQ_ALU_WORD1_OP2_V2_WRITE_MASK_MASK) | (write_mask << SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SHIFT) +#define SQ_ALU_WORD1_OP2_V2_SET_OMOD(sq_alu_word1_op2_v2_reg, omod) \ + sq_alu_word1_op2_v2_reg = (sq_alu_word1_op2_v2_reg & ~SQ_ALU_WORD1_OP2_V2_OMOD_MASK) | (omod << SQ_ALU_WORD1_OP2_V2_OMOD_SHIFT) +#define SQ_ALU_WORD1_OP2_V2_SET_ALU_INST(sq_alu_word1_op2_v2_reg, alu_inst) \ + sq_alu_word1_op2_v2_reg = (sq_alu_word1_op2_v2_reg & ~SQ_ALU_WORD1_OP2_V2_ALU_INST_MASK) | (alu_inst << SQ_ALU_WORD1_OP2_V2_ALU_INST_SHIFT) + +#if defined(LITTLEENDIAN_CPU) + + typedef struct _sq_alu_word1_op2_v2_t { + unsigned int src0_abs : SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SIZE; + unsigned int src1_abs : SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SIZE; + unsigned int update_execute_mask : SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SIZE; + unsigned int update_pred : SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SIZE; + unsigned int write_mask : SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SIZE; + unsigned int omod : SQ_ALU_WORD1_OP2_V2_OMOD_SIZE; + unsigned int alu_inst : SQ_ALU_WORD1_OP2_V2_ALU_INST_SIZE; + unsigned int : 14; + } sq_alu_word1_op2_v2_t; + +#elif defined(BIGENDIAN_CPU) + + typedef struct _sq_alu_word1_op2_v2_t { + unsigned int : 14; + unsigned int alu_inst : SQ_ALU_WORD1_OP2_V2_ALU_INST_SIZE; + unsigned int omod : SQ_ALU_WORD1_OP2_V2_OMOD_SIZE; + unsigned int write_mask : SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SIZE; + unsigned int update_pred : SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SIZE; + unsigned int update_execute_mask : SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SIZE; + unsigned int src1_abs : SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SIZE; + unsigned int src0_abs : SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SIZE; + } sq_alu_word1_op2_v2_t; + +#endif + +#if defined(LITTLEENDIAN_CPU) + + typedef struct _sq_alu_word1_op2_r6xx_t { + unsigned int src0_abs : SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SIZE; + unsigned int src1_abs : SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SIZE; + unsigned int update_execute_mask : SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SIZE; + unsigned int update_pred : SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SIZE; + unsigned int write_mask : SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SIZE; + unsigned int fog_export : 1; + unsigned int omod : SQ_ALU_WORD1_OP2_V2_OMOD_SIZE; + unsigned int alu_inst : 10; + unsigned int : 14; + } sq_alu_word1_op2_v1_t; + +#elif defined(BIGENDIAN_CPU) + + typedef struct _sq_alu_word1_op2_r6xx_t { + unsigned int : 14; + unsigned int alu_inst : 10; + unsigned int omod : SQ_ALU_WORD1_OP2_V2_OMOD_SIZE; + unsigned int fog_export : 1; + unsigned int write_mask : SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SIZE; + unsigned int update_pred : SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SIZE; + unsigned int update_execute_mask : SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SIZE; + unsigned int src1_abs : SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SIZE; + unsigned int src0_abs : SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SIZE; + } sq_alu_word1_op2_v1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_alu_word1_op2_v2_t f; + sq_alu_word1_op2_v1_t f6; +} sq_alu_word1_op2_v2_u; + + +/* + * SQ_ALU_WORD1_OP3 struct + */ + +#define SQ_ALU_WORD1_OP3_SRC2_SEL_SIZE 9 +#define SQ_ALU_WORD1_OP3_SRC2_REL_SIZE 1 +#define SQ_ALU_WORD1_OP3_SRC2_CHAN_SIZE 2 +#define SQ_ALU_WORD1_OP3_SRC2_NEG_SIZE 1 +#define SQ_ALU_WORD1_OP3_ALU_INST_SIZE 5 + +#define SQ_ALU_WORD1_OP3_SRC2_SEL_SHIFT 0 +#define SQ_ALU_WORD1_OP3_SRC2_REL_SHIFT 9 +#define SQ_ALU_WORD1_OP3_SRC2_CHAN_SHIFT 10 +#define SQ_ALU_WORD1_OP3_SRC2_NEG_SHIFT 12 +#define SQ_ALU_WORD1_OP3_ALU_INST_SHIFT 13 + +#define SQ_ALU_WORD1_OP3_SRC2_SEL_MASK 0x000001ff +#define SQ_ALU_WORD1_OP3_SRC2_REL_MASK 0x00000200 +#define SQ_ALU_WORD1_OP3_SRC2_CHAN_MASK 0x00000c00 +#define SQ_ALU_WORD1_OP3_SRC2_NEG_MASK 0x00001000 +#define SQ_ALU_WORD1_OP3_ALU_INST_MASK 0x0003e000 + +#define SQ_ALU_WORD1_OP3_MASK \ + (SQ_ALU_WORD1_OP3_SRC2_SEL_MASK | \ + SQ_ALU_WORD1_OP3_SRC2_REL_MASK | \ + SQ_ALU_WORD1_OP3_SRC2_CHAN_MASK | \ + SQ_ALU_WORD1_OP3_SRC2_NEG_MASK | \ + SQ_ALU_WORD1_OP3_ALU_INST_MASK) + +#define SQ_ALU_WORD1_OP3_DEFAULT 0x0001cdcd + +#define SQ_ALU_WORD1_OP3_GET_SRC2_SEL(sq_alu_word1_op3) \ + ((sq_alu_word1_op3 & SQ_ALU_WORD1_OP3_SRC2_SEL_MASK) >> SQ_ALU_WORD1_OP3_SRC2_SEL_SHIFT) +#define SQ_ALU_WORD1_OP3_GET_SRC2_REL(sq_alu_word1_op3) \ + ((sq_alu_word1_op3 & SQ_ALU_WORD1_OP3_SRC2_REL_MASK) >> SQ_ALU_WORD1_OP3_SRC2_REL_SHIFT) +#define SQ_ALU_WORD1_OP3_GET_SRC2_CHAN(sq_alu_word1_op3) \ + ((sq_alu_word1_op3 & SQ_ALU_WORD1_OP3_SRC2_CHAN_MASK) >> SQ_ALU_WORD1_OP3_SRC2_CHAN_SHIFT) +#define SQ_ALU_WORD1_OP3_GET_SRC2_NEG(sq_alu_word1_op3) \ + ((sq_alu_word1_op3 & SQ_ALU_WORD1_OP3_SRC2_NEG_MASK) >> SQ_ALU_WORD1_OP3_SRC2_NEG_SHIFT) +#define SQ_ALU_WORD1_OP3_GET_ALU_INST(sq_alu_word1_op3) \ + ((sq_alu_word1_op3 & SQ_ALU_WORD1_OP3_ALU_INST_MASK) >> SQ_ALU_WORD1_OP3_ALU_INST_SHIFT) + +#define SQ_ALU_WORD1_OP3_SET_SRC2_SEL(sq_alu_word1_op3_reg, src2_sel) \ + sq_alu_word1_op3_reg = (sq_alu_word1_op3_reg & ~SQ_ALU_WORD1_OP3_SRC2_SEL_MASK) | (src2_sel << SQ_ALU_WORD1_OP3_SRC2_SEL_SHIFT) +#define SQ_ALU_WORD1_OP3_SET_SRC2_REL(sq_alu_word1_op3_reg, src2_rel) \ + sq_alu_word1_op3_reg = (sq_alu_word1_op3_reg & ~SQ_ALU_WORD1_OP3_SRC2_REL_MASK) | (src2_rel << SQ_ALU_WORD1_OP3_SRC2_REL_SHIFT) +#define SQ_ALU_WORD1_OP3_SET_SRC2_CHAN(sq_alu_word1_op3_reg, src2_chan) \ + sq_alu_word1_op3_reg = (sq_alu_word1_op3_reg & ~SQ_ALU_WORD1_OP3_SRC2_CHAN_MASK) | (src2_chan << SQ_ALU_WORD1_OP3_SRC2_CHAN_SHIFT) +#define SQ_ALU_WORD1_OP3_SET_SRC2_NEG(sq_alu_word1_op3_reg, src2_neg) \ + sq_alu_word1_op3_reg = (sq_alu_word1_op3_reg & ~SQ_ALU_WORD1_OP3_SRC2_NEG_MASK) | (src2_neg << SQ_ALU_WORD1_OP3_SRC2_NEG_SHIFT) +#define SQ_ALU_WORD1_OP3_SET_ALU_INST(sq_alu_word1_op3_reg, alu_inst) \ + sq_alu_word1_op3_reg = (sq_alu_word1_op3_reg & ~SQ_ALU_WORD1_OP3_ALU_INST_MASK) | (alu_inst << SQ_ALU_WORD1_OP3_ALU_INST_SHIFT) + +#if defined(LITTLEENDIAN_CPU) + + typedef struct _sq_alu_word1_op3_t { + unsigned int src2_sel : SQ_ALU_WORD1_OP3_SRC2_SEL_SIZE; + unsigned int src2_rel : SQ_ALU_WORD1_OP3_SRC2_REL_SIZE; + unsigned int src2_chan : SQ_ALU_WORD1_OP3_SRC2_CHAN_SIZE; + unsigned int src2_neg : SQ_ALU_WORD1_OP3_SRC2_NEG_SIZE; + unsigned int alu_inst : SQ_ALU_WORD1_OP3_ALU_INST_SIZE; + unsigned int : 14; + } sq_alu_word1_op3_t; + +#elif defined(BIGENDIAN_CPU) + + typedef struct _sq_alu_word1_op3_t { + unsigned int : 14; + unsigned int alu_inst : SQ_ALU_WORD1_OP3_ALU_INST_SIZE; + unsigned int src2_neg : SQ_ALU_WORD1_OP3_SRC2_NEG_SIZE; + unsigned int src2_chan : SQ_ALU_WORD1_OP3_SRC2_CHAN_SIZE; + unsigned int src2_rel : SQ_ALU_WORD1_OP3_SRC2_REL_SIZE; + unsigned int src2_sel : SQ_ALU_WORD1_OP3_SRC2_SEL_SIZE; + } sq_alu_word1_op3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_alu_word1_op3_t f; +} sq_alu_word1_op3_u; + + +/* + * SQ_TEX_WORD0 struct + */ + +#define SQ_TEX_WORD0_TEX_INST_SIZE 5 +#define SQ_TEX_WORD0_BC_FRAC_MODE_SIZE 1 +#define SQ_TEX_WORD0_FETCH_WHOLE_QUAD_SIZE 1 +#define SQ_TEX_WORD0_RESOURCE_ID_SIZE 8 +#define SQ_TEX_WORD0_SRC_GPR_SIZE 7 +#define SQ_TEX_WORD0_SRC_REL_SIZE 1 +#define SQ_TEX_WORD0_ALT_CONST_SIZE 1 + +#define SQ_TEX_WORD0_TEX_INST_SHIFT 0 +#define SQ_TEX_WORD0_BC_FRAC_MODE_SHIFT 5 +#define SQ_TEX_WORD0_FETCH_WHOLE_QUAD_SHIFT 7 +#define SQ_TEX_WORD0_RESOURCE_ID_SHIFT 8 +#define SQ_TEX_WORD0_SRC_GPR_SHIFT 16 +#define SQ_TEX_WORD0_SRC_REL_SHIFT 23 +#define SQ_TEX_WORD0_ALT_CONST_SHIFT 24 + +#define SQ_TEX_WORD0_TEX_INST_MASK 0x0000001f +#define SQ_TEX_WORD0_BC_FRAC_MODE_MASK 0x00000020 +#define SQ_TEX_WORD0_FETCH_WHOLE_QUAD_MASK 0x00000080 +#define SQ_TEX_WORD0_RESOURCE_ID_MASK 0x0000ff00 +#define SQ_TEX_WORD0_SRC_GPR_MASK 0x007f0000 +#define SQ_TEX_WORD0_SRC_REL_MASK 0x00800000 +#define SQ_TEX_WORD0_ALT_CONST_MASK 0x01000000 + +#define SQ_TEX_WORD0_MASK \ + (SQ_TEX_WORD0_TEX_INST_MASK | \ + SQ_TEX_WORD0_BC_FRAC_MODE_MASK | \ + SQ_TEX_WORD0_FETCH_WHOLE_QUAD_MASK | \ + SQ_TEX_WORD0_RESOURCE_ID_MASK | \ + SQ_TEX_WORD0_SRC_GPR_MASK | \ + SQ_TEX_WORD0_SRC_REL_MASK | \ + SQ_TEX_WORD0_ALT_CONST_MASK) + +#define SQ_TEX_WORD0_DEFAULT 0x01cdcd8d + +#define SQ_TEX_WORD0_GET_TEX_INST(sq_tex_word0) \ + ((sq_tex_word0 & SQ_TEX_WORD0_TEX_INST_MASK) >> SQ_TEX_WORD0_TEX_INST_SHIFT) +#define SQ_TEX_WORD0_GET_BC_FRAC_MODE(sq_tex_word0) \ + ((sq_tex_word0 & SQ_TEX_WORD0_BC_FRAC_MODE_MASK) >> SQ_TEX_WORD0_BC_FRAC_MODE_SHIFT) +#define SQ_TEX_WORD0_GET_FETCH_WHOLE_QUAD(sq_tex_word0) \ + ((sq_tex_word0 & SQ_TEX_WORD0_FETCH_WHOLE_QUAD_MASK) >> SQ_TEX_WORD0_FETCH_WHOLE_QUAD_SHIFT) +#define SQ_TEX_WORD0_GET_RESOURCE_ID(sq_tex_word0) \ + ((sq_tex_word0 & SQ_TEX_WORD0_RESOURCE_ID_MASK) >> SQ_TEX_WORD0_RESOURCE_ID_SHIFT) +#define SQ_TEX_WORD0_GET_SRC_GPR(sq_tex_word0) \ + ((sq_tex_word0 & SQ_TEX_WORD0_SRC_GPR_MASK) >> SQ_TEX_WORD0_SRC_GPR_SHIFT) +#define SQ_TEX_WORD0_GET_SRC_REL(sq_tex_word0) \ + ((sq_tex_word0 & SQ_TEX_WORD0_SRC_REL_MASK) >> SQ_TEX_WORD0_SRC_REL_SHIFT) +#define SQ_TEX_WORD0_GET_ALT_CONST(sq_tex_word0) \ + ((sq_tex_word0 & SQ_TEX_WORD0_ALT_CONST_MASK) >> SQ_TEX_WORD0_ALT_CONST_SHIFT) + +#define SQ_TEX_WORD0_SET_TEX_INST(sq_tex_word0_reg, tex_inst) \ + sq_tex_word0_reg = (sq_tex_word0_reg & ~SQ_TEX_WORD0_TEX_INST_MASK) | (tex_inst << SQ_TEX_WORD0_TEX_INST_SHIFT) +#define SQ_TEX_WORD0_SET_BC_FRAC_MODE(sq_tex_word0_reg, bc_frac_mode) \ + sq_tex_word0_reg = (sq_tex_word0_reg & ~SQ_TEX_WORD0_BC_FRAC_MODE_MASK) | (bc_frac_mode << SQ_TEX_WORD0_BC_FRAC_MODE_SHIFT) +#define SQ_TEX_WORD0_SET_FETCH_WHOLE_QUAD(sq_tex_word0_reg, fetch_whole_quad) \ + sq_tex_word0_reg = (sq_tex_word0_reg & ~SQ_TEX_WORD0_FETCH_WHOLE_QUAD_MASK) | (fetch_whole_quad << SQ_TEX_WORD0_FETCH_WHOLE_QUAD_SHIFT) +#define SQ_TEX_WORD0_SET_RESOURCE_ID(sq_tex_word0_reg, resource_id) \ + sq_tex_word0_reg = (sq_tex_word0_reg & ~SQ_TEX_WORD0_RESOURCE_ID_MASK) | (resource_id << SQ_TEX_WORD0_RESOURCE_ID_SHIFT) +#define SQ_TEX_WORD0_SET_SRC_GPR(sq_tex_word0_reg, src_gpr) \ + sq_tex_word0_reg = (sq_tex_word0_reg & ~SQ_TEX_WORD0_SRC_GPR_MASK) | (src_gpr << SQ_TEX_WORD0_SRC_GPR_SHIFT) +#define SQ_TEX_WORD0_SET_SRC_REL(sq_tex_word0_reg, src_rel) \ + sq_tex_word0_reg = (sq_tex_word0_reg & ~SQ_TEX_WORD0_SRC_REL_MASK) | (src_rel << SQ_TEX_WORD0_SRC_REL_SHIFT) +#define SQ_TEX_WORD0_SET_ALT_CONST(sq_tex_word0_reg, alt_const) \ + sq_tex_word0_reg = (sq_tex_word0_reg & ~SQ_TEX_WORD0_ALT_CONST_MASK) | (alt_const << SQ_TEX_WORD0_ALT_CONST_SHIFT) + +#if defined(LITTLEENDIAN_CPU) + + typedef struct _sq_tex_word0_t { + unsigned int tex_inst : SQ_TEX_WORD0_TEX_INST_SIZE; + unsigned int bc_frac_mode : SQ_TEX_WORD0_BC_FRAC_MODE_SIZE; + unsigned int : 1; + unsigned int fetch_whole_quad : SQ_TEX_WORD0_FETCH_WHOLE_QUAD_SIZE; + unsigned int resource_id : SQ_TEX_WORD0_RESOURCE_ID_SIZE; + unsigned int src_gpr : SQ_TEX_WORD0_SRC_GPR_SIZE; + unsigned int src_rel : SQ_TEX_WORD0_SRC_REL_SIZE; + unsigned int alt_const : SQ_TEX_WORD0_ALT_CONST_SIZE; + unsigned int : 7; + } sq_tex_word0_t; + +#elif defined(BIGENDIAN_CPU) + + typedef struct _sq_tex_word0_t { + unsigned int : 7; + unsigned int alt_const : SQ_TEX_WORD0_ALT_CONST_SIZE; + unsigned int src_rel : SQ_TEX_WORD0_SRC_REL_SIZE; + unsigned int src_gpr : SQ_TEX_WORD0_SRC_GPR_SIZE; + unsigned int resource_id : SQ_TEX_WORD0_RESOURCE_ID_SIZE; + unsigned int fetch_whole_quad : SQ_TEX_WORD0_FETCH_WHOLE_QUAD_SIZE; + unsigned int : 1; + unsigned int bc_frac_mode : SQ_TEX_WORD0_BC_FRAC_MODE_SIZE; + unsigned int tex_inst : SQ_TEX_WORD0_TEX_INST_SIZE; + } sq_tex_word0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_tex_word0_t f; +} sq_tex_word0_u; + + +/* + * SQ_TEX_WORD1 struct + */ + +#define SQ_TEX_WORD1_DST_GPR_SIZE 7 +#define SQ_TEX_WORD1_DST_REL_SIZE 1 +#define SQ_TEX_WORD1_DST_SEL_X_SIZE 3 +#define SQ_TEX_WORD1_DST_SEL_Y_SIZE 3 +#define SQ_TEX_WORD1_DST_SEL_Z_SIZE 3 +#define SQ_TEX_WORD1_DST_SEL_W_SIZE 3 +#define SQ_TEX_WORD1_LOD_BIAS_SIZE 7 +#define SQ_TEX_WORD1_COORD_TYPE_X_SIZE 1 +#define SQ_TEX_WORD1_COORD_TYPE_Y_SIZE 1 +#define SQ_TEX_WORD1_COORD_TYPE_Z_SIZE 1 +#define SQ_TEX_WORD1_COORD_TYPE_W_SIZE 1 + +#define SQ_TEX_WORD1_DST_GPR_SHIFT 0 +#define SQ_TEX_WORD1_DST_REL_SHIFT 7 +#define SQ_TEX_WORD1_DST_SEL_X_SHIFT 9 +#define SQ_TEX_WORD1_DST_SEL_Y_SHIFT 12 +#define SQ_TEX_WORD1_DST_SEL_Z_SHIFT 15 +#define SQ_TEX_WORD1_DST_SEL_W_SHIFT 18 +#define SQ_TEX_WORD1_LOD_BIAS_SHIFT 21 +#define SQ_TEX_WORD1_COORD_TYPE_X_SHIFT 28 +#define SQ_TEX_WORD1_COORD_TYPE_Y_SHIFT 29 +#define SQ_TEX_WORD1_COORD_TYPE_Z_SHIFT 30 +#define SQ_TEX_WORD1_COORD_TYPE_W_SHIFT 31 + +#define SQ_TEX_WORD1_DST_GPR_MASK 0x0000007f +#define SQ_TEX_WORD1_DST_REL_MASK 0x00000080 +#define SQ_TEX_WORD1_DST_SEL_X_MASK 0x00000e00 +#define SQ_TEX_WORD1_DST_SEL_Y_MASK 0x00007000 +#define SQ_TEX_WORD1_DST_SEL_Z_MASK 0x00038000 +#define SQ_TEX_WORD1_DST_SEL_W_MASK 0x001c0000 +#define SQ_TEX_WORD1_LOD_BIAS_MASK 0x0fe00000 +#define SQ_TEX_WORD1_COORD_TYPE_X_MASK 0x10000000 +#define SQ_TEX_WORD1_COORD_TYPE_Y_MASK 0x20000000 +#define SQ_TEX_WORD1_COORD_TYPE_Z_MASK 0x40000000 +#define SQ_TEX_WORD1_COORD_TYPE_W_MASK 0x80000000 + +#define SQ_TEX_WORD1_MASK \ + (SQ_TEX_WORD1_DST_GPR_MASK | \ + SQ_TEX_WORD1_DST_REL_MASK | \ + SQ_TEX_WORD1_DST_SEL_X_MASK | \ + SQ_TEX_WORD1_DST_SEL_Y_MASK | \ + SQ_TEX_WORD1_DST_SEL_Z_MASK | \ + SQ_TEX_WORD1_DST_SEL_W_MASK | \ + SQ_TEX_WORD1_LOD_BIAS_MASK | \ + SQ_TEX_WORD1_COORD_TYPE_X_MASK | \ + SQ_TEX_WORD1_COORD_TYPE_Y_MASK | \ + SQ_TEX_WORD1_COORD_TYPE_Z_MASK | \ + SQ_TEX_WORD1_COORD_TYPE_W_MASK) + +#define SQ_TEX_WORD1_DEFAULT 0xcdcdcccd + +#define SQ_TEX_WORD1_GET_DST_GPR(sq_tex_word1) \ + ((sq_tex_word1 & SQ_TEX_WORD1_DST_GPR_MASK) >> SQ_TEX_WORD1_DST_GPR_SHIFT) +#define SQ_TEX_WORD1_GET_DST_REL(sq_tex_word1) \ + ((sq_tex_word1 & SQ_TEX_WORD1_DST_REL_MASK) >> SQ_TEX_WORD1_DST_REL_SHIFT) +#define SQ_TEX_WORD1_GET_DST_SEL_X(sq_tex_word1) \ + ((sq_tex_word1 & SQ_TEX_WORD1_DST_SEL_X_MASK) >> SQ_TEX_WORD1_DST_SEL_X_SHIFT) +#define SQ_TEX_WORD1_GET_DST_SEL_Y(sq_tex_word1) \ + ((sq_tex_word1 & SQ_TEX_WORD1_DST_SEL_Y_MASK) >> SQ_TEX_WORD1_DST_SEL_Y_SHIFT) +#define SQ_TEX_WORD1_GET_DST_SEL_Z(sq_tex_word1) \ + ((sq_tex_word1 & SQ_TEX_WORD1_DST_SEL_Z_MASK) >> SQ_TEX_WORD1_DST_SEL_Z_SHIFT) +#define SQ_TEX_WORD1_GET_DST_SEL_W(sq_tex_word1) \ + ((sq_tex_word1 & SQ_TEX_WORD1_DST_SEL_W_MASK) >> SQ_TEX_WORD1_DST_SEL_W_SHIFT) +#define SQ_TEX_WORD1_GET_LOD_BIAS(sq_tex_word1) \ + ((sq_tex_word1 & SQ_TEX_WORD1_LOD_BIAS_MASK) >> SQ_TEX_WORD1_LOD_BIAS_SHIFT) +#define SQ_TEX_WORD1_GET_COORD_TYPE_X(sq_tex_word1) \ + ((sq_tex_word1 & SQ_TEX_WORD1_COORD_TYPE_X_MASK) >> SQ_TEX_WORD1_COORD_TYPE_X_SHIFT) +#define SQ_TEX_WORD1_GET_COORD_TYPE_Y(sq_tex_word1) \ + ((sq_tex_word1 & SQ_TEX_WORD1_COORD_TYPE_Y_MASK) >> SQ_TEX_WORD1_COORD_TYPE_Y_SHIFT) +#define SQ_TEX_WORD1_GET_COORD_TYPE_Z(sq_tex_word1) \ + ((sq_tex_word1 & SQ_TEX_WORD1_COORD_TYPE_Z_MASK) >> SQ_TEX_WORD1_COORD_TYPE_Z_SHIFT) +#define SQ_TEX_WORD1_GET_COORD_TYPE_W(sq_tex_word1) \ + ((sq_tex_word1 & SQ_TEX_WORD1_COORD_TYPE_W_MASK) >> SQ_TEX_WORD1_COORD_TYPE_W_SHIFT) + +#define SQ_TEX_WORD1_SET_DST_GPR(sq_tex_word1_reg, dst_gpr) \ + sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_DST_GPR_MASK) | (dst_gpr << SQ_TEX_WORD1_DST_GPR_SHIFT) +#define SQ_TEX_WORD1_SET_DST_REL(sq_tex_word1_reg, dst_rel) \ + sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_DST_REL_MASK) | (dst_rel << SQ_TEX_WORD1_DST_REL_SHIFT) +#define SQ_TEX_WORD1_SET_DST_SEL_X(sq_tex_word1_reg, dst_sel_x) \ + sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_DST_SEL_X_MASK) | (dst_sel_x << SQ_TEX_WORD1_DST_SEL_X_SHIFT) +#define SQ_TEX_WORD1_SET_DST_SEL_Y(sq_tex_word1_reg, dst_sel_y) \ + sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_TEX_WORD1_DST_SEL_Y_SHIFT) +#define SQ_TEX_WORD1_SET_DST_SEL_Z(sq_tex_word1_reg, dst_sel_z) \ + sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_TEX_WORD1_DST_SEL_Z_SHIFT) +#define SQ_TEX_WORD1_SET_DST_SEL_W(sq_tex_word1_reg, dst_sel_w) \ + sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_DST_SEL_W_MASK) | (dst_sel_w << SQ_TEX_WORD1_DST_SEL_W_SHIFT) +#define SQ_TEX_WORD1_SET_LOD_BIAS(sq_tex_word1_reg, lod_bias) \ + sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_LOD_BIAS_MASK) | (lod_bias << SQ_TEX_WORD1_LOD_BIAS_SHIFT) +#define SQ_TEX_WORD1_SET_COORD_TYPE_X(sq_tex_word1_reg, coord_type_x) \ + sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_COORD_TYPE_X_MASK) | (coord_type_x << SQ_TEX_WORD1_COORD_TYPE_X_SHIFT) +#define SQ_TEX_WORD1_SET_COORD_TYPE_Y(sq_tex_word1_reg, coord_type_y) \ + sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_COORD_TYPE_Y_MASK) | (coord_type_y << SQ_TEX_WORD1_COORD_TYPE_Y_SHIFT) +#define SQ_TEX_WORD1_SET_COORD_TYPE_Z(sq_tex_word1_reg, coord_type_z) \ + sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_COORD_TYPE_Z_MASK) | (coord_type_z << SQ_TEX_WORD1_COORD_TYPE_Z_SHIFT) +#define SQ_TEX_WORD1_SET_COORD_TYPE_W(sq_tex_word1_reg, coord_type_w) \ + sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_COORD_TYPE_W_MASK) | (coord_type_w << SQ_TEX_WORD1_COORD_TYPE_W_SHIFT) + +#if defined(LITTLEENDIAN_CPU) + + typedef struct _sq_tex_word1_t { + unsigned int dst_gpr : SQ_TEX_WORD1_DST_GPR_SIZE; + unsigned int dst_rel : SQ_TEX_WORD1_DST_REL_SIZE; + unsigned int : 1; + unsigned int dst_sel_x : SQ_TEX_WORD1_DST_SEL_X_SIZE; + unsigned int dst_sel_y : SQ_TEX_WORD1_DST_SEL_Y_SIZE; + unsigned int dst_sel_z : SQ_TEX_WORD1_DST_SEL_Z_SIZE; + unsigned int dst_sel_w : SQ_TEX_WORD1_DST_SEL_W_SIZE; + unsigned int lod_bias : SQ_TEX_WORD1_LOD_BIAS_SIZE; + unsigned int coord_type_x : SQ_TEX_WORD1_COORD_TYPE_X_SIZE; + unsigned int coord_type_y : SQ_TEX_WORD1_COORD_TYPE_Y_SIZE; + unsigned int coord_type_z : SQ_TEX_WORD1_COORD_TYPE_Z_SIZE; + unsigned int coord_type_w : SQ_TEX_WORD1_COORD_TYPE_W_SIZE; + } sq_tex_word1_t; + +#elif defined(BIGENDIAN_CPU) + + typedef struct _sq_tex_word1_t { + unsigned int coord_type_w : SQ_TEX_WORD1_COORD_TYPE_W_SIZE; + unsigned int coord_type_z : SQ_TEX_WORD1_COORD_TYPE_Z_SIZE; + unsigned int coord_type_y : SQ_TEX_WORD1_COORD_TYPE_Y_SIZE; + unsigned int coord_type_x : SQ_TEX_WORD1_COORD_TYPE_X_SIZE; + unsigned int lod_bias : SQ_TEX_WORD1_LOD_BIAS_SIZE; + unsigned int dst_sel_w : SQ_TEX_WORD1_DST_SEL_W_SIZE; + unsigned int dst_sel_z : SQ_TEX_WORD1_DST_SEL_Z_SIZE; + unsigned int dst_sel_y : SQ_TEX_WORD1_DST_SEL_Y_SIZE; + unsigned int dst_sel_x : SQ_TEX_WORD1_DST_SEL_X_SIZE; + unsigned int : 1; + unsigned int dst_rel : SQ_TEX_WORD1_DST_REL_SIZE; + unsigned int dst_gpr : SQ_TEX_WORD1_DST_GPR_SIZE; + } sq_tex_word1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_tex_word1_t f; +} sq_tex_word1_u; + + +/* + * SQ_TEX_WORD2 struct + */ + +#define SQ_TEX_WORD2_OFFSET_X_SIZE 5 +#define SQ_TEX_WORD2_OFFSET_Y_SIZE 5 +#define SQ_TEX_WORD2_OFFSET_Z_SIZE 5 +#define SQ_TEX_WORD2_SAMPLER_ID_SIZE 5 +#define SQ_TEX_WORD2_SRC_SEL_X_SIZE 3 +#define SQ_TEX_WORD2_SRC_SEL_Y_SIZE 3 +#define SQ_TEX_WORD2_SRC_SEL_Z_SIZE 3 +#define SQ_TEX_WORD2_SRC_SEL_W_SIZE 3 + +#define SQ_TEX_WORD2_OFFSET_X_SHIFT 0 +#define SQ_TEX_WORD2_OFFSET_Y_SHIFT 5 +#define SQ_TEX_WORD2_OFFSET_Z_SHIFT 10 +#define SQ_TEX_WORD2_SAMPLER_ID_SHIFT 15 +#define SQ_TEX_WORD2_SRC_SEL_X_SHIFT 20 +#define SQ_TEX_WORD2_SRC_SEL_Y_SHIFT 23 +#define SQ_TEX_WORD2_SRC_SEL_Z_SHIFT 26 +#define SQ_TEX_WORD2_SRC_SEL_W_SHIFT 29 + +#define SQ_TEX_WORD2_OFFSET_X_MASK 0x0000001f +#define SQ_TEX_WORD2_OFFSET_Y_MASK 0x000003e0 +#define SQ_TEX_WORD2_OFFSET_Z_MASK 0x00007c00 +#define SQ_TEX_WORD2_SAMPLER_ID_MASK 0x000f8000 +#define SQ_TEX_WORD2_SRC_SEL_X_MASK 0x00700000 +#define SQ_TEX_WORD2_SRC_SEL_Y_MASK 0x03800000 +#define SQ_TEX_WORD2_SRC_SEL_Z_MASK 0x1c000000 +#define SQ_TEX_WORD2_SRC_SEL_W_MASK 0xe0000000 + +#define SQ_TEX_WORD2_MASK \ + (SQ_TEX_WORD2_OFFSET_X_MASK | \ + SQ_TEX_WORD2_OFFSET_Y_MASK | \ + SQ_TEX_WORD2_OFFSET_Z_MASK | \ + SQ_TEX_WORD2_SAMPLER_ID_MASK | \ + SQ_TEX_WORD2_SRC_SEL_X_MASK | \ + SQ_TEX_WORD2_SRC_SEL_Y_MASK | \ + SQ_TEX_WORD2_SRC_SEL_Z_MASK | \ + SQ_TEX_WORD2_SRC_SEL_W_MASK) + +#define SQ_TEX_WORD2_DEFAULT 0xcdcdcdcd + +#define SQ_TEX_WORD2_GET_OFFSET_X(sq_tex_word2) \ + ((sq_tex_word2 & SQ_TEX_WORD2_OFFSET_X_MASK) >> SQ_TEX_WORD2_OFFSET_X_SHIFT) +#define SQ_TEX_WORD2_GET_OFFSET_Y(sq_tex_word2) \ + ((sq_tex_word2 & SQ_TEX_WORD2_OFFSET_Y_MASK) >> SQ_TEX_WORD2_OFFSET_Y_SHIFT) +#define SQ_TEX_WORD2_GET_OFFSET_Z(sq_tex_word2) \ + ((sq_tex_word2 & SQ_TEX_WORD2_OFFSET_Z_MASK) >> SQ_TEX_WORD2_OFFSET_Z_SHIFT) +#define SQ_TEX_WORD2_GET_SAMPLER_ID(sq_tex_word2) \ + ((sq_tex_word2 & SQ_TEX_WORD2_SAMPLER_ID_MASK) >> SQ_TEX_WORD2_SAMPLER_ID_SHIFT) +#define SQ_TEX_WORD2_GET_SRC_SEL_X(sq_tex_word2) \ + ((sq_tex_word2 & SQ_TEX_WORD2_SRC_SEL_X_MASK) >> SQ_TEX_WORD2_SRC_SEL_X_SHIFT) +#define SQ_TEX_WORD2_GET_SRC_SEL_Y(sq_tex_word2) \ + ((sq_tex_word2 & SQ_TEX_WORD2_SRC_SEL_Y_MASK) >> SQ_TEX_WORD2_SRC_SEL_Y_SHIFT) +#define SQ_TEX_WORD2_GET_SRC_SEL_Z(sq_tex_word2) \ + ((sq_tex_word2 & SQ_TEX_WORD2_SRC_SEL_Z_MASK) >> SQ_TEX_WORD2_SRC_SEL_Z_SHIFT) +#define SQ_TEX_WORD2_GET_SRC_SEL_W(sq_tex_word2) \ + ((sq_tex_word2 & SQ_TEX_WORD2_SRC_SEL_W_MASK) >> SQ_TEX_WORD2_SRC_SEL_W_SHIFT) + +#define SQ_TEX_WORD2_SET_OFFSET_X(sq_tex_word2_reg, offset_x) \ + sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_OFFSET_X_MASK) | (offset_x << SQ_TEX_WORD2_OFFSET_X_SHIFT) +#define SQ_TEX_WORD2_SET_OFFSET_Y(sq_tex_word2_reg, offset_y) \ + sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_OFFSET_Y_MASK) | (offset_y << SQ_TEX_WORD2_OFFSET_Y_SHIFT) +#define SQ_TEX_WORD2_SET_OFFSET_Z(sq_tex_word2_reg, offset_z) \ + sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_OFFSET_Z_MASK) | (offset_z << SQ_TEX_WORD2_OFFSET_Z_SHIFT) +#define SQ_TEX_WORD2_SET_SAMPLER_ID(sq_tex_word2_reg, sampler_id) \ + sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_SAMPLER_ID_MASK) | (sampler_id << SQ_TEX_WORD2_SAMPLER_ID_SHIFT) +#define SQ_TEX_WORD2_SET_SRC_SEL_X(sq_tex_word2_reg, src_sel_x) \ + sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_SRC_SEL_X_MASK) | (src_sel_x << SQ_TEX_WORD2_SRC_SEL_X_SHIFT) +#define SQ_TEX_WORD2_SET_SRC_SEL_Y(sq_tex_word2_reg, src_sel_y) \ + sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_SRC_SEL_Y_MASK) | (src_sel_y << SQ_TEX_WORD2_SRC_SEL_Y_SHIFT) +#define SQ_TEX_WORD2_SET_SRC_SEL_Z(sq_tex_word2_reg, src_sel_z) \ + sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_SRC_SEL_Z_MASK) | (src_sel_z << SQ_TEX_WORD2_SRC_SEL_Z_SHIFT) +#define SQ_TEX_WORD2_SET_SRC_SEL_W(sq_tex_word2_reg, src_sel_w) \ + sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_SRC_SEL_W_MASK) | (src_sel_w << SQ_TEX_WORD2_SRC_SEL_W_SHIFT) + +#if defined(LITTLEENDIAN_CPU) + + typedef struct _sq_tex_word2_t { + unsigned int offset_x : SQ_TEX_WORD2_OFFSET_X_SIZE; + unsigned int offset_y : SQ_TEX_WORD2_OFFSET_Y_SIZE; + unsigned int offset_z : SQ_TEX_WORD2_OFFSET_Z_SIZE; + unsigned int sampler_id : SQ_TEX_WORD2_SAMPLER_ID_SIZE; + unsigned int src_sel_x : SQ_TEX_WORD2_SRC_SEL_X_SIZE; + unsigned int src_sel_y : SQ_TEX_WORD2_SRC_SEL_Y_SIZE; + unsigned int src_sel_z : SQ_TEX_WORD2_SRC_SEL_Z_SIZE; + unsigned int src_sel_w : SQ_TEX_WORD2_SRC_SEL_W_SIZE; + } sq_tex_word2_t; + +#elif defined(BIGENDIAN_CPU) + + typedef struct _sq_tex_word2_t { + unsigned int src_sel_w : SQ_TEX_WORD2_SRC_SEL_W_SIZE; + unsigned int src_sel_z : SQ_TEX_WORD2_SRC_SEL_Z_SIZE; + unsigned int src_sel_y : SQ_TEX_WORD2_SRC_SEL_Y_SIZE; + unsigned int src_sel_x : SQ_TEX_WORD2_SRC_SEL_X_SIZE; + unsigned int sampler_id : SQ_TEX_WORD2_SAMPLER_ID_SIZE; + unsigned int offset_z : SQ_TEX_WORD2_OFFSET_Z_SIZE; + unsigned int offset_y : SQ_TEX_WORD2_OFFSET_Y_SIZE; + unsigned int offset_x : SQ_TEX_WORD2_OFFSET_X_SIZE; + } sq_tex_word2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_tex_word2_t f; +} sq_tex_word2_u; + + +/* + * SQ_VTX_WORD0 struct + */ + +#define SQ_VTX_WORD0_VTX_INST_SIZE 5 +#define SQ_VTX_WORD0_FETCH_TYPE_SIZE 2 +#define SQ_VTX_WORD0_FETCH_WHOLE_QUAD_SIZE 1 +#define SQ_VTX_WORD0_BUFFER_ID_SIZE 8 +#define SQ_VTX_WORD0_SRC_GPR_SIZE 7 +#define SQ_VTX_WORD0_SRC_REL_SIZE 1 +#define SQ_VTX_WORD0_SRC_SEL_X_SIZE 2 +#define SQ_VTX_WORD0_MEGA_FETCH_COUNT_SIZE 6 + +#define SQ_VTX_WORD0_VTX_INST_SHIFT 0 +#define SQ_VTX_WORD0_FETCH_TYPE_SHIFT 5 +#define SQ_VTX_WORD0_FETCH_WHOLE_QUAD_SHIFT 7 +#define SQ_VTX_WORD0_BUFFER_ID_SHIFT 8 +#define SQ_VTX_WORD0_SRC_GPR_SHIFT 16 +#define SQ_VTX_WORD0_SRC_REL_SHIFT 23 +#define SQ_VTX_WORD0_SRC_SEL_X_SHIFT 24 +#define SQ_VTX_WORD0_MEGA_FETCH_COUNT_SHIFT 26 + +#define SQ_VTX_WORD0_VTX_INST_MASK 0x0000001f +#define SQ_VTX_WORD0_FETCH_TYPE_MASK 0x00000060 +#define SQ_VTX_WORD0_FETCH_WHOLE_QUAD_MASK 0x00000080 +#define SQ_VTX_WORD0_BUFFER_ID_MASK 0x0000ff00 +#define SQ_VTX_WORD0_SRC_GPR_MASK 0x007f0000 +#define SQ_VTX_WORD0_SRC_REL_MASK 0x00800000 +#define SQ_VTX_WORD0_SRC_SEL_X_MASK 0x03000000 +#define SQ_VTX_WORD0_MEGA_FETCH_COUNT_MASK 0xfc000000 + +#define SQ_VTX_WORD0_MASK \ + (SQ_VTX_WORD0_VTX_INST_MASK | \ + SQ_VTX_WORD0_FETCH_TYPE_MASK | \ + SQ_VTX_WORD0_FETCH_WHOLE_QUAD_MASK | \ + SQ_VTX_WORD0_BUFFER_ID_MASK | \ + SQ_VTX_WORD0_SRC_GPR_MASK | \ + SQ_VTX_WORD0_SRC_REL_MASK | \ + SQ_VTX_WORD0_SRC_SEL_X_MASK | \ + SQ_VTX_WORD0_MEGA_FETCH_COUNT_MASK) + +#define SQ_VTX_WORD0_DEFAULT 0xcdcdcdcd + +#define SQ_VTX_WORD0_GET_VTX_INST(sq_vtx_word0) \ + ((sq_vtx_word0 & SQ_VTX_WORD0_VTX_INST_MASK) >> SQ_VTX_WORD0_VTX_INST_SHIFT) +#define SQ_VTX_WORD0_GET_FETCH_TYPE(sq_vtx_word0) \ + ((sq_vtx_word0 & SQ_VTX_WORD0_FETCH_TYPE_MASK) >> SQ_VTX_WORD0_FETCH_TYPE_SHIFT) +#define SQ_VTX_WORD0_GET_FETCH_WHOLE_QUAD(sq_vtx_word0) \ + ((sq_vtx_word0 & SQ_VTX_WORD0_FETCH_WHOLE_QUAD_MASK) >> SQ_VTX_WORD0_FETCH_WHOLE_QUAD_SHIFT) +#define SQ_VTX_WORD0_GET_BUFFER_ID(sq_vtx_word0) \ + ((sq_vtx_word0 & SQ_VTX_WORD0_BUFFER_ID_MASK) >> SQ_VTX_WORD0_BUFFER_ID_SHIFT) +#define SQ_VTX_WORD0_GET_SRC_GPR(sq_vtx_word0) \ + ((sq_vtx_word0 & SQ_VTX_WORD0_SRC_GPR_MASK) >> SQ_VTX_WORD0_SRC_GPR_SHIFT) +#define SQ_VTX_WORD0_GET_SRC_REL(sq_vtx_word0) \ + ((sq_vtx_word0 & SQ_VTX_WORD0_SRC_REL_MASK) >> SQ_VTX_WORD0_SRC_REL_SHIFT) +#define SQ_VTX_WORD0_GET_SRC_SEL_X(sq_vtx_word0) \ + ((sq_vtx_word0 & SQ_VTX_WORD0_SRC_SEL_X_MASK) >> SQ_VTX_WORD0_SRC_SEL_X_SHIFT) +#define SQ_VTX_WORD0_GET_MEGA_FETCH_COUNT(sq_vtx_word0) \ + ((sq_vtx_word0 & SQ_VTX_WORD0_MEGA_FETCH_COUNT_MASK) >> SQ_VTX_WORD0_MEGA_FETCH_COUNT_SHIFT) + +#define SQ_VTX_WORD0_SET_VTX_INST(sq_vtx_word0_reg, vtx_inst) \ + sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_VTX_INST_MASK) | (vtx_inst << SQ_VTX_WORD0_VTX_INST_SHIFT) +#define SQ_VTX_WORD0_SET_FETCH_TYPE(sq_vtx_word0_reg, fetch_type) \ + sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_FETCH_TYPE_MASK) | (fetch_type << SQ_VTX_WORD0_FETCH_TYPE_SHIFT) +#define SQ_VTX_WORD0_SET_FETCH_WHOLE_QUAD(sq_vtx_word0_reg, fetch_whole_quad) \ + sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_FETCH_WHOLE_QUAD_MASK) | (fetch_whole_quad << SQ_VTX_WORD0_FETCH_WHOLE_QUAD_SHIFT) +#define SQ_VTX_WORD0_SET_BUFFER_ID(sq_vtx_word0_reg, buffer_id) \ + sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_BUFFER_ID_MASK) | (buffer_id << SQ_VTX_WORD0_BUFFER_ID_SHIFT) +#define SQ_VTX_WORD0_SET_SRC_GPR(sq_vtx_word0_reg, src_gpr) \ + sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_SRC_GPR_MASK) | (src_gpr << SQ_VTX_WORD0_SRC_GPR_SHIFT) +#define SQ_VTX_WORD0_SET_SRC_REL(sq_vtx_word0_reg, src_rel) \ + sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_SRC_REL_MASK) | (src_rel << SQ_VTX_WORD0_SRC_REL_SHIFT) +#define SQ_VTX_WORD0_SET_SRC_SEL_X(sq_vtx_word0_reg, src_sel_x) \ + sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_SRC_SEL_X_MASK) | (src_sel_x << SQ_VTX_WORD0_SRC_SEL_X_SHIFT) +#define SQ_VTX_WORD0_SET_MEGA_FETCH_COUNT(sq_vtx_word0_reg, mega_fetch_count) \ + sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_MEGA_FETCH_COUNT_MASK) | (mega_fetch_count << SQ_VTX_WORD0_MEGA_FETCH_COUNT_SHIFT) + +#if defined(LITTLEENDIAN_CPU) + + typedef struct _sq_vtx_word0_t { + unsigned int vtx_inst : SQ_VTX_WORD0_VTX_INST_SIZE; + unsigned int fetch_type : SQ_VTX_WORD0_FETCH_TYPE_SIZE; + unsigned int fetch_whole_quad : SQ_VTX_WORD0_FETCH_WHOLE_QUAD_SIZE; + unsigned int buffer_id : SQ_VTX_WORD0_BUFFER_ID_SIZE; + unsigned int src_gpr : SQ_VTX_WORD0_SRC_GPR_SIZE; + unsigned int src_rel : SQ_VTX_WORD0_SRC_REL_SIZE; + unsigned int src_sel_x : SQ_VTX_WORD0_SRC_SEL_X_SIZE; + unsigned int mega_fetch_count : SQ_VTX_WORD0_MEGA_FETCH_COUNT_SIZE; + } sq_vtx_word0_t; + +#elif defined(BIGENDIAN_CPU) + + typedef struct _sq_vtx_word0_t { + unsigned int mega_fetch_count : SQ_VTX_WORD0_MEGA_FETCH_COUNT_SIZE; + unsigned int src_sel_x : SQ_VTX_WORD0_SRC_SEL_X_SIZE; + unsigned int src_rel : SQ_VTX_WORD0_SRC_REL_SIZE; + unsigned int src_gpr : SQ_VTX_WORD0_SRC_GPR_SIZE; + unsigned int buffer_id : SQ_VTX_WORD0_BUFFER_ID_SIZE; + unsigned int fetch_whole_quad : SQ_VTX_WORD0_FETCH_WHOLE_QUAD_SIZE; + unsigned int fetch_type : SQ_VTX_WORD0_FETCH_TYPE_SIZE; + unsigned int vtx_inst : SQ_VTX_WORD0_VTX_INST_SIZE; + } sq_vtx_word0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vtx_word0_t f; +} sq_vtx_word0_u; + + +/* + * SQ_VTX_WORD1 struct + */ + +#define SQ_VTX_WORD1_DST_SEL_X_SIZE 3 +#define SQ_VTX_WORD1_DST_SEL_Y_SIZE 3 +#define SQ_VTX_WORD1_DST_SEL_Z_SIZE 3 +#define SQ_VTX_WORD1_DST_SEL_W_SIZE 3 +#define SQ_VTX_WORD1_USE_CONST_FIELDS_SIZE 1 +#define SQ_VTX_WORD1_DATA_FORMAT_SIZE 6 +#define SQ_VTX_WORD1_NUM_FORMAT_ALL_SIZE 2 +#define SQ_VTX_WORD1_FORMAT_COMP_ALL_SIZE 1 +#define SQ_VTX_WORD1_SRF_MODE_ALL_SIZE 1 + +#define SQ_VTX_WORD1_DST_SEL_X_SHIFT 9 +#define SQ_VTX_WORD1_DST_SEL_Y_SHIFT 12 +#define SQ_VTX_WORD1_DST_SEL_Z_SHIFT 15 +#define SQ_VTX_WORD1_DST_SEL_W_SHIFT 18 +#define SQ_VTX_WORD1_USE_CONST_FIELDS_SHIFT 21 +#define SQ_VTX_WORD1_DATA_FORMAT_SHIFT 22 +#define SQ_VTX_WORD1_NUM_FORMAT_ALL_SHIFT 28 +#define SQ_VTX_WORD1_FORMAT_COMP_ALL_SHIFT 30 +#define SQ_VTX_WORD1_SRF_MODE_ALL_SHIFT 31 + +#define SQ_VTX_WORD1_DST_SEL_X_MASK 0x00000e00 +#define SQ_VTX_WORD1_DST_SEL_Y_MASK 0x00007000 +#define SQ_VTX_WORD1_DST_SEL_Z_MASK 0x00038000 +#define SQ_VTX_WORD1_DST_SEL_W_MASK 0x001c0000 +#define SQ_VTX_WORD1_USE_CONST_FIELDS_MASK 0x00200000 +#define SQ_VTX_WORD1_DATA_FORMAT_MASK 0x0fc00000 +#define SQ_VTX_WORD1_NUM_FORMAT_ALL_MASK 0x30000000 +#define SQ_VTX_WORD1_FORMAT_COMP_ALL_MASK 0x40000000 +#define SQ_VTX_WORD1_SRF_MODE_ALL_MASK 0x80000000 + +#define SQ_VTX_WORD1_MASK \ + (SQ_VTX_WORD1_DST_SEL_X_MASK | \ + SQ_VTX_WORD1_DST_SEL_Y_MASK | \ + SQ_VTX_WORD1_DST_SEL_Z_MASK | \ + SQ_VTX_WORD1_DST_SEL_W_MASK | \ + SQ_VTX_WORD1_USE_CONST_FIELDS_MASK | \ + SQ_VTX_WORD1_DATA_FORMAT_MASK | \ + SQ_VTX_WORD1_NUM_FORMAT_ALL_MASK | \ + SQ_VTX_WORD1_FORMAT_COMP_ALL_MASK | \ + SQ_VTX_WORD1_SRF_MODE_ALL_MASK) + +#define SQ_VTX_WORD1_DEFAULT 0xcdcdcc00 + +#define SQ_VTX_WORD1_GET_DST_SEL_X(sq_vtx_word1) \ + ((sq_vtx_word1 & SQ_VTX_WORD1_DST_SEL_X_MASK) >> SQ_VTX_WORD1_DST_SEL_X_SHIFT) +#define SQ_VTX_WORD1_GET_DST_SEL_Y(sq_vtx_word1) \ + ((sq_vtx_word1 & SQ_VTX_WORD1_DST_SEL_Y_MASK) >> SQ_VTX_WORD1_DST_SEL_Y_SHIFT) +#define SQ_VTX_WORD1_GET_DST_SEL_Z(sq_vtx_word1) \ + ((sq_vtx_word1 & SQ_VTX_WORD1_DST_SEL_Z_MASK) >> SQ_VTX_WORD1_DST_SEL_Z_SHIFT) +#define SQ_VTX_WORD1_GET_DST_SEL_W(sq_vtx_word1) \ + ((sq_vtx_word1 & SQ_VTX_WORD1_DST_SEL_W_MASK) >> SQ_VTX_WORD1_DST_SEL_W_SHIFT) +#define SQ_VTX_WORD1_GET_USE_CONST_FIELDS(sq_vtx_word1) \ + ((sq_vtx_word1 & SQ_VTX_WORD1_USE_CONST_FIELDS_MASK) >> SQ_VTX_WORD1_USE_CONST_FIELDS_SHIFT) +#define SQ_VTX_WORD1_GET_DATA_FORMAT(sq_vtx_word1) \ + ((sq_vtx_word1 & SQ_VTX_WORD1_DATA_FORMAT_MASK) >> SQ_VTX_WORD1_DATA_FORMAT_SHIFT) +#define SQ_VTX_WORD1_GET_NUM_FORMAT_ALL(sq_vtx_word1) \ + ((sq_vtx_word1 & SQ_VTX_WORD1_NUM_FORMAT_ALL_MASK) >> SQ_VTX_WORD1_NUM_FORMAT_ALL_SHIFT) +#define SQ_VTX_WORD1_GET_FORMAT_COMP_ALL(sq_vtx_word1) \ + ((sq_vtx_word1 & SQ_VTX_WORD1_FORMAT_COMP_ALL_MASK) >> SQ_VTX_WORD1_FORMAT_COMP_ALL_SHIFT) +#define SQ_VTX_WORD1_GET_SRF_MODE_ALL(sq_vtx_word1) \ + ((sq_vtx_word1 & SQ_VTX_WORD1_SRF_MODE_ALL_MASK) >> SQ_VTX_WORD1_SRF_MODE_ALL_SHIFT) + +#define SQ_VTX_WORD1_SET_DST_SEL_X(sq_vtx_word1_reg, dst_sel_x) \ + sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_DST_SEL_X_MASK) | (dst_sel_x << SQ_VTX_WORD1_DST_SEL_X_SHIFT) +#define SQ_VTX_WORD1_SET_DST_SEL_Y(sq_vtx_word1_reg, dst_sel_y) \ + sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_VTX_WORD1_DST_SEL_Y_SHIFT) +#define SQ_VTX_WORD1_SET_DST_SEL_Z(sq_vtx_word1_reg, dst_sel_z) \ + sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_VTX_WORD1_DST_SEL_Z_SHIFT) +#define SQ_VTX_WORD1_SET_DST_SEL_W(sq_vtx_word1_reg, dst_sel_w) \ + sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_DST_SEL_W_MASK) | (dst_sel_w << SQ_VTX_WORD1_DST_SEL_W_SHIFT) +#define SQ_VTX_WORD1_SET_USE_CONST_FIELDS(sq_vtx_word1_reg, use_const_fields) \ + sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_USE_CONST_FIELDS_MASK) | (use_const_fields << SQ_VTX_WORD1_USE_CONST_FIELDS_SHIFT) +#define SQ_VTX_WORD1_SET_DATA_FORMAT(sq_vtx_word1_reg, data_format) \ + sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_DATA_FORMAT_MASK) | (data_format << SQ_VTX_WORD1_DATA_FORMAT_SHIFT) +#define SQ_VTX_WORD1_SET_NUM_FORMAT_ALL(sq_vtx_word1_reg, num_format_all) \ + sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_NUM_FORMAT_ALL_MASK) | (num_format_all << SQ_VTX_WORD1_NUM_FORMAT_ALL_SHIFT) +#define SQ_VTX_WORD1_SET_FORMAT_COMP_ALL(sq_vtx_word1_reg, format_comp_all) \ + sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_FORMAT_COMP_ALL_MASK) | (format_comp_all << SQ_VTX_WORD1_FORMAT_COMP_ALL_SHIFT) +#define SQ_VTX_WORD1_SET_SRF_MODE_ALL(sq_vtx_word1_reg, srf_mode_all) \ + sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_SRF_MODE_ALL_MASK) | (srf_mode_all << SQ_VTX_WORD1_SRF_MODE_ALL_SHIFT) + +#if defined(LITTLEENDIAN_CPU) + + typedef struct _sq_vtx_word1_t { + unsigned int : 9; + unsigned int dst_sel_x : SQ_VTX_WORD1_DST_SEL_X_SIZE; + unsigned int dst_sel_y : SQ_VTX_WORD1_DST_SEL_Y_SIZE; + unsigned int dst_sel_z : SQ_VTX_WORD1_DST_SEL_Z_SIZE; + unsigned int dst_sel_w : SQ_VTX_WORD1_DST_SEL_W_SIZE; + unsigned int use_const_fields : SQ_VTX_WORD1_USE_CONST_FIELDS_SIZE; + unsigned int data_format : SQ_VTX_WORD1_DATA_FORMAT_SIZE; + unsigned int num_format_all : SQ_VTX_WORD1_NUM_FORMAT_ALL_SIZE; + unsigned int format_comp_all : SQ_VTX_WORD1_FORMAT_COMP_ALL_SIZE; + unsigned int srf_mode_all : SQ_VTX_WORD1_SRF_MODE_ALL_SIZE; + } sq_vtx_word1_t; + +#elif defined(BIGENDIAN_CPU) + + typedef struct _sq_vtx_word1_t { + unsigned int srf_mode_all : SQ_VTX_WORD1_SRF_MODE_ALL_SIZE; + unsigned int format_comp_all : SQ_VTX_WORD1_FORMAT_COMP_ALL_SIZE; + unsigned int num_format_all : SQ_VTX_WORD1_NUM_FORMAT_ALL_SIZE; + unsigned int data_format : SQ_VTX_WORD1_DATA_FORMAT_SIZE; + unsigned int use_const_fields : SQ_VTX_WORD1_USE_CONST_FIELDS_SIZE; + unsigned int dst_sel_w : SQ_VTX_WORD1_DST_SEL_W_SIZE; + unsigned int dst_sel_z : SQ_VTX_WORD1_DST_SEL_Z_SIZE; + unsigned int dst_sel_y : SQ_VTX_WORD1_DST_SEL_Y_SIZE; + unsigned int dst_sel_x : SQ_VTX_WORD1_DST_SEL_X_SIZE; + unsigned int : 9; + } sq_vtx_word1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vtx_word1_t f; +} sq_vtx_word1_u; + + +/* + * SQ_VTX_WORD1_GPR struct + */ + +#define SQ_VTX_WORD1_GPR_DST_GPR_SIZE 7 +#define SQ_VTX_WORD1_GPR_DST_REL_SIZE 1 + +#define SQ_VTX_WORD1_GPR_DST_GPR_SHIFT 0 +#define SQ_VTX_WORD1_GPR_DST_REL_SHIFT 7 + +#define SQ_VTX_WORD1_GPR_DST_GPR_MASK 0x0000007f +#define SQ_VTX_WORD1_GPR_DST_REL_MASK 0x00000080 + +#define SQ_VTX_WORD1_GPR_MASK \ + (SQ_VTX_WORD1_GPR_DST_GPR_MASK | \ + SQ_VTX_WORD1_GPR_DST_REL_MASK) + +#define SQ_VTX_WORD1_GPR_DEFAULT 0x000000cd + +#define SQ_VTX_WORD1_GPR_GET_DST_GPR(sq_vtx_word1_gpr) \ + ((sq_vtx_word1_gpr & SQ_VTX_WORD1_GPR_DST_GPR_MASK) >> SQ_VTX_WORD1_GPR_DST_GPR_SHIFT) +#define SQ_VTX_WORD1_GPR_GET_DST_REL(sq_vtx_word1_gpr) \ + ((sq_vtx_word1_gpr & SQ_VTX_WORD1_GPR_DST_REL_MASK) >> SQ_VTX_WORD1_GPR_DST_REL_SHIFT) + +#define SQ_VTX_WORD1_GPR_SET_DST_GPR(sq_vtx_word1_gpr_reg, dst_gpr) \ + sq_vtx_word1_gpr_reg = (sq_vtx_word1_gpr_reg & ~SQ_VTX_WORD1_GPR_DST_GPR_MASK) | (dst_gpr << SQ_VTX_WORD1_GPR_DST_GPR_SHIFT) +#define SQ_VTX_WORD1_GPR_SET_DST_REL(sq_vtx_word1_gpr_reg, dst_rel) \ + sq_vtx_word1_gpr_reg = (sq_vtx_word1_gpr_reg & ~SQ_VTX_WORD1_GPR_DST_REL_MASK) | (dst_rel << SQ_VTX_WORD1_GPR_DST_REL_SHIFT) + +#if defined(LITTLEENDIAN_CPU) + + typedef struct _sq_vtx_word1_gpr_t { + unsigned int dst_gpr : SQ_VTX_WORD1_GPR_DST_GPR_SIZE; + unsigned int dst_rel : SQ_VTX_WORD1_GPR_DST_REL_SIZE; + unsigned int : 24; + } sq_vtx_word1_gpr_t; + +#elif defined(BIGENDIAN_CPU) + + typedef struct _sq_vtx_word1_gpr_t { + unsigned int : 24; + unsigned int dst_rel : SQ_VTX_WORD1_GPR_DST_REL_SIZE; + unsigned int dst_gpr : SQ_VTX_WORD1_GPR_DST_GPR_SIZE; + } sq_vtx_word1_gpr_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vtx_word1_gpr_t f; +} sq_vtx_word1_gpr_u; + + +/* + * SQ_VTX_WORD1_SEM struct + */ + +#define SQ_VTX_WORD1_SEM_SEMANTIC_ID_SIZE 8 + +#define SQ_VTX_WORD1_SEM_SEMANTIC_ID_SHIFT 0 + +#define SQ_VTX_WORD1_SEM_SEMANTIC_ID_MASK 0x000000ff + +#define SQ_VTX_WORD1_SEM_MASK \ + (SQ_VTX_WORD1_SEM_SEMANTIC_ID_MASK) + +#define SQ_VTX_WORD1_SEM_DEFAULT 0x000000cd + +#define SQ_VTX_WORD1_SEM_GET_SEMANTIC_ID(sq_vtx_word1_sem) \ + ((sq_vtx_word1_sem & SQ_VTX_WORD1_SEM_SEMANTIC_ID_MASK) >> SQ_VTX_WORD1_SEM_SEMANTIC_ID_SHIFT) + +#define SQ_VTX_WORD1_SEM_SET_SEMANTIC_ID(sq_vtx_word1_sem_reg, semantic_id) \ + sq_vtx_word1_sem_reg = (sq_vtx_word1_sem_reg & ~SQ_VTX_WORD1_SEM_SEMANTIC_ID_MASK) | (semantic_id << SQ_VTX_WORD1_SEM_SEMANTIC_ID_SHIFT) + +#if defined(LITTLEENDIAN_CPU) + + typedef struct _sq_vtx_word1_sem_t { + unsigned int semantic_id : SQ_VTX_WORD1_SEM_SEMANTIC_ID_SIZE; + unsigned int : 24; + } sq_vtx_word1_sem_t; + +#elif defined(BIGENDIAN_CPU) + + typedef struct _sq_vtx_word1_sem_t { + unsigned int : 24; + unsigned int semantic_id : SQ_VTX_WORD1_SEM_SEMANTIC_ID_SIZE; + } sq_vtx_word1_sem_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vtx_word1_sem_t f; +} sq_vtx_word1_sem_u; + + +/* + * SQ_VTX_WORD2 struct + */ + +#define SQ_VTX_WORD2_OFFSET_SIZE 16 +#define SQ_VTX_WORD2_ENDIAN_SWAP_SIZE 2 +#define SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_SIZE 1 +#define SQ_VTX_WORD2_MEGA_FETCH_SIZE 1 +#define SQ_VTX_WORD2_ALT_CONST_SIZE 1 + +#define SQ_VTX_WORD2_OFFSET_SHIFT 0 +#define SQ_VTX_WORD2_ENDIAN_SWAP_SHIFT 16 +#define SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_SHIFT 18 +#define SQ_VTX_WORD2_MEGA_FETCH_SHIFT 19 +#define SQ_VTX_WORD2_ALT_CONST_SHIFT 20 + +#define SQ_VTX_WORD2_OFFSET_MASK 0x0000ffff +#define SQ_VTX_WORD2_ENDIAN_SWAP_MASK 0x00030000 +#define SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_MASK 0x00040000 +#define SQ_VTX_WORD2_MEGA_FETCH_MASK 0x00080000 +#define SQ_VTX_WORD2_ALT_CONST_MASK 0x00100000 + +#define SQ_VTX_WORD2_MASK \ + (SQ_VTX_WORD2_OFFSET_MASK | \ + SQ_VTX_WORD2_ENDIAN_SWAP_MASK | \ + SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_MASK | \ + SQ_VTX_WORD2_MEGA_FETCH_MASK | \ + SQ_VTX_WORD2_ALT_CONST_MASK) + +#define SQ_VTX_WORD2_DEFAULT 0x000dcdcd + +#define SQ_VTX_WORD2_GET_OFFSET(sq_vtx_word2) \ + ((sq_vtx_word2 & SQ_VTX_WORD2_OFFSET_MASK) >> SQ_VTX_WORD2_OFFSET_SHIFT) +#define SQ_VTX_WORD2_GET_ENDIAN_SWAP(sq_vtx_word2) \ + ((sq_vtx_word2 & SQ_VTX_WORD2_ENDIAN_SWAP_MASK) >> SQ_VTX_WORD2_ENDIAN_SWAP_SHIFT) +#define SQ_VTX_WORD2_GET_CONST_BUF_NO_STRIDE(sq_vtx_word2) \ + ((sq_vtx_word2 & SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_MASK) >> SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_SHIFT) +#define SQ_VTX_WORD2_GET_MEGA_FETCH(sq_vtx_word2) \ + ((sq_vtx_word2 & SQ_VTX_WORD2_MEGA_FETCH_MASK) >> SQ_VTX_WORD2_MEGA_FETCH_SHIFT) +#define SQ_VTX_WORD2_GET_ALT_CONST(sq_vtx_word2) \ + ((sq_vtx_word2 & SQ_VTX_WORD2_ALT_CONST_MASK) >> SQ_VTX_WORD2_ALT_CONST_SHIFT) + +#define SQ_VTX_WORD2_SET_OFFSET(sq_vtx_word2_reg, offset) \ + sq_vtx_word2_reg = (sq_vtx_word2_reg & ~SQ_VTX_WORD2_OFFSET_MASK) | (offset << SQ_VTX_WORD2_OFFSET_SHIFT) +#define SQ_VTX_WORD2_SET_ENDIAN_SWAP(sq_vtx_word2_reg, endian_swap) \ + sq_vtx_word2_reg = (sq_vtx_word2_reg & ~SQ_VTX_WORD2_ENDIAN_SWAP_MASK) | (endian_swap << SQ_VTX_WORD2_ENDIAN_SWAP_SHIFT) +#define SQ_VTX_WORD2_SET_CONST_BUF_NO_STRIDE(sq_vtx_word2_reg, const_buf_no_stride) \ + sq_vtx_word2_reg = (sq_vtx_word2_reg & ~SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_MASK) | (const_buf_no_stride << SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_SHIFT) +#define SQ_VTX_WORD2_SET_MEGA_FETCH(sq_vtx_word2_reg, mega_fetch) \ + sq_vtx_word2_reg = (sq_vtx_word2_reg & ~SQ_VTX_WORD2_MEGA_FETCH_MASK) | (mega_fetch << SQ_VTX_WORD2_MEGA_FETCH_SHIFT) +#define SQ_VTX_WORD2_SET_ALT_CONST(sq_vtx_word2_reg, alt_const) \ + sq_vtx_word2_reg = (sq_vtx_word2_reg & ~SQ_VTX_WORD2_ALT_CONST_MASK) | (alt_const << SQ_VTX_WORD2_ALT_CONST_SHIFT) + +#if defined(LITTLEENDIAN_CPU) + + typedef struct _sq_vtx_word2_t { + unsigned int offset : SQ_VTX_WORD2_OFFSET_SIZE; + unsigned int endian_swap : SQ_VTX_WORD2_ENDIAN_SWAP_SIZE; + unsigned int const_buf_no_stride : SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_SIZE; + unsigned int mega_fetch : SQ_VTX_WORD2_MEGA_FETCH_SIZE; + unsigned int alt_const : SQ_VTX_WORD2_ALT_CONST_SIZE; + unsigned int : 11; + } sq_vtx_word2_t; + +#elif defined(BIGENDIAN_CPU) + + typedef struct _sq_vtx_word2_t { + unsigned int : 11; + unsigned int alt_const : SQ_VTX_WORD2_ALT_CONST_SIZE; + unsigned int mega_fetch : SQ_VTX_WORD2_MEGA_FETCH_SIZE; + unsigned int const_buf_no_stride : SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_SIZE; + unsigned int endian_swap : SQ_VTX_WORD2_ENDIAN_SWAP_SIZE; + unsigned int offset : SQ_VTX_WORD2_OFFSET_SIZE; + } sq_vtx_word2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vtx_word2_t f; +} sq_vtx_word2_u; + +#endif /* _SQ_MICRO_REG_H */ + + diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index df0128c378..b75db5b80c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -61,8 +61,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_tex.h" #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) #include "r600_context.h" -#include "r600_fragprog.h" -#include "r600_tex.h" +#include "r700_fragprog.h" +#include "r700_tex.h" #endif #include "utils.h" @@ -405,13 +405,13 @@ static const __DRItexBufferExtension r300TexBufferExtension = { #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) static const __DRItexOffsetExtension r600texOffsetExtension = { { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, - r600SetTexOffset, + r700SetTexOffset, }; static const __DRItexBufferExtension r600TexBufferExtension = { { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, - r600SetTexBuffer, - r600SetTexBuffer2, + r700SetTexBuffer, + r700SetTexBuffer2, }; #endif -- cgit v1.2.3 From e2dcebd2e6b2af6269a5ece6d6ced73ec8bb4a47 Mon Sep 17 00:00:00 2001 From: Richard Li Date: Fri, 8 May 2009 19:23:45 -0400 Subject: R6xx/R7xx: WIP r6xx-rewrite code --- src/mesa/drivers/dri/r600/Makefile | 3 + src/mesa/drivers/dri/r600/r600_cmdbuf.c | 589 ++++++++++++++++++++++++- src/mesa/drivers/dri/r600/r600_cmdbuf.h | 167 +++++++ src/mesa/drivers/dri/r600/r600_context.c | 69 +-- src/mesa/drivers/dri/r600/r600_context.h | 39 +- src/mesa/drivers/dri/r600/r600_emit.c | 224 +++++++++- src/mesa/drivers/dri/r600/r600_emit.h | 257 ++--------- src/mesa/drivers/dri/r600/r700_chip.c | 248 ++++++++++- src/mesa/drivers/dri/r600/r700_chip.h | 11 +- src/mesa/drivers/dri/r600/r700_clear.c | 117 +++-- src/mesa/drivers/dri/r600/r700_fragprog.c | 50 ++- src/mesa/drivers/dri/r600/r700_fragprog.h | 8 +- src/mesa/drivers/dri/r600/r700_ioctl.c | 28 +- src/mesa/drivers/dri/r600/r700_oglprog.c | 26 +- src/mesa/drivers/dri/r600/r700_render.c | 217 ++++----- src/mesa/drivers/dri/r600/r700_state.c | 265 ++++++----- src/mesa/drivers/dri/r600/r700_state.h | 1 + src/mesa/drivers/dri/r600/r700_tex.c | 24 +- src/mesa/drivers/dri/r600/r700_tex.h | 2 + src/mesa/drivers/dri/r600/r700_vertprog.c | 80 +--- src/mesa/drivers/dri/r600/r700_vertprog.h | 10 +- src/mesa/drivers/dri/radeon/radeon_cmdbuf.h | 124 +----- src/mesa/drivers/dri/radeon/radeon_common.c | 4 +- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 138 +++--- src/mesa/drivers/dri/radeon/radeon_fbo.c | 4 +- src/mesa/drivers/dri/radeon/radeon_screen.c | 11 +- 26 files changed, 1788 insertions(+), 928 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/Makefile b/src/mesa/drivers/dri/r600/Makefile index 00c56c03cd..474a3167b4 100644 --- a/src/mesa/drivers/dri/r600/Makefile +++ b/src/mesa/drivers/dri/r600/Makefile @@ -48,9 +48,12 @@ DRIVER_SOURCES = \ r700_fragprog.c \ r700_vertprog.c \ r700_shader.c \ + r700_shaderinst.c \ r700_ioctl.c \ r700_oglprog.c \ r700_chip.c \ + r700_state.c \ + r700_clear.c \ r700_render.c \ r700_tex.c \ r700_debug.c \ diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index bc14f9a755..8550457566 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -28,11 +28,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. **************************************************************************/ /** - * \file - * - * \author Nicolai Haehnle + * Mostly coppied from \radeon\radeon_cs_legacy.c */ +#include + #include "main/glheader.h" #include "main/state.h" #include "main/imports.h" @@ -52,11 +52,582 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_mipmap_tree.h" #include "radeon_reg.h" -/** - * Allocate memory for the command buffer and initialize the state atom - * list. Note that the initial hardware state is set by r600InitState(). - */ -void r600InitCmdBuf(r600ContextPtr r600) +struct r600_cs_manager_legacy { - rcommonInitCmdBuf(&r600->radeon); + struct radeon_cs_manager base; + struct radeon_context *ctx; + /* hack for scratch stuff */ + uint32_t pending_age; + uint32_t pending_count; +}; + +struct r600_cs_reloc_legacy { + struct radeon_cs_reloc base; + uint32_t cindices; + uint32_t *indices; + uint32_t *reloc_indices; + struct offset_modifiers offset_mod; +}; + +static struct radeon_cs * r600_cs_create(struct radeon_cs_manager *csm, + uint32_t ndw) +{ + struct radeon_cs *cs; + + cs = (struct radeon_cs*)calloc(1, sizeof(struct radeon_cs)); + if (cs == NULL) { + return NULL; + } + cs->csm = csm; + cs->ndw = (ndw + 0x3FF) & (~0x3FF); + cs->packets = (uint32_t*)malloc(4*cs->ndw); + if (cs->packets == NULL) { + free(cs); + return NULL; + } + cs->relocs_total_size = 0; + return cs; +} + +int r600_cs_write_reloc(struct radeon_cs *cs, + struct radeon_bo *bo, + uint32_t read_domain, + uint32_t write_domain, + uint32_t flags, + offset_modifiers* poffset_mod) +{ + struct r600_cs_reloc_legacy *relocs; + int i; + + relocs = (struct r600_cs_reloc_legacy *)cs->relocs; + /* check domains */ + if ((read_domain && write_domain) || (!read_domain && !write_domain)) { + /* in one CS a bo can only be in read or write domain but not + * in read & write domain at the same sime + */ + return -EINVAL; + } + if (read_domain == RADEON_GEM_DOMAIN_CPU) { + return -EINVAL; + } + if (write_domain == RADEON_GEM_DOMAIN_CPU) { + return -EINVAL; + } + /* check if bo is already referenced */ + for(i = 0; i < cs->crelocs; i++) { + uint32_t *indices; + uint32_t *reloc_indices; + + if (relocs[i].base.bo->handle == bo->handle) { + /* Check domains must be in read or write. As we check already + * checked that in argument one of the read or write domain was + * set we only need to check that if previous reloc as the read + * domain set then the read_domain should also be set for this + * new relocation. + */ + if (relocs[i].base.read_domain && !read_domain) { + return -EINVAL; + } + if (relocs[i].base.write_domain && !write_domain) { + return -EINVAL; + } + relocs[i].base.read_domain |= read_domain; + relocs[i].base.write_domain |= write_domain; + /* save indice */ + relocs[i].cindices++; + indices = (uint32_t*)realloc(relocs[i].indices, + relocs[i].cindices * 4); + reloc_indices = (uint32_t*)realloc(relocs[i].reloc_indices, + relocs[i].cindices * 4); + if ( (indices == NULL) || (reloc_indices == NULL) ) { + relocs[i].cindices -= 1; + return -ENOMEM; + } + relocs[i].indices = indices; + relocs[i].reloc_indices = reloc_indices; + relocs[i].indices[relocs[i].cindices - 1] = cs->cdw - 1; + relocs[i].reloc_indices[relocs[i].cindices - 1] = cs->section_cdw; + cs->section_ndw += 2; + cs->section_cdw += 2; + + relocs[i].offset_mod.shift = poffset_mod->shift; + relocs[i].offset_mod.shiftbits = poffset_mod->shiftbits; + relocs[i].offset_mod.mask = poffset_mod->mask; + + return 0; + } + } + /* add bo to reloc */ + relocs = (struct r600_cs_reloc_legacy*) + realloc(cs->relocs, + sizeof(struct r600_cs_reloc_legacy) * (cs->crelocs + 1)); + if (relocs == NULL) { + return -ENOMEM; + } + cs->relocs = relocs; + relocs[cs->crelocs].base.bo = bo; + relocs[cs->crelocs].base.read_domain = read_domain; + relocs[cs->crelocs].base.write_domain = write_domain; + relocs[cs->crelocs].base.flags = flags; + relocs[cs->crelocs].indices = (uint32_t*)malloc(4); + relocs[cs->crelocs].reloc_indices = (uint32_t*)malloc(4); + if ( (relocs[cs->crelocs].indices == NULL) || (relocs[cs->crelocs].reloc_indices == NULL) ) + { + return -ENOMEM; + } + relocs[cs->crelocs].offset_mod.shift = poffset_mod->shift; + relocs[cs->crelocs].offset_mod.shiftbits = poffset_mod->shiftbits; + relocs[cs->crelocs].offset_mod.mask = poffset_mod->mask; + + relocs[cs->crelocs].indices[0] = cs->cdw - 1; + relocs[cs->crelocs].reloc_indices[0] = cs->section_cdw; + cs->section_ndw += 2; + cs->section_cdw += 2; + relocs[cs->crelocs].cindices = 1; + cs->relocs_total_size += radeon_bo_legacy_relocs_size(bo); + cs->crelocs++; + + radeon_bo_ref(bo); + return 0; +} + +static int r600_cs_begin(struct radeon_cs *cs, + uint32_t ndw, + const char *file, + const char *func, + int line) +{ + if (cs->section) { + fprintf(stderr, "CS already in a section(%s,%s,%d)\n", + cs->section_file, cs->section_func, cs->section_line); + fprintf(stderr, "CS can't start section(%s,%s,%d)\n", + file, func, line); + return -EPIPE; + } + + if (cs->cdw + ndw + 32 > cs->ndw) { /* Left 32 DWORD (8 offset+pitch) spare room for reloc indices */ + uint32_t tmp, *ptr; + int num = (ndw > 0x3FF) ? ndw : 0x3FF; + + tmp = (cs->cdw + 1 + num) & (~num); + ptr = (uint32_t*)realloc(cs->packets, 4 * tmp); + if (ptr == NULL) { + return -ENOMEM; + } + cs->packets = ptr; + cs->ndw = tmp; + } + + cs->section = 1; + cs->section_ndw = 0; + cs->section_cdw = cs->cdw + ndw; /* start of reloc indices. */ + cs->section_file = file; + cs->section_func = func; + cs->section_line = line; + + return 0; +} + +static int r600_cs_end(struct radeon_cs *cs, + const char *file, + const char *func, + int line) + +{ + if (!cs->section) { + fprintf(stderr, "CS no section to end at (%s,%s,%d)\n", + file, func, line); + return -EPIPE; + } + cs->section = 0; + + if ( (cs->section_ndw + cs->cdw) != cs->section_cdw ) + { + fprintf(stderr, "CS section size missmatch start at (%s,%s,%d) %d vs %d\n", + cs->section_file, cs->section_func, cs->section_line, cs->section_ndw, cs->section_cdw); + fprintf(stderr, "CS section end at (%s,%s,%d)\n", + file, func, line); + return -EPIPE; + } + + cs->cdw = cs->section_cdw; + return 0; +} + +static int r600_cs_process_relocs(struct radeon_cs *cs, + uint32_t * reloc_chunk, + uint32_t * length_dw_reloc_chunk) +{ + struct r600_cs_manager_legacy *csm = (struct r600_cs_manager_legacy*)cs->csm; + struct r600_cs_reloc_legacy *relocs; + int i, j, r; + + uint32_t offset_dw = 0; + + csm = (struct r600_cs_manager_legacy*)cs->csm; + relocs = (struct r600_cs_reloc_legacy *)cs->relocs; +restart: + for (i = 0; i < cs->crelocs; i++) + { + for (j = 0; j < relocs[i].cindices; j++) + { + uint32_t soffset, eoffset, asicoffset; + + r = radeon_bo_legacy_validate(relocs[i].base.bo, + &soffset, &eoffset); + if (r == -EAGAIN) + { + goto restart; + } + if (r) + { + fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", + relocs[i].base.bo, soffset, eoffset); + return r; + } + asicoffset = cs->packets[relocs[i].indices[j]] + soffset; + if (asicoffset >= eoffset) + { + /* radeon_bo_debug(relocs[i].base.bo, 12); */ + fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", + relocs[i].base.bo, soffset, eoffset); + fprintf(stderr, "above end: %p 0x%08X 0x%08X\n", + relocs[i].base.bo, + cs->packets[relocs[i].indices[j]], + eoffset); + exit(0); + return -EINVAL; + } + /* apply offset operator */ + switch (relocs[i].offset_mod.shift) + { + case NO_SHIFT: + asicoffset = asicoffset & relocs[i].offset_mod.mask; + break; + case LEFT_SHIFT: + asicoffset = (asicoffset << relocs[i].offset_mod.shiftbits) & relocs[i].offset_mod.mask; + break; + case RIGHT_SHIFT: + asicoffset = (asicoffset >> relocs[i].offset_mod.shiftbits) & relocs[i].offset_mod.mask; + break; + default: + break; + }; + + /* pkt3 nop header in ib chunk */ + cs->packets[relocs[i].reloc_indices[j]] = 0xC0001000; + + /* reloc index in ib chunk */ + cs->packets[relocs[i].reloc_indices[j] + 1] = offset_dw; + + /* asic offset in reloc chunk */ /* see alex drm r600_nomm_relocate */ + reloc_chunk[offset_dw] = asicoffset; + reloc_chunk[offset_dw + 3] = 0; + + offset_dw += 4; + } + } + + *length_dw_reloc_chunk = offset_dw; + + return 0; +} + +static int r600_cs_set_age(struct radeon_cs *cs) /* -------------- */ +{ + struct r600_cs_manager_legacy *csm = (struct r600_cs_manager_legacy*)cs->csm; + struct r600_cs_reloc_legacy *relocs; + int i; + + relocs = (struct r600_cs_reloc_legacy *)cs->relocs; + for (i = 0; i < cs->crelocs; i++) { + radeon_bo_legacy_pending(relocs[i].base.bo, csm->pending_age); + radeon_bo_unref(relocs[i].base.bo); + } + return 0; +} + +static int r600_cs_emit(struct radeon_cs *cs) +{ + struct r600_cs_manager_legacy *csm = (struct r600_cs_manager_legacy*)cs->csm; + struct drm_radeon_cs cs_cmd; + struct drm_radeon_cs_chunk cs_chunk[2]; + drm_radeon_cmd_buffer_t cmd; + /* drm_r300_cmd_header_t age; */ + uint32_t length_dw_reloc_chunk; + uint64_t ull; + uint64_t * chunk_ptrs[2]; + uint32_t reloc_chunk[128]; + int r; + int retry = 0; + + /* TODO : put chip level things here if need. */ + /* csm->ctx->vtbl.emit_cs_header(cs, csm->ctx); */ + + /* TODO : append buffer age */ + + r = r600_cs_process_relocs(cs, &(reloc_chunk[0]), &length_dw_reloc_chunk); + if (r) { + return 0; + } + + /* raw ib chunk */ + cs_chunk[0].chunk_id = RADEON_CHUNK_ID_IB; + cs_chunk[0].length_dw = cs->cdw; + cs_chunk[0].chunk_data = (uint64_t)(cs->packets); + + /* reloc chaunk */ + cs_chunk[1].chunk_id = RADEON_CHUNK_ID_RELOCS; + cs_chunk[1].length_dw = length_dw_reloc_chunk; + cs_chunk[1].chunk_data = (uint64_t)&(reloc_chunk[0]); + + chunk_ptrs[0] = (uint64_t * )&(cs_chunk[0]); + chunk_ptrs[1] = (uint64_t * )&(cs_chunk[1]); + + cs_cmd.num_chunks = 2; + cs_cmd.cs_id = 0; + cs_cmd.chunks = (uint64_t)&(chunk_ptrs[0]); + + /* dump_cmdbuf(cs); */ + + do + { + r = drmCommandWriteRead(cs->csm->fd, DRM_RADEON_CS, &cs_cmd, sizeof(cs_cmd)); + retry++; + } while (r == -EAGAIN && retry < 1000); + + if (r) { + return r; + } + + r600_cs_set_age(cs); + + cs->csm->read_used = 0; + cs->csm->vram_write_used = 0; + cs->csm->gart_write_used = 0; + + return 0; +} + +static void inline r600_cs_free_reloc(void *relocs_p, int crelocs) +{ + struct r600_cs_reloc_legacy *relocs = relocs_p; + int i; + if (!relocs_p) + return; + for (i = 0; i < crelocs; i++) + { + free(relocs[i].indices); + free(relocs[i].reloc_indices); + } +} + +static int r600_cs_destroy(struct radeon_cs *cs) +{ + r600_cs_free_reloc(cs->relocs, cs->crelocs); + free(cs->relocs); + free(cs->packets); + free(cs); + return 0; +} + +static int r600_cs_erase(struct radeon_cs *cs) +{ + r600_cs_free_reloc(cs->relocs, cs->crelocs); + free(cs->relocs); + cs->relocs_total_size = 0; + cs->relocs = NULL; + cs->crelocs = 0; + cs->cdw = 0; + cs->section = 0; + return 0; +} + +static int r600_cs_need_flush(struct radeon_cs *cs) +{ + /* this function used to flush when the BO usage got to + * a certain size, now the higher levels handle this better */ + return 0; +} + +static void r600_cs_print(struct radeon_cs *cs, FILE *file) +{ +} + +static int r600_cs_check_space(struct radeon_cs *cs, struct radeon_cs_space_check *bos, int num_bo) +{ + struct radeon_cs_manager *csm = cs->csm; + int this_op_read = 0, this_op_gart_write = 0, this_op_vram_write = 0; + uint32_t read_domains, write_domain; + int i; + struct radeon_bo *bo; + + /* check the totals for this operation */ + + if (num_bo == 0) + return 0; + + /* prepare */ + for (i = 0; i < num_bo; i++) + { + bo = bos[i].bo; + + bos[i].new_accounted = 0; + read_domains = bos[i].read_domains; + write_domain = bos[i].write_domain; + + /* pinned bos don't count */ + if (radeon_legacy_bo_is_static(bo)) + continue; + + /* already accounted this bo */ + if (write_domain && (write_domain == bo->space_accounted)) + continue; + + if (read_domains && ((read_domains << 16) == bo->space_accounted)) + continue; + + if (bo->space_accounted == 0) + { + if (write_domain == RADEON_GEM_DOMAIN_VRAM) + this_op_vram_write += bo->size; + else if (write_domain == RADEON_GEM_DOMAIN_GTT) + this_op_gart_write += bo->size; + else + this_op_read += bo->size; + bos[i].new_accounted = (read_domains << 16) | write_domain; + } + else + { + uint16_t old_read, old_write; + + old_read = bo->space_accounted >> 16; + old_write = bo->space_accounted & 0xffff; + + if (write_domain && (old_read & write_domain)) + { + bos[i].new_accounted = write_domain; + /* moving from read to a write domain */ + if (write_domain == RADEON_GEM_DOMAIN_VRAM) + { + this_op_read -= bo->size; + this_op_vram_write += bo->size; + } + else if (write_domain == RADEON_GEM_DOMAIN_VRAM) + { + this_op_read -= bo->size; + this_op_gart_write += bo->size; + } + } + else if (read_domains & old_write) + { + bos[i].new_accounted = bo->space_accounted & 0xffff; + } + else + { + /* rewrite the domains */ + if (write_domain != old_write) + fprintf(stderr,"WRITE DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, write_domain, old_write); + if (read_domains != old_read) + fprintf(stderr,"READ DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, read_domains, old_read); + return RADEON_CS_SPACE_FLUSH; + } + } + } + + if (this_op_read < 0) + this_op_read = 0; + + /* check sizes - operation first */ + if ((this_op_read + this_op_gart_write > csm->gart_limit) || + (this_op_vram_write > csm->vram_limit)) { + return RADEON_CS_SPACE_OP_TO_BIG; + } + + if (((csm->vram_write_used + this_op_vram_write) > csm->vram_limit) || + ((csm->read_used + csm->gart_write_used + this_op_gart_write + this_op_read) > csm->gart_limit)) { + return RADEON_CS_SPACE_FLUSH; + } + + csm->gart_write_used += this_op_gart_write; + csm->vram_write_used += this_op_vram_write; + csm->read_used += this_op_read; + /* commit */ + for (i = 0; i < num_bo; i++) { + bo = bos[i].bo; + bo->space_accounted = bos[i].new_accounted; + } + + return RADEON_CS_SPACE_OK; +} + +static struct radeon_cs_funcs r600_cs_funcs = { + r600_cs_create, + r600_cs_write_reloc, + r600_cs_begin, + r600_cs_end, + r600_cs_emit, + r600_cs_destroy, + r600_cs_erase, + r600_cs_need_flush, + r600_cs_print, + r600_cs_check_space +}; + +struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_context *ctx) +{ + struct r600_cs_manager_legacy *csm; + + csm = (struct r600_cs_manager_legacy*) + calloc(1, sizeof(struct r600_cs_manager_legacy)); + if (csm == NULL) { + return NULL; + } + csm->base.funcs = &r600_cs_funcs; + csm->base.fd = ctx->dri.fd; + csm->ctx = ctx; + csm->pending_age = 1; + return (struct radeon_cs_manager*)csm; +} + +void r600InitCmdBuf(r600ContextPtr r600) /* from rcommonInitCmdBuf */ +{ + radeonContextPtr rmesa = &r600->radeon; + + GLuint size; + /* Initialize command buffer */ + size = 256 * driQueryOptioni(&rmesa->optionCache, + "command_buffer_size"); + if (size < 2 * rmesa->hw.max_state_size) { + size = 2 * rmesa->hw.max_state_size + 65535; + } + if (size > 64 * 256) + size = 64 * 256; + + if (rmesa->radeonScreen->kernel_mm) { + int fd = rmesa->radeonScreen->driScreen->fd; + rmesa->cmdbuf.csm = radeon_cs_manager_gem_ctor(fd); + } else { + rmesa->cmdbuf.csm = r600_radeon_cs_manager_legacy_ctor(rmesa); + } + if (rmesa->cmdbuf.csm == NULL) { + /* FIXME: fatal error */ + return; + } + rmesa->cmdbuf.cs = radeon_cs_create(rmesa->cmdbuf.csm, size); + assert(rmesa->cmdbuf.cs != NULL); + rmesa->cmdbuf.size = size; + + if (!rmesa->radeonScreen->kernel_mm) { + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]); + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, rmesa->radeonScreen->gartTextures.size); + } else { + struct drm_radeon_gem_info mminfo; + + if (!drmCommandWriteRead(rmesa->dri.fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo))) + { + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, mminfo.vram_visible); + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, mminfo.gart_size); + } + } } diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.h b/src/mesa/drivers/dri/r600/r600_cmdbuf.h index 1bab9c5821..dbb723b2b5 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.h +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.h @@ -37,6 +37,173 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define __R600_CMDBUF_H__ #include "r600_context.h" +#include "r600_emit.h" + +#define RADEON_CP_PACKET3_NOP 0xC0001000 +#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900 +#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 +#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00 +#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 +#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400 +#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 +#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800 +#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 +#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 +#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 +#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 +#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 +#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 +#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 +#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 +#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500 +#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 +#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 +#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 +#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 + +/* r6xx/r7xx packet 3 type offsets */ +#define R600_SET_CONFIG_REG_OFFSET 0x00008000 +#define R600_SET_CONFIG_REG_END 0x0000ac00 +#define R600_SET_CONTEXT_REG_OFFSET 0x00028000 +#define R600_SET_CONTEXT_REG_END 0x00029000 +#define R600_SET_ALU_CONST_OFFSET 0x00030000 +#define R600_SET_ALU_CONST_END 0x00032000 +#define R600_SET_RESOURCE_OFFSET 0x00038000 +#define R600_SET_RESOURCE_END 0x0003c000 +#define R600_SET_SAMPLER_OFFSET 0x0003c000 +#define R600_SET_SAMPLER_END 0x0003cff0 +#define R600_SET_CTL_CONST_OFFSET 0x0003cff0 +#define R600_SET_CTL_CONST_END 0x0003e200 +#define R600_SET_LOOP_CONST_OFFSET 0x0003e200 +#define R600_SET_LOOP_CONST_END 0x0003e380 +#define R600_SET_BOOL_CONST_OFFSET 0x0003e380 +#define R600_SET_BOOL_CONST_END 0x00040000 + +/* r6xx/r7xx packet 3 types */ +#define R600_IT_INDIRECT_BUFFER_END 0x00001700 +#define R600_IT_SET_PREDICATION 0x00002000 +#define R600_IT_REG_RMW 0x00002100 +#define R600_IT_COND_EXEC 0x00002200 +#define R600_IT_PRED_EXEC 0x00002300 +#define R600_IT_START_3D_CMDBUF 0x00002400 +#define R600_IT_DRAW_INDEX_2 0x00002700 +#define R600_IT_CONTEXT_CONTROL 0x00002800 +#define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900 +#define R600_IT_INDEX_TYPE 0x00002A00 +#define R600_IT_DRAW_INDEX 0x00002B00 +#define R600_IT_DRAW_INDEX_AUTO 0x00002D00 +#define R600_IT_DRAW_INDEX_IMMD 0x00002E00 +#define R600_IT_NUM_INSTANCES 0x00002F00 +#define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400 +#define R600_IT_INDIRECT_BUFFER_MP 0x00003800 +#define R600_IT_MEM_SEMAPHORE 0x00003900 +#define R600_IT_MPEG_INDEX 0x00003A00 +#define R600_IT_WAIT_REG_MEM 0x00003C00 +#define R600_IT_MEM_WRITE 0x00003D00 +#define R600_IT_INDIRECT_BUFFER 0x00003200 +#define R600_IT_CP_INTERRUPT 0x00004000 +#define R600_IT_SURFACE_SYNC 0x00004300 +#define R600_IT_ME_INITIALIZE 0x00004400 +#define R600_IT_COND_WRITE 0x00004500 +#define R600_IT_EVENT_WRITE 0x00004600 +#define R600_IT_EVENT_WRITE_EOP 0x00004700 +#define R600_IT_ONE_REG_WRITE 0x00005700 +#define R600_IT_SET_CONFIG_REG 0x00006800 +#define R600_IT_SET_CONTEXT_REG 0x00006900 +#define R600_IT_SET_ALU_CONST 0x00006A00 +#define R600_IT_SET_BOOL_CONST 0x00006B00 +#define R600_IT_SET_LOOP_CONST 0x00006C00 +#define R600_IT_SET_RESOURCE 0x00006D00 +#define R600_IT_SET_SAMPLER 0x00006E00 +#define R600_IT_SET_CTL_CONST 0x00006F00 +#define R600_IT_SURFACE_BASE_UPDATE 0x00007300 + +extern int r600_cs_write_reloc(struct radeon_cs *cs, + struct radeon_bo *bo, + uint32_t read_domain, + uint32_t write_domain, + uint32_t flags, + offset_modifiers* poffset_mod); + +static inline void r600_cs_write_dword(struct radeon_cs *cs, uint32_t dword) +{ + cs->packets[cs->cdw++] = dword; +} + +/** + * Write one dword to the command buffer. + */ +#define R600_OUT_BATCH(data) \ + do { \ + r600_cs_write_dword(b_l_rmesa->cmdbuf.cs, data);\ + } while(0) + +/** + * Write n dwords from ptr to the command buffer. + */ +#define R600_OUT_BATCH_TABLE(ptr,n) \ + do { \ + int _i; \ + for (_i=0; _i < n; _i++) {\ + r600_cs_write_dword(b_l_rmesa->cmdbuf.cs, ptr[_i]);\ + }\ + } while(0) + +/** + * Write a relocated dword to the command buffer. + */ +#define R600_OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags, offset_mod) \ + do { \ + if (0 && offset) { \ + fprintf(stderr, "(%s:%s:%d) offset : %d\n", \ + __FILE__, __FUNCTION__, __LINE__, offset); \ + } \ + r600_cs_write_dword(b_l_rmesa->cmdbuf.cs, offset); \ + r600_cs_write_reloc(b_l_rmesa->cmdbuf.cs, \ + bo, rd, wd, flags, offset_mod); \ + } while(0) + +/* R600/R700 */ +#define R600_OUT_BATCH_REGS(reg, num) \ +do { \ + if ((reg) >= R600_SET_CONFIG_REG_OFFSET && (reg) < R600_SET_CONFIG_REG_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, (num))); \ + OUT_BATCH(((reg) - R600_SET_CONFIG_REG_OFFSET) >> 2); \ + } else if ((reg) >= R600_SET_CONTEXT_REG_OFFSET && (reg) < R600_SET_CONTEXT_REG_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_CONTEXT_REG, (num))); \ + OUT_BATCH(((reg) - R600_SET_CONTEXT_REG_OFFSET) >> 2); \ + } else if ((reg) >= R600_SET_ALU_CONST_OFFSET && (reg) < R600_SET_ALU_CONST_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (num))); \ + OUT_BATCH(((reg) - R600_SET_ALU_CONST_OFFSET) >> 2); \ + } else if ((reg) >= R600_SET_RESOURCE_OFFSET && (reg) < R600_SET_RESOURCE_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, (num))); \ + OUT_BATCH(((reg) - R600_SET_RESOURCE_OFFSET) >> 2); \ + } else if ((reg) >= R600_SET_SAMPLER_OFFSET && (reg) < R600_SET_SAMPLER_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, (num))); \ + OUT_BATCH(((reg) - R600_SET_SAMPLER_OFFSET) >> 2); \ + } else if ((reg) >= R600_SET_CTL_CONST_OFFSET && (reg) < R600_SET_CTL_CONST_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, (num))); \ + OUT_BATCH(((reg) - R600_SET_CTL_CONST_OFFSET) >> 2); \ + } else if ((reg) >= R600_SET_LOOP_CONST_OFFSET && (reg) < R600_SET_LOOP_CONST_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_LOOP_CONST, (num))); \ + OUT_BATCH(((reg) - R600_SET_LOOP_CONST_OFFSET) >> 2); \ + } else if ((reg) >= R600_SET_BOOL_CONST_OFFSET && (reg) < R600_SET_BOOL_CONST_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_BOOL_CONST, (num))); \ + OUT_BATCH(((reg) - R600_SET_BOOL_CONST_OFFSET) >> 2); \ + } else { \ + OUT_BATCH(CP_PACKET0((reg), (num))); \ + } \ +} while (0) + +/** Single register write to command buffer; requires 3 dwords for most things. */ +#define R600_OUT_BATCH_REGVAL(reg, val) \ + R600_OUT_BATCH_REGS((reg), 1); \ + OUT_BATCH((val)) + +/** Continuous register range write to command buffer; requires 1 dword, + * expects count dwords afterwards for register contents. */ +#define R600_OUT_BATCH_REGSEQ(reg, count) \ + R600_OUT_BATCH_REGS((reg), (count)) extern void r600InitCmdBuf(r600ContextPtr r600); diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 1b43f68ac2..3c8ba003d4 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -156,42 +156,6 @@ const struct dri_extension gl_20_extension[] = { }; -extern struct tnl_pipeline_stage _r600_render_stage; -extern const struct tnl_pipeline_stage _r600_tcl_stage; - -static const struct tnl_pipeline_stage *r600_pipeline[] = { - - /* Try and go straight to t&l - */ - &_r600_tcl_stage, - - /* Catch any t&l fallbacks - */ - &_tnl_vertex_transform_stage, - &_tnl_normal_transform_stage, - &_tnl_lighting_stage, - &_tnl_fog_coordinate_stage, - &_tnl_texgen_stage, - &_tnl_texture_transform_stage, - &_tnl_vertex_program_stage, - - /* Try again to go to tcl? - * - no good for asymmetric-twoside (do with multipass) - * - no good for asymmetric-unfilled (do with multipass) - * - good for material - * - good for texgen - * - need to manipulate a bit of state - * - * - worth it/not worth it? - */ - - /* Else do them here. - */ - &_r600_render_stage, - &_tnl_render_stage, /* FALLBACK */ - 0, -}; - static void r600RunPipeline(GLcontext * ctx) { _mesa_lock_context_textures(ctx); @@ -244,31 +208,6 @@ static void r600_init_vtbl(radeonContextPtr radeon) radeon->vtbl.fallback = r600_fallback; } -/* to be enabled */ -static void r600EmitShader(GLcontext * ctx, - struct r600_dma_region *rvb, - GLvoid * data, - int sizeinDWORD) -{ -} -/* to be enabled */ -static void r600FreeDmaRegion(context_t *context, - struct r600_dma_region *region) -{ -} -/* to be enabled */ -static void r600EmitVec(GLcontext * ctx, - struct r600_dma_region *rvb, - GLvoid * data, - int size, - int stride, - int count) -{ -} -/* to be enabled */ -static void r600ReleaseArrays(GLcontext * ctx) -{ -} /* to be enabled */ static GLboolean r600LoadMemSurf(context_t *context, GLuint dst_offset, /* gpu addr */ @@ -287,6 +226,7 @@ static GLboolean r600AllocMemSurf(context_t *context, GLuint *prefered_heap, /* Now used RADEON_LOCAL_TEX_HEAP, return actual heap used. */ GLuint totalSize) { + return GL_TRUE; } /* to be enabled */ static int r600FlushCmdBuffer(context_t *context) @@ -332,6 +272,7 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, */ driParseConfigFiles(&r600->radeon.optionCache, &screen->optionCache, screen->driScreen->myNum, "r600"); + r600->radeon.initialMaxAnisotropy = driQueryOptionf(&r600->radeon.optionCache, "def_max_anisotropy"); @@ -344,9 +285,10 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, (r600->chipobj.InitFuncs)(&functions); r600->chipobj.EmitShader = r600EmitShader; + r600->chipobj.DeleteShader = r600DeleteShader; r600->chipobj.FreeDmaRegion = r600FreeDmaRegion; r600->chipobj.EmitVec = r600EmitVec; - r600->chipobj.ReleaseArrays = r600ReleaseArrays; + r600->chipobj.ReleaseArrays = r600ReleaseVec; r600->chipobj.LoadMemSurf = r600LoadMemSurf; r600->chipobj.AllocMemSurf = r600AllocMemSurf; r600->chipobj.FlushCmdBuffer = r600FlushCmdBuffer; @@ -476,8 +418,9 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, radeonInitSpanFuncs( ctx ); r600InitCmdBuf(r600); + + (r600->chipobj.InitState)(r600->radeon.glCtx); #if 0 /* to be enabled */ - r600InitState(r600); if (!(screen->chip_flags & RADEON_CHIPSET_TCL)) r600InitSwtcl(ctx); #endif diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index 74e34e3684..70108b74c4 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -140,26 +140,19 @@ struct r600_swtcl_info { GLubyte vertex_attr_count; }; -/* to be enabled */ /* DELETE FOLLOWING 2 SRTUCTS */ -struct r600_dma_buffer +enum { - int refcount; /* the number of retained regions in buf */ - drmBufPtr buf; - int id; + NO_SHIFT = 0, + LEFT_SHIFT = 1, + RIGHT_SHIFT = 2, }; -struct r600_dma_region + +typedef struct offset_modifiers { - struct r600_dma_buffer *buf; - char *address; /* == buf->address */ - int start; - int end; - int ptr; /* offsets from start of buf */ - - int aos_offset; /* address in GART memory */ - int aos_stride; /* distance between elements, in dwords */ - int aos_size; /* number of components (1-4) */ -}; -/* ----------------------- */ + GLuint shift; + GLuint shiftbits; + GLuint mask; +} offset_modifiers; typedef struct chip_object { @@ -175,14 +168,16 @@ typedef struct chip_object GLuint (*GetTexObjSize)(void); /* ------------ IN ------------------- */ - void (*EmitShader)( GLcontext * ctx, - struct r600_dma_region *rvb, + GLboolean (*EmitShader)( GLcontext * ctx, + void ** shaderbo, GLvoid * data, int sizeinDWORD); + GLboolean (*DeleteShader)(GLcontext * ctx, + void * shaderbo); void (*FreeDmaRegion)( GLcontext * ctx, - struct r600_dma_region *region); - void (*EmitVec)(GLcontext * ctx, - struct r600_dma_region *rvb, + void * shaderbo); + GLboolean (*EmitVec)(GLcontext * ctx, + struct radeon_aos *aos, GLvoid * data, int size, int stride, diff --git a/src/mesa/drivers/dri/r600/r600_emit.c b/src/mesa/drivers/dri/r600/r600_emit.c index 9d43873c4d..fc8f987cab 100644 --- a/src/mesa/drivers/dri/r600/r600_emit.c +++ b/src/mesa/drivers/dri/r600/r600_emit.c @@ -1,9 +1,8 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. +/************************************************************************** + +Copyright 2008, 2009 Advanced Micro Devices Inc. (AMD) -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. +Copyright (C) Advanced Micro Devices Inc. (AMD) 2009. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the @@ -27,10 +26,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. **************************************************************************/ -/** - * \file - * - * \author Keith Whitwell +/* + * Authors: + * Richard Li , + * CooperYuan , */ #include "main/glheader.h" @@ -48,6 +47,105 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r600_context.h" #include "r600_emit.h" +#if defined(USE_X86_ASM) +#define COPY_DWORDS( dst, src, nr ) \ +do { \ + int __tmp; \ + __asm__ __volatile__( "rep ; movsl" \ + : "=%c" (__tmp), "=D" (dst), "=S" (__tmp) \ + : "0" (nr), \ + "D" ((long)dst), \ + "S" ((long)src) ); \ +} while (0) +#else +#define COPY_DWORDS( dst, src, nr ) \ +do { \ + int j; \ + for ( j = 0 ; j < nr ; j++ ) \ + dst[j] = ((int *)src)[j]; \ + dst += nr; \ +} while (0) +#endif + +static void r600EmitVec4(uint32_t *out, GLvoid * data, int stride, int count) +{ + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); + + if (stride == 4) + COPY_DWORDS(out, data, count); + else + for (i = 0; i < count; i++) { + out[0] = *(int *)data; + out++; + data += stride; + } +} + +static void r600EmitVec8(uint32_t *out, GLvoid * data, int stride, int count) +{ + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); + + if (stride == 8) + COPY_DWORDS(out, data, count * 2); + else + for (i = 0; i < count; i++) { + out[0] = *(int *)data; + out[1] = *(int *)(data + 4); + out += 2; + data += stride; + } +} + +static void r600EmitVec12(uint32_t *out, GLvoid * data, int stride, int count) +{ + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); + + if (stride == 12) { + COPY_DWORDS(out, data, count * 3); + } + else + for (i = 0; i < count; i++) { + out[0] = *(int *)data; + out[1] = *(int *)(data + 4); + out[2] = *(int *)(data + 8); + out += 3; + data += stride; + } +} + +static void r600EmitVec16(uint32_t *out, GLvoid * data, int stride, int count) +{ + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); + + if (stride == 16) + COPY_DWORDS(out, data, count * 4); + else + for (i = 0; i < count; i++) { + out[0] = *(int *)data; + out[1] = *(int *)(data + 4); + out[2] = *(int *)(data + 8); + out[3] = *(int *)(data + 12); + out += 4; + data += stride; + } +} + /* Emit vertex data to GART memory * Route inputs to the vertex processor * This function should never return R600_FALLBACK_TCL when using software tcl. @@ -73,3 +171,111 @@ void r600EmitCacheFlush(r600ContextPtr rmesa) COMMIT_BATCH(); */ } + +GLboolean r600EmitShader(GLcontext * ctx, + void ** shaderbo, + GLvoid * data, + int sizeinDWORD) +{ + radeonContextPtr radeonctx = RADEON_CONTEXT(ctx); + + struct radeon_bo * pbo; + uint32_t *out; + +shader_again_alloc: + pbo = radeon_bo_open(radeonctx->radeonScreen->bom, + 0, + sizeinDWORD * 4, + 256, + RADEON_GEM_DOMAIN_GTT, + 0); + + if (!pbo) + { + rcommonFlushCmdBuf(radeonctx, __FUNCTION__); + goto shader_again_alloc; + } + + radeon_validate_bo(radeonctx, pbo, RADEON_GEM_DOMAIN_GTT, 0); + + if (radeon_revalidate_bos(radeonctx->glCtx) == GL_FALSE) + { + fprintf(stderr,"failure to revalidate BOs - badness\n"); + } + + radeon_bo_map(pbo, 1); + + radeon_bo_ref(pbo); + + out = (uint32_t*)(pbo->ptr); + + memcpy(out, data, sizeinDWORD * 4); + + *shaderbo = (void*)pbo; + + return GL_TRUE; +} + +GLboolean r600DeleteShader(GLcontext * ctx, + void * shaderbo) +{ + struct radeon_bo * pbo = (struct radeon_bo *)shaderbo; + + radeon_bo_unmap(pbo); + radeon_bo_unref(pbo); /* when bo->cref <= 0, bo will be bo_free */ + + return GL_TRUE; +} + +GLboolean r600EmitVec(GLcontext * ctx, + struct radeon_aos *aos, + GLvoid * data, + int size, + int stride, + int count) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + uint32_t *out; + + if (stride == 0) + { + radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); + aos->stride = 0; + } + else + { + radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); + aos->stride = size; + } + + aos->components = size; + aos->count = count; + + out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); + switch (size) { + case 1: r600EmitVec4(out, data, stride, count); break; + case 2: r600EmitVec8(out, data, stride, count); break; + case 3: r600EmitVec12(out, data, stride, count); break; + case 4: r600EmitVec16(out, data, stride, count); break; + default: + assert(0); + break; + } + + return GL_TRUE; +} + +void r600ReleaseVec(GLcontext * ctx) +{ + radeonReleaseArrays(ctx, ~0); +} + +void r600FreeDmaRegion(context_t *context, + void * shaderbo) +{ + struct radeon_bo *pbo = (struct radeon_bo *)shaderbo; + if(pbo) + { + radeon_bo_unref(pbo); + } +} diff --git a/src/mesa/drivers/dri/r600/r600_emit.h b/src/mesa/drivers/dri/r600/r600_emit.h index 3e1cf1ff5f..11765c868c 100644 --- a/src/mesa/drivers/dri/r600/r600_emit.h +++ b/src/mesa/drivers/dri/r600/r600_emit.h @@ -1,41 +1,38 @@ -/* - * Copyright (C) 2005 Vladimir Dergachev. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ +/************************************************************************** + +Copyright 2008, 2009 Advanced Micro Devices Inc. (AMD) + +Copyright (C) Advanced Micro Devices Inc. (AMD) 2009. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ /* * Authors: - * Vladimir Dergachev - * Nicolai Haehnle - * Aapo Tahkola - * Ben Skeggs - * Jerome Glisse + * Richard Li , + * CooperYuan , */ -/* This files defines functions for accessing R600 hardware. - */ + #ifndef __R600_EMIT_H__ #define __R600_EMIT_H__ @@ -44,180 +41,24 @@ #include "r600_cmdbuf.h" #include "radeon_reg.h" -static INLINE uint32_t cmdpacket0(struct radeon_screen *rscrn, - int reg, int count) -{ - if (count) { - return CP_PACKET0(reg, count - 1); - } - return CP_PACKET2; -} - -static INLINE uint32_t cmdvpu(struct radeon_screen *rscrn, int addr, int count) -{ - drm_r300_cmd_header_t cmd; - - cmd.u = 0; - cmd.vpu.cmd_type = R300_CMD_VPU; - cmd.vpu.count = count; - cmd.vpu.adrhi = ((unsigned int)addr & 0xFF00) >> 8; - cmd.vpu.adrlo = ((unsigned int)addr & 0x00FF); - - return cmd.u; -} - -static INLINE uint32_t cmdr500fp(struct radeon_screen *rscrn, - int addr, int count, int type, int clamp) -{ - drm_r300_cmd_header_t cmd; - - cmd.u = 0; - cmd.r500fp.cmd_type = R300_CMD_R500FP; - cmd.r500fp.count = count; - cmd.r500fp.adrhi_flags = ((unsigned int)addr & 0x100) >> 8; - cmd.r500fp.adrhi_flags |= type ? R500FP_CONSTANT_TYPE : 0; - cmd.r500fp.adrhi_flags |= clamp ? R500FP_CONSTANT_CLAMP : 0; - cmd.r500fp.adrlo = ((unsigned int)addr & 0x00FF); - - return cmd.u; -} - -static INLINE uint32_t cmdpacket3(struct radeon_screen *rscrn, int packet) -{ - drm_r300_cmd_header_t cmd; - - cmd.u = 0; - cmd.packet3.cmd_type = R300_CMD_PACKET3; - cmd.packet3.packet = packet; - - return cmd.u; -} - -static INLINE uint32_t cmdcpdelay(struct radeon_screen *rscrn, - unsigned short count) -{ - drm_r300_cmd_header_t cmd; - - cmd.u = 0; - - cmd.delay.cmd_type = R300_CMD_CP_DELAY; - cmd.delay.count = count; - - return cmd.u; -} - -static INLINE uint32_t cmdwait(struct radeon_screen *rscrn, - unsigned char flags) -{ - drm_r300_cmd_header_t cmd; - - cmd.u = 0; - cmd.wait.cmd_type = R300_CMD_WAIT; - cmd.wait.flags = flags; - - return cmd.u; -} - -static INLINE uint32_t cmdpacify(struct radeon_screen *rscrn) -{ - drm_r300_cmd_header_t cmd; - - cmd.u = 0; - cmd.header.cmd_type = R300_CMD_END3D; - - return cmd.u; -} - -/** - * Write the header of a packet3 to the command buffer. - * Outputs 2 dwords and expects (num_extra+1) additional dwords afterwards. - */ -#define OUT_BATCH_PACKET3(packet, num_extra) do {\ - if (!b_l_rmesa->radeonScreen->kernel_mm) { \ - OUT_BATCH(cmdpacket3(b_l_rmesa->radeonScreen,\ - R300_CMD_PACKET3_RAW)); \ - } else b_l_rmesa->cmdbuf.cs->section_cdw++;\ - OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ - } while(0) - -/** - * Must be sent to switch to 2d commands - */ -void static INLINE end_3d(radeonContextPtr radeon) -{ - BATCH_LOCALS(radeon); - - if (!radeon->radeonScreen->kernel_mm) { - BEGIN_BATCH_NO_AUTOSTATE(1); - OUT_BATCH(cmdpacify(radeon->radeonScreen)); - END_BATCH(); - } -} - -void static INLINE cp_delay(r600ContextPtr rmesa, unsigned short count) -{ - BATCH_LOCALS(&rmesa->radeon); - - if (!rmesa->radeon.radeonScreen->kernel_mm) { - BEGIN_BATCH_NO_AUTOSTATE(1); - OUT_BATCH(cmdcpdelay(rmesa->radeon.radeonScreen, count)); - END_BATCH(); - } -} - -void static INLINE cp_wait(radeonContextPtr radeon, unsigned char flags) -{ - BATCH_LOCALS(radeon); - uint32_t wait_until; - - if (!radeon->radeonScreen->kernel_mm) { - BEGIN_BATCH_NO_AUTOSTATE(1); - OUT_BATCH(cmdwait(radeon->radeonScreen, flags)); - END_BATCH(); - } else { - switch(flags) { - case R300_WAIT_2D: - wait_until = (1 << 14); - break; - case R300_WAIT_3D: - wait_until = (1 << 15); - break; - case R300_NEW_WAIT_2D_3D: - wait_until = (1 << 14) | (1 << 15); - break; - case R300_NEW_WAIT_2D_2D_CLEAN: - wait_until = (1 << 14) | (1 << 16) | (1 << 18); - break; - case R300_NEW_WAIT_3D_3D_CLEAN: - wait_until = (1 << 15) | (1 << 17) | (1 << 18); - break; - case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN: - wait_until = (1 << 14) | (1 << 16) | (1 << 18); - wait_until |= (1 << 15) | (1 << 17) | (1 << 18); - break; - default: - return; - } - BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); - OUT_BATCH(wait_until); - END_BATCH(); - } -} - -extern int r600EmitArrays(GLcontext * ctx); - -extern int r600PrimitiveType(r600ContextPtr rmesa, int prim); -extern int r600NumVerts(r600ContextPtr rmesa, int num_verts, int prim); - -extern void r600EmitCacheFlush(r600ContextPtr rmesa); - -extern GLuint r600VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr, - int *inputs, GLint * tab, GLuint nr); -extern GLuint r600VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr); -extern GLuint r600VAPInputCntl0(GLcontext * ctx, GLuint InputsRead); -extern GLuint r600VAPInputCntl1(GLcontext * ctx, GLuint InputsRead); -extern GLuint r600VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten); -extern GLuint r600VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten); +extern GLboolean r600EmitShader(GLcontext * ctx, + void ** shaderbo, + GLvoid * data, + int sizeinDWORD); + +extern GLboolean r600DeleteShader(GLcontext * ctx, + void * shaderbo); + +extern GLboolean r600EmitVec(GLcontext * ctx, + struct radeon_aos *aos, + GLvoid * data, + int size, + int stride, + int count); + +extern void r600ReleaseVec(GLcontext * ctx); + +extern void r600FreeDmaRegion(context_t *context, + void * shaderbo); #endif diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index d0371cdda0..e534bb11b2 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -29,15 +29,15 @@ #include "main/glheader.h" #include "r600_context.h" +#include "r600_cmdbuf.h" #include "r700_chip.h" #include "r700_state.h" #include "r700_tex.h" #include "r700_oglprog.h" +#include "r700_fragprog.h" +#include "r700_vertprog.h" #include "r700_ioctl.h" -/* to be enable -#include "r700_emit.h" -*/ extern const struct tnl_pipeline_stage *r700_pipeline[]; @@ -370,15 +370,235 @@ GLboolean r700InitChipObject(context_t *context) return GL_TRUE; } -GLboolean r700SendContextStates(context_t *context) +void r700SetupVTXConstans(GLcontext * ctx, + unsigned int nStreamID, + void * pAos, + unsigned int size, /* number of elements in vector */ + unsigned int stride, + unsigned int count) /* number of vectors in stream */ { -#if 0 //to be enable + context_t *context = R700_CONTEXT(ctx); + uint32_t *dest; + struct radeon_aos * paos = (struct radeon_aos *)pAos; + offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF}; + + BATCH_LOCALS(&context->radeon); + + unsigned int uSQ_VTX_CONSTANT_WORD0_0; + unsigned int uSQ_VTX_CONSTANT_WORD1_0; + unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0; + unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0; + unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0; + + uSQ_VTX_CONSTANT_WORD0_0 = paos->offset; + uSQ_VTX_CONSTANT_WORD1_0 = count * stride - 1; + + uSQ_VTX_CONSTANT_WORD2_0 |= 0 << BASE_ADDRESS_HI_shift /* TODO */ + |stride << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift + |GetSurfaceFormat(GL_FLOAT, size, NULL) << SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift /* TODO : trace back api for initial data type, not only GL_FLOAT */ + |SQ_NUM_FORMAT_SCALED << SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift + |SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit; + + uSQ_VTX_CONSTANT_WORD3_0 |= 1 << MEM_REQUEST_SIZE_shift; + + uSQ_VTX_CONSTANT_WORD6_0 |= SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift; + + BEGIN_BATCH_NO_AUTOSTATE(9); + + OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); + OUT_BATCH((nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE); + + R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD1_0, + paos->bo, + uSQ_VTX_CONSTANT_WORD1_0, + RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0); + OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0); + OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0); + + END_BATCH(); + COMMIT_BATCH(); + +} + +int r700SetupStreams(GLcontext * ctx) +{ + context_t *context = R700_CONTEXT(ctx); + + BATCH_LOCALS(&context->radeon); + + struct r700_vertex_program *vpc + = (struct r700_vertex_program *)ctx->VertexProgram._Current; + + TNLcontext *tnl = TNL_CONTEXT(ctx); + struct vertex_buffer *vb = &tnl->vb; + + unsigned int unBit; + unsigned int i; + + BEGIN_BATCH_NO_AUTOSTATE(6); + OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); + OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); + OUT_BATCH(0); + + OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); + OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX); + OUT_BATCH(0); + END_BATCH(); + COMMIT_BATCH(); + + //context->aos_count = 0; + for(i=0; imesa_program.Base.InputsRead & unBit) + { + (context->chipobj.EmitVec)(ctx, + &context->radeon.tcl.aos[i], + vb->AttribPtr[i]->data, + vb->AttribPtr[i]->size, + vb->AttribPtr[i]->stride, + vb->Count); + + /* currently aos are packed */ + r700SetupVTXConstans(ctx, + i, + (void*)(&context->radeon.tcl.aos[i]), + (unsigned int)vb->AttribPtr[i]->size, + (unsigned int)(vb->AttribPtr[i]->size * 4), + (unsigned int)vb->Count); + } + } + + return R600_FALLBACK_NONE; +} + +inline GLboolean setRelocReg(context_t *context, unsigned int reg, + void * pbo_vs, void * pbo_fs) +{ + BATCH_LOCALS(&context->radeon); + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + + struct radeon_bo * pbo; + uint32_t voffset; + offset_modifiers offset_mod; + + switch (reg + ASIC_CONTEXT_BASE_INDEX) + { + case mmCB_COLOR0_BASE: + case mmCB_COLOR1_BASE: + case mmCB_COLOR2_BASE: + case mmCB_COLOR3_BASE: + case mmCB_COLOR4_BASE: + case mmCB_COLOR5_BASE: + case mmCB_COLOR6_BASE: + case mmCB_COLOR7_BASE: + { + GLcontext *ctx = GL_CONTEXT(context); + struct radeon_renderbuffer *rrb; + + rrb = radeon_get_colorbuffer(&context->radeon); + if (!rrb || !rrb->bo) + { + fprintf(stderr, "no rrb\n"); + return GL_FALSE; + } + + offset_mod.shift = RIGHT_SHIFT; + offset_mod.shiftbits = 8; + offset_mod.mask = 0x00FFFFFF; + + R600_OUT_BATCH_RELOC(r700->CB_COLOR0_BASE.u32All, + rrb->bo, + r700->CB_COLOR0_BASE.u32All, + 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod); + return GL_TRUE; + } + break; + case mmDB_DEPTH_BASE: + { + GLcontext *ctx = GL_CONTEXT(context); + struct radeon_renderbuffer *rrb; + rrb = radeon_get_depthbuffer(&context->radeon); + + offset_mod.shift = RIGHT_SHIFT; + offset_mod.shiftbits = 8; + offset_mod.mask = 0x00FFFFFF; + + R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All, + rrb->bo, + r700->DB_DEPTH_BASE.u32All, + 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod); + + return GL_TRUE; + } + break; + case mmSQ_PGM_START_VS: + { + if(NULL != pbo_vs) + { + pbo = (struct radeon_bo *)pbo_vs; + } + else + { + pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); + } + + offset_mod.shift = RIGHT_SHIFT; + offset_mod.shiftbits = 8; + offset_mod.mask = 0x00FFFFFF; + + R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_VS.u32All, + pbo, + r700->SQ_PGM_START_VS.u32All, + RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + return GL_TRUE; + } + break; + case mmSQ_PGM_START_FS: + case mmSQ_PGM_START_ES: + case mmSQ_PGM_START_GS: + case mmSQ_PGM_START_PS: + { + if(NULL != pbo_fs) + { + pbo = (struct radeon_bo *)pbo_fs; + } + else + { + pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context)); + } + + offset_mod.shift = RIGHT_SHIFT; + offset_mod.shiftbits = 8; + offset_mod.mask = 0x00FFFFFF; + + voffset = 0; + R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_PS.u32All, + pbo, + r700->SQ_PGM_START_PS.u32All, + RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + return GL_TRUE; + } + break; + } + + return GL_FALSE; +} + +GLboolean r700SendContextStates(context_t *context, void * pbo_vs, void * pbo_fs) +{ + BATCH_LOCALS(&context->radeon); + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); ContextState * pState = r700->pStateList; ContextState * pInit; unsigned int toSend; - unsigned int ui; + unsigned int ui; while(NULL != pState) { @@ -401,17 +621,21 @@ GLboolean r700SendContextStates(context_t *context) pState = pState->pNext; - R700_CMDBUF_CHECK_SPACE(toSend + 2); - R700EP3(context, IT_SET_CONTEXT_REG, toSend); - R700E32(context, pInit->unOffset); - + BEGIN_BATCH_NO_AUTOSTATE(toSend + 2); + R600_OUT_BATCH_REGSEQ(((pInit->unOffset + ASIC_CONTEXT_BASE_INDEX)<<2), toSend); for(ui=0; uipuiValue)); + if( GL_FALSE == setRelocReg(context, (pInit->unOffset+ui), pbo_vs, pbo_fs) ) + { + /* for not reloc reg. */ + OUT_BATCH(*(pInit->puiValue)); + } pInit = pInit->pNext; }; + END_BATCH(); }; -#endif //to be enable + COMMIT_BATCH(); + return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h index f08190027c..30ca2cab84 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.h +++ b/src/mesa/drivers/dri/r600/r700_chip.h @@ -446,13 +446,22 @@ typedef struct _R700_CHIP_CONTEXT ContextState * pStateList; R700_TEXTURE_STATES texture_states; + + GLboolean bEnablePerspective; } R700_CHIP_CONTEXT; #define R700_CONTEXT_STATES(context) ((R700_CHIP_CONTEXT *)(context->chipobj.pvChipObj)) extern GLboolean r700InitChipObject(context_t *context); -extern GLboolean r700SendContextStates(context_t *context); +extern GLboolean r700SendContextStates(context_t *context, void * pbo_vs, void * pbo_fs); +extern int r700SetupStreams(GLcontext * ctx); +extern void r700SetupVTXConstans(GLcontext * ctx, + unsigned int nStreamID, + void * pAos, + unsigned int size, /* number of elements in vector */ + unsigned int stride, + unsigned int Count); /* number of vectors in stream */ #endif /* _R700_CHIP_H_ */ diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c index 5725360dac..743875dfe2 100644 --- a/src/mesa/drivers/dri/r600/r700_clear.c +++ b/src/mesa/drivers/dri/r600/r700_clear.c @@ -35,23 +35,12 @@ #include "r600_context.h" #include "r700_chip.h" -#if 0 /* to be enabled */ #include "r700_shaderinst.h" -#include "r700_emit.h" -#endif /* to be enabled */ +#include "r600_emit.h" extern void r700InitState (GLcontext * ctx); -#if 0 /* to be enabled */ -extern void r700SetupVTXConstans(GLcontext * ctx, - unsigned int nStreamID, - unsigned int aos_offset, - unsigned int size, /* number of elements in vector */ - unsigned int stride, - unsigned int count); -extern GLboolean r700SendContextStates(context_t *context); extern GLboolean r700SyncSurf(context_t *context); -#endif /* to be enabled */ static GLboolean r700ClearFast(context_t *context, GLbitfield mask) { @@ -63,17 +52,15 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) { GLcontext *ctx = GL_CONTEXT(context); -#if 0 /* to be enabled */ + BATCH_LOCALS(&context->radeon); + R700_CHIP_CONTEXT r700Saved; R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); - struct r600_dma_region aos_vs; - struct r600_dma_region aos_fs; - struct r600_dma_region aos_vb; - aos_vs.buf = NULL; - aos_fs.buf = NULL; - aos_vb.buf = NULL; - + void * pbo_vs; + void * pbo_fs; + struct radeon_aos aos_vb; + unsigned int ui; GLfloat fTemp; GLfloat fVb[] = { 1.0f, 1.0f, 1.0f, 1.0f, @@ -93,7 +80,7 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) 0x10000000, 0x340C90, 0x10000400, 0x20340C90, 0x10000800, 0x40340C90, 0x90000C00, 0x60200C90}; - if (context->screen->chip.type <= CHIP_TYPE_RV670) + if (context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV670) { uVs[9] = 0x541910; uVs[11] = 0x20541910; @@ -116,7 +103,7 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) r700InitState(ctx); - r700->CB_COLOR0_BASE.u32All = context->target.rt.gpu >> 8; + r700SetRenderTarget(context); /* Turn off perspective divid. */ SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit); @@ -152,15 +139,19 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) } /* Setup vb */ - R700_CMDBUF_CHECK_SPACE(6); - R700EP3 (context, IT_SET_CTL_CONST, 1); - R700E32 (context, mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); - R700E32 (context, 0); - R700EP3 (context, IT_SET_CTL_CONST, 1); - R700E32 (context, mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX); - R700E32 (context, 0); + BEGIN_BATCH_NO_AUTOSTATE(6); + OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); + OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); + OUT_BATCH(0); + + OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); + OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX); + OUT_BATCH(0); + END_BATCH(); + COMMIT_BATCH(); + (context->chipobj.EmitVec)(ctx, &aos_vb, (GLvoid *)fVb, 4, 16, 6); - r700SetupVTXConstans(ctx, VERT_ATTRIB_POS, (unsigned int)aos_vb.aos_offset, 4, 16, 6); + r700SetupVTXConstans(ctx, VERT_ATTRIB_POS, &aos_vb, 4, 16, 6); /* Setup shaders, copied from dump */ r700->SQ_PGM_RESOURCES_PS.u32All = 0; @@ -168,23 +159,26 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) SETbit(r700->SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); SETbit(r700->SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); /* vs */ - (context->chipobj.EmitShader)(ctx, &aos_vs, (GLvoid *)(&uVs[0]), 28); - r700->SQ_PGM_START_VS.u32All = (aos_vs.aos_offset >> 8) & 0x00FFFFFF; + (context->chipobj.EmitShader)(ctx, &pbo_vs, (GLvoid *)(&uVs[0]), 28); + r700->SQ_PGM_START_VS.u32All = 0; r700->SQ_PGM_RESOURCES_VS.u32All = 0x00800004; + /* vs const */ /* TODO : Set color here */ - R700_CMDBUF_CHECK_SPACE(4 + 2); - R700EP3 (context, IT_SET_ALU_CONST, 4); - R700E32 (context, SQ_ALU_CONSTANT_VS_OFFSET * 4); - R700E32 (context, *((unsigned int*)&(ctx->Color.ClearColor[0]))); - R700E32 (context, *((unsigned int*)&(ctx->Color.ClearColor[1]))); - R700E32 (context, *((unsigned int*)&(ctx->Color.ClearColor[2]))); - R700E32 (context, *((unsigned int*)&(ctx->Color.ClearColor[3]))); + BEGIN_BATCH_NO_AUTOSTATE(4 + 2); + OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, 4)); + OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4); + OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[0]))); + OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[1]))); + OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[2]))); + OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[3]))); + END_BATCH(); + COMMIT_BATCH(); r700->SPI_VS_OUT_CONFIG.u32All = 0x00000000; r700->SPI_PS_IN_CONTROL_0.u32All = 0x20000001; /* ps */ - (context->chipobj.EmitShader)(ctx, &aos_fs, (GLvoid *)(&uFs[0]), 12); - r700->SQ_PGM_START_PS.u32All = (aos_fs.aos_offset >> 8) & 0x00FFFFFF; + (context->chipobj.EmitShader)(ctx, &pbo_fs, (GLvoid *)(&uFs[0]), 12); + r700->SQ_PGM_START_PS.u32All = 0; r700->SQ_PGM_RESOURCES_PS.u32All = 0x00800002; r700->SQ_PGM_EXPORTS_PS.u32All = 0x00000002; r700->DB_SHADER_CONTROL.u32All = 0x00000200; @@ -192,12 +186,12 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) r700->CB_SHADER_CONTROL.u32All = 0x00000001; /* set a valid base address to make the command checker happy */ - r700->SQ_PGM_START_FS.u32All = (aos_fs.aos_offset >> 8) & 0x00FFFFFF; - r700->SQ_PGM_START_ES.u32All = (aos_fs.aos_offset >> 8) & 0x00FFFFFF; - r700->SQ_PGM_START_GS.u32All = (aos_fs.aos_offset >> 8) & 0x00FFFFFF; + r700->SQ_PGM_START_FS.u32All = 0; + r700->SQ_PGM_START_ES.u32All = 0; + r700->SQ_PGM_START_GS.u32All = 0; /* Now, send the states */ - r700SendContextStates(context); + r700SendContextStates(context, pbo_vs, pbo_fs); /* Draw */ GLuint numEntires, j; @@ -211,44 +205,47 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) + 3 /* VGT_PRIMITIVE_TYPE */ + numIndices + 3; /* DRAW_INDEX_IMMD */ - R700_CMDBUF_CHECK_SPACE(numEntires); + BEGIN_BATCH_NO_AUTOSTATE(numEntires); SETfield(VGT_INDEX_TYPE, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask); - R700EP3(context, IT_INDEX_TYPE, 0); - R700E32(context, VGT_INDEX_TYPE); + OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); + OUT_BATCH(VGT_INDEX_TYPE); VGT_NUM_INDICES = numIndices; SETfield(VGT_PRIMITIVE_TYPE, DI_PT_TRILIST, VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask); - R700EP3(context, IT_SET_CONFIG_REG, 1); - R700E32(context, mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); - R700E32(context, VGT_PRIMITIVE_TYPE); + + OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); + OUT_BATCH(VGT_PRIMITIVE_TYPE); SETfield(VGT_DRAW_INITIATOR, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask); SETfield(VGT_DRAW_INITIATOR, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask); - R700EP3(context, IT_DRAW_INDEX_IMMD, (numIndices + 1)); - R700E32(context, VGT_NUM_INDICES); - R700E32(context, VGT_DRAW_INITIATOR); + OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (numIndices + 1))); + OUT_BATCH(VGT_NUM_INDICES); + OUT_BATCH(VGT_DRAW_INITIATOR); for (j=0; jchipobj.FlushCmdBuffer)(context); /* TODO : keep these in context, don't load and release every time. */ - (context->chipobj.FreeDmaRegion)(context, &aos_vs); - (context->chipobj.FreeDmaRegion)(context, &aos_fs); - (context->chipobj.FreeDmaRegion)(context, &aos_vb); + (context->chipobj.DeleteShader)(context, &pbo_vs); + + (context->chipobj.DeleteShader)(context, &pbo_fs); + + (context->chipobj.FreeDmaRegion)(context, aos_vb.bo); /* Restore chip object. */ memcpy(r700, &r700Saved, sizeof(R700_CHIP_CONTEXT)); -#endif /* to be enabled */ - return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index 2b813828a5..d06af109e5 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -36,15 +36,11 @@ #include "shader/prog_statevars.h" #include "r600_context.h" +#include "r600_cmdbuf.h" #include "r700_chip.h" #include "r700_fragprog.h" -/* to be enabled */ -#if 0 -#include "r700_emit.h" -#endif - #include "r700_debug.h" //TODO : Validate FP input with VP output. @@ -250,9 +246,18 @@ GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp, return GL_TRUE; } +void * r700GetActiveFpShaderBo(GLcontext * ctx) +{ + struct r700_fragment_program *fp = (struct r700_fragment_program *) + (ctx->FragmentProgram._Current); + + return fp->shaderbo; +} + GLboolean r700SetupFragmentProgram(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); + BATCH_LOCALS(&context->radeon); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); @@ -271,14 +276,13 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) { Assemble( &(fp->r700Shader) ); } -/* to be enabled */ -#if 0 + /* Load fp to gpu */ (context->chipobj.EmitShader)(ctx, - &(fp->shadercode), + &(fp->shaderbo), (GLvoid *)(fp->r700Shader.pProgram), fp->r700Shader.uShaderBinaryDWORDSize); -#endif + fp->loaded = GL_TRUE; } @@ -288,10 +292,8 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) /* TODO : enable this after MemUse fixed *= (context->chipobj.MemUse)(context, fp->shadercode.buf->id); */ -/* to be enabled */ -#if 0 - r700->SQ_PGM_START_PS.u32All = (fp->shadercode.aos_offset >> 8) & 0x00FFFFFF; -#endif + + r700->SQ_PGM_START_PS.u32All = 0; /* set from buffer obj */ unNumOfReg = fp->r700Shader.nRegs + 1; @@ -337,25 +339,27 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) if(NULL != paramList) { _mesa_load_state_parameters(ctx, paramList); -/* to be enabled */ -#if 0 + unNumParamData = paramList->NumParameters * 4; - R700_CMDBUF_CHECK_SPACE(2 + unNumParamData); - R700EP3(context, IT_SET_ALU_CONST, unNumParamData); + BEGIN_BATCH_NO_AUTOSTATE(2 + unNumParamData); + + OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData)); + /* assembler map const from very beginning. */ - R700E32(context, SQ_ALU_CONSTANT_PS_OFFSET * 4); + OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4); unNumParamData = paramList->NumParameters; for(ui=0; uiParameterValues[ui][0]))); - R700E32(context, *((unsigned int*)&(paramList->ParameterValues[ui][1]))); - R700E32(context, *((unsigned int*)&(paramList->ParameterValues[ui][2]))); - R700E32(context, *((unsigned int*)&(paramList->ParameterValues[ui][3]))); + OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][0]))); + OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1]))); + OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2]))); + OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3]))); } -#endif + END_BATCH(); + COMMIT_BATCH(); } return GL_TRUE; diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.h b/src/mesa/drivers/dri/r600/r700_fragprog.h index 649ee4822d..9c7813e908 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.h +++ b/src/mesa/drivers/dri/r600/r700_fragprog.h @@ -40,10 +40,8 @@ struct r700_fragment_program GLboolean translated; GLboolean loaded; GLboolean error; -/* to be enabled */ -#if 0 - struct r600_dma_region shadercode; -#endif + + void * shaderbo; GLboolean WritesDepth; GLuint optimization; @@ -60,4 +58,6 @@ extern GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp, struct gl_fragment_program *mesa_vp); extern GLboolean r700SetupFragmentProgram(GLcontext * ctx); +extern void * r700GetActiveFpShaderBo(GLcontext * ctx); + #endif /*_R700_FRAGPROG_H_*/ diff --git a/src/mesa/drivers/dri/r600/r700_ioctl.c b/src/mesa/drivers/dri/r600/r700_ioctl.c index 0541dc76e4..7493efab0f 100644 --- a/src/mesa/drivers/dri/r600/r700_ioctl.c +++ b/src/mesa/drivers/dri/r600/r700_ioctl.c @@ -37,12 +37,38 @@ #include "radeon_lock.h" #include "r600_context.h" +#include "r700_chip.h" #include "r700_ioctl.h" #include "r700_clear.h" +static void r700Flush(GLcontext *ctx) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + context_t * context = R700_CONTEXT(ctx); + + if (RADEON_DEBUG & DEBUG_IOCTL) + fprintf(stderr, "%s %d\n", __FUNCTION__, radeon->cmdbuf.cs->cdw); + + /* okay if we have no cmds in the buffer && + we have no DMA flush && + we have no DMA buffer allocated. + then no point flushing anything at all. + */ + if (!radeon->dma.flush && !radeon->cmdbuf.cs->cdw && !radeon->dma.current) + return; + + if (radeon->dma.flush) + radeon->dma.flush( ctx ); + + r700SendContextStates(context, NULL, NULL); + + if (radeon->cmdbuf.cs->cdw) + rcommonFlushCmdBuf(radeon, __FUNCTION__); +} + void r700InitIoctlFuncs(struct dd_function_table *functions) { functions->Clear = r700Clear; functions->Finish = radeonFinish; - functions->Flush = radeonFlush; + functions->Flush = r700Flush; } diff --git a/src/mesa/drivers/dri/r600/r700_oglprog.c b/src/mesa/drivers/dri/r600/r700_oglprog.c index ee6377632b..dc8c936165 100644 --- a/src/mesa/drivers/dri/r600/r700_oglprog.c +++ b/src/mesa/drivers/dri/r600/r700_oglprog.c @@ -36,18 +36,16 @@ #include "r700_chip.h" #include "r700_oglprog.h" - -#if 0 /* to be enabled */ #include "r700_fragprog.h" #include "r700_vertprog.h" -#endif /* to be enabled */ + static struct gl_program *r700NewProgram(GLcontext * ctx, GLenum target, GLuint id) { struct gl_program *pProgram = NULL; -#if 0 /* to be enabled */ + struct r700_vertex_program *vp; struct r700_fragment_program *fp; @@ -62,7 +60,9 @@ static struct gl_program *r700NewProgram(GLcontext * ctx, id); vp->translated = GL_FALSE; vp->loaded = GL_FALSE; - vp->shadercode.buf = NULL; + + vp->shaderbo = NULL; + break; case GL_FRAGMENT_PROGRAM_NV: case GL_FRAGMENT_PROGRAM_ARB: @@ -73,18 +73,19 @@ static struct gl_program *r700NewProgram(GLcontext * ctx, id); fp->translated = GL_FALSE; fp->loaded = GL_FALSE; - fp->shadercode.buf = NULL; + + fp->shaderbo = NULL; + break; default: _mesa_problem(ctx, "Bad target in r700NewProgram"); } -#endif /* to be enabled */ + return pProgram; } static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) { -#if 0 /* to be enabled */ struct r700_vertex_program * vp; struct r700_fragment_program * fp; context_t *context = R700_CONTEXT(ctx); @@ -95,7 +96,9 @@ static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) case GL_VERTEX_PROGRAM_ARB: vp = (struct r700_vertex_program*)prog; /* Release DMA region */ - (context->chipobj.FreeDmaRegion)(context, &(vp->shadercode)); + + (context->chipobj.DeleteShader)(ctx, vp->shaderbo); + /* Clean up */ Clean_Up_Assembler(&(vp->r700AsmCode)); Clean_Up_Shader(&(vp->r700Shader)); @@ -104,7 +107,9 @@ static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) case GL_FRAGMENT_PROGRAM_ARB: fp = (struct r700_fragment_program*)prog; /* Release DMA region */ - (context->chipobj.FreeDmaRegion)(context, &(fp->shadercode)); + + (context->chipobj.DeleteShader)(ctx, fp->shaderbo); + /* Clean up */ Clean_Up_Assembler(&(fp->r700AsmCode)); Clean_Up_Shader(&(fp->r700Shader)); @@ -114,7 +119,6 @@ static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) } _mesa_delete_program(ctx, prog); -#endif /* to be enabled */ } static void diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index fce99ada54..f338cf823c 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -45,107 +45,64 @@ #include "tnl/t_pipeline.h" #include "r600_context.h" +#include "r600_cmdbuf.h" #include "r700_chip.h" +#include "r700_tex.h" -/* to be enable #include "r700_vertprog.h" #include "r700_fragprog.h" #include "r700_state.h" -#include "r700_tex.h" -#include "r700_emit.h" -*/ -#if 0 // to be enable void r700WaitForIdle(context_t *context) { - R700EP3 (context, IT_SET_CONFIG_REG, 1); - R700E32 (context, mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); - R700E32 (context, 1 << 15); + BATCH_LOCALS(&context->radeon); + BEGIN_BATCH_NO_AUTOSTATE(3); + + OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); + OUT_BATCH(1 << 15); + + END_BATCH(); + COMMIT_BATCH(); } void r700WaitForIdleClean(context_t *context) { - R700EP3 (context, IT_EVENT_WRITE, 0); - R700E32 (context, 0x16); + BATCH_LOCALS(&context->radeon); + BEGIN_BATCH_NO_AUTOSTATE(5); + + OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); + OUT_BATCH(0x16); - R700EP3 (context, IT_SET_CONFIG_REG, 1); - R700E32 (context, mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); - R700E32 (context, 1 << 17); + OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); + OUT_BATCH(1 << 17); + + END_BATCH(); + COMMIT_BATCH(); } static void r700Start3D(context_t *context) { - if (context->screen->chip.type <= CHIP_TYPE_RV670) + BATCH_LOCALS(&context->radeon); + if (context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV670) { - R700EP3 (context, IT_START_3D_CMDBUF, 1); - R700E32 (context, 0); + BEGIN_BATCH_NO_AUTOSTATE(2); + OUT_BATCH(CP_PACKET3(R600_IT_START_3D_CMDBUF, 1)); + OUT_BATCH(0); + END_BATCH(); } - R700EP3 (context, IT_CONTEXT_CONTROL, 1); - R700E32 (context, 0x80000000); - R700E32 (context, 0x80000000); - r700WaitForIdleClean(context); -} + BEGIN_BATCH_NO_AUTOSTATE(3); + OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1)); + OUT_BATCH(0x80000000); + OUT_BATCH(0x80000000); + END_BATCH(); + COMMIT_BATCH(); -static int r700SetupStreams(GLcontext * ctx) -{ - context_t *context = R700_CONTEXT(ctx); - - struct r700_vertex_program *vpc - = (struct r700_vertex_program *)ctx->VertexProgram._Current; - - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *vb = &tnl->vb; - - unsigned int unBit; - unsigned int i; - - R700_CMDBUF_CHECK_SPACE(6); - R700EP3 (context, IT_SET_CTL_CONST, 1); - R700E32 (context, mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); - R700E32 (context, 0); - - R700EP3 (context, IT_SET_CTL_CONST, 1); - R700E32 (context, mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX); - R700E32 (context, 0); - - context->aos_count = 0; - for(i=0; imesa_program.Base.InputsRead & unBit) - { - (context->chipobj.EmitVec)(ctx, - &(context->aos[context->aos_count]), - vb->AttribPtr[i]->data, - vb->AttribPtr[i]->size, - vb->AttribPtr[i]->stride, - vb->Count); - - context->aos[context->aos_count].aos_size = vb->AttribPtr[i]->size; - - /* currently aos are packed */ - r700SetupVTXConstans(ctx, - i, - (unsigned int)context->aos[context->aos_count].aos_offset, - (unsigned int)vb->AttribPtr[i]->size, - (unsigned int)(vb->AttribPtr[i]->size * 4), - (unsigned int)vb->Count); - /* TODO : enable this after MemUse fixed *= - (context->chipobj.MemUse)(context, context->aos[context->aos_count].buf->id); - */ - - context->aos_count++; - } - } - for(i=context->aos_count; iaos[i].buf = NULL; - } - - return R600_FALLBACK_NONE; + r700WaitForIdleClean(context); } static GLboolean r700SetupShaders(GLcontext * ctx) @@ -177,7 +134,7 @@ GLboolean r700SendTextureState(context_t *context) unsigned int i; R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); - +#if 0 /* to be enabled */ for(i=0; itexture_states.textures[i] != 0) @@ -204,12 +161,15 @@ GLboolean r700SendTextureState(context_t *context) R700E32 (context, r700->texture_states.samplers[i]->SQ_TEX_SAMPLER2.u32All); } } - +#endif return GL_TRUE; } GLboolean r700SyncSurf(context_t *context) { +#if 0 //to be enabled + BATCH_LOCALS(&context->radeon); + /* TODO : too heavy? */ unsigned int CP_COHER_CNTL = 0; @@ -221,23 +181,20 @@ GLboolean r700SyncSurf(context_t *context) |SMX_ACTION_ENA_bit; - R700_CMDBUF_CHECK_SPACE(5); - R700EP3(context, IT_SURFACE_SYNC, 3); - R700E32(context, CP_COHER_CNTL); - R700E32(context, 0xFFFFFFFF); - R700E32(context, 0x00000000); - R700E32(context, 10); + BEGIN_BATCH_NO_AUTOSTATE(5); + + OUT_BATCH(CP_PACKET3((IT_SURFACE_SYNC << 8), 3))); + OUT_BATCH(CP_COHER_CNTL); + OUT_BATCH(0xFFFFFFFF); + OUT_BATCH(0x00000000); + OUT_BATCH(10); + END_BATCH(); + COMMIT_BATCH(); +#endif return GL_TRUE; } -static void r700SetRenderTarget(context_t *context) -{ - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); - - r700->CB_COLOR0_BASE.u32All = context->target.rt.gpu >> 8; -} - unsigned int r700PrimitiveType(int prim) { switch (prim & PRIM_MODE_MASK) @@ -279,21 +236,21 @@ unsigned int r700PrimitiveType(int prim) } } -#endif // to be enable - static GLboolean r700RunRender(GLcontext * ctx, struct tnl_pipeline_stage *stage) { -#if 0 // to be enable context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + + BATCH_LOCALS(&context->radeon); + unsigned int i, j; TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; struct r700_fragment_program *fp = (struct r700_fragment_program *) (ctx->FragmentProgram._Current); - if (context->screen->chip.type <= CHIP_TYPE_RV670) + if (context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV670) { fp->r700AsmCode.bR6xx = 1; } @@ -329,7 +286,7 @@ static GLboolean r700RunRender(GLcontext * ctx, r700->SQ_PGM_START_ES.u32All = r700->SQ_PGM_START_PS.u32All; r700->SQ_PGM_START_GS.u32All = r700->SQ_PGM_START_PS.u32All; - r700SendContextStates(context); + r700SendContextStates(context, NULL, NULL); /* richard test code */ for (i = 0; i < vb->PrimitiveCount; i++) @@ -351,51 +308,55 @@ static GLboolean r700RunRender(GLcontext * ctx, + numIndices + 3 /* DRAW_INDEX_IMMD */ + 2; /* test stamp */ - R700_CMDBUF_CHECK_SPACE(numEntires); + BEGIN_BATCH_NO_AUTOSTATE(numEntires); VGT_INDEX_TYPE |= DI_INDEX_SIZE_32_BIT << INDEX_TYPE_shift; - R700EP3(context, IT_INDEX_TYPE, 0); - R700E32(context, VGT_INDEX_TYPE); + OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); + OUT_BATCH(VGT_INDEX_TYPE); VGT_NUM_INDICES = numIndices; VGT_PRIMITIVE_TYPE |= r700PrimitiveType(prim) << VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift; - R700EP3(context, IT_SET_CONFIG_REG, 1); - R700E32(context, mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); - R700E32(context, VGT_PRIMITIVE_TYPE); + OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); + OUT_BATCH(VGT_PRIMITIVE_TYPE); VGT_DRAW_INITIATOR |= DI_SRC_SEL_IMMEDIATE << SOURCE_SELECT_shift; VGT_DRAW_INITIATOR |= DI_MAJOR_MODE_0 << MAJOR_MODE_shift; - R700EP3(context, IT_DRAW_INDEX_IMMD, (numIndices + 1)); - R700E32(context, VGT_NUM_INDICES); - R700E32(context, VGT_DRAW_INITIATOR); + OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (numIndices + 1))); + OUT_BATCH(VGT_NUM_INDICES); + OUT_BATCH(VGT_DRAW_INITIATOR); for (j=0; jchipobj.FlushCmdBuffer)(context); - /* free aos => TODO : cache mgr */ - for (i = 0; i < context->aos_count; i++) - { - (context->chipobj.FreeDmaRegion)(context, &(context->aos[i])); - } -#endif // to be enable + (context->chipobj.ReleaseArrays)(ctx); + + //richard test + /* test stamp, write a number to mmSCRATCH4 */ + BEGIN_BATCH_NO_AUTOSTATE(3); + R600_OUT_BATCH_REGVAL((0x2144 << 2), 0x56785678); + END_BATCH(); + COMMIT_BATCH(); + + rcommonFlushCmdBuf( &context->radeon, __FUNCTION__ ); + return GL_FALSE; } @@ -412,11 +373,19 @@ static GLboolean r700RunTCLRender(GLcontext * ctx, /*----------------------*/ { GLboolean bRet = GL_FALSE; -#if 0 // to be enable + /* TODO : sw fallback */ + + /** + * Ensure all enabled and complete textures are uploaded along with any buffers being used. + */ + if(!r700ValidateBuffers(ctx)) + { + return GL_TRUE; + } + context_t *context = R700_CONTEXT(ctx); r700UpdateShaders(ctx); -#endif // to be enable bRet = r700RunRender(ctx, stage); diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 4341f33665..a31a89627c 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -52,10 +52,9 @@ #include "r700_chip.h" #include "r700_state.h" -#if 0 /* to be enabled */ #include "r700_fragprog.h" #include "r700_vertprog.h" -#endif /* to be enabled */ + void r700SetDefaultStates(context_t *context) //-------------------- { @@ -68,13 +67,13 @@ void r700UpdateShaders (GLcontext * ctx) //---------------------------------- GLvector4f dummy_attrib[_TNL_ATTRIB_MAX]; GLvector4f *temp_attrib[_TNL_ATTRIB_MAX]; -#if 0 /* to be enabled */ + struct r700_vertex_program *vp; int i; - if (context->NewGLState) + if (context->radeon.NewGLState) { - context->NewGLState = 0; + context->radeon.NewGLState = 0; for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) { @@ -108,7 +107,6 @@ void r700UpdateShaders (GLcontext * ctx) //---------------------------------- } r700UpdateStateParameters(ctx, _NEW_PROGRAM); -#endif /* to be enabled */ } /* @@ -116,6 +114,7 @@ void r700UpdateShaders (GLcontext * ctx) //---------------------------------- */ void r700UpdateViewportOffset(GLcontext * ctx) //------------------ { + return; } /** @@ -152,7 +151,6 @@ static void r700FetchStateParameter(GLcontext * ctx, void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //-------------------- { -#if 0 /* to be enabled */ struct r700_fragment_program *fp; struct gl_program_parameter_list *paramList; GLuint i; @@ -183,7 +181,6 @@ void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //------------ paramList->ParameterValues[i]); } } -#endif /* to be enabled */ } /** @@ -191,7 +188,6 @@ void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //------------ */ static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //------------------- { -#if 0 /* to be enabled */ context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); @@ -204,12 +200,16 @@ static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //----------- if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) { + _mesa_update_framebuffer(ctx); + /* this updates the DrawBuffer's Width/Height if it's a FBO */ + _mesa_update_draw_buffer_bounds(ctx); + r700UpdateDrawBuffer(ctx); } r700UpdateStateParameters(ctx, new_state); - if(GL_TRUE == context->bEnablePerspective) + if(GL_TRUE == r700->bEnablePerspective) { /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */ CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit); @@ -232,8 +232,7 @@ static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //----------- CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit); } - context->NewGLState |= new_state; -#endif /* to be enabled */ + context->radeon.NewGLState |= new_state; } static void r700SetDepthState(GLcontext * ctx) @@ -492,17 +491,11 @@ static void r700Viewport(GLcontext * ctx, GLsizei width, GLsizei height) //-------------------- { -#if 0 /* to be enabled */ context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); - context->vport_x = x; - context->vport_y = y; - context->vport_width = width; - context->vport_height= height; - - __DRIdrawablePrivate *dPriv = context->currentDraw; + __DRIdrawablePrivate *dPriv = context->radeon.dri.drawable; GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; @@ -534,12 +527,12 @@ static void r700Viewport(GLcontext * ctx, tz = v[MAT_TZ] * scale; /* TODO : Need DMA flush as well. */ - +#if 0 /* to be enabled */ if(context->cmdbuf.count_used > 0) { (context->chipobj.FlushCmdBuffer)(context); } - +#endif /* to be enabled */ r700->PA_CL_VPORT_XSCALE.u32All = *((unsigned int*)(&sx)); r700->PA_CL_VPORT_XOFFSET.u32All = *((unsigned int*)(&tx)); @@ -548,7 +541,6 @@ static void r700Viewport(GLcontext * ctx, r700->PA_CL_VPORT_ZSCALE.u32All = *((unsigned int*)(&sz)); r700->PA_CL_VPORT_ZOFFSET.u32All = *((unsigned int*)(&tz)); -#endif /* to be enabled */ } @@ -600,60 +592,47 @@ static void r700Scissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h) } } - -/** - * Calculate initial hardware state and register state functions. - * Assumes that the command buffer and state atoms have been - * initialized already. - */ -void r700InitState(GLcontext * ctx) //------------------- +void r700SetRenderTarget(context_t *context) { -#if 0 /* to be enabled */ - context_t *context = R700_CONTEXT(ctx); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); - - if(context->ctx->Visual.doubleBufferMode && context->sarea->pfCurrentPage == 0) - { - context->target.rt = context->screen->backBuffer; - } - else - { - context->target.rt = context->screen->frontBuffer; - } + struct radeon_renderbuffer *rrb; + unsigned int nPitchInPixel; + + /* screen/window/view */ SETfield(r700->CB_TARGET_MASK.u32All, 0xF, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask); SETfield(r700->CB_SHADER_MASK.u32All, 0xF, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask); /* screen */ r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0; - SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, context->screen->width, + + SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->width, PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask); - SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, context->screen->height, + SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->height, PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask); /* window */ SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit); - SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, context->currentDraw->x, + SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, context->radeon.dri.drawable->x, PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask); - SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, context->currentDraw->y, + SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, context->radeon.dri.drawable->y, PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask); - SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, context->currentDraw->x + context->currentDraw->w, + SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w, PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask); - SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, context->currentDraw->y + context->currentDraw->h, + SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h, PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask); /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */ r700->PA_SC_CLIPRECT_RULE.u32All = 0x0000FFFF; - SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, context->currentDraw->x, + SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, context->radeon.dri.drawable->x, PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask); - SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, context->currentDraw->y, + SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, context->radeon.dri.drawable->y, PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask); - SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, context->currentDraw->x + context->currentDraw->w, + SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w, PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask); - SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, context->currentDraw->y + context->currentDraw->h, + SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h, PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask); r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All; @@ -665,42 +644,138 @@ void r700InitState(GLcontext * ctx) //------------------- /* more....2d clip */ SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit); - SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, context->currentDraw->x, + SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, context->radeon.dri.drawable->x, PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask); - SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, context->currentDraw->y, + SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, context->radeon.dri.drawable->y, PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask); - SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, context->currentDraw->x + context->currentDraw->w, + SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w, PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask); - SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, context->currentDraw->y + context->currentDraw->h, + SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h, PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask); SETbit(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit); - SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, context->currentDraw->x, + SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, context->radeon.dri.drawable->x, PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, context->currentDraw->y, + SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, context->radeon.dri.drawable->y, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, context->currentDraw->x + context->currentDraw->w, + SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w, PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, context->currentDraw->y + context->currentDraw->h, + SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask); SETbit(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, WINDOW_OFFSET_DISABLE_bit); - SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, context->currentDraw->x, + SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, context->radeon.dri.drawable->x, PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, context->currentDraw->y, + SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, context->radeon.dri.drawable->y, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, context->currentDraw->x + context->currentDraw->w, + SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w, PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, context->currentDraw->y + context->currentDraw->h, + SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask); /* setup viewport */ - r700Viewport(ctx, + r700Viewport(GL_CONTEXT(context), 0, 0, - context->currentDraw->w, - context->currentDraw->h); + context->radeon.dri.drawable->w, + context->radeon.dri.drawable->h); + + rrb = radeon_get_colorbuffer(&context->radeon); + if (!rrb || !rrb->bo) { + fprintf(stderr, "no rrb\n"); + return; + } + + /* color buffer */ + r700->CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset; + nPitchInPixel = rrb->pitch/rrb->cpp; + SETfield(r700->CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1, + PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); + SETfield(r700->CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * rrb->base.Height)/64 )-1, + SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); + r700->CB_COLOR0_BASE.u32All = 0; + SETfield(r700->CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask); + SETfield(r700->CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL, + CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask); + if(4 == rrb->cpp) + { + SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_8_8_8_8, + CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask); + SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask); + } + else + { + SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_5_6_5, + CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask); + SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT_REV, + COMP_SWAP_shift, COMP_SWAP_mask); + } + SETbit(r700->CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit); + SETbit(r700->CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit); + SETfield(r700->CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask); + + /* depth buf */ + r700->DB_DEPTH_SIZE.u32All = 0; + r700->DB_DEPTH_BASE.u32All = 0; + r700->DB_DEPTH_INFO.u32All = 0; + + r700->DB_DEPTH_CONTROL.u32All = 0; + r700->DB_DEPTH_CLEAR.u32All = 0x3F800000; + r700->DB_DEPTH_VIEW.u32All = 0; + r700->DB_RENDER_CONTROL.u32All = 0; + r700->DB_RENDER_OVERRIDE.u32All = 0; + SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask); + SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask); + SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask); + + rrb = radeon_get_depthbuffer(&context->radeon); + if (!rrb) + return; + + nPitchInPixel = rrb->pitch/rrb->cpp; + + SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1, + PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); + SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * rrb->base.Height)/64 )-1, + SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */ + + if(4 == rrb->cpp) + { + switch (GL_CONTEXT(context)->Visual.depthBits) + { + case 16: + case 24: + SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24, + DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask); + break; + default: + fprintf(stderr, "Error: Unsupported depth %d... exiting\n", + GL_CONTEXT(context)->Visual.depthBits); + _mesa_exit(-1); + } + } + else + { + SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16, + DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask); + } + SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1, + DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask); + /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */ +} + +/** + * Calculate initial hardware state and register state functions. + * Assumes that the command buffer and state atoms have been + * initialized already. + */ +void r700InitState(GLcontext * ctx) //------------------- +{ + context_t *context = R700_CONTEXT(ctx); + + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + /* Turn off vgt reuse */ r700->VGT_REUSE_OFF.u32All = 0; SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit); @@ -740,7 +815,7 @@ void r700InitState(GLcontext * ctx) //------------------- POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask); /* Do scale XY and Z by 1/W0. */ - context->bEnablePerspective = GL_TRUE; + r700->bEnablePerspective = GL_TRUE; CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit); CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit); SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit); @@ -811,35 +886,8 @@ void r700InitState(GLcontext * ctx) //------------------- /* depth buf */ r700->DB_DEPTH_SIZE.u32All = 0; - SETfield(r700->DB_DEPTH_SIZE.u32All, (context->screen->depthBuffer.pitch/8)-1, - PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); - SETfield(r700->DB_DEPTH_SIZE.u32All, ( (context->screen->depthBuffer.size / context->screen->cpp)/64 )-1, - SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */ - r700->DB_DEPTH_BASE.u32All = context->screen->depthBuffer.gpu >> 8; + r700->DB_DEPTH_BASE.u32All = 0; r700->DB_DEPTH_INFO.u32All = 0; - if(4 == context->screen->cpp) /* TODO : in scrren create, gives z its own format alloc. */ - { - switch (ctx->Visual.depthBits) - { - case 16: - case 24: - SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24, - DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask); - break; - default: - fprintf(stderr, "Error: Unsupported depth %d... exiting\n", - ctx->Visual.depthBits); - _mesa_exit(-1); - } - } - else - { - SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16, - DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask); - } - SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1, - DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask); - /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */ r700->DB_DEPTH_CONTROL.u32All = 0; r700->DB_DEPTH_CLEAR.u32All = 0x3F800000; r700->DB_DEPTH_VIEW.u32All = 0; @@ -850,27 +898,9 @@ void r700InitState(GLcontext * ctx) //------------------- SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask); /* color buffer */ - SETfield(r700->CB_COLOR0_SIZE.u32All, (context->screen->frontBuffer.pitch/8)-1, - PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); - SETfield(r700->CB_COLOR0_SIZE.u32All, ( (context->screen->frontBuffer.size / context->screen->cpp)/64 )-1, - SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); - r700->CB_COLOR0_BASE.u32All = context->screen->frontBuffer.gpu >> 8; - SETfield(r700->CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask); - SETfield(r700->CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL, - CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask); - if(4 == context->screen->cpp) - { - SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_8_8_8_8, - CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask); - SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask); - } - else - { - SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_5_6_5, - CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask); - SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT_REV, - COMP_SWAP_shift, COMP_SWAP_mask); - } + r700->CB_COLOR0_SIZE.u32All = 0; + r700->CB_COLOR0_BASE.u32All = 0; + r700->CB_COLOR0_INFO.u32All = 0; SETbit(r700->CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit); SETbit(r700->CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit); SETfield(r700->CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask); @@ -879,8 +909,7 @@ void r700InitState(GLcontext * ctx) //------------------- r700->CB_COLOR0_FRAG.u32All = 0; r700->CB_COLOR0_MASK.u32All = 0; - r700->PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000; -#endif /* to be enabled */ + r700->PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000; } void r700InitStateFuncs(struct dd_function_table *functions) //----------------- diff --git a/src/mesa/drivers/dri/r600/r700_state.h b/src/mesa/drivers/dri/r600/r700_state.h index b9542f4dd2..a75c7f0188 100644 --- a/src/mesa/drivers/dri/r600/r700_state.h +++ b/src/mesa/drivers/dri/r600/r700_state.h @@ -42,6 +42,7 @@ extern void r700UpdateDrawBuffer (GLcontext * ctx); extern void r700InitState (GLcontext * ctx); extern void r700InitStateFuncs (struct dd_function_table *functions); +extern void r700SetRenderTarget(context_t *context); extern void r700SetDefaultStates(context_t * context); #endif /* _R600_SCREEN_H */ diff --git a/src/mesa/drivers/dri/r600/r700_tex.c b/src/mesa/drivers/dri/r600/r700_tex.c index 75300d2c5f..85352022bc 100644 --- a/src/mesa/drivers/dri/r600/r700_tex.c +++ b/src/mesa/drivers/dri/r600/r700_tex.c @@ -42,9 +42,7 @@ #include "r600_context.h" #include "r700_chip.h" -#if 0 /* to be enabled */ #include "r700_state.h" -#endif /* to be enabled */ #include "r700_tex.h" @@ -72,7 +70,6 @@ void r700SetTexOffset(__DRIcontext *pDRICtx, GLint texname, { } -#if 0 /* to be enabled */ static GLboolean r700GetTexFormat(struct gl_texture_object *tObj, GLuint mesa_format) { r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; @@ -548,7 +545,6 @@ static void compute_tex_image_offset( *curOffset += size; } -#endif /* to be enabled */ void r700DestroyTexObj(context_t context, r700TexObjPtr t) { @@ -563,9 +559,9 @@ void r700DestroyTexObj(context_t context, r700TexObjPtr t) //} } -#if 0 /* to be enabled */ static void r700SetTexImages(context_t *context, struct gl_texture_object *tObj) { +#if 0 /* to be enabled */ r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; const struct gl_texture_image *baseImage = tObj->Image[0][tObj->BaseLevel]; GLint curOffset; @@ -668,6 +664,7 @@ static void r700SetTexImages(context_t *context, struct gl_texture_object *tObj) TEX_WIDTH_shift, TEX_WIDTH_mask); SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, tObj->Image[0][t->base.firstLevel]->Height - 1, TEX_HEIGHT_shift, TEX_HEIGHT_mask); +#endif /* to be enabled */ } static void r700UploadSubImage(context_t *context, @@ -677,6 +674,7 @@ static void r700UploadSubImage(context_t *context, GLint y, GLuint face) { +#if 0 /* to be enabled */ struct gl_texture_image *texImage = NULL; GLuint offset; GLint imageWidth, imageHeight; @@ -739,10 +737,12 @@ static void r700UploadSubImage(context_t *context, t->src_hight_in_pexel[face][hwlevel], /* height */ t->byte_per_texel, /* byte_per_pixel */ pSrc); /* source data */ +#endif /* to be enabled */ } int r700UploadTexImages(GLcontext * ctx, struct gl_texture_object *tObj, GLuint face) { +#if 0 /* to be enabled */ context_t *context = R700_CONTEXT(ctx); r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; @@ -823,7 +823,7 @@ int r700UploadTexImages(GLcontext * ctx, struct gl_texture_object *tObj, GLuint SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, t->base.firstLevel, BASE_LEVEL_shift, BASE_LEVEL_mask); SETfield(t->texture_state.SQ_TEX_RESOURCE5.u32All, t->base.lastLevel, LAST_LEVEL_shift, LAST_LEVEL_mask); } - +#endif /* to be enabled */ return 0; } @@ -889,8 +889,6 @@ static const struct gl_texture_format *r700Choose8888TexFormat(GLenum srcFormat, return gtfRet; } -#endif /* to be enabled */ - static r700TexObjPtr r700AllocTexObj(struct gl_texture_object *texObj) { r700TexObjPtr t; @@ -1527,6 +1525,16 @@ void r700UpdateTextureState(context_t * context) #endif /* to be enabled */ } +/** + * Ensure all enabled and complete textures are uploaded along with any buffers being used. + */ +GLboolean r700ValidateBuffers(GLcontext * ctx) +{ + /* TODO */ + + return radeon_revalidate_bos(ctx); +} + void r700InitTextureFuncs(struct dd_function_table *functions) { /* Note: we only plug in the functions we implement in the driver diff --git a/src/mesa/drivers/dri/r600/r700_tex.h b/src/mesa/drivers/dri/r600/r700_tex.h index 13290578a1..e322bbc47d 100644 --- a/src/mesa/drivers/dri/r600/r700_tex.h +++ b/src/mesa/drivers/dri/r600/r700_tex.h @@ -97,6 +97,8 @@ extern void r700SetTexOffset(__DRIcontext *pDRICtx, extern void r700DestroyTexObj(context_t rmesa, r700TexObjPtr t); +extern GLboolean r700ValidateBuffers(GLcontext * ctx); + extern void r700InitTextureFuncs(struct dd_function_table *functions); #endif /* __r700_TEX_H__ */ diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index 22a12a00d1..f0dfbe20f0 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -39,15 +39,12 @@ #include "shader/prog_statevars.h" #include "r600_context.h" +#include "r600_cmdbuf.h" #include "r700_chip.h" #include "r700_debug.h" #include "r700_vertprog.h" -#if 0 /* to be enabled */ -#include "r700_emit.h" -#endif - unsigned int Map_Vertex_Output(r700_AssemblerBase *pAsm, struct gl_vertex_program *mesa_vp, unsigned int unStart) @@ -297,11 +294,10 @@ GLboolean r700TranslateVertexShader(struct r700_vertex_program *vp, void r700SelectVertexShader(GLcontext *ctx) { -#if 0 /* to be enabled */ context_t *context = R700_CONTEXT(ctx); struct r700_vertex_program *vpc = (struct r700_vertex_program *)ctx->VertexProgram._Current; - if (context->screen->chip.type <= CHIP_TYPE_RV670) + if (context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV670) { vpc->r700AsmCode.bR6xx = 1; } @@ -327,56 +323,22 @@ void r700SelectVertexShader(GLcontext *ctx) r700TranslateVertexShader(vpc, &(vpc->mesa_program) ); } -#endif /* to be enabled */ } -void r700SetupVTXConstans(GLcontext * ctx, - unsigned int nStreamID, - unsigned int aos_offset, - unsigned int size, /* number of elements in vector */ - unsigned int stride, - unsigned int count) /* number of vectors in stream */ +void * r700GetActiveVpShaderBo(GLcontext * ctx) { - context_t *context = R700_CONTEXT(ctx); - uint32_t *dest; - - unsigned int uSQ_VTX_CONSTANT_WORD0_0; - unsigned int uSQ_VTX_CONSTANT_WORD1_0; - unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0; - unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0; - unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0; - - uSQ_VTX_CONSTANT_WORD0_0 = aos_offset; - uSQ_VTX_CONSTANT_WORD1_0 = count * stride - 1; - - uSQ_VTX_CONSTANT_WORD2_0 |= 0 << BASE_ADDRESS_HI_shift /* TODO */ - |stride << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift - |GetSurfaceFormat(GL_FLOAT, size, NULL) << SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift /* TODO : trace back api for initial data type, not only GL_FLOAT */ - |SQ_NUM_FORMAT_SCALED << SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift - |SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit; - - uSQ_VTX_CONSTANT_WORD3_0 |= 1 << MEM_REQUEST_SIZE_shift; - - uSQ_VTX_CONSTANT_WORD6_0 |= SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift; -#if 0 /* to be enabled */ - R700_CMDBUF_CHECK_SPACE(9); - R700EP3 (context, IT_SET_RESOURCE, 7); - R700E32 (context, (nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE); - - R700E32 (context, uSQ_VTX_CONSTANT_WORD0_0); - R700E32 (context, uSQ_VTX_CONSTANT_WORD1_0); - R700E32 (context, uSQ_VTX_CONSTANT_WORD2_0); - R700E32 (context, uSQ_VTX_CONSTANT_WORD3_0); - R700E32 (context, 0); - R700E32 (context, 0); - R700E32 (context, uSQ_VTX_CONSTANT_WORD6_0); -#endif /* to be enabled */ + struct r700_vertex_program *vp + = (struct r700_vertex_program *)ctx->VertexProgram._Current; + + return vp->shaderbo; } GLboolean r700SetupVertexProgram(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); + BATCH_LOCALS(&context->radeon); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); struct r700_vertex_program *vp @@ -396,7 +358,7 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) /* Load vp to gpu */ (context->chipobj.EmitShader)(ctx, - &(vp->shadercode), + &(vp->shaderbo), (GLvoid *)(vp->r700Shader.pProgram), vp->r700Shader.uShaderBinaryDWORDSize); @@ -410,7 +372,7 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) (context->chipobj.MemUse)(context, vp->shadercode.buf->id); */ - r700->SQ_PGM_START_VS.u32All = (vp->shadercode.aos_offset >> 8) & 0x00FFFFFF; + r700->SQ_PGM_START_VS.u32All = 0; /* set from buffer object. */ SETfield(r700->SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.nRegs + 1, NUM_GPRS_shift, NUM_GPRS_mask); @@ -438,24 +400,26 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) if(NULL != paramList) { _mesa_load_state_parameters(ctx, paramList); -#if 0 /* to be enabled */ + unNumParamData = paramList->NumParameters * 4; - R700_CMDBUF_CHECK_SPACE(unNumParamData + 2); - R700EP3 (context, IT_SET_ALU_CONST, unNumParamData); + BEGIN_BATCH_NO_AUTOSTATE(unNumParamData + 2); + + OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData)); /* assembler map const from very beginning. */ - R700E32 (context, SQ_ALU_CONSTANT_VS_OFFSET * 4); + OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4); unNumParamData = paramList->NumParameters; for(ui=0; uiParameterValues[ui][0]))); - R700E32 (context, *((unsigned int*)&(paramList->ParameterValues[ui][1]))); - R700E32 (context, *((unsigned int*)&(paramList->ParameterValues[ui][2]))); - R700E32 (context, *((unsigned int*)&(paramList->ParameterValues[ui][3]))); + OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][0]))); + OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1]))); + OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2]))); + OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3]))); } -#endif /* to be enabled */ + END_BATCH(); + COMMIT_BATCH(); } return GL_TRUE; diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.h b/src/mesa/drivers/dri/r600/r700_vertprog.h index 0822335c10..6a9726a3d0 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.h +++ b/src/mesa/drivers/dri/r600/r700_vertprog.h @@ -55,7 +55,8 @@ struct r700_vertex_program /* ... */ - struct r600_dma_region shadercode; + void * shaderbo; + ArrayDesc aos_desc[VERT_ATTRIB_MAX]; }; @@ -82,11 +83,6 @@ extern void r700SelectVertexShader(GLcontext *ctx); extern GLboolean r700SetupVertexProgram(GLcontext * ctx); -extern void r700SetupVTXConstans(GLcontext * ctx, - unsigned int nStreamID, - unsigned int aos_offset, - unsigned int size, /* number of elements in vector */ - unsigned int stride, - unsigned int Count); /* number of vectors in stream */ +extern void * r700GetActiveVpShaderBo(GLcontext * ctx); #endif /* _R700_VERTPROG_H_ */ diff --git a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h index 851b488433..abb023c7de 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h +++ b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h @@ -16,85 +16,7 @@ void rcommonBeginBatch(radeonContextPtr rmesa, const char *function, int line); -#define RADEON_CP_PACKET3_NOP 0xC0001000 -#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900 -#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 -#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00 -#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 -#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400 -#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 -#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800 -#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 -#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 -#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 -#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 -#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 -#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 -#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 -#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 -#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500 -#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 -#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 -#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 -#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 - -/* r6xx/r7xx packet 3 type offsets */ -#define R600_SET_CONFIG_REG_OFFSET 0x00008000 -#define R600_SET_CONFIG_REG_END 0x0000ac00 -#define R600_SET_CONTEXT_REG_OFFSET 0x00028000 -#define R600_SET_CONTEXT_REG_END 0x00029000 -#define R600_SET_ALU_CONST_OFFSET 0x00030000 -#define R600_SET_ALU_CONST_END 0x00032000 -#define R600_SET_RESOURCE_OFFSET 0x00038000 -#define R600_SET_RESOURCE_END 0x0003c000 -#define R600_SET_SAMPLER_OFFSET 0x0003c000 -#define R600_SET_SAMPLER_END 0x0003cff0 -#define R600_SET_CTL_CONST_OFFSET 0x0003cff0 -#define R600_SET_CTL_CONST_END 0x0003e200 -#define R600_SET_LOOP_CONST_OFFSET 0x0003e200 -#define R600_SET_LOOP_CONST_END 0x0003e380 -#define R600_SET_BOOL_CONST_OFFSET 0x0003e380 -#define R600_SET_BOOL_CONST_END 0x00040000 - -/* r6xx/r7xx packet 3 types */ -#define R600_IT_INDIRECT_BUFFER_END 0x00001700 -#define R600_IT_SET_PREDICATION 0x00002000 -#define R600_IT_REG_RMW 0x00002100 -#define R600_IT_COND_EXEC 0x00002200 -#define R600_IT_PRED_EXEC 0x00002300 -#define R600_IT_START_3D_CMDBUF 0x00002400 -#define R600_IT_DRAW_INDEX_2 0x00002700 -#define R600_IT_CONTEXT_CONTROL 0x00002800 -#define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900 -#define R600_IT_INDEX_TYPE 0x00002A00 -#define R600_IT_DRAW_INDEX 0x00002B00 -#define R600_IT_DRAW_INDEX_AUTO 0x00002D00 -#define R600_IT_DRAW_INDEX_IMMD 0x00002E00 -#define R600_IT_NUM_INSTANCES 0x00002F00 -#define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400 -#define R600_IT_INDIRECT_BUFFER_MP 0x00003800 -#define R600_IT_MEM_SEMAPHORE 0x00003900 -#define R600_IT_MPEG_INDEX 0x00003A00 -#define R600_IT_WAIT_REG_MEM 0x00003C00 -#define R600_IT_MEM_WRITE 0x00003D00 -#define R600_IT_INDIRECT_BUFFER 0x00003200 -#define R600_IT_CP_INTERRUPT 0x00004000 -#define R600_IT_SURFACE_SYNC 0x00004300 -#define R600_IT_ME_INITIALIZE 0x00004400 -#define R600_IT_COND_WRITE 0x00004500 -#define R600_IT_EVENT_WRITE 0x00004600 -#define R600_IT_EVENT_WRITE_EOP 0x00004700 -#define R600_IT_ONE_REG_WRITE 0x00005700 -#define R600_IT_SET_CONFIG_REG 0x00006800 -#define R600_IT_SET_CONTEXT_REG 0x00006900 -#define R600_IT_SET_ALU_CONST 0x00006A00 -#define R600_IT_SET_BOOL_CONST 0x00006B00 -#define R600_IT_SET_LOOP_CONST 0x00006C00 -#define R600_IT_SET_RESOURCE 0x00006D00 -#define R600_IT_SET_SAMPLER 0x00006E00 -#define R600_IT_SET_CTL_CONST 0x00006F00 -#define R600_IT_SURFACE_BASE_UPDATE 0x00007300 - +/* +r6/r7 : code here moved */ #define CP_PACKET2 (2 << 30) #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) @@ -188,54 +110,14 @@ void rcommonBeginBatch(radeonContextPtr rmesa, #define OUT_BATCH_FLOAT32(f) \ OUT_BATCH(radeonPackFloat32((f))) -/* R600/R700 */ -#define R600_OUT_BATCH_REGS(reg, num) \ -do { \ - if ((reg) >= R600_SET_CONFIG_REG_OFFSET && (reg) < R600_SET_CONFIG_REG_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, (num))); \ - OUT_BATCH(((reg) - R600_SET_CONFIG_REG_OFFSET) >> 2); \ - } else if ((reg) >= R600_SET_CONTEXT_REG_OFFSET && (reg) < R600_SET_CONTEXT_REG_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_CONTEXT_REG, (num))); \ - OUT_BATCH(((reg) - R600_SET_CONTEXT_REG_OFFSET) >> 2); \ - } else if ((reg) >= R600_SET_ALU_CONST_OFFSET && (reg) < R600_SET_ALU_CONST_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (num))); \ - OUT_BATCH(((reg) - R600_SET_ALU_CONST_OFFSET) >> 2); \ - } else if ((reg) >= R600_SET_RESOURCE_OFFSET && (reg) < R600_SET_RESOURCE_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, (num))); \ - OUT_BATCH(((reg) - R600_SET_RESOURCE_OFFSET) >> 2); \ - } else if ((reg) >= R600_SET_SAMPLER_OFFSET && (reg) < R600_SET_SAMPLER_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, (num))); \ - OUT_BATCH(((reg) - R600_SET_SAMPLER_OFFSET) >> 2); \ - } else if ((reg) >= R600_SET_CTL_CONST_OFFSET && (reg) < R600_SET_CTL_CONST_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, (num))); \ - OUT_BATCH(((reg) - R600_SET_CTL_CONST_OFFSET) >> 2); \ - } else if ((reg) >= R600_SET_LOOP_CONST_OFFSET && (reg) < R600_SET_LOOP_CONST_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_LOOP_CONST, (num))); \ - OUT_BATCH(((reg) - R600_SET_LOOP_CONST_OFFSET) >> 2); \ - } else if ((reg) >= R600_SET_BOOL_CONST_OFFSET && (reg) < R600_SET_BOOL_CONST_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_BOOL_CONST, (num))); \ - OUT_BATCH(((reg) - R600_SET_BOOL_CONST_OFFSET) >> 2); \ - } else { \ - OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (num))); \ - } \ -} while (0) - -/** Single register write to command buffer; requires 3 dwords for most things. */ -#define R600_OUT_BATCH_REGVAL(reg, val) \ - R600_OUT_BATCH_REGS((reg), 1); \ - OUT_BATCH((val)) - -/** Continuous register range write to command buffer; requires 1 dword, - * expects count dwords afterwards for register contents. */ -#define R600_OUT_BATCH_REGSEQ(reg, count) \ - R600_OUT_BATCH_REGS((reg), (count)) +/* +r6/r7 : code here moved */ /* Fire the buffered vertices no matter what. */ static INLINE void radeon_firevertices(radeonContextPtr radeon) { if (radeon->cmdbuf.cs->cdw || radeon->dma.flush ) - radeonFlush(radeon->glCtx); + radeon->glCtx->Driver.Flush(radeon->glCtx); /* +r6/r7 */ } #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 756c09fff3..691615938f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -914,7 +914,7 @@ again: if (ret == RADEON_CS_SPACE_OP_TO_BIG) return GL_FALSE; if (ret == RADEON_CS_SPACE_FLUSH) { - radeonFlush(ctx); + ctx->Driver.Flush(ctx); /* +r6/r7 */ if (flushed) return GL_FALSE; flushed = 1; @@ -1014,7 +1014,7 @@ void radeonFinish(GLcontext * ctx) struct gl_framebuffer *fb = ctx->DrawBuffer; int i; - radeonFlush(ctx); + ctx->Driver.Flush(ctx); /* +r6/r7 */ if (radeon->radeonScreen->kernel_mm) { for (i = 0; i < fb->_NumColorDrawBuffers; i++) { diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index b47b095cf2..b33417e93e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -216,22 +216,28 @@ static int cs_process_relocs(struct radeon_cs *cs) csm = (struct cs_manager_legacy*)cs->csm; relocs = (struct cs_reloc_legacy *)cs->relocs; - restart: - for (i = 0; i < cs->crelocs; i++) { - for (j = 0; j < relocs[i].cindices; j++) { +restart: + for (i = 0; i < cs->crelocs; i++) + { + for (j = 0; j < relocs[i].cindices; j++) + { uint32_t soffset, eoffset; r = radeon_bo_legacy_validate(relocs[i].base.bo, &soffset, &eoffset); - if (r == -EAGAIN) - goto restart; - if (r) { + if (r == -EAGAIN) + { + goto restart; + } + if (r) + { fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", relocs[i].base.bo, soffset, eoffset); return r; } cs->packets[relocs[i].indices[j]] += soffset; - if (cs->packets[relocs[i].indices[j]] >= eoffset) { + if (cs->packets[relocs[i].indices[j]] >= eoffset) + { /* radeon_bo_debug(relocs[i].base.bo, 12); */ fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", relocs[i].base.bo, soffset, eoffset); @@ -280,7 +286,8 @@ static int cs_emit(struct radeon_cs *cs) csm->ctx->vtbl.emit_cs_header(cs, csm->ctx); /* append buffer age */ - if (IS_R300_CLASS(csm->ctx->radeonScreen)) { + if ( IS_R300_CLASS(csm->ctx->radeonScreen) ) + { age.scratch.cmd_type = R300_CMD_SCRATCH; /* Scratch register 2 corresponds to what radeonGetAge polls */ csm->pending_age = 0; @@ -315,7 +322,8 @@ static int cs_emit(struct radeon_cs *cs) if (r) { return r; } - if (!IS_R300_CLASS(csm->ctx->radeonScreen)) { + if ((!IS_R300_CLASS(csm->ctx->radeonScreen)) && + (!IS_R600_CLASS(csm->ctx->radeonScreen))) { /* +r6/r7 : No irq for r6/r7 yet. */ drm_radeon_irq_emit_t emit_cmd; emit_cmd.irq_seq = &csm->pending_age; r = drmCommandWrite(cs->csm->fd, DRM_RADEON_IRQ_EMIT, &emit_cmd, sizeof(emit_cmd)); @@ -387,59 +395,71 @@ static int cs_check_space(struct radeon_cs *cs, struct radeon_cs_space_check *bo return 0; /* prepare */ - for (i = 0; i < num_bo; i++) { - bo = bos[i].bo; - - bos[i].new_accounted = 0; - read_domains = bos[i].read_domains; - write_domain = bos[i].write_domain; - - /* pinned bos don't count */ - if (radeon_legacy_bo_is_static(bo)) - continue; + for (i = 0; i < num_bo; i++) + { + bo = bos[i].bo; + + bos[i].new_accounted = 0; + read_domains = bos[i].read_domains; + write_domain = bos[i].write_domain; + + /* pinned bos don't count */ + if (radeon_legacy_bo_is_static(bo)) + continue; - /* already accounted this bo */ - if (write_domain && (write_domain == bo->space_accounted)) - continue; + /* already accounted this bo */ + if (write_domain && (write_domain == bo->space_accounted)) + continue; - if (read_domains && ((read_domains << 16) == bo->space_accounted)) - continue; + if (read_domains && ((read_domains << 16) == bo->space_accounted)) + continue; - if (bo->space_accounted == 0) { - if (write_domain == RADEON_GEM_DOMAIN_VRAM) - this_op_vram_write += bo->size; - else if (write_domain == RADEON_GEM_DOMAIN_GTT) - this_op_gart_write += bo->size; - else - this_op_read += bo->size; - bos[i].new_accounted = (read_domains << 16) | write_domain; - } else { - uint16_t old_read, old_write; - - old_read = bo->space_accounted >> 16; - old_write = bo->space_accounted & 0xffff; - - if (write_domain && (old_read & write_domain)) { - bos[i].new_accounted = write_domain; - /* moving from read to a write domain */ - if (write_domain == RADEON_GEM_DOMAIN_VRAM) { - this_op_read -= bo->size; - this_op_vram_write += bo->size; - } else if (write_domain == RADEON_GEM_DOMAIN_VRAM) { - this_op_read -= bo->size; - this_op_gart_write += bo->size; - } - } else if (read_domains & old_write) { - bos[i].new_accounted = bo->space_accounted & 0xffff; - } else { - /* rewrite the domains */ - if (write_domain != old_write) - fprintf(stderr,"WRITE DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, write_domain, old_write); - if (read_domains != old_read) - fprintf(stderr,"READ DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, read_domains, old_read); - return RADEON_CS_SPACE_FLUSH; - } - } + if (bo->space_accounted == 0) + { + if (write_domain == RADEON_GEM_DOMAIN_VRAM) + this_op_vram_write += bo->size; + else if (write_domain == RADEON_GEM_DOMAIN_GTT) + this_op_gart_write += bo->size; + else + this_op_read += bo->size; + bos[i].new_accounted = (read_domains << 16) | write_domain; + } + else + { + uint16_t old_read, old_write; + + old_read = bo->space_accounted >> 16; + old_write = bo->space_accounted & 0xffff; + + if (write_domain && (old_read & write_domain)) + { + bos[i].new_accounted = write_domain; + /* moving from read to a write domain */ + if (write_domain == RADEON_GEM_DOMAIN_VRAM) + { + this_op_read -= bo->size; + this_op_vram_write += bo->size; + } + else if (write_domain == RADEON_GEM_DOMAIN_VRAM) + { + this_op_read -= bo->size; + this_op_gart_write += bo->size; + } + } + else if (read_domains & old_write) + { + bos[i].new_accounted = bo->space_accounted & 0xffff; + } + else + { + /* rewrite the domains */ + if (write_domain != old_write) + fprintf(stderr,"WRITE DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, write_domain, old_write); + if (read_domains != old_read) + fprintf(stderr,"READ DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, read_domains, old_read); + return RADEON_CS_SPACE_FLUSH; + } + } } if (this_op_read < 0) diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index f62ca7f9eb..b2585eae77 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -165,7 +165,7 @@ radeon_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, return GL_FALSE; } - radeonFlush(ctx); + ctx->Driver.Flush(ctx); /* +r6/r7 */ if (rrb->bo) radeon_bo_unref(rrb->bo); @@ -371,7 +371,7 @@ radeon_framebuffer_renderbuffer(GLcontext * ctx, GLenum attachment, struct gl_renderbuffer *rb) { - radeonFlush(ctx); + ctx->Driver.Flush(ctx); /* +r6/r7 */ _mesa_framebuffer_renderbuffer(ctx, fb, attachment, rb); radeon_draw_buffer(ctx, fb); diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index b75db5b80c..be3b816b86 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -61,8 +61,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_tex.h" #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) #include "r600_context.h" -#include "r700_fragprog.h" -#include "r700_tex.h" +//#include "r700_driconf.h" /* +r6/r7 */ +#include "r700_tex.h" /* +r6/r7 */ #endif #include "utils.h" @@ -405,13 +405,13 @@ static const __DRItexBufferExtension r300TexBufferExtension = { #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) static const __DRItexOffsetExtension r600texOffsetExtension = { { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, - r700SetTexOffset, + r700SetTexOffset, /* +r6/r7 */ }; static const __DRItexBufferExtension r600TexBufferExtension = { { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, - r700SetTexBuffer, - r700SetTexBuffer2, + r700SetTexBuffer, /* +r6/r7 */ + r700SetTexBuffer2, /* +r6/r7 */ }; #endif @@ -941,7 +941,6 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); #endif - /* parse information in __driConfigOptions */ driParseOptionInfo (&screen->optionCache, __driConfigOptions, __driNConfigOptions); -- cgit v1.2.3 From 2a7a2c6b77116fd475e1d05fb0adbd1702d11f77 Mon Sep 17 00:00:00 2001 From: Richard Li Date: Fri, 15 May 2009 19:37:09 -0400 Subject: Fix r6 code bugs. --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 19 +-- src/mesa/drivers/dri/r600/r600_cmdbuf.h | 36 ++--- src/mesa/drivers/dri/r600/r600_context.c | 12 ++ src/mesa/drivers/dri/r600/r600_context.h | 5 +- src/mesa/drivers/dri/r600/r600_emit.c | 15 +- src/mesa/drivers/dri/r600/r600_emit.h | 3 +- src/mesa/drivers/dri/r600/r600_swtcl.c | 6 +- src/mesa/drivers/dri/r600/r700_chip.c | 153 ++++++++++++++------- src/mesa/drivers/dri/r600/r700_chip.h | 4 +- src/mesa/drivers/dri/r600/r700_clear.c | 62 +++++---- src/mesa/drivers/dri/r600/r700_fragprog.c | 15 +- src/mesa/drivers/dri/r600/r700_ioctl.c | 2 +- src/mesa/drivers/dri/r600/r700_render.c | 67 +++++---- src/mesa/drivers/dri/r600/r700_state.c | 6 +- src/mesa/drivers/dri/r600/r700_vertprog.c | 15 +- .../drivers/dri/radeon/radeon_common_context.c | 12 ++ src/mesa/drivers/dri/radeon/radeon_screen.c | 40 ++++-- 17 files changed, 299 insertions(+), 173 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 8550457566..b1f78388e4 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -188,6 +188,7 @@ int r600_cs_write_reloc(struct radeon_cs *cs, cs->crelocs++; radeon_bo_ref(bo); + return 0; } @@ -245,6 +246,8 @@ static int r600_cs_end(struct radeon_cs *cs, { fprintf(stderr, "CS section size missmatch start at (%s,%s,%d) %d vs %d\n", cs->section_file, cs->section_func, cs->section_line, cs->section_ndw, cs->section_cdw); + fprintf(stderr, "cs->section_ndw = %d, cs->cdw = %d, cs->section_cdw = %d \n", + cs->section_ndw, cs->cdw, cs->section_cdw); fprintf(stderr, "CS section end at (%s,%s,%d)\n", file, func, line); return -EPIPE; @@ -356,7 +359,7 @@ static int r600_cs_emit(struct radeon_cs *cs) /* drm_r300_cmd_header_t age; */ uint32_t length_dw_reloc_chunk; uint64_t ull; - uint64_t * chunk_ptrs[2]; + uint64_t chunk_ptrs[2]; uint32_t reloc_chunk[128]; int r; int retry = 0; @@ -370,23 +373,23 @@ static int r600_cs_emit(struct radeon_cs *cs) if (r) { return 0; } - + /* raw ib chunk */ cs_chunk[0].chunk_id = RADEON_CHUNK_ID_IB; cs_chunk[0].length_dw = cs->cdw; - cs_chunk[0].chunk_data = (uint64_t)(cs->packets); + cs_chunk[0].chunk_data = (unsigned long)(cs->packets); /* reloc chaunk */ cs_chunk[1].chunk_id = RADEON_CHUNK_ID_RELOCS; cs_chunk[1].length_dw = length_dw_reloc_chunk; - cs_chunk[1].chunk_data = (uint64_t)&(reloc_chunk[0]); + cs_chunk[1].chunk_data = (unsigned long)&(reloc_chunk[0]); - chunk_ptrs[0] = (uint64_t * )&(cs_chunk[0]); - chunk_ptrs[1] = (uint64_t * )&(cs_chunk[1]); + chunk_ptrs[0] = (uint64_t)(unsigned long)&(cs_chunk[0]); + chunk_ptrs[1] = (uint64_t)(unsigned long)&(cs_chunk[1]); cs_cmd.num_chunks = 2; - cs_cmd.cs_id = 0; - cs_cmd.chunks = (uint64_t)&(chunk_ptrs[0]); + /* cs_cmd.cs_id = 0; */ + cs_cmd.chunks = (uint64_t)(unsigned long)chunk_ptrs; /* dump_cmdbuf(cs); */ diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.h b/src/mesa/drivers/dri/r600/r600_cmdbuf.h index dbb723b2b5..9ad73d9d3a 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.h +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.h @@ -167,38 +167,38 @@ static inline void r600_cs_write_dword(struct radeon_cs *cs, uint32_t dword) #define R600_OUT_BATCH_REGS(reg, num) \ do { \ if ((reg) >= R600_SET_CONFIG_REG_OFFSET && (reg) < R600_SET_CONFIG_REG_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, (num))); \ - OUT_BATCH(((reg) - R600_SET_CONFIG_REG_OFFSET) >> 2); \ + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, (num))); \ + R600_OUT_BATCH(((reg) - R600_SET_CONFIG_REG_OFFSET) >> 2); \ } else if ((reg) >= R600_SET_CONTEXT_REG_OFFSET && (reg) < R600_SET_CONTEXT_REG_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_CONTEXT_REG, (num))); \ - OUT_BATCH(((reg) - R600_SET_CONTEXT_REG_OFFSET) >> 2); \ + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONTEXT_REG, (num))); \ + R600_OUT_BATCH(((reg) - R600_SET_CONTEXT_REG_OFFSET) >> 2); \ } else if ((reg) >= R600_SET_ALU_CONST_OFFSET && (reg) < R600_SET_ALU_CONST_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (num))); \ - OUT_BATCH(((reg) - R600_SET_ALU_CONST_OFFSET) >> 2); \ + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (num))); \ + R600_OUT_BATCH(((reg) - R600_SET_ALU_CONST_OFFSET) >> 2); \ } else if ((reg) >= R600_SET_RESOURCE_OFFSET && (reg) < R600_SET_RESOURCE_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, (num))); \ - OUT_BATCH(((reg) - R600_SET_RESOURCE_OFFSET) >> 2); \ + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, (num))); \ + R600_OUT_BATCH(((reg) - R600_SET_RESOURCE_OFFSET) >> 2); \ } else if ((reg) >= R600_SET_SAMPLER_OFFSET && (reg) < R600_SET_SAMPLER_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, (num))); \ - OUT_BATCH(((reg) - R600_SET_SAMPLER_OFFSET) >> 2); \ + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, (num))); \ + R600_OUT_BATCH(((reg) - R600_SET_SAMPLER_OFFSET) >> 2); \ } else if ((reg) >= R600_SET_CTL_CONST_OFFSET && (reg) < R600_SET_CTL_CONST_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, (num))); \ - OUT_BATCH(((reg) - R600_SET_CTL_CONST_OFFSET) >> 2); \ + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, (num))); \ + R600_OUT_BATCH(((reg) - R600_SET_CTL_CONST_OFFSET) >> 2); \ } else if ((reg) >= R600_SET_LOOP_CONST_OFFSET && (reg) < R600_SET_LOOP_CONST_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_LOOP_CONST, (num))); \ - OUT_BATCH(((reg) - R600_SET_LOOP_CONST_OFFSET) >> 2); \ + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_LOOP_CONST, (num))); \ + R600_OUT_BATCH(((reg) - R600_SET_LOOP_CONST_OFFSET) >> 2); \ } else if ((reg) >= R600_SET_BOOL_CONST_OFFSET && (reg) < R600_SET_BOOL_CONST_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_BOOL_CONST, (num))); \ - OUT_BATCH(((reg) - R600_SET_BOOL_CONST_OFFSET) >> 2); \ + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_BOOL_CONST, (num))); \ + R600_OUT_BATCH(((reg) - R600_SET_BOOL_CONST_OFFSET) >> 2); \ } else { \ - OUT_BATCH(CP_PACKET0((reg), (num))); \ + R600_OUT_BATCH(CP_PACKET0((reg), (num))); \ } \ } while (0) /** Single register write to command buffer; requires 3 dwords for most things. */ #define R600_OUT_BATCH_REGVAL(reg, val) \ R600_OUT_BATCH_REGS((reg), 1); \ - OUT_BATCH((val)) + R600_OUT_BATCH((val)) /** Continuous register range write to command buffer; requires 1 dword, * expects count dwords afterwards for register contents. */ diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 3c8ba003d4..e6c03ecfd5 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -448,3 +448,15 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, return GL_TRUE; } +/* Clean our own things only, radeonDestroyContext will do every thing else. */ +void +r600DestroyContext (__DRIcontextPrivate * driContextPriv) +{ + GET_CURRENT_CONTEXT (ctx); + context_t *context = R700_CONTEXT(ctx); + + (context->chipobj.DestroyChipObj)(context->chipobj.pvChipObj); +} + + + diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index 70108b74c4..ae80037602 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -159,7 +159,7 @@ typedef struct chip_object void *pvChipObj; /* ------------ OUT ------------------- */ - GLboolean (*DestroyChipObj)(void* pvChipObj); + GLboolean (*DestroyChipObj)(GLcontext * ctx); void (*InitFuncs)(struct dd_function_table *functions); @@ -171,7 +171,8 @@ typedef struct chip_object GLboolean (*EmitShader)( GLcontext * ctx, void ** shaderbo, GLvoid * data, - int sizeinDWORD); + int sizeinDWORD, + char * szShaderUsage); GLboolean (*DeleteShader)(GLcontext * ctx, void * shaderbo); void (*FreeDmaRegion)( GLcontext * ctx, diff --git a/src/mesa/drivers/dri/r600/r600_emit.c b/src/mesa/drivers/dri/r600/r600_emit.c index fc8f987cab..dee4cd3435 100644 --- a/src/mesa/drivers/dri/r600/r600_emit.c +++ b/src/mesa/drivers/dri/r600/r600_emit.c @@ -175,7 +175,8 @@ void r600EmitCacheFlush(r600ContextPtr rmesa) GLboolean r600EmitShader(GLcontext * ctx, void ** shaderbo, GLvoid * data, - int sizeinDWORD) + int sizeinDWORD, + char * szShaderUsage) { radeonContextPtr radeonctx = RADEON_CONTEXT(ctx); @@ -183,12 +184,22 @@ GLboolean r600EmitShader(GLcontext * ctx, uint32_t *out; shader_again_alloc: +#ifdef RADEON_DEBUG_BO pbo = radeon_bo_open(radeonctx->radeonScreen->bom, 0, sizeinDWORD * 4, 256, + RADEON_GEM_DOMAIN_GTT, + 0, + szShaderUsage); +#else + pbo = radeon_bo_open(radeonctx->radeonScreen->bom, + 0, + sizeinDWORD * 4, + 256, RADEON_GEM_DOMAIN_GTT, 0); +#endif /* RADEON_DEBUG_BO */ if (!pbo) { @@ -211,6 +222,8 @@ shader_again_alloc: memcpy(out, data, sizeinDWORD * 4); + radeon_bo_unmap(pbo); + *shaderbo = (void*)pbo; return GL_TRUE; diff --git a/src/mesa/drivers/dri/r600/r600_emit.h b/src/mesa/drivers/dri/r600/r600_emit.h index 11765c868c..a2d8312287 100644 --- a/src/mesa/drivers/dri/r600/r600_emit.h +++ b/src/mesa/drivers/dri/r600/r600_emit.h @@ -44,7 +44,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. extern GLboolean r600EmitShader(GLcontext * ctx, void ** shaderbo, GLvoid * data, - int sizeinDWORD); + int sizeinDWORD, + char * szShaderUsage); extern GLboolean r600DeleteShader(GLcontext * ctx, void * shaderbo); diff --git a/src/mesa/drivers/dri/r600/r600_swtcl.c b/src/mesa/drivers/dri/r600/r600_swtcl.c index 4d134070d6..a60e7c942c 100644 --- a/src/mesa/drivers/dri/r600/r600_swtcl.c +++ b/src/mesa/drivers/dri/r600/r600_swtcl.c @@ -594,8 +594,8 @@ static void r600EmitVertexAOS(r600ContextPtr rmesa, GLuint vertex_size, struct r BEGIN_BATCH(7); OUT_BATCH_PACKET3(R600_PACKET3_3D_LOAD_VBPNTR, 2); - OUT_BATCH(1); - OUT_BATCH(vertex_size | (vertex_size << 8)); + R600_OUT_BATCH(1); + R600_OUT_BATCH(vertex_size | (vertex_size << 8)); OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0); END_BATCH(); #endif /* to be enabled */ @@ -612,7 +612,7 @@ static void r600EmitVbufPrim(r600ContextPtr rmesa, GLuint primitive, GLuint vert BEGIN_BATCH(3); OUT_BATCH_PACKET3(R600_PACKET3_3D_DRAW_VBUF_2, 0); - OUT_BATCH(R600_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type); + R600_OUT_BATCH(R600_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type); END_BATCH(); #endif /* to be enabled */ } diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index e534bb11b2..1f160364fa 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -41,16 +41,27 @@ extern const struct tnl_pipeline_stage *r700_pipeline[]; -static GLboolean r700DestroyChipObj(void* pvChipObj) +static GLboolean r700DestroyChipObj(GLcontext * ctx) { + context_t * context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700; - if(NULL == pvChipObj) + if(NULL == context->chipobj.pvChipObj) { return GL_TRUE; } - r700 = (R700_CHIP_CONTEXT *)pvChipObj; + r700 = (R700_CHIP_CONTEXT *)(context->chipobj.pvChipObj); + + if(0 != r700->pbo_vs_clear) + { + (context->chipobj.DeleteShader)(context, r700->pbo_vs_clear); + } + + if(0 != r700->pbo_fs_clear) + { + (context->chipobj.DeleteShader)(context, r700->pbo_fs_clear); + } FREE(r700->pStateList); @@ -405,19 +416,19 @@ void r700SetupVTXConstans(GLcontext * ctx, BEGIN_BATCH_NO_AUTOSTATE(9); - OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); - OUT_BATCH((nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); + R600_OUT_BATCH((nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE); - R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD1_0, + R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0, paos->bo, - uSQ_VTX_CONSTANT_WORD1_0, + uSQ_VTX_CONSTANT_WORD0_0, RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); - OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0); - OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0); - OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0); END_BATCH(); COMMIT_BATCH(); @@ -440,13 +451,13 @@ int r700SetupStreams(GLcontext * ctx) unsigned int i; BEGIN_BATCH_NO_AUTOSTATE(6); - OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); - OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); - OUT_BATCH(0); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); + R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); + R600_OUT_BATCH(0); - OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); - OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX); - OUT_BATCH(0); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); + R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX); + R600_OUT_BATCH(0); END_BATCH(); COMMIT_BATCH(); @@ -476,8 +487,33 @@ int r700SetupStreams(GLcontext * ctx) return R600_FALLBACK_NONE; } +inline GLboolean needRelocReg(context_t *context, unsigned int reg) +{ + switch (reg + ASIC_CONTEXT_BASE_INDEX) + { + case mmCB_COLOR0_BASE: + case mmCB_COLOR1_BASE: + case mmCB_COLOR2_BASE: + case mmCB_COLOR3_BASE: + case mmCB_COLOR4_BASE: + case mmCB_COLOR5_BASE: + case mmCB_COLOR6_BASE: + case mmCB_COLOR7_BASE: + case mmDB_DEPTH_BASE: + case mmSQ_PGM_START_VS: + case mmSQ_PGM_START_FS: + case mmSQ_PGM_START_ES: + case mmSQ_PGM_START_GS: + case mmSQ_PGM_START_PS: + return GL_TRUE; + break; + } + + return GL_FALSE; +} + inline GLboolean setRelocReg(context_t *context, unsigned int reg, - void * pbo_vs, void * pbo_fs) + GLboolean bUseStockShader) { BATCH_LOCALS(&context->radeon); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -507,9 +543,10 @@ inline GLboolean setRelocReg(context_t *context, unsigned int reg, return GL_FALSE; } - offset_mod.shift = RIGHT_SHIFT; - offset_mod.shiftbits = 8; - offset_mod.mask = 0x00FFFFFF; + /* refer to radeonCreateScreen : screen->fbLocation = (temp & 0xffff) << 16; */ + offset_mod.shift = NO_SHIFT; + offset_mod.shiftbits = 0; + offset_mod.mask = 0xFFFFFFFF; R600_OUT_BATCH_RELOC(r700->CB_COLOR0_BASE.u32All, rrb->bo, @@ -524,9 +561,9 @@ inline GLboolean setRelocReg(context_t *context, unsigned int reg, struct radeon_renderbuffer *rrb; rrb = radeon_get_depthbuffer(&context->radeon); - offset_mod.shift = RIGHT_SHIFT; - offset_mod.shiftbits = 8; - offset_mod.mask = 0x00FFFFFF; + offset_mod.shift = NO_SHIFT; + offset_mod.shiftbits = 0; + offset_mod.mask = 0xFFFFFFFF; R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All, rrb->bo, @@ -538,18 +575,25 @@ inline GLboolean setRelocReg(context_t *context, unsigned int reg, break; case mmSQ_PGM_START_VS: { - if(NULL != pbo_vs) + if(GL_TRUE == bUseStockShader) { - pbo = (struct radeon_bo *)pbo_vs; + if(NULL != r700->pbo_vs_clear) + { + pbo = (struct radeon_bo *)(r700->pbo_vs_clear); + } + else + { + return GL_FALSE; + } } else { pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); } - offset_mod.shift = RIGHT_SHIFT; - offset_mod.shiftbits = 8; - offset_mod.mask = 0x00FFFFFF; + offset_mod.shift = NO_SHIFT; + offset_mod.shiftbits = 0; + offset_mod.mask = 0xFFFFFFFF; R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_VS.u32All, pbo, @@ -563,18 +607,25 @@ inline GLboolean setRelocReg(context_t *context, unsigned int reg, case mmSQ_PGM_START_GS: case mmSQ_PGM_START_PS: { - if(NULL != pbo_fs) + if(GL_TRUE == bUseStockShader) { - pbo = (struct radeon_bo *)pbo_fs; + if(NULL != r700->pbo_fs_clear) + { + pbo = (struct radeon_bo *)(r700->pbo_fs_clear); + } + else + { + return GL_FALSE; + } } else { pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context)); } - offset_mod.shift = RIGHT_SHIFT; - offset_mod.shiftbits = 8; - offset_mod.mask = 0x00FFFFFF; + offset_mod.shift = NO_SHIFT; + offset_mod.shiftbits = 0; + offset_mod.mask = 0xFFFFFFFF; voffset = 0; R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_PS.u32All, @@ -589,7 +640,7 @@ inline GLboolean setRelocReg(context_t *context, unsigned int reg, return GL_FALSE; } -GLboolean r700SendContextStates(context_t *context, void * pbo_vs, void * pbo_fs) +GLboolean r700SendContextStates(context_t *context, GLboolean bUseStockShader) { BATCH_LOCALS(&context->radeon); @@ -606,18 +657,22 @@ GLboolean r700SendContextStates(context_t *context, void * pbo_vs, void * pbo_fs pInit = pState; - while(NULL != pState->pNext) + if(GL_FALSE == needRelocReg(context, pState->unOffset)) { - if( (pState->pNext->unOffset - pState->unOffset) > 1 ) + while(NULL != pState->pNext) { - break; - } - else - { - pState = pState->pNext; - toSend++; - } - }; + if( ((pState->pNext->unOffset - pState->unOffset) > 1) + || (GL_TRUE == needRelocReg(context, pState->pNext->unOffset)) ) + { + break; + } + else + { + pState = pState->pNext; + toSend++; + } + }; + } pState = pState->pNext; @@ -625,10 +680,10 @@ GLboolean r700SendContextStates(context_t *context, void * pbo_vs, void * pbo_fs R600_OUT_BATCH_REGSEQ(((pInit->unOffset + ASIC_CONTEXT_BASE_INDEX)<<2), toSend); for(ui=0; uiunOffset+ui), pbo_vs, pbo_fs) ) + if( GL_FALSE == setRelocReg(context, (pInit->unOffset+ui), bUseStockShader) ) { /* for not reloc reg. */ - OUT_BATCH(*(pInit->puiValue)); + R600_OUT_BATCH(*(pInit->puiValue)); } pInit = pInit->pNext; }; diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h index 30ca2cab84..42a72b7019 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.h +++ b/src/mesa/drivers/dri/r600/r700_chip.h @@ -447,6 +447,8 @@ typedef struct _R700_CHIP_CONTEXT R700_TEXTURE_STATES texture_states; + void * pbo_vs_clear; + void * pbo_fs_clear; GLboolean bEnablePerspective; } R700_CHIP_CONTEXT; @@ -454,7 +456,7 @@ typedef struct _R700_CHIP_CONTEXT #define R700_CONTEXT_STATES(context) ((R700_CHIP_CONTEXT *)(context->chipobj.pvChipObj)) extern GLboolean r700InitChipObject(context_t *context); -extern GLboolean r700SendContextStates(context_t *context, void * pbo_vs, void * pbo_fs); +extern GLboolean r700SendContextStates(context_t *context, GLboolean bUseStockShader); extern int r700SetupStreams(GLcontext * ctx); extern void r700SetupVTXConstans(GLcontext * ctx, unsigned int nStreamID, diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c index 743875dfe2..9a7cc000a6 100644 --- a/src/mesa/drivers/dri/r600/r700_clear.c +++ b/src/mesa/drivers/dri/r600/r700_clear.c @@ -140,17 +140,18 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) /* Setup vb */ BEGIN_BATCH_NO_AUTOSTATE(6); - OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); - OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); - OUT_BATCH(0); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); + R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); + R600_OUT_BATCH(0); - OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); - OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX); - OUT_BATCH(0); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); + R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX); + R600_OUT_BATCH(0); END_BATCH(); COMMIT_BATCH(); (context->chipobj.EmitVec)(ctx, &aos_vb, (GLvoid *)fVb, 4, 16, 6); + r700SetupVTXConstans(ctx, VERT_ATTRIB_POS, &aos_vb, 4, 16, 6); /* Setup shaders, copied from dump */ @@ -159,25 +160,33 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) SETbit(r700->SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); SETbit(r700->SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); /* vs */ - (context->chipobj.EmitShader)(ctx, &pbo_vs, (GLvoid *)(&uVs[0]), 28); + if(0 == r700->pbo_vs_clear) + { + (context->chipobj.EmitShader)(ctx, &(r700->pbo_vs_clear), (GLvoid *)(&uVs[0]), 28, "Clr VS"); + } + r700->SQ_PGM_START_VS.u32All = 0; r700->SQ_PGM_RESOURCES_VS.u32All = 0x00800004; /* vs const */ /* TODO : Set color here */ BEGIN_BATCH_NO_AUTOSTATE(4 + 2); - OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, 4)); - OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4); - OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[0]))); - OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[1]))); - OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[2]))); - OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[3]))); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, 4)); + R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4); + R600_OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[0]))); + R600_OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[1]))); + R600_OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[2]))); + R600_OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[3]))); END_BATCH(); COMMIT_BATCH(); r700->SPI_VS_OUT_CONFIG.u32All = 0x00000000; r700->SPI_PS_IN_CONTROL_0.u32All = 0x20000001; /* ps */ - (context->chipobj.EmitShader)(ctx, &pbo_fs, (GLvoid *)(&uFs[0]), 12); + if(0 == r700->pbo_fs_clear) + { + (context->chipobj.EmitShader)(ctx, &(r700->pbo_fs_clear), (GLvoid *)(&uFs[0]), 12, "Clr PS"); + } + r700->SQ_PGM_START_PS.u32All = 0; r700->SQ_PGM_RESOURCES_PS.u32All = 0x00800002; r700->SQ_PGM_EXPORTS_PS.u32All = 0x00000002; @@ -191,7 +200,7 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) r700->SQ_PGM_START_GS.u32All = 0; /* Now, send the states */ - r700SendContextStates(context, pbo_vs, pbo_fs); + r700SendContextStates(context, GL_TRUE); /* Draw */ GLuint numEntires, j; @@ -209,38 +218,33 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) SETfield(VGT_INDEX_TYPE, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask); - OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); - OUT_BATCH(VGT_INDEX_TYPE); + R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); + R600_OUT_BATCH(VGT_INDEX_TYPE); VGT_NUM_INDICES = numIndices; SETfield(VGT_PRIMITIVE_TYPE, DI_PT_TRILIST, VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask); - OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); - OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); - OUT_BATCH(VGT_PRIMITIVE_TYPE); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + R600_OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); + R600_OUT_BATCH(VGT_PRIMITIVE_TYPE); SETfield(VGT_DRAW_INITIATOR, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask); SETfield(VGT_DRAW_INITIATOR, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask); - OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (numIndices + 1))); - OUT_BATCH(VGT_NUM_INDICES); - OUT_BATCH(VGT_DRAW_INITIATOR); + R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (numIndices + 1))); + R600_OUT_BATCH(VGT_NUM_INDICES); + R600_OUT_BATCH(VGT_DRAW_INITIATOR); for (j=0; jchipobj.FlushCmdBuffer)(context); - /* TODO : keep these in context, don't load and release every time. */ - (context->chipobj.DeleteShader)(context, &pbo_vs); - - (context->chipobj.DeleteShader)(context, &pbo_fs); - (context->chipobj.FreeDmaRegion)(context, aos_vb.bo); /* Restore chip object. */ diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index d06af109e5..3aacad9919 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -281,7 +281,8 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) (context->chipobj.EmitShader)(ctx, &(fp->shaderbo), (GLvoid *)(fp->r700Shader.pProgram), - fp->r700Shader.uShaderBinaryDWORDSize); + fp->r700Shader.uShaderBinaryDWORDSize, + "FS"); fp->loaded = GL_TRUE; } @@ -344,19 +345,19 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) BEGIN_BATCH_NO_AUTOSTATE(2 + unNumParamData); - OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData)); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData)); /* assembler map const from very beginning. */ - OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4); + R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4); unNumParamData = paramList->NumParameters; for(ui=0; uiParameterValues[ui][0]))); - OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1]))); - OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2]))); - OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][0]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3]))); } END_BATCH(); COMMIT_BATCH(); diff --git a/src/mesa/drivers/dri/r600/r700_ioctl.c b/src/mesa/drivers/dri/r600/r700_ioctl.c index 7493efab0f..1ab3ee7de5 100644 --- a/src/mesa/drivers/dri/r600/r700_ioctl.c +++ b/src/mesa/drivers/dri/r600/r700_ioctl.c @@ -60,7 +60,7 @@ static void r700Flush(GLcontext *ctx) if (radeon->dma.flush) radeon->dma.flush( ctx ); - r700SendContextStates(context, NULL, NULL); + r700SendContextStates(context, GL_FALSE); if (radeon->cmdbuf.cs->cdw) rcommonFlushCmdBuf(radeon, __FUNCTION__); diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index f338cf823c..aee6a68565 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -59,9 +59,9 @@ void r700WaitForIdle(context_t *context) BATCH_LOCALS(&context->radeon); BEGIN_BATCH_NO_AUTOSTATE(3); - OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); - OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); - OUT_BATCH(1 << 15); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + R600_OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); + R600_OUT_BATCH(1 << 15); END_BATCH(); COMMIT_BATCH(); @@ -72,12 +72,12 @@ void r700WaitForIdleClean(context_t *context) BATCH_LOCALS(&context->radeon); BEGIN_BATCH_NO_AUTOSTATE(5); - OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); - OUT_BATCH(0x16); + R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); + R600_OUT_BATCH(0x16); - OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); - OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); - OUT_BATCH(1 << 17); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + R600_OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); + R600_OUT_BATCH(1 << 17); END_BATCH(); COMMIT_BATCH(); @@ -89,15 +89,15 @@ static void r700Start3D(context_t *context) if (context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV670) { BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH(CP_PACKET3(R600_IT_START_3D_CMDBUF, 1)); - OUT_BATCH(0); + R600_OUT_BATCH(CP_PACKET3(R600_IT_START_3D_CMDBUF, 1)); + R600_OUT_BATCH(0); END_BATCH(); } BEGIN_BATCH_NO_AUTOSTATE(3); - OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1)); - OUT_BATCH(0x80000000); - OUT_BATCH(0x80000000); + R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1)); + R600_OUT_BATCH(0x80000000); + R600_OUT_BATCH(0x80000000); END_BATCH(); COMMIT_BATCH(); @@ -183,11 +183,11 @@ GLboolean r700SyncSurf(context_t *context) BEGIN_BATCH_NO_AUTOSTATE(5); - OUT_BATCH(CP_PACKET3((IT_SURFACE_SYNC << 8), 3))); - OUT_BATCH(CP_COHER_CNTL); - OUT_BATCH(0xFFFFFFFF); - OUT_BATCH(0x00000000); - OUT_BATCH(10); + R600_OUT_BATCH(CP_PACKET3((IT_SURFACE_SYNC << 8), 3))); + R600_OUT_BATCH(CP_COHER_CNTL); + R600_OUT_BATCH(0xFFFFFFFF); + R600_OUT_BATCH(0x00000000); + R600_OUT_BATCH(10); END_BATCH(); COMMIT_BATCH(); @@ -241,7 +241,7 @@ static GLboolean r700RunRender(GLcontext * ctx, { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); - +#if 1 BATCH_LOCALS(&context->radeon); unsigned int i, j; @@ -286,7 +286,7 @@ static GLboolean r700RunRender(GLcontext * ctx, r700->SQ_PGM_START_ES.u32All = r700->SQ_PGM_START_PS.u32All; r700->SQ_PGM_START_GS.u32All = r700->SQ_PGM_START_PS.u32All; - r700SendContextStates(context, NULL, NULL); + r700SendContextStates(context, GL_FALSE); /* richard test code */ for (i = 0; i < vb->PrimitiveCount; i++) @@ -305,33 +305,32 @@ static GLboolean r700RunRender(GLcontext * ctx, numEntires = 2 /* VGT_INDEX_TYPE */ + 3 /* VGT_PRIMITIVE_TYPE */ - + numIndices + 3 /* DRAW_INDEX_IMMD */ - + 2; /* test stamp */ + + numIndices + 3; /* DRAW_INDEX_IMMD */ BEGIN_BATCH_NO_AUTOSTATE(numEntires); VGT_INDEX_TYPE |= DI_INDEX_SIZE_32_BIT << INDEX_TYPE_shift; - OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); - OUT_BATCH(VGT_INDEX_TYPE); + R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); + R600_OUT_BATCH(VGT_INDEX_TYPE); VGT_NUM_INDICES = numIndices; VGT_PRIMITIVE_TYPE |= r700PrimitiveType(prim) << VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift; - OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); - OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); - OUT_BATCH(VGT_PRIMITIVE_TYPE); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + R600_OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); + R600_OUT_BATCH(VGT_PRIMITIVE_TYPE); VGT_DRAW_INITIATOR |= DI_SRC_SEL_IMMEDIATE << SOURCE_SELECT_shift; VGT_DRAW_INITIATOR |= DI_MAJOR_MODE_0 << MAJOR_MODE_shift; - OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (numIndices + 1))); - OUT_BATCH(VGT_NUM_INDICES); - OUT_BATCH(VGT_DRAW_INITIATOR); + R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (numIndices + 1))); + R600_OUT_BATCH(VGT_NUM_INDICES); + R600_OUT_BATCH(VGT_DRAW_INITIATOR); for (j=0; jradeon, __FUNCTION__ ); return GL_FALSE; diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index a31a89627c..117d0add8b 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -692,7 +692,7 @@ void r700SetRenderTarget(context_t *context) nPitchInPixel = rrb->pitch/rrb->cpp; SETfield(r700->CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1, PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); - SETfield(r700->CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * rrb->base.Height)/64 )-1, + SETfield(r700->CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1, SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); r700->CB_COLOR0_BASE.u32All = 0; SETfield(r700->CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask); @@ -737,7 +737,7 @@ void r700SetRenderTarget(context_t *context) SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1, PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); - SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * rrb->base.Height)/64 )-1, + SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1, SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */ if(4 == rrb->cpp) @@ -909,7 +909,7 @@ void r700InitState(GLcontext * ctx) //------------------- r700->CB_COLOR0_FRAG.u32All = 0; r700->CB_COLOR0_MASK.u32All = 0; - r700->PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000; + r700->PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000; } void r700InitStateFuncs(struct dd_function_table *functions) //----------------- diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index f0dfbe20f0..4d113e2e0b 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -360,7 +360,8 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) (context->chipobj.EmitShader)(ctx, &(vp->shaderbo), (GLvoid *)(vp->r700Shader.pProgram), - vp->r700Shader.uShaderBinaryDWORDSize); + vp->r700Shader.uShaderBinaryDWORDSize, + "VS"); vp->loaded = GL_TRUE; } @@ -405,18 +406,18 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) BEGIN_BATCH_NO_AUTOSTATE(unNumParamData + 2); - OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData)); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData)); /* assembler map const from very beginning. */ - OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4); + R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4); unNumParamData = paramList->NumParameters; for(ui=0; uiParameterValues[ui][0]))); - OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1]))); - OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2]))); - OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][0]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3]))); } END_BATCH(); COMMIT_BATCH(); diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index f8a29fdba0..30c858fce0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -216,6 +216,11 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv ) radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL; + /* +r6/r7 */ + __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); + /* --------- */ + if (radeon == current) { radeon_firevertices(radeon); _mesa_make_current(NULL, NULL, NULL); @@ -224,6 +229,13 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv ) assert(radeon); if (radeon) { +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) /* +r6/r7 */ + if (IS_R600_CLASS(screen)) + { + r600DestroyContext(driContextPriv); + } +#endif + if (radeon->dma.current) { rcommonFlushCmdBuf( radeon, __FUNCTION__ ); } diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index be3b816b86..1d26e2c40a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1086,16 +1086,38 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->AGPMode = dri_priv->AGPMode; ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp); - if (ret) { - if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm) - screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; - else { - FREE( screen ); - fprintf(stderr, "Unable to get fb location need newer drm\n"); - return NULL; + + /* +r6/r7 */ + if(screen->chip_family >= CHIP_FAMILY_R600) + { + if (ret) + { + FREE( screen ); + fprintf(stderr, "Unable to get fb location need newer drm\n"); + return NULL; } - } else { - screen->fbLocation = (temp & 0xffff) << 16; + else + { + screen->fbLocation = (temp & 0xffff) << 24; + } + } + else + { + if (ret) + { + if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm) + screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; + else + { + FREE( screen ); + fprintf(stderr, "Unable to get fb location need newer drm\n"); + return NULL; + } + } + else + { + screen->fbLocation = (temp & 0xffff) << 16; + } } if (IS_R300_CLASS(screen)) { -- cgit v1.2.3 From 616692cac5e094c01b6d85741592b4ed59bafeef Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 29 May 2009 13:53:57 -0400 Subject: more cleanup --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 2 +- src/mesa/drivers/dri/r600/r600_cmdbuf.h | 2 +- src/mesa/drivers/dri/r600/r600_context.c | 30 ++++++++++++++---------------- src/mesa/drivers/dri/r600/r600_context.h | 29 ----------------------------- src/mesa/drivers/dri/r600/r600_emit.c | 2 +- 5 files changed, 17 insertions(+), 48 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index b1f78388e4..72a2ac1a8f 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -593,7 +593,7 @@ struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_cont return (struct radeon_cs_manager*)csm; } -void r600InitCmdBuf(r600ContextPtr r600) /* from rcommonInitCmdBuf */ +void r600InitCmdBuf(context_t *r600) /* from rcommonInitCmdBuf */ { radeonContextPtr rmesa = &r600->radeon; diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.h b/src/mesa/drivers/dri/r600/r600_cmdbuf.h index 9ad73d9d3a..6c3ceb38fa 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.h +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.h @@ -205,6 +205,6 @@ do { \ #define R600_OUT_BATCH_REGSEQ(reg, count) \ R600_OUT_BATCH_REGS((reg), (count)) -extern void r600InitCmdBuf(r600ContextPtr r600); +extern void r600InitCmdBuf(context_t *r600); #endif /* __R600_CMDBUF_H__ */ diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 8baaa6aca8..a82dc7f36b 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -190,11 +190,11 @@ static void r600_vtbl_pre_emit_atoms(radeonContextPtr radeon) static void r600_fallback(GLcontext *ctx, GLuint bit, GLboolean mode) { - r600ContextPtr r600 = R600_CONTEXT(ctx); + context_t *context = R700_CONTEXT(ctx); if (mode) - r600->radeon.Fallback |= bit; + context->radeon.Fallback |= bit; else - r600->radeon.Fallback &= ~bit; + context->radeon.Fallback &= ~bit; } static void r600_init_vtbl(radeonContextPtr radeon) @@ -216,7 +216,7 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); struct dd_function_table functions; - r600ContextPtr r600; + context_t *r600; GLcontext *ctx; int tcl_mode; @@ -225,7 +225,7 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, assert(screen); /* Allocate the R600 context */ - r600 = (r600ContextPtr) CALLOC(sizeof(*r600)); + r600 = (context_t*) CALLOC(sizeof(*r600)); if (!r600) return GL_FALSE; @@ -328,17 +328,15 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, _tnl_allow_vertex_fog(ctx, GL_TRUE); /* currently bogus data */ - if (screen->chip_flags & RADEON_CHIPSET_TCL) { - ctx->Const.VertexProgram.MaxInstructions = VSF_MAX_FRAGMENT_LENGTH / 4; - ctx->Const.VertexProgram.MaxNativeInstructions = - VSF_MAX_FRAGMENT_LENGTH / 4; - ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */ - ctx->Const.VertexProgram.MaxTemps = 32; - ctx->Const.VertexProgram.MaxNativeTemps = - /*VSF_MAX_FRAGMENT_TEMPS */ 32; - ctx->Const.VertexProgram.MaxNativeParameters = 256; /* r420 */ - ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; - } + ctx->Const.VertexProgram.MaxInstructions = VSF_MAX_FRAGMENT_LENGTH / 4; + ctx->Const.VertexProgram.MaxNativeInstructions = + VSF_MAX_FRAGMENT_LENGTH / 4; + ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */ + ctx->Const.VertexProgram.MaxTemps = 32; + ctx->Const.VertexProgram.MaxNativeTemps = + /*VSF_MAX_FRAGMENT_TEMPS */ 32; + ctx->Const.VertexProgram.MaxNativeParameters = 256; /* r420 */ + ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; ctx->Const.FragmentProgram.MaxNativeTemps = PFS_NUM_TEMP_REGS; ctx->Const.FragmentProgram.MaxNativeAttribs = 11; /* copy i915... */ diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index 454cc7bad5..63c018dc9b 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -49,9 +49,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/colormac.h" struct r600_context; -typedef struct r600_context r600ContextRec; -typedef struct r600_context *r600ContextPtr; - typedef struct r600_context context_t; #include "main/mm.h" @@ -116,30 +113,6 @@ extern int hw_tcl_on; #define R600_FALLBACK_TCL 1 #define R600_FALLBACK_RAST 2 -/* r600_swtcl.c - */ -struct r600_swtcl_info { - /* - * Offset of the 4UB color data within a hardware (swtcl) vertex. - */ - GLuint coloroffset; - - /** - * Offset of the 3UB specular color data within a hardware (swtcl) vertex. - */ - GLuint specoffset; - - struct vertex_attribute{ - GLuint attr; - GLubyte format; - GLubyte dst_loc; - GLuint swizzle; - GLubyte write_mask; - } vert_attrs[VERT_ATTRIB_MAX]; - - GLubyte vertex_attr_count; -}; - enum { NO_SHIFT = 0, @@ -194,11 +167,9 @@ struct r600_context { GLboolean disable_lowimpact_fallback; - struct r600_swtcl_info swtcl; GLboolean vap_flush_needed; }; -#define R600_CONTEXT(ctx) ((r600ContextPtr)(ctx->DriverCtx)) #define R700_CONTEXT(ctx) ((context_t *)(ctx->DriverCtx)) #define GL_CONTEXT(context) ((GLcontext *)(context->radeon.glCtx)) diff --git a/src/mesa/drivers/dri/r600/r600_emit.c b/src/mesa/drivers/dri/r600/r600_emit.c index 711dfefd73..7f25cb1868 100644 --- a/src/mesa/drivers/dri/r600/r600_emit.c +++ b/src/mesa/drivers/dri/r600/r600_emit.c @@ -47,7 +47,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r600_context.h" #include "r600_emit.h" -void r600EmitCacheFlush(r600ContextPtr rmesa) +void r600EmitCacheFlush(context_t *rmesa) { BATCH_LOCALS(&rmesa->radeon); /* -- cgit v1.2.3 From ada26c40593d1bce972c445aa22f26811f6e6223 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 3 Jun 2009 14:29:06 -0400 Subject: dump command buffer --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 72a2ac1a8f..5edc42b532 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -350,6 +350,17 @@ static int r600_cs_set_age(struct radeon_cs *cs) /* -------------- */ return 0; } +static void dump_cmdbuf(struct radeon_cs *cs) +{ + int i; + fprintf(stderr,"--start--\n"); + for (i = 0; i < cs->cdw; i++){ + fprintf(stderr,"0x%08x\n", cs->packets[i]); + } + fprintf(stderr,"--end--\n"); + +} + static int r600_cs_emit(struct radeon_cs *cs) { struct r600_cs_manager_legacy *csm = (struct r600_cs_manager_legacy*)cs->csm; @@ -391,7 +402,7 @@ static int r600_cs_emit(struct radeon_cs *cs) /* cs_cmd.cs_id = 0; */ cs_cmd.chunks = (uint64_t)(unsigned long)chunk_ptrs; - /* dump_cmdbuf(cs); */ + dump_cmdbuf(cs); do { -- cgit v1.2.3 From eaadba6eee05cd725295821e0c1f5e1a01e99e89 Mon Sep 17 00:00:00 2001 From: Cooper Yuan Date: Thu, 25 Jun 2009 19:48:43 +0800 Subject: Fix color data can't be fetched issue --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 2 +- src/mesa/drivers/dri/r600/r700_clear.c | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 5edc42b532..90f546edf1 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -288,7 +288,7 @@ restart: relocs[i].base.bo, soffset, eoffset); return r; } - asicoffset = cs->packets[relocs[i].indices[j]] + soffset; + asicoffset = soffset; if (asicoffset >= eoffset) { /* radeon_bo_debug(relocs[i].base.bo, 12); */ diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c index f142aafd03..b04441da28 100644 --- a/src/mesa/drivers/dri/r600/r700_clear.c +++ b/src/mesa/drivers/dri/r600/r700_clear.c @@ -63,9 +63,6 @@ void r700Clear(GLcontext * ctx, GLbitfield mask) int i; struct gl_framebuffer *fb = ctx->DrawBuffer; - /* XXX FIXME */ - return; - if( GL_TRUE == r700ClearFast(context, mask) ) { return; -- cgit v1.2.3 From 1bad691a177240e8281592fa66c9e6ab0869f618 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 6 Jul 2009 00:00:10 -0400 Subject: R6xx/r7xx: first pass at texture support texture bo setup isn't quite working yet --- src/mesa/drivers/dri/r600/Makefile | 3 +- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 2 +- src/mesa/drivers/dri/r600/r600_context.c | 2 +- src/mesa/drivers/dri/r600/r600_tex.c | 438 ++++++ src/mesa/drivers/dri/r600/r600_tex.h | 63 + src/mesa/drivers/dri/r600/r600_texstate.c | 795 ++++++++++ src/mesa/drivers/dri/r600/r700_chip.c | 2 +- src/mesa/drivers/dri/r600/r700_chip.h | 4 +- src/mesa/drivers/dri/r600/r700_render.c | 74 +- src/mesa/drivers/dri/r600/r700_tex.c | 1558 -------------------- src/mesa/drivers/dri/r600/r700_tex.h | 104 -- .../drivers/dri/radeon/radeon_common_context.h | 13 + src/mesa/drivers/dri/radeon/radeon_screen.c | 8 +- 13 files changed, 1365 insertions(+), 1701 deletions(-) create mode 100644 src/mesa/drivers/dri/r600/r600_tex.c create mode 100644 src/mesa/drivers/dri/r600/r600_tex.h create mode 100644 src/mesa/drivers/dri/r600/r600_texstate.c delete mode 100644 src/mesa/drivers/dri/r600/r700_tex.c delete mode 100644 src/mesa/drivers/dri/r600/r700_tex.h (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/Makefile b/src/mesa/drivers/dri/r600/Makefile index 667eb1f919..6db0154784 100644 --- a/src/mesa/drivers/dri/r600/Makefile +++ b/src/mesa/drivers/dri/r600/Makefile @@ -50,7 +50,8 @@ DRIVER_SOURCES = \ r700_state.c \ r700_clear.c \ r700_render.c \ - r700_tex.c \ + r600_tex.c \ + r600_texstate.c \ r700_debug.c \ $(RADEON_COMMON_SOURCES) \ $(EGL_SOURCES) diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 90f546edf1..4609e86bb9 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -52,7 +52,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_mipmap_tree.h" #include "radeon_reg.h" -struct r600_cs_manager_legacy +struct r600_cs_manager_legacy { struct radeon_cs_manager base; struct radeon_context *ctx; diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 526d02ed57..78bad8726b 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -251,7 +251,7 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, r700InitChipObject(r600); /* let the eag... */ r700InitStateFuncs(&functions); - r700InitTextureFuncs(&functions); + r600InitTextureFuncs(&functions); r700InitShaderFuncs(&functions); r700InitIoctlFuncs(&functions); diff --git a/src/mesa/drivers/dri/r600/r600_tex.c b/src/mesa/drivers/dri/r600/r600_tex.c new file mode 100644 index 0000000000..5845c05810 --- /dev/null +++ b/src/mesa/drivers/dri/r600/r600_tex.c @@ -0,0 +1,438 @@ +/* +Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + +The Weather Channel (TM) funded Tungsten Graphics to develop the +initial release of the Radeon 8500 driver under the XFree86 license. +This notice must be preserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +/** + * \file + * + * \author Keith Whitwell + */ + +#include "main/glheader.h" +#include "main/imports.h" +#include "main/colormac.h" +#include "main/context.h" +#include "main/enums.h" +#include "main/image.h" +#include "main/mipmap.h" +#include "main/simple_list.h" +#include "main/texformat.h" +#include "main/texstore.h" +#include "main/teximage.h" +#include "main/texobj.h" + +#include "texmem.h" + +#include "r600_context.h" +#include "r700_state.h" +#include "radeon_mipmap_tree.h" +#include "r600_tex.h" + +#include "xmlpool.h" + + +static unsigned int translate_wrap_mode(GLenum wrapmode) +{ + switch(wrapmode) { + case GL_REPEAT: return SQ_TEX_WRAP; + case GL_CLAMP: return SQ_TEX_CLAMP_HALF_BORDER; + case GL_CLAMP_TO_EDGE: return SQ_TEX_CLAMP_LAST_TEXEL; + case GL_CLAMP_TO_BORDER: return SQ_TEX_CLAMP_BORDER; + case GL_MIRRORED_REPEAT: return SQ_TEX_MIRROR_ONCE_HALF_BORDER; + case GL_MIRROR_CLAMP_EXT: return SQ_TEX_MIRROR; + case GL_MIRROR_CLAMP_TO_EDGE_EXT: return SQ_TEX_MIRROR_ONCE_BORDER; + case GL_MIRROR_CLAMP_TO_BORDER_EXT: return SQ_TEX_MIRROR_ONCE_LAST_TEXEL; + default: + _mesa_problem(NULL, "bad wrap mode in %s", __FUNCTION__); + return 0; + } +} + + +/** + * Update the cached hardware registers based on the current texture wrap modes. + * + * \param t Texture object whose wrap modes are to be set + */ +static void r600UpdateTexWrap(radeonTexObjPtr t) +{ + struct gl_texture_object *tObj = &t->base; + + SETfield(t->SQ_TEX_SAMPLER0, translate_wrap_mode(tObj->WrapS), + SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift, SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask); + + if (tObj->Target != GL_TEXTURE_1D) { + SETfield(t->SQ_TEX_SAMPLER0, translate_wrap_mode(tObj->WrapT), + CLAMP_Y_shift, CLAMP_Y_mask); + + if (tObj->Target == GL_TEXTURE_3D) + SETfield(t->SQ_TEX_SAMPLER0, translate_wrap_mode(tObj->WrapR), + CLAMP_Z_shift, CLAMP_Z_mask); + } +} + +static void r600SetTexDefaultState(radeonTexObjPtr t) +{ + /* Init text object to default states. */ + t->SQ_TEX_RESOURCE0 = 0; + SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_2D, DIM_shift, DIM_mask); + SETfield(t->SQ_TEX_RESOURCE0, ARRAY_LINEAR_GENERAL, + SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift, SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask); + CLEARbit(t->SQ_TEX_RESOURCE0, TILE_TYPE_bit); + + t->SQ_TEX_RESOURCE1 = 0; + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE2 = 0; + t->SQ_TEX_RESOURCE3 = 0; + + t->SQ_TEX_RESOURCE4 = 0; + SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED, + FORMAT_COMP_X_shift, FORMAT_COMP_X_mask); + SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED, + FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask); + SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED, + FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask); + SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED, + FORMAT_COMP_W_shift, FORMAT_COMP_W_mask); + SETfield(t->SQ_TEX_RESOURCE4, SQ_NUM_FORMAT_NORM, + SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift, SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_mask); + CLEARbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit); + CLEARbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit); + SETfield(t->SQ_TEX_RESOURCE4, SQ_ENDIAN_NONE, + SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift, SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_mask); + SETfield(t->SQ_TEX_RESOURCE4, 1, REQUEST_SIZE_shift, REQUEST_SIZE_mask); + t->SQ_TEX_RESOURCE4 |= SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift + |SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift + |SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift + |SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift; + SETfield(t->SQ_TEX_RESOURCE4, 0, BASE_LEVEL_shift, BASE_LEVEL_mask); /* mip-maps */ + + t->SQ_TEX_RESOURCE5 = 0; + t->SQ_TEX_RESOURCE6 = 0; + + SETfield(t->SQ_TEX_RESOURCE6, SQ_TEX_VTX_VALID_TEXTURE, + SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask); + + /* Initialize sampler registers */ + t->SQ_TEX_SAMPLER0 = 0; + t->SQ_TEX_SAMPLER0 |= + SQ_TEX_WRAP << SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift + |SQ_TEX_WRAP << CLAMP_Y_shift + |SQ_TEX_WRAP << CLAMP_Z_shift + |SQ_TEX_XY_FILTER_POINT << XY_MAG_FILTER_shift + |SQ_TEX_XY_FILTER_POINT << XY_MIN_FILTER_shift + |SQ_TEX_Z_FILTER_NONE << Z_FILTER_shift + |SQ_TEX_Z_FILTER_NONE << MIP_FILTER_shift + |SQ_TEX_BORDER_COLOR_TRANS_BLACK << BORDER_COLOR_TYPE_shift; + + t->SQ_TEX_SAMPLER1 = 0x7FF << MAX_LOD_shift; + + t->SQ_TEX_SAMPLER2 = 0; + SETbit(t->SQ_TEX_SAMPLER2, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit); +} + + +static GLuint aniso_filter(GLfloat anisotropy) +{ +#if 0 + if (anisotropy >= 16.0) { + return R300_TX_MAX_ANISO_16_TO_1; + } else if (anisotropy >= 8.0) { + return R300_TX_MAX_ANISO_8_TO_1; + } else if (anisotropy >= 4.0) { + return R300_TX_MAX_ANISO_4_TO_1; + } else if (anisotropy >= 2.0) { + return R300_TX_MAX_ANISO_2_TO_1; + } else { + return R300_TX_MAX_ANISO_1_TO_1; + } +#endif + return 0; +} + +/** + * Set the texture magnification and minification modes. + * + * \param t Texture whose filter modes are to be set + * \param minf Texture minification mode + * \param magf Texture magnification mode + * \param anisotropy Maximum anisotropy level + */ +static void r600SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloat anisotropy) +{ + /* Force revalidation to account for switches from/to mipmapping. */ + t->validated = GL_FALSE; + + /* Note that EXT_texture_filter_anisotropic is extremely vague about + * how anisotropic filtering interacts with the "normal" filter modes. + * When anisotropic filtering is enabled, we override min and mag + * filter settings completely. This includes driconf's settings. + */ + if (anisotropy >= 2.0 && (minf != GL_NEAREST) && (magf != GL_NEAREST)) { + /*t->pp_txfilter |= R300_TX_MAG_FILTER_ANISO + | R300_TX_MIN_FILTER_ANISO + | R300_TX_MIN_FILTER_MIP_LINEAR + | aniso_filter(anisotropy);*/ + if (RADEON_DEBUG & DEBUG_TEXTURE) + fprintf(stderr, "Using maximum anisotropy of %f\n", anisotropy); + return; + } + + switch (minf) { + case GL_NEAREST: + SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point, + XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); + SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_None, + MIP_FILTER_shift, MIP_FILTER_mask); + break; + case GL_LINEAR: + SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear, + XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); + SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_None, + MIP_FILTER_shift, MIP_FILTER_mask); + break; + case GL_NEAREST_MIPMAP_NEAREST: + SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point, + XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); + SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Point, + MIP_FILTER_shift, MIP_FILTER_mask); + break; + case GL_NEAREST_MIPMAP_LINEAR: + SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point, + XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); + SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Linear, + MIP_FILTER_shift, MIP_FILTER_mask); + break; + case GL_LINEAR_MIPMAP_NEAREST: + SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear, + XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); + SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Point, + MIP_FILTER_shift, MIP_FILTER_mask); + break; + case GL_LINEAR_MIPMAP_LINEAR: + SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear, + XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); + SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Linear, + MIP_FILTER_shift, MIP_FILTER_mask); + break; + } + + /* Note we don't have 3D mipmaps so only use the mag filter setting + * to set the 3D texture filter mode. + */ + switch (magf) { + case GL_NEAREST: + SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point, + XY_MAG_FILTER_shift, XY_MAG_FILTER_mask); + break; + case GL_LINEAR: + SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear, + XY_MAG_FILTER_shift, XY_MAG_FILTER_mask); + break; + } +} + +static void r600SetTexBorderColor(radeonTexObjPtr t, const GLfloat color[4]) +{ +#if 0 + GLubyte c[4]; + CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]); + CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]); + CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]); + CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]); + t->pp_border_color = PACK_COLOR_8888(c[3], c[0], c[1], c[2]); +#endif +} + +/** + * Changes variables and flags for a state update, which will happen at the + * next UpdateTextureState + */ + +static void r600TexParameter(GLcontext * ctx, GLenum target, + struct gl_texture_object *texObj, + GLenum pname, const GLfloat * params) +{ + radeonTexObj* t = radeon_tex_obj(texObj); + + if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { + fprintf(stderr, "%s( %s )\n", __FUNCTION__, + _mesa_lookup_enum_by_nr(pname)); + } + + switch (pname) { + case GL_TEXTURE_MIN_FILTER: + case GL_TEXTURE_MAG_FILTER: + case GL_TEXTURE_MAX_ANISOTROPY_EXT: + r600SetTexFilter(t, texObj->MinFilter, texObj->MagFilter, texObj->MaxAnisotropy); + break; + + case GL_TEXTURE_WRAP_S: + case GL_TEXTURE_WRAP_T: + case GL_TEXTURE_WRAP_R: + r600UpdateTexWrap(t); + break; + + case GL_TEXTURE_BORDER_COLOR: + r600SetTexBorderColor(t, texObj->BorderColor); + break; + + case GL_TEXTURE_BASE_LEVEL: + case GL_TEXTURE_MAX_LEVEL: + case GL_TEXTURE_MIN_LOD: + case GL_TEXTURE_MAX_LOD: + /* This isn't the most efficient solution but there doesn't appear to + * be a nice alternative. Since there's no LOD clamping, + * we just have to rely on loading the right subset of mipmap levels + * to simulate a clamped LOD. + */ + if (t->mt) { + radeon_miptree_unreference(t->mt); + t->mt = 0; + t->validated = GL_FALSE; + } + break; + + case GL_DEPTH_TEXTURE_MODE: + if (!texObj->Image[0][texObj->BaseLevel]) + return; + if (texObj->Image[0][texObj->BaseLevel]->TexFormat->BaseFormat + == GL_DEPTH_COMPONENT) { + r600SetDepthTexMode(texObj); + break; + } else { + /* If the texture isn't a depth texture, changing this + * state won't cause any changes to the hardware. + * Don't force a flush of texture state. + */ + return; + } + + default: + return; + } +} + +static void r600DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) +{ + context_t* rmesa = R700_CONTEXT(ctx); + radeonTexObj* t = radeon_tex_obj(texObj); + + if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { + fprintf(stderr, "%s( %p (target = %s) )\n", __FUNCTION__, + (void *)texObj, + _mesa_lookup_enum_by_nr(texObj->Target)); + } + + if (rmesa) { + // fixme + int i; + //radeon_firevertices(&rmesa->radeon); + + for(i = 0; i < R700_MAX_TEXTURE_UNITS; ++i) + if (rmesa->hw.textures[i] == t) + rmesa->hw.textures[i] = 0; + } + + if (t->bo) { + radeon_bo_unref(t->bo); + t->bo = NULL; + } + + if (t->mt) { + radeon_miptree_unreference(t->mt); + t->mt = 0; + } + _mesa_delete_texture_object(ctx, texObj); +} + +/** + * Allocate a new texture object. + * Called via ctx->Driver.NewTextureObject. + * Note: this function will be called during context creation to + * allocate the default texture objects. + * Fixup MaxAnisotropy according to user preference. + */ +static struct gl_texture_object *r600NewTextureObject(GLcontext * ctx, + GLuint name, + GLenum target) +{ + context_t* rmesa = R700_CONTEXT(ctx); + radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj); + + + if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { + fprintf(stderr, "%s( %p (target = %s) )\n", __FUNCTION__, + t, _mesa_lookup_enum_by_nr(target)); + } + + _mesa_initialize_texture_object(&t->base, name, target); + t->base.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy; + + /* Initialize hardware state */ + r600SetTexDefaultState(t); + r600UpdateTexWrap(t); + r600SetTexFilter(t, t->base.MinFilter, t->base.MagFilter, t->base.MaxAnisotropy); + r600SetTexBorderColor(t, t->base.BorderColor); + + return &t->base; +} + +void r600InitTextureFuncs(struct dd_function_table *functions) +{ + /* Note: we only plug in the functions we implement in the driver + * since _mesa_init_driver_functions() was already called. + */ + functions->NewTextureImage = radeonNewTextureImage; + functions->FreeTexImageData = radeonFreeTexImageData; + functions->MapTexture = radeonMapTexture; + functions->UnmapTexture = radeonUnmapTexture; + + functions->ChooseTextureFormat = radeonChooseTextureFormat_mesa; + functions->TexImage1D = radeonTexImage1D; + functions->TexImage2D = radeonTexImage2D; + functions->TexImage3D = radeonTexImage3D; + functions->TexSubImage1D = radeonTexSubImage1D; + functions->TexSubImage2D = radeonTexSubImage2D; + functions->TexSubImage3D = radeonTexSubImage3D; + functions->GetTexImage = radeonGetTexImage; + functions->GetCompressedTexImage = radeonGetCompressedTexImage; + functions->NewTextureObject = r600NewTextureObject; + functions->DeleteTexture = r600DeleteTexture; + functions->IsTextureResident = driIsTextureResident; + + functions->TexParameter = r600TexParameter; + + functions->CompressedTexImage2D = radeonCompressedTexImage2D; + functions->CompressedTexSubImage2D = radeonCompressedTexSubImage2D; + + functions->GenerateMipmap = radeonGenerateMipmap; + + driInitTextureFormats(); +} diff --git a/src/mesa/drivers/dri/r600/r600_tex.h b/src/mesa/drivers/dri/r600/r600_tex.h new file mode 100644 index 0000000000..fb0e1a023e --- /dev/null +++ b/src/mesa/drivers/dri/r600/r600_tex.h @@ -0,0 +1,63 @@ +/* +Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + +The Weather Channel (TM) funded Tungsten Graphics to develop the +initial release of the Radeon 8500 driver under the XFree86 license. +This notice must be preserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Keith Whitwell + */ + +#ifndef __r600_TEX_H__ +#define __r600_TEX_H__ + +/* TODO : review this after texture load code. */ +#define R700_BLIT_WIDTH_BYTES 1024 +/* The BASE_ADDRESS and MIP_ADDRESS fields are 256-byte-aligned */ +#define R700_TEXTURE_ALIGNMENT_MASK 0x255 +/* Texel pitch is 8 alignment. */ +#define R700_TEXEL_PITCH_ALIGNMENT_MASK 0x7 + +#define R700_MAX_TEXTURE_UNITS 8 /* TODO : should be 16, lets make it work, review later */ + +extern void r600SetDepthTexMode(struct gl_texture_object *tObj); + +extern void r600SetTexBuffer(__DRIcontext *pDRICtx, GLint target, + __DRIdrawable *dPriv); + +extern void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, + GLint format, __DRIdrawable *dPriv); + +extern void r600SetTexOffset(__DRIcontext *pDRICtx, GLint texname, + unsigned long long offset, GLint depth, + GLuint pitch); + +extern GLboolean r600ValidateBuffers(GLcontext * ctx); + +extern void r600InitTextureFuncs(struct dd_function_table *functions); + +#endif /* __r600_TEX_H__ */ diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c new file mode 100644 index 0000000000..5a249d4f14 --- /dev/null +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -0,0 +1,795 @@ +/* +Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + +The Weather Channel (TM) funded Tungsten Graphics to develop the +initial release of the Radeon 8500 driver under the XFree86 license. +This notice must be preserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/** + * \file + * + * \author Keith Whitwell + * + * \todo Enable R300 texture tiling code? + */ + +#include "main/glheader.h" +#include "main/imports.h" +#include "main/context.h" +#include "main/macros.h" +#include "main/texformat.h" +#include "main/teximage.h" +#include "main/texobj.h" +#include "main/enums.h" + +#include "r600_context.h" +#include "r700_state.h" +#include "radeon_mipmap_tree.h" +#include "r600_tex.h" + +void r600UpdateTextureState(GLcontext * ctx) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + struct gl_texture_unit *texUnit; + struct radeon_tex_obj *t; + GLuint unit; + + for (unit = 0; unit < R700_MAX_TEXTURE_UNITS; unit++) { + texUnit = &ctx->Texture.Unit[unit]; + t = radeon_tex_obj(ctx->Texture.Unit[unit]._Current); + + if (texUnit->_ReallyEnabled) { + if (!t) + continue; + r700->textures[unit] = t; + } + } +} + +static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, GLuint mesa_format) +{ + radeonTexObj *t = radeon_tex_obj(tObj); + + t->SQ_TEX_RESOURCE4 &= ~( SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask + |SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask + |SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask + |SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask ); + + switch (mesa_format) /* This is mesa format. */ + { + case MESA_FORMAT_RGBA8888: + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGBA8888_REV: + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ARGB8888: + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ARGB8888_REV: + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGB888: + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGB565: + SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGB565_REV: + SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ARGB4444: + SETfield(t->SQ_TEX_RESOURCE1, FMT_4_4_4_4, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ARGB4444_REV: + SETfield(t->SQ_TEX_RESOURCE1, FMT_4_4_4_4, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ARGB1555: + SETfield(t->SQ_TEX_RESOURCE1, FMT_1_5_5_5, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ARGB1555_REV: + SETfield(t->SQ_TEX_RESOURCE1, FMT_1_5_5_5, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_AL88: + case MESA_FORMAT_AL88_REV: /* TODO : Check this. */ + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGB332: + SETfield(t->SQ_TEX_RESOURCE1, FMT_3_3_2, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_A8: /* ZERO, ZERO, ZERO, X */ + SETfield(t->SQ_TEX_RESOURCE1, FMT_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_L8: /* X, X, X, ONE */ + SETfield(t->SQ_TEX_RESOURCE1, FMT_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_I8: /* X, X, X, X */ + case MESA_FORMAT_CI8: + SETfield(t->SQ_TEX_RESOURCE1, FMT_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + /* YUV422 TODO conversion */ /* X, Y, Z, ONE, G8R8_G8B8 */ + /* + case MESA_FORMAT_YCBCR: + t->SQ_TEX_RESOURCE1.bitfields.DATA_FORMAT = ; + break; + */ + /* VUY422 TODO conversion */ /* X, Y, Z, ONE, G8R8_G8B8 */ + /* + case MESA_FORMAT_YCBCR_REV: + t->SQ_TEX_RESOURCE1.bitfields.DATA_FORMAT = ; + break; + */ + case MESA_FORMAT_RGB_DXT1: /* not supported yet */ + + break; + case MESA_FORMAT_RGBA_DXT1: /* not supported yet */ + + break; + case MESA_FORMAT_RGBA_DXT3: /* not supported yet */ + + break; + case MESA_FORMAT_RGBA_DXT5: /* not supported yet */ + + break; + case MESA_FORMAT_RGBA_FLOAT32: + SETfield(t->SQ_TEX_RESOURCE1, FMT_32_32_32_32_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGBA_FLOAT16: + SETfield(t->SQ_TEX_RESOURCE1, FMT_16_16_16_16_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGB_FLOAT32: /* X, Y, Z, ONE */ + SETfield(t->SQ_TEX_RESOURCE1, FMT_32_32_32_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGB_FLOAT16: + SETfield(t->SQ_TEX_RESOURCE1, FMT_16_16_16_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ALPHA_FLOAT32: /* ZERO, ZERO, ZERO, X */ + SETfield(t->SQ_TEX_RESOURCE1, FMT_32_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ALPHA_FLOAT16: /* ZERO, ZERO, ZERO, X */ + SETfield(t->SQ_TEX_RESOURCE1, FMT_16_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_LUMINANCE_FLOAT32: /* X, X, X, ONE */ + SETfield(t->SQ_TEX_RESOURCE1, FMT_32_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_LUMINANCE_FLOAT16: /* X, X, X, ONE */ + SETfield(t->SQ_TEX_RESOURCE1, FMT_16_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32: + SETfield(t->SQ_TEX_RESOURCE1, FMT_32_32_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16: + SETfield(t->SQ_TEX_RESOURCE1, FMT_16_16_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */ + SETfield(t->SQ_TEX_RESOURCE1, FMT_32_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */ + SETfield(t->SQ_TEX_RESOURCE1, FMT_16_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_Z16: + case MESA_FORMAT_Z24_S8: + case MESA_FORMAT_Z32: + switch (mesa_format) { + case MESA_FORMAT_Z16: + SETfield(t->SQ_TEX_RESOURCE1, FMT_16, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + break; + case MESA_FORMAT_Z24_S8: + SETfield(t->SQ_TEX_RESOURCE1, FMT_24_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + break; + case MESA_FORMAT_Z32: + SETfield(t->SQ_TEX_RESOURCE1, FMT_32, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + break; + }; + switch (tObj->DepthMode) { + case GL_LUMINANCE: /* X, X, X, ONE */ + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case GL_INTENSITY: /* X, X, X, X */ + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case GL_ALPHA: /* ZERO, ZERO, ZERO, X */ + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + default: + return GL_FALSE; + } + break; + default: + /* Not supported format */ + return GL_FALSE; + }; + + return GL_TRUE; +} + +void r600SetDepthTexMode(struct gl_texture_object *tObj) +{ + const GLuint *format; + radeonTexObjPtr t; + + if (!tObj) + return; + + t = radeon_tex_obj(tObj); + + r600GetTexFormat(tObj, tObj->Image[0][tObj->BaseLevel]->TexFormat->MesaFormat); + +} + +/** + * Compute the cached hardware register values for the given texture object. + * + * \param rmesa Context pointer + * \param t the r300 texture object + */ +static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *texObj) +{ + radeonTexObj *t = radeon_tex_obj(texObj); + const struct gl_texture_image *firstImage; + int firstlevel = t->mt ? t->mt->firstLevel : 0; + GLuint uTexelPitch; + + firstImage = t->base.Image[0][firstlevel]; + + if (!t->image_override) { + if (!r600GetTexFormat(texObj, firstImage->TexFormat->MesaFormat)) { + _mesa_problem(NULL, "unexpected texture format in %s", + __FUNCTION__); + return; + } + } + + if (t->image_override && t->bo) + return; + + switch (texObj->Target) { + case GL_TEXTURE_1D: + SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_1D, DIM_shift, DIM_mask); + SETfield(t->SQ_TEX_RESOURCE1, 0, TEX_DEPTH_shift, TEX_DEPTH_mask); + break; + case GL_TEXTURE_2D: + case GL_TEXTURE_RECTANGLE_NV: + SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_2D, DIM_shift, DIM_mask); + SETfield(t->SQ_TEX_RESOURCE1, 0, TEX_DEPTH_shift, TEX_DEPTH_mask); + break; + case GL_TEXTURE_3D: + SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_3D, DIM_shift, DIM_mask); + SETfield(t->SQ_TEX_RESOURCE1, firstImage->Depth - 1, // ??? + TEX_DEPTH_shift, TEX_DEPTH_mask); + break; + case GL_TEXTURE_CUBE_MAP: + SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_CUBEMAP, DIM_shift, DIM_mask); + SETfield(t->SQ_TEX_RESOURCE1, 0, TEX_DEPTH_shift, TEX_DEPTH_mask); + break; + default: + _mesa_problem(NULL, "unexpected texture target type in %s", __FUNCTION__); + return; + } + + uTexelPitch = (firstImage->Width + R700_TEXEL_PITCH_ALIGNMENT_MASK) + & ~R700_TEXEL_PITCH_ALIGNMENT_MASK; + + SETfield(t->SQ_TEX_RESOURCE0, (uTexelPitch/8)-1, PITCH_shift, PITCH_mask); + SETfield(t->SQ_TEX_RESOURCE0, firstImage->Width - 1, + TEX_WIDTH_shift, TEX_WIDTH_mask); + SETfield(t->SQ_TEX_RESOURCE1, firstImage->Height - 1, + TEX_HEIGHT_shift, TEX_HEIGHT_mask); + +} + +/** + * Ensure the given texture is ready for rendering. + * + * Mostly this means populating the texture object's mipmap tree. + */ +static GLboolean r600_validate_texture(GLcontext * ctx, struct gl_texture_object *texObj) +{ + context_t *rmesa = R700_CONTEXT(ctx); + radeonTexObj *t = radeon_tex_obj(texObj); + + if (!radeon_validate_texture_miptree(ctx, texObj)) + return GL_FALSE; + + /* Configure the hardware registers (more precisely, the cached version + * of the hardware registers). */ + setup_hardware_state(rmesa, texObj); + + t->validated = GL_TRUE; + return GL_TRUE; +} + +/** + * Ensure all enabled and complete textures are uploaded along with any buffers being used. + */ +GLboolean r600ValidateBuffers(GLcontext * ctx) +{ + context_t *rmesa = R700_CONTEXT(ctx); + struct radeon_renderbuffer *rrb; + int i; + + radeon_validate_reset_bos(&rmesa->radeon); + + rrb = radeon_get_colorbuffer(&rmesa->radeon); + /* color buffer */ + if (rrb && rrb->bo) { + radeon_validate_bo(&rmesa->radeon, rrb->bo, + 0, RADEON_GEM_DOMAIN_VRAM); + } + + /* depth buffer */ + rrb = radeon_get_depthbuffer(&rmesa->radeon); + if (rrb && rrb->bo) { + radeon_validate_bo(&rmesa->radeon, rrb->bo, + 0, RADEON_GEM_DOMAIN_VRAM); + } + + for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) { + radeonTexObj *t; + + if (!ctx->Texture.Unit[i]._ReallyEnabled) + continue; + + if (!r600_validate_texture(ctx, ctx->Texture.Unit[i]._Current)) { + _mesa_warning(ctx, + "failed to validate texture for unit %d.\n", + i); + } + t = radeon_tex_obj(ctx->Texture.Unit[i]._Current); + if (t->image_override && t->bo) + radeon_validate_bo(&rmesa->radeon, t->bo, + RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); + + else if (t->mt->bo) + radeon_validate_bo(&rmesa->radeon, t->mt->bo, + RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); + } + if (rmesa->radeon.dma.current) + radeon_validate_bo(&rmesa->radeon, rmesa->radeon.dma.current, RADEON_GEM_DOMAIN_GTT, 0); + + return radeon_revalidate_bos(ctx); +} + +void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname, + unsigned long long offset, GLint depth, GLuint pitch) +{ + context_t *rmesa = pDRICtx->driverPrivate; + struct gl_texture_object *tObj = + _mesa_lookup_texture(rmesa->radeon.glCtx, texname); + radeonTexObjPtr t = radeon_tex_obj(tObj); + uint32_t pitch_val; + + if (!tObj) + return; + + t->image_override = GL_TRUE; + + if (!offset) + return; + + t->bo = NULL; + t->override_offset = offset; + pitch_val = pitch; + switch (depth) { + case 32: + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + pitch_val /= 4; + break; + case 24: + default: + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + pitch_val /= 4; + break; + case 16: + SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + pitch_val /= 2; + break; + } + + pitch_val = (pitch_val + R700_TEXEL_PITCH_ALIGNMENT_MASK) + & ~R700_TEXEL_PITCH_ALIGNMENT_MASK; + SETfield(t->SQ_TEX_RESOURCE0, (pitch_val/8)-1, PITCH_shift, PITCH_mask); +} + +void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, __DRIdrawable *dPriv) +{ + struct gl_texture_unit *texUnit; + struct gl_texture_object *texObj; + struct gl_texture_image *texImage; + struct radeon_renderbuffer *rb; + radeon_texture_image *rImage; + radeonContextPtr radeon; + context_t *rmesa; + struct radeon_framebuffer *rfb; + radeonTexObjPtr t; + uint32_t pitch_val; + uint32_t internalFormat, type, format; + + type = GL_BGRA; + format = GL_UNSIGNED_BYTE; + internalFormat = (glx_texture_format == GLX_TEXTURE_FORMAT_RGB_EXT ? 3 : 4); + + radeon = pDRICtx->driverPrivate; + rmesa = pDRICtx->driverPrivate; + + rfb = dPriv->driverPrivate; + texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit]; + texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target); + texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0); + + rImage = get_radeon_texture_image(texImage); + t = radeon_tex_obj(texObj); + if (t == NULL) { + return; + } + + radeon_update_renderbuffers(pDRICtx, dPriv); + /* back & depth buffer are useless free them right away */ + rb = (void*)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = (void*)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = rfb->color_rb[0]; + if (rb->bo == NULL) { + /* Failed to BO for the buffer */ + return; + } + + _mesa_lock_texture(radeon->glCtx, texObj); + if (t->bo) { + radeon_bo_unref(t->bo); + t->bo = NULL; + } + if (rImage->bo) { + radeon_bo_unref(rImage->bo); + rImage->bo = NULL; + } + if (t->mt) { + radeon_miptree_unreference(t->mt); + t->mt = NULL; + } + if (rImage->mt) { + radeon_miptree_unreference(rImage->mt); + rImage->mt = NULL; + } + _mesa_init_teximage_fields(radeon->glCtx, target, texImage, + rb->width, rb->height, 1, 0, rb->cpp); + texImage->RowStride = rb->pitch / rb->cpp; + texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx, + internalFormat, + type, format, 0); + rImage->bo = rb->bo; + radeon_bo_ref(rImage->bo); + t->bo = rb->bo; + radeon_bo_ref(t->bo); + t->image_override = GL_TRUE; + t->override_offset = 0; + pitch_val = rb->pitch; + switch (rb->cpp) { + case 4: + if (glx_texture_format == GLX_TEXTURE_FORMAT_RGB_EXT) { + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + } else { + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + } + pitch_val /= 4; + break; + case 3: + default: + // FMT_8_8_8 ??? + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + pitch_val /= 4; + break; + case 2: + SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + pitch_val /= 2; + break; + } + + pitch_val = (pitch_val + R700_TEXEL_PITCH_ALIGNMENT_MASK) + & ~R700_TEXEL_PITCH_ALIGNMENT_MASK; + + SETfield(t->SQ_TEX_RESOURCE0, (pitch_val/8)-1, PITCH_shift, PITCH_mask); + SETfield(t->SQ_TEX_RESOURCE0, rb->width - 1, + TEX_WIDTH_shift, TEX_WIDTH_mask); + SETfield(t->SQ_TEX_RESOURCE1, rb->height - 1, + TEX_HEIGHT_shift, TEX_HEIGHT_mask); + + t->validated = GL_TRUE; + _mesa_unlock_texture(radeon->glCtx, texObj); + return; +} + +void r600SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) +{ + r600SetTexBuffer2(pDRICtx, target, GLX_TEXTURE_FORMAT_RGBA_EXT, dPriv); +} diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 4ace9c946b..ae380d83fc 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -32,7 +32,7 @@ #include "r600_cmdbuf.h" #include "r700_state.h" -#include "r700_tex.h" +#include "r600_tex.h" #include "r700_oglprog.h" #include "r700_fragprog.h" #include "r700_vertprog.h" diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h index fc38e96cb7..41654fd563 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.h +++ b/src/mesa/drivers/dri/r600/r700_chip.h @@ -148,6 +148,7 @@ union UINT_FLOAT float f32All; }; +#if 0 typedef struct _TEXTURE_STATE_STRUCT { union UINT_FLOAT SQ_TEX_RESOURCE0; @@ -173,6 +174,7 @@ typedef struct _R700_TEXTURE_STATES TEXTURE_STATE_STRUCT *textures[R700_TEXTURE_NUMBERUNITS]; SAMPLER_STATE_STRUCT *samplers[R700_TEXTURE_NUMBERUNITS]; } R700_TEXTURE_STATES; +#endif typedef struct _RENDER_TARGET_STATE_STRUCT { @@ -506,7 +508,7 @@ typedef struct _R700_CHIP_CONTEXT ContextState* pStateList; - R700_TEXTURE_STATES texture_states; + radeonTexObj* textures[R700_TEXTURE_NUMBERUNITS]; GLboolean bEnablePerspective; diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index a1ad929a67..b29a1aa918 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -44,10 +44,11 @@ #include "tnl/t_vertex.h" #include "tnl/t_pipeline.h" +#include "radeon_mipmap_tree.h" #include "r600_context.h" #include "r600_cmdbuf.h" -#include "r700_tex.h" +#include "r600_tex.h" #include "r700_vertprog.h" #include "r700_fragprog.h" @@ -131,36 +132,46 @@ static GLboolean r700SetupShaders(GLcontext * ctx) GLboolean r700SendTextureState(context_t *context) { unsigned int i; - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); -#if 0 /* to be enabled */ - for(i=0; itexture_states.textures[i] != 0) - { - R700_CMDBUF_CHECK_SPACE(9); - R700EP3 (context, IT_SET_RESOURCE, 7); - R700E32 (context, i * 7); - R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE0.u32All); - R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE1.u32All); - R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE2.u32All); - R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE3.u32All); - R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE4.u32All); - R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE5.u32All); - R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE6.u32All); - } + offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF}; + struct radeon_bo *bo = NULL; + BATCH_LOCALS(&context->radeon); - if(r700->texture_states.samplers[i] != 0) - { - R700_CMDBUF_CHECK_SPACE(5); - R700EP3 (context, IT_SET_SAMPLER, 3); - R700E32 (context, i * 3); // Base at 0x7000 - R700E32 (context, r700->texture_states.samplers[i]->SQ_TEX_SAMPLER0.u32All); - R700E32 (context, r700->texture_states.samplers[i]->SQ_TEX_SAMPLER1.u32All); - R700E32 (context, r700->texture_states.samplers[i]->SQ_TEX_SAMPLER2.u32All); - } + for (i=0; itextures[i]; + if (t) { + if (!t->image_override) + bo = t->mt->bo; + else + bo = t->bo; + if (bo) { + BEGIN_BATCH_NO_AUTOSTATE(14); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); + R600_OUT_BATCH(i * 7); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1); + R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2, + bo, + 0, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod); + R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3, + bo, + 0, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6); + + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3)); + R600_OUT_BATCH(i * 3); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2); + END_BATCH(); + COMMIT_BATCH(); + } + } } -#endif return GL_TRUE; } @@ -253,6 +264,9 @@ static GLboolean r700RunRender(GLcontext * ctx, fp->r700AsmCode.bR6xx = 1; } + if (!r600ValidateBuffers(ctx)) + return GL_TRUE; + r700Start3D(context); /* TODO : this is too much. */ r700SyncSurf(context); /* TODO : make it light. */ @@ -273,7 +287,7 @@ static GLboolean r700RunRender(GLcontext * ctx, /* flush TX */ //r700SyncSurf(context); /* */ - r700UpdateTextureState(context); + r600UpdateTextureState(ctx); r700SendTextureState(context); if(GL_FALSE == fp->translated) @@ -391,7 +405,7 @@ static GLboolean r700RunTCLRender(GLcontext * ctx, /*----------------------*/ /** * Ensure all enabled and complete textures are uploaded along with any buffers being used. */ - if(!r700ValidateBuffers(ctx)) + if(!r600ValidateBuffers(ctx)) { return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r600/r700_tex.c b/src/mesa/drivers/dri/r600/r700_tex.c deleted file mode 100644 index 21c9379729..0000000000 --- a/src/mesa/drivers/dri/r600/r700_tex.c +++ /dev/null @@ -1,1558 +0,0 @@ -/* - * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * Authors: - * Richard Li , - */ - -#include "main/glheader.h" -#include "main/imports.h" -#include "main/colormac.h" -#include "main/context.h" -#include "main/simple_list.h" -#include "main/texformat.h" -#include "main/texstore.h" -#include "texmem.h" -#include "main/teximage.h" -#include "main/texobj.h" -#include "main/macros.h" -#include "xmlpool.h" - -#include "radeon_common.h" - -#include "r600_context.h" - -#include "r700_state.h" - -#include "r700_tex.h" - - -/* to be enable */ -void r700SetTexBuffer(__DRIcontext *pDRICtx, GLint target, - __DRIdrawable *dPriv) -{ -} - -/* to be enable */ -void r700SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, - GLint format, __DRIdrawable *dPriv) -{ -} - -/* to be enable */ -void r700SetTexOffset(__DRIcontext *pDRICtx, GLint texname, - unsigned long long offset, GLint depth, - GLuint pitch) -{ -} - -static GLboolean r700GetTexFormat(struct gl_texture_object *tObj, GLuint mesa_format) -{ - r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; - - t->texture_state.SQ_TEX_RESOURCE4.u32All &= ~( SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask - |SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask - |SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask - |SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask ); - - switch (mesa_format) /* This is mesa format. */ - { - case MESA_FORMAT_RGBA8888: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8_8_8_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - - break; - case MESA_FORMAT_RGBA8888_REV: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8_8_8_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - - break; - case MESA_FORMAT_ARGB8888: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8_8_8_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_ARGB8888_REV: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8_8_8_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - - case MESA_FORMAT_RGB888: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8_8_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_RGB565: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_5_6_5, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_RGB565_REV: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_5_6_5, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_ARGB4444: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_4_4_4_4, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_ARGB4444_REV: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_4_4_4_4, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_ARGB1555: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_1_5_5_5, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_ARGB1555_REV: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_1_5_5_5, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_AL88: - case MESA_FORMAT_AL88_REV: /* TODO : Check this. */ - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_RGB332: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_3_3_2, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_A8: /* ZERO, ZERO, ZERO, X */ - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_L8: /* X, X, X, ONE */ - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_I8: /* X, X, X, X */ - case MESA_FORMAT_CI8: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - /* YUV422 TODO conversion */ /* X, Y, Z, ONE, G8R8_G8B8 */ - /* - case MESA_FORMAT_YCBCR: - t->texture_state.SQ_TEX_RESOURCE1.bitfields.DATA_FORMAT = ; - break; - */ - /* VUY422 TODO conversion */ /* X, Y, Z, ONE, G8R8_G8B8 */ - /* - case MESA_FORMAT_YCBCR_REV: - t->texture_state.SQ_TEX_RESOURCE1.bitfields.DATA_FORMAT = ; - break; - */ - case MESA_FORMAT_RGB_DXT1: /* not supported yet */ - - break; - case MESA_FORMAT_RGBA_DXT1: /* not supported yet */ - - break; - case MESA_FORMAT_RGBA_DXT3: /* not supported yet */ - - break; - case MESA_FORMAT_RGBA_DXT5: /* not supported yet */ - - break; - case MESA_FORMAT_RGBA_FLOAT32: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_32_32_32_32_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_RGBA_FLOAT16: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_16_16_16_16_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_RGB_FLOAT32: /* X, Y, Z, ONE */ - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_32_32_32_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_RGB_FLOAT16: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_16_16_16_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_ALPHA_FLOAT32: /* ZERO, ZERO, ZERO, X */ - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_32_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_ALPHA_FLOAT16: /* ZERO, ZERO, ZERO, X */ - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_16_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_LUMINANCE_FLOAT32: /* X, X, X, ONE */ - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_32_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_LUMINANCE_FLOAT16: /* X, X, X, ONE */ - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_16_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_32_32_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_16_16_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */ - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_32_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */ - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_16_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_Z16: - case MESA_FORMAT_Z24_S8: - case MESA_FORMAT_Z32: - switch (mesa_format) - { - case MESA_FORMAT_Z16: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_16, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - break; - case MESA_FORMAT_Z24_S8: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_24_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - break; - case MESA_FORMAT_Z32: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_32, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - }; - switch (tObj->DepthMode) - { - case GL_LUMINANCE: /* X, X, X, ONE */ - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case GL_INTENSITY: /* X, X, X, X */ - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case GL_ALPHA: /* ZERO, ZERO, ZERO, X */ - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - default: - return GL_FALSE; - } - break; - default: - /* Not supported format */ - return GL_FALSE; - }; - - return GL_TRUE; -} - -static void compute_tex_image_offset( - struct gl_texture_object *tObj, - GLuint face, - GLint level, - GLint* curOffset) -{ - r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; - const struct gl_texture_image* texImage; - GLuint blitWidth = R700_BLIT_WIDTH_BYTES; - GLuint texelBytes; - GLuint size; - GLuint pitch; - - texImage = tObj->Image[0][level + t->base.firstLevel]; - if (!texImage) - { - return; - } - - texelBytes = texImage->TexFormat->TexelBytes; - - pitch = (texImage->Width + R700_TEXEL_PITCH_ALIGNMENT_MASK) & ~R700_TEXEL_PITCH_ALIGNMENT_MASK; - - /* find image size in bytes */ - if (texImage->IsCompressed) - { - /* not supported yet */ - } - else if (tObj->Target == GL_TEXTURE_RECTANGLE_NV) - { - if( (ARRAY_LINEAR_ALIGNED << SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift) - == (t->texture_state.SQ_TEX_RESOURCE0.u32All & SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask) ) - { - pitch = (texImage->Width * texelBytes + 255) & ~255; - } - else - { - if(0 == level) - { - pitch = (pitch * texelBytes + 63) & ~63; - } - else - { - pitch = texImage->Width * texelBytes; - } - } - size = pitch * texImage->Height; - blitWidth = 64 / texelBytes; - pitch /= texelBytes; - } - else - { - if( (ARRAY_LINEAR_ALIGNED << SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift) - == (t->texture_state.SQ_TEX_RESOURCE0.u32All & SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask) ) - { - pitch = (texImage->Width * texelBytes + 255) & ~255; - } - else - { - if(0 == level) - { - pitch = (pitch * texelBytes + 31) & ~31; - } - else - { - pitch = texImage->Width * texelBytes; - } - } - size = pitch * texImage->Height * texImage->Depth; - blitWidth = MAX2(texImage->Width, 64 / texelBytes); - pitch /= texelBytes; - } - assert(size > 0); - - if( (0 == level) || (1 == level) ) /* 0 for BASE_ADDRESS, 1 for MIP_ADDRESS */ - { - *curOffset = (*curOffset + R700_TEXTURE_ALIGNMENT_MASK) & ~R700_TEXTURE_ALIGNMENT_MASK; - } - - if (texelBytes) - { - /* fix x and y coords up later together with offset */ - t->texel_pitch[face][level] = pitch; - t->level_offset[face][level] = *curOffset; - t->byte_per_texel = texelBytes; - t->src_width_in_pexel[face][level] = texImage->Width; - t->src_hight_in_pexel[face][level] = texImage->Height; - } - else - { - /* Do it like one byte texel. */ - pitch = (size + R700_TEXEL_PITCH_ALIGNMENT_MASK) & ~R700_TEXEL_PITCH_ALIGNMENT_MASK; - t->texel_pitch[face][level] = pitch; - t->level_offset[face][level] = *curOffset; - t->byte_per_texel = 1; - t->src_width_in_pexel[face][level] = size; - t->src_hight_in_pexel[face][level] = 1; - } - - *curOffset += size; -} - -void r700DestroyTexObj(context_t context, r700TexObjPtr t) -{ - /* TODO : nuke r700 chip texture and sampler pointer. */ - //int i; - - //for (i = 0; i < rmesa->ctx->Const.MaxTextureUnits; i++) - //{ - //if (rmesa->state.texture.unit[i].texobj == t) { - // rmesa->state.texture.unit[i].texobj = NULL; - //} - //} -} - -static void r700SetTexImages(context_t *context, struct gl_texture_object *tObj) -{ -#if 0 /* to be enabled */ - r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; - const struct gl_texture_image *baseImage = tObj->Image[0][tObj->BaseLevel]; - GLint curOffset; - GLint i, texelBytes; - GLint numLevels; - GLint log2Width, log2Height, log2Depth; - GLuint uTexelPitch; - - if (!t->image_override) - { - if(GL_FALSE == r700GetTexFormat(tObj, baseImage->TexFormat->MesaFormat) ) - { - _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__); - return; - } - } - - texelBytes = baseImage->TexFormat->TexelBytes; - - switch (tObj->Target) - { - case GL_TEXTURE_1D: - SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, SQ_TEX_DIM_1D, DIM_shift, DIM_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, 0, TEX_DEPTH_shift, TEX_DEPTH_mask); - break; - case GL_TEXTURE_2D: - case GL_TEXTURE_RECTANGLE_NV: - SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, SQ_TEX_DIM_2D, DIM_shift, DIM_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, 0, TEX_DEPTH_shift, TEX_DEPTH_mask); - break; - case GL_TEXTURE_3D: - SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, SQ_TEX_DIM_3D, DIM_shift, DIM_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, tObj->Image[0][t->base.firstLevel]->Depth - 1, - TEX_DEPTH_shift, TEX_DEPTH_mask); - break; - case GL_TEXTURE_CUBE_MAP: - SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, SQ_TEX_DIM_CUBEMAP, DIM_shift, DIM_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, 0, TEX_DEPTH_shift, TEX_DEPTH_mask); - break; - default: - _mesa_problem(NULL, "unexpected texture target type in %s", __FUNCTION__); - return; - } - - /* Compute which mipmap levels we really want to send to the hardware. - */ - driCalculateTextureFirstLastLevel((driTextureObject *) t); - log2Width = tObj->Image[0][t->base.firstLevel]->WidthLog2; - log2Height = tObj->Image[0][t->base.firstLevel]->HeightLog2; - log2Depth = tObj->Image[0][t->base.firstLevel]->DepthLog2; - - numLevels = t->base.lastLevel - t->base.firstLevel + 1; - - assert(numLevels <= RADEON_MAX_TEXTURE_LEVELS); - - /* Calculate mipmap offsets and dimensions for blitting (uploading) - * The idea is that we lay out the mipmap levels within a block of - * memory organized as a rectangle of width BLIT_WIDTH_BYTES. - */ - t->tile_bits = 0; - - curOffset = 0; - - if (tObj->Target == GL_TEXTURE_CUBE_MAP) - { - ASSERT(log2Width == log2Height); - - for(i = 0; i < numLevels; i++) - { - /* i is hw level */ - GLuint face; - for(face = 0; face < 6; face++) - { - compute_tex_image_offset(tObj, face, i, &curOffset); - } - } - } - else - { - for (i = 0; i < numLevels; i++) - { - /* i is hw level */ - compute_tex_image_offset(tObj, 0, i, &curOffset); - } - } - - /* Align the total size of texture memory block. - */ - t->base.totalSize = (curOffset + R700_TEXTURE_ALIGNMENT_MASK) & ~R700_TEXTURE_ALIGNMENT_MASK; - - t->pitch = 0; - - /* TODO : baseImage->IsCompressed, tObj->Target == GL_TEXTURE_RECTANGLE_NV */ - - uTexelPitch = (tObj->Image[0][t->base.firstLevel]->Width + R700_TEXEL_PITCH_ALIGNMENT_MASK) - & ~R700_TEXEL_PITCH_ALIGNMENT_MASK; - - SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, (uTexelPitch/8)-1, PITCH_shift, PITCH_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, tObj->Image[0][t->base.firstLevel]->Width - 1, - TEX_WIDTH_shift, TEX_WIDTH_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, tObj->Image[0][t->base.firstLevel]->Height - 1, - TEX_HEIGHT_shift, TEX_HEIGHT_mask); -#endif /* to be enabled */ -} - -static void r700UploadSubImage(context_t *context, - r700TexObjPtr t, - GLint hwlevel, /* relative level to first real level. */ - GLint x, - GLint y, - GLuint face) -{ -#if 0 /* to be enabled */ - struct gl_texture_image *texImage = NULL; - GLuint offset; - GLint imageWidth, imageHeight; - GLint ret; - const int level = hwlevel + t->base.firstLevel; - - unsigned char *pSrc; - - ASSERT(face < 6); - - /* Ensure we have a valid texture to upload */ - if ((hwlevel < 0) || (hwlevel >= RADEON_MAX_TEXTURE_LEVELS)) - { - _mesa_problem(NULL, "bad texture level in %s", __FUNCTION__); - return; - } - - texImage = t->base.tObj->Image[face][level]; - - if (!texImage) - { - return; - } - if (!texImage->Data) - { - return; - } - - if (t->base.tObj->Target == GL_TEXTURE_RECTANGLE_NV) - { - /* TODO : - assert(level == 0); - assert(hwlevel == 0); - - r300UploadRectSubImage(rmesa, t, texImage, x, y, width, height); - */ - return; - } - else if (texImage->IsClientData) - { - /* TODO : - r300UploadGARTClientSubImage(rmesa, t, texImage, hwlevel, x, y, - width, height); - */ - return; - } - - imageWidth = texImage->Width; - imageHeight = texImage->Height; - - /* use hwlevel for hwsurf. */ - offset = t->bufAddr + t->level_offset[face][hwlevel]; - - pSrc = (unsigned char*)(texImage->Data); - - (context->chipobj.LoadMemSurf)(context, - offset, /* gpu addr */ - t->texel_pitch[face][hwlevel], /* dst_pitch_in_pixel */ - t->src_width_in_pexel[face][hwlevel], /*src_width_in_pixel */ - t->src_hight_in_pexel[face][hwlevel], /* height */ - t->byte_per_texel, /* byte_per_pixel */ - pSrc); /* source data */ -#endif /* to be enabled */ -} - -int r700UploadTexImages(GLcontext * ctx, struct gl_texture_object *tObj, GLuint face) -{ -#if 0 /* to be enabled */ - context_t *context = R700_CONTEXT(ctx); - r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; - - int heap; - const int numLevels = t->base.lastLevel - t->base.firstLevel + 1; - - if (t->image_override) - { - return 0; - } - - if (t->base.totalSize == 0) - { - return 0; - } - /* TODO */ - /*LOCK_HARDWARE(&rmesa->radeon);*/ - - if (t->base.memBlock == NULL) - { - heap = RADEON_LOCAL_TEX_HEAP; - if( GL_FALSE == (context->chipobj.AllocMemSurf)(context, - &(t->base.memBlock), - &(t->base.heap), - &heap, /* prefered_heap, also return the actual heap used. */ - t->base.totalSize) ) - { - /* TODO */ - /* UNLOCK_HARDWARE(&rmesa->radeon); */ - return -1; - } - - /* Set the base offset of the texture image */ - t->bufAddr = context->screen->texOffset[heap] + t->base.memBlock->ofs; - t->offset = t->bufAddr; - - /* - if (!(t->base.tObj->Image[0][0]->IsClientData)) - { - t->offset |= t->tile_bits; - } - */ - } - - /* Let the world know we've used this memory recently. - */ - driUpdateTextureLRU((driTextureObject *) t); - - /* TODO */ - /* UNLOCK_HARDWARE(&rmesa->radeon); */ - - /* Upload any images that are new */ - if (t->my_dirty_images[face]) - { - int i; - for(i = 0; i < numLevels; i++) - { - if( (t->my_dirty_images[face] & (1 << (i + t->base.firstLevel))) !=0) - { - r700UploadSubImage(context, - t, - i, /* i is hw level */ - 0, - 0, - face); - } - } - t->base.dirty_images[face] = 0; - t->my_dirty_images[face] = 0; - } - - /* TODO : 3D, CUBE */ - t->texture_state.SQ_TEX_RESOURCE2.u32All = t->bufAddr / 256; - if( (t->base.lastLevel - t->base.firstLevel) > 0 ) - { - t->texture_state.SQ_TEX_RESOURCE3.u32All = (t->bufAddr + t->level_offset[0][1]) / 256; /* MIP_ADDRESS */ - - SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, t->base.firstLevel, BASE_LEVEL_shift, BASE_LEVEL_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE5.u32All, t->base.lastLevel, LAST_LEVEL_shift, LAST_LEVEL_mask); - } -#endif /* to be enabled */ - return 0; -} - -static GLboolean r700EnableTexture2D(GLcontext * ctx, int unit) -{ - context_t *context = R700_CONTEXT(ctx); - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - struct gl_texture_object *tObj = texUnit->_Current; - r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; - - ASSERT(tObj->Target == GL_TEXTURE_2D || tObj->Target == GL_TEXTURE_1D); - - if (t->base.dirty_images[0]) - { - r700SetTexImages(context, tObj); - r700UploadTexImages(ctx, tObj, 0); - if (!t->base.memBlock && !t->image_override) - { - return GL_FALSE; - } - } - return GL_TRUE; -} - -/* try to find a format which will only need a memcopy */ -static const struct gl_texture_format *r700Choose8888TexFormat(GLenum srcFormat, - GLenum srcType) -{ - struct gl_texture_format * gtfRet; - - const GLuint ui = 1; - const GLubyte littleEndian = *((const GLubyte *)&ui); - - if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8) || - (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && !littleEndian) || - (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || - (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && littleEndian)) - { - gtfRet = &_mesa_texformat_rgba8888; - } - else if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || - (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && littleEndian) || - (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8) || - (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && !littleEndian)) - { - gtfRet = &_mesa_texformat_rgba8888_rev; - } - else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && !littleEndian) || - srcType == GL_UNSIGNED_INT_8_8_8_8)) - { - gtfRet = &_mesa_texformat_argb8888_rev; - } - else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && littleEndian) || - srcType == GL_UNSIGNED_INT_8_8_8_8_REV)) - { - gtfRet = &_mesa_texformat_argb8888; - } - else - { - gtfRet = _dri_texformat_argb8888; - } - - return gtfRet; -} - -static r700TexObjPtr r700AllocTexObj(struct gl_texture_object *texObj) -{ - r700TexObjPtr t; - - t = CALLOC_STRUCT(r700_tex_obj); - texObj->DriverData = t; - if (t != NULL) - { -#if 0 /* to be enabled */ - /* Initialize non-image-dependent parts of the state: - */ - t->base.tObj = texObj; - t->border_fallback = GL_FALSE; - - make_empty_list(&t->base); - - /* Init text object to default states. */ - t->texture_state.SQ_TEX_RESOURCE0.u32All = 0; - SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, SQ_TEX_DIM_2D, DIM_shift, DIM_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, ARRAY_LINEAR_GENERAL, - SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift, SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask); - CLEARbit(t->texture_state.SQ_TEX_RESOURCE0.u32All, TILE_TYPE_bit); - - t->texture_state.SQ_TEX_RESOURCE1.u32All = 0; - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8_8_8_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE2.u32All = 0; - t->texture_state.SQ_TEX_RESOURCE3.u32All = 0; - - t->texture_state.SQ_TEX_RESOURCE4.u32All = 0; - SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_FORMAT_COMP_UNSIGNED, - FORMAT_COMP_X_shift, FORMAT_COMP_X_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_FORMAT_COMP_UNSIGNED, - FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_FORMAT_COMP_UNSIGNED, - FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_FORMAT_COMP_UNSIGNED, - FORMAT_COMP_W_shift, FORMAT_COMP_W_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_NUM_FORMAT_NORM, - SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift, SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_mask); - CLEARbit(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit); - CLEARbit(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit); - SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_ENDIAN_NONE, - SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift, SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, 1, REQUEST_SIZE_shift, REQUEST_SIZE_mask); - t->texture_state.SQ_TEX_RESOURCE4.u32All |= SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift - |SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift - |SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift - |SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift; - SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, 0, BASE_LEVEL_shift, BASE_LEVEL_mask); /* mip-maps */ - - t->texture_state.SQ_TEX_RESOURCE5.u32All = 0; - - t->texture_state.SQ_TEX_RESOURCE6.u32All = 0; - - SETfield(t->texture_state.SQ_TEX_RESOURCE6.u32All, SQ_TEX_VTX_VALID_TEXTURE, - SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask); - - /* Initialize sampler registers */ - t->sampler_state.SQ_TEX_SAMPLER0.u32All = 0; - t->sampler_state.SQ_TEX_SAMPLER0.u32All |= - SQ_TEX_WRAP << SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift - |SQ_TEX_WRAP << CLAMP_Y_shift - |SQ_TEX_WRAP << CLAMP_Z_shift - |SQ_TEX_XY_FILTER_POINT << XY_MAG_FILTER_shift - |SQ_TEX_XY_FILTER_POINT << XY_MIN_FILTER_shift - |SQ_TEX_Z_FILTER_NONE << Z_FILTER_shift - |SQ_TEX_Z_FILTER_NONE << MIP_FILTER_shift - |SQ_TEX_BORDER_COLOR_TRANS_BLACK << BORDER_COLOR_TYPE_shift; - - t->sampler_state.SQ_TEX_SAMPLER1.u32All = 0x7FF << MAX_LOD_shift; - - t->sampler_state.SQ_TEX_SAMPLER2.u32All = 0; - SETbit(t->sampler_state.SQ_TEX_SAMPLER2.u32All, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit); -#endif /* to be enabled */ - } - - return t; -} - -static GLboolean -r700ValidateClientStorage(GLcontext * ctx, GLenum target, - GLint internalFormat, - GLint srcWidth, GLint srcHeight, - GLenum format, GLenum type, const void *pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - if (!ctx->Unpack.ClientStorage) - { - return 0; - } - - if (ctx->_ImageTransferState || - texImage->IsCompressed || texObj->GenerateMipmap) - { - return 0; - } - - /* This list is incomplete, may be different on ppc??? - */ - switch (internalFormat) - { - case GL_RGBA: - if (format == GL_BGRA && type == GL_UNSIGNED_INT_8_8_8_8_REV) - { - texImage->TexFormat = _dri_texformat_argb8888; - } - else - { - return 0; - } - break; - - case GL_RGB: - if (format == GL_RGB && type == GL_UNSIGNED_SHORT_5_6_5) - { - texImage->TexFormat = _dri_texformat_rgb565; - } - else - { - return 0; - } - break; - - case GL_YCBCR_MESA: - if (format == GL_YCBCR_MESA && - type == GL_UNSIGNED_SHORT_8_8_REV_APPLE) - { - texImage->TexFormat = &_mesa_texformat_ycbcr_rev; - } - else if( format == GL_YCBCR_MESA && - (type == GL_UNSIGNED_SHORT_8_8_APPLE || type == GL_UNSIGNED_BYTE)) - { - texImage->TexFormat = &_mesa_texformat_ycbcr; - } - else - { - return 0; - } - break; - - default: - return 0; - } - - /* Could deal with these packing issues, but currently don't: - */ - if (packing->SkipPixels || - packing->SkipRows || packing->SwapBytes || packing->LsbFirst) - { - return 0; - } - - GLint srcRowStride = _mesa_image_row_stride(packing, srcWidth, format, type); - - /* Have validated that _mesa_transfer_teximage would be a straight - * memcpy at this point. NOTE: future calls to TexSubImage will - * overwrite the client data. This is explicitly mentioned in the - * extension spec. - */ - texImage->Data = (void *)pixels; - texImage->IsClientData = GL_TRUE; - texImage->RowStride = srcRowStride / texImage->TexFormat->TexelBytes; - - return 1; -} - -static void r700TexImage1D(GLcontext * ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint border, - GLenum format, GLenum type, const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ -} - -static void r700TexImage2D(GLcontext * ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint height, GLint border, - GLenum format, GLenum type, const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ -#if 0 /* to be enabled */ - r700TexObjPtr r700t = (r700TexObjPtr) texObj->DriverData; - - driTextureObject *t = (driTextureObject *) texObj->DriverData; - GLuint face; - - /* which cube face or ordinary 2D image */ - switch (target) - { - case GL_TEXTURE_CUBE_MAP_POSITIVE_X: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_X: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Y: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Z: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z: - face = (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X; - ASSERT(face < 6); - break; - default: - face = 0; - } - - if (t != NULL) - { - driSwapOutTextureObject(t); - } - else - { - t = (driTextureObject *) r700AllocTexObj(texObj); - if (!t) - { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage2D"); - return; - } - } - - texImage->IsClientData = GL_FALSE; - - if (r700ValidateClientStorage(ctx, target, - internalFormat, - width, height, - format, type, pixels, - packing, texObj, texImage)) - { - /* client maintained surface */ - } - else - { - /* Normal path: copy (to cached memory) and eventually upload - * via another copy to GART memory and then a blit... Could - * eliminate one copy by going straight to (permanent) GART. - * - * Note, this will call r700ChooseTextureFormat. - */ - _mesa_store_teximage2d(ctx, target, level, internalFormat, - width, height, border, format, type, - pixels, &ctx->Unpack, texObj, texImage); - - t->dirty_images[face] |= (1 << level); - - /* mesa dirty_images is not correct, so use own one for now, review it later. */ - r700t->my_dirty_images[face] |= (1 << level); - } -#endif /* to be enabled */ -} - -static void r700TexImage3D(GLcontext * ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint height, GLint depth, - GLint border, - GLenum format, GLenum type, const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ -} - -static void r700TexSubImage1D(GLcontext * ctx, GLenum target, GLint level, - GLint xoffset, - GLsizei width, - GLenum format, GLenum type, - const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - -} - -static void r700TexSubImage2D(GLcontext * ctx, GLenum target, GLint level, - GLint xoffset, GLint yoffset, - GLsizei width, GLsizei height, - GLenum format, GLenum type, - const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ -} - -static void r700TexSubImage3D(GLcontext * ctx, GLenum target, GLint level, - GLint xoffset, GLint yoffset, GLint zoffset, - GLsizei width, GLsizei height, GLsizei depth, - GLenum format, GLenum type, - const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ -} - -/** - * Allocate a new texture object. - * Called via ctx->Driver.NewTextureObject. - * Note: this function will be called during context creation to - * allocate the default texture objects. - * Note: we could use containment here to 'derive' the driver-specific - * texture object from the core mesa gl_texture_object. Not done at this time. - */ -static struct gl_texture_object *r700NewTextureObject(GLcontext * ctx, - GLuint name, - GLenum target) -{ - context_t *context = R700_CONTEXT(ctx); - - struct gl_texture_object *obj; - - obj = _mesa_new_texture_object(ctx, name, target); - if (!obj) - { - return NULL; - } - - //obj->MaxAnisotropy = context->initialMaxAnisotropy; - - r700AllocTexObj(obj); - - return obj; -} - -static void r700BindTexture(GLcontext * ctx, GLenum target, - struct gl_texture_object *texObj) -{ - if ((target == GL_TEXTURE_1D) - || (target == GL_TEXTURE_2D) - || (target == GL_TEXTURE_3D) - || (target == GL_TEXTURE_CUBE_MAP) - || (target == GL_TEXTURE_RECTANGLE_NV)) - { - assert(texObj->DriverData != NULL); - } -} - -static void r700DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) -{ -} - -#if 0 /* to be enabled */ -static void r700SetTexMinFilter(r700TexObjPtr t, GLenum minf) -{ - switch (minf) - { - case GL_NEAREST: - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Point, - XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_MipFilter_None, - MIP_FILTER_shift, MIP_FILTER_mask); - break; - case GL_LINEAR: - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Linear, - XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_MipFilter_None, - MIP_FILTER_shift, MIP_FILTER_mask); - break; - case GL_NEAREST_MIPMAP_NEAREST: - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Point, - XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_MipFilter_Point, - MIP_FILTER_shift, MIP_FILTER_mask); - break; - case GL_LINEAR_MIPMAP_NEAREST: - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Linear, - XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_MipFilter_Point, - MIP_FILTER_shift, MIP_FILTER_mask); - break; - case GL_NEAREST_MIPMAP_LINEAR: - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Point, - XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_MipFilter_Linear, - MIP_FILTER_shift, MIP_FILTER_mask); - break; - case GL_LINEAR_MIPMAP_LINEAR: - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Linear, - XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_MipFilter_Linear, - MIP_FILTER_shift, MIP_FILTER_mask); - break; - default: - /* no case */ - break; - } -} - -static void r700SetTexMagFilter(r700TexObjPtr t, GLenum magf) -{ - switch(magf) - { - case GL_NEAREST: - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Point, - XY_MAG_FILTER_shift, XY_MAG_FILTER_mask); - - break; - case GL_LINEAR: - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Linear, - XY_MAG_FILTER_shift, XY_MAG_FILTER_mask); - - break; - default: - break; - } -} - -static unsigned int r700GetWrapMode(GLenum wrapmode) -{ - switch(wrapmode) - { - case GL_REPEAT: - return SQ_TEX_WRAP; - case GL_CLAMP: - return SQ_TEX_CLAMP_HALF_BORDER; - case GL_CLAMP_TO_EDGE: - return SQ_TEX_CLAMP_LAST_TEXEL; - case GL_CLAMP_TO_BORDER: - return SQ_TEX_CLAMP_BORDER; - case GL_MIRRORED_REPEAT: - return SQ_TEX_MIRROR_ONCE_HALF_BORDER; - case GL_MIRROR_CLAMP_EXT: - return SQ_TEX_MIRROR; - case GL_MIRROR_CLAMP_TO_EDGE_EXT: - return SQ_TEX_MIRROR_ONCE_BORDER; - case GL_MIRROR_CLAMP_TO_BORDER_EXT: - return SQ_TEX_MIRROR_ONCE_LAST_TEXEL; - default: - _mesa_problem(NULL, "bad wrap mode in %s", __FUNCTION__); - return 0; - } -} -#endif /* to be enabled */ - -static void r700TexParameter(GLcontext * ctx, GLenum target, - struct gl_texture_object *texObj, - GLenum pname, const GLfloat * params) -{ - r700TexObjPtr t = (r700TexObjPtr) texObj->DriverData; -#if 0 /* to be enabled */ - switch (pname) - { - case GL_TEXTURE_MIN_FILTER: - r700SetTexMinFilter(t, texObj->MinFilter); - break; - case GL_TEXTURE_MAG_FILTER: - r700SetTexMagFilter(t, texObj->MagFilter); - break; - case GL_TEXTURE_MAX_ANISOTROPY_EXT: - - r700SetTexMinFilter(t, texObj->MinFilter); - r700SetTexMagFilter(t, texObj->MagFilter); - - break; - - case GL_TEXTURE_WRAP_S: - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, r700GetWrapMode(texObj->WrapS), - SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift, SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask); - break; - case GL_TEXTURE_WRAP_T: - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, r700GetWrapMode(texObj->WrapT), - CLAMP_Y_shift, CLAMP_Y_mask); - break; - case GL_TEXTURE_WRAP_R: - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, r700GetWrapMode(texObj->WrapR), - CLAMP_Z_shift, CLAMP_Z_mask); - break; - - case GL_TEXTURE_BORDER_COLOR: - /* TODO : set border color regs before rendering. */ - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, SQ_TEX_BORDER_COLOR_REGISTER, - BORDER_COLOR_TYPE_shift, BORDER_COLOR_TYPE_mask); - break; - - case GL_TEXTURE_BASE_LEVEL: - case GL_TEXTURE_MAX_LEVEL: - case GL_TEXTURE_MIN_LOD: - case GL_TEXTURE_MAX_LOD: - /* TODO : we do support this, add it later. */ - driSwapOutTextureObject((driTextureObject *) t); - break; - - case GL_DEPTH_TEXTURE_MODE: - if (!texObj->Image[0][texObj->BaseLevel]) - { - return; - } - if (texObj->Image[0][texObj->BaseLevel]->TexFormat->BaseFormat - == GL_DEPTH_COMPONENT) - { - /* TODO : r700SetDepthTexMode(texObj); */ - break; - } - else - { - /* If not depth texture, just return. */ - return; - } - - default: - return; - } -#endif /* to be enabled */ -} - -static void r700CompressedTexImage2D(GLcontext * ctx, GLenum target, - GLint level, GLint internalFormat, - GLint width, GLint height, GLint border, - GLsizei imageSize, const GLvoid * data, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ -} - -static void r700CompressedTexSubImage2D(GLcontext * ctx, GLenum target, - GLint level, GLint xoffset, - GLint yoffset, GLsizei width, - GLsizei height, GLenum format, - GLsizei imageSize, const GLvoid * data, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ -} - -static GLboolean r700UpdateTextureUnit(GLcontext * ctx, int unit) -{ - return GL_TRUE; -} - -static GLboolean r700EnableTextureRect(GLcontext * ctx, int unit) -{ - return GL_TRUE; -} - -static GLboolean r700EnableTexture3D(GLcontext * ctx, int unit) -{ - return GL_TRUE; -} - -static GLboolean r700EnableTextureCube(GLcontext * ctx, int unit) -{ - return GL_TRUE; -} - -static GLboolean r700UpdateTexture(GLcontext * ctx, int unit) -{ -#if 0 /* to be enabled */ - context_t *context = R700_CONTEXT(ctx); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); - - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - struct gl_texture_object *tObj = texUnit->_Current; - r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; - - if( r700->texture_states.textures[unit] != &(t->texture_state) ) - { - if(NULL != r700->texture_states.textures[unit]) - { /* there is an old one. */ - } - - r700->texture_states.textures[unit] = &(t->texture_state); - r700->texture_states.samplers[unit] = &(t->sampler_state); - driUpdateTextureLRU((driTextureObject *) t); /* XXX: should be locked! */ - } -#endif /* to be enabled */ - - return GL_TRUE; -} - -void r700UpdateTextureState(context_t * context) -{ -#if 0 /* to be enabled */ - GLboolean bRet; - GLuint unit; - GLcontext * ctx = context->ctx; - struct gl_texture_unit *texUnit; - - for (unit = 0; unit < 8; unit++) - { - texUnit = &ctx->Texture.Unit[unit]; - - if (texUnit->_ReallyEnabled & (TEXTURE_RECT_BIT)) - { - bRet = (r700EnableTextureRect(ctx, unit) && - r700UpdateTexture(ctx, unit)); - } - else if (texUnit->_ReallyEnabled & (TEXTURE_1D_BIT | TEXTURE_2D_BIT)) - { - bRet = (r700EnableTexture2D(ctx, unit) && - r700UpdateTexture(ctx, unit)); - } - else if (texUnit->_ReallyEnabled & (TEXTURE_3D_BIT)) - { - bRet = (r700EnableTexture3D(ctx, unit) && - r700UpdateTexture(ctx, unit)); - } - else if (texUnit->_ReallyEnabled & (TEXTURE_CUBE_BIT)) - { - bRet = (r700EnableTextureCube(ctx, unit) && - r700UpdateTexture(ctx, unit)); - } - else if (texUnit->_ReallyEnabled) - { - bRet = GL_FALSE; - } - else - { - bRet = GL_TRUE; - } - - if (!bRet) - { - _mesa_warning(ctx, "failed to update texture state for unit %d.\n", unit); - } - } -#endif /* to be enabled */ -} - -/** - * Ensure all enabled and complete textures are uploaded along with any buffers being used. - */ -GLboolean r700ValidateBuffers(GLcontext * ctx) -{ - /* TODO */ - - return radeon_revalidate_bos(ctx); -} - -void r700InitTextureFuncs(struct dd_function_table *functions) -{ - /* Note: we only plug in the functions we implement in the driver - * since _mesa_init_driver_functions() was already called. - */ - functions->ChooseTextureFormat = radeonChooseTextureFormat_mesa; - functions->TexImage1D = r700TexImage1D; - functions->TexImage2D = r700TexImage2D; - functions->TexImage3D = r700TexImage3D; - functions->TexSubImage1D = r700TexSubImage1D; - functions->TexSubImage2D = r700TexSubImage2D; - functions->TexSubImage3D = r700TexSubImage3D; - functions->NewTextureObject = r700NewTextureObject; - functions->BindTexture = r700BindTexture; - functions->DeleteTexture = r700DeleteTexture; - functions->IsTextureResident = driIsTextureResident; - - functions->TexParameter = r700TexParameter; - - functions->CompressedTexImage2D = r700CompressedTexImage2D; - functions->CompressedTexSubImage2D = r700CompressedTexSubImage2D; - - driInitTextureFormats(); -} - - diff --git a/src/mesa/drivers/dri/r600/r700_tex.h b/src/mesa/drivers/dri/r600/r700_tex.h deleted file mode 100644 index e322bbc47d..0000000000 --- a/src/mesa/drivers/dri/r600/r700_tex.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * Authors: - * Richard Li , - */ - -#ifndef __r700_TEX_H__ -#define __r700_TEX_H__ - -#include "texmem.h" - -#include "r700_chip.h" - -/* TODO : review this after texture load code. */ -#define R700_BLIT_WIDTH_BYTES 1024 -/* The BASE_ADDRESS and MIP_ADDRESS fields are 256-byte-aligned */ -#define R700_TEXTURE_ALIGNMENT_MASK 0x255 -/* Texel pitch is 8 alignment. */ -#define R700_TEXEL_PITCH_ALIGNMENT_MASK 0x7 - -#define R700_MAX_TEXTURE_UNITS 8 /* TODO : should be 16, lets make it work, review later */ - -typedef struct r700_tex_obj r700TexObj, *r700TexObjPtr; - -/* Texture object in locally shared texture space. - */ -struct r700_tex_obj -{ - driTextureObject base; - - /* r300 tex obj */ - GLuint bufAddr; - GLboolean image_override; - GLuint pitch; - GLuint filter; - GLuint filter_1; - GLuint pitch_reg; - GLuint size; - GLuint format; - GLuint offset; - GLuint unknown4; - GLuint unknown5; - GLboolean border_fallback; - GLuint tile_bits; - - /* r700 texture states */ - TEXTURE_STATE_STRUCT texture_state; - SAMPLER_STATE_STRUCT sampler_state; - - GLuint texel_pitch[6][RADEON_MAX_TEXTURE_LEVELS]; - GLuint level_offset[6][RADEON_MAX_TEXTURE_LEVELS]; - GLuint byte_per_texel; - GLuint src_width_in_pexel[6][RADEON_MAX_TEXTURE_LEVELS]; - GLuint src_hight_in_pexel[6][RADEON_MAX_TEXTURE_LEVELS]; - - GLuint my_dirty_images[6]; /* TODO : review */ -}; - -extern void r700SetTexBuffer(__DRIcontext *pDRICtx, GLint target, - __DRIdrawable *dPriv); - -extern void r700SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, - GLint format, __DRIdrawable *dPriv); - -extern void r700SetTexOffset(__DRIcontext *pDRICtx, GLint texname, - unsigned long long offset, GLint depth, - GLuint pitch); - -extern GLuint r700GetTexObjSize(void); -extern void r700UpdateTextureState(context_t * context); - -extern void r700SetTexOffset(__DRIcontext *pDRICtx, - GLint texname, - unsigned long long offset, - GLint depth, - GLuint pitch); - -extern void r700DestroyTexObj(context_t rmesa, r700TexObjPtr t); - -extern GLboolean r700ValidateBuffers(GLcontext * ctx); - -extern void r700InitTextureFuncs(struct dd_function_table *functions); - -#endif /* __r700_TEX_H__ */ diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index 96bc685876..43e705ee59 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -227,6 +227,19 @@ struct radeon_tex_obj { GLuint pp_txfilter_1; /* r300 */ + /* r700 texture states */ + GLuint SQ_TEX_RESOURCE0; + GLuint SQ_TEX_RESOURCE1; + GLuint SQ_TEX_RESOURCE2; + GLuint SQ_TEX_RESOURCE3; + GLuint SQ_TEX_RESOURCE4; + GLuint SQ_TEX_RESOURCE5; + GLuint SQ_TEX_RESOURCE6; + + GLuint SQ_TEX_SAMPLER0; + GLuint SQ_TEX_SAMPLER1; + GLuint SQ_TEX_SAMPLER2; + GLboolean border_fallback; diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index e23d53c7a1..355fa8683a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -62,7 +62,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) #include "r600_context.h" #include "r700_driconf.h" /* +r6/r7 */ -#include "r700_tex.h" /* +r6/r7 */ +#include "r600_tex.h" /* +r6/r7 */ #endif #include "utils.h" @@ -405,13 +405,13 @@ static const __DRItexBufferExtension r300TexBufferExtension = { #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) static const __DRItexOffsetExtension r600texOffsetExtension = { { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, - r700SetTexOffset, /* +r6/r7 */ + r600SetTexOffset, /* +r6/r7 */ }; static const __DRItexBufferExtension r600TexBufferExtension = { { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, - r700SetTexBuffer, /* +r6/r7 */ - r700SetTexBuffer2, /* +r6/r7 */ + r600SetTexBuffer, /* +r6/r7 */ + r600SetTexBuffer2, /* +r6/r7 */ }; #endif -- cgit v1.2.3 From f74d1c26acaacf688545ecc1ddb996a02e991ccb Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 7 Jul 2009 02:12:38 -0400 Subject: r6xx/r7xx: add sw blit for tex upload Can be used for buffer swap as well. --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 17 ++++++ src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 85 ++++++++++++++------------ 2 files changed, 64 insertions(+), 38 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 4609e86bb9..9f26b257d0 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -645,3 +645,20 @@ void r600InitCmdBuf(context_t *r600) /* from rcommonInitCmdBuf */ } } } + +void r600_sw_blit(char *srcp, int src_pitch, char *dstp, int dst_pitch, + int x, int y, int w, int h, int cpp) +{ + char *src = srcp; + char *dst = dstp; + + src += (y * src_pitch) + (x * cpp); + dst += (y * dst_pitch) + (x * cpp); + + while (h--) { + memcpy(dst, src, w * cpp); + src += src_pitch; + dst += dst_pitch; + } +} + diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index 0b0a2aa2c4..276926ce69 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -609,44 +609,53 @@ static int bo_vram_validate(struct radeon_bo *bo, driUpdateTextureLRU(&bo_legacy->tobj->base); if (bo_legacy->dirty || bo_legacy->tobj->base.dirty_images[0]) { - /* Copy to VRAM using a blit. - * All memory is 4K aligned. We're using 1024 pixels wide blits. - */ - drm_radeon_texture_t tex; - drm_radeon_tex_image_t tmp; - int ret; - - tex.offset = bo_legacy->offset; - tex.image = &tmp; - assert(!(tex.offset & 1023)); - - tmp.x = 0; - tmp.y = 0; - if (bo->size < 4096) { - tmp.width = (bo->size + 3) / 4; - tmp.height = 1; - } else { - tmp.width = 1024; - tmp.height = (bo->size + 4095) / 4096; - } - tmp.data = bo_legacy->ptr; - tex.format = RADEON_TXFORMAT_ARGB8888; - tex.width = tmp.width; - tex.height = tmp.height; - tex.pitch = MAX2(tmp.width / 16, 1); - do { - ret = drmCommandWriteRead(bo->bom->fd, - DRM_RADEON_TEXTURE, - &tex, - sizeof(drm_radeon_texture_t)); - if (ret) { - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "DRM_RADEON_TEXTURE: again!\n"); - usleep(1); - } - } while (ret == -EAGAIN); - bo_legacy->dirty = 0; - bo_legacy->tobj->base.dirty_images[0] = 0; + if (IS_R600_CLASS(boml->screen)) { + char *src = bo_legacy->ptr; + char *dst = (char *) boml->screen->driScreen->pFB + + (bo_legacy->offset - boml->fb_location); + + /* FIXME: alignment, pitch, etc. */ + r600_sw_blit(src, 0, dst, 0, 0, 0, 1, 1, bo->size); + } else { + /* Copy to VRAM using a blit. + * All memory is 4K aligned. We're using 1024 pixels wide blits. + */ + drm_radeon_texture_t tex; + drm_radeon_tex_image_t tmp; + int ret; + + tex.offset = bo_legacy->offset; + tex.image = &tmp; + assert(!(tex.offset & 1023)); + + tmp.x = 0; + tmp.y = 0; + if (bo->size < 4096) { + tmp.width = (bo->size + 3) / 4; + tmp.height = 1; + } else { + tmp.width = 1024; + tmp.height = (bo->size + 4095) / 4096; + } + tmp.data = bo_legacy->ptr; + tex.format = RADEON_TXFORMAT_ARGB8888; + tex.width = tmp.width; + tex.height = tmp.height; + tex.pitch = MAX2(tmp.width / 16, 1); + do { + ret = drmCommandWriteRead(bo->bom->fd, + DRM_RADEON_TEXTURE, + &tex, + sizeof(drm_radeon_texture_t)); + if (ret) { + if (RADEON_DEBUG & DEBUG_IOCTL) + fprintf(stderr, "DRM_RADEON_TEXTURE: again!\n"); + usleep(1); + } + } while (ret == -EAGAIN); + } + bo_legacy->dirty = 0; + bo_legacy->tobj->base.dirty_images[0] = 0; } return 0; } -- cgit v1.2.3 From 93ab69a0eff8e0b264ec8888cfd0ac11ea0e274f Mon Sep 17 00:00:00 2001 From: Richard Li Date: Wed, 8 Jul 2009 14:49:48 -0400 Subject: Fix buffer age implementaion bug. --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 31 +++++++++++++++++++++++++- src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 7 ++++-- 2 files changed, 35 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 9f26b257d0..0035910792 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -378,7 +378,36 @@ static int r600_cs_emit(struct radeon_cs *cs) /* TODO : put chip level things here if need. */ /* csm->ctx->vtbl.emit_cs_header(cs, csm->ctx); */ - /* TODO : append buffer age */ + BATCH_LOCALS(csm->ctx); + drm_radeon_getparam_t gp; + uint32_t current_scratchx_age; + + gp.param = RADEON_PARAM_LAST_CLEAR; + gp.value = (int *)¤t_scratchx_age; + r = drmCommandWriteRead(cs->csm->fd, + DRM_RADEON_GETPARAM, + &gp, + sizeof(gp)); + if (r) + { + fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, r); + exit(1); + } + + csm->pending_age = 0; + csm->pending_count = 1; + + current_scratchx_age++; + csm->pending_age = current_scratchx_age; + + BEGIN_BATCH_NO_AUTOSTATE(2); + R600_OUT_BATCH(0x2142); /* scratch 2 */ + R600_OUT_BATCH(current_scratchx_age); + END_BATCH(); + COMMIT_BATCH(); + + //TODO ioctl to get back cs id assigned in drm + //csm->pending_age = cs_id_back; r = r600_cs_process_relocs(cs, &(reloc_chunk[0]), &length_dw_reloc_chunk); if (r) { diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index 276926ce69..ae5f0c4cfe 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -171,7 +171,9 @@ static void legacy_get_current_age(struct bo_manager_legacy *boml) unsigned char *RADEONMMIO = NULL; int r; - if (IS_R300_CLASS(boml->screen)) { + if ( IS_R300_CLASS(boml->screen) + || IS_R600_CLASS(boml->screen) ) + { gp.param = RADEON_PARAM_LAST_CLEAR; gp.value = (int *)&boml->current_age; r = drmCommandWriteRead(boml->base.fd, DRM_RADEON_GETPARAM, @@ -180,7 +182,8 @@ static void legacy_get_current_age(struct bo_manager_legacy *boml) fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, r); exit(1); } - } else { + } + else { RADEONMMIO = boml->screen->mmio.map; boml->current_age = boml->screen->scratch[3]; boml->current_age = INREG(RADEON_GUI_SCRATCH_REG3); -- cgit v1.2.3 From 0de26dba2edf1c9d9b77b42ea1ad35604c009e32 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 9 Jul 2009 17:15:23 -0400 Subject: R6xx/r7xx: disable CS dump Don't fprintf to a xterm with the lock held. --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 0035910792..1ea1bf846e 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -431,7 +431,7 @@ static int r600_cs_emit(struct radeon_cs *cs) /* cs_cmd.cs_id = 0; */ cs_cmd.chunks = (uint64_t)(unsigned long)chunk_ptrs; - dump_cmdbuf(cs); + //dump_cmdbuf(cs); do { -- cgit v1.2.3 From 37c0cde80aa99435c7b58b36e5e186782cff4e77 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 10 Jul 2009 12:04:56 -0400 Subject: R6xx/r7xx: use packet 3 for scratch emit no need to allow packet 0 scratch regs in the drm --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 1ea1bf846e..b8e1debf8f 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -400,8 +400,9 @@ static int r600_cs_emit(struct radeon_cs *cs) current_scratchx_age++; csm->pending_age = current_scratchx_age; - BEGIN_BATCH_NO_AUTOSTATE(2); - R600_OUT_BATCH(0x2142); /* scratch 2 */ + BEGIN_BATCH_NO_AUTOSTATE(3); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + R600_OUT_BATCH((SCRATCH_REG2 - R600_SET_CONFIG_REG_OFFSET) >> 2); R600_OUT_BATCH(current_scratchx_age); END_BATCH(); COMMIT_BATCH(); -- cgit v1.2.3 From efe7ad233ca8fa1b7e1aabf706c433955c5c51e8 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 15 Jul 2009 11:16:41 -0400 Subject: Use memcpy directly in the common code This alleviates the need for an additional symbol. --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 16 ---------------- src/mesa/drivers/dri/radeon/radeon_bo_legacy.c | 2 +- src/mesa/drivers/dri/radeon/radeon_common.c | 14 +++++++++++--- 3 files changed, 12 insertions(+), 20 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index b8e1debf8f..7bde3360b6 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -676,19 +676,3 @@ void r600InitCmdBuf(context_t *r600) /* from rcommonInitCmdBuf */ } } -void r600_sw_blit(char *srcp, int src_pitch, char *dstp, int dst_pitch, - int x, int y, int w, int h, int cpp) -{ - char *src = srcp; - char *dst = dstp; - - src += (y * src_pitch) + (x * cpp); - dst += (y * dst_pitch) + (x * cpp); - - while (h--) { - memcpy(dst, src, w * cpp); - src += src_pitch; - dst += dst_pitch; - } -} - diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c index ae5f0c4cfe..94c2d97825 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c @@ -618,7 +618,7 @@ static int bo_vram_validate(struct radeon_bo *bo, (bo_legacy->offset - boml->fb_location); /* FIXME: alignment, pitch, etc. */ - r600_sw_blit(src, 0, dst, 0, 0, 0, 1, 1, bo->size); + memcpy(dst, src, bo->size); } else { /* Copy to VRAM using a blit. * All memory is 4K aligned. We're using 1024 pixels wide blits. diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index e75e6a33de..1848b7113e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -476,8 +476,9 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, continue; if (IS_R600_CLASS(rmesa->radeonScreen)) { - int src_pitch = rmesa->radeonScreen->backPitch * rmesa->radeonScreen->cpp; - int dst_pitch = rmesa->radeonScreen->frontPitch * rmesa->radeonScreen->cpp; + int cpp = rmesa->radeonScreen->cpp; + int src_pitch = rmesa->radeonScreen->backPitch * cpp; + int dst_pitch = rmesa->radeonScreen->frontPitch * cpp; char *src = (char *)rmesa->radeonScreen->driScreen->pFB + rmesa->radeonScreen->backOffset; char *dst = (char *)rmesa->radeonScreen->driScreen->pFB + rmesa->radeonScreen->frontOffset; int j; @@ -489,7 +490,14 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, int w = pb[j].x2 - x; int h = pb[j].y2 - y; - r600_sw_blit(src, src_pitch, dst, dst_pitch, x, y, w, h, rmesa->radeonScreen->cpp); + src += (y * src_pitch) + (x * cpp); + dst += (y * dst_pitch) + (x * cpp); + + while (h--) { + memcpy(dst, src, w * cpp); + src += src_pitch; + dst += dst_pitch; + } } } -- cgit v1.2.3 From 11606e873d38a320195ab4e23181579f766ae45c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Jul 2009 02:59:36 -0400 Subject: Fix more merge fallout --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 2 +- src/mesa/drivers/dri/radeon/radeon_bo_legacy.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 7bde3360b6..95a311dac7 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -521,7 +521,7 @@ static int r600_cs_check_space(struct radeon_cs *cs, struct radeon_cs_space_chec write_domain = bos[i].write_domain; /* pinned bos don't count */ - if (radeon_legacy_bo_is_static(bo)) + if (radeon_bo_is_static(bo)) continue; /* already accounted this bo */ diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h index 9187cd7201..0db817cab0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h +++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h @@ -43,5 +43,4 @@ void radeon_bo_manager_legacy_dtor(struct radeon_bo_manager *bom); void radeon_bo_legacy_texture_age(struct radeon_bo_manager *bom); unsigned radeon_bo_legacy_relocs_size(struct radeon_bo *bo); -int radeon_legacy_bo_is_static(struct radeon_bo *bo); #endif -- cgit v1.2.3 From 0850776f1afa69d9db62c3991a36fbc343f75d66 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Jul 2009 11:50:43 -0400 Subject: R6xx/r7xx: remove unused function Spotted by kdekorte on IRC --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 110 +------------------------------- 1 file changed, 1 insertion(+), 109 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 95a311dac7..ca9dab8639 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -498,113 +498,6 @@ static void r600_cs_print(struct radeon_cs *cs, FILE *file) { } -static int r600_cs_check_space(struct radeon_cs *cs, struct radeon_cs_space_check *bos, int num_bo) -{ - struct radeon_cs_manager *csm = cs->csm; - int this_op_read = 0, this_op_gart_write = 0, this_op_vram_write = 0; - uint32_t read_domains, write_domain; - int i; - struct radeon_bo *bo; - - /* check the totals for this operation */ - - if (num_bo == 0) - return 0; - - /* prepare */ - for (i = 0; i < num_bo; i++) - { - bo = bos[i].bo; - - bos[i].new_accounted = 0; - read_domains = bos[i].read_domains; - write_domain = bos[i].write_domain; - - /* pinned bos don't count */ - if (radeon_bo_is_static(bo)) - continue; - - /* already accounted this bo */ - if (write_domain && (write_domain == bo->space_accounted)) - continue; - - if (read_domains && ((read_domains << 16) == bo->space_accounted)) - continue; - - if (bo->space_accounted == 0) - { - if (write_domain == RADEON_GEM_DOMAIN_VRAM) - this_op_vram_write += bo->size; - else if (write_domain == RADEON_GEM_DOMAIN_GTT) - this_op_gart_write += bo->size; - else - this_op_read += bo->size; - bos[i].new_accounted = (read_domains << 16) | write_domain; - } - else - { - uint16_t old_read, old_write; - - old_read = bo->space_accounted >> 16; - old_write = bo->space_accounted & 0xffff; - - if (write_domain && (old_read & write_domain)) - { - bos[i].new_accounted = write_domain; - /* moving from read to a write domain */ - if (write_domain == RADEON_GEM_DOMAIN_VRAM) - { - this_op_read -= bo->size; - this_op_vram_write += bo->size; - } - else if (write_domain == RADEON_GEM_DOMAIN_VRAM) - { - this_op_read -= bo->size; - this_op_gart_write += bo->size; - } - } - else if (read_domains & old_write) - { - bos[i].new_accounted = bo->space_accounted & 0xffff; - } - else - { - /* rewrite the domains */ - if (write_domain != old_write) - fprintf(stderr,"WRITE DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, write_domain, old_write); - if (read_domains != old_read) - fprintf(stderr,"READ DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, read_domains, old_read); - return RADEON_CS_SPACE_FLUSH; - } - } - } - - if (this_op_read < 0) - this_op_read = 0; - - /* check sizes - operation first */ - if ((this_op_read + this_op_gart_write > csm->gart_limit) || - (this_op_vram_write > csm->vram_limit)) { - return RADEON_CS_SPACE_OP_TO_BIG; - } - - if (((csm->vram_write_used + this_op_vram_write) > csm->vram_limit) || - ((csm->read_used + csm->gart_write_used + this_op_gart_write + this_op_read) > csm->gart_limit)) { - return RADEON_CS_SPACE_FLUSH; - } - - csm->gart_write_used += this_op_gart_write; - csm->vram_write_used += this_op_vram_write; - csm->read_used += this_op_read; - /* commit */ - for (i = 0; i < num_bo; i++) { - bo = bos[i].bo; - bo->space_accounted = bos[i].new_accounted; - } - - return RADEON_CS_SPACE_OK; -} - static struct radeon_cs_funcs r600_cs_funcs = { r600_cs_create, r600_cs_write_reloc, @@ -614,8 +507,7 @@ static struct radeon_cs_funcs r600_cs_funcs = { r600_cs_destroy, r600_cs_erase, r600_cs_need_flush, - r600_cs_print, - r600_cs_check_space + r600_cs_print }; struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_context *ctx) -- cgit v1.2.3 From c42a6163144aa5441262235818b59b3108833a61 Mon Sep 17 00:00:00 2001 From: Kevin DeKorte Date: Thu, 16 Jul 2009 11:57:14 -0400 Subject: Warning fixes --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 15 --------------- src/mesa/drivers/dri/r600/r600_cmdbuf.h | 19 +++++++++++++++++++ src/mesa/drivers/dri/r600/r700_clear.c | 1 - 3 files changed, 19 insertions(+), 16 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index ca9dab8639..74fec02584 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -52,22 +52,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_mipmap_tree.h" #include "radeon_reg.h" -struct r600_cs_manager_legacy -{ - struct radeon_cs_manager base; - struct radeon_context *ctx; - /* hack for scratch stuff */ - uint32_t pending_age; - uint32_t pending_count; -}; -struct r600_cs_reloc_legacy { - struct radeon_cs_reloc base; - uint32_t cindices; - uint32_t *indices; - uint32_t *reloc_indices; - struct offset_modifiers offset_mod; -}; static struct radeon_cs * r600_cs_create(struct radeon_cs_manager *csm, uint32_t ndw) diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.h b/src/mesa/drivers/dri/r600/r600_cmdbuf.h index 6c3ceb38fa..bd1ed7fdff 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.h +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.h @@ -118,6 +118,23 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define R600_IT_SET_CTL_CONST 0x00006F00 #define R600_IT_SURFACE_BASE_UPDATE 0x00007300 +struct r600_cs_manager_legacy +{ + struct radeon_cs_manager base; + struct radeon_context *ctx; + /* hack for scratch stuff */ + uint32_t pending_age; + uint32_t pending_count; +}; + +struct r600_cs_reloc_legacy { + struct radeon_cs_reloc base; + uint32_t cindices; + uint32_t *indices; + uint32_t *reloc_indices; + struct offset_modifiers offset_mod; +}; + extern int r600_cs_write_reloc(struct radeon_cs *cs, struct radeon_bo *bo, uint32_t read_domain, @@ -130,6 +147,8 @@ static inline void r600_cs_write_dword(struct radeon_cs *cs, uint32_t dword) cs->packets[cs->cdw++] = dword; } +struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_context *ctx); + /** * Write one dword to the command buffer. */ diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c index e484845cc6..46a7010363 100644 --- a/src/mesa/drivers/dri/r600/r700_clear.c +++ b/src/mesa/drivers/dri/r600/r700_clear.c @@ -63,7 +63,6 @@ void r700Clear(GLcontext * ctx, GLbitfield mask) { return; } - if (!context->radeon.radeonScreen->driScreen->dri2.enabled) { LOCK_HARDWARE(&context->radeon); UNLOCK_HARDWARE(&context->radeon); -- cgit v1.2.3 From 826f1f9c6fd976ff36594e272c0a391187ca0bd8 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 31 Jul 2009 02:13:43 -0400 Subject: r600: get updated pending age from cs ioctl REQUIRES AN UPDATED DRM --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 37 +++------------------------------ 1 file changed, 3 insertions(+), 34 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 74fec02584..e9ad9ba64c 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -351,10 +351,7 @@ static int r600_cs_emit(struct radeon_cs *cs) struct r600_cs_manager_legacy *csm = (struct r600_cs_manager_legacy*)cs->csm; struct drm_radeon_cs cs_cmd; struct drm_radeon_cs_chunk cs_chunk[2]; - drm_radeon_cmd_buffer_t cmd; - /* drm_r300_cmd_header_t age; */ uint32_t length_dw_reloc_chunk; - uint64_t ull; uint64_t chunk_ptrs[2]; uint32_t reloc_chunk[128]; int r; @@ -363,43 +360,13 @@ static int r600_cs_emit(struct radeon_cs *cs) /* TODO : put chip level things here if need. */ /* csm->ctx->vtbl.emit_cs_header(cs, csm->ctx); */ - BATCH_LOCALS(csm->ctx); - drm_radeon_getparam_t gp; - uint32_t current_scratchx_age; - - gp.param = RADEON_PARAM_LAST_CLEAR; - gp.value = (int *)¤t_scratchx_age; - r = drmCommandWriteRead(cs->csm->fd, - DRM_RADEON_GETPARAM, - &gp, - sizeof(gp)); - if (r) - { - fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, r); - exit(1); - } - - csm->pending_age = 0; csm->pending_count = 1; - current_scratchx_age++; - csm->pending_age = current_scratchx_age; - - BEGIN_BATCH_NO_AUTOSTATE(3); - R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); - R600_OUT_BATCH((SCRATCH_REG2 - R600_SET_CONFIG_REG_OFFSET) >> 2); - R600_OUT_BATCH(current_scratchx_age); - END_BATCH(); - COMMIT_BATCH(); - - //TODO ioctl to get back cs id assigned in drm - //csm->pending_age = cs_id_back; - r = r600_cs_process_relocs(cs, &(reloc_chunk[0]), &length_dw_reloc_chunk); if (r) { return 0; } - + /* raw ib chunk */ cs_chunk[0].chunk_id = RADEON_CHUNK_ID_IB; cs_chunk[0].length_dw = cs->cdw; @@ -429,6 +396,8 @@ static int r600_cs_emit(struct radeon_cs *cs) return r; } + csm->pending_age = cs_cmd.cs_id; + r600_cs_set_age(cs); cs->csm->read_used = 0; -- cgit v1.2.3 From 19ce428c8a08565b06795f4b8020dc6399694789 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 31 Jul 2009 11:33:16 -0400 Subject: r600: ensure we have enough room for full state emit full state is roughly 4000 dwords, but will vary depending on the rendering. Also fix some warnings. --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 3 ++- src/mesa/drivers/dri/r600/r700_fragprog.c | 4 ---- src/mesa/drivers/dri/r600/r700_render.c | 3 +++ src/mesa/drivers/dri/r600/r700_vertprog.c | 7 ------- 4 files changed, 5 insertions(+), 12 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index e9ad9ba64c..15b99926d2 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -483,8 +483,9 @@ struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_cont void r600InitCmdBuf(context_t *r600) /* from rcommonInitCmdBuf */ { radeonContextPtr rmesa = &r600->radeon; - GLuint size; + rmesa->hw.max_state_size = 4000; /* rough estimate */ + /* Initialize command buffer */ size = 256 * driQueryOptioni(&rmesa->optionCache, "command_buffer_size"); diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index 587134676b..4ac37f1dfe 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -262,15 +262,12 @@ void * r700GetActiveFpShaderBo(GLcontext * ctx) GLboolean r700SetupFragmentProgram(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); - BATCH_LOCALS(&context->radeon); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); struct r700_fragment_program *fp = (struct r700_fragment_program *) (ctx->FragmentProgram._Current); r700_AssemblerBase *pAsm = &(fp->r700AsmCode); struct gl_fragment_program *mesa_fp = &(fp->mesa_program); - struct gl_program_parameter_list *paramList; - unsigned int unNumParamData; unsigned int ui, i; unsigned int unNumOfReg; unsigned int unBit; @@ -398,7 +395,6 @@ GLboolean r700SendPSConstants(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); BATCH_LOCALS(&context->radeon); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); struct r700_fragment_program *fp = (struct r700_fragment_program *) (ctx->FragmentProgram._Current); struct gl_program_parameter_list *paramList; diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index c26c20e6ee..bd4e0bfff4 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -277,6 +277,9 @@ void r700EmitState(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); + rcommonEnsureCmdBufSpace(&context->radeon, + context->radeon.hw.max_state_size, __FUNCTION__); + r700Start3D(context); r700SendSQConfig(context); r700SendFSState(context); // FIXME just a place holder for now diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index fda6f75687..8652f1d472 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -335,18 +335,12 @@ void * r700GetActiveVpShaderBo(GLcontext * ctx) GLboolean r700SetupVertexProgram(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); - - BATCH_LOCALS(&context->radeon); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); struct r700_vertex_program *vp = (struct r700_vertex_program *)ctx->VertexProgram._Current; struct gl_program_parameter_list *paramList; - unsigned int unNumParamData; - - unsigned int ui; if(GL_FALSE == vp->loaded) { @@ -400,7 +394,6 @@ GLboolean r700SendVSConstants(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); BATCH_LOCALS(&context->radeon); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); struct r700_vertex_program *vp = (struct r700_vertex_program *)ctx->VertexProgram._Current; struct gl_program_parameter_list *paramList; -- cgit v1.2.3 From 177c33c481d84058f57e761b25cba735b9c7e6ea Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 31 Jul 2009 12:06:26 -0400 Subject: r600: remove unused offset_mod stuff this is a step in migrating to the common cs code --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 27 ++----------------- src/mesa/drivers/dri/r600/r600_cmdbuf.h | 8 +++--- src/mesa/drivers/dri/r600/r600_context.h | 7 ----- src/mesa/drivers/dri/r600/r700_chip.c | 44 ++++++------------------------- src/mesa/drivers/dri/r600/r700_render.c | 7 +---- src/mesa/drivers/dri/r600/r700_vertprog.c | 2 -- 6 files changed, 14 insertions(+), 81 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 15b99926d2..d2e75c011c 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -78,8 +78,7 @@ int r600_cs_write_reloc(struct radeon_cs *cs, struct radeon_bo *bo, uint32_t read_domain, uint32_t write_domain, - uint32_t flags, - offset_modifiers* poffset_mod) + uint32_t flags) { struct r600_cs_reloc_legacy *relocs; int i; @@ -135,10 +134,6 @@ int r600_cs_write_reloc(struct radeon_cs *cs, cs->section_ndw += 2; cs->section_cdw += 2; - relocs[i].offset_mod.shift = poffset_mod->shift; - relocs[i].offset_mod.shiftbits = poffset_mod->shiftbits; - relocs[i].offset_mod.mask = poffset_mod->mask; - return 0; } } @@ -160,9 +155,6 @@ int r600_cs_write_reloc(struct radeon_cs *cs, { return -ENOMEM; } - relocs[cs->crelocs].offset_mod.shift = poffset_mod->shift; - relocs[cs->crelocs].offset_mod.shiftbits = poffset_mod->shiftbits; - relocs[cs->crelocs].offset_mod.mask = poffset_mod->mask; relocs[cs->crelocs].indices[0] = cs->cdw - 1; relocs[cs->crelocs].reloc_indices[0] = cs->section_cdw; @@ -286,28 +278,13 @@ restart: exit(0); return -EINVAL; } - /* apply offset operator */ - switch (relocs[i].offset_mod.shift) - { - case NO_SHIFT: - asicoffset = asicoffset & relocs[i].offset_mod.mask; - break; - case LEFT_SHIFT: - asicoffset = (asicoffset << relocs[i].offset_mod.shiftbits) & relocs[i].offset_mod.mask; - break; - case RIGHT_SHIFT: - asicoffset = (asicoffset >> relocs[i].offset_mod.shiftbits) & relocs[i].offset_mod.mask; - break; - default: - break; - }; /* pkt3 nop header in ib chunk */ cs->packets[relocs[i].reloc_indices[j]] = 0xC0001000; /* reloc index in ib chunk */ cs->packets[relocs[i].reloc_indices[j] + 1] = offset_dw; - + /* asic offset in reloc chunk */ /* see alex drm r600_nomm_relocate */ reloc_chunk[offset_dw] = asicoffset; reloc_chunk[offset_dw + 3] = 0; diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.h b/src/mesa/drivers/dri/r600/r600_cmdbuf.h index bd1ed7fdff..5df0cf1ab6 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.h +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.h @@ -132,15 +132,13 @@ struct r600_cs_reloc_legacy { uint32_t cindices; uint32_t *indices; uint32_t *reloc_indices; - struct offset_modifiers offset_mod; }; extern int r600_cs_write_reloc(struct radeon_cs *cs, struct radeon_bo *bo, uint32_t read_domain, uint32_t write_domain, - uint32_t flags, - offset_modifiers* poffset_mod); + uint32_t flags); static inline void r600_cs_write_dword(struct radeon_cs *cs, uint32_t dword) { @@ -171,7 +169,7 @@ struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_cont /** * Write a relocated dword to the command buffer. */ -#define R600_OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags, offset_mod) \ +#define R600_OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) \ do { \ if (0 && offset) { \ fprintf(stderr, "(%s:%s:%d) offset : %d\n", \ @@ -179,7 +177,7 @@ struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_cont } \ r600_cs_write_dword(b_l_rmesa->cmdbuf.cs, offset); \ r600_cs_write_reloc(b_l_rmesa->cmdbuf.cs, \ - bo, rd, wd, flags, offset_mod); \ + bo, rd, wd, flags); \ } while(0) /* R600/R700 */ diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index bcb33e1386..fbb8164af5 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -128,13 +128,6 @@ enum RIGHT_SHIFT = 2, }; -typedef struct offset_modifiers -{ - GLuint shift; - GLuint shiftbits; - GLuint mask; -} offset_modifiers; - /** * \brief R600 context structure. */ diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index f6face50db..ad4f29b729 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -247,7 +247,6 @@ GLboolean r700SendTextureState(context_t *context) { unsigned int i; R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF}; struct radeon_bo *bo = NULL; BATCH_LOCALS(&context->radeon); @@ -272,11 +271,11 @@ GLboolean r700SendTextureState(context_t *context) R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2, bo, 0, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod); + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3, bo, r700->textures[i]->SQ_TEX_RESOURCE3, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod); + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6); @@ -314,8 +313,6 @@ void r700SetupVTXConstants(GLcontext * ctx, { context_t *context = R700_CONTEXT(ctx); struct radeon_aos * paos = (struct radeon_aos *)pAos; - offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF}; - BATCH_LOCALS(&context->radeon); unsigned int uSQ_VTX_CONSTANT_WORD0_0; @@ -357,7 +354,7 @@ void r700SetupVTXConstants(GLcontext * ctx, R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0, paos->bo, uSQ_VTX_CONSTANT_WORD0_0, - RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + RADEON_GEM_DOMAIN_GTT, 0, 0); R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0); R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0); R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0); @@ -483,7 +480,6 @@ GLboolean r700SendDepthTargetState(context_t *context) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_renderbuffer *rrb; - offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); rrb = radeon_get_depthbuffer(&context->radeon); @@ -492,10 +488,6 @@ GLboolean r700SendDepthTargetState(context_t *context) return GL_FALSE; } - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - BEGIN_BATCH_NO_AUTOSTATE(9); R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2); R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All); @@ -504,7 +496,7 @@ GLboolean r700SendDepthTargetState(context_t *context) R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All, rrb->bo, r700->DB_DEPTH_BASE.u32All, - 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod); + 0, RADEON_GEM_DOMAIN_VRAM, 0); R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All); R600_OUT_BATCH(r700->DB_HTILE_DATA_BASE.u32All); END_BATCH(); @@ -541,7 +533,6 @@ GLboolean r700SendRenderTargetState(context_t *context, int id) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_renderbuffer *rrb; - offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); rrb = radeon_get_colorbuffer(&context->radeon); @@ -556,16 +547,12 @@ GLboolean r700SendRenderTargetState(context_t *context, int id) if (!r700->render_target[id].enabled) return GL_FALSE; - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - BEGIN_BATCH_NO_AUTOSTATE(3); R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1); R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All, rrb->bo, r700->render_target[id].CB_COLOR0_BASE.u32All, - 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod); + 0, RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) && @@ -603,15 +590,10 @@ GLboolean r700SendPSState(context_t *context) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; - offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context)); - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); BEGIN_BATCH_NO_AUTOSTATE(3); @@ -619,7 +601,7 @@ GLboolean r700SendPSState(context_t *context) R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All, pbo, r700->ps.SQ_PGM_START_PS.u32All, - RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + RADEON_GEM_DOMAIN_GTT, 0, 0); END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(9); @@ -637,15 +619,10 @@ GLboolean r700SendVSState(context_t *context) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; - offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); BEGIN_BATCH_NO_AUTOSTATE(3); @@ -653,7 +630,7 @@ GLboolean r700SendVSState(context_t *context) R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All, pbo, r700->vs.SQ_PGM_START_VS.u32All, - RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + RADEON_GEM_DOMAIN_GTT, 0, 0); END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(6); @@ -670,7 +647,6 @@ GLboolean r700SendFSState(context_t *context) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; - offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); /* XXX fixme @@ -684,10 +660,6 @@ GLboolean r700SendFSState(context_t *context) r700->fs.SQ_PGM_CF_OFFSET_FS.u32All = 0; /* XXX */ - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); BEGIN_BATCH_NO_AUTOSTATE(3); @@ -695,7 +667,7 @@ GLboolean r700SendFSState(context_t *context) R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All, pbo, r700->fs.SQ_PGM_START_FS.u32All, - RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + RADEON_GEM_DOMAIN_GTT, 0, 0); END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(6); diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index bd4e0bfff4..5a1f04f87c 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -150,17 +150,12 @@ GLboolean r700SyncSurf(context_t *context, { BATCH_LOCALS(&context->radeon); uint32_t cp_coher_size; - offset_modifiers offset_mod; if (pbo->size == 0xffffffff) cp_coher_size = 0xffffffff; else cp_coher_size = ((pbo->size + 255) >> 8); - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - BEGIN_BATCH_NO_AUTOSTATE(5); R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_SYNC, 3)); R600_OUT_BATCH(sync_type); @@ -168,7 +163,7 @@ GLboolean r700SyncSurf(context_t *context, R600_OUT_BATCH_RELOC(0, pbo, 0, - read_domain, write_domain, 0, &offset_mod); // ??? + read_domain, write_domain, 0); // ??? R600_OUT_BATCH(10); END_BATCH(); diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index 8652f1d472..1c5c20f66e 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -340,8 +340,6 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) struct r700_vertex_program *vp = (struct r700_vertex_program *)ctx->VertexProgram._Current; - struct gl_program_parameter_list *paramList; - if(GL_FALSE == vp->loaded) { if(vp->r700Shader.bNeedsAssembly == GL_TRUE) -- cgit v1.2.3 From 80d80d23b6078b8a5c79675ebbdeda665251f13b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 31 Jul 2009 14:48:46 -0400 Subject: r600: fix reloc setup re-use the same reloc index for bos that are referenced multiple times. Fixes rain demo. --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 68 +++++++++++++++------------------ 1 file changed, 31 insertions(+), 37 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index d2e75c011c..8debecbab9 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -247,50 +247,44 @@ static int r600_cs_process_relocs(struct radeon_cs *cs, csm = (struct r600_cs_manager_legacy*)cs->csm; relocs = (struct r600_cs_reloc_legacy *)cs->relocs; restart: - for (i = 0; i < cs->crelocs; i++) - { - for (j = 0; j < relocs[i].cindices; j++) - { + for (i = 0; i < cs->crelocs; i++) { uint32_t soffset, eoffset, asicoffset; r = radeon_bo_legacy_validate(relocs[i].base.bo, - &soffset, &eoffset); - if (r == -EAGAIN) - { - goto restart; + &soffset, &eoffset); + if (r == -EAGAIN) { + goto restart; } - if (r) - { - fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", - relocs[i].base.bo, soffset, eoffset); - return r; + if (r) { + fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", + relocs[i].base.bo, soffset, eoffset); + return r; } asicoffset = soffset; - if (asicoffset >= eoffset) - { - /* radeon_bo_debug(relocs[i].base.bo, 12); */ - fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", - relocs[i].base.bo, soffset, eoffset); - fprintf(stderr, "above end: %p 0x%08X 0x%08X\n", - relocs[i].base.bo, - cs->packets[relocs[i].indices[j]], - eoffset); - exit(0); - return -EINVAL; - } - /* pkt3 nop header in ib chunk */ - cs->packets[relocs[i].reloc_indices[j]] = 0xC0001000; - - /* reloc index in ib chunk */ - cs->packets[relocs[i].reloc_indices[j] + 1] = offset_dw; - - /* asic offset in reloc chunk */ /* see alex drm r600_nomm_relocate */ - reloc_chunk[offset_dw] = asicoffset; - reloc_chunk[offset_dw + 3] = 0; - - offset_dw += 4; - } + for (j = 0; j < relocs[i].cindices; j++) { + if (asicoffset >= eoffset) { + /* radeon_bo_debug(relocs[i].base.bo, 12); */ + fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", + relocs[i].base.bo, soffset, eoffset); + fprintf(stderr, "above end: %p 0x%08X 0x%08X\n", + relocs[i].base.bo, + cs->packets[relocs[i].indices[j]], + eoffset); + exit(0); + return -EINVAL; + } + /* pkt3 nop header in ib chunk */ + cs->packets[relocs[i].reloc_indices[j]] = 0xC0001000; + /* reloc index in ib chunk */ + cs->packets[relocs[i].reloc_indices[j] + 1] = offset_dw; + } + + /* asic offset in reloc chunk */ /* see alex drm r600_nomm_relocate */ + reloc_chunk[offset_dw] = asicoffset; + reloc_chunk[offset_dw + 3] = 0; + + offset_dw += 4; } *length_dw_reloc_chunk = offset_dw; -- cgit v1.2.3 From d07bf2b35c1419bdef824092e509c70ffb11fd67 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Sun, 2 Aug 2009 18:26:12 -0400 Subject: r600: handle state emit better - move shader-related state with the rest of the shader setup/emit - start to track dirty state better --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 3 +++ src/mesa/drivers/dri/r600/r700_render.c | 19 +++++++++++-------- src/mesa/drivers/dri/r600/r700_state.c | 2 ++ 3 files changed, 16 insertions(+), 8 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 8debecbab9..dc2fb0144a 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -457,6 +457,9 @@ void r600InitCmdBuf(context_t *r600) /* from rcommonInitCmdBuf */ GLuint size; rmesa->hw.max_state_size = 4000; /* rough estimate */ + rmesa->hw.all_dirty = GL_TRUE; + rmesa->hw.is_dirty = GL_TRUE; + /* Initialize command buffer */ size = 256 * driQueryOptioni(&rmesa->optionCache, "command_buffer_size"); diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 34a4385841..20376d2c36 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -139,6 +139,13 @@ static GLboolean r700SetupShaders(GLcontext * ctx) r600UpdateTextureState(ctx); + r700SendFSState(context); // FIXME just a place holder for now + r700SendPSState(context); + r700SendVSState(context); + + r700SendTextureState(context); + r700SetupStreams(ctx); + return GL_TRUE; } @@ -274,18 +281,16 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim void r700EmitState(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); + radeonContextPtr radeon = &context->radeon; + + if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw.all_dirty) + return; rcommonEnsureCmdBufSpace(&context->radeon, context->radeon.hw.max_state_size, __FUNCTION__); r700Start3D(context); r700SendSQConfig(context); - r700SendFSState(context); // FIXME just a place holder for now - r700SendPSState(context); - r700SendVSState(context); - - r700SendTextureState(context); - r700SetupStreams(ctx); r700SendUCPState(context); r700SendContextStates(context); @@ -325,8 +330,6 @@ static GLboolean r700RunRender(GLcontext * ctx, radeonReleaseArrays(ctx, ~0); - rcommonFlushCmdBuf( &context->radeon, __FUNCTION__ ); - return GL_FALSE; } diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index b75f531503..e95f52400a 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -1854,6 +1854,8 @@ void r700InitState(GLcontext * ctx) //------------------- /* Set up color compare mask */ r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF; + context->radeon.hw.all_dirty = GL_TRUE; + } void r700InitStateFuncs(struct dd_function_table *functions) //----------------- -- cgit v1.2.3 From 525ddb1f56aceee74a08764315dc6420f198ccc2 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 20 Aug 2009 03:19:58 -0400 Subject: r600: rework emit code make sure we allocate enough space for relocs --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 32 +++++++++++++------------- src/mesa/drivers/dri/r600/r600_cmdbuf.h | 4 +++- src/mesa/drivers/dri/r600/r700_chip.c | 40 +++++++++++++++++++-------------- src/mesa/drivers/dri/r600/r700_render.c | 5 +++-- 4 files changed, 44 insertions(+), 37 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index dc2fb0144a..83687bb720 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -129,10 +129,10 @@ int r600_cs_write_reloc(struct radeon_cs *cs, } relocs[i].indices = indices; relocs[i].reloc_indices = reloc_indices; - relocs[i].indices[relocs[i].cindices - 1] = cs->cdw - 1; - relocs[i].reloc_indices[relocs[i].cindices - 1] = cs->section_cdw; - cs->section_ndw += 2; + relocs[i].indices[relocs[i].cindices - 1] = cs->cdw; + relocs[i].reloc_indices[relocs[i].cindices - 1] = cs->cdw; cs->section_cdw += 2; + cs->cdw += 2; return 0; } @@ -156,10 +156,10 @@ int r600_cs_write_reloc(struct radeon_cs *cs, return -ENOMEM; } - relocs[cs->crelocs].indices[0] = cs->cdw - 1; - relocs[cs->crelocs].reloc_indices[0] = cs->section_cdw; - cs->section_ndw += 2; + relocs[cs->crelocs].indices[0] = cs->cdw; + relocs[cs->crelocs].reloc_indices[0] = cs->cdw; cs->section_cdw += 2; + cs->cdw += 2; relocs[cs->crelocs].cindices = 1; cs->relocs_total_size += radeon_bo_legacy_relocs_size(bo); cs->crelocs++; @@ -183,7 +183,14 @@ static int r600_cs_begin(struct radeon_cs *cs, return -EPIPE; } - if (cs->cdw + ndw + 32 > cs->ndw) { /* Left 32 DWORD (8 offset+pitch) spare room for reloc indices */ + cs->section = 1; + cs->section_ndw = ndw; + cs->section_cdw = 0; + cs->section_file = file; + cs->section_func = func; + cs->section_line = line; + + if (cs->cdw + ndw > cs->ndw) { uint32_t tmp, *ptr; int num = (ndw > 0x3FF) ? ndw : 0x3FF; @@ -196,13 +203,6 @@ static int r600_cs_begin(struct radeon_cs *cs, cs->ndw = tmp; } - cs->section = 1; - cs->section_ndw = 0; - cs->section_cdw = cs->cdw + ndw; /* start of reloc indices. */ - cs->section_file = file; - cs->section_func = func; - cs->section_line = line; - return 0; } @@ -219,8 +219,7 @@ static int r600_cs_end(struct radeon_cs *cs, } cs->section = 0; - if ( (cs->section_ndw + cs->cdw) != cs->section_cdw ) - { + if ( cs->section_ndw != cs->section_cdw ) { fprintf(stderr, "CS section size missmatch start at (%s,%s,%d) %d vs %d\n", cs->section_file, cs->section_func, cs->section_line, cs->section_ndw, cs->section_cdw); fprintf(stderr, "cs->section_ndw = %d, cs->cdw = %d, cs->section_cdw = %d \n", @@ -230,7 +229,6 @@ static int r600_cs_end(struct radeon_cs *cs, return -EPIPE; } - cs->cdw = cs->section_cdw; return 0; } diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.h b/src/mesa/drivers/dri/r600/r600_cmdbuf.h index 5df0cf1ab6..06eddf2eee 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.h +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.h @@ -143,6 +143,9 @@ extern int r600_cs_write_reloc(struct radeon_cs *cs, static inline void r600_cs_write_dword(struct radeon_cs *cs, uint32_t dword) { cs->packets[cs->cdw++] = dword; + if (cs->section) { + cs->section_cdw++; + } } struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_context *ctx); @@ -175,7 +178,6 @@ struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_cont fprintf(stderr, "(%s:%s:%d) offset : %d\n", \ __FILE__, __FUNCTION__, __LINE__, offset); \ } \ - r600_cs_write_dword(b_l_rmesa->cmdbuf.cs, offset); \ r600_cs_write_reloc(b_l_rmesa->cmdbuf.cs, \ bo, rd, wd, flags); \ } while(0) diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index f461d08a70..c3c0923ebb 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -276,11 +276,16 @@ GLboolean r700SendTextureState(context_t *context) RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, TC_ACTION_ENA_bit); - BEGIN_BATCH_NO_AUTOSTATE(9); + BEGIN_BATCH_NO_AUTOSTATE(9 + 4); R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); R600_OUT_BATCH(i * 7); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1); + R600_OUT_BATCH(0); /* r700->textures[i]->SQ_TEX_RESOURCE2 */ + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6); R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2, bo, 0, @@ -289,9 +294,6 @@ GLboolean r700SendTextureState(context_t *context) bo, r700->textures[i]->SQ_TEX_RESOURCE3, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6); END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(5); @@ -362,22 +364,21 @@ void r700SetupVTXConstants(GLcontext * ctx, SETfield(uSQ_VTX_CONSTANT_WORD6_0, SQ_TEX_VTX_VALID_BUFFER, SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask); - BEGIN_BATCH_NO_AUTOSTATE(9); + BEGIN_BATCH_NO_AUTOSTATE(9 + 2); R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); R600_OUT_BATCH((nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE); - - R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0, - paos->bo, - uSQ_VTX_CONSTANT_WORD0_0, - RADEON_GEM_DOMAIN_GTT, 0, 0); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0); R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0); R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0); R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0); R600_OUT_BATCH(0); R600_OUT_BATCH(0); R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0); - + R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0, + paos->bo, + uSQ_VTX_CONSTANT_WORD0_0, + RADEON_GEM_DOMAIN_GTT, 0, 0); END_BATCH(); COMMIT_BATCH(); @@ -515,16 +516,17 @@ GLboolean r700SendDepthTargetState(context_t *context) return GL_FALSE; } - BEGIN_BATCH_NO_AUTOSTATE(8); + BEGIN_BATCH_NO_AUTOSTATE(8 + 2); R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2); R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All); R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All); R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 2); + R600_OUT_BATCH(r700->DB_DEPTH_BASE.u32All); + R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All); R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All, rrb->bo, r700->DB_DEPTH_BASE.u32All, 0, RADEON_GEM_DOMAIN_VRAM, 0); - R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All); END_BATCH(); if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) && @@ -561,8 +563,9 @@ GLboolean r700SendRenderTargetState(context_t *context, int id) if (!r700->render_target[id].enabled) return GL_FALSE; - BEGIN_BATCH_NO_AUTOSTATE(3); + BEGIN_BATCH_NO_AUTOSTATE(3 + 2); R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1); + R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_BASE.u32All); R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All, rrb->bo, r700->render_target[id].CB_COLOR0_BASE.u32All, @@ -607,8 +610,9 @@ GLboolean r700SendPSState(context_t *context) r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); - BEGIN_BATCH_NO_AUTOSTATE(3); + BEGIN_BATCH_NO_AUTOSTATE(3 + 2); R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1); + R600_OUT_BATCH(r700->ps.SQ_PGM_START_PS.u32All); R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All, pbo, r700->ps.SQ_PGM_START_PS.u32All, @@ -639,8 +643,9 @@ GLboolean r700SendVSState(context_t *context) r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); - BEGIN_BATCH_NO_AUTOSTATE(3); + BEGIN_BATCH_NO_AUTOSTATE(3 + 2); R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1); + R600_OUT_BATCH(r700->vs.SQ_PGM_START_VS.u32All); R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All, pbo, r700->vs.SQ_PGM_START_VS.u32All, @@ -679,8 +684,9 @@ GLboolean r700SendFSState(context_t *context) r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); - BEGIN_BATCH_NO_AUTOSTATE(3); + BEGIN_BATCH_NO_AUTOSTATE(3 + 2); R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1); + R600_OUT_BATCH(r700->fs.SQ_PGM_START_FS.u32All); R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All, pbo, r700->fs.SQ_PGM_START_FS.u32All, diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 6985bd4ffa..58b4491d00 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -166,15 +166,16 @@ GLboolean r700SyncSurf(context_t *context, else cp_coher_size = ((pbo->size + 255) >> 8); - BEGIN_BATCH_NO_AUTOSTATE(5); + BEGIN_BATCH_NO_AUTOSTATE(5 + 2); R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_SYNC, 3)); R600_OUT_BATCH(sync_type); R600_OUT_BATCH(cp_coher_size); + R600_OUT_BATCH(0); + R600_OUT_BATCH(10); R600_OUT_BATCH_RELOC(0, pbo, 0, read_domain, write_domain, 0); // ??? - R600_OUT_BATCH(10); END_BATCH(); COMMIT_BATCH(); -- cgit v1.2.3 From ba48e78b1f7cf307d505583f758c65b158f5aae0 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 20 Aug 2009 18:55:41 -0400 Subject: r600: convert to using common radeon state atoms switches more state handling to common code. We need should be more fine grained with the state atoms eventually. --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 10 +- src/mesa/drivers/dri/r600/r600_context.h | 44 +++--- src/mesa/drivers/dri/r600/r600_emit.c | 1 - src/mesa/drivers/dri/r600/r700_chip.c | 147 +++++++++++---------- src/mesa/drivers/dri/r600/r700_ioctl.c | 25 +--- src/mesa/drivers/dri/r600/r700_render.c | 86 ++---------- src/mesa/drivers/dri/r600/r700_state.c | 67 +++++----- .../drivers/dri/radeon/radeon_common_context.c | 7 - 8 files changed, 154 insertions(+), 233 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 83687bb720..38814b6d71 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -451,12 +451,10 @@ struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_cont void r600InitCmdBuf(context_t *r600) /* from rcommonInitCmdBuf */ { - radeonContextPtr rmesa = &r600->radeon; - GLuint size; - rmesa->hw.max_state_size = 4000; /* rough estimate */ + radeonContextPtr rmesa = &r600->radeon; + GLuint size; - rmesa->hw.all_dirty = GL_TRUE; - rmesa->hw.is_dirty = GL_TRUE; + r600InitAtoms(r600); /* Initialize command buffer */ size = 256 * driQueryOptioni(&rmesa->optionCache, @@ -480,7 +478,7 @@ void r600InitCmdBuf(context_t *r600) /* from rcommonInitCmdBuf */ rmesa->cmdbuf.cs = radeon_cs_create(rmesa->cmdbuf.csm, size); assert(rmesa->cmdbuf.cs != NULL); rmesa->cmdbuf.size = size; - + if (!rmesa->radeonScreen->kernel_mm) { radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]); radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, rmesa->radeonScreen->gartTextures.size); diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index 0cf2eb2daa..a9b080baa3 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -55,9 +55,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. struct r600_context; typedef struct r600_context context_t; -GLboolean r700SendPSState(context_t *context); -GLboolean r700SendVSState(context_t *context); -GLboolean r700SendSQConfig(context_t *context); +extern GLboolean r700SendPSState(context_t *context); +extern GLboolean r700SendVSState(context_t *context); +extern GLboolean r700SendFSState(context_t *context); #include "main/mm.h" @@ -112,6 +112,22 @@ enum RIGHT_SHIFT = 2, }; +struct r600_hw_state { + struct radeon_state_atom sq; + struct radeon_state_atom db; + struct radeon_state_atom db_target; + struct radeon_state_atom sc; + struct radeon_state_atom cl; + struct radeon_state_atom ucp; + struct radeon_state_atom su; + struct radeon_state_atom cb; + struct radeon_state_atom cb_target; + struct radeon_state_atom sx; + struct radeon_state_atom vgt; + struct radeon_state_atom spi; + struct radeon_state_atom vpt; +}; + /** * \brief R600 context structure. */ @@ -121,6 +137,8 @@ struct r600_context { /* ------ */ R700_CHIP_CONTEXT hw; + struct r600_hw_state atoms; + /* Vertex buffers */ GLvector4f dummy_attrib[_TNL_ATTRIB_MAX]; @@ -143,28 +161,14 @@ do { \ rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \ } while (0) -#define R600_STATECHANGE(r600, atom) \ +#define R600_STATECHANGE(r600, ATOM) \ do { \ R600_NEWPRIM(r600); \ - (atom) = GL_TRUE; \ + r600->atoms.ATOM.dirty = GL_TRUE; \ r600->radeon.hw.is_dirty = GL_TRUE; \ } while(0) -extern GLboolean r700SendSPIState(context_t *context); -extern GLboolean r700SendVGTState(context_t *context); -extern GLboolean r700SendSXState(context_t *context); -extern GLboolean r700SendDBState(context_t *context); -extern GLboolean r700SendCBState(context_t *context); -extern GLboolean r700SendSUState(context_t *context); -extern GLboolean r700SendCLState(context_t *context); -extern GLboolean r700SendSCState(context_t *context); -extern GLboolean r700SendViewportState(context_t *context, int id); -extern GLboolean r700SendRenderTargetState(context_t *context, int id); extern GLboolean r700SendTextureState(context_t *context); -extern GLboolean r700SendDepthTargetState(context_t *context); -extern GLboolean r700SendUCPState(context_t *context); -extern GLboolean r700SendFSState(context_t *context); -extern void r700EmitState(GLcontext * ctx); extern GLboolean r700SyncSurf(context_t *context, struct radeon_bo *pbo, @@ -180,6 +184,8 @@ extern void r700SetupVTXConstants(GLcontext * ctx, unsigned int stride, unsigned int Count); /* number of vectors in stream */ +extern void r600InitAtoms(context_t *context); + #define RADEON_D_CAPTURE 0 #define RADEON_D_PLAYBACK 1 #define RADEON_D_PLAYBACK_RAW 2 diff --git a/src/mesa/drivers/dri/r600/r600_emit.c b/src/mesa/drivers/dri/r600/r600_emit.c index b695ed9583..b0c7294682 100644 --- a/src/mesa/drivers/dri/r600/r600_emit.c +++ b/src/mesa/drivers/dri/r600/r600_emit.c @@ -49,7 +49,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. void r600EmitCacheFlush(context_t *rmesa) { - BATCH_LOCALS(&rmesa->radeon); } GLboolean r600EmitShader(GLcontext * ctx, diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 7f46b0c468..2d68f021df 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -27,6 +27,7 @@ #include "main/imports.h" #include "main/glheader.h" +#include "main/simple_list.h" #include "r600_context.h" #include "r600_cmdbuf.h" @@ -220,8 +221,9 @@ int r700SetupStreams(GLcontext * ctx) return R600_FALLBACK_NONE; } -GLboolean r700SendDepthTargetState(context_t *context) +static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_renderbuffer *rrb; BATCH_LOCALS(&context->radeon); @@ -229,7 +231,7 @@ GLboolean r700SendDepthTargetState(context_t *context) rrb = radeon_get_depthbuffer(&context->radeon); if (!rrb || !rrb->bo) { fprintf(stderr, "no rrb\n"); - return GL_FALSE; + return; } BEGIN_BATCH_NO_AUTOSTATE(8 + 2); @@ -255,31 +257,27 @@ GLboolean r700SendDepthTargetState(context_t *context) COMMIT_BATCH(); - r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM, - DB_ACTION_ENA_bit | DB_DEST_BASE_ENA_bit); - - r700->db_target_dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendRenderTargetState(context_t *context, int id) +static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_renderbuffer *rrb; BATCH_LOCALS(&context->radeon); + int id = 0; rrb = radeon_get_colorbuffer(&context->radeon); if (!rrb || !rrb->bo) { fprintf(stderr, "no rrb\n"); - return GL_FALSE; + return; } if (id > R700_MAX_RENDER_TARGETS) - return GL_FALSE; + return; if (!r700->render_target[id].enabled) - return GL_FALSE; + return; BEGIN_BATCH_NO_AUTOSTATE(3 + 2); R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1); @@ -309,12 +307,6 @@ GLboolean r700SendRenderTargetState(context_t *context, int id) COMMIT_BATCH(); - r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM, - CB_ACTION_ENA_bit | (1 << (id + 6))); - - r700->render_target[id].dirty = GL_FALSE; - - return GL_TRUE; } GLboolean r700SendPSState(context_t *context) @@ -429,16 +421,18 @@ GLboolean r700SendFSState(context_t *context) return GL_TRUE; } -GLboolean r700SendViewportState(context_t *context, int id) +static void r700SendViewportState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); + int id = 0; if (id > R700_MAX_VIEWPORTS) - return GL_FALSE; + return; if (!r700->viewport[id].enabled) - return GL_FALSE; + return; BEGIN_BATCH_NO_AUTOSTATE(16); R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL + (8 * id), 2); @@ -458,13 +452,11 @@ GLboolean r700SendViewportState(context_t *context, int id) COMMIT_BATCH(); - r700->viewport[id].dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendSQConfig(context_t *context) +static void r700SendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); @@ -496,20 +488,17 @@ GLboolean r700SendSQConfig(context_t *context) END_BATCH(); COMMIT_BATCH(); - - r700->sq_dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendUCPState(context_t *context) +static void r700SendUCPState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); int i; for (i = 0; i < R700_MAX_UCP; i++) { - if (r700->ucp[i].enabled && r700->ucp[i].dirty) { + if (r700->ucp[i].enabled) { BEGIN_BATCH_NO_AUTOSTATE(6); R600_OUT_BATCH_REGSEQ(PA_CL_UCP_0_X + (16 * i), 4); R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_X.u32All); @@ -518,15 +507,13 @@ GLboolean r700SendUCPState(context_t *context) R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_W.u32All); END_BATCH(); COMMIT_BATCH(); - r700->ucp[i].dirty = GL_FALSE; } } - - return GL_TRUE; } -GLboolean r700SendSPIState(context_t *context) +static void r700SendSPIState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); unsigned int ui; @@ -596,14 +583,11 @@ GLboolean r700SendSPIState(context_t *context) END_BATCH(); COMMIT_BATCH(); - - r700->spi_dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendVGTState(context_t *context) +static void r700SendVGTState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); @@ -644,14 +628,11 @@ GLboolean r700SendVGTState(context_t *context) END_BATCH(); COMMIT_BATCH(); - - r700->vgt_dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendSXState(context_t *context) +static void r700SendSXState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); @@ -661,14 +642,11 @@ GLboolean r700SendSXState(context_t *context) R600_OUT_BATCH_REGVAL(SX_ALPHA_REF, r700->SX_ALPHA_REF.u32All); END_BATCH(); COMMIT_BATCH(); - - r700->sx_dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendDBState(context_t *context) +static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); @@ -695,14 +673,11 @@ GLboolean r700SendDBState(context_t *context) END_BATCH(); COMMIT_BATCH(); - - r700->db_dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendCBState(context_t *context) +static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); unsigned int ui; @@ -757,13 +732,11 @@ GLboolean r700SendCBState(context_t *context) COMMIT_BATCH(); - r700->cb_dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendSUState(context_t *context) +static void r700SendSUState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); @@ -789,13 +762,11 @@ GLboolean r700SendSUState(context_t *context) END_BATCH(); COMMIT_BATCH(); - r700->su_dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendCLState(context_t *context) +static void r700SendCLState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); @@ -813,15 +784,12 @@ GLboolean r700SendCLState(context_t *context) END_BATCH(); COMMIT_BATCH(); - - r700->cl_dirty = GL_FALSE; - - return GL_TRUE; } // XXX need to split this up -GLboolean r700SendSCState(context_t *context) +static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); @@ -860,8 +828,47 @@ GLboolean r700SendSCState(context_t *context) END_BATCH(); COMMIT_BATCH(); +} - r700->sc_dirty = GL_FALSE; +static int check_always(GLcontext *ctx, struct radeon_state_atom *atom) +{ + return atom->cmd_size; +} - return GL_TRUE; +#define ALLOC_STATE( ATOM, SZ, EMIT ) \ +do { \ + context->atoms.ATOM.cmd_size = (SZ); \ + context->atoms.ATOM.cmd = NULL; \ + context->atoms.ATOM.name = #ATOM; \ + context->atoms.ATOM.idx = 0; \ + context->atoms.ATOM.check = check_always; \ + context->atoms.ATOM.dirty = GL_FALSE; \ + context->atoms.ATOM.emit = (EMIT); \ + context->radeon.hw.max_state_size += (SZ); \ + insert_at_tail(&context->radeon.hw.atomlist, &context->atoms.ATOM); \ +} while (0) + +void r600InitAtoms(context_t *context) +{ + + /* Setup the atom linked list */ + make_empty_list(&context->radeon.hw.atomlist); + context->radeon.hw.atomlist.name = "atom-list"; + + ALLOC_STATE(sq, 34, r700SendSQConfig); + ALLOC_STATE(db, 27, r700SendDBState); + ALLOC_STATE(db_target, 19, r700SendDepthTargetState); + ALLOC_STATE(sc, 47, r700SendSCState); + ALLOC_STATE(cl, 18, r700SendCLState); + ALLOC_STATE(ucp, 36, r700SendUCPState); + ALLOC_STATE(su, 19, r700SendSUState); + ALLOC_STATE(cb, 39, r700SendCBState); + ALLOC_STATE(cb_target, 32, r700SendRenderTargetState); + ALLOC_STATE(sx, 9, r700SendSXState); + ALLOC_STATE(vgt, 41, r700SendVGTState); + ALLOC_STATE(spi, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState); + ALLOC_STATE(vpt, 16, r700SendViewportState); + + context->radeon.hw.is_dirty = GL_TRUE; + context->radeon.hw.all_dirty = GL_TRUE; } diff --git a/src/mesa/drivers/dri/r600/r700_ioctl.c b/src/mesa/drivers/dri/r600/r700_ioctl.c index e0e506d665..72a8978976 100644 --- a/src/mesa/drivers/dri/r600/r700_ioctl.c +++ b/src/mesa/drivers/dri/r600/r700_ioctl.c @@ -41,33 +41,10 @@ #include "r700_ioctl.h" #include "r700_clear.h" -static void r700Flush(GLcontext *ctx) -{ - radeonContextPtr radeon = RADEON_CONTEXT(ctx); - - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s %d\n", __FUNCTION__, radeon->cmdbuf.cs->cdw); - - /* okay if we have no cmds in the buffer && - we have no DMA flush && - we have no DMA buffer allocated. - then no point flushing anything at all. - */ - if (!radeon->dma.flush && !radeon->cmdbuf.cs->cdw && is_empty_list(&radeon->dma.reserved)) - return; - - if (radeon->dma.flush) - radeon->dma.flush( ctx ); - - r700EmitState(ctx); - - if (radeon->cmdbuf.cs->cdw) - rcommonFlushCmdBuf(radeon, __FUNCTION__); -} void r700InitIoctlFuncs(struct dd_function_table *functions) { functions->Clear = r700Clear; functions->Finish = radeonFinish; - functions->Flush = r700Flush; + functions->Flush = radeonFlush; } diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 52f8f90dad..f0cd357c76 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -332,96 +332,28 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim } -static void r700EmitAtoms(GLcontext * ctx, GLboolean dirty) -{ - context_t *context = R700_CONTEXT(ctx); - radeonContextPtr radeon = &context->radeon; - R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); - - if ((r700->sq_dirty || radeon->hw.all_dirty) == dirty) - r700SendSQConfig(context); - r700SendUCPState(context); - if ((r700->sc_dirty || radeon->hw.all_dirty) == dirty) - r700SendSCState(context); - if ((r700->su_dirty || radeon->hw.all_dirty) == dirty) - r700SendSUState(context); - if ((r700->cl_dirty || radeon->hw.all_dirty) == dirty) - r700SendCLState(context); - if ((r700->cb_dirty || radeon->hw.all_dirty) == dirty) - r700SendCBState(context); - if ((r700->db_dirty || radeon->hw.all_dirty) == dirty) - r700SendDBState(context); - if ((r700->sx_dirty || radeon->hw.all_dirty) == dirty) - r700SendSXState(context); - if ((r700->vgt_dirty || radeon->hw.all_dirty) == dirty) - r700SendVGTState(context); - if ((r700->spi_dirty || radeon->hw.all_dirty) == dirty) - r700SendSPIState(context); - if ((r700->viewport[0].dirty || radeon->hw.all_dirty) == dirty) - r700SendViewportState(context, 0); - if ((r700->render_target[0].dirty || radeon->hw.all_dirty) == dirty) - r700SendRenderTargetState(context, 0); - if ((r700->db_target_dirty || radeon->hw.all_dirty) == dirty) - r700SendDepthTargetState(context); - -} - -void r700EmitState(GLcontext * ctx) -{ - context_t *context = R700_CONTEXT(ctx); - radeonContextPtr radeon = &context->radeon; - - if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS)) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (radeon->vtbl.pre_emit_state) - radeon->vtbl.pre_emit_state(radeon); - - if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw.all_dirty) - return; - - rcommonEnsureCmdBufSpace(&context->radeon, - 652, __FUNCTION__); - - if (!radeon->cmdbuf.cs->cdw) { - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Begin reemit state\n"); - - r700EmitAtoms(ctx, GL_FALSE); - } - - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Begin dirty state\n"); - - r700EmitAtoms(ctx, GL_TRUE); - radeon->hw.is_dirty = GL_FALSE; - radeon->hw.all_dirty = GL_FALSE; - -} - static GLboolean r700RunRender(GLcontext * ctx, struct tnl_pipeline_stage *stage) { context_t *context = R700_CONTEXT(ctx); radeonContextPtr radeon = &context->radeon; - unsigned int i, ind_count = 0; + unsigned int i, ind_count = 0, id = 0; TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; + struct radeon_renderbuffer *rrb; for (i = 0; i < vb->PrimitiveCount; i++) ind_count += vb->Primitive[i].count + 10; /* just an estimate, need to properly calculate this */ rcommonEnsureCmdBufSpace(&context->radeon, - radeon->hw.max_state_size + ind_count, __FUNCTION__); + radeon->hw.max_state_size + ind_count + 1000, __FUNCTION__); r700Start3D(context); - r700UpdateShaders(ctx); r700SetScissor(context); r700SetupShaders(ctx); - - r700EmitState(ctx); + radeonEmitState(radeon); /* richard test code */ for (i = 0; i < vb->PrimitiveCount; i++) { @@ -434,6 +366,16 @@ static GLboolean r700RunRender(GLcontext * ctx, /* Flush render op cached for last several quads. */ r700WaitForIdleClean(context); + rrb = radeon_get_colorbuffer(&context->radeon); + if (!rrb || !rrb->bo) + r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM, + CB_ACTION_ENA_bit | (1 << (id + 6))); + + rrb = radeon_get_depthbuffer(&context->radeon); + if (!rrb || !rrb->bo) + r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM, + DB_ACTION_ENA_bit | DB_DEST_BASE_ENA_bit); + radeonReleaseArrays(ctx, ~0); return GL_FALSE; diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index ada394ec61..6b44cc0ceb 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -153,7 +153,7 @@ void r700UpdateViewportOffset(GLcontext * ctx) //------------------ /* Note: this should also modify whatever data the context reset * code uses... */ - R600_STATECHANGE(context, r700->viewport[id].dirty); + R600_STATECHANGE(context, vpt); r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx; r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty; } @@ -170,8 +170,8 @@ void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //--------------------- context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - R600_STATECHANGE(context, r700->render_target[0].dirty); - R600_STATECHANGE(context, r700->db_target_dirty); + R600_STATECHANGE(context, cb_target); + R600_STATECHANGE(context, db_target); r700SetRenderTarget(context, 0); r700SetDepthTarget(context); @@ -244,8 +244,8 @@ static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //----------- r700UpdateStateParameters(ctx, new_state); - R600_STATECHANGE(context, r700->cl_dirty); - R600_STATECHANGE(context, r700->spi_dirty); + R600_STATECHANGE(context, cl); + R600_STATECHANGE(context, spi); if(GL_TRUE == r700->bEnablePerspective) { @@ -278,7 +278,7 @@ static void r700SetDepthState(GLcontext * ctx) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - R600_STATECHANGE(context, r700->db_dirty); + R600_STATECHANGE(context, db); if (ctx->Depth.Test) { @@ -346,7 +346,7 @@ static void r700SetAlphaState(GLcontext * ctx) uint32_t alpha_func = REF_ALWAYS; GLboolean really_enabled = ctx->Color.AlphaEnabled; - R600_STATECHANGE(context, r700->sx_dirty); + R600_STATECHANGE(context, sx); switch (ctx->Color.AlphaFunc) { case GL_NEVER: @@ -400,7 +400,7 @@ static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //------------- context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - R600_STATECHANGE(context, r700->cb_dirty); + R600_STATECHANGE(context, cb); r700->CB_BLEND_RED.f32All = cf[0]; r700->CB_BLEND_GREEN.f32All = cf[1]; @@ -470,7 +470,7 @@ static void r700SetBlendState(GLcontext * ctx) int id = 0; uint32_t blend_reg = 0, eqn, eqnA; - R600_STATECHANGE(context, r700->cb_dirty); + R600_STATECHANGE(context, cb); if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) { SETfield(blend_reg, @@ -661,7 +661,7 @@ static void r700SetLogicOpState(GLcontext *ctx) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw); - R600_STATECHANGE(context, r700->cb_dirty); + R600_STATECHANGE(context, cb); if (RGBA_LOGICOP_ENABLED(ctx)) SETfield(r700->CB_COLOR_CONTROL.u32All, @@ -685,7 +685,7 @@ static void r700UpdateCulling(GLcontext * ctx) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw); - R600_STATECHANGE(context, r700->su_dirty); + R600_STATECHANGE(context, su); CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit); @@ -733,7 +733,7 @@ static void r700UpdateLineStipple(GLcontext * ctx) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw); - R600_STATECHANGE(context, r700->sc_dirty); + R600_STATECHANGE(context, sc); if (ctx->Line.StippleFlag) { @@ -817,7 +817,7 @@ static void r700ColorMask(GLcontext * ctx, (a ? 8 : 0)); if (mask != r700->CB_SHADER_MASK.u32All) { - R600_STATECHANGE(context, r700->cb_dirty); + R600_STATECHANGE(context, cb); SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask); } } @@ -875,7 +875,7 @@ static void r700ShadeModel(GLcontext * ctx, GLenum mode) //-------------------- context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - R600_STATECHANGE(context, r700->spi_dirty); + R600_STATECHANGE(context, spi); /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */ switch (mode) { @@ -898,7 +898,7 @@ static void r700PointSize(GLcontext * ctx, GLfloat size) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - R600_STATECHANGE(context, r700->su_dirty); + R600_STATECHANGE(context, su); /* We need to clamp to user defined range here, because * the HW clamping happens only for per vertex point size. */ @@ -920,7 +920,7 @@ static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * pa context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - R600_STATECHANGE(context, r700->su_dirty); + R600_STATECHANGE(context, su); /* format is 12.4 fixed point */ switch (pname) { @@ -1006,7 +1006,7 @@ static void r700SetStencilState(GLcontext * ctx, GLboolean state) } if (hw_stencil) { - R600_STATECHANGE(context, r700->db_dirty); + R600_STATECHANGE(context, db); if (state) SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit); else @@ -1024,7 +1024,7 @@ static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face, //fixme //r300CatchStencilFallback(ctx); - R600_STATECHANGE(context, r700->db_dirty); + R600_STATECHANGE(context, db); //front SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0], @@ -1055,7 +1055,7 @@ static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) / //fixme //r300CatchStencilFallback(ctx); - R600_STATECHANGE(context, r700->db_dirty); + R600_STATECHANGE(context, db); // front SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0], @@ -1077,7 +1077,7 @@ static void r700StencilOpSeparate(GLcontext * ctx, GLenum face, //fixme //r300CatchStencilFallback(ctx); - R600_STATECHANGE(context, r700->db_dirty); + R600_STATECHANGE(context, db); SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]), STENCILFAIL_shift, STENCILFAIL_mask); @@ -1121,7 +1121,7 @@ static void r700UpdateWindow(GLcontext * ctx, int id) //-------------------- GLfloat sz = v[MAT_SZ] * depthScale; GLfloat tz = v[MAT_TZ] * depthScale; - R600_STATECHANGE(context, r700->viewport[id].dirty); + R600_STATECHANGE(context, vpt); r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx; r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx; @@ -1160,7 +1160,7 @@ static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //--------------- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4)); - R600_STATECHANGE(context, r700->su_dirty); + R600_STATECHANGE(context, su); if (lineWidth > 0xFFFF) lineWidth = 0xFFFF; @@ -1173,7 +1173,7 @@ static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - R600_STATECHANGE(context, r700->sc_dirty); + R600_STATECHANGE(context, sc); SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask); SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask); @@ -1185,7 +1185,7 @@ static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - R600_STATECHANGE(context, r700->su_dirty); + R600_STATECHANGE(context, su); if (state) { SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit); @@ -1215,7 +1215,7 @@ static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) // factor *= 12.0; - R600_STATECHANGE(context, r700->su_dirty); + R600_STATECHANGE(context, su); r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor; r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant; @@ -1228,7 +1228,7 @@ static void r700UpdatePolygonMode(GLcontext * ctx) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - R600_STATECHANGE(context, r700->su_dirty); + R600_STATECHANGE(context, su); SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask); @@ -1305,7 +1305,7 @@ static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) p = (GLint) plane - (GLint) GL_CLIP_PLANE0; ip = (GLint *)ctx->Transform._ClipUserPlane[p]; - R600_STATECHANGE(context, r700->ucp[p].dirty); + R600_STATECHANGE(context, ucp); r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0]; r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1]; @@ -1321,7 +1321,7 @@ static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state) p = cap - GL_CLIP_PLANE0; - R600_STATECHANGE(context, r700->cl_dirty); + R600_STATECHANGE(context, cl); if (state) { r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p); @@ -1356,7 +1356,7 @@ void r700SetScissor(context_t *context) //--------------- y2 = rrb->dPriv->y + rrb->dPriv->h; } - R600_STATECHANGE(context, r700->sc_dirty); + R600_STATECHANGE(context, sc); /* window */ SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit); @@ -1426,8 +1426,8 @@ static void r700SetRenderTarget(context_t *context, int id) return; } - R600_STATECHANGE(context, r700->render_target[id].dirty); - R600_STATECHANGE(context, r700->cb_dirty); + R600_STATECHANGE(context, cb_target); + R600_STATECHANGE(context, cb); /* screen/window/view */ SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask); @@ -1475,8 +1475,7 @@ static void r700SetDepthTarget(context_t *context) if (!rrb) return; - R600_STATECHANGE(context, r700->db_target_dirty); - R600_STATECHANGE(context, r700->db_dirty); + R600_STATECHANGE(context, db_target); /* depth buf */ r700->DB_DEPTH_SIZE.u32All = 0; @@ -1538,7 +1537,7 @@ static void r700InitSQConfig(GLcontext * ctx) int num_gs_stack_entries; int num_es_stack_entries; - R600_STATECHANGE(context, r700->sq_dirty); + R600_STATECHANGE(context, sq); // SQ ps_prio = 0; diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index 13711963e2..ad4584a2bd 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -298,10 +298,6 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv ) GET_CURRENT_CONTEXT(ctx); radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL; -#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) /* +r6/r7 */ - __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; - radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); -#endif if (radeon == current) { radeon_firevertices(radeon); @@ -338,9 +334,6 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv ) rcommonDestroyCmdBuf(radeon); -#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) /* +r6/r7 */ - if (!IS_R600_CLASS(screen)) -#endif radeon_destroy_atom_list(radeon); if (radeon->state.scissor.pClipRects) { -- cgit v1.2.3 From becb50f84dc94f643dc480d6a2256518f1a5a854 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Sun, 23 Aug 2009 16:06:31 -0400 Subject: r600: bump reloc_chunk size This fixes openarena reloc errors. This needs to be made more dynamic. --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 38814b6d71..10ea766896 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -322,7 +322,7 @@ static int r600_cs_emit(struct radeon_cs *cs) struct drm_radeon_cs_chunk cs_chunk[2]; uint32_t length_dw_reloc_chunk; uint64_t chunk_ptrs[2]; - uint32_t reloc_chunk[128]; + uint32_t reloc_chunk[256]; int r; int retry = 0; -- cgit v1.2.3 From f758a8bf2e155725507bfe75add1fa81ccb569ae Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 24 Aug 2009 00:47:34 -0400 Subject: r600: switch to common cs functions needed for dri2. Pulled from Dave's WIP patch. --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 10 +++++----- src/mesa/drivers/dri/r600/r600_cmdbuf.h | 35 +++++++++------------------------ 2 files changed, 14 insertions(+), 31 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 10ea766896..a330d5b151 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -74,11 +74,11 @@ static struct radeon_cs * r600_cs_create(struct radeon_cs_manager *csm, return cs; } -int r600_cs_write_reloc(struct radeon_cs *cs, - struct radeon_bo *bo, - uint32_t read_domain, - uint32_t write_domain, - uint32_t flags) +static int r600_cs_write_reloc(struct radeon_cs *cs, + struct radeon_bo *bo, + uint32_t read_domain, + uint32_t write_domain, + uint32_t flags) { struct r600_cs_reloc_legacy *relocs; int i; diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.h b/src/mesa/drivers/dri/r600/r600_cmdbuf.h index 06eddf2eee..eba43d37b6 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.h +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.h @@ -134,40 +134,23 @@ struct r600_cs_reloc_legacy { uint32_t *reloc_indices; }; -extern int r600_cs_write_reloc(struct radeon_cs *cs, - struct radeon_bo *bo, - uint32_t read_domain, - uint32_t write_domain, - uint32_t flags); - -static inline void r600_cs_write_dword(struct radeon_cs *cs, uint32_t dword) -{ - cs->packets[cs->cdw++] = dword; - if (cs->section) { - cs->section_cdw++; - } -} - struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_context *ctx); /** * Write one dword to the command buffer. */ -#define R600_OUT_BATCH(data) \ - do { \ - r600_cs_write_dword(b_l_rmesa->cmdbuf.cs, data);\ - } while(0) +#define R600_OUT_BATCH(data) \ +do { \ + radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, data); \ +} while(0) /** * Write n dwords from ptr to the command buffer. */ -#define R600_OUT_BATCH_TABLE(ptr,n) \ - do { \ - int _i; \ - for (_i=0; _i < n; _i++) {\ - r600_cs_write_dword(b_l_rmesa->cmdbuf.cs, ptr[_i]);\ - }\ - } while(0) +#define R600_OUT_BATCH_TABLE(ptr,n) \ +do { \ + radeon_cs_write_table(b_l_rmesa->cmdbuf.cs, ptr, n); \ +} while(0) /** * Write a relocated dword to the command buffer. @@ -178,7 +161,7 @@ struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_cont fprintf(stderr, "(%s:%s:%d) offset : %d\n", \ __FILE__, __FUNCTION__, __LINE__, offset); \ } \ - r600_cs_write_reloc(b_l_rmesa->cmdbuf.cs, \ + radeon_cs_write_reloc(b_l_rmesa->cmdbuf.cs, \ bo, rd, wd, flags); \ } while(0) -- cgit v1.2.3 From 5d10890795d9bddc8cafc4afb19cacf164d6e667 Mon Sep 17 00:00:00 2001 From: Pauli Nieminen Date: Tue, 25 Aug 2009 21:46:32 +0300 Subject: radeon/r600: Fix remaining warnings when building 64 bit binary. --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 2 ++ src/mesa/drivers/dri/r600/r700_assembler.c | 4 ++-- src/mesa/drivers/dri/radeon/radeon_cmdbuf.h | 7 ++++--- src/mesa/drivers/dri/radeon/radeon_dma.c | 2 +- 4 files changed, 9 insertions(+), 6 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index a330d5b151..050d7bc6d0 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -304,6 +304,7 @@ static int r600_cs_set_age(struct radeon_cs *cs) /* -------------- */ return 0; } +#if 0 static void dump_cmdbuf(struct radeon_cs *cs) { int i; @@ -314,6 +315,7 @@ static void dump_cmdbuf(struct radeon_cs *cs) fprintf(stderr,"--end--\n"); } +#endif static int r600_cs_emit(struct radeon_cs *cs) { diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index eaacd06113..834c23593b 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -2132,7 +2132,7 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) alu_instruction_ptr->m_Word1_OP2.f6.write_mask = pAsm->D.dst.writew; break; default: - alu_instruction_ptr->m_Word1_OP2.f6.write_mask = SQ_SEL_MASK; + alu_instruction_ptr->m_Word1_OP2.f6.write_mask = 1; //SQ_SEL_MASK; break; } alu_instruction_ptr->m_Word1_OP2.f6.omod = SQ_ALU_OMOD_OFF; @@ -2161,7 +2161,7 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) alu_instruction_ptr->m_Word1_OP2.f.write_mask = pAsm->D.dst.writew; break; default: - alu_instruction_ptr->m_Word1_OP2.f.write_mask = SQ_SEL_MASK; + alu_instruction_ptr->m_Word1_OP2.f.write_mask = 1; //SQ_SEL_MASK; break; } alu_instruction_ptr->m_Word1_OP2.f.omod = SQ_ALU_OMOD_OFF; diff --git a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h index 410df4d665..6fcd1ce7ca 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h +++ b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h @@ -54,11 +54,12 @@ void rcommonBeginBatch(radeonContextPtr rmesa, */ #define OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) \ do { \ - if (0 && offset) { \ + int __offset = (offset); \ + if (0 && __offset) { \ fprintf(stderr, "(%s:%s:%d) offset : %d\n", \ - __FILE__, __FUNCTION__, __LINE__, offset); \ + __FILE__, __FUNCTION__, __LINE__, __offset); \ } \ - radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, offset); \ + radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, __offset); \ radeon_cs_write_reloc(b_l_rmesa->cmdbuf.cs, \ bo, rd, wd, flags); \ if (!b_l_rmesa->radeonScreen->kernel_mm) \ diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c index f15013c33b..51f764cf47 100644 --- a/src/mesa/drivers/dri/radeon/radeon_dma.c +++ b/src/mesa/drivers/dri/radeon/radeon_dma.c @@ -333,7 +333,7 @@ void radeonReleaseDmaRegions(radeonContextPtr rmesa) foreach(dma_bo, &rmesa->dma.reserved) ++reserved; - fprintf(stderr, "%s: free %u, wait %u, reserved %u, minimum_size: %u\n", + fprintf(stderr, "%s: free %zu, wait %zu, reserved %zu, minimum_size: %zu\n", __FUNCTION__, free, wait, reserved, rmesa->dma.minimum_size); } -- cgit v1.2.3 From 490f640cd58d215281076ae6e0e70649db6b0ed5 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 26 Aug 2009 12:17:44 -0400 Subject: r600: make reloc_chunk size dynamic --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 12 +++++++++--- src/mesa/drivers/dri/r600/r700_render.c | 3 +-- 2 files changed, 10 insertions(+), 5 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 050d7bc6d0..1734b0a89f 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -324,7 +324,7 @@ static int r600_cs_emit(struct radeon_cs *cs) struct drm_radeon_cs_chunk cs_chunk[2]; uint32_t length_dw_reloc_chunk; uint64_t chunk_ptrs[2]; - uint32_t reloc_chunk[256]; + uint32_t *reloc_chunk; int r; int retry = 0; @@ -333,8 +333,11 @@ static int r600_cs_emit(struct radeon_cs *cs) csm->pending_count = 1; - r = r600_cs_process_relocs(cs, &(reloc_chunk[0]), &length_dw_reloc_chunk); + reloc_chunk = (uint32_t*)calloc(1, cs->crelocs * 4 * 4); + + r = r600_cs_process_relocs(cs, reloc_chunk, &length_dw_reloc_chunk); if (r) { + free(reloc_chunk); return 0; } @@ -346,7 +349,7 @@ static int r600_cs_emit(struct radeon_cs *cs) /* reloc chaunk */ cs_chunk[1].chunk_id = RADEON_CHUNK_ID_RELOCS; cs_chunk[1].length_dw = length_dw_reloc_chunk; - cs_chunk[1].chunk_data = (unsigned long)&(reloc_chunk[0]); + cs_chunk[1].chunk_data = (unsigned long)reloc_chunk; chunk_ptrs[0] = (uint64_t)(unsigned long)&(cs_chunk[0]); chunk_ptrs[1] = (uint64_t)(unsigned long)&(cs_chunk[1]); @@ -364,6 +367,7 @@ static int r600_cs_emit(struct radeon_cs *cs) } while (r == -EAGAIN && retry < 1000); if (r) { + free(reloc_chunk); return r; } @@ -375,6 +379,8 @@ static int r600_cs_emit(struct radeon_cs *cs) cs->csm->vram_write_used = 0; cs->csm->gart_write_used = 0; + free(reloc_chunk); + return 0; } diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index d64e921bda..0b3ceb01ba 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -143,8 +143,7 @@ GLboolean r700SyncSurf(context_t *context, R600_OUT_BATCH_RELOC(0, pbo, 0, - read_domain, write_domain, 0); // ??? - + read_domain, write_domain, 0); END_BATCH(); COMMIT_BATCH(); -- cgit v1.2.3 From f988c750a9d3baa2c71f9fd1c0493daef93afc86 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 26 Aug 2009 13:08:49 -0400 Subject: r600: add missing radeon_cs_space_set_flush call fixes crash in etracer reported by kdekorte on IRC --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 1734b0a89f..65930ff589 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -487,6 +487,9 @@ void r600InitCmdBuf(context_t *r600) /* from rcommonInitCmdBuf */ assert(rmesa->cmdbuf.cs != NULL); rmesa->cmdbuf.size = size; + radeon_cs_space_set_flush(rmesa->cmdbuf.cs, + (void (*)(void *))rmesa->glCtx->Driver.Flush, rmesa->glCtx); + if (!rmesa->radeonScreen->kernel_mm) { radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]); radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, rmesa->radeonScreen->gartTextures.size); -- cgit v1.2.3 From b13a553dd419cc6997725d4bce956daa7eb64806 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 4 Sep 2009 14:03:51 -0400 Subject: r600: fix Elts handling Patch from taiu on IRC. fixes bug 23585 --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 12 ++++++++++-- src/mesa/drivers/dri/r600/r700_render.c | 7 ++++++- 2 files changed, 16 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r600_cmdbuf.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 65930ff589..3cfe03a45f 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -192,9 +192,9 @@ static int r600_cs_begin(struct radeon_cs *cs, if (cs->cdw + ndw > cs->ndw) { uint32_t tmp, *ptr; - int num = (ndw > 0x3FF) ? ndw : 0x3FF; + int num = (ndw > 0x400) ? ndw : 0x400; - tmp = (cs->cdw + 1 + num) & (~num); + tmp = (cs->cdw + num + 0x3FF) & (~0x3FF); ptr = (uint32_t*)realloc(cs->packets, 4 * tmp); if (ptr == NULL) { return -ENOMEM; @@ -229,6 +229,14 @@ static int r600_cs_end(struct radeon_cs *cs, return -EPIPE; } + if (cs->cdw > cs->ndw) { + fprintf(stderr, "CS section overflow at (%s,%s,%d) cdw %d ndw %d\n", + cs->section_file, cs->section_func, cs->section_line,cs->cdw,cs->ndw); + fprintf(stderr, "CS section end at (%s,%s,%d)\n", + file, func, line); + assert(0); + } + return 0; } diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index e1bbbfef35..3566bf3ca7 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -257,6 +257,8 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim uint32_t vgt_index_type = 0; uint32_t vgt_primitive_type = 0; uint32_t vgt_num_indices = 0; + TNLcontext *tnl = TNL_CONTEXT(ctx); + struct vertex_buffer *vb = &tnl->vb; type = r700PrimitiveType(prim); num_indices = r700NumVerts(end - start, prim); @@ -300,7 +302,10 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim R600_OUT_BATCH(vgt_draw_initiator); for (i = start; i < (start + num_indices); i++) { - R600_OUT_BATCH(i); + if(vb->Elts) + R600_OUT_BATCH(vb->Elts[i]); + else + R600_OUT_BATCH(i); } END_BATCH(); COMMIT_BATCH(); -- cgit v1.2.3