From cc893d9a98255d3c26df7123ba5cc02e478c9328 Mon Sep 17 00:00:00 2001 From: Kevin DeKorte Date: Mon, 20 Jul 2009 18:56:47 -0400 Subject: r600: fix dst reg indexing This fixes segfaults in apps like teapot and tunnel --- src/mesa/drivers/dri/r600/r700_assembler.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_assembler.c') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 1d41c5cf78..2d40dfa708 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -2193,6 +2193,7 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) GLboolean next_ins(r700_AssemblerBase *pAsm) { struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); + uint index; if( GL_TRUE == IsTex(pILInst->Opcode) ) { @@ -2213,14 +2214,20 @@ GLboolean next_ins(r700_AssemblerBase *pAsm) if(pAsm->D.dst.rtype == DST_REG_OUT) { + if (pAsm->starting_export_register_number >= pAsm->D.dst.reg) { + index = 0; + } else { + index = pAsm->D.dst.reg - pAsm->starting_export_register_number; + } + if(pAsm->D.dst.op3) { // There is no mask for OP3 instructions, so all channels are written - pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number] = 0xF; + pAsm->pucOutMask[index] = 0xF; } else { - pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number] + pAsm->pucOutMask[index] |= (unsigned char)pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask; } } -- cgit v1.2.3 From 7edb2a9eef698c386042e6cead68ac516ec15616 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 21 Jul 2009 17:44:36 -0400 Subject: Revert "r600: fix dst reg indexing" This reverts commit cc893d9a98255d3c26df7123ba5cc02e478c9328. Richard has the proper fix. --- src/mesa/drivers/dri/r600/r700_assembler.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_assembler.c') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 2d40dfa708..1d41c5cf78 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -2193,7 +2193,6 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) GLboolean next_ins(r700_AssemblerBase *pAsm) { struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); - uint index; if( GL_TRUE == IsTex(pILInst->Opcode) ) { @@ -2214,20 +2213,14 @@ GLboolean next_ins(r700_AssemblerBase *pAsm) if(pAsm->D.dst.rtype == DST_REG_OUT) { - if (pAsm->starting_export_register_number >= pAsm->D.dst.reg) { - index = 0; - } else { - index = pAsm->D.dst.reg - pAsm->starting_export_register_number; - } - if(pAsm->D.dst.op3) { // There is no mask for OP3 instructions, so all channels are written - pAsm->pucOutMask[index] = 0xF; + pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number] = 0xF; } else { - pAsm->pucOutMask[index] + pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number] |= (unsigned char)pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask; } } -- cgit v1.2.3 From 0f6d3aece7b193dcacbd94f87ac734ee3a44b366 Mon Sep 17 00:00:00 2001 From: Cooper Yuan Date: Wed, 29 Jul 2009 15:23:56 +0800 Subject: R6xx/r7xx: VS export fog color as parameter --- src/mesa/drivers/dri/r600/r700_assembler.c | 16 ++++++++++++++++ src/mesa/drivers/dri/r600/r700_fragprog.c | 6 ++++++ 2 files changed, 22 insertions(+) (limited to 'src/mesa/drivers/dri/r600/r700_assembler.c') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 1d41c5cf78..ebd5ff106b 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -4014,6 +4014,22 @@ GLboolean Process_Vertex_Exports(r700_AssemblerBase *pR700AsmCode, export_starting_index++; } + unBit = 1 << VERT_RESULT_FOGC; + if(OutputsWritten & unBit) + { + if( GL_FALSE == Process_Export(pR700AsmCode, + SQ_EXPORT_PARAM, + export_starting_index, + 1, + pR700AsmCode->ucVP_OutputMap[VERT_RESULT_FOGC], + GL_FALSE) ) + { + return GL_FALSE; + } + + export_starting_index++; + } + for(i=0; i<8; i++) { unBit = 1 << (VERT_RESULT_TEX0 + i); diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index 88e66491ba..a473dfe888 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -67,6 +67,12 @@ void Map_Fragment_Program(r700_AssemblerBase *pAsm, pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1] = pAsm->number_used_registers++; } + unBit = 1 << FRAG_ATTRIB_FOGC; + if(mesa_fp->Base.InputsRead & unBit) + { + pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC] = pAsm->number_used_registers++; + } + for(i=0; i<8; i++) { unBit = 1 << (FRAG_ATTRIB_TEX0 + i); -- cgit v1.2.3 From 86ac0ae0b09566d0cd66dcfc17192780f7e2df03 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Sat, 1 Aug 2009 20:55:43 -0400 Subject: r600: fix rectangle textures It might be better to add an instruction to normalize the coordinates for rectanglular textures as there are some limitations to wrap modes on unnormalized tex coords. fixes texrect --- src/mesa/drivers/dri/r600/r700_assembler.c | 36 +++++++++++++++++++++--------- src/mesa/drivers/dri/r600/r700_assembler.h | 2 +- 2 files changed, 27 insertions(+), 11 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_assembler.c') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index ebd5ff106b..0abf112b55 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -1205,7 +1205,7 @@ GLboolean tex_src(r700_AssemblerBase *pAsm) return GL_TRUE; } -GLboolean assemble_tex_instruction(r700_AssemblerBase *pAsm) +GLboolean assemble_tex_instruction(r700_AssemblerBase *pAsm, GLboolean normalized) { PVSSRC * texture_coordinate_source; PVSSRC * texture_unit_source; @@ -1227,10 +1227,18 @@ GLboolean assemble_tex_instruction(r700_AssemblerBase *pAsm) tex_instruction_ptr->m_Word0.f.resource_id = texture_unit_source->reg; tex_instruction_ptr->m_Word1.f.lod_bias = 0x0; - tex_instruction_ptr->m_Word1.f.coord_type_x = SQ_TEX_NORMALIZED; - tex_instruction_ptr->m_Word1.f.coord_type_y = SQ_TEX_NORMALIZED; - tex_instruction_ptr->m_Word1.f.coord_type_z = SQ_TEX_NORMALIZED; - tex_instruction_ptr->m_Word1.f.coord_type_w = SQ_TEX_NORMALIZED; + if (normalized) { + tex_instruction_ptr->m_Word1.f.coord_type_x = SQ_TEX_NORMALIZED; + tex_instruction_ptr->m_Word1.f.coord_type_y = SQ_TEX_NORMALIZED; + tex_instruction_ptr->m_Word1.f.coord_type_z = SQ_TEX_NORMALIZED; + tex_instruction_ptr->m_Word1.f.coord_type_w = SQ_TEX_NORMALIZED; + } else { + /* XXX: UNNORMALIZED tex coords have limited wrap modes */ + tex_instruction_ptr->m_Word1.f.coord_type_x = SQ_TEX_UNNORMALIZED; + tex_instruction_ptr->m_Word1.f.coord_type_y = SQ_TEX_UNNORMALIZED; + tex_instruction_ptr->m_Word1.f.coord_type_z = SQ_TEX_UNNORMALIZED; + tex_instruction_ptr->m_Word1.f.coord_type_w = SQ_TEX_UNNORMALIZED; + } tex_instruction_ptr->m_Word2.f.offset_x = 0x0; tex_instruction_ptr->m_Word2.f.offset_y = 0x0; @@ -2196,11 +2204,19 @@ GLboolean next_ins(r700_AssemblerBase *pAsm) if( GL_TRUE == IsTex(pILInst->Opcode) ) { - if( GL_FALSE == assemble_tex_instruction(pAsm) ) - { - r700_error(ERROR_ASM_TEXINSTRUCTION, "Error assembling TEX instruction"); - return GL_FALSE; - } + if (pILInst->TexSrcTarget == TEXTURE_RECT_INDEX) { + if( GL_FALSE == assemble_tex_instruction(pAsm, GL_FALSE) ) + { + r700_error(ERROR_ASM_TEXINSTRUCTION, "Error assembling TEX instruction"); + return GL_FALSE; + } + } else { + if( GL_FALSE == assemble_tex_instruction(pAsm, GL_TRUE) ) + { + r700_error(ERROR_ASM_TEXINSTRUCTION, "Error assembling TEX instruction"); + return GL_FALSE; + } + } } else { //ALU diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index e9b21b802e..f9c4d849c6 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -424,7 +424,7 @@ GLboolean assemble_src(r700_AssemblerBase *pAsm, GLboolean assemble_dst(r700_AssemblerBase *pAsm); GLboolean tex_dst(r700_AssemblerBase *pAsm); GLboolean tex_src(r700_AssemblerBase *pAsm); -GLboolean assemble_tex_instruction(r700_AssemblerBase *pAsm); +GLboolean assemble_tex_instruction(r700_AssemblerBase *pAsm, GLboolean normalized); void initialize(r700_AssemblerBase *pAsm); GLboolean assemble_alu_src(R700ALUInstruction* alu_instruction_ptr, int source_index, -- cgit v1.2.3 From 1e52b8b4e02c887cb493e5e2bde902b54e9c72fd Mon Sep 17 00:00:00 2001 From: Cooper Yuan Date: Wed, 12 Aug 2009 17:39:18 +0800 Subject: r600: A shader is bound that exports Z as a float into Red channel --- src/mesa/drivers/dri/r600/r700_assembler.c | 3 +++ src/mesa/drivers/dri/r600/r700_fragprog.c | 1 + 2 files changed, 4 insertions(+) (limited to 'src/mesa/drivers/dri/r600/r700_assembler.c') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 0abf112b55..eaacd06113 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -3839,6 +3839,9 @@ GLboolean Process_Export(r700_AssemblerBase* pAsm, if (export_count == 1) { ucWriteMask = pAsm->pucOutMask[starting_register_number - pAsm->starting_export_register_number]; + /* exports Z as a float into Red channel */ + if (GL_TRUE == is_depth_export) + ucWriteMask = 0x1; if( (ucWriteMask & 0x1) != 0) { diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index efeea905c1..6249bde6f1 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -118,6 +118,7 @@ void Map_Fragment_Program(r700_AssemblerBase *pAsm, pAsm->uiFP_OutputMap[FRAG_RESULT_DEPTH] = pAsm->number_used_registers++; pAsm->number_of_exports++; pAsm->number_of_colorandz_exports++; + pAsm->pR700Shader->depthIsExported = 1; } pAsm->pucOutMask = (unsigned char*) MALLOC(pAsm->number_of_exports); -- cgit v1.2.3