From 27c07b6b28cb5d9f0b2ba446846670a234e48228 Mon Sep 17 00:00:00 2001 From: Richard Li Date: Tue, 21 Apr 2009 12:54:20 -0400 Subject: Initial pull of code from r6xx-r7xx-support branch Not functional yet. --- src/mesa/drivers/dri/r600/r700_render.c | 462 ++++++++++++++++++++++++++++++++ 1 file changed, 462 insertions(+) create mode 100644 src/mesa/drivers/dri/r600/r700_render.c (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c new file mode 100644 index 0000000000..fce99ada54 --- /dev/null +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -0,0 +1,462 @@ +/* + * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Richard Li , + * CooperYuan , + */ + +#include "main/glheader.h" +#include "main/state.h" +#include "main/imports.h" +#include "main/enums.h" +#include "main/macros.h" +#include "main/context.h" +#include "main/dd.h" +#include "main/simple_list.h" +#include "main/api_arrayelt.h" +#include "swrast/swrast.h" +#include "swrast_setup/swrast_setup.h" +#include "vbo/vbo.h" + +#include "tnl/tnl.h" +#include "tnl/t_vp_build.h" +#include "tnl/t_context.h" +#include "tnl/t_vertex.h" +#include "tnl/t_pipeline.h" + +#include "r600_context.h" + +#include "r700_chip.h" + +/* to be enable +#include "r700_vertprog.h" +#include "r700_fragprog.h" +#include "r700_state.h" +#include "r700_tex.h" +#include "r700_emit.h" +*/ + +#if 0 // to be enable +void r700WaitForIdle(context_t *context) +{ + R700EP3 (context, IT_SET_CONFIG_REG, 1); + R700E32 (context, mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); + R700E32 (context, 1 << 15); +} + +void r700WaitForIdleClean(context_t *context) +{ + R700EP3 (context, IT_EVENT_WRITE, 0); + R700E32 (context, 0x16); + + R700EP3 (context, IT_SET_CONFIG_REG, 1); + R700E32 (context, mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); + R700E32 (context, 1 << 17); +} + +static void r700Start3D(context_t *context) +{ + if (context->screen->chip.type <= CHIP_TYPE_RV670) + { + R700EP3 (context, IT_START_3D_CMDBUF, 1); + R700E32 (context, 0); + } + + R700EP3 (context, IT_CONTEXT_CONTROL, 1); + R700E32 (context, 0x80000000); + R700E32 (context, 0x80000000); + r700WaitForIdleClean(context); +} + + +static int r700SetupStreams(GLcontext * ctx) +{ + context_t *context = R700_CONTEXT(ctx); + + struct r700_vertex_program *vpc + = (struct r700_vertex_program *)ctx->VertexProgram._Current; + + TNLcontext *tnl = TNL_CONTEXT(ctx); + struct vertex_buffer *vb = &tnl->vb; + + unsigned int unBit; + unsigned int i; + + R700_CMDBUF_CHECK_SPACE(6); + R700EP3 (context, IT_SET_CTL_CONST, 1); + R700E32 (context, mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); + R700E32 (context, 0); + + R700EP3 (context, IT_SET_CTL_CONST, 1); + R700E32 (context, mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX); + R700E32 (context, 0); + + context->aos_count = 0; + for(i=0; imesa_program.Base.InputsRead & unBit) + { + (context->chipobj.EmitVec)(ctx, + &(context->aos[context->aos_count]), + vb->AttribPtr[i]->data, + vb->AttribPtr[i]->size, + vb->AttribPtr[i]->stride, + vb->Count); + + context->aos[context->aos_count].aos_size = vb->AttribPtr[i]->size; + + /* currently aos are packed */ + r700SetupVTXConstans(ctx, + i, + (unsigned int)context->aos[context->aos_count].aos_offset, + (unsigned int)vb->AttribPtr[i]->size, + (unsigned int)(vb->AttribPtr[i]->size * 4), + (unsigned int)vb->Count); + /* TODO : enable this after MemUse fixed *= + (context->chipobj.MemUse)(context, context->aos[context->aos_count].buf->id); + */ + + context->aos_count++; + } + } + for(i=context->aos_count; iaos[i].buf = NULL; + } + + return R600_FALLBACK_NONE; +} + +static GLboolean r700SetupShaders(GLcontext * ctx) +{ + context_t *context = R700_CONTEXT(ctx); + + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + + GLuint exportCount; + + r700->SQ_PGM_RESOURCES_PS.u32All = 0; + r700->SQ_PGM_RESOURCES_VS.u32All = 0; + + SETbit(r700->SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); + SETbit(r700->SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); + + r700SetupVertexProgram(ctx); + + r700SetupFragmentProgram(ctx); + + exportCount = (r700->SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift); + r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1; + + return GL_TRUE; +} + +GLboolean r700SendTextureState(context_t *context) +{ + unsigned int i; + + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + + for(i=0; itexture_states.textures[i] != 0) + { + R700_CMDBUF_CHECK_SPACE(9); + R700EP3 (context, IT_SET_RESOURCE, 7); + R700E32 (context, i * 7); + R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE0.u32All); + R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE1.u32All); + R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE2.u32All); + R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE3.u32All); + R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE4.u32All); + R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE5.u32All); + R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE6.u32All); + } + + if(r700->texture_states.samplers[i] != 0) + { + R700_CMDBUF_CHECK_SPACE(5); + R700EP3 (context, IT_SET_SAMPLER, 3); + R700E32 (context, i * 3); // Base at 0x7000 + R700E32 (context, r700->texture_states.samplers[i]->SQ_TEX_SAMPLER0.u32All); + R700E32 (context, r700->texture_states.samplers[i]->SQ_TEX_SAMPLER1.u32All); + R700E32 (context, r700->texture_states.samplers[i]->SQ_TEX_SAMPLER2.u32All); + } + } + + return GL_TRUE; +} + +GLboolean r700SyncSurf(context_t *context) +{ + /* TODO : too heavy? */ + unsigned int CP_COHER_CNTL = 0; + + CP_COHER_CNTL |= TC_ACTION_ENA_bit + |VC_ACTION_ENA_bit + |CB_ACTION_ENA_bit + |DB_ACTION_ENA_bit + |SH_ACTION_ENA_bit + |SMX_ACTION_ENA_bit; + + + R700_CMDBUF_CHECK_SPACE(5); + R700EP3(context, IT_SURFACE_SYNC, 3); + R700E32(context, CP_COHER_CNTL); + R700E32(context, 0xFFFFFFFF); + R700E32(context, 0x00000000); + R700E32(context, 10); + + return GL_TRUE; +} + +static void r700SetRenderTarget(context_t *context) +{ + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + + r700->CB_COLOR0_BASE.u32All = context->target.rt.gpu >> 8; +} + +unsigned int r700PrimitiveType(int prim) +{ + switch (prim & PRIM_MODE_MASK) + { + case GL_POINTS: + return DI_PT_POINTLIST; + break; + case GL_LINES: + return DI_PT_LINELIST; + break; + case GL_LINE_STRIP: + return DI_PT_LINESTRIP; + break; + case GL_LINE_LOOP: + return DI_PT_LINELOOP; + break; + case GL_TRIANGLES: + return DI_PT_TRILIST; + break; + case GL_TRIANGLE_STRIP: + return DI_PT_TRISTRIP; + break; + case GL_TRIANGLE_FAN: + return DI_PT_TRIFAN; + break; + case GL_QUADS: + return DI_PT_QUADLIST; + break; + case GL_QUAD_STRIP: + return DI_PT_QUADSTRIP; + break; + case GL_POLYGON: + return DI_PT_POLYGON; + break; + default: + assert(0); + return -1; + break; + } +} + +#endif // to be enable + +static GLboolean r700RunRender(GLcontext * ctx, + struct tnl_pipeline_stage *stage) +{ +#if 0 // to be enable + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + unsigned int i, j; + TNLcontext *tnl = TNL_CONTEXT(ctx); + struct vertex_buffer *vb = &tnl->vb; + + struct r700_fragment_program *fp = (struct r700_fragment_program *) + (ctx->FragmentProgram._Current); + if (context->screen->chip.type <= CHIP_TYPE_RV670) + { + fp->r700AsmCode.bR6xx = 1; + } + + r700Start3D(context); /* TODO : this is too much. */ + + r700SyncSurf(context); /* TODO : make it light. */ + + r700UpdateShaders(ctx); + + r700SetRenderTarget(context); + + if(r700SetupStreams(ctx)) + { + return GL_TRUE; + } + + r700UpdateTextureState(context); + r700SendTextureState(context); + + if(GL_FALSE == fp->translated) + { + if( GL_FALSE == r700TranslateFragmentShader(fp, &(fp->mesa_program)) ) + { + return GL_TRUE; + } + } + + r700SetupShaders(ctx); + + /* set a valid base address to make the command checker happy */ + r700->SQ_PGM_START_FS.u32All = r700->SQ_PGM_START_PS.u32All; + r700->SQ_PGM_START_ES.u32All = r700->SQ_PGM_START_PS.u32All; + r700->SQ_PGM_START_GS.u32All = r700->SQ_PGM_START_PS.u32All; + + r700SendContextStates(context); + + /* richard test code */ + for (i = 0; i < vb->PrimitiveCount; i++) + { + GLuint prim = _tnl_translate_prim(&vb->Primitive[i]); + GLuint start = vb->Primitive[i].start; + GLuint end = vb->Primitive[i].start + vb->Primitive[i].count; + GLuint numIndices = vb->Primitive[i].count; + GLuint numEntires; + //r300RunRenderPrimitive(rmesa, ctx, start, end, prim); + + unsigned int VGT_DRAW_INITIATOR = 0; + unsigned int VGT_INDEX_TYPE = 0; + unsigned int VGT_PRIMITIVE_TYPE = 0; + unsigned int VGT_NUM_INDICES = 0; + + numEntires = 2 /* VGT_INDEX_TYPE */ + + 3 /* VGT_PRIMITIVE_TYPE */ + + numIndices + 3 /* DRAW_INDEX_IMMD */ + + 2; /* test stamp */ + + R700_CMDBUF_CHECK_SPACE(numEntires); + + VGT_INDEX_TYPE |= DI_INDEX_SIZE_32_BIT << INDEX_TYPE_shift; + + R700EP3(context, IT_INDEX_TYPE, 0); + R700E32(context, VGT_INDEX_TYPE); + + VGT_NUM_INDICES = numIndices; + + VGT_PRIMITIVE_TYPE |= r700PrimitiveType(prim) << VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift; + R700EP3(context, IT_SET_CONFIG_REG, 1); + R700E32(context, mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); + R700E32(context, VGT_PRIMITIVE_TYPE); + + VGT_DRAW_INITIATOR |= DI_SRC_SEL_IMMEDIATE << SOURCE_SELECT_shift; + VGT_DRAW_INITIATOR |= DI_MAJOR_MODE_0 << MAJOR_MODE_shift; + + R700EP3(context, IT_DRAW_INDEX_IMMD, (numIndices + 1)); + R700E32(context, VGT_NUM_INDICES); + R700E32(context, VGT_DRAW_INITIATOR); + + for (j=0; jchipobj.FlushCmdBuffer)(context); + + /* free aos => TODO : cache mgr */ + for (i = 0; i < context->aos_count; i++) + { + (context->chipobj.FreeDmaRegion)(context, &(context->aos[i])); + } +#endif // to be enable + return GL_FALSE; +} + +static GLboolean r700RunNonTCLRender(GLcontext * ctx, + struct tnl_pipeline_stage *stage) /* -------------------- */ +{ + GLboolean bRet = GL_TRUE; + + return bRet; +} + +static GLboolean r700RunTCLRender(GLcontext * ctx, /*----------------------*/ + struct tnl_pipeline_stage *stage) +{ + GLboolean bRet = GL_FALSE; + +#if 0 // to be enable + context_t *context = R700_CONTEXT(ctx); + + r700UpdateShaders(ctx); +#endif // to be enable + + bRet = r700RunRender(ctx, stage); + + return bRet; + //GL_FALSE will stop to do other pipe stage in _tnl_run_pipeline + //The render here DOES finish the whole pipe, so GL_FALSE should be returned for success. +} + +const struct tnl_pipeline_stage _r700_render_stage = { + "r700 Hardware Rasterization", + NULL, + NULL, + NULL, + NULL, + r700RunNonTCLRender +}; + +const struct tnl_pipeline_stage _r700_tcl_stage = { + "r700 Hardware Transform, Clipping and Lighting", + NULL, + NULL, + NULL, + NULL, + r700RunTCLRender +}; + +const struct tnl_pipeline_stage *r700_pipeline[] = +{ + &_r700_tcl_stage, + &_tnl_vertex_transform_stage, + &_tnl_normal_transform_stage, + &_tnl_lighting_stage, + &_tnl_fog_coordinate_stage, + &_tnl_texgen_stage, + &_tnl_texture_transform_stage, + &_tnl_vertex_program_stage, + + &_r700_render_stage, + &_tnl_render_stage, + 0, +}; + + -- cgit v1.2.3 From e2dcebd2e6b2af6269a5ece6d6ced73ec8bb4a47 Mon Sep 17 00:00:00 2001 From: Richard Li Date: Fri, 8 May 2009 19:23:45 -0400 Subject: R6xx/R7xx: WIP r6xx-rewrite code --- src/mesa/drivers/dri/r600/Makefile | 3 + src/mesa/drivers/dri/r600/r600_cmdbuf.c | 589 ++++++++++++++++++++++++- src/mesa/drivers/dri/r600/r600_cmdbuf.h | 167 +++++++ src/mesa/drivers/dri/r600/r600_context.c | 69 +-- src/mesa/drivers/dri/r600/r600_context.h | 39 +- src/mesa/drivers/dri/r600/r600_emit.c | 224 +++++++++- src/mesa/drivers/dri/r600/r600_emit.h | 257 ++--------- src/mesa/drivers/dri/r600/r700_chip.c | 248 ++++++++++- src/mesa/drivers/dri/r600/r700_chip.h | 11 +- src/mesa/drivers/dri/r600/r700_clear.c | 117 +++-- src/mesa/drivers/dri/r600/r700_fragprog.c | 50 ++- src/mesa/drivers/dri/r600/r700_fragprog.h | 8 +- src/mesa/drivers/dri/r600/r700_ioctl.c | 28 +- src/mesa/drivers/dri/r600/r700_oglprog.c | 26 +- src/mesa/drivers/dri/r600/r700_render.c | 217 ++++----- src/mesa/drivers/dri/r600/r700_state.c | 265 ++++++----- src/mesa/drivers/dri/r600/r700_state.h | 1 + src/mesa/drivers/dri/r600/r700_tex.c | 24 +- src/mesa/drivers/dri/r600/r700_tex.h | 2 + src/mesa/drivers/dri/r600/r700_vertprog.c | 80 +--- src/mesa/drivers/dri/r600/r700_vertprog.h | 10 +- src/mesa/drivers/dri/radeon/radeon_cmdbuf.h | 124 +----- src/mesa/drivers/dri/radeon/radeon_common.c | 4 +- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 138 +++--- src/mesa/drivers/dri/radeon/radeon_fbo.c | 4 +- src/mesa/drivers/dri/radeon/radeon_screen.c | 11 +- 26 files changed, 1788 insertions(+), 928 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/Makefile b/src/mesa/drivers/dri/r600/Makefile index 00c56c03cd..474a3167b4 100644 --- a/src/mesa/drivers/dri/r600/Makefile +++ b/src/mesa/drivers/dri/r600/Makefile @@ -48,9 +48,12 @@ DRIVER_SOURCES = \ r700_fragprog.c \ r700_vertprog.c \ r700_shader.c \ + r700_shaderinst.c \ r700_ioctl.c \ r700_oglprog.c \ r700_chip.c \ + r700_state.c \ + r700_clear.c \ r700_render.c \ r700_tex.c \ r700_debug.c \ diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index bc14f9a755..8550457566 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -28,11 +28,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. **************************************************************************/ /** - * \file - * - * \author Nicolai Haehnle + * Mostly coppied from \radeon\radeon_cs_legacy.c */ +#include + #include "main/glheader.h" #include "main/state.h" #include "main/imports.h" @@ -52,11 +52,582 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_mipmap_tree.h" #include "radeon_reg.h" -/** - * Allocate memory for the command buffer and initialize the state atom - * list. Note that the initial hardware state is set by r600InitState(). - */ -void r600InitCmdBuf(r600ContextPtr r600) +struct r600_cs_manager_legacy { - rcommonInitCmdBuf(&r600->radeon); + struct radeon_cs_manager base; + struct radeon_context *ctx; + /* hack for scratch stuff */ + uint32_t pending_age; + uint32_t pending_count; +}; + +struct r600_cs_reloc_legacy { + struct radeon_cs_reloc base; + uint32_t cindices; + uint32_t *indices; + uint32_t *reloc_indices; + struct offset_modifiers offset_mod; +}; + +static struct radeon_cs * r600_cs_create(struct radeon_cs_manager *csm, + uint32_t ndw) +{ + struct radeon_cs *cs; + + cs = (struct radeon_cs*)calloc(1, sizeof(struct radeon_cs)); + if (cs == NULL) { + return NULL; + } + cs->csm = csm; + cs->ndw = (ndw + 0x3FF) & (~0x3FF); + cs->packets = (uint32_t*)malloc(4*cs->ndw); + if (cs->packets == NULL) { + free(cs); + return NULL; + } + cs->relocs_total_size = 0; + return cs; +} + +int r600_cs_write_reloc(struct radeon_cs *cs, + struct radeon_bo *bo, + uint32_t read_domain, + uint32_t write_domain, + uint32_t flags, + offset_modifiers* poffset_mod) +{ + struct r600_cs_reloc_legacy *relocs; + int i; + + relocs = (struct r600_cs_reloc_legacy *)cs->relocs; + /* check domains */ + if ((read_domain && write_domain) || (!read_domain && !write_domain)) { + /* in one CS a bo can only be in read or write domain but not + * in read & write domain at the same sime + */ + return -EINVAL; + } + if (read_domain == RADEON_GEM_DOMAIN_CPU) { + return -EINVAL; + } + if (write_domain == RADEON_GEM_DOMAIN_CPU) { + return -EINVAL; + } + /* check if bo is already referenced */ + for(i = 0; i < cs->crelocs; i++) { + uint32_t *indices; + uint32_t *reloc_indices; + + if (relocs[i].base.bo->handle == bo->handle) { + /* Check domains must be in read or write. As we check already + * checked that in argument one of the read or write domain was + * set we only need to check that if previous reloc as the read + * domain set then the read_domain should also be set for this + * new relocation. + */ + if (relocs[i].base.read_domain && !read_domain) { + return -EINVAL; + } + if (relocs[i].base.write_domain && !write_domain) { + return -EINVAL; + } + relocs[i].base.read_domain |= read_domain; + relocs[i].base.write_domain |= write_domain; + /* save indice */ + relocs[i].cindices++; + indices = (uint32_t*)realloc(relocs[i].indices, + relocs[i].cindices * 4); + reloc_indices = (uint32_t*)realloc(relocs[i].reloc_indices, + relocs[i].cindices * 4); + if ( (indices == NULL) || (reloc_indices == NULL) ) { + relocs[i].cindices -= 1; + return -ENOMEM; + } + relocs[i].indices = indices; + relocs[i].reloc_indices = reloc_indices; + relocs[i].indices[relocs[i].cindices - 1] = cs->cdw - 1; + relocs[i].reloc_indices[relocs[i].cindices - 1] = cs->section_cdw; + cs->section_ndw += 2; + cs->section_cdw += 2; + + relocs[i].offset_mod.shift = poffset_mod->shift; + relocs[i].offset_mod.shiftbits = poffset_mod->shiftbits; + relocs[i].offset_mod.mask = poffset_mod->mask; + + return 0; + } + } + /* add bo to reloc */ + relocs = (struct r600_cs_reloc_legacy*) + realloc(cs->relocs, + sizeof(struct r600_cs_reloc_legacy) * (cs->crelocs + 1)); + if (relocs == NULL) { + return -ENOMEM; + } + cs->relocs = relocs; + relocs[cs->crelocs].base.bo = bo; + relocs[cs->crelocs].base.read_domain = read_domain; + relocs[cs->crelocs].base.write_domain = write_domain; + relocs[cs->crelocs].base.flags = flags; + relocs[cs->crelocs].indices = (uint32_t*)malloc(4); + relocs[cs->crelocs].reloc_indices = (uint32_t*)malloc(4); + if ( (relocs[cs->crelocs].indices == NULL) || (relocs[cs->crelocs].reloc_indices == NULL) ) + { + return -ENOMEM; + } + relocs[cs->crelocs].offset_mod.shift = poffset_mod->shift; + relocs[cs->crelocs].offset_mod.shiftbits = poffset_mod->shiftbits; + relocs[cs->crelocs].offset_mod.mask = poffset_mod->mask; + + relocs[cs->crelocs].indices[0] = cs->cdw - 1; + relocs[cs->crelocs].reloc_indices[0] = cs->section_cdw; + cs->section_ndw += 2; + cs->section_cdw += 2; + relocs[cs->crelocs].cindices = 1; + cs->relocs_total_size += radeon_bo_legacy_relocs_size(bo); + cs->crelocs++; + + radeon_bo_ref(bo); + return 0; +} + +static int r600_cs_begin(struct radeon_cs *cs, + uint32_t ndw, + const char *file, + const char *func, + int line) +{ + if (cs->section) { + fprintf(stderr, "CS already in a section(%s,%s,%d)\n", + cs->section_file, cs->section_func, cs->section_line); + fprintf(stderr, "CS can't start section(%s,%s,%d)\n", + file, func, line); + return -EPIPE; + } + + if (cs->cdw + ndw + 32 > cs->ndw) { /* Left 32 DWORD (8 offset+pitch) spare room for reloc indices */ + uint32_t tmp, *ptr; + int num = (ndw > 0x3FF) ? ndw : 0x3FF; + + tmp = (cs->cdw + 1 + num) & (~num); + ptr = (uint32_t*)realloc(cs->packets, 4 * tmp); + if (ptr == NULL) { + return -ENOMEM; + } + cs->packets = ptr; + cs->ndw = tmp; + } + + cs->section = 1; + cs->section_ndw = 0; + cs->section_cdw = cs->cdw + ndw; /* start of reloc indices. */ + cs->section_file = file; + cs->section_func = func; + cs->section_line = line; + + return 0; +} + +static int r600_cs_end(struct radeon_cs *cs, + const char *file, + const char *func, + int line) + +{ + if (!cs->section) { + fprintf(stderr, "CS no section to end at (%s,%s,%d)\n", + file, func, line); + return -EPIPE; + } + cs->section = 0; + + if ( (cs->section_ndw + cs->cdw) != cs->section_cdw ) + { + fprintf(stderr, "CS section size missmatch start at (%s,%s,%d) %d vs %d\n", + cs->section_file, cs->section_func, cs->section_line, cs->section_ndw, cs->section_cdw); + fprintf(stderr, "CS section end at (%s,%s,%d)\n", + file, func, line); + return -EPIPE; + } + + cs->cdw = cs->section_cdw; + return 0; +} + +static int r600_cs_process_relocs(struct radeon_cs *cs, + uint32_t * reloc_chunk, + uint32_t * length_dw_reloc_chunk) +{ + struct r600_cs_manager_legacy *csm = (struct r600_cs_manager_legacy*)cs->csm; + struct r600_cs_reloc_legacy *relocs; + int i, j, r; + + uint32_t offset_dw = 0; + + csm = (struct r600_cs_manager_legacy*)cs->csm; + relocs = (struct r600_cs_reloc_legacy *)cs->relocs; +restart: + for (i = 0; i < cs->crelocs; i++) + { + for (j = 0; j < relocs[i].cindices; j++) + { + uint32_t soffset, eoffset, asicoffset; + + r = radeon_bo_legacy_validate(relocs[i].base.bo, + &soffset, &eoffset); + if (r == -EAGAIN) + { + goto restart; + } + if (r) + { + fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", + relocs[i].base.bo, soffset, eoffset); + return r; + } + asicoffset = cs->packets[relocs[i].indices[j]] + soffset; + if (asicoffset >= eoffset) + { + /* radeon_bo_debug(relocs[i].base.bo, 12); */ + fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", + relocs[i].base.bo, soffset, eoffset); + fprintf(stderr, "above end: %p 0x%08X 0x%08X\n", + relocs[i].base.bo, + cs->packets[relocs[i].indices[j]], + eoffset); + exit(0); + return -EINVAL; + } + /* apply offset operator */ + switch (relocs[i].offset_mod.shift) + { + case NO_SHIFT: + asicoffset = asicoffset & relocs[i].offset_mod.mask; + break; + case LEFT_SHIFT: + asicoffset = (asicoffset << relocs[i].offset_mod.shiftbits) & relocs[i].offset_mod.mask; + break; + case RIGHT_SHIFT: + asicoffset = (asicoffset >> relocs[i].offset_mod.shiftbits) & relocs[i].offset_mod.mask; + break; + default: + break; + }; + + /* pkt3 nop header in ib chunk */ + cs->packets[relocs[i].reloc_indices[j]] = 0xC0001000; + + /* reloc index in ib chunk */ + cs->packets[relocs[i].reloc_indices[j] + 1] = offset_dw; + + /* asic offset in reloc chunk */ /* see alex drm r600_nomm_relocate */ + reloc_chunk[offset_dw] = asicoffset; + reloc_chunk[offset_dw + 3] = 0; + + offset_dw += 4; + } + } + + *length_dw_reloc_chunk = offset_dw; + + return 0; +} + +static int r600_cs_set_age(struct radeon_cs *cs) /* -------------- */ +{ + struct r600_cs_manager_legacy *csm = (struct r600_cs_manager_legacy*)cs->csm; + struct r600_cs_reloc_legacy *relocs; + int i; + + relocs = (struct r600_cs_reloc_legacy *)cs->relocs; + for (i = 0; i < cs->crelocs; i++) { + radeon_bo_legacy_pending(relocs[i].base.bo, csm->pending_age); + radeon_bo_unref(relocs[i].base.bo); + } + return 0; +} + +static int r600_cs_emit(struct radeon_cs *cs) +{ + struct r600_cs_manager_legacy *csm = (struct r600_cs_manager_legacy*)cs->csm; + struct drm_radeon_cs cs_cmd; + struct drm_radeon_cs_chunk cs_chunk[2]; + drm_radeon_cmd_buffer_t cmd; + /* drm_r300_cmd_header_t age; */ + uint32_t length_dw_reloc_chunk; + uint64_t ull; + uint64_t * chunk_ptrs[2]; + uint32_t reloc_chunk[128]; + int r; + int retry = 0; + + /* TODO : put chip level things here if need. */ + /* csm->ctx->vtbl.emit_cs_header(cs, csm->ctx); */ + + /* TODO : append buffer age */ + + r = r600_cs_process_relocs(cs, &(reloc_chunk[0]), &length_dw_reloc_chunk); + if (r) { + return 0; + } + + /* raw ib chunk */ + cs_chunk[0].chunk_id = RADEON_CHUNK_ID_IB; + cs_chunk[0].length_dw = cs->cdw; + cs_chunk[0].chunk_data = (uint64_t)(cs->packets); + + /* reloc chaunk */ + cs_chunk[1].chunk_id = RADEON_CHUNK_ID_RELOCS; + cs_chunk[1].length_dw = length_dw_reloc_chunk; + cs_chunk[1].chunk_data = (uint64_t)&(reloc_chunk[0]); + + chunk_ptrs[0] = (uint64_t * )&(cs_chunk[0]); + chunk_ptrs[1] = (uint64_t * )&(cs_chunk[1]); + + cs_cmd.num_chunks = 2; + cs_cmd.cs_id = 0; + cs_cmd.chunks = (uint64_t)&(chunk_ptrs[0]); + + /* dump_cmdbuf(cs); */ + + do + { + r = drmCommandWriteRead(cs->csm->fd, DRM_RADEON_CS, &cs_cmd, sizeof(cs_cmd)); + retry++; + } while (r == -EAGAIN && retry < 1000); + + if (r) { + return r; + } + + r600_cs_set_age(cs); + + cs->csm->read_used = 0; + cs->csm->vram_write_used = 0; + cs->csm->gart_write_used = 0; + + return 0; +} + +static void inline r600_cs_free_reloc(void *relocs_p, int crelocs) +{ + struct r600_cs_reloc_legacy *relocs = relocs_p; + int i; + if (!relocs_p) + return; + for (i = 0; i < crelocs; i++) + { + free(relocs[i].indices); + free(relocs[i].reloc_indices); + } +} + +static int r600_cs_destroy(struct radeon_cs *cs) +{ + r600_cs_free_reloc(cs->relocs, cs->crelocs); + free(cs->relocs); + free(cs->packets); + free(cs); + return 0; +} + +static int r600_cs_erase(struct radeon_cs *cs) +{ + r600_cs_free_reloc(cs->relocs, cs->crelocs); + free(cs->relocs); + cs->relocs_total_size = 0; + cs->relocs = NULL; + cs->crelocs = 0; + cs->cdw = 0; + cs->section = 0; + return 0; +} + +static int r600_cs_need_flush(struct radeon_cs *cs) +{ + /* this function used to flush when the BO usage got to + * a certain size, now the higher levels handle this better */ + return 0; +} + +static void r600_cs_print(struct radeon_cs *cs, FILE *file) +{ +} + +static int r600_cs_check_space(struct radeon_cs *cs, struct radeon_cs_space_check *bos, int num_bo) +{ + struct radeon_cs_manager *csm = cs->csm; + int this_op_read = 0, this_op_gart_write = 0, this_op_vram_write = 0; + uint32_t read_domains, write_domain; + int i; + struct radeon_bo *bo; + + /* check the totals for this operation */ + + if (num_bo == 0) + return 0; + + /* prepare */ + for (i = 0; i < num_bo; i++) + { + bo = bos[i].bo; + + bos[i].new_accounted = 0; + read_domains = bos[i].read_domains; + write_domain = bos[i].write_domain; + + /* pinned bos don't count */ + if (radeon_legacy_bo_is_static(bo)) + continue; + + /* already accounted this bo */ + if (write_domain && (write_domain == bo->space_accounted)) + continue; + + if (read_domains && ((read_domains << 16) == bo->space_accounted)) + continue; + + if (bo->space_accounted == 0) + { + if (write_domain == RADEON_GEM_DOMAIN_VRAM) + this_op_vram_write += bo->size; + else if (write_domain == RADEON_GEM_DOMAIN_GTT) + this_op_gart_write += bo->size; + else + this_op_read += bo->size; + bos[i].new_accounted = (read_domains << 16) | write_domain; + } + else + { + uint16_t old_read, old_write; + + old_read = bo->space_accounted >> 16; + old_write = bo->space_accounted & 0xffff; + + if (write_domain && (old_read & write_domain)) + { + bos[i].new_accounted = write_domain; + /* moving from read to a write domain */ + if (write_domain == RADEON_GEM_DOMAIN_VRAM) + { + this_op_read -= bo->size; + this_op_vram_write += bo->size; + } + else if (write_domain == RADEON_GEM_DOMAIN_VRAM) + { + this_op_read -= bo->size; + this_op_gart_write += bo->size; + } + } + else if (read_domains & old_write) + { + bos[i].new_accounted = bo->space_accounted & 0xffff; + } + else + { + /* rewrite the domains */ + if (write_domain != old_write) + fprintf(stderr,"WRITE DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, write_domain, old_write); + if (read_domains != old_read) + fprintf(stderr,"READ DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, read_domains, old_read); + return RADEON_CS_SPACE_FLUSH; + } + } + } + + if (this_op_read < 0) + this_op_read = 0; + + /* check sizes - operation first */ + if ((this_op_read + this_op_gart_write > csm->gart_limit) || + (this_op_vram_write > csm->vram_limit)) { + return RADEON_CS_SPACE_OP_TO_BIG; + } + + if (((csm->vram_write_used + this_op_vram_write) > csm->vram_limit) || + ((csm->read_used + csm->gart_write_used + this_op_gart_write + this_op_read) > csm->gart_limit)) { + return RADEON_CS_SPACE_FLUSH; + } + + csm->gart_write_used += this_op_gart_write; + csm->vram_write_used += this_op_vram_write; + csm->read_used += this_op_read; + /* commit */ + for (i = 0; i < num_bo; i++) { + bo = bos[i].bo; + bo->space_accounted = bos[i].new_accounted; + } + + return RADEON_CS_SPACE_OK; +} + +static struct radeon_cs_funcs r600_cs_funcs = { + r600_cs_create, + r600_cs_write_reloc, + r600_cs_begin, + r600_cs_end, + r600_cs_emit, + r600_cs_destroy, + r600_cs_erase, + r600_cs_need_flush, + r600_cs_print, + r600_cs_check_space +}; + +struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_context *ctx) +{ + struct r600_cs_manager_legacy *csm; + + csm = (struct r600_cs_manager_legacy*) + calloc(1, sizeof(struct r600_cs_manager_legacy)); + if (csm == NULL) { + return NULL; + } + csm->base.funcs = &r600_cs_funcs; + csm->base.fd = ctx->dri.fd; + csm->ctx = ctx; + csm->pending_age = 1; + return (struct radeon_cs_manager*)csm; +} + +void r600InitCmdBuf(r600ContextPtr r600) /* from rcommonInitCmdBuf */ +{ + radeonContextPtr rmesa = &r600->radeon; + + GLuint size; + /* Initialize command buffer */ + size = 256 * driQueryOptioni(&rmesa->optionCache, + "command_buffer_size"); + if (size < 2 * rmesa->hw.max_state_size) { + size = 2 * rmesa->hw.max_state_size + 65535; + } + if (size > 64 * 256) + size = 64 * 256; + + if (rmesa->radeonScreen->kernel_mm) { + int fd = rmesa->radeonScreen->driScreen->fd; + rmesa->cmdbuf.csm = radeon_cs_manager_gem_ctor(fd); + } else { + rmesa->cmdbuf.csm = r600_radeon_cs_manager_legacy_ctor(rmesa); + } + if (rmesa->cmdbuf.csm == NULL) { + /* FIXME: fatal error */ + return; + } + rmesa->cmdbuf.cs = radeon_cs_create(rmesa->cmdbuf.csm, size); + assert(rmesa->cmdbuf.cs != NULL); + rmesa->cmdbuf.size = size; + + if (!rmesa->radeonScreen->kernel_mm) { + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]); + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, rmesa->radeonScreen->gartTextures.size); + } else { + struct drm_radeon_gem_info mminfo; + + if (!drmCommandWriteRead(rmesa->dri.fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo))) + { + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, mminfo.vram_visible); + radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, mminfo.gart_size); + } + } } diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.h b/src/mesa/drivers/dri/r600/r600_cmdbuf.h index 1bab9c5821..dbb723b2b5 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.h +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.h @@ -37,6 +37,173 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define __R600_CMDBUF_H__ #include "r600_context.h" +#include "r600_emit.h" + +#define RADEON_CP_PACKET3_NOP 0xC0001000 +#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900 +#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 +#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00 +#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 +#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400 +#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 +#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800 +#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 +#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 +#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 +#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 +#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 +#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 +#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 +#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 +#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500 +#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 +#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 +#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 +#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 + +/* r6xx/r7xx packet 3 type offsets */ +#define R600_SET_CONFIG_REG_OFFSET 0x00008000 +#define R600_SET_CONFIG_REG_END 0x0000ac00 +#define R600_SET_CONTEXT_REG_OFFSET 0x00028000 +#define R600_SET_CONTEXT_REG_END 0x00029000 +#define R600_SET_ALU_CONST_OFFSET 0x00030000 +#define R600_SET_ALU_CONST_END 0x00032000 +#define R600_SET_RESOURCE_OFFSET 0x00038000 +#define R600_SET_RESOURCE_END 0x0003c000 +#define R600_SET_SAMPLER_OFFSET 0x0003c000 +#define R600_SET_SAMPLER_END 0x0003cff0 +#define R600_SET_CTL_CONST_OFFSET 0x0003cff0 +#define R600_SET_CTL_CONST_END 0x0003e200 +#define R600_SET_LOOP_CONST_OFFSET 0x0003e200 +#define R600_SET_LOOP_CONST_END 0x0003e380 +#define R600_SET_BOOL_CONST_OFFSET 0x0003e380 +#define R600_SET_BOOL_CONST_END 0x00040000 + +/* r6xx/r7xx packet 3 types */ +#define R600_IT_INDIRECT_BUFFER_END 0x00001700 +#define R600_IT_SET_PREDICATION 0x00002000 +#define R600_IT_REG_RMW 0x00002100 +#define R600_IT_COND_EXEC 0x00002200 +#define R600_IT_PRED_EXEC 0x00002300 +#define R600_IT_START_3D_CMDBUF 0x00002400 +#define R600_IT_DRAW_INDEX_2 0x00002700 +#define R600_IT_CONTEXT_CONTROL 0x00002800 +#define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900 +#define R600_IT_INDEX_TYPE 0x00002A00 +#define R600_IT_DRAW_INDEX 0x00002B00 +#define R600_IT_DRAW_INDEX_AUTO 0x00002D00 +#define R600_IT_DRAW_INDEX_IMMD 0x00002E00 +#define R600_IT_NUM_INSTANCES 0x00002F00 +#define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400 +#define R600_IT_INDIRECT_BUFFER_MP 0x00003800 +#define R600_IT_MEM_SEMAPHORE 0x00003900 +#define R600_IT_MPEG_INDEX 0x00003A00 +#define R600_IT_WAIT_REG_MEM 0x00003C00 +#define R600_IT_MEM_WRITE 0x00003D00 +#define R600_IT_INDIRECT_BUFFER 0x00003200 +#define R600_IT_CP_INTERRUPT 0x00004000 +#define R600_IT_SURFACE_SYNC 0x00004300 +#define R600_IT_ME_INITIALIZE 0x00004400 +#define R600_IT_COND_WRITE 0x00004500 +#define R600_IT_EVENT_WRITE 0x00004600 +#define R600_IT_EVENT_WRITE_EOP 0x00004700 +#define R600_IT_ONE_REG_WRITE 0x00005700 +#define R600_IT_SET_CONFIG_REG 0x00006800 +#define R600_IT_SET_CONTEXT_REG 0x00006900 +#define R600_IT_SET_ALU_CONST 0x00006A00 +#define R600_IT_SET_BOOL_CONST 0x00006B00 +#define R600_IT_SET_LOOP_CONST 0x00006C00 +#define R600_IT_SET_RESOURCE 0x00006D00 +#define R600_IT_SET_SAMPLER 0x00006E00 +#define R600_IT_SET_CTL_CONST 0x00006F00 +#define R600_IT_SURFACE_BASE_UPDATE 0x00007300 + +extern int r600_cs_write_reloc(struct radeon_cs *cs, + struct radeon_bo *bo, + uint32_t read_domain, + uint32_t write_domain, + uint32_t flags, + offset_modifiers* poffset_mod); + +static inline void r600_cs_write_dword(struct radeon_cs *cs, uint32_t dword) +{ + cs->packets[cs->cdw++] = dword; +} + +/** + * Write one dword to the command buffer. + */ +#define R600_OUT_BATCH(data) \ + do { \ + r600_cs_write_dword(b_l_rmesa->cmdbuf.cs, data);\ + } while(0) + +/** + * Write n dwords from ptr to the command buffer. + */ +#define R600_OUT_BATCH_TABLE(ptr,n) \ + do { \ + int _i; \ + for (_i=0; _i < n; _i++) {\ + r600_cs_write_dword(b_l_rmesa->cmdbuf.cs, ptr[_i]);\ + }\ + } while(0) + +/** + * Write a relocated dword to the command buffer. + */ +#define R600_OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags, offset_mod) \ + do { \ + if (0 && offset) { \ + fprintf(stderr, "(%s:%s:%d) offset : %d\n", \ + __FILE__, __FUNCTION__, __LINE__, offset); \ + } \ + r600_cs_write_dword(b_l_rmesa->cmdbuf.cs, offset); \ + r600_cs_write_reloc(b_l_rmesa->cmdbuf.cs, \ + bo, rd, wd, flags, offset_mod); \ + } while(0) + +/* R600/R700 */ +#define R600_OUT_BATCH_REGS(reg, num) \ +do { \ + if ((reg) >= R600_SET_CONFIG_REG_OFFSET && (reg) < R600_SET_CONFIG_REG_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, (num))); \ + OUT_BATCH(((reg) - R600_SET_CONFIG_REG_OFFSET) >> 2); \ + } else if ((reg) >= R600_SET_CONTEXT_REG_OFFSET && (reg) < R600_SET_CONTEXT_REG_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_CONTEXT_REG, (num))); \ + OUT_BATCH(((reg) - R600_SET_CONTEXT_REG_OFFSET) >> 2); \ + } else if ((reg) >= R600_SET_ALU_CONST_OFFSET && (reg) < R600_SET_ALU_CONST_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (num))); \ + OUT_BATCH(((reg) - R600_SET_ALU_CONST_OFFSET) >> 2); \ + } else if ((reg) >= R600_SET_RESOURCE_OFFSET && (reg) < R600_SET_RESOURCE_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, (num))); \ + OUT_BATCH(((reg) - R600_SET_RESOURCE_OFFSET) >> 2); \ + } else if ((reg) >= R600_SET_SAMPLER_OFFSET && (reg) < R600_SET_SAMPLER_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, (num))); \ + OUT_BATCH(((reg) - R600_SET_SAMPLER_OFFSET) >> 2); \ + } else if ((reg) >= R600_SET_CTL_CONST_OFFSET && (reg) < R600_SET_CTL_CONST_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, (num))); \ + OUT_BATCH(((reg) - R600_SET_CTL_CONST_OFFSET) >> 2); \ + } else if ((reg) >= R600_SET_LOOP_CONST_OFFSET && (reg) < R600_SET_LOOP_CONST_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_LOOP_CONST, (num))); \ + OUT_BATCH(((reg) - R600_SET_LOOP_CONST_OFFSET) >> 2); \ + } else if ((reg) >= R600_SET_BOOL_CONST_OFFSET && (reg) < R600_SET_BOOL_CONST_END) { \ + OUT_BATCH(CP_PACKET3(R600_IT_SET_BOOL_CONST, (num))); \ + OUT_BATCH(((reg) - R600_SET_BOOL_CONST_OFFSET) >> 2); \ + } else { \ + OUT_BATCH(CP_PACKET0((reg), (num))); \ + } \ +} while (0) + +/** Single register write to command buffer; requires 3 dwords for most things. */ +#define R600_OUT_BATCH_REGVAL(reg, val) \ + R600_OUT_BATCH_REGS((reg), 1); \ + OUT_BATCH((val)) + +/** Continuous register range write to command buffer; requires 1 dword, + * expects count dwords afterwards for register contents. */ +#define R600_OUT_BATCH_REGSEQ(reg, count) \ + R600_OUT_BATCH_REGS((reg), (count)) extern void r600InitCmdBuf(r600ContextPtr r600); diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 1b43f68ac2..3c8ba003d4 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -156,42 +156,6 @@ const struct dri_extension gl_20_extension[] = { }; -extern struct tnl_pipeline_stage _r600_render_stage; -extern const struct tnl_pipeline_stage _r600_tcl_stage; - -static const struct tnl_pipeline_stage *r600_pipeline[] = { - - /* Try and go straight to t&l - */ - &_r600_tcl_stage, - - /* Catch any t&l fallbacks - */ - &_tnl_vertex_transform_stage, - &_tnl_normal_transform_stage, - &_tnl_lighting_stage, - &_tnl_fog_coordinate_stage, - &_tnl_texgen_stage, - &_tnl_texture_transform_stage, - &_tnl_vertex_program_stage, - - /* Try again to go to tcl? - * - no good for asymmetric-twoside (do with multipass) - * - no good for asymmetric-unfilled (do with multipass) - * - good for material - * - good for texgen - * - need to manipulate a bit of state - * - * - worth it/not worth it? - */ - - /* Else do them here. - */ - &_r600_render_stage, - &_tnl_render_stage, /* FALLBACK */ - 0, -}; - static void r600RunPipeline(GLcontext * ctx) { _mesa_lock_context_textures(ctx); @@ -244,31 +208,6 @@ static void r600_init_vtbl(radeonContextPtr radeon) radeon->vtbl.fallback = r600_fallback; } -/* to be enabled */ -static void r600EmitShader(GLcontext * ctx, - struct r600_dma_region *rvb, - GLvoid * data, - int sizeinDWORD) -{ -} -/* to be enabled */ -static void r600FreeDmaRegion(context_t *context, - struct r600_dma_region *region) -{ -} -/* to be enabled */ -static void r600EmitVec(GLcontext * ctx, - struct r600_dma_region *rvb, - GLvoid * data, - int size, - int stride, - int count) -{ -} -/* to be enabled */ -static void r600ReleaseArrays(GLcontext * ctx) -{ -} /* to be enabled */ static GLboolean r600LoadMemSurf(context_t *context, GLuint dst_offset, /* gpu addr */ @@ -287,6 +226,7 @@ static GLboolean r600AllocMemSurf(context_t *context, GLuint *prefered_heap, /* Now used RADEON_LOCAL_TEX_HEAP, return actual heap used. */ GLuint totalSize) { + return GL_TRUE; } /* to be enabled */ static int r600FlushCmdBuffer(context_t *context) @@ -332,6 +272,7 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, */ driParseConfigFiles(&r600->radeon.optionCache, &screen->optionCache, screen->driScreen->myNum, "r600"); + r600->radeon.initialMaxAnisotropy = driQueryOptionf(&r600->radeon.optionCache, "def_max_anisotropy"); @@ -344,9 +285,10 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, (r600->chipobj.InitFuncs)(&functions); r600->chipobj.EmitShader = r600EmitShader; + r600->chipobj.DeleteShader = r600DeleteShader; r600->chipobj.FreeDmaRegion = r600FreeDmaRegion; r600->chipobj.EmitVec = r600EmitVec; - r600->chipobj.ReleaseArrays = r600ReleaseArrays; + r600->chipobj.ReleaseArrays = r600ReleaseVec; r600->chipobj.LoadMemSurf = r600LoadMemSurf; r600->chipobj.AllocMemSurf = r600AllocMemSurf; r600->chipobj.FlushCmdBuffer = r600FlushCmdBuffer; @@ -476,8 +418,9 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, radeonInitSpanFuncs( ctx ); r600InitCmdBuf(r600); + + (r600->chipobj.InitState)(r600->radeon.glCtx); #if 0 /* to be enabled */ - r600InitState(r600); if (!(screen->chip_flags & RADEON_CHIPSET_TCL)) r600InitSwtcl(ctx); #endif diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index 74e34e3684..70108b74c4 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -140,26 +140,19 @@ struct r600_swtcl_info { GLubyte vertex_attr_count; }; -/* to be enabled */ /* DELETE FOLLOWING 2 SRTUCTS */ -struct r600_dma_buffer +enum { - int refcount; /* the number of retained regions in buf */ - drmBufPtr buf; - int id; + NO_SHIFT = 0, + LEFT_SHIFT = 1, + RIGHT_SHIFT = 2, }; -struct r600_dma_region + +typedef struct offset_modifiers { - struct r600_dma_buffer *buf; - char *address; /* == buf->address */ - int start; - int end; - int ptr; /* offsets from start of buf */ - - int aos_offset; /* address in GART memory */ - int aos_stride; /* distance between elements, in dwords */ - int aos_size; /* number of components (1-4) */ -}; -/* ----------------------- */ + GLuint shift; + GLuint shiftbits; + GLuint mask; +} offset_modifiers; typedef struct chip_object { @@ -175,14 +168,16 @@ typedef struct chip_object GLuint (*GetTexObjSize)(void); /* ------------ IN ------------------- */ - void (*EmitShader)( GLcontext * ctx, - struct r600_dma_region *rvb, + GLboolean (*EmitShader)( GLcontext * ctx, + void ** shaderbo, GLvoid * data, int sizeinDWORD); + GLboolean (*DeleteShader)(GLcontext * ctx, + void * shaderbo); void (*FreeDmaRegion)( GLcontext * ctx, - struct r600_dma_region *region); - void (*EmitVec)(GLcontext * ctx, - struct r600_dma_region *rvb, + void * shaderbo); + GLboolean (*EmitVec)(GLcontext * ctx, + struct radeon_aos *aos, GLvoid * data, int size, int stride, diff --git a/src/mesa/drivers/dri/r600/r600_emit.c b/src/mesa/drivers/dri/r600/r600_emit.c index 9d43873c4d..fc8f987cab 100644 --- a/src/mesa/drivers/dri/r600/r600_emit.c +++ b/src/mesa/drivers/dri/r600/r600_emit.c @@ -1,9 +1,8 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. +/************************************************************************** + +Copyright 2008, 2009 Advanced Micro Devices Inc. (AMD) -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. +Copyright (C) Advanced Micro Devices Inc. (AMD) 2009. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the @@ -27,10 +26,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. **************************************************************************/ -/** - * \file - * - * \author Keith Whitwell +/* + * Authors: + * Richard Li , + * CooperYuan , */ #include "main/glheader.h" @@ -48,6 +47,105 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r600_context.h" #include "r600_emit.h" +#if defined(USE_X86_ASM) +#define COPY_DWORDS( dst, src, nr ) \ +do { \ + int __tmp; \ + __asm__ __volatile__( "rep ; movsl" \ + : "=%c" (__tmp), "=D" (dst), "=S" (__tmp) \ + : "0" (nr), \ + "D" ((long)dst), \ + "S" ((long)src) ); \ +} while (0) +#else +#define COPY_DWORDS( dst, src, nr ) \ +do { \ + int j; \ + for ( j = 0 ; j < nr ; j++ ) \ + dst[j] = ((int *)src)[j]; \ + dst += nr; \ +} while (0) +#endif + +static void r600EmitVec4(uint32_t *out, GLvoid * data, int stride, int count) +{ + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); + + if (stride == 4) + COPY_DWORDS(out, data, count); + else + for (i = 0; i < count; i++) { + out[0] = *(int *)data; + out++; + data += stride; + } +} + +static void r600EmitVec8(uint32_t *out, GLvoid * data, int stride, int count) +{ + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); + + if (stride == 8) + COPY_DWORDS(out, data, count * 2); + else + for (i = 0; i < count; i++) { + out[0] = *(int *)data; + out[1] = *(int *)(data + 4); + out += 2; + data += stride; + } +} + +static void r600EmitVec12(uint32_t *out, GLvoid * data, int stride, int count) +{ + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); + + if (stride == 12) { + COPY_DWORDS(out, data, count * 3); + } + else + for (i = 0; i < count; i++) { + out[0] = *(int *)data; + out[1] = *(int *)(data + 4); + out[2] = *(int *)(data + 8); + out += 3; + data += stride; + } +} + +static void r600EmitVec16(uint32_t *out, GLvoid * data, int stride, int count) +{ + int i; + + if (RADEON_DEBUG & DEBUG_VERTS) + fprintf(stderr, "%s count %d stride %d out %p data %p\n", + __FUNCTION__, count, stride, (void *)out, (void *)data); + + if (stride == 16) + COPY_DWORDS(out, data, count * 4); + else + for (i = 0; i < count; i++) { + out[0] = *(int *)data; + out[1] = *(int *)(data + 4); + out[2] = *(int *)(data + 8); + out[3] = *(int *)(data + 12); + out += 4; + data += stride; + } +} + /* Emit vertex data to GART memory * Route inputs to the vertex processor * This function should never return R600_FALLBACK_TCL when using software tcl. @@ -73,3 +171,111 @@ void r600EmitCacheFlush(r600ContextPtr rmesa) COMMIT_BATCH(); */ } + +GLboolean r600EmitShader(GLcontext * ctx, + void ** shaderbo, + GLvoid * data, + int sizeinDWORD) +{ + radeonContextPtr radeonctx = RADEON_CONTEXT(ctx); + + struct radeon_bo * pbo; + uint32_t *out; + +shader_again_alloc: + pbo = radeon_bo_open(radeonctx->radeonScreen->bom, + 0, + sizeinDWORD * 4, + 256, + RADEON_GEM_DOMAIN_GTT, + 0); + + if (!pbo) + { + rcommonFlushCmdBuf(radeonctx, __FUNCTION__); + goto shader_again_alloc; + } + + radeon_validate_bo(radeonctx, pbo, RADEON_GEM_DOMAIN_GTT, 0); + + if (radeon_revalidate_bos(radeonctx->glCtx) == GL_FALSE) + { + fprintf(stderr,"failure to revalidate BOs - badness\n"); + } + + radeon_bo_map(pbo, 1); + + radeon_bo_ref(pbo); + + out = (uint32_t*)(pbo->ptr); + + memcpy(out, data, sizeinDWORD * 4); + + *shaderbo = (void*)pbo; + + return GL_TRUE; +} + +GLboolean r600DeleteShader(GLcontext * ctx, + void * shaderbo) +{ + struct radeon_bo * pbo = (struct radeon_bo *)shaderbo; + + radeon_bo_unmap(pbo); + radeon_bo_unref(pbo); /* when bo->cref <= 0, bo will be bo_free */ + + return GL_TRUE; +} + +GLboolean r600EmitVec(GLcontext * ctx, + struct radeon_aos *aos, + GLvoid * data, + int size, + int stride, + int count) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + uint32_t *out; + + if (stride == 0) + { + radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); + aos->stride = 0; + } + else + { + radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); + aos->stride = size; + } + + aos->components = size; + aos->count = count; + + out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); + switch (size) { + case 1: r600EmitVec4(out, data, stride, count); break; + case 2: r600EmitVec8(out, data, stride, count); break; + case 3: r600EmitVec12(out, data, stride, count); break; + case 4: r600EmitVec16(out, data, stride, count); break; + default: + assert(0); + break; + } + + return GL_TRUE; +} + +void r600ReleaseVec(GLcontext * ctx) +{ + radeonReleaseArrays(ctx, ~0); +} + +void r600FreeDmaRegion(context_t *context, + void * shaderbo) +{ + struct radeon_bo *pbo = (struct radeon_bo *)shaderbo; + if(pbo) + { + radeon_bo_unref(pbo); + } +} diff --git a/src/mesa/drivers/dri/r600/r600_emit.h b/src/mesa/drivers/dri/r600/r600_emit.h index 3e1cf1ff5f..11765c868c 100644 --- a/src/mesa/drivers/dri/r600/r600_emit.h +++ b/src/mesa/drivers/dri/r600/r600_emit.h @@ -1,41 +1,38 @@ -/* - * Copyright (C) 2005 Vladimir Dergachev. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ +/************************************************************************** + +Copyright 2008, 2009 Advanced Micro Devices Inc. (AMD) + +Copyright (C) Advanced Micro Devices Inc. (AMD) 2009. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ /* * Authors: - * Vladimir Dergachev - * Nicolai Haehnle - * Aapo Tahkola - * Ben Skeggs - * Jerome Glisse + * Richard Li , + * CooperYuan , */ -/* This files defines functions for accessing R600 hardware. - */ + #ifndef __R600_EMIT_H__ #define __R600_EMIT_H__ @@ -44,180 +41,24 @@ #include "r600_cmdbuf.h" #include "radeon_reg.h" -static INLINE uint32_t cmdpacket0(struct radeon_screen *rscrn, - int reg, int count) -{ - if (count) { - return CP_PACKET0(reg, count - 1); - } - return CP_PACKET2; -} - -static INLINE uint32_t cmdvpu(struct radeon_screen *rscrn, int addr, int count) -{ - drm_r300_cmd_header_t cmd; - - cmd.u = 0; - cmd.vpu.cmd_type = R300_CMD_VPU; - cmd.vpu.count = count; - cmd.vpu.adrhi = ((unsigned int)addr & 0xFF00) >> 8; - cmd.vpu.adrlo = ((unsigned int)addr & 0x00FF); - - return cmd.u; -} - -static INLINE uint32_t cmdr500fp(struct radeon_screen *rscrn, - int addr, int count, int type, int clamp) -{ - drm_r300_cmd_header_t cmd; - - cmd.u = 0; - cmd.r500fp.cmd_type = R300_CMD_R500FP; - cmd.r500fp.count = count; - cmd.r500fp.adrhi_flags = ((unsigned int)addr & 0x100) >> 8; - cmd.r500fp.adrhi_flags |= type ? R500FP_CONSTANT_TYPE : 0; - cmd.r500fp.adrhi_flags |= clamp ? R500FP_CONSTANT_CLAMP : 0; - cmd.r500fp.adrlo = ((unsigned int)addr & 0x00FF); - - return cmd.u; -} - -static INLINE uint32_t cmdpacket3(struct radeon_screen *rscrn, int packet) -{ - drm_r300_cmd_header_t cmd; - - cmd.u = 0; - cmd.packet3.cmd_type = R300_CMD_PACKET3; - cmd.packet3.packet = packet; - - return cmd.u; -} - -static INLINE uint32_t cmdcpdelay(struct radeon_screen *rscrn, - unsigned short count) -{ - drm_r300_cmd_header_t cmd; - - cmd.u = 0; - - cmd.delay.cmd_type = R300_CMD_CP_DELAY; - cmd.delay.count = count; - - return cmd.u; -} - -static INLINE uint32_t cmdwait(struct radeon_screen *rscrn, - unsigned char flags) -{ - drm_r300_cmd_header_t cmd; - - cmd.u = 0; - cmd.wait.cmd_type = R300_CMD_WAIT; - cmd.wait.flags = flags; - - return cmd.u; -} - -static INLINE uint32_t cmdpacify(struct radeon_screen *rscrn) -{ - drm_r300_cmd_header_t cmd; - - cmd.u = 0; - cmd.header.cmd_type = R300_CMD_END3D; - - return cmd.u; -} - -/** - * Write the header of a packet3 to the command buffer. - * Outputs 2 dwords and expects (num_extra+1) additional dwords afterwards. - */ -#define OUT_BATCH_PACKET3(packet, num_extra) do {\ - if (!b_l_rmesa->radeonScreen->kernel_mm) { \ - OUT_BATCH(cmdpacket3(b_l_rmesa->radeonScreen,\ - R300_CMD_PACKET3_RAW)); \ - } else b_l_rmesa->cmdbuf.cs->section_cdw++;\ - OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ - } while(0) - -/** - * Must be sent to switch to 2d commands - */ -void static INLINE end_3d(radeonContextPtr radeon) -{ - BATCH_LOCALS(radeon); - - if (!radeon->radeonScreen->kernel_mm) { - BEGIN_BATCH_NO_AUTOSTATE(1); - OUT_BATCH(cmdpacify(radeon->radeonScreen)); - END_BATCH(); - } -} - -void static INLINE cp_delay(r600ContextPtr rmesa, unsigned short count) -{ - BATCH_LOCALS(&rmesa->radeon); - - if (!rmesa->radeon.radeonScreen->kernel_mm) { - BEGIN_BATCH_NO_AUTOSTATE(1); - OUT_BATCH(cmdcpdelay(rmesa->radeon.radeonScreen, count)); - END_BATCH(); - } -} - -void static INLINE cp_wait(radeonContextPtr radeon, unsigned char flags) -{ - BATCH_LOCALS(radeon); - uint32_t wait_until; - - if (!radeon->radeonScreen->kernel_mm) { - BEGIN_BATCH_NO_AUTOSTATE(1); - OUT_BATCH(cmdwait(radeon->radeonScreen, flags)); - END_BATCH(); - } else { - switch(flags) { - case R300_WAIT_2D: - wait_until = (1 << 14); - break; - case R300_WAIT_3D: - wait_until = (1 << 15); - break; - case R300_NEW_WAIT_2D_3D: - wait_until = (1 << 14) | (1 << 15); - break; - case R300_NEW_WAIT_2D_2D_CLEAN: - wait_until = (1 << 14) | (1 << 16) | (1 << 18); - break; - case R300_NEW_WAIT_3D_3D_CLEAN: - wait_until = (1 << 15) | (1 << 17) | (1 << 18); - break; - case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN: - wait_until = (1 << 14) | (1 << 16) | (1 << 18); - wait_until |= (1 << 15) | (1 << 17) | (1 << 18); - break; - default: - return; - } - BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); - OUT_BATCH(wait_until); - END_BATCH(); - } -} - -extern int r600EmitArrays(GLcontext * ctx); - -extern int r600PrimitiveType(r600ContextPtr rmesa, int prim); -extern int r600NumVerts(r600ContextPtr rmesa, int num_verts, int prim); - -extern void r600EmitCacheFlush(r600ContextPtr rmesa); - -extern GLuint r600VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr, - int *inputs, GLint * tab, GLuint nr); -extern GLuint r600VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr); -extern GLuint r600VAPInputCntl0(GLcontext * ctx, GLuint InputsRead); -extern GLuint r600VAPInputCntl1(GLcontext * ctx, GLuint InputsRead); -extern GLuint r600VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten); -extern GLuint r600VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten); +extern GLboolean r600EmitShader(GLcontext * ctx, + void ** shaderbo, + GLvoid * data, + int sizeinDWORD); + +extern GLboolean r600DeleteShader(GLcontext * ctx, + void * shaderbo); + +extern GLboolean r600EmitVec(GLcontext * ctx, + struct radeon_aos *aos, + GLvoid * data, + int size, + int stride, + int count); + +extern void r600ReleaseVec(GLcontext * ctx); + +extern void r600FreeDmaRegion(context_t *context, + void * shaderbo); #endif diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index d0371cdda0..e534bb11b2 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -29,15 +29,15 @@ #include "main/glheader.h" #include "r600_context.h" +#include "r600_cmdbuf.h" #include "r700_chip.h" #include "r700_state.h" #include "r700_tex.h" #include "r700_oglprog.h" +#include "r700_fragprog.h" +#include "r700_vertprog.h" #include "r700_ioctl.h" -/* to be enable -#include "r700_emit.h" -*/ extern const struct tnl_pipeline_stage *r700_pipeline[]; @@ -370,15 +370,235 @@ GLboolean r700InitChipObject(context_t *context) return GL_TRUE; } -GLboolean r700SendContextStates(context_t *context) +void r700SetupVTXConstans(GLcontext * ctx, + unsigned int nStreamID, + void * pAos, + unsigned int size, /* number of elements in vector */ + unsigned int stride, + unsigned int count) /* number of vectors in stream */ { -#if 0 //to be enable + context_t *context = R700_CONTEXT(ctx); + uint32_t *dest; + struct radeon_aos * paos = (struct radeon_aos *)pAos; + offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF}; + + BATCH_LOCALS(&context->radeon); + + unsigned int uSQ_VTX_CONSTANT_WORD0_0; + unsigned int uSQ_VTX_CONSTANT_WORD1_0; + unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0; + unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0; + unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0; + + uSQ_VTX_CONSTANT_WORD0_0 = paos->offset; + uSQ_VTX_CONSTANT_WORD1_0 = count * stride - 1; + + uSQ_VTX_CONSTANT_WORD2_0 |= 0 << BASE_ADDRESS_HI_shift /* TODO */ + |stride << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift + |GetSurfaceFormat(GL_FLOAT, size, NULL) << SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift /* TODO : trace back api for initial data type, not only GL_FLOAT */ + |SQ_NUM_FORMAT_SCALED << SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift + |SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit; + + uSQ_VTX_CONSTANT_WORD3_0 |= 1 << MEM_REQUEST_SIZE_shift; + + uSQ_VTX_CONSTANT_WORD6_0 |= SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift; + + BEGIN_BATCH_NO_AUTOSTATE(9); + + OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); + OUT_BATCH((nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE); + + R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD1_0, + paos->bo, + uSQ_VTX_CONSTANT_WORD1_0, + RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0); + OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0); + OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0); + + END_BATCH(); + COMMIT_BATCH(); + +} + +int r700SetupStreams(GLcontext * ctx) +{ + context_t *context = R700_CONTEXT(ctx); + + BATCH_LOCALS(&context->radeon); + + struct r700_vertex_program *vpc + = (struct r700_vertex_program *)ctx->VertexProgram._Current; + + TNLcontext *tnl = TNL_CONTEXT(ctx); + struct vertex_buffer *vb = &tnl->vb; + + unsigned int unBit; + unsigned int i; + + BEGIN_BATCH_NO_AUTOSTATE(6); + OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); + OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); + OUT_BATCH(0); + + OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); + OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX); + OUT_BATCH(0); + END_BATCH(); + COMMIT_BATCH(); + + //context->aos_count = 0; + for(i=0; imesa_program.Base.InputsRead & unBit) + { + (context->chipobj.EmitVec)(ctx, + &context->radeon.tcl.aos[i], + vb->AttribPtr[i]->data, + vb->AttribPtr[i]->size, + vb->AttribPtr[i]->stride, + vb->Count); + + /* currently aos are packed */ + r700SetupVTXConstans(ctx, + i, + (void*)(&context->radeon.tcl.aos[i]), + (unsigned int)vb->AttribPtr[i]->size, + (unsigned int)(vb->AttribPtr[i]->size * 4), + (unsigned int)vb->Count); + } + } + + return R600_FALLBACK_NONE; +} + +inline GLboolean setRelocReg(context_t *context, unsigned int reg, + void * pbo_vs, void * pbo_fs) +{ + BATCH_LOCALS(&context->radeon); + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + + struct radeon_bo * pbo; + uint32_t voffset; + offset_modifiers offset_mod; + + switch (reg + ASIC_CONTEXT_BASE_INDEX) + { + case mmCB_COLOR0_BASE: + case mmCB_COLOR1_BASE: + case mmCB_COLOR2_BASE: + case mmCB_COLOR3_BASE: + case mmCB_COLOR4_BASE: + case mmCB_COLOR5_BASE: + case mmCB_COLOR6_BASE: + case mmCB_COLOR7_BASE: + { + GLcontext *ctx = GL_CONTEXT(context); + struct radeon_renderbuffer *rrb; + + rrb = radeon_get_colorbuffer(&context->radeon); + if (!rrb || !rrb->bo) + { + fprintf(stderr, "no rrb\n"); + return GL_FALSE; + } + + offset_mod.shift = RIGHT_SHIFT; + offset_mod.shiftbits = 8; + offset_mod.mask = 0x00FFFFFF; + + R600_OUT_BATCH_RELOC(r700->CB_COLOR0_BASE.u32All, + rrb->bo, + r700->CB_COLOR0_BASE.u32All, + 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod); + return GL_TRUE; + } + break; + case mmDB_DEPTH_BASE: + { + GLcontext *ctx = GL_CONTEXT(context); + struct radeon_renderbuffer *rrb; + rrb = radeon_get_depthbuffer(&context->radeon); + + offset_mod.shift = RIGHT_SHIFT; + offset_mod.shiftbits = 8; + offset_mod.mask = 0x00FFFFFF; + + R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All, + rrb->bo, + r700->DB_DEPTH_BASE.u32All, + 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod); + + return GL_TRUE; + } + break; + case mmSQ_PGM_START_VS: + { + if(NULL != pbo_vs) + { + pbo = (struct radeon_bo *)pbo_vs; + } + else + { + pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); + } + + offset_mod.shift = RIGHT_SHIFT; + offset_mod.shiftbits = 8; + offset_mod.mask = 0x00FFFFFF; + + R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_VS.u32All, + pbo, + r700->SQ_PGM_START_VS.u32All, + RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + return GL_TRUE; + } + break; + case mmSQ_PGM_START_FS: + case mmSQ_PGM_START_ES: + case mmSQ_PGM_START_GS: + case mmSQ_PGM_START_PS: + { + if(NULL != pbo_fs) + { + pbo = (struct radeon_bo *)pbo_fs; + } + else + { + pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context)); + } + + offset_mod.shift = RIGHT_SHIFT; + offset_mod.shiftbits = 8; + offset_mod.mask = 0x00FFFFFF; + + voffset = 0; + R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_PS.u32All, + pbo, + r700->SQ_PGM_START_PS.u32All, + RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + return GL_TRUE; + } + break; + } + + return GL_FALSE; +} + +GLboolean r700SendContextStates(context_t *context, void * pbo_vs, void * pbo_fs) +{ + BATCH_LOCALS(&context->radeon); + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); ContextState * pState = r700->pStateList; ContextState * pInit; unsigned int toSend; - unsigned int ui; + unsigned int ui; while(NULL != pState) { @@ -401,17 +621,21 @@ GLboolean r700SendContextStates(context_t *context) pState = pState->pNext; - R700_CMDBUF_CHECK_SPACE(toSend + 2); - R700EP3(context, IT_SET_CONTEXT_REG, toSend); - R700E32(context, pInit->unOffset); - + BEGIN_BATCH_NO_AUTOSTATE(toSend + 2); + R600_OUT_BATCH_REGSEQ(((pInit->unOffset + ASIC_CONTEXT_BASE_INDEX)<<2), toSend); for(ui=0; uipuiValue)); + if( GL_FALSE == setRelocReg(context, (pInit->unOffset+ui), pbo_vs, pbo_fs) ) + { + /* for not reloc reg. */ + OUT_BATCH(*(pInit->puiValue)); + } pInit = pInit->pNext; }; + END_BATCH(); }; -#endif //to be enable + COMMIT_BATCH(); + return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h index f08190027c..30ca2cab84 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.h +++ b/src/mesa/drivers/dri/r600/r700_chip.h @@ -446,13 +446,22 @@ typedef struct _R700_CHIP_CONTEXT ContextState * pStateList; R700_TEXTURE_STATES texture_states; + + GLboolean bEnablePerspective; } R700_CHIP_CONTEXT; #define R700_CONTEXT_STATES(context) ((R700_CHIP_CONTEXT *)(context->chipobj.pvChipObj)) extern GLboolean r700InitChipObject(context_t *context); -extern GLboolean r700SendContextStates(context_t *context); +extern GLboolean r700SendContextStates(context_t *context, void * pbo_vs, void * pbo_fs); +extern int r700SetupStreams(GLcontext * ctx); +extern void r700SetupVTXConstans(GLcontext * ctx, + unsigned int nStreamID, + void * pAos, + unsigned int size, /* number of elements in vector */ + unsigned int stride, + unsigned int Count); /* number of vectors in stream */ #endif /* _R700_CHIP_H_ */ diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c index 5725360dac..743875dfe2 100644 --- a/src/mesa/drivers/dri/r600/r700_clear.c +++ b/src/mesa/drivers/dri/r600/r700_clear.c @@ -35,23 +35,12 @@ #include "r600_context.h" #include "r700_chip.h" -#if 0 /* to be enabled */ #include "r700_shaderinst.h" -#include "r700_emit.h" -#endif /* to be enabled */ +#include "r600_emit.h" extern void r700InitState (GLcontext * ctx); -#if 0 /* to be enabled */ -extern void r700SetupVTXConstans(GLcontext * ctx, - unsigned int nStreamID, - unsigned int aos_offset, - unsigned int size, /* number of elements in vector */ - unsigned int stride, - unsigned int count); -extern GLboolean r700SendContextStates(context_t *context); extern GLboolean r700SyncSurf(context_t *context); -#endif /* to be enabled */ static GLboolean r700ClearFast(context_t *context, GLbitfield mask) { @@ -63,17 +52,15 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) { GLcontext *ctx = GL_CONTEXT(context); -#if 0 /* to be enabled */ + BATCH_LOCALS(&context->radeon); + R700_CHIP_CONTEXT r700Saved; R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); - struct r600_dma_region aos_vs; - struct r600_dma_region aos_fs; - struct r600_dma_region aos_vb; - aos_vs.buf = NULL; - aos_fs.buf = NULL; - aos_vb.buf = NULL; - + void * pbo_vs; + void * pbo_fs; + struct radeon_aos aos_vb; + unsigned int ui; GLfloat fTemp; GLfloat fVb[] = { 1.0f, 1.0f, 1.0f, 1.0f, @@ -93,7 +80,7 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) 0x10000000, 0x340C90, 0x10000400, 0x20340C90, 0x10000800, 0x40340C90, 0x90000C00, 0x60200C90}; - if (context->screen->chip.type <= CHIP_TYPE_RV670) + if (context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV670) { uVs[9] = 0x541910; uVs[11] = 0x20541910; @@ -116,7 +103,7 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) r700InitState(ctx); - r700->CB_COLOR0_BASE.u32All = context->target.rt.gpu >> 8; + r700SetRenderTarget(context); /* Turn off perspective divid. */ SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit); @@ -152,15 +139,19 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) } /* Setup vb */ - R700_CMDBUF_CHECK_SPACE(6); - R700EP3 (context, IT_SET_CTL_CONST, 1); - R700E32 (context, mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); - R700E32 (context, 0); - R700EP3 (context, IT_SET_CTL_CONST, 1); - R700E32 (context, mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX); - R700E32 (context, 0); + BEGIN_BATCH_NO_AUTOSTATE(6); + OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); + OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); + OUT_BATCH(0); + + OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); + OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX); + OUT_BATCH(0); + END_BATCH(); + COMMIT_BATCH(); + (context->chipobj.EmitVec)(ctx, &aos_vb, (GLvoid *)fVb, 4, 16, 6); - r700SetupVTXConstans(ctx, VERT_ATTRIB_POS, (unsigned int)aos_vb.aos_offset, 4, 16, 6); + r700SetupVTXConstans(ctx, VERT_ATTRIB_POS, &aos_vb, 4, 16, 6); /* Setup shaders, copied from dump */ r700->SQ_PGM_RESOURCES_PS.u32All = 0; @@ -168,23 +159,26 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) SETbit(r700->SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); SETbit(r700->SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); /* vs */ - (context->chipobj.EmitShader)(ctx, &aos_vs, (GLvoid *)(&uVs[0]), 28); - r700->SQ_PGM_START_VS.u32All = (aos_vs.aos_offset >> 8) & 0x00FFFFFF; + (context->chipobj.EmitShader)(ctx, &pbo_vs, (GLvoid *)(&uVs[0]), 28); + r700->SQ_PGM_START_VS.u32All = 0; r700->SQ_PGM_RESOURCES_VS.u32All = 0x00800004; + /* vs const */ /* TODO : Set color here */ - R700_CMDBUF_CHECK_SPACE(4 + 2); - R700EP3 (context, IT_SET_ALU_CONST, 4); - R700E32 (context, SQ_ALU_CONSTANT_VS_OFFSET * 4); - R700E32 (context, *((unsigned int*)&(ctx->Color.ClearColor[0]))); - R700E32 (context, *((unsigned int*)&(ctx->Color.ClearColor[1]))); - R700E32 (context, *((unsigned int*)&(ctx->Color.ClearColor[2]))); - R700E32 (context, *((unsigned int*)&(ctx->Color.ClearColor[3]))); + BEGIN_BATCH_NO_AUTOSTATE(4 + 2); + OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, 4)); + OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4); + OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[0]))); + OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[1]))); + OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[2]))); + OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[3]))); + END_BATCH(); + COMMIT_BATCH(); r700->SPI_VS_OUT_CONFIG.u32All = 0x00000000; r700->SPI_PS_IN_CONTROL_0.u32All = 0x20000001; /* ps */ - (context->chipobj.EmitShader)(ctx, &aos_fs, (GLvoid *)(&uFs[0]), 12); - r700->SQ_PGM_START_PS.u32All = (aos_fs.aos_offset >> 8) & 0x00FFFFFF; + (context->chipobj.EmitShader)(ctx, &pbo_fs, (GLvoid *)(&uFs[0]), 12); + r700->SQ_PGM_START_PS.u32All = 0; r700->SQ_PGM_RESOURCES_PS.u32All = 0x00800002; r700->SQ_PGM_EXPORTS_PS.u32All = 0x00000002; r700->DB_SHADER_CONTROL.u32All = 0x00000200; @@ -192,12 +186,12 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) r700->CB_SHADER_CONTROL.u32All = 0x00000001; /* set a valid base address to make the command checker happy */ - r700->SQ_PGM_START_FS.u32All = (aos_fs.aos_offset >> 8) & 0x00FFFFFF; - r700->SQ_PGM_START_ES.u32All = (aos_fs.aos_offset >> 8) & 0x00FFFFFF; - r700->SQ_PGM_START_GS.u32All = (aos_fs.aos_offset >> 8) & 0x00FFFFFF; + r700->SQ_PGM_START_FS.u32All = 0; + r700->SQ_PGM_START_ES.u32All = 0; + r700->SQ_PGM_START_GS.u32All = 0; /* Now, send the states */ - r700SendContextStates(context); + r700SendContextStates(context, pbo_vs, pbo_fs); /* Draw */ GLuint numEntires, j; @@ -211,44 +205,47 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) + 3 /* VGT_PRIMITIVE_TYPE */ + numIndices + 3; /* DRAW_INDEX_IMMD */ - R700_CMDBUF_CHECK_SPACE(numEntires); + BEGIN_BATCH_NO_AUTOSTATE(numEntires); SETfield(VGT_INDEX_TYPE, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask); - R700EP3(context, IT_INDEX_TYPE, 0); - R700E32(context, VGT_INDEX_TYPE); + OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); + OUT_BATCH(VGT_INDEX_TYPE); VGT_NUM_INDICES = numIndices; SETfield(VGT_PRIMITIVE_TYPE, DI_PT_TRILIST, VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask); - R700EP3(context, IT_SET_CONFIG_REG, 1); - R700E32(context, mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); - R700E32(context, VGT_PRIMITIVE_TYPE); + + OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); + OUT_BATCH(VGT_PRIMITIVE_TYPE); SETfield(VGT_DRAW_INITIATOR, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask); SETfield(VGT_DRAW_INITIATOR, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask); - R700EP3(context, IT_DRAW_INDEX_IMMD, (numIndices + 1)); - R700E32(context, VGT_NUM_INDICES); - R700E32(context, VGT_DRAW_INITIATOR); + OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (numIndices + 1))); + OUT_BATCH(VGT_NUM_INDICES); + OUT_BATCH(VGT_DRAW_INITIATOR); for (j=0; jchipobj.FlushCmdBuffer)(context); /* TODO : keep these in context, don't load and release every time. */ - (context->chipobj.FreeDmaRegion)(context, &aos_vs); - (context->chipobj.FreeDmaRegion)(context, &aos_fs); - (context->chipobj.FreeDmaRegion)(context, &aos_vb); + (context->chipobj.DeleteShader)(context, &pbo_vs); + + (context->chipobj.DeleteShader)(context, &pbo_fs); + + (context->chipobj.FreeDmaRegion)(context, aos_vb.bo); /* Restore chip object. */ memcpy(r700, &r700Saved, sizeof(R700_CHIP_CONTEXT)); -#endif /* to be enabled */ - return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index 2b813828a5..d06af109e5 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -36,15 +36,11 @@ #include "shader/prog_statevars.h" #include "r600_context.h" +#include "r600_cmdbuf.h" #include "r700_chip.h" #include "r700_fragprog.h" -/* to be enabled */ -#if 0 -#include "r700_emit.h" -#endif - #include "r700_debug.h" //TODO : Validate FP input with VP output. @@ -250,9 +246,18 @@ GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp, return GL_TRUE; } +void * r700GetActiveFpShaderBo(GLcontext * ctx) +{ + struct r700_fragment_program *fp = (struct r700_fragment_program *) + (ctx->FragmentProgram._Current); + + return fp->shaderbo; +} + GLboolean r700SetupFragmentProgram(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); + BATCH_LOCALS(&context->radeon); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); @@ -271,14 +276,13 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) { Assemble( &(fp->r700Shader) ); } -/* to be enabled */ -#if 0 + /* Load fp to gpu */ (context->chipobj.EmitShader)(ctx, - &(fp->shadercode), + &(fp->shaderbo), (GLvoid *)(fp->r700Shader.pProgram), fp->r700Shader.uShaderBinaryDWORDSize); -#endif + fp->loaded = GL_TRUE; } @@ -288,10 +292,8 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) /* TODO : enable this after MemUse fixed *= (context->chipobj.MemUse)(context, fp->shadercode.buf->id); */ -/* to be enabled */ -#if 0 - r700->SQ_PGM_START_PS.u32All = (fp->shadercode.aos_offset >> 8) & 0x00FFFFFF; -#endif + + r700->SQ_PGM_START_PS.u32All = 0; /* set from buffer obj */ unNumOfReg = fp->r700Shader.nRegs + 1; @@ -337,25 +339,27 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) if(NULL != paramList) { _mesa_load_state_parameters(ctx, paramList); -/* to be enabled */ -#if 0 + unNumParamData = paramList->NumParameters * 4; - R700_CMDBUF_CHECK_SPACE(2 + unNumParamData); - R700EP3(context, IT_SET_ALU_CONST, unNumParamData); + BEGIN_BATCH_NO_AUTOSTATE(2 + unNumParamData); + + OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData)); + /* assembler map const from very beginning. */ - R700E32(context, SQ_ALU_CONSTANT_PS_OFFSET * 4); + OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4); unNumParamData = paramList->NumParameters; for(ui=0; uiParameterValues[ui][0]))); - R700E32(context, *((unsigned int*)&(paramList->ParameterValues[ui][1]))); - R700E32(context, *((unsigned int*)&(paramList->ParameterValues[ui][2]))); - R700E32(context, *((unsigned int*)&(paramList->ParameterValues[ui][3]))); + OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][0]))); + OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1]))); + OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2]))); + OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3]))); } -#endif + END_BATCH(); + COMMIT_BATCH(); } return GL_TRUE; diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.h b/src/mesa/drivers/dri/r600/r700_fragprog.h index 649ee4822d..9c7813e908 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.h +++ b/src/mesa/drivers/dri/r600/r700_fragprog.h @@ -40,10 +40,8 @@ struct r700_fragment_program GLboolean translated; GLboolean loaded; GLboolean error; -/* to be enabled */ -#if 0 - struct r600_dma_region shadercode; -#endif + + void * shaderbo; GLboolean WritesDepth; GLuint optimization; @@ -60,4 +58,6 @@ extern GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp, struct gl_fragment_program *mesa_vp); extern GLboolean r700SetupFragmentProgram(GLcontext * ctx); +extern void * r700GetActiveFpShaderBo(GLcontext * ctx); + #endif /*_R700_FRAGPROG_H_*/ diff --git a/src/mesa/drivers/dri/r600/r700_ioctl.c b/src/mesa/drivers/dri/r600/r700_ioctl.c index 0541dc76e4..7493efab0f 100644 --- a/src/mesa/drivers/dri/r600/r700_ioctl.c +++ b/src/mesa/drivers/dri/r600/r700_ioctl.c @@ -37,12 +37,38 @@ #include "radeon_lock.h" #include "r600_context.h" +#include "r700_chip.h" #include "r700_ioctl.h" #include "r700_clear.h" +static void r700Flush(GLcontext *ctx) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + context_t * context = R700_CONTEXT(ctx); + + if (RADEON_DEBUG & DEBUG_IOCTL) + fprintf(stderr, "%s %d\n", __FUNCTION__, radeon->cmdbuf.cs->cdw); + + /* okay if we have no cmds in the buffer && + we have no DMA flush && + we have no DMA buffer allocated. + then no point flushing anything at all. + */ + if (!radeon->dma.flush && !radeon->cmdbuf.cs->cdw && !radeon->dma.current) + return; + + if (radeon->dma.flush) + radeon->dma.flush( ctx ); + + r700SendContextStates(context, NULL, NULL); + + if (radeon->cmdbuf.cs->cdw) + rcommonFlushCmdBuf(radeon, __FUNCTION__); +} + void r700InitIoctlFuncs(struct dd_function_table *functions) { functions->Clear = r700Clear; functions->Finish = radeonFinish; - functions->Flush = radeonFlush; + functions->Flush = r700Flush; } diff --git a/src/mesa/drivers/dri/r600/r700_oglprog.c b/src/mesa/drivers/dri/r600/r700_oglprog.c index ee6377632b..dc8c936165 100644 --- a/src/mesa/drivers/dri/r600/r700_oglprog.c +++ b/src/mesa/drivers/dri/r600/r700_oglprog.c @@ -36,18 +36,16 @@ #include "r700_chip.h" #include "r700_oglprog.h" - -#if 0 /* to be enabled */ #include "r700_fragprog.h" #include "r700_vertprog.h" -#endif /* to be enabled */ + static struct gl_program *r700NewProgram(GLcontext * ctx, GLenum target, GLuint id) { struct gl_program *pProgram = NULL; -#if 0 /* to be enabled */ + struct r700_vertex_program *vp; struct r700_fragment_program *fp; @@ -62,7 +60,9 @@ static struct gl_program *r700NewProgram(GLcontext * ctx, id); vp->translated = GL_FALSE; vp->loaded = GL_FALSE; - vp->shadercode.buf = NULL; + + vp->shaderbo = NULL; + break; case GL_FRAGMENT_PROGRAM_NV: case GL_FRAGMENT_PROGRAM_ARB: @@ -73,18 +73,19 @@ static struct gl_program *r700NewProgram(GLcontext * ctx, id); fp->translated = GL_FALSE; fp->loaded = GL_FALSE; - fp->shadercode.buf = NULL; + + fp->shaderbo = NULL; + break; default: _mesa_problem(ctx, "Bad target in r700NewProgram"); } -#endif /* to be enabled */ + return pProgram; } static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) { -#if 0 /* to be enabled */ struct r700_vertex_program * vp; struct r700_fragment_program * fp; context_t *context = R700_CONTEXT(ctx); @@ -95,7 +96,9 @@ static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) case GL_VERTEX_PROGRAM_ARB: vp = (struct r700_vertex_program*)prog; /* Release DMA region */ - (context->chipobj.FreeDmaRegion)(context, &(vp->shadercode)); + + (context->chipobj.DeleteShader)(ctx, vp->shaderbo); + /* Clean up */ Clean_Up_Assembler(&(vp->r700AsmCode)); Clean_Up_Shader(&(vp->r700Shader)); @@ -104,7 +107,9 @@ static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) case GL_FRAGMENT_PROGRAM_ARB: fp = (struct r700_fragment_program*)prog; /* Release DMA region */ - (context->chipobj.FreeDmaRegion)(context, &(fp->shadercode)); + + (context->chipobj.DeleteShader)(ctx, fp->shaderbo); + /* Clean up */ Clean_Up_Assembler(&(fp->r700AsmCode)); Clean_Up_Shader(&(fp->r700Shader)); @@ -114,7 +119,6 @@ static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) } _mesa_delete_program(ctx, prog); -#endif /* to be enabled */ } static void diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index fce99ada54..f338cf823c 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -45,107 +45,64 @@ #include "tnl/t_pipeline.h" #include "r600_context.h" +#include "r600_cmdbuf.h" #include "r700_chip.h" +#include "r700_tex.h" -/* to be enable #include "r700_vertprog.h" #include "r700_fragprog.h" #include "r700_state.h" -#include "r700_tex.h" -#include "r700_emit.h" -*/ -#if 0 // to be enable void r700WaitForIdle(context_t *context) { - R700EP3 (context, IT_SET_CONFIG_REG, 1); - R700E32 (context, mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); - R700E32 (context, 1 << 15); + BATCH_LOCALS(&context->radeon); + BEGIN_BATCH_NO_AUTOSTATE(3); + + OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); + OUT_BATCH(1 << 15); + + END_BATCH(); + COMMIT_BATCH(); } void r700WaitForIdleClean(context_t *context) { - R700EP3 (context, IT_EVENT_WRITE, 0); - R700E32 (context, 0x16); + BATCH_LOCALS(&context->radeon); + BEGIN_BATCH_NO_AUTOSTATE(5); + + OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); + OUT_BATCH(0x16); - R700EP3 (context, IT_SET_CONFIG_REG, 1); - R700E32 (context, mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); - R700E32 (context, 1 << 17); + OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); + OUT_BATCH(1 << 17); + + END_BATCH(); + COMMIT_BATCH(); } static void r700Start3D(context_t *context) { - if (context->screen->chip.type <= CHIP_TYPE_RV670) + BATCH_LOCALS(&context->radeon); + if (context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV670) { - R700EP3 (context, IT_START_3D_CMDBUF, 1); - R700E32 (context, 0); + BEGIN_BATCH_NO_AUTOSTATE(2); + OUT_BATCH(CP_PACKET3(R600_IT_START_3D_CMDBUF, 1)); + OUT_BATCH(0); + END_BATCH(); } - R700EP3 (context, IT_CONTEXT_CONTROL, 1); - R700E32 (context, 0x80000000); - R700E32 (context, 0x80000000); - r700WaitForIdleClean(context); -} + BEGIN_BATCH_NO_AUTOSTATE(3); + OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1)); + OUT_BATCH(0x80000000); + OUT_BATCH(0x80000000); + END_BATCH(); + COMMIT_BATCH(); -static int r700SetupStreams(GLcontext * ctx) -{ - context_t *context = R700_CONTEXT(ctx); - - struct r700_vertex_program *vpc - = (struct r700_vertex_program *)ctx->VertexProgram._Current; - - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *vb = &tnl->vb; - - unsigned int unBit; - unsigned int i; - - R700_CMDBUF_CHECK_SPACE(6); - R700EP3 (context, IT_SET_CTL_CONST, 1); - R700E32 (context, mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); - R700E32 (context, 0); - - R700EP3 (context, IT_SET_CTL_CONST, 1); - R700E32 (context, mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX); - R700E32 (context, 0); - - context->aos_count = 0; - for(i=0; imesa_program.Base.InputsRead & unBit) - { - (context->chipobj.EmitVec)(ctx, - &(context->aos[context->aos_count]), - vb->AttribPtr[i]->data, - vb->AttribPtr[i]->size, - vb->AttribPtr[i]->stride, - vb->Count); - - context->aos[context->aos_count].aos_size = vb->AttribPtr[i]->size; - - /* currently aos are packed */ - r700SetupVTXConstans(ctx, - i, - (unsigned int)context->aos[context->aos_count].aos_offset, - (unsigned int)vb->AttribPtr[i]->size, - (unsigned int)(vb->AttribPtr[i]->size * 4), - (unsigned int)vb->Count); - /* TODO : enable this after MemUse fixed *= - (context->chipobj.MemUse)(context, context->aos[context->aos_count].buf->id); - */ - - context->aos_count++; - } - } - for(i=context->aos_count; iaos[i].buf = NULL; - } - - return R600_FALLBACK_NONE; + r700WaitForIdleClean(context); } static GLboolean r700SetupShaders(GLcontext * ctx) @@ -177,7 +134,7 @@ GLboolean r700SendTextureState(context_t *context) unsigned int i; R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); - +#if 0 /* to be enabled */ for(i=0; itexture_states.textures[i] != 0) @@ -204,12 +161,15 @@ GLboolean r700SendTextureState(context_t *context) R700E32 (context, r700->texture_states.samplers[i]->SQ_TEX_SAMPLER2.u32All); } } - +#endif return GL_TRUE; } GLboolean r700SyncSurf(context_t *context) { +#if 0 //to be enabled + BATCH_LOCALS(&context->radeon); + /* TODO : too heavy? */ unsigned int CP_COHER_CNTL = 0; @@ -221,23 +181,20 @@ GLboolean r700SyncSurf(context_t *context) |SMX_ACTION_ENA_bit; - R700_CMDBUF_CHECK_SPACE(5); - R700EP3(context, IT_SURFACE_SYNC, 3); - R700E32(context, CP_COHER_CNTL); - R700E32(context, 0xFFFFFFFF); - R700E32(context, 0x00000000); - R700E32(context, 10); + BEGIN_BATCH_NO_AUTOSTATE(5); + + OUT_BATCH(CP_PACKET3((IT_SURFACE_SYNC << 8), 3))); + OUT_BATCH(CP_COHER_CNTL); + OUT_BATCH(0xFFFFFFFF); + OUT_BATCH(0x00000000); + OUT_BATCH(10); + END_BATCH(); + COMMIT_BATCH(); +#endif return GL_TRUE; } -static void r700SetRenderTarget(context_t *context) -{ - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); - - r700->CB_COLOR0_BASE.u32All = context->target.rt.gpu >> 8; -} - unsigned int r700PrimitiveType(int prim) { switch (prim & PRIM_MODE_MASK) @@ -279,21 +236,21 @@ unsigned int r700PrimitiveType(int prim) } } -#endif // to be enable - static GLboolean r700RunRender(GLcontext * ctx, struct tnl_pipeline_stage *stage) { -#if 0 // to be enable context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + + BATCH_LOCALS(&context->radeon); + unsigned int i, j; TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; struct r700_fragment_program *fp = (struct r700_fragment_program *) (ctx->FragmentProgram._Current); - if (context->screen->chip.type <= CHIP_TYPE_RV670) + if (context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV670) { fp->r700AsmCode.bR6xx = 1; } @@ -329,7 +286,7 @@ static GLboolean r700RunRender(GLcontext * ctx, r700->SQ_PGM_START_ES.u32All = r700->SQ_PGM_START_PS.u32All; r700->SQ_PGM_START_GS.u32All = r700->SQ_PGM_START_PS.u32All; - r700SendContextStates(context); + r700SendContextStates(context, NULL, NULL); /* richard test code */ for (i = 0; i < vb->PrimitiveCount; i++) @@ -351,51 +308,55 @@ static GLboolean r700RunRender(GLcontext * ctx, + numIndices + 3 /* DRAW_INDEX_IMMD */ + 2; /* test stamp */ - R700_CMDBUF_CHECK_SPACE(numEntires); + BEGIN_BATCH_NO_AUTOSTATE(numEntires); VGT_INDEX_TYPE |= DI_INDEX_SIZE_32_BIT << INDEX_TYPE_shift; - R700EP3(context, IT_INDEX_TYPE, 0); - R700E32(context, VGT_INDEX_TYPE); + OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); + OUT_BATCH(VGT_INDEX_TYPE); VGT_NUM_INDICES = numIndices; VGT_PRIMITIVE_TYPE |= r700PrimitiveType(prim) << VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift; - R700EP3(context, IT_SET_CONFIG_REG, 1); - R700E32(context, mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); - R700E32(context, VGT_PRIMITIVE_TYPE); + OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); + OUT_BATCH(VGT_PRIMITIVE_TYPE); VGT_DRAW_INITIATOR |= DI_SRC_SEL_IMMEDIATE << SOURCE_SELECT_shift; VGT_DRAW_INITIATOR |= DI_MAJOR_MODE_0 << MAJOR_MODE_shift; - R700EP3(context, IT_DRAW_INDEX_IMMD, (numIndices + 1)); - R700E32(context, VGT_NUM_INDICES); - R700E32(context, VGT_DRAW_INITIATOR); + OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (numIndices + 1))); + OUT_BATCH(VGT_NUM_INDICES); + OUT_BATCH(VGT_DRAW_INITIATOR); for (j=0; jchipobj.FlushCmdBuffer)(context); - /* free aos => TODO : cache mgr */ - for (i = 0; i < context->aos_count; i++) - { - (context->chipobj.FreeDmaRegion)(context, &(context->aos[i])); - } -#endif // to be enable + (context->chipobj.ReleaseArrays)(ctx); + + //richard test + /* test stamp, write a number to mmSCRATCH4 */ + BEGIN_BATCH_NO_AUTOSTATE(3); + R600_OUT_BATCH_REGVAL((0x2144 << 2), 0x56785678); + END_BATCH(); + COMMIT_BATCH(); + + rcommonFlushCmdBuf( &context->radeon, __FUNCTION__ ); + return GL_FALSE; } @@ -412,11 +373,19 @@ static GLboolean r700RunTCLRender(GLcontext * ctx, /*----------------------*/ { GLboolean bRet = GL_FALSE; -#if 0 // to be enable + /* TODO : sw fallback */ + + /** + * Ensure all enabled and complete textures are uploaded along with any buffers being used. + */ + if(!r700ValidateBuffers(ctx)) + { + return GL_TRUE; + } + context_t *context = R700_CONTEXT(ctx); r700UpdateShaders(ctx); -#endif // to be enable bRet = r700RunRender(ctx, stage); diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 4341f33665..a31a89627c 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -52,10 +52,9 @@ #include "r700_chip.h" #include "r700_state.h" -#if 0 /* to be enabled */ #include "r700_fragprog.h" #include "r700_vertprog.h" -#endif /* to be enabled */ + void r700SetDefaultStates(context_t *context) //-------------------- { @@ -68,13 +67,13 @@ void r700UpdateShaders (GLcontext * ctx) //---------------------------------- GLvector4f dummy_attrib[_TNL_ATTRIB_MAX]; GLvector4f *temp_attrib[_TNL_ATTRIB_MAX]; -#if 0 /* to be enabled */ + struct r700_vertex_program *vp; int i; - if (context->NewGLState) + if (context->radeon.NewGLState) { - context->NewGLState = 0; + context->radeon.NewGLState = 0; for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) { @@ -108,7 +107,6 @@ void r700UpdateShaders (GLcontext * ctx) //---------------------------------- } r700UpdateStateParameters(ctx, _NEW_PROGRAM); -#endif /* to be enabled */ } /* @@ -116,6 +114,7 @@ void r700UpdateShaders (GLcontext * ctx) //---------------------------------- */ void r700UpdateViewportOffset(GLcontext * ctx) //------------------ { + return; } /** @@ -152,7 +151,6 @@ static void r700FetchStateParameter(GLcontext * ctx, void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //-------------------- { -#if 0 /* to be enabled */ struct r700_fragment_program *fp; struct gl_program_parameter_list *paramList; GLuint i; @@ -183,7 +181,6 @@ void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //------------ paramList->ParameterValues[i]); } } -#endif /* to be enabled */ } /** @@ -191,7 +188,6 @@ void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //------------ */ static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //------------------- { -#if 0 /* to be enabled */ context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); @@ -204,12 +200,16 @@ static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //----------- if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) { + _mesa_update_framebuffer(ctx); + /* this updates the DrawBuffer's Width/Height if it's a FBO */ + _mesa_update_draw_buffer_bounds(ctx); + r700UpdateDrawBuffer(ctx); } r700UpdateStateParameters(ctx, new_state); - if(GL_TRUE == context->bEnablePerspective) + if(GL_TRUE == r700->bEnablePerspective) { /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */ CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit); @@ -232,8 +232,7 @@ static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //----------- CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit); } - context->NewGLState |= new_state; -#endif /* to be enabled */ + context->radeon.NewGLState |= new_state; } static void r700SetDepthState(GLcontext * ctx) @@ -492,17 +491,11 @@ static void r700Viewport(GLcontext * ctx, GLsizei width, GLsizei height) //-------------------- { -#if 0 /* to be enabled */ context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); - context->vport_x = x; - context->vport_y = y; - context->vport_width = width; - context->vport_height= height; - - __DRIdrawablePrivate *dPriv = context->currentDraw; + __DRIdrawablePrivate *dPriv = context->radeon.dri.drawable; GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; @@ -534,12 +527,12 @@ static void r700Viewport(GLcontext * ctx, tz = v[MAT_TZ] * scale; /* TODO : Need DMA flush as well. */ - +#if 0 /* to be enabled */ if(context->cmdbuf.count_used > 0) { (context->chipobj.FlushCmdBuffer)(context); } - +#endif /* to be enabled */ r700->PA_CL_VPORT_XSCALE.u32All = *((unsigned int*)(&sx)); r700->PA_CL_VPORT_XOFFSET.u32All = *((unsigned int*)(&tx)); @@ -548,7 +541,6 @@ static void r700Viewport(GLcontext * ctx, r700->PA_CL_VPORT_ZSCALE.u32All = *((unsigned int*)(&sz)); r700->PA_CL_VPORT_ZOFFSET.u32All = *((unsigned int*)(&tz)); -#endif /* to be enabled */ } @@ -600,60 +592,47 @@ static void r700Scissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h) } } - -/** - * Calculate initial hardware state and register state functions. - * Assumes that the command buffer and state atoms have been - * initialized already. - */ -void r700InitState(GLcontext * ctx) //------------------- +void r700SetRenderTarget(context_t *context) { -#if 0 /* to be enabled */ - context_t *context = R700_CONTEXT(ctx); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); - - if(context->ctx->Visual.doubleBufferMode && context->sarea->pfCurrentPage == 0) - { - context->target.rt = context->screen->backBuffer; - } - else - { - context->target.rt = context->screen->frontBuffer; - } + struct radeon_renderbuffer *rrb; + unsigned int nPitchInPixel; + + /* screen/window/view */ SETfield(r700->CB_TARGET_MASK.u32All, 0xF, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask); SETfield(r700->CB_SHADER_MASK.u32All, 0xF, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask); /* screen */ r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0; - SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, context->screen->width, + + SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->width, PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask); - SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, context->screen->height, + SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->height, PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask); /* window */ SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit); - SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, context->currentDraw->x, + SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, context->radeon.dri.drawable->x, PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask); - SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, context->currentDraw->y, + SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, context->radeon.dri.drawable->y, PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask); - SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, context->currentDraw->x + context->currentDraw->w, + SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w, PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask); - SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, context->currentDraw->y + context->currentDraw->h, + SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h, PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask); /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */ r700->PA_SC_CLIPRECT_RULE.u32All = 0x0000FFFF; - SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, context->currentDraw->x, + SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, context->radeon.dri.drawable->x, PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask); - SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, context->currentDraw->y, + SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, context->radeon.dri.drawable->y, PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask); - SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, context->currentDraw->x + context->currentDraw->w, + SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w, PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask); - SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, context->currentDraw->y + context->currentDraw->h, + SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h, PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask); r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All; @@ -665,42 +644,138 @@ void r700InitState(GLcontext * ctx) //------------------- /* more....2d clip */ SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit); - SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, context->currentDraw->x, + SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, context->radeon.dri.drawable->x, PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask); - SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, context->currentDraw->y, + SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, context->radeon.dri.drawable->y, PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask); - SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, context->currentDraw->x + context->currentDraw->w, + SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w, PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask); - SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, context->currentDraw->y + context->currentDraw->h, + SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h, PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask); SETbit(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit); - SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, context->currentDraw->x, + SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, context->radeon.dri.drawable->x, PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, context->currentDraw->y, + SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, context->radeon.dri.drawable->y, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, context->currentDraw->x + context->currentDraw->w, + SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w, PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, context->currentDraw->y + context->currentDraw->h, + SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask); SETbit(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, WINDOW_OFFSET_DISABLE_bit); - SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, context->currentDraw->x, + SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, context->radeon.dri.drawable->x, PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, context->currentDraw->y, + SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, context->radeon.dri.drawable->y, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, context->currentDraw->x + context->currentDraw->w, + SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w, PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, context->currentDraw->y + context->currentDraw->h, + SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask); /* setup viewport */ - r700Viewport(ctx, + r700Viewport(GL_CONTEXT(context), 0, 0, - context->currentDraw->w, - context->currentDraw->h); + context->radeon.dri.drawable->w, + context->radeon.dri.drawable->h); + + rrb = radeon_get_colorbuffer(&context->radeon); + if (!rrb || !rrb->bo) { + fprintf(stderr, "no rrb\n"); + return; + } + + /* color buffer */ + r700->CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset; + nPitchInPixel = rrb->pitch/rrb->cpp; + SETfield(r700->CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1, + PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); + SETfield(r700->CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * rrb->base.Height)/64 )-1, + SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); + r700->CB_COLOR0_BASE.u32All = 0; + SETfield(r700->CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask); + SETfield(r700->CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL, + CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask); + if(4 == rrb->cpp) + { + SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_8_8_8_8, + CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask); + SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask); + } + else + { + SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_5_6_5, + CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask); + SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT_REV, + COMP_SWAP_shift, COMP_SWAP_mask); + } + SETbit(r700->CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit); + SETbit(r700->CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit); + SETfield(r700->CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask); + + /* depth buf */ + r700->DB_DEPTH_SIZE.u32All = 0; + r700->DB_DEPTH_BASE.u32All = 0; + r700->DB_DEPTH_INFO.u32All = 0; + + r700->DB_DEPTH_CONTROL.u32All = 0; + r700->DB_DEPTH_CLEAR.u32All = 0x3F800000; + r700->DB_DEPTH_VIEW.u32All = 0; + r700->DB_RENDER_CONTROL.u32All = 0; + r700->DB_RENDER_OVERRIDE.u32All = 0; + SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask); + SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask); + SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask); + + rrb = radeon_get_depthbuffer(&context->radeon); + if (!rrb) + return; + + nPitchInPixel = rrb->pitch/rrb->cpp; + + SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1, + PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); + SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * rrb->base.Height)/64 )-1, + SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */ + + if(4 == rrb->cpp) + { + switch (GL_CONTEXT(context)->Visual.depthBits) + { + case 16: + case 24: + SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24, + DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask); + break; + default: + fprintf(stderr, "Error: Unsupported depth %d... exiting\n", + GL_CONTEXT(context)->Visual.depthBits); + _mesa_exit(-1); + } + } + else + { + SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16, + DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask); + } + SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1, + DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask); + /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */ +} + +/** + * Calculate initial hardware state and register state functions. + * Assumes that the command buffer and state atoms have been + * initialized already. + */ +void r700InitState(GLcontext * ctx) //------------------- +{ + context_t *context = R700_CONTEXT(ctx); + + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + /* Turn off vgt reuse */ r700->VGT_REUSE_OFF.u32All = 0; SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit); @@ -740,7 +815,7 @@ void r700InitState(GLcontext * ctx) //------------------- POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask); /* Do scale XY and Z by 1/W0. */ - context->bEnablePerspective = GL_TRUE; + r700->bEnablePerspective = GL_TRUE; CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit); CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit); SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit); @@ -811,35 +886,8 @@ void r700InitState(GLcontext * ctx) //------------------- /* depth buf */ r700->DB_DEPTH_SIZE.u32All = 0; - SETfield(r700->DB_DEPTH_SIZE.u32All, (context->screen->depthBuffer.pitch/8)-1, - PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); - SETfield(r700->DB_DEPTH_SIZE.u32All, ( (context->screen->depthBuffer.size / context->screen->cpp)/64 )-1, - SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */ - r700->DB_DEPTH_BASE.u32All = context->screen->depthBuffer.gpu >> 8; + r700->DB_DEPTH_BASE.u32All = 0; r700->DB_DEPTH_INFO.u32All = 0; - if(4 == context->screen->cpp) /* TODO : in scrren create, gives z its own format alloc. */ - { - switch (ctx->Visual.depthBits) - { - case 16: - case 24: - SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24, - DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask); - break; - default: - fprintf(stderr, "Error: Unsupported depth %d... exiting\n", - ctx->Visual.depthBits); - _mesa_exit(-1); - } - } - else - { - SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16, - DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask); - } - SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1, - DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask); - /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */ r700->DB_DEPTH_CONTROL.u32All = 0; r700->DB_DEPTH_CLEAR.u32All = 0x3F800000; r700->DB_DEPTH_VIEW.u32All = 0; @@ -850,27 +898,9 @@ void r700InitState(GLcontext * ctx) //------------------- SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask); /* color buffer */ - SETfield(r700->CB_COLOR0_SIZE.u32All, (context->screen->frontBuffer.pitch/8)-1, - PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); - SETfield(r700->CB_COLOR0_SIZE.u32All, ( (context->screen->frontBuffer.size / context->screen->cpp)/64 )-1, - SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); - r700->CB_COLOR0_BASE.u32All = context->screen->frontBuffer.gpu >> 8; - SETfield(r700->CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask); - SETfield(r700->CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL, - CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask); - if(4 == context->screen->cpp) - { - SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_8_8_8_8, - CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask); - SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask); - } - else - { - SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_5_6_5, - CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask); - SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT_REV, - COMP_SWAP_shift, COMP_SWAP_mask); - } + r700->CB_COLOR0_SIZE.u32All = 0; + r700->CB_COLOR0_BASE.u32All = 0; + r700->CB_COLOR0_INFO.u32All = 0; SETbit(r700->CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit); SETbit(r700->CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit); SETfield(r700->CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask); @@ -879,8 +909,7 @@ void r700InitState(GLcontext * ctx) //------------------- r700->CB_COLOR0_FRAG.u32All = 0; r700->CB_COLOR0_MASK.u32All = 0; - r700->PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000; -#endif /* to be enabled */ + r700->PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000; } void r700InitStateFuncs(struct dd_function_table *functions) //----------------- diff --git a/src/mesa/drivers/dri/r600/r700_state.h b/src/mesa/drivers/dri/r600/r700_state.h index b9542f4dd2..a75c7f0188 100644 --- a/src/mesa/drivers/dri/r600/r700_state.h +++ b/src/mesa/drivers/dri/r600/r700_state.h @@ -42,6 +42,7 @@ extern void r700UpdateDrawBuffer (GLcontext * ctx); extern void r700InitState (GLcontext * ctx); extern void r700InitStateFuncs (struct dd_function_table *functions); +extern void r700SetRenderTarget(context_t *context); extern void r700SetDefaultStates(context_t * context); #endif /* _R600_SCREEN_H */ diff --git a/src/mesa/drivers/dri/r600/r700_tex.c b/src/mesa/drivers/dri/r600/r700_tex.c index 75300d2c5f..85352022bc 100644 --- a/src/mesa/drivers/dri/r600/r700_tex.c +++ b/src/mesa/drivers/dri/r600/r700_tex.c @@ -42,9 +42,7 @@ #include "r600_context.h" #include "r700_chip.h" -#if 0 /* to be enabled */ #include "r700_state.h" -#endif /* to be enabled */ #include "r700_tex.h" @@ -72,7 +70,6 @@ void r700SetTexOffset(__DRIcontext *pDRICtx, GLint texname, { } -#if 0 /* to be enabled */ static GLboolean r700GetTexFormat(struct gl_texture_object *tObj, GLuint mesa_format) { r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; @@ -548,7 +545,6 @@ static void compute_tex_image_offset( *curOffset += size; } -#endif /* to be enabled */ void r700DestroyTexObj(context_t context, r700TexObjPtr t) { @@ -563,9 +559,9 @@ void r700DestroyTexObj(context_t context, r700TexObjPtr t) //} } -#if 0 /* to be enabled */ static void r700SetTexImages(context_t *context, struct gl_texture_object *tObj) { +#if 0 /* to be enabled */ r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; const struct gl_texture_image *baseImage = tObj->Image[0][tObj->BaseLevel]; GLint curOffset; @@ -668,6 +664,7 @@ static void r700SetTexImages(context_t *context, struct gl_texture_object *tObj) TEX_WIDTH_shift, TEX_WIDTH_mask); SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, tObj->Image[0][t->base.firstLevel]->Height - 1, TEX_HEIGHT_shift, TEX_HEIGHT_mask); +#endif /* to be enabled */ } static void r700UploadSubImage(context_t *context, @@ -677,6 +674,7 @@ static void r700UploadSubImage(context_t *context, GLint y, GLuint face) { +#if 0 /* to be enabled */ struct gl_texture_image *texImage = NULL; GLuint offset; GLint imageWidth, imageHeight; @@ -739,10 +737,12 @@ static void r700UploadSubImage(context_t *context, t->src_hight_in_pexel[face][hwlevel], /* height */ t->byte_per_texel, /* byte_per_pixel */ pSrc); /* source data */ +#endif /* to be enabled */ } int r700UploadTexImages(GLcontext * ctx, struct gl_texture_object *tObj, GLuint face) { +#if 0 /* to be enabled */ context_t *context = R700_CONTEXT(ctx); r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; @@ -823,7 +823,7 @@ int r700UploadTexImages(GLcontext * ctx, struct gl_texture_object *tObj, GLuint SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, t->base.firstLevel, BASE_LEVEL_shift, BASE_LEVEL_mask); SETfield(t->texture_state.SQ_TEX_RESOURCE5.u32All, t->base.lastLevel, LAST_LEVEL_shift, LAST_LEVEL_mask); } - +#endif /* to be enabled */ return 0; } @@ -889,8 +889,6 @@ static const struct gl_texture_format *r700Choose8888TexFormat(GLenum srcFormat, return gtfRet; } -#endif /* to be enabled */ - static r700TexObjPtr r700AllocTexObj(struct gl_texture_object *texObj) { r700TexObjPtr t; @@ -1527,6 +1525,16 @@ void r700UpdateTextureState(context_t * context) #endif /* to be enabled */ } +/** + * Ensure all enabled and complete textures are uploaded along with any buffers being used. + */ +GLboolean r700ValidateBuffers(GLcontext * ctx) +{ + /* TODO */ + + return radeon_revalidate_bos(ctx); +} + void r700InitTextureFuncs(struct dd_function_table *functions) { /* Note: we only plug in the functions we implement in the driver diff --git a/src/mesa/drivers/dri/r600/r700_tex.h b/src/mesa/drivers/dri/r600/r700_tex.h index 13290578a1..e322bbc47d 100644 --- a/src/mesa/drivers/dri/r600/r700_tex.h +++ b/src/mesa/drivers/dri/r600/r700_tex.h @@ -97,6 +97,8 @@ extern void r700SetTexOffset(__DRIcontext *pDRICtx, extern void r700DestroyTexObj(context_t rmesa, r700TexObjPtr t); +extern GLboolean r700ValidateBuffers(GLcontext * ctx); + extern void r700InitTextureFuncs(struct dd_function_table *functions); #endif /* __r700_TEX_H__ */ diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index 22a12a00d1..f0dfbe20f0 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -39,15 +39,12 @@ #include "shader/prog_statevars.h" #include "r600_context.h" +#include "r600_cmdbuf.h" #include "r700_chip.h" #include "r700_debug.h" #include "r700_vertprog.h" -#if 0 /* to be enabled */ -#include "r700_emit.h" -#endif - unsigned int Map_Vertex_Output(r700_AssemblerBase *pAsm, struct gl_vertex_program *mesa_vp, unsigned int unStart) @@ -297,11 +294,10 @@ GLboolean r700TranslateVertexShader(struct r700_vertex_program *vp, void r700SelectVertexShader(GLcontext *ctx) { -#if 0 /* to be enabled */ context_t *context = R700_CONTEXT(ctx); struct r700_vertex_program *vpc = (struct r700_vertex_program *)ctx->VertexProgram._Current; - if (context->screen->chip.type <= CHIP_TYPE_RV670) + if (context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV670) { vpc->r700AsmCode.bR6xx = 1; } @@ -327,56 +323,22 @@ void r700SelectVertexShader(GLcontext *ctx) r700TranslateVertexShader(vpc, &(vpc->mesa_program) ); } -#endif /* to be enabled */ } -void r700SetupVTXConstans(GLcontext * ctx, - unsigned int nStreamID, - unsigned int aos_offset, - unsigned int size, /* number of elements in vector */ - unsigned int stride, - unsigned int count) /* number of vectors in stream */ +void * r700GetActiveVpShaderBo(GLcontext * ctx) { - context_t *context = R700_CONTEXT(ctx); - uint32_t *dest; - - unsigned int uSQ_VTX_CONSTANT_WORD0_0; - unsigned int uSQ_VTX_CONSTANT_WORD1_0; - unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0; - unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0; - unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0; - - uSQ_VTX_CONSTANT_WORD0_0 = aos_offset; - uSQ_VTX_CONSTANT_WORD1_0 = count * stride - 1; - - uSQ_VTX_CONSTANT_WORD2_0 |= 0 << BASE_ADDRESS_HI_shift /* TODO */ - |stride << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift - |GetSurfaceFormat(GL_FLOAT, size, NULL) << SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift /* TODO : trace back api for initial data type, not only GL_FLOAT */ - |SQ_NUM_FORMAT_SCALED << SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift - |SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit; - - uSQ_VTX_CONSTANT_WORD3_0 |= 1 << MEM_REQUEST_SIZE_shift; - - uSQ_VTX_CONSTANT_WORD6_0 |= SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift; -#if 0 /* to be enabled */ - R700_CMDBUF_CHECK_SPACE(9); - R700EP3 (context, IT_SET_RESOURCE, 7); - R700E32 (context, (nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE); - - R700E32 (context, uSQ_VTX_CONSTANT_WORD0_0); - R700E32 (context, uSQ_VTX_CONSTANT_WORD1_0); - R700E32 (context, uSQ_VTX_CONSTANT_WORD2_0); - R700E32 (context, uSQ_VTX_CONSTANT_WORD3_0); - R700E32 (context, 0); - R700E32 (context, 0); - R700E32 (context, uSQ_VTX_CONSTANT_WORD6_0); -#endif /* to be enabled */ + struct r700_vertex_program *vp + = (struct r700_vertex_program *)ctx->VertexProgram._Current; + + return vp->shaderbo; } GLboolean r700SetupVertexProgram(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); + BATCH_LOCALS(&context->radeon); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); struct r700_vertex_program *vp @@ -396,7 +358,7 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) /* Load vp to gpu */ (context->chipobj.EmitShader)(ctx, - &(vp->shadercode), + &(vp->shaderbo), (GLvoid *)(vp->r700Shader.pProgram), vp->r700Shader.uShaderBinaryDWORDSize); @@ -410,7 +372,7 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) (context->chipobj.MemUse)(context, vp->shadercode.buf->id); */ - r700->SQ_PGM_START_VS.u32All = (vp->shadercode.aos_offset >> 8) & 0x00FFFFFF; + r700->SQ_PGM_START_VS.u32All = 0; /* set from buffer object. */ SETfield(r700->SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.nRegs + 1, NUM_GPRS_shift, NUM_GPRS_mask); @@ -438,24 +400,26 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) if(NULL != paramList) { _mesa_load_state_parameters(ctx, paramList); -#if 0 /* to be enabled */ + unNumParamData = paramList->NumParameters * 4; - R700_CMDBUF_CHECK_SPACE(unNumParamData + 2); - R700EP3 (context, IT_SET_ALU_CONST, unNumParamData); + BEGIN_BATCH_NO_AUTOSTATE(unNumParamData + 2); + + OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData)); /* assembler map const from very beginning. */ - R700E32 (context, SQ_ALU_CONSTANT_VS_OFFSET * 4); + OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4); unNumParamData = paramList->NumParameters; for(ui=0; uiParameterValues[ui][0]))); - R700E32 (context, *((unsigned int*)&(paramList->ParameterValues[ui][1]))); - R700E32 (context, *((unsigned int*)&(paramList->ParameterValues[ui][2]))); - R700E32 (context, *((unsigned int*)&(paramList->ParameterValues[ui][3]))); + OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][0]))); + OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1]))); + OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2]))); + OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3]))); } -#endif /* to be enabled */ + END_BATCH(); + COMMIT_BATCH(); } return GL_TRUE; diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.h b/src/mesa/drivers/dri/r600/r700_vertprog.h index 0822335c10..6a9726a3d0 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.h +++ b/src/mesa/drivers/dri/r600/r700_vertprog.h @@ -55,7 +55,8 @@ struct r700_vertex_program /* ... */ - struct r600_dma_region shadercode; + void * shaderbo; + ArrayDesc aos_desc[VERT_ATTRIB_MAX]; }; @@ -82,11 +83,6 @@ extern void r700SelectVertexShader(GLcontext *ctx); extern GLboolean r700SetupVertexProgram(GLcontext * ctx); -extern void r700SetupVTXConstans(GLcontext * ctx, - unsigned int nStreamID, - unsigned int aos_offset, - unsigned int size, /* number of elements in vector */ - unsigned int stride, - unsigned int Count); /* number of vectors in stream */ +extern void * r700GetActiveVpShaderBo(GLcontext * ctx); #endif /* _R700_VERTPROG_H_ */ diff --git a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h index 851b488433..abb023c7de 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h +++ b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h @@ -16,85 +16,7 @@ void rcommonBeginBatch(radeonContextPtr rmesa, const char *function, int line); -#define RADEON_CP_PACKET3_NOP 0xC0001000 -#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900 -#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 -#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00 -#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 -#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400 -#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 -#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800 -#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 -#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 -#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 -#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 -#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 -#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 -#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 -#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 -#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500 -#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 -#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 -#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 -#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 - -/* r6xx/r7xx packet 3 type offsets */ -#define R600_SET_CONFIG_REG_OFFSET 0x00008000 -#define R600_SET_CONFIG_REG_END 0x0000ac00 -#define R600_SET_CONTEXT_REG_OFFSET 0x00028000 -#define R600_SET_CONTEXT_REG_END 0x00029000 -#define R600_SET_ALU_CONST_OFFSET 0x00030000 -#define R600_SET_ALU_CONST_END 0x00032000 -#define R600_SET_RESOURCE_OFFSET 0x00038000 -#define R600_SET_RESOURCE_END 0x0003c000 -#define R600_SET_SAMPLER_OFFSET 0x0003c000 -#define R600_SET_SAMPLER_END 0x0003cff0 -#define R600_SET_CTL_CONST_OFFSET 0x0003cff0 -#define R600_SET_CTL_CONST_END 0x0003e200 -#define R600_SET_LOOP_CONST_OFFSET 0x0003e200 -#define R600_SET_LOOP_CONST_END 0x0003e380 -#define R600_SET_BOOL_CONST_OFFSET 0x0003e380 -#define R600_SET_BOOL_CONST_END 0x00040000 - -/* r6xx/r7xx packet 3 types */ -#define R600_IT_INDIRECT_BUFFER_END 0x00001700 -#define R600_IT_SET_PREDICATION 0x00002000 -#define R600_IT_REG_RMW 0x00002100 -#define R600_IT_COND_EXEC 0x00002200 -#define R600_IT_PRED_EXEC 0x00002300 -#define R600_IT_START_3D_CMDBUF 0x00002400 -#define R600_IT_DRAW_INDEX_2 0x00002700 -#define R600_IT_CONTEXT_CONTROL 0x00002800 -#define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900 -#define R600_IT_INDEX_TYPE 0x00002A00 -#define R600_IT_DRAW_INDEX 0x00002B00 -#define R600_IT_DRAW_INDEX_AUTO 0x00002D00 -#define R600_IT_DRAW_INDEX_IMMD 0x00002E00 -#define R600_IT_NUM_INSTANCES 0x00002F00 -#define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400 -#define R600_IT_INDIRECT_BUFFER_MP 0x00003800 -#define R600_IT_MEM_SEMAPHORE 0x00003900 -#define R600_IT_MPEG_INDEX 0x00003A00 -#define R600_IT_WAIT_REG_MEM 0x00003C00 -#define R600_IT_MEM_WRITE 0x00003D00 -#define R600_IT_INDIRECT_BUFFER 0x00003200 -#define R600_IT_CP_INTERRUPT 0x00004000 -#define R600_IT_SURFACE_SYNC 0x00004300 -#define R600_IT_ME_INITIALIZE 0x00004400 -#define R600_IT_COND_WRITE 0x00004500 -#define R600_IT_EVENT_WRITE 0x00004600 -#define R600_IT_EVENT_WRITE_EOP 0x00004700 -#define R600_IT_ONE_REG_WRITE 0x00005700 -#define R600_IT_SET_CONFIG_REG 0x00006800 -#define R600_IT_SET_CONTEXT_REG 0x00006900 -#define R600_IT_SET_ALU_CONST 0x00006A00 -#define R600_IT_SET_BOOL_CONST 0x00006B00 -#define R600_IT_SET_LOOP_CONST 0x00006C00 -#define R600_IT_SET_RESOURCE 0x00006D00 -#define R600_IT_SET_SAMPLER 0x00006E00 -#define R600_IT_SET_CTL_CONST 0x00006F00 -#define R600_IT_SURFACE_BASE_UPDATE 0x00007300 - +/* +r6/r7 : code here moved */ #define CP_PACKET2 (2 << 30) #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) @@ -188,54 +110,14 @@ void rcommonBeginBatch(radeonContextPtr rmesa, #define OUT_BATCH_FLOAT32(f) \ OUT_BATCH(radeonPackFloat32((f))) -/* R600/R700 */ -#define R600_OUT_BATCH_REGS(reg, num) \ -do { \ - if ((reg) >= R600_SET_CONFIG_REG_OFFSET && (reg) < R600_SET_CONFIG_REG_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, (num))); \ - OUT_BATCH(((reg) - R600_SET_CONFIG_REG_OFFSET) >> 2); \ - } else if ((reg) >= R600_SET_CONTEXT_REG_OFFSET && (reg) < R600_SET_CONTEXT_REG_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_CONTEXT_REG, (num))); \ - OUT_BATCH(((reg) - R600_SET_CONTEXT_REG_OFFSET) >> 2); \ - } else if ((reg) >= R600_SET_ALU_CONST_OFFSET && (reg) < R600_SET_ALU_CONST_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (num))); \ - OUT_BATCH(((reg) - R600_SET_ALU_CONST_OFFSET) >> 2); \ - } else if ((reg) >= R600_SET_RESOURCE_OFFSET && (reg) < R600_SET_RESOURCE_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, (num))); \ - OUT_BATCH(((reg) - R600_SET_RESOURCE_OFFSET) >> 2); \ - } else if ((reg) >= R600_SET_SAMPLER_OFFSET && (reg) < R600_SET_SAMPLER_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, (num))); \ - OUT_BATCH(((reg) - R600_SET_SAMPLER_OFFSET) >> 2); \ - } else if ((reg) >= R600_SET_CTL_CONST_OFFSET && (reg) < R600_SET_CTL_CONST_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, (num))); \ - OUT_BATCH(((reg) - R600_SET_CTL_CONST_OFFSET) >> 2); \ - } else if ((reg) >= R600_SET_LOOP_CONST_OFFSET && (reg) < R600_SET_LOOP_CONST_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_LOOP_CONST, (num))); \ - OUT_BATCH(((reg) - R600_SET_LOOP_CONST_OFFSET) >> 2); \ - } else if ((reg) >= R600_SET_BOOL_CONST_OFFSET && (reg) < R600_SET_BOOL_CONST_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_BOOL_CONST, (num))); \ - OUT_BATCH(((reg) - R600_SET_BOOL_CONST_OFFSET) >> 2); \ - } else { \ - OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (num))); \ - } \ -} while (0) - -/** Single register write to command buffer; requires 3 dwords for most things. */ -#define R600_OUT_BATCH_REGVAL(reg, val) \ - R600_OUT_BATCH_REGS((reg), 1); \ - OUT_BATCH((val)) - -/** Continuous register range write to command buffer; requires 1 dword, - * expects count dwords afterwards for register contents. */ -#define R600_OUT_BATCH_REGSEQ(reg, count) \ - R600_OUT_BATCH_REGS((reg), (count)) +/* +r6/r7 : code here moved */ /* Fire the buffered vertices no matter what. */ static INLINE void radeon_firevertices(radeonContextPtr radeon) { if (radeon->cmdbuf.cs->cdw || radeon->dma.flush ) - radeonFlush(radeon->glCtx); + radeon->glCtx->Driver.Flush(radeon->glCtx); /* +r6/r7 */ } #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 756c09fff3..691615938f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -914,7 +914,7 @@ again: if (ret == RADEON_CS_SPACE_OP_TO_BIG) return GL_FALSE; if (ret == RADEON_CS_SPACE_FLUSH) { - radeonFlush(ctx); + ctx->Driver.Flush(ctx); /* +r6/r7 */ if (flushed) return GL_FALSE; flushed = 1; @@ -1014,7 +1014,7 @@ void radeonFinish(GLcontext * ctx) struct gl_framebuffer *fb = ctx->DrawBuffer; int i; - radeonFlush(ctx); + ctx->Driver.Flush(ctx); /* +r6/r7 */ if (radeon->radeonScreen->kernel_mm) { for (i = 0; i < fb->_NumColorDrawBuffers; i++) { diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index b47b095cf2..b33417e93e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -216,22 +216,28 @@ static int cs_process_relocs(struct radeon_cs *cs) csm = (struct cs_manager_legacy*)cs->csm; relocs = (struct cs_reloc_legacy *)cs->relocs; - restart: - for (i = 0; i < cs->crelocs; i++) { - for (j = 0; j < relocs[i].cindices; j++) { +restart: + for (i = 0; i < cs->crelocs; i++) + { + for (j = 0; j < relocs[i].cindices; j++) + { uint32_t soffset, eoffset; r = radeon_bo_legacy_validate(relocs[i].base.bo, &soffset, &eoffset); - if (r == -EAGAIN) - goto restart; - if (r) { + if (r == -EAGAIN) + { + goto restart; + } + if (r) + { fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", relocs[i].base.bo, soffset, eoffset); return r; } cs->packets[relocs[i].indices[j]] += soffset; - if (cs->packets[relocs[i].indices[j]] >= eoffset) { + if (cs->packets[relocs[i].indices[j]] >= eoffset) + { /* radeon_bo_debug(relocs[i].base.bo, 12); */ fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", relocs[i].base.bo, soffset, eoffset); @@ -280,7 +286,8 @@ static int cs_emit(struct radeon_cs *cs) csm->ctx->vtbl.emit_cs_header(cs, csm->ctx); /* append buffer age */ - if (IS_R300_CLASS(csm->ctx->radeonScreen)) { + if ( IS_R300_CLASS(csm->ctx->radeonScreen) ) + { age.scratch.cmd_type = R300_CMD_SCRATCH; /* Scratch register 2 corresponds to what radeonGetAge polls */ csm->pending_age = 0; @@ -315,7 +322,8 @@ static int cs_emit(struct radeon_cs *cs) if (r) { return r; } - if (!IS_R300_CLASS(csm->ctx->radeonScreen)) { + if ((!IS_R300_CLASS(csm->ctx->radeonScreen)) && + (!IS_R600_CLASS(csm->ctx->radeonScreen))) { /* +r6/r7 : No irq for r6/r7 yet. */ drm_radeon_irq_emit_t emit_cmd; emit_cmd.irq_seq = &csm->pending_age; r = drmCommandWrite(cs->csm->fd, DRM_RADEON_IRQ_EMIT, &emit_cmd, sizeof(emit_cmd)); @@ -387,59 +395,71 @@ static int cs_check_space(struct radeon_cs *cs, struct radeon_cs_space_check *bo return 0; /* prepare */ - for (i = 0; i < num_bo; i++) { - bo = bos[i].bo; - - bos[i].new_accounted = 0; - read_domains = bos[i].read_domains; - write_domain = bos[i].write_domain; - - /* pinned bos don't count */ - if (radeon_legacy_bo_is_static(bo)) - continue; + for (i = 0; i < num_bo; i++) + { + bo = bos[i].bo; + + bos[i].new_accounted = 0; + read_domains = bos[i].read_domains; + write_domain = bos[i].write_domain; + + /* pinned bos don't count */ + if (radeon_legacy_bo_is_static(bo)) + continue; - /* already accounted this bo */ - if (write_domain && (write_domain == bo->space_accounted)) - continue; + /* already accounted this bo */ + if (write_domain && (write_domain == bo->space_accounted)) + continue; - if (read_domains && ((read_domains << 16) == bo->space_accounted)) - continue; + if (read_domains && ((read_domains << 16) == bo->space_accounted)) + continue; - if (bo->space_accounted == 0) { - if (write_domain == RADEON_GEM_DOMAIN_VRAM) - this_op_vram_write += bo->size; - else if (write_domain == RADEON_GEM_DOMAIN_GTT) - this_op_gart_write += bo->size; - else - this_op_read += bo->size; - bos[i].new_accounted = (read_domains << 16) | write_domain; - } else { - uint16_t old_read, old_write; - - old_read = bo->space_accounted >> 16; - old_write = bo->space_accounted & 0xffff; - - if (write_domain && (old_read & write_domain)) { - bos[i].new_accounted = write_domain; - /* moving from read to a write domain */ - if (write_domain == RADEON_GEM_DOMAIN_VRAM) { - this_op_read -= bo->size; - this_op_vram_write += bo->size; - } else if (write_domain == RADEON_GEM_DOMAIN_VRAM) { - this_op_read -= bo->size; - this_op_gart_write += bo->size; - } - } else if (read_domains & old_write) { - bos[i].new_accounted = bo->space_accounted & 0xffff; - } else { - /* rewrite the domains */ - if (write_domain != old_write) - fprintf(stderr,"WRITE DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, write_domain, old_write); - if (read_domains != old_read) - fprintf(stderr,"READ DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, read_domains, old_read); - return RADEON_CS_SPACE_FLUSH; - } - } + if (bo->space_accounted == 0) + { + if (write_domain == RADEON_GEM_DOMAIN_VRAM) + this_op_vram_write += bo->size; + else if (write_domain == RADEON_GEM_DOMAIN_GTT) + this_op_gart_write += bo->size; + else + this_op_read += bo->size; + bos[i].new_accounted = (read_domains << 16) | write_domain; + } + else + { + uint16_t old_read, old_write; + + old_read = bo->space_accounted >> 16; + old_write = bo->space_accounted & 0xffff; + + if (write_domain && (old_read & write_domain)) + { + bos[i].new_accounted = write_domain; + /* moving from read to a write domain */ + if (write_domain == RADEON_GEM_DOMAIN_VRAM) + { + this_op_read -= bo->size; + this_op_vram_write += bo->size; + } + else if (write_domain == RADEON_GEM_DOMAIN_VRAM) + { + this_op_read -= bo->size; + this_op_gart_write += bo->size; + } + } + else if (read_domains & old_write) + { + bos[i].new_accounted = bo->space_accounted & 0xffff; + } + else + { + /* rewrite the domains */ + if (write_domain != old_write) + fprintf(stderr,"WRITE DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, write_domain, old_write); + if (read_domains != old_read) + fprintf(stderr,"READ DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, read_domains, old_read); + return RADEON_CS_SPACE_FLUSH; + } + } } if (this_op_read < 0) diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index f62ca7f9eb..b2585eae77 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -165,7 +165,7 @@ radeon_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, return GL_FALSE; } - radeonFlush(ctx); + ctx->Driver.Flush(ctx); /* +r6/r7 */ if (rrb->bo) radeon_bo_unref(rrb->bo); @@ -371,7 +371,7 @@ radeon_framebuffer_renderbuffer(GLcontext * ctx, GLenum attachment, struct gl_renderbuffer *rb) { - radeonFlush(ctx); + ctx->Driver.Flush(ctx); /* +r6/r7 */ _mesa_framebuffer_renderbuffer(ctx, fb, attachment, rb); radeon_draw_buffer(ctx, fb); diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index b75db5b80c..be3b816b86 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -61,8 +61,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r300_tex.h" #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) #include "r600_context.h" -#include "r700_fragprog.h" -#include "r700_tex.h" +//#include "r700_driconf.h" /* +r6/r7 */ +#include "r700_tex.h" /* +r6/r7 */ #endif #include "utils.h" @@ -405,13 +405,13 @@ static const __DRItexBufferExtension r300TexBufferExtension = { #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) static const __DRItexOffsetExtension r600texOffsetExtension = { { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, - r700SetTexOffset, + r700SetTexOffset, /* +r6/r7 */ }; static const __DRItexBufferExtension r600TexBufferExtension = { { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, - r700SetTexBuffer, - r700SetTexBuffer2, + r700SetTexBuffer, /* +r6/r7 */ + r700SetTexBuffer2, /* +r6/r7 */ }; #endif @@ -941,7 +941,6 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); #endif - /* parse information in __driConfigOptions */ driParseOptionInfo (&screen->optionCache, __driConfigOptions, __driNConfigOptions); -- cgit v1.2.3 From 2a7a2c6b77116fd475e1d05fb0adbd1702d11f77 Mon Sep 17 00:00:00 2001 From: Richard Li Date: Fri, 15 May 2009 19:37:09 -0400 Subject: Fix r6 code bugs. --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 19 +-- src/mesa/drivers/dri/r600/r600_cmdbuf.h | 36 ++--- src/mesa/drivers/dri/r600/r600_context.c | 12 ++ src/mesa/drivers/dri/r600/r600_context.h | 5 +- src/mesa/drivers/dri/r600/r600_emit.c | 15 +- src/mesa/drivers/dri/r600/r600_emit.h | 3 +- src/mesa/drivers/dri/r600/r600_swtcl.c | 6 +- src/mesa/drivers/dri/r600/r700_chip.c | 153 ++++++++++++++------- src/mesa/drivers/dri/r600/r700_chip.h | 4 +- src/mesa/drivers/dri/r600/r700_clear.c | 62 +++++---- src/mesa/drivers/dri/r600/r700_fragprog.c | 15 +- src/mesa/drivers/dri/r600/r700_ioctl.c | 2 +- src/mesa/drivers/dri/r600/r700_render.c | 67 +++++---- src/mesa/drivers/dri/r600/r700_state.c | 6 +- src/mesa/drivers/dri/r600/r700_vertprog.c | 15 +- .../drivers/dri/radeon/radeon_common_context.c | 12 ++ src/mesa/drivers/dri/radeon/radeon_screen.c | 40 ++++-- 17 files changed, 299 insertions(+), 173 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 8550457566..b1f78388e4 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -188,6 +188,7 @@ int r600_cs_write_reloc(struct radeon_cs *cs, cs->crelocs++; radeon_bo_ref(bo); + return 0; } @@ -245,6 +246,8 @@ static int r600_cs_end(struct radeon_cs *cs, { fprintf(stderr, "CS section size missmatch start at (%s,%s,%d) %d vs %d\n", cs->section_file, cs->section_func, cs->section_line, cs->section_ndw, cs->section_cdw); + fprintf(stderr, "cs->section_ndw = %d, cs->cdw = %d, cs->section_cdw = %d \n", + cs->section_ndw, cs->cdw, cs->section_cdw); fprintf(stderr, "CS section end at (%s,%s,%d)\n", file, func, line); return -EPIPE; @@ -356,7 +359,7 @@ static int r600_cs_emit(struct radeon_cs *cs) /* drm_r300_cmd_header_t age; */ uint32_t length_dw_reloc_chunk; uint64_t ull; - uint64_t * chunk_ptrs[2]; + uint64_t chunk_ptrs[2]; uint32_t reloc_chunk[128]; int r; int retry = 0; @@ -370,23 +373,23 @@ static int r600_cs_emit(struct radeon_cs *cs) if (r) { return 0; } - + /* raw ib chunk */ cs_chunk[0].chunk_id = RADEON_CHUNK_ID_IB; cs_chunk[0].length_dw = cs->cdw; - cs_chunk[0].chunk_data = (uint64_t)(cs->packets); + cs_chunk[0].chunk_data = (unsigned long)(cs->packets); /* reloc chaunk */ cs_chunk[1].chunk_id = RADEON_CHUNK_ID_RELOCS; cs_chunk[1].length_dw = length_dw_reloc_chunk; - cs_chunk[1].chunk_data = (uint64_t)&(reloc_chunk[0]); + cs_chunk[1].chunk_data = (unsigned long)&(reloc_chunk[0]); - chunk_ptrs[0] = (uint64_t * )&(cs_chunk[0]); - chunk_ptrs[1] = (uint64_t * )&(cs_chunk[1]); + chunk_ptrs[0] = (uint64_t)(unsigned long)&(cs_chunk[0]); + chunk_ptrs[1] = (uint64_t)(unsigned long)&(cs_chunk[1]); cs_cmd.num_chunks = 2; - cs_cmd.cs_id = 0; - cs_cmd.chunks = (uint64_t)&(chunk_ptrs[0]); + /* cs_cmd.cs_id = 0; */ + cs_cmd.chunks = (uint64_t)(unsigned long)chunk_ptrs; /* dump_cmdbuf(cs); */ diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.h b/src/mesa/drivers/dri/r600/r600_cmdbuf.h index dbb723b2b5..9ad73d9d3a 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.h +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.h @@ -167,38 +167,38 @@ static inline void r600_cs_write_dword(struct radeon_cs *cs, uint32_t dword) #define R600_OUT_BATCH_REGS(reg, num) \ do { \ if ((reg) >= R600_SET_CONFIG_REG_OFFSET && (reg) < R600_SET_CONFIG_REG_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, (num))); \ - OUT_BATCH(((reg) - R600_SET_CONFIG_REG_OFFSET) >> 2); \ + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, (num))); \ + R600_OUT_BATCH(((reg) - R600_SET_CONFIG_REG_OFFSET) >> 2); \ } else if ((reg) >= R600_SET_CONTEXT_REG_OFFSET && (reg) < R600_SET_CONTEXT_REG_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_CONTEXT_REG, (num))); \ - OUT_BATCH(((reg) - R600_SET_CONTEXT_REG_OFFSET) >> 2); \ + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONTEXT_REG, (num))); \ + R600_OUT_BATCH(((reg) - R600_SET_CONTEXT_REG_OFFSET) >> 2); \ } else if ((reg) >= R600_SET_ALU_CONST_OFFSET && (reg) < R600_SET_ALU_CONST_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (num))); \ - OUT_BATCH(((reg) - R600_SET_ALU_CONST_OFFSET) >> 2); \ + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (num))); \ + R600_OUT_BATCH(((reg) - R600_SET_ALU_CONST_OFFSET) >> 2); \ } else if ((reg) >= R600_SET_RESOURCE_OFFSET && (reg) < R600_SET_RESOURCE_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, (num))); \ - OUT_BATCH(((reg) - R600_SET_RESOURCE_OFFSET) >> 2); \ + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, (num))); \ + R600_OUT_BATCH(((reg) - R600_SET_RESOURCE_OFFSET) >> 2); \ } else if ((reg) >= R600_SET_SAMPLER_OFFSET && (reg) < R600_SET_SAMPLER_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, (num))); \ - OUT_BATCH(((reg) - R600_SET_SAMPLER_OFFSET) >> 2); \ + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, (num))); \ + R600_OUT_BATCH(((reg) - R600_SET_SAMPLER_OFFSET) >> 2); \ } else if ((reg) >= R600_SET_CTL_CONST_OFFSET && (reg) < R600_SET_CTL_CONST_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, (num))); \ - OUT_BATCH(((reg) - R600_SET_CTL_CONST_OFFSET) >> 2); \ + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, (num))); \ + R600_OUT_BATCH(((reg) - R600_SET_CTL_CONST_OFFSET) >> 2); \ } else if ((reg) >= R600_SET_LOOP_CONST_OFFSET && (reg) < R600_SET_LOOP_CONST_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_LOOP_CONST, (num))); \ - OUT_BATCH(((reg) - R600_SET_LOOP_CONST_OFFSET) >> 2); \ + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_LOOP_CONST, (num))); \ + R600_OUT_BATCH(((reg) - R600_SET_LOOP_CONST_OFFSET) >> 2); \ } else if ((reg) >= R600_SET_BOOL_CONST_OFFSET && (reg) < R600_SET_BOOL_CONST_END) { \ - OUT_BATCH(CP_PACKET3(R600_IT_SET_BOOL_CONST, (num))); \ - OUT_BATCH(((reg) - R600_SET_BOOL_CONST_OFFSET) >> 2); \ + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_BOOL_CONST, (num))); \ + R600_OUT_BATCH(((reg) - R600_SET_BOOL_CONST_OFFSET) >> 2); \ } else { \ - OUT_BATCH(CP_PACKET0((reg), (num))); \ + R600_OUT_BATCH(CP_PACKET0((reg), (num))); \ } \ } while (0) /** Single register write to command buffer; requires 3 dwords for most things. */ #define R600_OUT_BATCH_REGVAL(reg, val) \ R600_OUT_BATCH_REGS((reg), 1); \ - OUT_BATCH((val)) + R600_OUT_BATCH((val)) /** Continuous register range write to command buffer; requires 1 dword, * expects count dwords afterwards for register contents. */ diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 3c8ba003d4..e6c03ecfd5 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -448,3 +448,15 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, return GL_TRUE; } +/* Clean our own things only, radeonDestroyContext will do every thing else. */ +void +r600DestroyContext (__DRIcontextPrivate * driContextPriv) +{ + GET_CURRENT_CONTEXT (ctx); + context_t *context = R700_CONTEXT(ctx); + + (context->chipobj.DestroyChipObj)(context->chipobj.pvChipObj); +} + + + diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index 70108b74c4..ae80037602 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -159,7 +159,7 @@ typedef struct chip_object void *pvChipObj; /* ------------ OUT ------------------- */ - GLboolean (*DestroyChipObj)(void* pvChipObj); + GLboolean (*DestroyChipObj)(GLcontext * ctx); void (*InitFuncs)(struct dd_function_table *functions); @@ -171,7 +171,8 @@ typedef struct chip_object GLboolean (*EmitShader)( GLcontext * ctx, void ** shaderbo, GLvoid * data, - int sizeinDWORD); + int sizeinDWORD, + char * szShaderUsage); GLboolean (*DeleteShader)(GLcontext * ctx, void * shaderbo); void (*FreeDmaRegion)( GLcontext * ctx, diff --git a/src/mesa/drivers/dri/r600/r600_emit.c b/src/mesa/drivers/dri/r600/r600_emit.c index fc8f987cab..dee4cd3435 100644 --- a/src/mesa/drivers/dri/r600/r600_emit.c +++ b/src/mesa/drivers/dri/r600/r600_emit.c @@ -175,7 +175,8 @@ void r600EmitCacheFlush(r600ContextPtr rmesa) GLboolean r600EmitShader(GLcontext * ctx, void ** shaderbo, GLvoid * data, - int sizeinDWORD) + int sizeinDWORD, + char * szShaderUsage) { radeonContextPtr radeonctx = RADEON_CONTEXT(ctx); @@ -183,12 +184,22 @@ GLboolean r600EmitShader(GLcontext * ctx, uint32_t *out; shader_again_alloc: +#ifdef RADEON_DEBUG_BO pbo = radeon_bo_open(radeonctx->radeonScreen->bom, 0, sizeinDWORD * 4, 256, + RADEON_GEM_DOMAIN_GTT, + 0, + szShaderUsage); +#else + pbo = radeon_bo_open(radeonctx->radeonScreen->bom, + 0, + sizeinDWORD * 4, + 256, RADEON_GEM_DOMAIN_GTT, 0); +#endif /* RADEON_DEBUG_BO */ if (!pbo) { @@ -211,6 +222,8 @@ shader_again_alloc: memcpy(out, data, sizeinDWORD * 4); + radeon_bo_unmap(pbo); + *shaderbo = (void*)pbo; return GL_TRUE; diff --git a/src/mesa/drivers/dri/r600/r600_emit.h b/src/mesa/drivers/dri/r600/r600_emit.h index 11765c868c..a2d8312287 100644 --- a/src/mesa/drivers/dri/r600/r600_emit.h +++ b/src/mesa/drivers/dri/r600/r600_emit.h @@ -44,7 +44,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. extern GLboolean r600EmitShader(GLcontext * ctx, void ** shaderbo, GLvoid * data, - int sizeinDWORD); + int sizeinDWORD, + char * szShaderUsage); extern GLboolean r600DeleteShader(GLcontext * ctx, void * shaderbo); diff --git a/src/mesa/drivers/dri/r600/r600_swtcl.c b/src/mesa/drivers/dri/r600/r600_swtcl.c index 4d134070d6..a60e7c942c 100644 --- a/src/mesa/drivers/dri/r600/r600_swtcl.c +++ b/src/mesa/drivers/dri/r600/r600_swtcl.c @@ -594,8 +594,8 @@ static void r600EmitVertexAOS(r600ContextPtr rmesa, GLuint vertex_size, struct r BEGIN_BATCH(7); OUT_BATCH_PACKET3(R600_PACKET3_3D_LOAD_VBPNTR, 2); - OUT_BATCH(1); - OUT_BATCH(vertex_size | (vertex_size << 8)); + R600_OUT_BATCH(1); + R600_OUT_BATCH(vertex_size | (vertex_size << 8)); OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0); END_BATCH(); #endif /* to be enabled */ @@ -612,7 +612,7 @@ static void r600EmitVbufPrim(r600ContextPtr rmesa, GLuint primitive, GLuint vert BEGIN_BATCH(3); OUT_BATCH_PACKET3(R600_PACKET3_3D_DRAW_VBUF_2, 0); - OUT_BATCH(R600_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type); + R600_OUT_BATCH(R600_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type); END_BATCH(); #endif /* to be enabled */ } diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index e534bb11b2..1f160364fa 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -41,16 +41,27 @@ extern const struct tnl_pipeline_stage *r700_pipeline[]; -static GLboolean r700DestroyChipObj(void* pvChipObj) +static GLboolean r700DestroyChipObj(GLcontext * ctx) { + context_t * context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700; - if(NULL == pvChipObj) + if(NULL == context->chipobj.pvChipObj) { return GL_TRUE; } - r700 = (R700_CHIP_CONTEXT *)pvChipObj; + r700 = (R700_CHIP_CONTEXT *)(context->chipobj.pvChipObj); + + if(0 != r700->pbo_vs_clear) + { + (context->chipobj.DeleteShader)(context, r700->pbo_vs_clear); + } + + if(0 != r700->pbo_fs_clear) + { + (context->chipobj.DeleteShader)(context, r700->pbo_fs_clear); + } FREE(r700->pStateList); @@ -405,19 +416,19 @@ void r700SetupVTXConstans(GLcontext * ctx, BEGIN_BATCH_NO_AUTOSTATE(9); - OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); - OUT_BATCH((nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); + R600_OUT_BATCH((nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE); - R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD1_0, + R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0, paos->bo, - uSQ_VTX_CONSTANT_WORD1_0, + uSQ_VTX_CONSTANT_WORD0_0, RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); - OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0); - OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0); - OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0); END_BATCH(); COMMIT_BATCH(); @@ -440,13 +451,13 @@ int r700SetupStreams(GLcontext * ctx) unsigned int i; BEGIN_BATCH_NO_AUTOSTATE(6); - OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); - OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); - OUT_BATCH(0); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); + R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); + R600_OUT_BATCH(0); - OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); - OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX); - OUT_BATCH(0); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); + R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX); + R600_OUT_BATCH(0); END_BATCH(); COMMIT_BATCH(); @@ -476,8 +487,33 @@ int r700SetupStreams(GLcontext * ctx) return R600_FALLBACK_NONE; } +inline GLboolean needRelocReg(context_t *context, unsigned int reg) +{ + switch (reg + ASIC_CONTEXT_BASE_INDEX) + { + case mmCB_COLOR0_BASE: + case mmCB_COLOR1_BASE: + case mmCB_COLOR2_BASE: + case mmCB_COLOR3_BASE: + case mmCB_COLOR4_BASE: + case mmCB_COLOR5_BASE: + case mmCB_COLOR6_BASE: + case mmCB_COLOR7_BASE: + case mmDB_DEPTH_BASE: + case mmSQ_PGM_START_VS: + case mmSQ_PGM_START_FS: + case mmSQ_PGM_START_ES: + case mmSQ_PGM_START_GS: + case mmSQ_PGM_START_PS: + return GL_TRUE; + break; + } + + return GL_FALSE; +} + inline GLboolean setRelocReg(context_t *context, unsigned int reg, - void * pbo_vs, void * pbo_fs) + GLboolean bUseStockShader) { BATCH_LOCALS(&context->radeon); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -507,9 +543,10 @@ inline GLboolean setRelocReg(context_t *context, unsigned int reg, return GL_FALSE; } - offset_mod.shift = RIGHT_SHIFT; - offset_mod.shiftbits = 8; - offset_mod.mask = 0x00FFFFFF; + /* refer to radeonCreateScreen : screen->fbLocation = (temp & 0xffff) << 16; */ + offset_mod.shift = NO_SHIFT; + offset_mod.shiftbits = 0; + offset_mod.mask = 0xFFFFFFFF; R600_OUT_BATCH_RELOC(r700->CB_COLOR0_BASE.u32All, rrb->bo, @@ -524,9 +561,9 @@ inline GLboolean setRelocReg(context_t *context, unsigned int reg, struct radeon_renderbuffer *rrb; rrb = radeon_get_depthbuffer(&context->radeon); - offset_mod.shift = RIGHT_SHIFT; - offset_mod.shiftbits = 8; - offset_mod.mask = 0x00FFFFFF; + offset_mod.shift = NO_SHIFT; + offset_mod.shiftbits = 0; + offset_mod.mask = 0xFFFFFFFF; R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All, rrb->bo, @@ -538,18 +575,25 @@ inline GLboolean setRelocReg(context_t *context, unsigned int reg, break; case mmSQ_PGM_START_VS: { - if(NULL != pbo_vs) + if(GL_TRUE == bUseStockShader) { - pbo = (struct radeon_bo *)pbo_vs; + if(NULL != r700->pbo_vs_clear) + { + pbo = (struct radeon_bo *)(r700->pbo_vs_clear); + } + else + { + return GL_FALSE; + } } else { pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); } - offset_mod.shift = RIGHT_SHIFT; - offset_mod.shiftbits = 8; - offset_mod.mask = 0x00FFFFFF; + offset_mod.shift = NO_SHIFT; + offset_mod.shiftbits = 0; + offset_mod.mask = 0xFFFFFFFF; R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_VS.u32All, pbo, @@ -563,18 +607,25 @@ inline GLboolean setRelocReg(context_t *context, unsigned int reg, case mmSQ_PGM_START_GS: case mmSQ_PGM_START_PS: { - if(NULL != pbo_fs) + if(GL_TRUE == bUseStockShader) { - pbo = (struct radeon_bo *)pbo_fs; + if(NULL != r700->pbo_fs_clear) + { + pbo = (struct radeon_bo *)(r700->pbo_fs_clear); + } + else + { + return GL_FALSE; + } } else { pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context)); } - offset_mod.shift = RIGHT_SHIFT; - offset_mod.shiftbits = 8; - offset_mod.mask = 0x00FFFFFF; + offset_mod.shift = NO_SHIFT; + offset_mod.shiftbits = 0; + offset_mod.mask = 0xFFFFFFFF; voffset = 0; R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_PS.u32All, @@ -589,7 +640,7 @@ inline GLboolean setRelocReg(context_t *context, unsigned int reg, return GL_FALSE; } -GLboolean r700SendContextStates(context_t *context, void * pbo_vs, void * pbo_fs) +GLboolean r700SendContextStates(context_t *context, GLboolean bUseStockShader) { BATCH_LOCALS(&context->radeon); @@ -606,18 +657,22 @@ GLboolean r700SendContextStates(context_t *context, void * pbo_vs, void * pbo_fs pInit = pState; - while(NULL != pState->pNext) + if(GL_FALSE == needRelocReg(context, pState->unOffset)) { - if( (pState->pNext->unOffset - pState->unOffset) > 1 ) + while(NULL != pState->pNext) { - break; - } - else - { - pState = pState->pNext; - toSend++; - } - }; + if( ((pState->pNext->unOffset - pState->unOffset) > 1) + || (GL_TRUE == needRelocReg(context, pState->pNext->unOffset)) ) + { + break; + } + else + { + pState = pState->pNext; + toSend++; + } + }; + } pState = pState->pNext; @@ -625,10 +680,10 @@ GLboolean r700SendContextStates(context_t *context, void * pbo_vs, void * pbo_fs R600_OUT_BATCH_REGSEQ(((pInit->unOffset + ASIC_CONTEXT_BASE_INDEX)<<2), toSend); for(ui=0; uiunOffset+ui), pbo_vs, pbo_fs) ) + if( GL_FALSE == setRelocReg(context, (pInit->unOffset+ui), bUseStockShader) ) { /* for not reloc reg. */ - OUT_BATCH(*(pInit->puiValue)); + R600_OUT_BATCH(*(pInit->puiValue)); } pInit = pInit->pNext; }; diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h index 30ca2cab84..42a72b7019 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.h +++ b/src/mesa/drivers/dri/r600/r700_chip.h @@ -447,6 +447,8 @@ typedef struct _R700_CHIP_CONTEXT R700_TEXTURE_STATES texture_states; + void * pbo_vs_clear; + void * pbo_fs_clear; GLboolean bEnablePerspective; } R700_CHIP_CONTEXT; @@ -454,7 +456,7 @@ typedef struct _R700_CHIP_CONTEXT #define R700_CONTEXT_STATES(context) ((R700_CHIP_CONTEXT *)(context->chipobj.pvChipObj)) extern GLboolean r700InitChipObject(context_t *context); -extern GLboolean r700SendContextStates(context_t *context, void * pbo_vs, void * pbo_fs); +extern GLboolean r700SendContextStates(context_t *context, GLboolean bUseStockShader); extern int r700SetupStreams(GLcontext * ctx); extern void r700SetupVTXConstans(GLcontext * ctx, unsigned int nStreamID, diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c index 743875dfe2..9a7cc000a6 100644 --- a/src/mesa/drivers/dri/r600/r700_clear.c +++ b/src/mesa/drivers/dri/r600/r700_clear.c @@ -140,17 +140,18 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) /* Setup vb */ BEGIN_BATCH_NO_AUTOSTATE(6); - OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); - OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); - OUT_BATCH(0); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); + R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); + R600_OUT_BATCH(0); - OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); - OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX); - OUT_BATCH(0); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); + R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX); + R600_OUT_BATCH(0); END_BATCH(); COMMIT_BATCH(); (context->chipobj.EmitVec)(ctx, &aos_vb, (GLvoid *)fVb, 4, 16, 6); + r700SetupVTXConstans(ctx, VERT_ATTRIB_POS, &aos_vb, 4, 16, 6); /* Setup shaders, copied from dump */ @@ -159,25 +160,33 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) SETbit(r700->SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); SETbit(r700->SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); /* vs */ - (context->chipobj.EmitShader)(ctx, &pbo_vs, (GLvoid *)(&uVs[0]), 28); + if(0 == r700->pbo_vs_clear) + { + (context->chipobj.EmitShader)(ctx, &(r700->pbo_vs_clear), (GLvoid *)(&uVs[0]), 28, "Clr VS"); + } + r700->SQ_PGM_START_VS.u32All = 0; r700->SQ_PGM_RESOURCES_VS.u32All = 0x00800004; /* vs const */ /* TODO : Set color here */ BEGIN_BATCH_NO_AUTOSTATE(4 + 2); - OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, 4)); - OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4); - OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[0]))); - OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[1]))); - OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[2]))); - OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[3]))); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, 4)); + R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4); + R600_OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[0]))); + R600_OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[1]))); + R600_OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[2]))); + R600_OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[3]))); END_BATCH(); COMMIT_BATCH(); r700->SPI_VS_OUT_CONFIG.u32All = 0x00000000; r700->SPI_PS_IN_CONTROL_0.u32All = 0x20000001; /* ps */ - (context->chipobj.EmitShader)(ctx, &pbo_fs, (GLvoid *)(&uFs[0]), 12); + if(0 == r700->pbo_fs_clear) + { + (context->chipobj.EmitShader)(ctx, &(r700->pbo_fs_clear), (GLvoid *)(&uFs[0]), 12, "Clr PS"); + } + r700->SQ_PGM_START_PS.u32All = 0; r700->SQ_PGM_RESOURCES_PS.u32All = 0x00800002; r700->SQ_PGM_EXPORTS_PS.u32All = 0x00000002; @@ -191,7 +200,7 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) r700->SQ_PGM_START_GS.u32All = 0; /* Now, send the states */ - r700SendContextStates(context, pbo_vs, pbo_fs); + r700SendContextStates(context, GL_TRUE); /* Draw */ GLuint numEntires, j; @@ -209,38 +218,33 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) SETfield(VGT_INDEX_TYPE, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask); - OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); - OUT_BATCH(VGT_INDEX_TYPE); + R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); + R600_OUT_BATCH(VGT_INDEX_TYPE); VGT_NUM_INDICES = numIndices; SETfield(VGT_PRIMITIVE_TYPE, DI_PT_TRILIST, VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask); - OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); - OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); - OUT_BATCH(VGT_PRIMITIVE_TYPE); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + R600_OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); + R600_OUT_BATCH(VGT_PRIMITIVE_TYPE); SETfield(VGT_DRAW_INITIATOR, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask); SETfield(VGT_DRAW_INITIATOR, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask); - OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (numIndices + 1))); - OUT_BATCH(VGT_NUM_INDICES); - OUT_BATCH(VGT_DRAW_INITIATOR); + R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (numIndices + 1))); + R600_OUT_BATCH(VGT_NUM_INDICES); + R600_OUT_BATCH(VGT_DRAW_INITIATOR); for (j=0; jchipobj.FlushCmdBuffer)(context); - /* TODO : keep these in context, don't load and release every time. */ - (context->chipobj.DeleteShader)(context, &pbo_vs); - - (context->chipobj.DeleteShader)(context, &pbo_fs); - (context->chipobj.FreeDmaRegion)(context, aos_vb.bo); /* Restore chip object. */ diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index d06af109e5..3aacad9919 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -281,7 +281,8 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) (context->chipobj.EmitShader)(ctx, &(fp->shaderbo), (GLvoid *)(fp->r700Shader.pProgram), - fp->r700Shader.uShaderBinaryDWORDSize); + fp->r700Shader.uShaderBinaryDWORDSize, + "FS"); fp->loaded = GL_TRUE; } @@ -344,19 +345,19 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) BEGIN_BATCH_NO_AUTOSTATE(2 + unNumParamData); - OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData)); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData)); /* assembler map const from very beginning. */ - OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4); + R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4); unNumParamData = paramList->NumParameters; for(ui=0; uiParameterValues[ui][0]))); - OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1]))); - OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2]))); - OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][0]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3]))); } END_BATCH(); COMMIT_BATCH(); diff --git a/src/mesa/drivers/dri/r600/r700_ioctl.c b/src/mesa/drivers/dri/r600/r700_ioctl.c index 7493efab0f..1ab3ee7de5 100644 --- a/src/mesa/drivers/dri/r600/r700_ioctl.c +++ b/src/mesa/drivers/dri/r600/r700_ioctl.c @@ -60,7 +60,7 @@ static void r700Flush(GLcontext *ctx) if (radeon->dma.flush) radeon->dma.flush( ctx ); - r700SendContextStates(context, NULL, NULL); + r700SendContextStates(context, GL_FALSE); if (radeon->cmdbuf.cs->cdw) rcommonFlushCmdBuf(radeon, __FUNCTION__); diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index f338cf823c..aee6a68565 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -59,9 +59,9 @@ void r700WaitForIdle(context_t *context) BATCH_LOCALS(&context->radeon); BEGIN_BATCH_NO_AUTOSTATE(3); - OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); - OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); - OUT_BATCH(1 << 15); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + R600_OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); + R600_OUT_BATCH(1 << 15); END_BATCH(); COMMIT_BATCH(); @@ -72,12 +72,12 @@ void r700WaitForIdleClean(context_t *context) BATCH_LOCALS(&context->radeon); BEGIN_BATCH_NO_AUTOSTATE(5); - OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); - OUT_BATCH(0x16); + R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); + R600_OUT_BATCH(0x16); - OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); - OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); - OUT_BATCH(1 << 17); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + R600_OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); + R600_OUT_BATCH(1 << 17); END_BATCH(); COMMIT_BATCH(); @@ -89,15 +89,15 @@ static void r700Start3D(context_t *context) if (context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV670) { BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH(CP_PACKET3(R600_IT_START_3D_CMDBUF, 1)); - OUT_BATCH(0); + R600_OUT_BATCH(CP_PACKET3(R600_IT_START_3D_CMDBUF, 1)); + R600_OUT_BATCH(0); END_BATCH(); } BEGIN_BATCH_NO_AUTOSTATE(3); - OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1)); - OUT_BATCH(0x80000000); - OUT_BATCH(0x80000000); + R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1)); + R600_OUT_BATCH(0x80000000); + R600_OUT_BATCH(0x80000000); END_BATCH(); COMMIT_BATCH(); @@ -183,11 +183,11 @@ GLboolean r700SyncSurf(context_t *context) BEGIN_BATCH_NO_AUTOSTATE(5); - OUT_BATCH(CP_PACKET3((IT_SURFACE_SYNC << 8), 3))); - OUT_BATCH(CP_COHER_CNTL); - OUT_BATCH(0xFFFFFFFF); - OUT_BATCH(0x00000000); - OUT_BATCH(10); + R600_OUT_BATCH(CP_PACKET3((IT_SURFACE_SYNC << 8), 3))); + R600_OUT_BATCH(CP_COHER_CNTL); + R600_OUT_BATCH(0xFFFFFFFF); + R600_OUT_BATCH(0x00000000); + R600_OUT_BATCH(10); END_BATCH(); COMMIT_BATCH(); @@ -241,7 +241,7 @@ static GLboolean r700RunRender(GLcontext * ctx, { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); - +#if 1 BATCH_LOCALS(&context->radeon); unsigned int i, j; @@ -286,7 +286,7 @@ static GLboolean r700RunRender(GLcontext * ctx, r700->SQ_PGM_START_ES.u32All = r700->SQ_PGM_START_PS.u32All; r700->SQ_PGM_START_GS.u32All = r700->SQ_PGM_START_PS.u32All; - r700SendContextStates(context, NULL, NULL); + r700SendContextStates(context, GL_FALSE); /* richard test code */ for (i = 0; i < vb->PrimitiveCount; i++) @@ -305,33 +305,32 @@ static GLboolean r700RunRender(GLcontext * ctx, numEntires = 2 /* VGT_INDEX_TYPE */ + 3 /* VGT_PRIMITIVE_TYPE */ - + numIndices + 3 /* DRAW_INDEX_IMMD */ - + 2; /* test stamp */ + + numIndices + 3; /* DRAW_INDEX_IMMD */ BEGIN_BATCH_NO_AUTOSTATE(numEntires); VGT_INDEX_TYPE |= DI_INDEX_SIZE_32_BIT << INDEX_TYPE_shift; - OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); - OUT_BATCH(VGT_INDEX_TYPE); + R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); + R600_OUT_BATCH(VGT_INDEX_TYPE); VGT_NUM_INDICES = numIndices; VGT_PRIMITIVE_TYPE |= r700PrimitiveType(prim) << VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift; - OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); - OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); - OUT_BATCH(VGT_PRIMITIVE_TYPE); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + R600_OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); + R600_OUT_BATCH(VGT_PRIMITIVE_TYPE); VGT_DRAW_INITIATOR |= DI_SRC_SEL_IMMEDIATE << SOURCE_SELECT_shift; VGT_DRAW_INITIATOR |= DI_MAJOR_MODE_0 << MAJOR_MODE_shift; - OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (numIndices + 1))); - OUT_BATCH(VGT_NUM_INDICES); - OUT_BATCH(VGT_DRAW_INITIATOR); + R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (numIndices + 1))); + R600_OUT_BATCH(VGT_NUM_INDICES); + R600_OUT_BATCH(VGT_DRAW_INITIATOR); for (j=0; jradeon, __FUNCTION__ ); return GL_FALSE; diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index a31a89627c..117d0add8b 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -692,7 +692,7 @@ void r700SetRenderTarget(context_t *context) nPitchInPixel = rrb->pitch/rrb->cpp; SETfield(r700->CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1, PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); - SETfield(r700->CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * rrb->base.Height)/64 )-1, + SETfield(r700->CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1, SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); r700->CB_COLOR0_BASE.u32All = 0; SETfield(r700->CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask); @@ -737,7 +737,7 @@ void r700SetRenderTarget(context_t *context) SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1, PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); - SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * rrb->base.Height)/64 )-1, + SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1, SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */ if(4 == rrb->cpp) @@ -909,7 +909,7 @@ void r700InitState(GLcontext * ctx) //------------------- r700->CB_COLOR0_FRAG.u32All = 0; r700->CB_COLOR0_MASK.u32All = 0; - r700->PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000; + r700->PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000; } void r700InitStateFuncs(struct dd_function_table *functions) //----------------- diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index f0dfbe20f0..4d113e2e0b 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -360,7 +360,8 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) (context->chipobj.EmitShader)(ctx, &(vp->shaderbo), (GLvoid *)(vp->r700Shader.pProgram), - vp->r700Shader.uShaderBinaryDWORDSize); + vp->r700Shader.uShaderBinaryDWORDSize, + "VS"); vp->loaded = GL_TRUE; } @@ -405,18 +406,18 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) BEGIN_BATCH_NO_AUTOSTATE(unNumParamData + 2); - OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData)); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData)); /* assembler map const from very beginning. */ - OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4); + R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4); unNumParamData = paramList->NumParameters; for(ui=0; uiParameterValues[ui][0]))); - OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1]))); - OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2]))); - OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][0]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3]))); } END_BATCH(); COMMIT_BATCH(); diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index f8a29fdba0..30c858fce0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -216,6 +216,11 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv ) radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL; + /* +r6/r7 */ + __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); + /* --------- */ + if (radeon == current) { radeon_firevertices(radeon); _mesa_make_current(NULL, NULL, NULL); @@ -224,6 +229,13 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv ) assert(radeon); if (radeon) { +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) /* +r6/r7 */ + if (IS_R600_CLASS(screen)) + { + r600DestroyContext(driContextPriv); + } +#endif + if (radeon->dma.current) { rcommonFlushCmdBuf( radeon, __FUNCTION__ ); } diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index be3b816b86..1d26e2c40a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1086,16 +1086,38 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->AGPMode = dri_priv->AGPMode; ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp); - if (ret) { - if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm) - screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; - else { - FREE( screen ); - fprintf(stderr, "Unable to get fb location need newer drm\n"); - return NULL; + + /* +r6/r7 */ + if(screen->chip_family >= CHIP_FAMILY_R600) + { + if (ret) + { + FREE( screen ); + fprintf(stderr, "Unable to get fb location need newer drm\n"); + return NULL; } - } else { - screen->fbLocation = (temp & 0xffff) << 16; + else + { + screen->fbLocation = (temp & 0xffff) << 24; + } + } + else + { + if (ret) + { + if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm) + screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; + else + { + FREE( screen ); + fprintf(stderr, "Unable to get fb location need newer drm\n"); + return NULL; + } + } + else + { + screen->fbLocation = (temp & 0xffff) << 16; + } } if (IS_R300_CLASS(screen)) { -- cgit v1.2.3 From 1b84d228d5a3c15530567ce193455af4932839bf Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 21 May 2009 17:38:14 -0400 Subject: r6xx: fix count on START_3D packet --- src/mesa/drivers/dri/r600/r700_render.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index aee6a68565..3d7eec3403 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -89,9 +89,9 @@ static void r700Start3D(context_t *context) if (context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV670) { BEGIN_BATCH_NO_AUTOSTATE(2); - R600_OUT_BATCH(CP_PACKET3(R600_IT_START_3D_CMDBUF, 1)); + R600_OUT_BATCH(CP_PACKET3(R600_IT_START_3D_CMDBUF, 0)); R600_OUT_BATCH(0); - END_BATCH(); + END_BATCH(); } BEGIN_BATCH_NO_AUTOSTATE(3); -- cgit v1.2.3 From 930b42693eb2e875d2447897dd1379d7bd273a95 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 26 May 2009 11:36:55 -0400 Subject: R6xx: select proper shader format --- src/mesa/drivers/dri/r600/r700_render.c | 2 +- src/mesa/drivers/dri/r600/r700_vertprog.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 3d7eec3403..464023e96f 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -250,7 +250,7 @@ static GLboolean r700RunRender(GLcontext * ctx, struct r700_fragment_program *fp = (struct r700_fragment_program *) (ctx->FragmentProgram._Current); - if (context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV670) + if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) { fp->r700AsmCode.bR6xx = 1; } diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index 4d113e2e0b..932555376c 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -297,7 +297,7 @@ void r700SelectVertexShader(GLcontext *ctx) context_t *context = R700_CONTEXT(ctx); struct r700_vertex_program *vpc = (struct r700_vertex_program *)ctx->VertexProgram._Current; - if (context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV670) + if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) { vpc->r700AsmCode.bR6xx = 1; } -- cgit v1.2.3 From f3eaba017c77f4dcf6cdecba7c19c9ea4fd3ce63 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 26 May 2009 12:21:54 -0400 Subject: r6xx: fix more r6xx specific cases --- src/mesa/drivers/dri/r600/r700_clear.c | 2 +- src/mesa/drivers/dri/r600/r700_render.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c index e2571626dc..c011b863fe 100644 --- a/src/mesa/drivers/dri/r600/r700_clear.c +++ b/src/mesa/drivers/dri/r600/r700_clear.c @@ -80,7 +80,7 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) 0x10000000, 0x340C90, 0x10000400, 0x20340C90, 0x10000800, 0x40340C90, 0x90000C00, 0x60200C90}; - if (context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV670) + if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) { uVs[9] = 0x541910; uVs[11] = 0x20541910; diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 464023e96f..fccf416c8c 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -86,7 +86,7 @@ void r700WaitForIdleClean(context_t *context) static void r700Start3D(context_t *context) { BATCH_LOCALS(&context->radeon); - if (context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV670) + if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) { BEGIN_BATCH_NO_AUTOSTATE(2); R600_OUT_BATCH(CP_PACKET3(R600_IT_START_3D_CMDBUF, 0)); -- cgit v1.2.3 From 98bc31171770456e245c157d19433f7d5ea28438 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 26 May 2009 14:30:26 -0400 Subject: enable surface sync function - needs to be more fine-grained --- src/mesa/drivers/dri/r600/r700_render.c | 45 ++++++++++++++++++++------------- 1 file changed, 27 insertions(+), 18 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index fccf416c8c..43b279da5c 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -61,7 +61,7 @@ void r700WaitForIdle(context_t *context) R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); R600_OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); - R600_OUT_BATCH(1 << 15); + R600_OUT_BATCH(WAIT_3D_IDLE_bit); END_BATCH(); COMMIT_BATCH(); @@ -73,11 +73,11 @@ void r700WaitForIdleClean(context_t *context) BEGIN_BATCH_NO_AUTOSTATE(5); R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); - R600_OUT_BATCH(0x16); + R600_OUT_BATCH(CACHE_FLUSH_AND_INV_EVENT); R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); R600_OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX); - R600_OUT_BATCH(1 << 17); + R600_OUT_BATCH(WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); END_BATCH(); COMMIT_BATCH(); @@ -167,23 +167,21 @@ GLboolean r700SendTextureState(context_t *context) GLboolean r700SyncSurf(context_t *context) { -#if 0 //to be enabled BATCH_LOCALS(&context->radeon); /* TODO : too heavy? */ unsigned int CP_COHER_CNTL = 0; - CP_COHER_CNTL |= TC_ACTION_ENA_bit - |VC_ACTION_ENA_bit - |CB_ACTION_ENA_bit - |DB_ACTION_ENA_bit - |SH_ACTION_ENA_bit - |SMX_ACTION_ENA_bit; + CP_COHER_CNTL |= (TC_ACTION_ENA_bit + | VC_ACTION_ENA_bit + | CB_ACTION_ENA_bit + | DB_ACTION_ENA_bit + | SH_ACTION_ENA_bit + | SMX_ACTION_ENA_bit); BEGIN_BATCH_NO_AUTOSTATE(5); - - R600_OUT_BATCH(CP_PACKET3((IT_SURFACE_SYNC << 8), 3))); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_SYNC, 3)); R600_OUT_BATCH(CP_COHER_CNTL); R600_OUT_BATCH(0xFFFFFFFF); R600_OUT_BATCH(0x00000000); @@ -191,7 +189,7 @@ GLboolean r700SyncSurf(context_t *context) END_BATCH(); COMMIT_BATCH(); -#endif + return GL_TRUE; } @@ -268,6 +266,9 @@ static GLboolean r700RunRender(GLcontext * ctx, return GL_TRUE; } + /* flush TX */ + //r700SyncSurf(context); /* */ + r700UpdateTextureState(context); r700SendTextureState(context); @@ -279,6 +280,10 @@ static GLboolean r700RunRender(GLcontext * ctx, } } + /* flush SQ */ + //r700SyncSurf(context); /* */ + //r700SyncSurf(context); /* */ + r700SetupShaders(ctx); /* set a valid base address to make the command checker happy */ @@ -286,6 +291,9 @@ static GLboolean r700RunRender(GLcontext * ctx, r700->SQ_PGM_START_ES.u32All = r700->SQ_PGM_START_PS.u32All; r700->SQ_PGM_START_GS.u32All = r700->SQ_PGM_START_PS.u32All; + /* flush vtx */ + //r700SyncSurf(context); /* */ + r700SendContextStates(context, GL_FALSE); /* richard test code */ @@ -337,11 +345,10 @@ static GLboolean r700RunRender(GLcontext * ctx, } /* Flush render op cached for last several quads. */ - BEGIN_BATCH_NO_AUTOSTATE(2); - R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); - R600_OUT_BATCH(CACHE_FLUSH_AND_INV_EVENT); - END_BATCH(); - COMMIT_BATCH(); + r700WaitForIdleClean(context); + + /* flush dst */ + //r700SyncSurf(context); /* */ (context->chipobj.FlushCmdBuffer)(context); @@ -353,6 +360,8 @@ static GLboolean r700RunRender(GLcontext * ctx, R600_OUT_BATCH_REGVAL((0x2144 << 2), 0x56785678); END_BATCH(); COMMIT_BATCH(); + + #endif //0 rcommonFlushCmdBuf( &context->radeon, __FUNCTION__ ); -- cgit v1.2.3 From 7f022fb5cd282826dac37b7ac0c02f551b6f5f98 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 28 May 2009 17:18:17 -0400 Subject: Argh. fix last commit. clears are still broken --- src/mesa/drivers/dri/r600/r700_clear.c | 2 ++ src/mesa/drivers/dri/r600/r700_render.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c index fa0d81b725..7ebab8daa1 100644 --- a/src/mesa/drivers/dri/r600/r700_clear.c +++ b/src/mesa/drivers/dri/r600/r700_clear.c @@ -41,6 +41,8 @@ extern void r700InitState (GLcontext * ctx); extern GLboolean r700SyncSurf(context_t *context); +extern void r700Start3D(context_t *context); +extern void r700WaitForIdleClean(context_t *context); static GLboolean r700ClearFast(context_t *context, GLbitfield mask) { diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 43b279da5c..a6f937ddeb 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -83,7 +83,7 @@ void r700WaitForIdleClean(context_t *context) COMMIT_BATCH(); } -static void r700Start3D(context_t *context) +void r700Start3D(context_t *context) { BATCH_LOCALS(&context->radeon); if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) -- cgit v1.2.3 From 846b24ea82cfb8a4867b6da1345584379f4aaa04 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 29 May 2009 12:49:45 -0400 Subject: r6xx/r7xx: switch to common dma functions for vecs --- src/mesa/drivers/dri/r600/r600_context.c | 4 - src/mesa/drivers/dri/r600/r600_context.h | 10 -- src/mesa/drivers/dri/r600/r600_emit.c | 162 ------------------------------- src/mesa/drivers/dri/r600/r600_emit.h | 12 --- src/mesa/drivers/dri/r600/r700_chip.c | 12 +-- src/mesa/drivers/dri/r600/r700_clear.c | 8 +- src/mesa/drivers/dri/r600/r700_render.c | 4 +- 7 files changed, 9 insertions(+), 203 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 5be486b176..3ea8f00086 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -286,12 +286,8 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, (r600->chipobj.InitFuncs)(&functions); r600->chipobj.EmitShader = r600EmitShader; r600->chipobj.DeleteShader = r600DeleteShader; - r600->chipobj.FreeDmaRegion = r600FreeDmaRegion; - r600->chipobj.EmitVec = r600EmitVec; - r600->chipobj.ReleaseArrays = r600ReleaseVec; r600->chipobj.LoadMemSurf = r600LoadMemSurf; r600->chipobj.AllocMemSurf = r600AllocMemSurf; - r600->chipobj.FlushCmdBuffer = r600FlushCmdBuffer; r600->chipobj.MemUse = r600MemUse; if (!radeonInitContext(&r600->radeon, &functions, diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index ae80037602..2740c0a1f8 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -175,17 +175,7 @@ typedef struct chip_object char * szShaderUsage); GLboolean (*DeleteShader)(GLcontext * ctx, void * shaderbo); - void (*FreeDmaRegion)( GLcontext * ctx, - void * shaderbo); - GLboolean (*EmitVec)(GLcontext * ctx, - struct radeon_aos *aos, - GLvoid * data, - int size, - int stride, - int count); void (*MemUse)(context_t *context, int id); - void (*ReleaseArrays)(GLcontext * ctx); - int (*FlushCmdBuffer)(GLcontext * ctx); GLboolean (*LoadMemSurf)(context_t *context, GLuint dst_offset, /* gpu addr */ GLuint dst_pitch_in_pixel, diff --git a/src/mesa/drivers/dri/r600/r600_emit.c b/src/mesa/drivers/dri/r600/r600_emit.c index e4ba656ee8..711dfefd73 100644 --- a/src/mesa/drivers/dri/r600/r600_emit.c +++ b/src/mesa/drivers/dri/r600/r600_emit.c @@ -47,115 +47,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r600_context.h" #include "r600_emit.h" -#if defined(USE_X86_ASM) -#define COPY_DWORDS( dst, src, nr ) \ -do { \ - int __tmp; \ - __asm__ __volatile__( "rep ; movsl" \ - : "=%c" (__tmp), "=D" (dst), "=S" (__tmp) \ - : "0" (nr), \ - "D" ((long)dst), \ - "S" ((long)src) ); \ -} while (0) -#else -#define COPY_DWORDS( dst, src, nr ) \ -do { \ - int j; \ - for ( j = 0 ; j < nr ; j++ ) \ - dst[j] = ((int *)src)[j]; \ - dst += nr; \ -} while (0) -#endif - -static void r600EmitVec4(uint32_t *out, GLvoid * data, int stride, int count) -{ - int i; - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d out %p data %p\n", - __FUNCTION__, count, stride, (void *)out, (void *)data); - - if (stride == 4) - COPY_DWORDS(out, data, count); - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out++; - data += stride; - } -} - -static void r600EmitVec8(uint32_t *out, GLvoid * data, int stride, int count) -{ - int i; - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d out %p data %p\n", - __FUNCTION__, count, stride, (void *)out, (void *)data); - - if (stride == 8) - COPY_DWORDS(out, data, count * 2); - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out[1] = *(int *)(data + 4); - out += 2; - data += stride; - } -} - -static void r600EmitVec12(uint32_t *out, GLvoid * data, int stride, int count) -{ - int i; - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d out %p data %p\n", - __FUNCTION__, count, stride, (void *)out, (void *)data); - - if (stride == 12) { - COPY_DWORDS(out, data, count * 3); - } - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out[1] = *(int *)(data + 4); - out[2] = *(int *)(data + 8); - out += 3; - data += stride; - } -} - -static void r600EmitVec16(uint32_t *out, GLvoid * data, int stride, int count) -{ - int i; - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s count %d stride %d out %p data %p\n", - __FUNCTION__, count, stride, (void *)out, (void *)data); - - if (stride == 16) - COPY_DWORDS(out, data, count * 4); - else - for (i = 0; i < count; i++) { - out[0] = *(int *)data; - out[1] = *(int *)(data + 4); - out[2] = *(int *)(data + 8); - out[3] = *(int *)(data + 12); - out += 4; - data += stride; - } -} - -/* Emit vertex data to GART memory - * Route inputs to the vertex processor - * This function should never return R600_FALLBACK_TCL when using software tcl. - */ -int r600EmitArrays(GLcontext * ctx) -{ - - return R600_FALLBACK_NONE; -} - void r600EmitCacheFlush(r600ContextPtr rmesa) { BATCH_LOCALS(&rmesa->radeon); @@ -241,56 +132,3 @@ GLboolean r600DeleteShader(GLcontext * ctx, return GL_TRUE; } - -GLboolean r600EmitVec(GLcontext * ctx, - struct radeon_aos *aos, - GLvoid * data, - int size, - int stride, - int count) -{ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - uint32_t *out; - - if (stride == 0) - { - radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); - aos->stride = 0; - } - else - { - radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); - aos->stride = size; - } - - aos->components = size; - aos->count = count; - - out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); - switch (size) { - case 1: r600EmitVec4(out, data, stride, count); break; - case 2: r600EmitVec8(out, data, stride, count); break; - case 3: r600EmitVec12(out, data, stride, count); break; - case 4: r600EmitVec16(out, data, stride, count); break; - default: - assert(0); - break; - } - - return GL_TRUE; -} - -void r600ReleaseVec(GLcontext * ctx) -{ - radeonReleaseArrays(ctx, ~0); -} - -void r600FreeDmaRegion(context_t *context, - void * shaderbo) -{ - struct radeon_bo *pbo = (struct radeon_bo *)shaderbo; - if(pbo) - { - radeon_bo_unref(pbo); - } -} diff --git a/src/mesa/drivers/dri/r600/r600_emit.h b/src/mesa/drivers/dri/r600/r600_emit.h index a2d8312287..d3c9ef59eb 100644 --- a/src/mesa/drivers/dri/r600/r600_emit.h +++ b/src/mesa/drivers/dri/r600/r600_emit.h @@ -50,16 +50,4 @@ extern GLboolean r600EmitShader(GLcontext * ctx, extern GLboolean r600DeleteShader(GLcontext * ctx, void * shaderbo); -extern GLboolean r600EmitVec(GLcontext * ctx, - struct radeon_aos *aos, - GLvoid * data, - int size, - int stride, - int count); - -extern void r600ReleaseVec(GLcontext * ctx); - -extern void r600FreeDmaRegion(context_t *context, - void * shaderbo); - #endif diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 9395bae296..12e9b474e1 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -467,12 +467,12 @@ int r700SetupStreams(GLcontext * ctx) unBit = 1 << i; if(vpc->mesa_program.Base.InputsRead & unBit) { - (context->chipobj.EmitVec)(ctx, - &context->radeon.tcl.aos[i], - vb->AttribPtr[i]->data, - vb->AttribPtr[i]->size, - vb->AttribPtr[i]->stride, - vb->Count); + rcommon_emit_vector(ctx, + &context->radeon.tcl.aos[i], + vb->AttribPtr[i]->data, + vb->AttribPtr[i]->size, + vb->AttribPtr[i]->stride, + vb->Count); /* currently aos are packed */ r700SetupVTXConstans(ctx, diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c index 7ebab8daa1..ffe236131c 100644 --- a/src/mesa/drivers/dri/r600/r700_clear.c +++ b/src/mesa/drivers/dri/r600/r700_clear.c @@ -154,7 +154,7 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) END_BATCH(); COMMIT_BATCH(); - (context->chipobj.EmitVec)(ctx, &aos_vb, (GLvoid *)fVb, 4, 16, 6); + rcommon_emit_vector(ctx, &aos_vb, (GLvoid *)fVb, 4, 16, 6); r700SetupVTXConstans(ctx, VERT_ATTRIB_POS, &aos_vb, 4, 16, 6); @@ -249,10 +249,6 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask) r700WaitForIdleClean(context); - (context->chipobj.FlushCmdBuffer)(context); - - (context->chipobj.FreeDmaRegion)(context, aos_vb.bo); - /* Restore chip object. */ memcpy(r700, &r700Saved, sizeof(R700_CHIP_CONTEXT)); @@ -268,7 +264,7 @@ void r700Clear(GLcontext * ctx, GLbitfield mask) return; } - r700ClearWithDraw(context, mask); + //r700ClearWithDraw(context, mask); } diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index a6f937ddeb..35f30605ce 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -350,9 +350,7 @@ static GLboolean r700RunRender(GLcontext * ctx, /* flush dst */ //r700SyncSurf(context); /* */ - (context->chipobj.FlushCmdBuffer)(context); - - (context->chipobj.ReleaseArrays)(ctx); + radeonReleaseArrays(ctx, 0); //richard test /* test stamp, write a number to mmSCRATCH4 */ -- cgit v1.2.3 From 9bcc421e68e041f44a554f710788c5042169cd1a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 29 May 2009 13:16:23 -0400 Subject: R6xx/r7xx: remove old sw tcl bits --- src/mesa/drivers/dri/r600/Makefile | 1 - src/mesa/drivers/dri/r600/r600_context.c | 13 +- src/mesa/drivers/dri/r600/r600_swtcl.c | 640 ------------------------------- src/mesa/drivers/dri/r600/r600_swtcl.h | 62 --- src/mesa/drivers/dri/r600/r700_render.c | 3 +- 5 files changed, 3 insertions(+), 716 deletions(-) delete mode 100644 src/mesa/drivers/dri/r600/r600_swtcl.c delete mode 100644 src/mesa/drivers/dri/r600/r600_swtcl.h (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/Makefile b/src/mesa/drivers/dri/r600/Makefile index 474a3167b4..2ad9d238df 100644 --- a/src/mesa/drivers/dri/r600/Makefile +++ b/src/mesa/drivers/dri/r600/Makefile @@ -43,7 +43,6 @@ DRIVER_SOURCES = \ radeon_program_pair.c \ radeon_nqssadce.c \ r600_emit.c \ - r600_swtcl.c \ r700_assembler.c \ r700_fragprog.c \ r700_vertprog.c \ diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 3ea8f00086..cbb63ba1f9 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -61,7 +61,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_span.h" #include "r600_cmdbuf.h" #include "r600_emit.h" -#include "r600_swtcl.h" #include "radeon_bocs_wrapper.h" #include "r700_chip.h" @@ -203,7 +202,7 @@ static void r600_init_vtbl(radeonContextPtr radeon) radeon->vtbl.get_lock = r600_get_lock; radeon->vtbl.update_viewport_offset = r700UpdateViewportOffset; radeon->vtbl.emit_cs_header = r600_vtbl_emit_cs_header; - radeon->vtbl.swtcl_flush = r600_swtcl_flush; + radeon->vtbl.swtcl_flush = NULL; radeon->vtbl.pre_emit_atoms = r600_vtbl_pre_emit_atoms; radeon->vtbl.fallback = r600_fallback; } @@ -228,13 +227,7 @@ static GLboolean r600AllocMemSurf(context_t *context, { return GL_TRUE; } -/* to be enabled */ -static int r600FlushCmdBuffer(context_t *context) -{ - int ret = 0; - return ret; -} /* to be enabled */ static void r600MemUse(context_t *context, int id) { @@ -416,10 +409,6 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, r600InitCmdBuf(r600); (r600->chipobj.InitState)(r600->radeon.glCtx); -#if 0 /* to be enabled */ - if (!(screen->chip_flags & RADEON_CHIPSET_TCL)) - r600InitSwtcl(ctx); -#endif TNL_CONTEXT(ctx)->Driver.RunPipeline = r600RunPipeline; diff --git a/src/mesa/drivers/dri/r600/r600_swtcl.c b/src/mesa/drivers/dri/r600/r600_swtcl.c deleted file mode 100644 index a60e7c942c..0000000000 --- a/src/mesa/drivers/dri/r600/r600_swtcl.c +++ /dev/null @@ -1,640 +0,0 @@ -/************************************************************************** - -Copyright (C) 2007 Dave Airlie - -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Dave Airlie - * Maciej Cencora - */ - -#include "tnl/tnl.h" -#include "tnl/t_pipeline.h" - -#include "r600_swtcl.h" -#include "r600_emit.h" - -#define EMIT_ATTR( ATTR, STYLE ) \ -do { \ - rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \ - rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \ - rmesa->radeon.swtcl.vertex_attr_count++; \ -} while (0) - -#define EMIT_PAD( N ) \ -do { \ - rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \ - rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \ - rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N); \ - rmesa->radeon.swtcl.vertex_attr_count++; \ -} while (0) - -#define ADD_ATTR(_attr, _format, _dst_loc, _swizzle, _write_mask) \ -do { \ - attrs[num_attrs].attr = (_attr); \ - attrs[num_attrs].format = (_format); \ - attrs[num_attrs].dst_loc = (_dst_loc); \ - attrs[num_attrs].swizzle = (_swizzle); \ - attrs[num_attrs].write_mask = (_write_mask); \ - ++num_attrs; \ -} while (0) - -static void r600SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsWritten) -{ -} - - -static void r600SetVertexFormat( GLcontext *ctx ) -{ -#if 0 /* to be enabled */ - r600ContextPtr rmesa = R600_CONTEXT( ctx ); - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *VB = &tnl->vb; - int fog_id = -1; - GLuint InputsRead = 0; - GLuint OutputsWritten = 0; - int num_attrs = 0; - struct vertex_attribute *attrs = rmesa->swtcl.vert_attrs; - - rmesa->swtcl.coloroffset = rmesa->swtcl.specoffset = 0; - rmesa->radeon.swtcl.vertex_attr_count = 0; - - if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_POS)) { - InputsRead |= 1 << VERT_ATTRIB_POS; - OutputsWritten |= 1 << VERT_RESULT_HPOS; - EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F ); - ADD_ATTR(VERT_ATTRIB_POS, EMIT_4F, SWTCL_OVM_POS, SWIZZLE_XYZW, MASK_XYZW); - rmesa->swtcl.coloroffset = 4; - } - - if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_COLOR0)) { - InputsRead |= 1 << VERT_ATTRIB_COLOR0; - OutputsWritten |= 1 << VERT_RESULT_COL0; -#if MESA_LITTLE_ENDIAN - EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA ); - ADD_ATTR(VERT_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA, SWTCL_OVM_COLOR0, SWIZZLE_XYZW, MASK_XYZW); -#else - EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR ); - ADD_ATTR(VERT_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR, SWTCL_OVM_COLOR0, SWIZZLE_XYZW, MASK_XYZW); -#endif - } - - if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_COLOR1 )) { - GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE); - InputsRead |= 1 << VERT_ATTRIB_COLOR1; - OutputsWritten |= 1 << VERT_RESULT_COL1; -#if MESA_LITTLE_ENDIAN - EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_4UB_4F_RGBA ); - ADD_ATTR(VERT_ATTRIB_COLOR1, EMIT_4UB_4F_RGBA, SWTCL_OVM_COLOR1, swiz, MASK_XYZW); -#else - EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_4UB_4F_ABGR ); - ADD_ATTR(VERT_ATTRIB_COLOR1, EMIT_4UB_4F_ABGR, SWTCL_OVM_COLOR1, swiz, MASK_XYZW); -#endif - rmesa->swtcl.specoffset = rmesa->swtcl.coloroffset + 1; - } - - if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_POINTSIZE )) { - GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO); - InputsRead |= 1 << VERT_ATTRIB_POINT_SIZE; - OutputsWritten |= 1 << VERT_RESULT_PSIZ; - EMIT_ATTR( _TNL_ATTRIB_POINTSIZE, EMIT_1F ); - ADD_ATTR(VERT_ATTRIB_POINT_SIZE, EMIT_1F, SWTCL_OVM_POINT_SIZE, swiz, MASK_X); - } - - if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_FOG)) { - /* find first free tex coord slot */ - if (RENDERINPUTS_TEST_RANGE(tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { - int i; - for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - if (!RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_TEX(i) )) { - fog_id = i; - break; - } - } - } else { - fog_id = 0; - } - - if (fog_id == -1) { - fprintf(stderr, "\tout of free texcoords to do fog\n"); - _mesa_exit(-1); - } - - InputsRead |= 1 << VERT_ATTRIB_FOG; - OutputsWritten |= 1 << VERT_RESULT_FOGC; - GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO); - EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1F ); - ADD_ATTR(VERT_ATTRIB_FOG, EMIT_1F, SWTCL_OVM_TEX(fog_id), swiz, MASK_X); - } - - if (RENDERINPUTS_TEST_RANGE(tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { - int i; - GLuint swiz, mask, format; - for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_TEX(i) )) { - switch (VB->TexCoordPtr[i]->size) { - case 1: - case 2: - format = EMIT_2F; - swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_ZERO, SWIZZLE_ZERO); - mask = MASK_X | MASK_Y; - break; - case 3: - format = EMIT_3F; - swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO); - mask = MASK_X | MASK_Y | MASK_Z; - break; - case 4: - format = EMIT_4F; - swiz = SWIZZLE_XYZW; - mask = MASK_XYZW; - break; - default: - continue; - } - InputsRead |= 1 << (VERT_ATTRIB_TEX0 + i); - OutputsWritten |= 1 << (VERT_RESULT_TEX0 + i); - EMIT_ATTR(_TNL_ATTRIB_TEX(i), format); - ADD_ATTR(VERT_ATTRIB_TEX0 + i, format, SWTCL_OVM_TEX(i), swiz, mask); - } - } - } - - /* RS can't put fragment position on the pixel stack, so stuff it in texcoord if needed */ - if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_POS) && (ctx->FragmentProgram._Current->Base.InputsRead & FRAG_BIT_WPOS)) { - int first_free_tex = -1; - if (fog_id >= 0) { - first_free_tex = fog_id+1; - } else { - if (RENDERINPUTS_TEST_RANGE(tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { - int i; - for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - if (!RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_TEX(i) )) { - first_free_tex = i; - break; - } - } - } else { - first_free_tex = 0; - } - } - - if (first_free_tex == -1) { - fprintf(stderr, "\tout of free texcoords to write w pos\n"); - _mesa_exit(-1); - } - - InputsRead |= 1 << (VERT_ATTRIB_TEX0 + first_free_tex); - OutputsWritten |= 1 << (VERT_RESULT_TEX0 + first_free_tex); - EMIT_ATTR( _TNL_ATTRIB_TEX(first_free_tex), EMIT_4F ); - ADD_ATTR(VERT_ATTRIB_TEX0 + first_free_tex, EMIT_4F, SWTCL_OVM_TEX(first_free_tex), SWIZZLE_XYZW, MASK_XYZW); - } - - R600_NEWPRIM(rmesa); - r600SwtclVAPSetup(ctx, InputsRead, OutputsWritten); - - rmesa->radeon.swtcl.vertex_size = - _tnl_install_attrs( ctx, - rmesa->radeon.swtcl.vertex_attrs, - rmesa->radeon.swtcl.vertex_attr_count, - NULL, 0 ); - - rmesa->radeon.swtcl.vertex_size /= 4; - - RENDERINPUTS_COPY(rmesa->state.render_inputs_bitset, tnl->render_inputs_bitset); -#endif /* to be enabled */ -} - - -static GLuint reduced_prim[] = { - GL_POINTS, - GL_LINES, - GL_LINES, - GL_LINES, - GL_TRIANGLES, - GL_TRIANGLES, - GL_TRIANGLES, - GL_TRIANGLES, - GL_TRIANGLES, - GL_TRIANGLES, -}; - -static void r600RasterPrimitive( GLcontext *ctx, GLuint prim ); -static void r600RenderPrimitive( GLcontext *ctx, GLenum prim ); - -/*********************************************************************** - * Emit primitives as inline vertices * - ***********************************************************************/ - - -#define HAVE_POINTS 1 -#define HAVE_LINES 1 -#define HAVE_LINE_STRIPS 1 -#define HAVE_TRIANGLES 1 -#define HAVE_TRI_STRIPS 1 -#define HAVE_TRI_STRIP_1 0 -#define HAVE_TRI_FANS 1 -#define HAVE_QUADS 0 -#define HAVE_QUAD_STRIPS 0 -#define HAVE_POLYGONS 1 -#define HAVE_ELTS 1 - -#undef LOCAL_VARS -#undef ALLOC_VERTS -#define CTX_ARG r600ContextPtr rmesa -#define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size -#define ALLOC_VERTS( n, size ) rcommonAllocDmaLowVerts( &rmesa->radeon, n, size * 4 ) -#define LOCAL_VARS \ - r600ContextPtr rmesa = R600_CONTEXT(ctx); \ - const char *r600verts = (char *)rmesa->radeon.swtcl.verts; -#define VERT(x) (r600Vertex *)(r600verts + ((x) * vertsize * sizeof(int))) -#define VERTEX r600Vertex -#undef TAG -#define TAG(x) r600_##x -#include "tnl_dd/t_dd_triemit.h" - - - -/*********************************************************************** - * Macros for t_dd_tritmp.h to draw basic primitives * - ***********************************************************************/ - -#define QUAD( a, b, c, d ) r600_quad( rmesa, a, b, c, d ) -#define TRI( a, b, c ) r600_triangle( rmesa, a, b, c ) -#define LINE( a, b ) r600_line( rmesa, a, b ) -#define POINT( a ) r600_point( rmesa, a ) - -/*********************************************************************** - * Build render functions from dd templates * - ***********************************************************************/ - -#define R600_TWOSIDE_BIT 0x01 -#define R600_UNFILLED_BIT 0x02 -#define R600_MAX_TRIFUNC 0x04 - -static struct { - tnl_points_func points; - tnl_line_func line; - tnl_triangle_func triangle; - tnl_quad_func quad; -} rast_tab[R600_MAX_TRIFUNC]; - -#define DO_FALLBACK 0 -#define DO_UNFILLED (IND & R600_UNFILLED_BIT) -#define DO_TWOSIDE (IND & R600_TWOSIDE_BIT) -#define DO_FLAT 0 -#define DO_OFFSET 0 -#define DO_TRI 1 -#define DO_QUAD 1 -#define DO_LINE 1 -#define DO_POINTS 1 -#define DO_FULL_QUAD 1 - -#define HAVE_RGBA 1 -#define HAVE_SPEC 1 -#define HAVE_BACK_COLORS 0 -#define HAVE_HW_FLATSHADE 1 -#define TAB rast_tab - -#define DEPTH_SCALE 1.0 -#define UNFILLED_TRI unfilled_tri -#define UNFILLED_QUAD unfilled_quad -#define VERT_X(_v) _v->v.x -#define VERT_Y(_v) _v->v.y -#define VERT_Z(_v) _v->v.z -#define AREA_IS_CCW( a ) (a < 0) -#define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + (e*rmesa->radeon.swtcl.vertex_size*sizeof(int))) - -#define VERT_SET_RGBA( v, c ) \ -do { \ - r600_color_t *color = (r600_color_t *)&((v)->ui[coloroffset]); \ - UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]); \ - UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]); \ - UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]); \ - UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]); \ -} while (0) - -#define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset] - -#define VERT_SET_SPEC( v0, c ) \ -do { \ - if (specoffset) { \ - UNCLAMPED_FLOAT_TO_UBYTE(v0->v.specular.red, (c)[0]); \ - UNCLAMPED_FLOAT_TO_UBYTE(v0->v.specular.green, (c)[1]); \ - UNCLAMPED_FLOAT_TO_UBYTE(v0->v.specular.blue, (c)[2]); \ - } \ -} while (0) - -#define VERT_COPY_SPEC( v0, v1 ) \ -do { \ - if (specoffset) { \ - v0->v.specular.red = v1->v.specular.red; \ - v0->v.specular.green = v1->v.specular.green; \ - v0->v.specular.blue = v1->v.specular.blue; \ - } \ -} while (0) - -#define VERT_SAVE_RGBA( idx ) color[idx] = v[idx]->ui[coloroffset] -#define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx] -#define VERT_SAVE_SPEC( idx ) if (specoffset) spec[idx] = v[idx]->ui[specoffset] -#define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx] - -#undef LOCAL_VARS -#undef TAG -#undef INIT - -#define LOCAL_VARS(n) \ - r600ContextPtr rmesa = R600_CONTEXT(ctx); \ - GLuint color[n] = { 0, }, spec[n] = { 0, }; \ - GLuint coloroffset = rmesa->swtcl.coloroffset; \ - GLuint specoffset = rmesa->swtcl.specoffset; \ - (void) color; (void) spec; (void) coloroffset; (void) specoffset; - -/*********************************************************************** - * Helpers for rendering unfilled primitives * - ***********************************************************************/ - -#define RASTERIZE(x) r600RasterPrimitive( ctx, reduced_prim[x] ) -#define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive -#undef TAG -#define TAG(x) x -#include "tnl_dd/t_dd_unfilled.h" -#undef IND - - -/*********************************************************************** - * Generate GL render functions * - ***********************************************************************/ - - -#define IND (0) -#define TAG(x) x -#include "tnl_dd/t_dd_tritmp.h" - -#define IND (R600_TWOSIDE_BIT) -#define TAG(x) x##_twoside -#include "tnl_dd/t_dd_tritmp.h" - -#define IND (R600_UNFILLED_BIT) -#define TAG(x) x##_unfilled -#include "tnl_dd/t_dd_tritmp.h" - -#define IND (R600_TWOSIDE_BIT|R600_UNFILLED_BIT) -#define TAG(x) x##_twoside_unfilled -#include "tnl_dd/t_dd_tritmp.h" - - - -static void init_rast_tab( void ) -{ - init(); - init_twoside(); - init_unfilled(); - init_twoside_unfilled(); -} - -/**********************************************************************/ -/* Render unclipped begin/end objects */ -/**********************************************************************/ - -#define RENDER_POINTS( start, count ) \ - for ( ; start < count ; start++) \ - r600_point( rmesa, VERT(start) ) -#define RENDER_LINE( v0, v1 ) \ - r600_line( rmesa, VERT(v0), VERT(v1) ) -#define RENDER_TRI( v0, v1, v2 ) \ - r600_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) ) -#define RENDER_QUAD( v0, v1, v2, v3 ) \ - r600_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) ) -#define INIT(x) do { \ - r600RenderPrimitive( ctx, x ); \ -} while (0) -#undef LOCAL_VARS -#define LOCAL_VARS \ - r600ContextPtr rmesa = R600_CONTEXT(ctx); \ - const GLuint vertsize = rmesa->radeon.swtcl.vertex_size; \ - const char *r600verts = (char *)rmesa->radeon.swtcl.verts; \ - const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \ - const GLboolean stipple = ctx->Line.StippleFlag; \ - (void) elt; (void) stipple; -#define RESET_STIPPLE //if ( stipple ) r200ResetLineStipple( ctx ); -#define RESET_OCCLUSION -#define PRESERVE_VB_DEFS -#define ELT(x) (x) -#define TAG(x) r600_##x##_verts -#include "tnl/t_vb_rendertmp.h" -#undef ELT -#undef TAG -#define TAG(x) r600_##x##_elts -#define ELT(x) elt[x] -#include "tnl/t_vb_rendertmp.h" - - - - -/**********************************************************************/ -/* Choose render functions */ -/**********************************************************************/ -static void r600ChooseRenderState( GLcontext *ctx ) -{ - TNLcontext *tnl = TNL_CONTEXT(ctx); - r600ContextPtr rmesa = R600_CONTEXT(ctx); - GLuint index = 0; - GLuint flags = ctx->_TriangleCaps; - - if (flags & DD_TRI_LIGHT_TWOSIDE) index |= R600_TWOSIDE_BIT; - if (flags & DD_TRI_UNFILLED) index |= R600_UNFILLED_BIT; - - if (index != rmesa->radeon.swtcl.RenderIndex) { - tnl->Driver.Render.Points = rast_tab[index].points; - tnl->Driver.Render.Line = rast_tab[index].line; - tnl->Driver.Render.ClippedLine = rast_tab[index].line; - tnl->Driver.Render.Triangle = rast_tab[index].triangle; - tnl->Driver.Render.Quad = rast_tab[index].quad; - - if (index == 0) { - tnl->Driver.Render.PrimTabVerts = r600_render_tab_verts; - tnl->Driver.Render.PrimTabElts = r600_render_tab_elts; - tnl->Driver.Render.ClippedPolygon = r600_fast_clipped_poly; - } else { - tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts; - tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts; - tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon; - } - - rmesa->radeon.swtcl.RenderIndex = index; - } -} - - -static void r600RenderStart(GLcontext *ctx) -{ -#if 0 /* to be enabled */ - r600ContextPtr rmesa = R600_CONTEXT( ctx ); - - r600ChooseRenderState(ctx); - r600SetVertexFormat(ctx); - - r600ValidateBuffers(ctx); - - r600UpdateShaders(rmesa); - r600UpdateShaderStates(rmesa); - - r600EmitCacheFlush(rmesa); - - /* investigate if we can put back flush optimisation if needed */ - if (rmesa->radeon.dma.flush != NULL) { - rmesa->radeon.dma.flush(ctx); - } -#endif /* to be enabled */ -} - -static void r600RenderFinish(GLcontext *ctx) -{ -} - -static void r600RasterPrimitive( GLcontext *ctx, GLuint hwprim ) -{ -#if 0 /* to be enabled */ - r600ContextPtr rmesa = R600_CONTEXT(ctx); - - if (rmesa->radeon.swtcl.hw_primitive != hwprim) { - R600_NEWPRIM( rmesa ); - rmesa->radeon.swtcl.hw_primitive = hwprim; - } -#endif /* to be enabled */ -} - -static void r600RenderPrimitive(GLcontext *ctx, GLenum prim) -{ - - r600ContextPtr rmesa = R600_CONTEXT(ctx); - rmesa->radeon.swtcl.render_primitive = prim; - - if ((prim == GL_TRIANGLES) && (ctx->_TriangleCaps & DD_TRI_UNFILLED)) - return; - - r600RasterPrimitive( ctx, reduced_prim[prim] ); -} - -static void r600ResetLineStipple(GLcontext *ctx) -{ -} - -void r600InitSwtcl(GLcontext *ctx) -{ - TNLcontext *tnl = TNL_CONTEXT(ctx); - r600ContextPtr rmesa = R600_CONTEXT(ctx); - static int firsttime = 1; - - if (firsttime) { - init_rast_tab(); - firsttime = 0; - } - - tnl->Driver.Render.Start = r600RenderStart; - tnl->Driver.Render.Finish = r600RenderFinish; - tnl->Driver.Render.PrimitiveNotify = r600RenderPrimitive; - tnl->Driver.Render.ResetLineStipple = r600ResetLineStipple; - tnl->Driver.Render.BuildVertices = _tnl_build_vertices; - tnl->Driver.Render.CopyPV = _tnl_copy_pv; - tnl->Driver.Render.Interp = _tnl_interp; - - /* FIXME: what are these numbers? */ - _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12, - 48 * sizeof(GLfloat) ); - - rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf; - rmesa->radeon.swtcl.RenderIndex = ~0; - rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES; - rmesa->radeon.swtcl.hw_primitive = 0; - - _tnl_invalidate_vertex_state( ctx, ~0 ); - _tnl_invalidate_vertices( ctx, ~0 ); - - _tnl_need_projected_coords( ctx, GL_FALSE ); - r600ChooseRenderState(ctx); -} - -void r600DestroySwtcl(GLcontext *ctx) -{ -} - -static void r600EmitVertexAOS(r600ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset) -{ -#if 0 /* to be enabled */ - BATCH_LOCALS(&rmesa->radeon); - - if (RADEON_DEBUG & DEBUG_VERTS) - fprintf(stderr, "%s: vertex_size %d, offset 0x%x \n", - __FUNCTION__, vertex_size, offset); - - BEGIN_BATCH(7); - OUT_BATCH_PACKET3(R600_PACKET3_3D_LOAD_VBPNTR, 2); - R600_OUT_BATCH(1); - R600_OUT_BATCH(vertex_size | (vertex_size << 8)); - OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0); - END_BATCH(); -#endif /* to be enabled */ -} - -static void r600EmitVbufPrim(r600ContextPtr rmesa, GLuint primitive, GLuint vertex_nr) -{ -#if 0 /* to be enabled */ - BATCH_LOCALS(&rmesa->radeon); - int type, num_verts; - - type = r600PrimitiveType(rmesa, primitive); - num_verts = r600NumVerts(rmesa, vertex_nr, primitive); - - BEGIN_BATCH(3); - OUT_BATCH_PACKET3(R600_PACKET3_3D_DRAW_VBUF_2, 0); - R600_OUT_BATCH(R600_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type); - END_BATCH(); -#endif /* to be enabled */ -} - -void r600_swtcl_flush(GLcontext *ctx, uint32_t current_offset) -{ -#if 0 /* to be enabled */ - r600ContextPtr rmesa = R600_CONTEXT(ctx); - - rcommonEnsureCmdBufSpace(&rmesa->radeon, - rmesa->radeon.hw.max_state_size + (12*sizeof(int)), - __FUNCTION__); - radeonEmitState(&rmesa->radeon); - r600EmitVertexAOS(rmesa, - rmesa->radeon.swtcl.vertex_size, - rmesa->radeon.dma.current, - current_offset); - - r600EmitVbufPrim(rmesa, - rmesa->radeon.swtcl.hw_primitive, - rmesa->radeon.swtcl.numverts); - r600EmitCacheFlush(rmesa); - COMMIT_BATCH(); -#endif /* to be enabled */ -} diff --git a/src/mesa/drivers/dri/r600/r600_swtcl.h b/src/mesa/drivers/dri/r600/r600_swtcl.h deleted file mode 100644 index bc0fdaf830..0000000000 --- a/src/mesa/drivers/dri/r600/r600_swtcl.h +++ /dev/null @@ -1,62 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - -/* - * Authors: - * Keith Whitwell - original r200 code - * Dave Airlie - */ - -#ifndef __R600_SWTCL_H__ -#define __R600_SWTCL_H__ - -#include "main/mtypes.h" -#include "swrast/swrast.h" -#include "r600_context.h" - -#define MASK_XYZW (R600_WRITE_ENA_X | R600_WRITE_ENA_Y | R600_WRITE_ENA_Z | R600_WRITE_ENA_W) -#define MASK_X R600_WRITE_ENA_X -#define MASK_Y R600_WRITE_ENA_Y -#define MASK_Z R600_WRITE_ENA_Z -#define MASK_W R600_WRITE_ENA_W - -/* - * Here are definitions of OVM locations of vertex attributes for non TCL hw - */ -#define SWTCL_OVM_POS 0 -#define SWTCL_OVM_COLOR0 2 -#define SWTCL_OVM_COLOR1 3 -#define SWTCL_OVM_TEX(n) ((n) + 6) -#define SWTCL_OVM_POINT_SIZE 15 - - -extern void r600InitSwtcl( GLcontext *ctx ); -extern void r600DestroySwtcl( GLcontext *ctx ); - -extern void r600_swtcl_flush(GLcontext *ctx, uint32_t current_offset); -#endif diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 35f30605ce..78b92d695e 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -354,11 +354,12 @@ static GLboolean r700RunRender(GLcontext * ctx, //richard test /* test stamp, write a number to mmSCRATCH4 */ +#if 0 BEGIN_BATCH_NO_AUTOSTATE(3); R600_OUT_BATCH_REGVAL((0x2144 << 2), 0x56785678); END_BATCH(); COMMIT_BATCH(); - +#endif #endif //0 rcommonFlushCmdBuf( &context->radeon, __FUNCTION__ ); -- cgit v1.2.3 From e6eb0ce6ef61e16c5d986b370a13c7b62364ad4e Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 29 May 2009 14:45:07 -0400 Subject: more cleanup --- src/mesa/drivers/dri/r600/r700_chip.c | 73 ++++++++------------------------- src/mesa/drivers/dri/r600/r700_chip.h | 4 +- src/mesa/drivers/dri/r600/r700_ioctl.c | 4 +- src/mesa/drivers/dri/r600/r700_render.c | 2 +- 4 files changed, 21 insertions(+), 62 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 5cd0d72d6e..3db03578ed 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -53,16 +53,6 @@ static GLboolean r700DestroyChipObj(GLcontext * ctx) r700 = (R700_CHIP_CONTEXT *)(context->chipobj.pvChipObj); - if(0 != r700->pbo_vs_clear) - { - r600DeleteShader(context, r700->pbo_vs_clear); - } - - if(0 != r700->pbo_fs_clear) - { - r600DeleteShader(context, r700->pbo_fs_clear); - } - FREE(r700->pStateList); FREE(r700); @@ -512,8 +502,7 @@ inline GLboolean needRelocReg(context_t *context, unsigned int reg) return GL_FALSE; } -inline GLboolean setRelocReg(context_t *context, unsigned int reg, - GLboolean bUseStockShader) +inline GLboolean setRelocReg(context_t *context, unsigned int reg) { BATCH_LOCALS(&context->radeon); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -573,63 +562,35 @@ inline GLboolean setRelocReg(context_t *context, unsigned int reg, return GL_TRUE; } break; - case mmSQ_PGM_START_VS: - { - if(GL_TRUE == bUseStockShader) - { - if(NULL != r700->pbo_vs_clear) - { - pbo = (struct radeon_bo *)(r700->pbo_vs_clear); - } - else - { - return GL_FALSE; - } - } - else - { - pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); - } + case mmSQ_PGM_START_VS: + { + pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); offset_mod.shift = NO_SHIFT; offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; + offset_mod.mask = 0xFFFFFFFF; - R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_VS.u32All, - pbo, + R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_VS.u32All, + pbo, r700->SQ_PGM_START_VS.u32All, RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); return GL_TRUE; } break; - case mmSQ_PGM_START_FS: - case mmSQ_PGM_START_ES: - case mmSQ_PGM_START_GS: - case mmSQ_PGM_START_PS: + case mmSQ_PGM_START_FS: + case mmSQ_PGM_START_ES: + case mmSQ_PGM_START_GS: + case mmSQ_PGM_START_PS: { - if(GL_TRUE == bUseStockShader) - { - if(NULL != r700->pbo_fs_clear) - { - pbo = (struct radeon_bo *)(r700->pbo_fs_clear); - } - else - { - return GL_FALSE; - } - } - else - { - pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context)); - } + pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context)); offset_mod.shift = NO_SHIFT; offset_mod.shiftbits = 0; offset_mod.mask = 0xFFFFFFFF; voffset = 0; - R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_PS.u32All, - pbo, + R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_PS.u32All, + pbo, r700->SQ_PGM_START_PS.u32All, RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); return GL_TRUE; @@ -640,7 +601,7 @@ inline GLboolean setRelocReg(context_t *context, unsigned int reg, return GL_FALSE; } -GLboolean r700SendContextStates(context_t *context, GLboolean bUseStockShader) +GLboolean r700SendContextStates(context_t *context) { BATCH_LOCALS(&context->radeon); @@ -676,11 +637,11 @@ GLboolean r700SendContextStates(context_t *context, GLboolean bUseStockShader) pState = pState->pNext; - BEGIN_BATCH_NO_AUTOSTATE(toSend + 2); + BEGIN_BATCH_NO_AUTOSTATE(toSend + 2); R600_OUT_BATCH_REGSEQ(((pInit->unOffset + ASIC_CONTEXT_BASE_INDEX)<<2), toSend); for(ui=0; uiunOffset, bUseStockShader) ) + if( GL_FALSE == setRelocReg(context, pInit->unOffset) ) { /* for not reloc reg. */ R600_OUT_BATCH(*(pInit->puiValue)); diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h index c8d9cbfbda..88b5075479 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.h +++ b/src/mesa/drivers/dri/r600/r700_chip.h @@ -447,8 +447,6 @@ typedef struct _R700_CHIP_CONTEXT R700_TEXTURE_STATES texture_states; - void * pbo_vs_clear; - void * pbo_fs_clear; GLboolean bEnablePerspective; } R700_CHIP_CONTEXT; @@ -456,7 +454,7 @@ typedef struct _R700_CHIP_CONTEXT #define R700_CONTEXT_STATES(context) ((R700_CHIP_CONTEXT *)(context->chipobj.pvChipObj)) extern GLboolean r700InitChipObject(context_t *context); -extern GLboolean r700SendContextStates(context_t *context, GLboolean bUseStockShader); +extern GLboolean r700SendContextStates(context_t *context); extern int r700SetupStreams(GLcontext * ctx); extern void r700SetupVTXConstants(GLcontext * ctx, unsigned int nStreamID, diff --git a/src/mesa/drivers/dri/r600/r700_ioctl.c b/src/mesa/drivers/dri/r600/r700_ioctl.c index 1ab3ee7de5..f8c3359a47 100644 --- a/src/mesa/drivers/dri/r600/r700_ioctl.c +++ b/src/mesa/drivers/dri/r600/r700_ioctl.c @@ -60,8 +60,8 @@ static void r700Flush(GLcontext *ctx) if (radeon->dma.flush) radeon->dma.flush( ctx ); - r700SendContextStates(context, GL_FALSE); - + r700SendContextStates(context); + if (radeon->cmdbuf.cs->cdw) rcommonFlushCmdBuf(radeon, __FUNCTION__); } diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 78b92d695e..1f0604da5d 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -294,7 +294,7 @@ static GLboolean r700RunRender(GLcontext * ctx, /* flush vtx */ //r700SyncSurf(context); /* */ - r700SendContextStates(context, GL_FALSE); + r700SendContextStates(context); /* richard test code */ for (i = 0; i < vb->PrimitiveCount; i++) -- cgit v1.2.3 From 5a8b67f3638485fc1536ab7d2cfeccc854b5e8fc Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 29 May 2009 14:55:12 -0400 Subject: more cleanup --- src/mesa/drivers/dri/r600/r600_context.c | 3 ++- src/mesa/drivers/dri/r600/r600_context.h | 1 - src/mesa/drivers/dri/r600/r700_chip.c | 4 ---- src/mesa/drivers/dri/r600/r700_render.c | 2 +- 4 files changed, 3 insertions(+), 7 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 9b057ad1b5..bd537160f1 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -92,6 +92,7 @@ int hw_tcl_on = 1; #include "extension_helper.h" +extern const struct tnl_pipeline_stage *r700_pipeline[]; const struct dri_extension card_extensions[] = { /* *INDENT-OFF* */ @@ -310,7 +311,7 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, /* Install the customized pipeline: */ _tnl_destroy_pipeline(ctx); - _tnl_install_pipeline(ctx, (const struct tnl_pipeline_stage **)(r600->chipobj.stages)); + _tnl_install_pipeline(ctx, r700_pipeline); /* Try and keep materials and vertices separate: */ diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index 6f41bbcbbc..8bfcb7b4e0 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -140,7 +140,6 @@ typedef struct chip_object GLuint (*GetTexObjSize)(void); - struct tnl_pipeline_stage **stages; } chip_object; /** diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 3db03578ed..3ceb2794b0 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -39,8 +39,6 @@ #include "r700_vertprog.h" #include "r700_ioctl.h" -extern const struct tnl_pipeline_stage *r700_pipeline[]; - static GLboolean r700DestroyChipObj(GLcontext * ctx) { context_t * context = R700_CONTEXT(ctx); @@ -89,8 +87,6 @@ GLboolean r700InitChipObject(context_t *context) context->chipobj.GetTexObjSize = r700GetTexObjSize; - context->chipobj.stages = r700_pipeline; - context->chipobj.InitFuncs = r700InitFuncs; context->chipobj.InitState = r700InitState; diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 1f0604da5d..ded5f51a6a 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -195,7 +195,7 @@ GLboolean r700SyncSurf(context_t *context) unsigned int r700PrimitiveType(int prim) { - switch (prim & PRIM_MODE_MASK) + switch (prim & PRIM_MODE_MASK) { case GL_POINTS: return DI_PT_POINTLIST; -- cgit v1.2.3 From d8694cd3f69dfc40509544293aa35f297571e878 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 29 May 2009 15:37:04 -0400 Subject: get rid of chip_object struct --- src/mesa/drivers/dri/r600/r600_context.c | 6 +----- src/mesa/drivers/dri/r600/r600_context.h | 30 ++++++++++++++++-------------- src/mesa/drivers/dri/r600/r700_assembler.c | 1 - src/mesa/drivers/dri/r600/r700_chip.c | 26 +------------------------- src/mesa/drivers/dri/r600/r700_chip.h | 12 ------------ src/mesa/drivers/dri/r600/r700_clear.c | 1 - src/mesa/drivers/dri/r600/r700_fragprog.c | 3 +-- src/mesa/drivers/dri/r600/r700_ioctl.c | 1 - src/mesa/drivers/dri/r600/r700_oglprog.c | 1 - src/mesa/drivers/dri/r600/r700_render.c | 7 +++---- src/mesa/drivers/dri/r600/r700_shader.c | 1 - src/mesa/drivers/dri/r600/r700_state.c | 20 +++++++------------- src/mesa/drivers/dri/r600/r700_tex.c | 1 - src/mesa/drivers/dri/r600/r700_vertprog.c | 3 +-- 14 files changed, 30 insertions(+), 83 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index c54dae0c53..526d02ed57 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -63,7 +63,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r600_emit.h" #include "radeon_bocs_wrapper.h" -#include "r700_chip.h" #include "r700_state.h" #include "r700_ioctl.h" @@ -369,9 +368,6 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc"); } - r600->disable_lowimpact_fallback = - driQueryOptionb(&r600->radeon.optionCache, - "disable_lowimpact_fallback"); radeon_fbo_init(&r600->radeon); radeonInitSpanFuncs( ctx ); @@ -410,7 +406,7 @@ r600DestroyContext (__DRIcontextPrivate * driContextPriv) context_t *context = ctx ? R700_CONTEXT(ctx) : NULL; if (context) - (context->chipobj.DestroyChipObj)(context->chipobj.pvChipObj); + FREE(context->hw.pStateList); } diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index 321b05d930..52512aacc0 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -48,6 +48,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/mtypes.h" #include "main/colormac.h" +#include "r700_chip.h" + struct r600_context; typedef struct r600_context context_t; @@ -127,32 +129,20 @@ typedef struct offset_modifiers GLuint mask; } offset_modifiers; -typedef struct chip_object -{ - void *pvChipObj; - - /* ------------ OUT ------------------- */ - GLboolean (*DestroyChipObj)(GLcontext * ctx); - -} chip_object; - /** * \brief R600 context structure. */ struct r600_context { struct radeon_context radeon; /* parent class, must be first */ - /* ------ */ - chip_object chipobj; + /* ------ */ + R700_CHIP_CONTEXT hw; /* Vertex buffers */ GLvector4f dummy_attrib[_TNL_ATTRIB_MAX]; GLvector4f *temp_attrib[_TNL_ATTRIB_MAX]; - GLboolean disable_lowimpact_fallback; - - GLboolean vap_flush_needed; }; #define R700_CONTEXT(ctx) ((context_t *)(ctx->DriverCtx)) @@ -163,6 +153,18 @@ extern GLboolean r600CreateContext(const __GLcontextModes * glVisual, __DRIcontextPrivate * driContextPriv, void *sharedContextPrivate); +#define R700_CONTEXT_STATES(context) ((R700_CHIP_CONTEXT *)(&context->hw)) + +extern GLboolean r700InitChipObject(context_t *context); +extern GLboolean r700SendContextStates(context_t *context); +extern int r700SetupStreams(GLcontext * ctx); +extern void r700SetupVTXConstants(GLcontext * ctx, + unsigned int nStreamID, + void * pAos, + unsigned int size, /* number of elements in vector */ + unsigned int stride, + unsigned int Count); /* number of vectors in stream */ + #define RADEON_D_CAPTURE 0 #define RADEON_D_PLAYBACK 1 #define RADEON_D_PLAYBACK_RAW 2 diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 1610020ee8..a564d6f099 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -34,7 +34,6 @@ #include "main/imports.h" #include "r600_context.h" -#include "r700_chip.h" #include "r700_debug.h" #include "r700_assembler.h" diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 9b30249231..5ae70c99c7 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -31,7 +31,6 @@ #include "r600_context.h" #include "r600_cmdbuf.h" -#include "r700_chip.h" #include "r700_state.h" #include "r700_tex.h" #include "r700_oglprog.h" @@ -39,25 +38,6 @@ #include "r700_vertprog.h" #include "r700_ioctl.h" -static GLboolean r700DestroyChipObj(GLcontext * ctx) -{ - context_t * context = R700_CONTEXT(ctx); - R700_CHIP_CONTEXT *r700; - - if(NULL == context->chipobj.pvChipObj) - { - return GL_TRUE; - } - - r700 = (R700_CHIP_CONTEXT *)(context->chipobj.pvChipObj); - - FREE(r700->pStateList); - - FREE(r700); - - return GL_TRUE; -} - #define LINK_STATES(reg) \ do \ { \ @@ -71,11 +51,7 @@ GLboolean r700InitChipObject(context_t *context) { ContextState * pStateListWork; - R700_CHIP_CONTEXT *r700 = CALLOC( sizeof(R700_CHIP_CONTEXT) ); - - context->chipobj.pvChipObj = (void*)r700; - - context->chipobj.DestroyChipObj = r700DestroyChipObj; + R700_CHIP_CONTEXT *r700 = &context->hw; /* init state list */ r700->pStateList = (ContextState*) MALLOC (sizeof(ContextState)*sizeof(R700_CHIP_CONTEXT)/sizeof(unsigned int)); diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h index 88b5075479..918cb222d4 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.h +++ b/src/mesa/drivers/dri/r600/r700_chip.h @@ -451,17 +451,5 @@ typedef struct _R700_CHIP_CONTEXT } R700_CHIP_CONTEXT; -#define R700_CONTEXT_STATES(context) ((R700_CHIP_CONTEXT *)(context->chipobj.pvChipObj)) - -extern GLboolean r700InitChipObject(context_t *context); -extern GLboolean r700SendContextStates(context_t *context); -extern int r700SetupStreams(GLcontext * ctx); -extern void r700SetupVTXConstants(GLcontext * ctx, - unsigned int nStreamID, - void * pAos, - unsigned int size, /* number of elements in vector */ - unsigned int stride, - unsigned int Count); /* number of vectors in stream */ - #endif /* _R700_CHIP_H_ */ diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c index e610514e01..e1164a09d7 100644 --- a/src/mesa/drivers/dri/r600/r700_clear.c +++ b/src/mesa/drivers/dri/r600/r700_clear.c @@ -33,7 +33,6 @@ #include "main/enums.h" #include "r600_context.h" -#include "r700_chip.h" #include "r700_shaderinst.h" #include "r600_emit.h" diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index c46094dcd7..cebb82d853 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -38,7 +38,6 @@ #include "r600_context.h" #include "r600_cmdbuf.h" -#include "r700_chip.h" #include "r700_fragprog.h" #include "r700_debug.h" @@ -259,7 +258,7 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) context_t *context = R700_CONTEXT(ctx); BATCH_LOCALS(&context->radeon); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); struct r700_fragment_program *fp = (struct r700_fragment_program *) (ctx->FragmentProgram._Current); diff --git a/src/mesa/drivers/dri/r600/r700_ioctl.c b/src/mesa/drivers/dri/r600/r700_ioctl.c index f8c3359a47..c479532001 100644 --- a/src/mesa/drivers/dri/r600/r700_ioctl.c +++ b/src/mesa/drivers/dri/r600/r700_ioctl.c @@ -37,7 +37,6 @@ #include "radeon_lock.h" #include "r600_context.h" -#include "r700_chip.h" #include "r700_ioctl.h" #include "r700_clear.h" diff --git a/src/mesa/drivers/dri/r600/r700_oglprog.c b/src/mesa/drivers/dri/r600/r700_oglprog.c index ba49367dc4..36de143b1a 100644 --- a/src/mesa/drivers/dri/r600/r700_oglprog.c +++ b/src/mesa/drivers/dri/r600/r700_oglprog.c @@ -34,7 +34,6 @@ #include "r600_context.h" -#include "r700_chip.h" #include "r700_oglprog.h" #include "r700_fragprog.h" #include "r700_vertprog.h" diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index ded5f51a6a..cc90e8dfb7 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -47,7 +47,6 @@ #include "r600_context.h" #include "r600_cmdbuf.h" -#include "r700_chip.h" #include "r700_tex.h" #include "r700_vertprog.h" @@ -109,7 +108,7 @@ static GLboolean r700SetupShaders(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); GLuint exportCount; @@ -133,7 +132,7 @@ GLboolean r700SendTextureState(context_t *context) { unsigned int i; - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); #if 0 /* to be enabled */ for(i=0; ichipobj.pvChipObj); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); #if 1 BATCH_LOCALS(&context->radeon); diff --git a/src/mesa/drivers/dri/r600/r700_shader.c b/src/mesa/drivers/dri/r600/r700_shader.c index 446f9f959b..b4fd51c137 100644 --- a/src/mesa/drivers/dri/r600/r700_shader.c +++ b/src/mesa/drivers/dri/r600/r700_shader.c @@ -35,7 +35,6 @@ #include "main/glheader.h" #include "r600_context.h" -#include "r700_chip.h" #include "r700_debug.h" #include "r700_shader.h" diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index e3e78df16c..768e184623 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -49,7 +49,6 @@ #include "r600_context.h" -#include "r700_chip.h" #include "r700_state.h" #include "r700_fragprog.h" @@ -190,7 +189,7 @@ static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //----------- { context_t *context = R700_CONTEXT(ctx); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); _swrast_InvalidateState(ctx, new_state); _swsetup_InvalidateState(ctx, new_state); @@ -239,7 +238,7 @@ static void r700SetDepthState(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); if (ctx->Depth.Test) { @@ -322,7 +321,7 @@ static void r700BlendFuncSeparate(GLcontext * ctx, static void r700UpdateCulling(GLcontext * ctx) { - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(R700_CONTEXT(ctx)->chipobj.pvChipObj); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw); CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit); @@ -490,7 +489,7 @@ static void r700Viewport(GLcontext * ctx, { context_t *context = R700_CONTEXT(ctx); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); __DRIdrawablePrivate *dPriv = context->radeon.dri.drawable; @@ -524,12 +523,7 @@ static void r700Viewport(GLcontext * ctx, tz = v[MAT_TZ] * scale; /* TODO : Need DMA flush as well. */ -#if 0 /* to be enabled */ - if(context->cmdbuf.count_used > 0) - { - (context->chipobj.FlushCmdBuffer)(context); - } -#endif /* to be enabled */ + r700->PA_CL_VPORT_XSCALE.u32All = *((unsigned int*)(&sx)); r700->PA_CL_VPORT_XOFFSET.u32All = *((unsigned int*)(&tx)); @@ -591,7 +585,7 @@ static void r700Scissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h) void r700SetRenderTarget(context_t *context) { - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); struct radeon_renderbuffer *rrb; unsigned int nPitchInPixel; @@ -774,7 +768,7 @@ void r700InitState(GLcontext * ctx) //------------------- { context_t *context = R700_CONTEXT(ctx); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); /* Turn off vgt reuse */ r700->VGT_REUSE_OFF.u32All = 0; diff --git a/src/mesa/drivers/dri/r600/r700_tex.c b/src/mesa/drivers/dri/r600/r700_tex.c index e2de8faf77..21c9379729 100644 --- a/src/mesa/drivers/dri/r600/r700_tex.c +++ b/src/mesa/drivers/dri/r600/r700_tex.c @@ -40,7 +40,6 @@ #include "radeon_common.h" #include "r600_context.h" -#include "r700_chip.h" #include "r700_state.h" diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index 2861918c42..a827de197b 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -41,7 +41,6 @@ #include "r600_context.h" #include "r600_cmdbuf.h" -#include "r700_chip.h" #include "r700_debug.h" #include "r700_vertprog.h" @@ -339,7 +338,7 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) BATCH_LOCALS(&context->radeon); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); struct r700_vertex_program *vp = (struct r700_vertex_program *)ctx->VertexProgram._Current; -- cgit v1.2.3 From f5d479d7f50abf5d88a388ee80af3222c8bb7e6f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 3 Jun 2009 14:19:26 -0400 Subject: Clean up scissor and viewport code Switch to common functions where applicable --- src/mesa/drivers/dri/r600/r700_render.c | 2 + src/mesa/drivers/dri/r600/r700_state.c | 335 +++++++++++++++++--------------- 2 files changed, 176 insertions(+), 161 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index cc90e8dfb7..3a4328fdfe 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -258,7 +258,9 @@ static GLboolean r700RunRender(GLcontext * ctx, r700UpdateShaders(ctx); + r700SetScissor(context); r700SetRenderTarget(context); + r700SetDepthTarget(context); if(r700SetupStreams(ctx)) { diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index d1f77ef6ef..ca1c84f5dc 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -113,6 +113,9 @@ void r700UpdateShaders (GLcontext * ctx) //---------------------------------- */ void r700UpdateViewportOffset(GLcontext * ctx) //------------------ { + + //radeonUpdateScissor(ctx); + return; } @@ -481,62 +484,61 @@ static void r700StencilOpSeparate(GLcontext * ctx, GLenum face, { } -static void r700Viewport(GLcontext * ctx, - GLint x, - GLint y, - GLsizei width, - GLsizei height) //-------------------- +static void r700UpdateWindow(GLcontext * ctx) //-------------------- { - context_t *context = R700_CONTEXT(ctx); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - - __DRIdrawablePrivate *dPriv = context->radeon.dri.drawable; - - GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; - GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + __DRIdrawablePrivate *dPriv = context->radeon.dri.drawable; + GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; + GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; + const GLfloat *v = ctx->Viewport._WindowMap.m; + const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF; + const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0); + GLfloat y_scale, y_bias; + + if (render_to_fbo) { + y_scale = 1.0; + y_bias = 0; + } else { + y_scale = -1.0; + y_bias = yoffset; + } - const GLfloat *v = ctx->Viewport._WindowMap.m; + GLfloat sx = v[MAT_SX]; + GLfloat tx = v[MAT_TX] + xoffset; + GLfloat sy = v[MAT_SY] * y_scale; + GLfloat ty = (v[MAT_TY] * y_scale) + y_bias; + GLfloat sz = v[MAT_SZ] * depthScale; + GLfloat tz = v[MAT_TZ] * depthScale; - GLfloat sx, tx, sy, ty, sz, tz; - GLfloat scale; + /* TODO : Need DMA flush as well. */ - switch (ctx->Visual.depthBits) - { - case 16: - scale = 1.0 / (GLfloat) 0xffff; - break; - case 24: - scale = 1.0 / (GLfloat) 0xffffff; - break; - default: - fprintf(stderr, "Error: Unsupported depth %d... exiting\n", - ctx->Visual.depthBits); - _mesa_exit(-1); - } + r700->PA_CL_VPORT_XSCALE.u32All = *((unsigned int*)(&sx)); + r700->PA_CL_VPORT_XOFFSET.u32All = *((unsigned int*)(&tx)); - sx = v[MAT_SX]; - tx = v[MAT_TX] + xoffset; - sy = -v[MAT_SY]; - ty = (-v[MAT_TY]) + yoffset; - sz = v[MAT_SZ] * scale; - tz = v[MAT_TZ] * scale; + r700->PA_CL_VPORT_YSCALE.u32All = *((unsigned int*)(&sy)); + r700->PA_CL_VPORT_YOFFSET.u32All = *((unsigned int*)(&ty)); - /* TODO : Need DMA flush as well. */ + r700->PA_CL_VPORT_ZSCALE.u32All = *((unsigned int*)(&sz)); + r700->PA_CL_VPORT_ZOFFSET.u32All = *((unsigned int*)(&tz)); +} - r700->PA_CL_VPORT_XSCALE.u32All = *((unsigned int*)(&sx)); - r700->PA_CL_VPORT_XOFFSET.u32All = *((unsigned int*)(&tx)); - r700->PA_CL_VPORT_YSCALE.u32All = *((unsigned int*)(&sy)); - r700->PA_CL_VPORT_YOFFSET.u32All = *((unsigned int*)(&ty)); +static void r700Viewport(GLcontext * ctx, + GLint x, + GLint y, + GLsizei width, + GLsizei height) //-------------------- +{ + r700UpdateWindow(ctx); - r700->PA_CL_VPORT_ZSCALE.u32All = *((unsigned int*)(&sz)); - r700->PA_CL_VPORT_ZOFFSET.u32All = *((unsigned int*)(&tz)); + radeon_viewport(ctx, x, y, width, height); } - static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //------------- { + r700UpdateWindow(ctx); } static void r700PointSize(GLcontext * ctx, GLfloat size) //------------------- @@ -564,23 +566,91 @@ static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) //- { } -static void r700Scissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h) //--------------- +void r700SetScissor(context_t *context) //--------------- { - if (ctx->Scissor.Enabled) - { - /* We don't pipeline cliprect changes */ - /* r700Flush(ctx); */ - - //__DRIdrawablePrivate *dPriv = radeon->dri.drawable; - //int x1 = dPriv->x + ctx->Scissor.X; - //int y1 = dPriv->y + dPriv->h - (ctx->Scissor.Y + ctx->Scissor.Height); - - //radeon->state.scissor.rect.x1 = x1; - //radeon->state.scissor.rect.y1 = y1; - //radeon->state.scissor.rect.x2 = x1 + ctx->Scissor.Width; - //radeon->state.scissor.rect.y2 = y1 + ctx->Scissor.Height; - /* radeonRecalcScissorRects(radeon); */ + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + unsigned x1, y1, x2, y2; + struct radeon_renderbuffer *rrb; + + rrb = radeon_get_colorbuffer(&context->radeon); + if (!rrb || !rrb->bo) { + fprintf(stderr, "no rrb\n"); + return; + } + if (context->radeon.state.scissor.enabled) { + x1 = context->radeon.state.scissor.rect.x1; + y1 = context->radeon.state.scissor.rect.y1; + x2 = context->radeon.state.scissor.rect.x2 - 1; + y2 = context->radeon.state.scissor.rect.y2 - 1; + } else { + x1 = 0; + y1 = 0; + x2 = rrb->width - 1; + y2 = rrb->height - 1; } + + /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */ + r700->PA_SC_CLIPRECT_RULE.u32All = 0x0000FFFF; + + /* window */ + SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit); + SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1, + PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask); + SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1, + PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask); + + SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2, + PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask); + SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2, + PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask); + + + SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1, + PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask); + SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1, + PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask); + SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2, + PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask); + SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2, + PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask); + + r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All; + r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All; + r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All; + r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All; + r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All; + r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All; + + /* more....2d clip */ + SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit); + SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1, + PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask); + SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1, + PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask); + SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2, + PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask); + SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2, + PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask); + + SETbit(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit); + SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, x1, + PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask); + SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, y1, + PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask); + SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, x2, + PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask); + SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, y2, + PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask); + + SETbit(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, WINDOW_OFFSET_DISABLE_bit); + SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, x1, + PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask); + SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, y1, + PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask); + SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, x2, + PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask); + SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, y2, + PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask); } void r700SetRenderTarget(context_t *context) @@ -594,95 +664,15 @@ void r700SetRenderTarget(context_t *context) SETfield(r700->CB_TARGET_MASK.u32All, 0xF, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask); SETfield(r700->CB_SHADER_MASK.u32All, 0xF, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask); - /* screen */ - r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0; - - SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->width, - PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask); - SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->height, - PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask); - - /* window */ - SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit); - SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, context->radeon.dri.drawable->x, - PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask); - SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, context->radeon.dri.drawable->y, - PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask); - - SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w, - PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask); - SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h, - PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask); - - /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */ - r700->PA_SC_CLIPRECT_RULE.u32All = 0x0000FFFF; - - SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, context->radeon.dri.drawable->x, - PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask); - SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, context->radeon.dri.drawable->y, - PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask); - SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w, - PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask); - SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h, - PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask); - - r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All; - r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All; - r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All; - r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All; - r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All; - r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All; - - /* edgerule for triangles, points, recs, lines */ - r700->PA_SC_EDGERULE.u32All = 0x555AA96A; - - /* more....2d clip */ - SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit); - SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, context->radeon.dri.drawable->x, - PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask); - SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, context->radeon.dri.drawable->y, - PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask); - SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w, - PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask); - SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h, - PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask); - - SETbit(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit); - SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, context->radeon.dri.drawable->x, - PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, context->radeon.dri.drawable->y, - PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w, - PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h, - PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask); - - SETbit(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, WINDOW_OFFSET_DISABLE_bit); - SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, context->radeon.dri.drawable->x, - PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, context->radeon.dri.drawable->y, - PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w, - PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h, - PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask); - - /* setup viewport */ - r700Viewport(GL_CONTEXT(context), - 0, - 0, - context->radeon.dri.drawable->w, - context->radeon.dri.drawable->h); - rrb = radeon_get_colorbuffer(&context->radeon); if (!rrb || !rrb->bo) { fprintf(stderr, "no rrb\n"); return; } - /* color buffer */ + /* color buffer */ r700->CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset; - + nPitchInPixel = rrb->pitch/rrb->cpp; SETfield(r700->CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1, PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); @@ -690,8 +680,8 @@ void r700SetRenderTarget(context_t *context) SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); r700->CB_COLOR0_BASE.u32All = 0; SETfield(r700->CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask); - SETfield(r700->CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL, - CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask); + SETfield(r700->CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL, + CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask); if(4 == rrb->cpp) { SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_8_8_8_8, @@ -702,14 +692,23 @@ void r700SetRenderTarget(context_t *context) { SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_5_6_5, CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask); - SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT_REV, - COMP_SWAP_shift, COMP_SWAP_mask); - } + SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT_REV, + COMP_SWAP_shift, COMP_SWAP_mask); + } SETbit(r700->CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit); SETbit(r700->CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit); SETfield(r700->CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask); - /* depth buf */ +} + +void r700SetDepthTarget(context_t *context) +{ + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + + struct radeon_renderbuffer *rrb; + unsigned int nPitchInPixel; + + /* depth buf */ r700->DB_DEPTH_SIZE.u32All = 0; r700->DB_DEPTH_BASE.u32All = 0; r700->DB_DEPTH_INFO.u32All = 0; @@ -719,8 +718,8 @@ void r700SetRenderTarget(context_t *context) r700->DB_DEPTH_VIEW.u32All = 0; r700->DB_RENDER_CONTROL.u32All = 0; r700->DB_RENDER_OVERRIDE.u32All = 0; - SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask); - SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask); + SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask); + SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask); SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask); rrb = radeon_get_depthbuffer(&context->radeon); @@ -734,14 +733,14 @@ void r700SetRenderTarget(context_t *context) SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1, SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */ - if(4 == rrb->cpp) + if(4 == rrb->cpp) { - switch (GL_CONTEXT(context)->Visual.depthBits) + switch (GL_CONTEXT(context)->Visual.depthBits) { - case 16: + case 16: case 24: - SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24, - DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask); + SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24, + DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask); break; default: fprintf(stderr, "Error: Unsupported depth %d... exiting\n", @@ -751,12 +750,12 @@ void r700SetRenderTarget(context_t *context) } else { - SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16, - DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask); - } - SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1, - DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask); - /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */ + SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16, + DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask); + } + SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1, + DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask); + /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */ } /** @@ -808,6 +807,16 @@ void r700InitState(GLcontext * ctx) //------------------- SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES, POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask); + /* screen */ + r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0; + + SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, + ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->width, + PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask); + SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, + ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->height, + PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask); + /* Do scale XY and Z by 1/W0. */ r700->bEnablePerspective = GL_TRUE; CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit); @@ -831,7 +840,7 @@ void r700InitState(GLcontext * ctx) //------------------- SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask); /* Set up line control */ - SETfield(r700->PA_SU_LINE_CNTL.u32All, 0x8, + SETfield(r700->PA_SU_LINE_CNTL.u32All, 0x8, PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask); r700->PA_SC_LINE_CNTL.u32All = 0; @@ -879,7 +888,7 @@ void r700InitState(GLcontext * ctx) //------------------- r700->SX_MISC.u32All = 0; /* depth buf */ - r700->DB_DEPTH_SIZE.u32All = 0; + r700->DB_DEPTH_SIZE.u32All = 0; r700->DB_DEPTH_BASE.u32All = 0; r700->DB_DEPTH_INFO.u32All = 0; r700->DB_DEPTH_CONTROL.u32All = 0; @@ -943,6 +952,10 @@ void r700InitStateFuncs(struct dd_function_table *functions) //----------------- functions->ClipPlane = r700ClipPlane; - functions->Scissor = r700Scissor; + functions->Scissor = radeonScissor; + + functions->DrawBuffer = radeonDrawBuffer; + functions->ReadBuffer = radeonReadBuffer; + } -- cgit v1.2.3 From 8c27d99eb84709013f420a7500ddfdef71ac7391 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 4 Jun 2009 20:22:14 -0400 Subject: re-arrange state structure - split out renderbuffers - split out shaders - split our viewports Only send the state needed. --- src/mesa/drivers/dri/r600/r700_chip.c | 646 ++++++++++++++---------------- src/mesa/drivers/dri/r600/r700_chip.h | 426 +++++++++----------- src/mesa/drivers/dri/r600/r700_fragprog.c | 10 +- src/mesa/drivers/dri/r600/r700_render.c | 21 +- src/mesa/drivers/dri/r600/r700_state.c | 117 +++--- src/mesa/drivers/dri/r600/r700_state.h | 2 +- src/mesa/drivers/dri/r600/r700_vertprog.c | 6 +- 7 files changed, 557 insertions(+), 671 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 5737847439..7fd557ca8e 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -57,122 +57,105 @@ GLboolean r700InitChipObject(context_t *context) r700->pStateList = (ContextState*) MALLOC (sizeof(ContextState)*sizeof(R700_CHIP_CONTEXT)/sizeof(unsigned int)); pStateListWork = r700->pStateList; - LINK_STATES(DB_DEPTH_SIZE); - LINK_STATES(DB_DEPTH_VIEW); - - LINK_STATES(DB_DEPTH_BASE); - LINK_STATES(DB_DEPTH_INFO); + // DB + LINK_STATES(DB_DEPTH_SIZE); + LINK_STATES(DB_DEPTH_VIEW); + LINK_STATES(DB_DEPTH_BASE); + LINK_STATES(DB_DEPTH_INFO); LINK_STATES(DB_HTILE_DATA_BASE); - LINK_STATES(DB_STENCIL_CLEAR); - LINK_STATES(DB_DEPTH_CLEAR); - - LINK_STATES(PA_SC_SCREEN_SCISSOR_TL); - LINK_STATES(PA_SC_SCREEN_SCISSOR_BR); - - LINK_STATES(CB_COLOR0_BASE); - - LINK_STATES(CB_COLOR0_SIZE); - - LINK_STATES(CB_COLOR0_VIEW); - - LINK_STATES(CB_COLOR0_INFO); - LINK_STATES(CB_COLOR1_INFO); - LINK_STATES(CB_COLOR2_INFO); - LINK_STATES(CB_COLOR3_INFO); - LINK_STATES(CB_COLOR4_INFO); - LINK_STATES(CB_COLOR5_INFO); - LINK_STATES(CB_COLOR6_INFO); - LINK_STATES(CB_COLOR7_INFO); - - LINK_STATES(CB_COLOR0_TILE); - - LINK_STATES(CB_COLOR0_FRAG); - - LINK_STATES(CB_COLOR0_MASK); + LINK_STATES(DB_DEPTH_CLEAR); + LINK_STATES(DB_DEPTH_CONTROL); + LINK_STATES(DB_SHADER_CONTROL); + LINK_STATES(DB_RENDER_CONTROL); + LINK_STATES(DB_RENDER_OVERRIDE); + LINK_STATES(DB_HTILE_SURFACE); + LINK_STATES(DB_ALPHA_TO_MASK); + // SC + LINK_STATES(PA_SC_SCREEN_SCISSOR_TL); + LINK_STATES(PA_SC_SCREEN_SCISSOR_BR); LINK_STATES(PA_SC_WINDOW_OFFSET); - LINK_STATES(PA_SC_WINDOW_SCISSOR_TL); - LINK_STATES(PA_SC_WINDOW_SCISSOR_BR); - LINK_STATES(PA_SC_CLIPRECT_RULE); - LINK_STATES(PA_SC_CLIPRECT_0_TL); - LINK_STATES(PA_SC_CLIPRECT_0_BR); - LINK_STATES(PA_SC_CLIPRECT_1_TL); - LINK_STATES(PA_SC_CLIPRECT_1_BR); - LINK_STATES(PA_SC_CLIPRECT_2_TL); - LINK_STATES(PA_SC_CLIPRECT_2_BR); - LINK_STATES(PA_SC_CLIPRECT_3_TL); - LINK_STATES(PA_SC_CLIPRECT_3_BR); - - LINK_STATES(PA_SC_EDGERULE); - - LINK_STATES(CB_TARGET_MASK); - LINK_STATES(CB_SHADER_MASK); - LINK_STATES(PA_SC_GENERIC_SCISSOR_TL); - LINK_STATES(PA_SC_GENERIC_SCISSOR_BR); - - LINK_STATES(PA_SC_VPORT_SCISSOR_0_TL); - LINK_STATES(PA_SC_VPORT_SCISSOR_0_BR); - LINK_STATES(PA_SC_VPORT_SCISSOR_1_TL); - LINK_STATES(PA_SC_VPORT_SCISSOR_1_BR); - - LINK_STATES(PA_SC_VPORT_ZMIN_0); - LINK_STATES(PA_SC_VPORT_ZMAX_0); - - LINK_STATES(SX_MISC); - - LINK_STATES(SQ_VTX_SEMANTIC_0); - LINK_STATES(SQ_VTX_SEMANTIC_1); - LINK_STATES(SQ_VTX_SEMANTIC_2); - LINK_STATES(SQ_VTX_SEMANTIC_3); - LINK_STATES(SQ_VTX_SEMANTIC_4); - LINK_STATES(SQ_VTX_SEMANTIC_5); - LINK_STATES(SQ_VTX_SEMANTIC_6); - LINK_STATES(SQ_VTX_SEMANTIC_7); - LINK_STATES(SQ_VTX_SEMANTIC_8); - LINK_STATES(SQ_VTX_SEMANTIC_9); - LINK_STATES(SQ_VTX_SEMANTIC_10); - LINK_STATES(SQ_VTX_SEMANTIC_11); - LINK_STATES(SQ_VTX_SEMANTIC_12); - LINK_STATES(SQ_VTX_SEMANTIC_13); - LINK_STATES(SQ_VTX_SEMANTIC_14); - LINK_STATES(SQ_VTX_SEMANTIC_15); - LINK_STATES(SQ_VTX_SEMANTIC_16); - LINK_STATES(SQ_VTX_SEMANTIC_17); - LINK_STATES(SQ_VTX_SEMANTIC_18); - LINK_STATES(SQ_VTX_SEMANTIC_19); - LINK_STATES(SQ_VTX_SEMANTIC_20); - LINK_STATES(SQ_VTX_SEMANTIC_21); - LINK_STATES(SQ_VTX_SEMANTIC_22); - LINK_STATES(SQ_VTX_SEMANTIC_23); - LINK_STATES(SQ_VTX_SEMANTIC_24); - LINK_STATES(SQ_VTX_SEMANTIC_25); - LINK_STATES(SQ_VTX_SEMANTIC_26); - LINK_STATES(SQ_VTX_SEMANTIC_27); - LINK_STATES(SQ_VTX_SEMANTIC_28); - LINK_STATES(SQ_VTX_SEMANTIC_29); - LINK_STATES(SQ_VTX_SEMANTIC_30); - LINK_STATES(SQ_VTX_SEMANTIC_31); - - LINK_STATES(VGT_MAX_VTX_INDX); - LINK_STATES(VGT_MIN_VTX_INDX); - LINK_STATES(VGT_INDX_OFFSET); - LINK_STATES(VGT_MULTI_PRIM_IB_RESET_INDX); - LINK_STATES(SX_ALPHA_TEST_CONTROL); - - LINK_STATES(CB_BLEND_RED); + LINK_STATES(PA_SC_WINDOW_SCISSOR_TL); + LINK_STATES(PA_SC_WINDOW_SCISSOR_BR); + LINK_STATES(PA_SC_CLIPRECT_RULE); + LINK_STATES(PA_SC_CLIPRECT_0_TL); + LINK_STATES(PA_SC_CLIPRECT_0_BR); + LINK_STATES(PA_SC_CLIPRECT_1_TL); + LINK_STATES(PA_SC_CLIPRECT_1_BR); + LINK_STATES(PA_SC_CLIPRECT_2_TL); + LINK_STATES(PA_SC_CLIPRECT_2_BR); + LINK_STATES(PA_SC_CLIPRECT_3_TL); + LINK_STATES(PA_SC_CLIPRECT_3_BR); + LINK_STATES(PA_SC_EDGERULE); + LINK_STATES(PA_SC_GENERIC_SCISSOR_TL); + LINK_STATES(PA_SC_GENERIC_SCISSOR_BR); + LINK_STATES(PA_SC_LINE_STIPPLE); + LINK_STATES(PA_SC_MPASS_PS_CNTL); + LINK_STATES(PA_SC_MODE_CNTL); + LINK_STATES(PA_SC_LINE_CNTL); + LINK_STATES(PA_SC_AA_CONFIG); + LINK_STATES(PA_SC_AA_SAMPLE_LOCS_MCTX); + LINK_STATES(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX); + LINK_STATES(PA_SC_AA_MASK); + + // SU + LINK_STATES(PA_SU_POINT_SIZE); + LINK_STATES(PA_SU_POINT_MINMAX); + LINK_STATES(PA_SU_LINE_CNTL); + LINK_STATES(PA_SU_SC_MODE_CNTL); + LINK_STATES(PA_SU_VTX_CNTL); + LINK_STATES(PA_SU_POLY_OFFSET_DB_FMT_CNTL); + LINK_STATES(PA_SU_POLY_OFFSET_CLAMP); + LINK_STATES(PA_SU_POLY_OFFSET_FRONT_SCALE); + LINK_STATES(PA_SU_POLY_OFFSET_FRONT_OFFSET); + LINK_STATES(PA_SU_POLY_OFFSET_BACK_SCALE); + + // CL + LINK_STATES(PA_CL_CLIP_CNTL); + LINK_STATES(PA_CL_VTE_CNTL); + LINK_STATES(PA_CL_VS_OUT_CNTL); + LINK_STATES(PA_CL_NANINF_CNTL); + LINK_STATES(PA_CL_GB_VERT_CLIP_ADJ); + LINK_STATES(PA_CL_GB_VERT_DISC_ADJ); + LINK_STATES(PA_CL_GB_HORZ_CLIP_ADJ); + LINK_STATES(PA_CL_GB_HORZ_DISC_ADJ); + + // CB + LINK_STATES(CB_TARGET_MASK); + LINK_STATES(CB_SHADER_MASK); + LINK_STATES(CB_BLEND_RED); LINK_STATES(CB_BLEND_GREEN); - LINK_STATES(CB_BLEND_BLUE); + LINK_STATES(CB_BLEND_BLUE); LINK_STATES(CB_BLEND_ALPHA); + LINK_STATES(CB_SHADER_CONTROL); + LINK_STATES(CB_COLOR_CONTROL); + LINK_STATES(CB_CLRCMP_CONTROL); + LINK_STATES(CB_CLRCMP_SRC); + LINK_STATES(CB_CLRCMP_DST); + LINK_STATES(CB_CLRCMP_MSK); + + // SX + LINK_STATES(SX_MISC); + LINK_STATES(SX_ALPHA_TEST_CONTROL); + + // VGT + LINK_STATES(VGT_MAX_VTX_INDX); + LINK_STATES(VGT_MIN_VTX_INDX); + LINK_STATES(VGT_INDX_OFFSET); + LINK_STATES(VGT_MULTI_PRIM_IB_RESET_INDX); + LINK_STATES(VGT_OUTPUT_PATH_CNTL); + LINK_STATES(VGT_GS_MODE); + LINK_STATES(VGT_PRIMITIVEID_EN); + LINK_STATES(VGT_DMA_NUM_INSTANCES); + LINK_STATES(VGT_MULTI_PRIM_IB_RESET_EN); + LINK_STATES(VGT_INSTANCE_STEP_RATE_0); + LINK_STATES(VGT_INSTANCE_STEP_RATE_1); + LINK_STATES(VGT_STRMOUT_EN); + LINK_STATES(VGT_REUSE_OFF); - LINK_STATES(PA_CL_VPORT_XSCALE); - LINK_STATES(PA_CL_VPORT_XOFFSET); - LINK_STATES(PA_CL_VPORT_YSCALE); - LINK_STATES(PA_CL_VPORT_YOFFSET); - LINK_STATES(PA_CL_VPORT_ZSCALE); - LINK_STATES(PA_CL_VPORT_ZOFFSET); - - LINK_STATES(SPI_VS_OUT_ID_0); + // SPI + LINK_STATES(SPI_VS_OUT_ID_0); LINK_STATES(SPI_VS_OUT_ID_1); LINK_STATES(SPI_VS_OUT_ID_2); LINK_STATES(SPI_VS_OUT_ID_3); @@ -182,152 +165,33 @@ GLboolean r700InitChipObject(context_t *context) LINK_STATES(SPI_VS_OUT_ID_7); LINK_STATES(SPI_VS_OUT_ID_8); LINK_STATES(SPI_VS_OUT_ID_9); - - LINK_STATES(SPI_PS_INPUT_CNTL_0); - LINK_STATES(SPI_PS_INPUT_CNTL_1); - LINK_STATES(SPI_PS_INPUT_CNTL_2); - LINK_STATES(SPI_PS_INPUT_CNTL_3); - LINK_STATES(SPI_PS_INPUT_CNTL_4); - LINK_STATES(SPI_PS_INPUT_CNTL_5); - LINK_STATES(SPI_PS_INPUT_CNTL_6); - LINK_STATES(SPI_PS_INPUT_CNTL_7); - LINK_STATES(SPI_PS_INPUT_CNTL_8); - LINK_STATES(SPI_PS_INPUT_CNTL_9); - LINK_STATES(SPI_PS_INPUT_CNTL_10); - LINK_STATES(SPI_PS_INPUT_CNTL_11); - LINK_STATES(SPI_PS_INPUT_CNTL_12); - LINK_STATES(SPI_PS_INPUT_CNTL_13); - LINK_STATES(SPI_PS_INPUT_CNTL_14); - LINK_STATES(SPI_PS_INPUT_CNTL_15); - LINK_STATES(SPI_PS_INPUT_CNTL_16); - LINK_STATES(SPI_PS_INPUT_CNTL_17); - LINK_STATES(SPI_PS_INPUT_CNTL_18); - LINK_STATES(SPI_PS_INPUT_CNTL_19); - LINK_STATES(SPI_PS_INPUT_CNTL_20); - LINK_STATES(SPI_PS_INPUT_CNTL_21); - LINK_STATES(SPI_PS_INPUT_CNTL_22); - LINK_STATES(SPI_PS_INPUT_CNTL_23); - LINK_STATES(SPI_PS_INPUT_CNTL_24); - LINK_STATES(SPI_PS_INPUT_CNTL_25); - LINK_STATES(SPI_PS_INPUT_CNTL_26); - LINK_STATES(SPI_PS_INPUT_CNTL_27); - LINK_STATES(SPI_PS_INPUT_CNTL_28); - LINK_STATES(SPI_PS_INPUT_CNTL_29); - LINK_STATES(SPI_PS_INPUT_CNTL_30); - LINK_STATES(SPI_PS_INPUT_CNTL_31); - LINK_STATES(SPI_VS_OUT_CONFIG); + LINK_STATES(SPI_VS_OUT_CONFIG); LINK_STATES(SPI_THREAD_GROUPING); - LINK_STATES(SPI_PS_IN_CONTROL_0); + LINK_STATES(SPI_PS_IN_CONTROL_0); LINK_STATES(SPI_PS_IN_CONTROL_1); LINK_STATES(SPI_INTERP_CONTROL_0); - - LINK_STATES(SPI_INPUT_Z); + LINK_STATES(SPI_INPUT_Z); LINK_STATES(SPI_FOG_CNTL); - LINK_STATES(CB_BLEND0_CONTROL); - - LINK_STATES(CB_SHADER_CONTROL); - - /*LINK_STATES(VGT_DRAW_INITIATOR); */ - - LINK_STATES(DB_DEPTH_CONTROL); - - LINK_STATES(CB_COLOR_CONTROL); - LINK_STATES(DB_SHADER_CONTROL); - LINK_STATES(PA_CL_CLIP_CNTL); - LINK_STATES(PA_SU_SC_MODE_CNTL); - LINK_STATES(PA_CL_VTE_CNTL); - LINK_STATES(PA_CL_VS_OUT_CNTL); - LINK_STATES(PA_CL_NANINF_CNTL); - - LINK_STATES(SQ_PGM_START_PS); - LINK_STATES(SQ_PGM_RESOURCES_PS); - LINK_STATES(SQ_PGM_EXPORTS_PS); - LINK_STATES(SQ_PGM_START_VS); - LINK_STATES(SQ_PGM_RESOURCES_VS); - LINK_STATES(SQ_PGM_START_GS); - LINK_STATES(SQ_PGM_RESOURCES_GS); - LINK_STATES(SQ_PGM_START_ES); - LINK_STATES(SQ_PGM_RESOURCES_ES); - LINK_STATES(SQ_PGM_START_FS); - LINK_STATES(SQ_PGM_RESOURCES_FS); - LINK_STATES(SQ_ESGS_RING_ITEMSIZE); - LINK_STATES(SQ_GSVS_RING_ITEMSIZE); + // SQ + LINK_STATES(SQ_ESGS_RING_ITEMSIZE); + LINK_STATES(SQ_GSVS_RING_ITEMSIZE); LINK_STATES(SQ_ESTMP_RING_ITEMSIZE); LINK_STATES(SQ_GSTMP_RING_ITEMSIZE); LINK_STATES(SQ_VSTMP_RING_ITEMSIZE); LINK_STATES(SQ_PSTMP_RING_ITEMSIZE); - LINK_STATES(SQ_FBUF_RING_ITEMSIZE); + LINK_STATES(SQ_FBUF_RING_ITEMSIZE); LINK_STATES(SQ_REDUC_RING_ITEMSIZE); - LINK_STATES(SQ_GS_VERT_ITEMSIZE); - LINK_STATES(SQ_PGM_CF_OFFSET_PS); - LINK_STATES(SQ_PGM_CF_OFFSET_VS); - LINK_STATES(SQ_PGM_CF_OFFSET_GS); - LINK_STATES(SQ_PGM_CF_OFFSET_ES); - LINK_STATES(SQ_PGM_CF_OFFSET_FS); - - LINK_STATES(PA_SU_POINT_SIZE); - LINK_STATES(PA_SU_POINT_MINMAX); - LINK_STATES(PA_SU_LINE_CNTL); - LINK_STATES(PA_SC_LINE_STIPPLE); - LINK_STATES(VGT_OUTPUT_PATH_CNTL); - - LINK_STATES(VGT_GS_MODE); - - LINK_STATES(PA_SC_MPASS_PS_CNTL); - LINK_STATES(PA_SC_MODE_CNTL); - - LINK_STATES(VGT_PRIMITIVEID_EN); - LINK_STATES(VGT_DMA_NUM_INSTANCES); - - LINK_STATES(VGT_MULTI_PRIM_IB_RESET_EN); - - LINK_STATES(VGT_INSTANCE_STEP_RATE_0); - LINK_STATES(VGT_INSTANCE_STEP_RATE_1); - - LINK_STATES(VGT_STRMOUT_EN); - LINK_STATES(VGT_REUSE_OFF); - - LINK_STATES(PA_SC_LINE_CNTL); - LINK_STATES(PA_SC_AA_CONFIG); - LINK_STATES(PA_SU_VTX_CNTL); - LINK_STATES(PA_CL_GB_VERT_CLIP_ADJ); - LINK_STATES(PA_CL_GB_VERT_DISC_ADJ); - LINK_STATES(PA_CL_GB_HORZ_CLIP_ADJ); - LINK_STATES(PA_CL_GB_HORZ_DISC_ADJ); - LINK_STATES(PA_SC_AA_SAMPLE_LOCS_MCTX); - LINK_STATES(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX); - - LINK_STATES(CB_CLRCMP_CONTROL); - LINK_STATES(CB_CLRCMP_SRC); - LINK_STATES(CB_CLRCMP_DST); - LINK_STATES(CB_CLRCMP_MSK); - - LINK_STATES(PA_SC_AA_MASK); - - LINK_STATES(DB_RENDER_CONTROL); - LINK_STATES(DB_RENDER_OVERRIDE); - - LINK_STATES(DB_HTILE_SURFACE); - - LINK_STATES(DB_ALPHA_TO_MASK); - - LINK_STATES(PA_SU_POLY_OFFSET_DB_FMT_CNTL); - LINK_STATES(PA_SU_POLY_OFFSET_CLAMP); - LINK_STATES(PA_SU_POLY_OFFSET_FRONT_SCALE); - LINK_STATES(PA_SU_POLY_OFFSET_FRONT_OFFSET); - LINK_STATES(PA_SU_POLY_OFFSET_BACK_SCALE); + //LINK_STATES(SQ_GS_VERT_ITEMSIZE); - pStateListWork->puiValue = (unsigned int*)&(r700->PA_SU_POLY_OFFSET_BACK_OFFSET); - pStateListWork->unOffset = mmPA_SU_POLY_OFFSET_BACK_OFFSET - ASIC_CONTEXT_BASE_INDEX; + pStateListWork->puiValue = (unsigned int*)&(r700->SQ_GS_VERT_ITEMSIZE); + pStateListWork->unOffset = mmSQ_GS_VERT_ITEMSIZE - ASIC_CONTEXT_BASE_INDEX; pStateListWork->pNext = NULL; /* END OF STATE LIST */ - /* TODO : may need order sorting in case someone break the order of states in R700_CHIP_CONTEXT. */ - return GL_TRUE; } -void r700SetupVTXConstants(GLcontext * ctx, +void r700SetupVTXConstants(GLcontext * ctx, unsigned int nStreamID, void * pAos, unsigned int size, /* number of elements in vector */ @@ -348,37 +212,37 @@ void r700SetupVTXConstants(GLcontext * ctx, unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0; uSQ_VTX_CONSTANT_WORD0_0 = paos->offset; - uSQ_VTX_CONSTANT_WORD1_0 = count * stride - 1; - - uSQ_VTX_CONSTANT_WORD2_0 |= 0 << BASE_ADDRESS_HI_shift /* TODO */ - |stride << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift - |GetSurfaceFormat(GL_FLOAT, size, NULL) << SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift /* TODO : trace back api for initial data type, not only GL_FLOAT */ - |SQ_NUM_FORMAT_SCALED << SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift - |SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit; - - uSQ_VTX_CONSTANT_WORD3_0 |= 1 << MEM_REQUEST_SIZE_shift; - - uSQ_VTX_CONSTANT_WORD6_0 |= SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift; + uSQ_VTX_CONSTANT_WORD1_0 = count * stride - 1; + + uSQ_VTX_CONSTANT_WORD2_0 |= 0 << BASE_ADDRESS_HI_shift /* TODO */ + |stride << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift + |GetSurfaceFormat(GL_FLOAT, size, NULL) << SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift /* TODO : trace back api for initial data type, not only GL_FLOAT */ + |SQ_NUM_FORMAT_SCALED << SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift + |SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit; + + uSQ_VTX_CONSTANT_WORD3_0 |= 1 << MEM_REQUEST_SIZE_shift; + + uSQ_VTX_CONSTANT_WORD6_0 |= SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift; BEGIN_BATCH_NO_AUTOSTATE(9); - R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); R600_OUT_BATCH((nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE); - R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0, - paos->bo, - uSQ_VTX_CONSTANT_WORD0_0, - RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); - R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0); - R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0); - R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0); - R600_OUT_BATCH(0); - R600_OUT_BATCH(0); - R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0); + R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0, + paos->bo, + uSQ_VTX_CONSTANT_WORD0_0, + RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0); END_BATCH(); COMMIT_BATCH(); - + } int r700SetupStreams(GLcontext * ctx) @@ -411,17 +275,17 @@ int r700SetupStreams(GLcontext * ctx) for(i=0; imesa_program.Base.InputsRead & unBit) - { - rcommon_emit_vector(ctx, + if(vpc->mesa_program.Base.InputsRead & unBit) + { + rcommon_emit_vector(ctx, &context->radeon.tcl.aos[i], vb->AttribPtr[i]->data, vb->AttribPtr[i]->size, - vb->AttribPtr[i]->stride, + vb->AttribPtr[i]->stride, vb->Count); /* currently aos are packed */ - r700SetupVTXConstants(ctx, + r700SetupVTXConstants(ctx, i, (void*)(&context->radeon.tcl.aos[i]), (unsigned int)vb->AttribPtr[i]->size, @@ -429,13 +293,13 @@ int r700SetupStreams(GLcontext * ctx) (unsigned int)vb->Count); } } - + return R600_FALLBACK_NONE; } inline GLboolean needRelocReg(context_t *context, unsigned int reg) { - switch (reg + ASIC_CONTEXT_BASE_INDEX) + switch (reg + ASIC_CONTEXT_BASE_INDEX) { case mmCB_COLOR0_BASE: case mmCB_COLOR1_BASE: @@ -444,13 +308,13 @@ inline GLboolean needRelocReg(context_t *context, unsigned int reg) case mmCB_COLOR4_BASE: case mmCB_COLOR5_BASE: case mmCB_COLOR6_BASE: - case mmCB_COLOR7_BASE: + case mmCB_COLOR7_BASE: case mmDB_DEPTH_BASE: - case mmSQ_PGM_START_VS: - case mmSQ_PGM_START_FS: - case mmSQ_PGM_START_ES: - case mmSQ_PGM_START_GS: - case mmSQ_PGM_START_PS: + case mmSQ_PGM_START_VS: + case mmSQ_PGM_START_FS: + case mmSQ_PGM_START_ES: + case mmSQ_PGM_START_GS: + case mmSQ_PGM_START_PS: return GL_TRUE; break; } @@ -467,39 +331,8 @@ inline GLboolean setRelocReg(context_t *context, unsigned int reg) uint32_t voffset; offset_modifiers offset_mod; - switch (reg + ASIC_CONTEXT_BASE_INDEX) + switch (reg + ASIC_CONTEXT_BASE_INDEX) { - case mmCB_COLOR0_BASE: - case mmCB_COLOR1_BASE: - case mmCB_COLOR2_BASE: - case mmCB_COLOR3_BASE: - case mmCB_COLOR4_BASE: - case mmCB_COLOR5_BASE: - case mmCB_COLOR6_BASE: - case mmCB_COLOR7_BASE: - { - GLcontext *ctx = GL_CONTEXT(context); - struct radeon_renderbuffer *rrb; - - rrb = radeon_get_colorbuffer(&context->radeon); - if (!rrb || !rrb->bo) - { - fprintf(stderr, "no rrb\n"); - return GL_FALSE; - } - - /* refer to radeonCreateScreen : screen->fbLocation = (temp & 0xffff) << 16; */ - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - - R600_OUT_BATCH_RELOC(r700->CB_COLOR0_BASE.u32All, - rrb->bo, - r700->CB_COLOR0_BASE.u32All, - 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod); - return GL_TRUE; - } - break; case mmDB_DEPTH_BASE: { GLcontext *ctx = GL_CONTEXT(context); @@ -510,48 +343,14 @@ inline GLboolean setRelocReg(context_t *context, unsigned int reg) offset_mod.shiftbits = 0; offset_mod.mask = 0xFFFFFFFF; - R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All, - rrb->bo, - r700->DB_DEPTH_BASE.u32All, + R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All, + rrb->bo, + r700->DB_DEPTH_BASE.u32All, 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod); return GL_TRUE; } break; - case mmSQ_PGM_START_VS: - { - pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); - - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - - R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_VS.u32All, - pbo, - r700->SQ_PGM_START_VS.u32All, - RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); - return GL_TRUE; - } - break; - case mmSQ_PGM_START_FS: - case mmSQ_PGM_START_ES: - case mmSQ_PGM_START_GS: - case mmSQ_PGM_START_PS: - { - pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context)); - - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - - voffset = 0; - R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_PS.u32All, - pbo, - r700->SQ_PGM_START_PS.u32All, - RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); - return GL_TRUE; - } - break; } return GL_FALSE; @@ -566,7 +365,7 @@ GLboolean r700SendContextStates(context_t *context) ContextState * pState = r700->pStateList; ContextState * pInit; unsigned int toSend; - unsigned int ui; + unsigned int ui; while(NULL != pState) { @@ -612,5 +411,162 @@ GLboolean r700SendContextStates(context_t *context) } +GLboolean r700SendRenderTargetState(context_t *context, int id) +{ + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + struct radeon_renderbuffer *rrb; + struct radeon_bo * pbo; + offset_modifiers offset_mod; + BATCH_LOCALS(&context->radeon); + + rrb = radeon_get_colorbuffer(&context->radeon); + if (!rrb || !rrb->bo) { + fprintf(stderr, "no rrb\n"); + return GL_FALSE; + } + + if (id > R700_MAX_RENDER_TARGETS) + return GL_FALSE; + + if (!r700->render_target[id].enabled) + return GL_FALSE; + + offset_mod.shift = NO_SHIFT; + offset_mod.shiftbits = 0; + offset_mod.mask = 0xFFFFFFFF; + + BEGIN_BATCH_NO_AUTOSTATE(3); + R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1); + R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All, + rrb->bo, + r700->render_target[id].CB_COLOR0_BASE.u32All, + 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod); + END_BATCH(); + + if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) && + (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) { + BEGIN_BATCH_NO_AUTOSTATE(2); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0)); + R600_OUT_BATCH((2 << id)); + END_BATCH(); + } + + BEGIN_BATCH_NO_AUTOSTATE(18); + R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), r700->render_target[id].CB_COLOR0_SIZE.u32All); + R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), r700->render_target[id].CB_COLOR0_VIEW.u32All); + R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), r700->render_target[id].CB_COLOR0_INFO.u32All); + R600_OUT_BATCH_REGVAL(CB_COLOR0_TILE + (4 * id), r700->render_target[id].CB_COLOR0_TILE.u32All); + R600_OUT_BATCH_REGVAL(CB_COLOR0_FRAG + (4 * id), r700->render_target[id].CB_COLOR0_FRAG.u32All); + R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), r700->render_target[id].CB_COLOR0_MASK.u32All); + END_BATCH(); + + if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) { + BEGIN_BATCH_NO_AUTOSTATE(3); + R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * id), r700->render_target[id].CB_BLEND0_CONTROL.u32All); + END_BATCH(); + } + + COMMIT_BATCH(); + + return GL_TRUE; +} + +GLboolean r700SendPSState(context_t *context) +{ + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + struct radeon_renderbuffer *rrb; + struct radeon_bo * pbo; + offset_modifiers offset_mod; + BATCH_LOCALS(&context->radeon); + + pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context)); + + offset_mod.shift = NO_SHIFT; + offset_mod.shiftbits = 0; + offset_mod.mask = 0xFFFFFFFF; + + BEGIN_BATCH_NO_AUTOSTATE(3); + R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1); + R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All, + pbo, + r700->ps.SQ_PGM_START_PS.u32All, + RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + END_BATCH(); + + BEGIN_BATCH_NO_AUTOSTATE(9); + R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, r700->ps.SQ_PGM_RESOURCES_PS.u32All); + R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, r700->ps.SQ_PGM_EXPORTS_PS.u32All); + R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, r700->ps.SQ_PGM_CF_OFFSET_PS.u32All); + END_BATCH(); + + COMMIT_BATCH(); + + return GL_TRUE; +} + +GLboolean r700SendVSState(context_t *context) +{ + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + struct radeon_renderbuffer *rrb; + struct radeon_bo * pbo; + offset_modifiers offset_mod; + BATCH_LOCALS(&context->radeon); + + pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); + + offset_mod.shift = NO_SHIFT; + offset_mod.shiftbits = 0; + offset_mod.mask = 0xFFFFFFFF; + + BEGIN_BATCH_NO_AUTOSTATE(3); + R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1); + R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All, + pbo, + r700->vs.SQ_PGM_START_VS.u32All, + RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + END_BATCH(); + + BEGIN_BATCH_NO_AUTOSTATE(6); + R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, r700->vs.SQ_PGM_RESOURCES_VS.u32All); + R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, r700->vs.SQ_PGM_CF_OFFSET_VS.u32All); + END_BATCH(); + + COMMIT_BATCH(); + + return GL_TRUE; +} +GLboolean r700SendViewportState(context_t *context, int id) +{ + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + struct radeon_renderbuffer *rrb; + struct radeon_bo * pbo; + offset_modifiers offset_mod; + BATCH_LOCALS(&context->radeon); + + if (id > R700_MAX_VIEWPORTS) + return GL_FALSE; + + if (!r700->viewport[id].enabled) + return GL_FALSE; + + BEGIN_BATCH_NO_AUTOSTATE(16); + R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL + (8 * id), 2); + R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All); + R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All); + R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_ZMIN_0 + (8 * id), 2); + R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All); + R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All); + R600_OUT_BATCH_REGSEQ(PA_CL_VPORT_XSCALE_0 + (24 * id), 6); + R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XSCALE.u32All); + R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XOFFSET.u32All); + R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YSCALE.u32All); + R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YOFFSET.u32All); + R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZSCALE.u32All); + R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZOFFSET.u32All); + END_BATCH(); + COMMIT_BATCH(); + + return GL_TRUE; +} diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h index 4ceada7378..2129c0bdf4 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.h +++ b/src/mesa/drivers/dri/r600/r700_chip.h @@ -42,6 +42,10 @@ #define CLEARbit(x, bit) ( (x) &= ~(bit) ) #define R700_TEXTURE_NUMBERUNITS 16 +#define R700_MAX_RENDER_TARGETS 8 +#define R700_MAX_VIEWPORTS 16 +#define R700_MAX_SHADER_EXPORTS 32 +#define R700_MAX_UCP 6 /* Enum not show in r600_*.h */ @@ -170,6 +174,79 @@ typedef struct _R700_TEXTURE_STATES SAMPLER_STATE_STRUCT *samplers[R700_TEXTURE_NUMBERUNITS]; } R700_TEXTURE_STATES; +typedef struct _RENDER_TARGET_STATE_STRUCT +{ + union UINT_FLOAT CB_COLOR0_BASE; /* 0xA010 */ + union UINT_FLOAT CB_COLOR0_SIZE; /* 0xA018 */ + union UINT_FLOAT CB_COLOR0_VIEW; /* 0xA020 */ + union UINT_FLOAT CB_COLOR0_INFO; /* 0xA028 */ + union UINT_FLOAT CB_COLOR0_TILE; /* 0xA030 */ + union UINT_FLOAT CB_COLOR0_FRAG; /* 0xA038 */ + union UINT_FLOAT CB_COLOR0_MASK; /* 0xA040 */ + union UINT_FLOAT CB_BLEND0_CONTROL; /* 0xA1E0 */ + GLboolean enabled; +} RENDER_TARGET_STATE_STRUCT; + +typedef struct _VIEWPORT_STATE_STRUCT +{ + union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_TL; /* 0xA094 */ + union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_BR; /* 0xA095 */ + union UINT_FLOAT PA_SC_VPORT_ZMIN_0; /* 0xA0B4 */ + union UINT_FLOAT PA_SC_VPORT_ZMAX_0; /* 0xA0B5 */ + union UINT_FLOAT PA_CL_VPORT_XSCALE; /* 0xA10F */ + union UINT_FLOAT PA_CL_VPORT_XOFFSET; /* 0xA110 */ + union UINT_FLOAT PA_CL_VPORT_YSCALE; /* 0xA111 */ + union UINT_FLOAT PA_CL_VPORT_YOFFSET; /* 0xA112 */ + union UINT_FLOAT PA_CL_VPORT_ZSCALE; /* 0xA113 */ + union UINT_FLOAT PA_CL_VPORT_ZOFFSET; /* 0xA114 */ + GLboolean enabled; +} VIEWPORT_STATE_STRUCT; + +typedef struct _UCP_STATE_STRUCT +{ + union UINT_FLOAT PA_CL_UCP_0_X; + union UINT_FLOAT PA_CL_UCP_0_Y; + union UINT_FLOAT PA_CL_UCP_0_Z; + union UINT_FLOAT PA_CL_UCP_0_W; + GLboolean enabled; +} UCP_STATE_STRUCT; + +typedef struct _PS_STATE_STRUCT +{ + union UINT_FLOAT SQ_PGM_START_PS ; /* 0xA210 */ + union UINT_FLOAT SQ_PGM_RESOURCES_PS ; /* 0xA214 */ + union UINT_FLOAT SQ_PGM_EXPORTS_PS ; /* 0xA215 */ + union UINT_FLOAT SQ_PGM_CF_OFFSET_PS ; /* 0xA233 */ +} PS_STATE_STRUCT; + +typedef struct _VS_STATE_STRUCT +{ + union UINT_FLOAT SQ_PGM_START_VS ; /* 0xA216 */ + union UINT_FLOAT SQ_PGM_RESOURCES_VS ; /* 0xA21A */ + union UINT_FLOAT SQ_PGM_CF_OFFSET_VS ; /* 0xA234 */ +} VS_STATE_STRUCT; + +typedef struct _GS_STATE_STRUCT +{ + union UINT_FLOAT SQ_PGM_START_GS ; /* 0xA21B */ + union UINT_FLOAT SQ_PGM_RESOURCES_GS ; /* 0xA21F */ + union UINT_FLOAT SQ_PGM_CF_OFFSET_GS ; /* 0xA235 */ +} GS_STATE_STRUCT; + +typedef struct _ES_STATE_STRUCT +{ + union UINT_FLOAT SQ_PGM_START_ES ; /* 0xA220 */ + union UINT_FLOAT SQ_PGM_RESOURCES_ES ; /* 0xA224 */ + union UINT_FLOAT SQ_PGM_CF_OFFSET_ES ; /* 0xA236 */ +} ES_STATE_STRUCT; + +typedef struct _FS_STATE_STRUCT +{ + union UINT_FLOAT SQ_PGM_START_FS ; /* 0xA225 */ + union UINT_FLOAT SQ_PGM_RESOURCES_FS ; /* 0xA229 */ + union UINT_FLOAT SQ_PGM_CF_OFFSET_FS ; /* 0xA237 */ +} FS_STATE_STRUCT; + typedef struct ContextState { unsigned int * puiValue; @@ -179,43 +256,27 @@ typedef struct ContextState typedef struct _R700_CHIP_CONTEXT { + // DB union UINT_FLOAT DB_DEPTH_SIZE ; /* 0xA000 */ union UINT_FLOAT DB_DEPTH_VIEW ; /* 0xA001 */ - union UINT_FLOAT DB_DEPTH_BASE ; /* 0xA003 */ union UINT_FLOAT DB_DEPTH_INFO ; /* 0xA004 */ - union UINT_FLOAT DB_HTILE_DATA_BASE ; /* 0xA005 */ - - union UINT_FLOAT DB_STENCIL_CLEAR ; /* 0xA00A */ + union UINT_FLOAT DB_HTILE_DATA_BASE ; /* 0xA005 */ + union UINT_FLOAT DB_STENCIL_CLEAR ; /* 0xA00A */ union UINT_FLOAT DB_DEPTH_CLEAR ; /* 0xA00B */ - - union UINT_FLOAT PA_SC_SCREEN_SCISSOR_TL ; /* 0xA00C */ - union UINT_FLOAT PA_SC_SCREEN_SCISSOR_BR ; /* 0xA00D */ - - union UINT_FLOAT CB_COLOR0_BASE ; /* 0xA010 */ - - union UINT_FLOAT CB_COLOR0_SIZE ; /* 0xA018 */ - - union UINT_FLOAT CB_COLOR0_VIEW ; /* 0xA020 */ - - union UINT_FLOAT CB_COLOR0_INFO ; /* 0xA028 */ - union UINT_FLOAT CB_COLOR1_INFO ; /* 0xA029 */ - union UINT_FLOAT CB_COLOR2_INFO ; /* 0xA02A */ - union UINT_FLOAT CB_COLOR3_INFO ; /* 0xA02B */ - union UINT_FLOAT CB_COLOR4_INFO ; /* 0xA02C */ - union UINT_FLOAT CB_COLOR5_INFO ; /* 0xA02D */ - union UINT_FLOAT CB_COLOR6_INFO ; /* 0xA02E */ - union UINT_FLOAT CB_COLOR7_INFO ; /* 0xA02F */ - - union UINT_FLOAT CB_COLOR0_TILE ; /* 0xA030 */ - - union UINT_FLOAT CB_COLOR0_FRAG ; /* 0xA038 */ - - union UINT_FLOAT CB_COLOR0_MASK ; /* 0xA040 */ - - union UINT_FLOAT PA_SC_WINDOW_OFFSET ; /* 0xA080 */ - union UINT_FLOAT PA_SC_WINDOW_SCISSOR_TL ; /* 0xA081 */ - union UINT_FLOAT PA_SC_WINDOW_SCISSOR_BR ; /* 0xA082 */ + union UINT_FLOAT DB_RENDER_CONTROL ; /* 0xA343 */ + union UINT_FLOAT DB_RENDER_OVERRIDE ; /* 0xA344 */ + union UINT_FLOAT DB_HTILE_SURFACE ; /* 0xA349 */ + union UINT_FLOAT DB_ALPHA_TO_MASK ; /* 0xA351 */ + union UINT_FLOAT DB_DEPTH_CONTROL ; /* 0xA200 */ + union UINT_FLOAT DB_SHADER_CONTROL ; /* 0xA203 */ + + // SC + union UINT_FLOAT PA_SC_SCREEN_SCISSOR_TL ; /* 0xA00C */ + union UINT_FLOAT PA_SC_SCREEN_SCISSOR_BR ; /* 0xA00D */ + union UINT_FLOAT PA_SC_WINDOW_OFFSET ; /* 0xA080 */ + union UINT_FLOAT PA_SC_WINDOW_SCISSOR_TL ; /* 0xA081 */ + union UINT_FLOAT PA_SC_WINDOW_SCISSOR_BR ; /* 0xA082 */ union UINT_FLOAT PA_SC_CLIPRECT_RULE ; /* 0xA083 */ union UINT_FLOAT PA_SC_CLIPRECT_0_TL ; /* 0xA084 */ union UINT_FLOAT PA_SC_CLIPRECT_0_BR ; /* 0xA085 */ @@ -225,78 +286,82 @@ typedef struct _R700_CHIP_CONTEXT union UINT_FLOAT PA_SC_CLIPRECT_2_BR ; /* 0xA089 */ union UINT_FLOAT PA_SC_CLIPRECT_3_TL ; /* 0xA08A */ union UINT_FLOAT PA_SC_CLIPRECT_3_BR ; /* 0xA08B */ - union UINT_FLOAT PA_SC_EDGERULE ; /* 0xA08C */ + union UINT_FLOAT PA_SC_GENERIC_SCISSOR_TL ; /* 0xA090 */ + union UINT_FLOAT PA_SC_GENERIC_SCISSOR_BR ; /* 0xA091 */ + union UINT_FLOAT PA_SC_LINE_STIPPLE ; /* 0xA283 */ + union UINT_FLOAT PA_SC_LINE_CNTL ; /* 0xA300 */ + union UINT_FLOAT PA_SC_AA_CONFIG ; /* 0xA301 */ + union UINT_FLOAT PA_SC_MPASS_PS_CNTL ; /* 0xA292 */ + union UINT_FLOAT PA_SC_MODE_CNTL ; /* 0xA293 */ + union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_MCTX ; /* 0xA307 */ + union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX; /* 0xA308 */ + union UINT_FLOAT PA_SC_AA_MASK ; /* 0xA312 */ + // CL + union UINT_FLOAT PA_CL_CLIP_CNTL ; /* 0xA204 */ + union UINT_FLOAT PA_CL_VTE_CNTL ; /* 0xA206 */ + union UINT_FLOAT PA_CL_VS_OUT_CNTL ; /* 0xA207 */ + union UINT_FLOAT PA_CL_NANINF_CNTL ; /* 0xA208 */ + union UINT_FLOAT PA_CL_GB_VERT_CLIP_ADJ ; /* 0xA303 */ + union UINT_FLOAT PA_CL_GB_VERT_DISC_ADJ ; /* 0xA304 */ + union UINT_FLOAT PA_CL_GB_HORZ_CLIP_ADJ ; /* 0xA305 */ + union UINT_FLOAT PA_CL_GB_HORZ_DISC_ADJ ; /* 0xA306 */ + + // SU + union UINT_FLOAT PA_SU_SC_MODE_CNTL ; /* 0xA205 */ + union UINT_FLOAT PA_SU_POINT_SIZE ; /* 0xA280 */ + union UINT_FLOAT PA_SU_POINT_MINMAX ; /* 0xA281 */ + union UINT_FLOAT PA_SU_LINE_CNTL ; /* 0xA282 */ + union UINT_FLOAT PA_SU_VTX_CNTL ; /* 0xA302 */ + union UINT_FLOAT PA_SU_POLY_OFFSET_DB_FMT_CNTL; /* 0xA37E */ + union UINT_FLOAT PA_SU_POLY_OFFSET_CLAMP ; /* 0xA37F */ + union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_SCALE; /* 0xA380 */ + union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_OFFSET; /* 0xA381 */ + union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_SCALE; /* 0xA382 */ + union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_OFFSET; /* 0xA383 */ + + VIEWPORT_STATE_STRUCT viewport[R700_MAX_VIEWPORTS]; + UCP_STATE_STRUCT ucp[R700_MAX_UCP]; + + // CB union UINT_FLOAT CB_TARGET_MASK ; /* 0xA08E */ union UINT_FLOAT CB_SHADER_MASK ; /* 0xA08F */ - union UINT_FLOAT PA_SC_GENERIC_SCISSOR_TL ; /* 0xA090 */ - union UINT_FLOAT PA_SC_GENERIC_SCISSOR_BR ; /* 0xA091 */ - - union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_TL ; /* 0xA094 */ - union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_BR ; /* 0xA095 */ - union UINT_FLOAT PA_SC_VPORT_SCISSOR_1_TL ; /* 0xA096 */ - union UINT_FLOAT PA_SC_VPORT_SCISSOR_1_BR ; /* 0xA097 */ - - union UINT_FLOAT PA_SC_VPORT_ZMIN_0 ; /* 0xA0B4 */ - union UINT_FLOAT PA_SC_VPORT_ZMAX_0 ; /* 0xA0B5 */ - - union UINT_FLOAT SX_MISC ; /* 0xA0D4 */ - - union UINT_FLOAT SQ_VTX_SEMANTIC_0 ; /* 0xA0E0 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_1 ; /* 0xA0E1 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_2 ; /* 0xA0E2 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_3 ; /* 0xA0E3 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_4 ; /* 0xA0E4 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_5 ; /* 0xA0E5 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_6 ; /* 0xA0E6 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_7 ; /* 0xA0E7 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_8 ; /* 0xA0E8 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_9 ; /* 0xA0E9 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_10 ; /* 0xA0EA */ - union UINT_FLOAT SQ_VTX_SEMANTIC_11 ; /* 0xA0EB */ - union UINT_FLOAT SQ_VTX_SEMANTIC_12 ; /* 0xA0EC */ - union UINT_FLOAT SQ_VTX_SEMANTIC_13 ; /* 0xA0ED */ - union UINT_FLOAT SQ_VTX_SEMANTIC_14 ; /* 0xA0EE */ - union UINT_FLOAT SQ_VTX_SEMANTIC_15 ; /* 0xA0EF */ - union UINT_FLOAT SQ_VTX_SEMANTIC_16 ; /* 0xA0F0 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_17 ; /* 0xA0F1 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_18 ; /* 0xA0F2 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_19 ; /* 0xA0F3 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_20 ; /* 0xA0F4 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_21 ; /* 0xA0F5 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_22 ; /* 0xA0F6 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_23 ; /* 0xA0F7 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_24 ; /* 0xA0F8 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_25 ; /* 0xA0F9 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_26 ; /* 0xA0FA */ - union UINT_FLOAT SQ_VTX_SEMANTIC_27 ; /* 0xA0FB */ - union UINT_FLOAT SQ_VTX_SEMANTIC_28 ; /* 0xA0FC */ - union UINT_FLOAT SQ_VTX_SEMANTIC_29 ; /* 0xA0FD */ - union UINT_FLOAT SQ_VTX_SEMANTIC_30 ; /* 0xA0FE */ - union UINT_FLOAT SQ_VTX_SEMANTIC_31 ; /* 0xA0FF */ + union UINT_FLOAT CB_BLEND_RED ; /* 0xA105 */ + union UINT_FLOAT CB_BLEND_GREEN ; /* 0xA106 */ + union UINT_FLOAT CB_BLEND_BLUE ; /* 0xA107 */ + union UINT_FLOAT CB_BLEND_ALPHA ; /* 0xA108 */ + union UINT_FLOAT CB_SHADER_CONTROL ; /* 0xA1E8 */ + union UINT_FLOAT CB_COLOR_CONTROL ; /* 0xA202 */ + union UINT_FLOAT CB_CLRCMP_CONTROL ; /* 0xA30C */ + union UINT_FLOAT CB_CLRCMP_SRC ; /* 0xA30D */ + union UINT_FLOAT CB_CLRCMP_DST ; /* 0xA30E */ + union UINT_FLOAT CB_CLRCMP_MSK ; /* 0xA30F */ + RENDER_TARGET_STATE_STRUCT render_target[R700_MAX_RENDER_TARGETS]; + + // SX + union UINT_FLOAT SX_MISC ; /* 0xA0D4 */ + union UINT_FLOAT SX_ALPHA_TEST_CONTROL ; /* 0xA104 */ + // VGT union UINT_FLOAT VGT_MAX_VTX_INDX ; /* 0xA100 */ union UINT_FLOAT VGT_MIN_VTX_INDX ; /* 0xA101 */ union UINT_FLOAT VGT_INDX_OFFSET ; /* 0xA102 */ - union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_INDX; /* 0xA103 */ - union UINT_FLOAT SX_ALPHA_TEST_CONTROL ; /* 0xA104 */ + union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_INDX; /* 0xA103 */ + union UINT_FLOAT VGT_OUTPUT_PATH_CNTL ; /* 0xA284 */ + union UINT_FLOAT VGT_GS_MODE ; /* 0xA290 */ + union UINT_FLOAT VGT_PRIMITIVEID_EN ; /* 0xA2A1 */ + union UINT_FLOAT VGT_DMA_NUM_INSTANCES ; /* 0xA2A2 */ + union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_EN; /* 0xA2A5 */ + union UINT_FLOAT VGT_INSTANCE_STEP_RATE_0 ; /* 0xA2A8 */ + union UINT_FLOAT VGT_INSTANCE_STEP_RATE_1 ; /* 0xA2A9 */ + union UINT_FLOAT VGT_STRMOUT_EN ; /* 0xA2AC */ + union UINT_FLOAT VGT_REUSE_OFF ; /* 0xA2AD */ - union UINT_FLOAT CB_BLEND_RED ; /* 0xA105 */ - union UINT_FLOAT CB_BLEND_GREEN ; /* 0xA106 */ - union UINT_FLOAT CB_BLEND_BLUE ; /* 0xA107 */ - union UINT_FLOAT CB_BLEND_ALPHA ; /* 0xA108 */ - - union UINT_FLOAT PA_CL_VPORT_XSCALE ; /* 0xA10F */ - union UINT_FLOAT PA_CL_VPORT_XOFFSET ; /* 0xA110 */ - union UINT_FLOAT PA_CL_VPORT_YSCALE ; /* 0xA111 */ - union UINT_FLOAT PA_CL_VPORT_YOFFSET ; /* 0xA112 */ - union UINT_FLOAT PA_CL_VPORT_ZSCALE ; /* 0xA113 */ - union UINT_FLOAT PA_CL_VPORT_ZOFFSET ; /* 0xA114 */ - + // SPI union UINT_FLOAT SPI_VS_OUT_ID_0 ; /* 0xA185 */ union UINT_FLOAT SPI_VS_OUT_ID_1 ; /* 0xA186 */ - union UINT_FLOAT SPI_VS_OUT_ID_2 ; /* 0xA187 */ + union UINT_FLOAT SPI_VS_OUT_ID_2 ; /* 0xA187 */ union UINT_FLOAT SPI_VS_OUT_ID_3 ; /* 0xA188 */ union UINT_FLOAT SPI_VS_OUT_ID_4 ; /* 0xA189 */ union UINT_FLOAT SPI_VS_OUT_ID_5 ; /* 0xA18A */ @@ -304,149 +369,40 @@ typedef struct _R700_CHIP_CONTEXT union UINT_FLOAT SPI_VS_OUT_ID_7 ; /* 0xA18C */ union UINT_FLOAT SPI_VS_OUT_ID_8 ; /* 0xA18D */ union UINT_FLOAT SPI_VS_OUT_ID_9 ; /* 0xA18E */ - - union UINT_FLOAT SPI_PS_INPUT_CNTL_0 ; /* 0xA191 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_1 ; /* 0xA192 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_2 ; /* 0xA193 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_3 ; /* 0xA194 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_4 ; /* 0xA195 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_5 ; /* 0xA196 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_6 ; /* 0xA197 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_7 ; /* 0xA198 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_8 ; /* 0xA199 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_9 ; /* 0xA19A */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_10 ; /* 0xA19B */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_11 ; /* 0xA19C */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_12 ; /* 0xA19D */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_13 ; /* 0xA19E */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_14 ; /* 0xA19F */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_15 ; /* 0xA1A0 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_16 ; /* 0xA1A1 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_17 ; /* 0xA1A2 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_18 ; /* 0xA1A3 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_19 ; /* 0xA1A4 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_20 ; /* 0xA1A5 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_21 ; /* 0xA1A6 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_22 ; /* 0xA1A7 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_23 ; /* 0xA1A8 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_24 ; /* 0xA1A9 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_25 ; /* 0xA1AA */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_26 ; /* 0xA1AB */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_27 ; /* 0xA1AC */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_28 ; /* 0xA1AD */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_29 ; /* 0xA1AE */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_30 ; /* 0xA1AF */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_31 ; /* 0xA1B0 */ - union UINT_FLOAT SPI_VS_OUT_CONFIG ; /* 0xA1B1 */ - union UINT_FLOAT SPI_THREAD_GROUPING ; /* 0xA1B2 */ - union UINT_FLOAT SPI_PS_IN_CONTROL_0 ; /* 0xA1B3 */ - union UINT_FLOAT SPI_PS_IN_CONTROL_1 ; /* 0xA1B4 */ - union UINT_FLOAT SPI_INTERP_CONTROL_0 ; /* 0xA1B5 */ - - union UINT_FLOAT SPI_INPUT_Z ; /* 0xA1B6 */ - union UINT_FLOAT SPI_FOG_CNTL ; /* 0xA1B7 */ - - union UINT_FLOAT CB_BLEND0_CONTROL ; /* 0xA1E0 */ - - union UINT_FLOAT CB_SHADER_CONTROL ; /* 0xA1E8 */ - - /*union UINT_FLOAT VGT_DRAW_INITIATOR*/ ; /* 0xA1FC */ - - union UINT_FLOAT DB_DEPTH_CONTROL ; /* 0xA200 */ - - union UINT_FLOAT CB_COLOR_CONTROL ; /* 0xA202 */ - union UINT_FLOAT DB_SHADER_CONTROL ; /* 0xA203 */ - union UINT_FLOAT PA_CL_CLIP_CNTL ; /* 0xA204 */ - union UINT_FLOAT PA_SU_SC_MODE_CNTL ; /* 0xA205 */ - union UINT_FLOAT PA_CL_VTE_CNTL ; /* 0xA206 */ - union UINT_FLOAT PA_CL_VS_OUT_CNTL ; /* 0xA207 */ - union UINT_FLOAT PA_CL_NANINF_CNTL ; /* 0xA208 */ - - union UINT_FLOAT SQ_PGM_START_PS ; /* 0xA210 */ - union UINT_FLOAT SQ_PGM_RESOURCES_PS ; /* 0xA214 */ - union UINT_FLOAT SQ_PGM_EXPORTS_PS ; /* 0xA215 */ - union UINT_FLOAT SQ_PGM_START_VS ; /* 0xA216 */ - union UINT_FLOAT SQ_PGM_RESOURCES_VS ; /* 0xA21A */ - union UINT_FLOAT SQ_PGM_START_GS ; /* 0xA21B */ - union UINT_FLOAT SQ_PGM_RESOURCES_GS ; /* 0xA21F */ - union UINT_FLOAT SQ_PGM_START_ES ; /* 0xA220 */ - union UINT_FLOAT SQ_PGM_RESOURCES_ES ; /* 0xA224 */ - union UINT_FLOAT SQ_PGM_START_FS ; /* 0xA225 */ - union UINT_FLOAT SQ_PGM_RESOURCES_FS ; /* 0xA229 */ - union UINT_FLOAT SQ_ESGS_RING_ITEMSIZE ; /* 0xA22A */ - union UINT_FLOAT SQ_GSVS_RING_ITEMSIZE ; /* 0xA22B */ - union UINT_FLOAT SQ_ESTMP_RING_ITEMSIZE ; /* 0xA22C */ - union UINT_FLOAT SQ_GSTMP_RING_ITEMSIZE ; /* 0xA22D */ - union UINT_FLOAT SQ_VSTMP_RING_ITEMSIZE ; /* 0xA22E */ - union UINT_FLOAT SQ_PSTMP_RING_ITEMSIZE ; /* 0xA22F */ - union UINT_FLOAT SQ_FBUF_RING_ITEMSIZE ; /* 0xA230 */ - union UINT_FLOAT SQ_REDUC_RING_ITEMSIZE ; /* 0xA231 */ - union UINT_FLOAT SQ_GS_VERT_ITEMSIZE ; /* 0xA232 */ - union UINT_FLOAT SQ_PGM_CF_OFFSET_PS ; /* 0xA233 */ - union UINT_FLOAT SQ_PGM_CF_OFFSET_VS ; /* 0xA234 */ - union UINT_FLOAT SQ_PGM_CF_OFFSET_GS ; /* 0xA235 */ - union UINT_FLOAT SQ_PGM_CF_OFFSET_ES ; /* 0xA236 */ - union UINT_FLOAT SQ_PGM_CF_OFFSET_FS ; /* 0xA237 */ - - union UINT_FLOAT PA_SU_POINT_SIZE ; /* 0xA280 */ - union UINT_FLOAT PA_SU_POINT_MINMAX ; /* 0xA281 */ - union UINT_FLOAT PA_SU_LINE_CNTL ; /* 0xA282 */ - union UINT_FLOAT PA_SC_LINE_STIPPLE ; /* 0xA283 */ - union UINT_FLOAT VGT_OUTPUT_PATH_CNTL ; /* 0xA284 */ - - union UINT_FLOAT VGT_GS_MODE ; /* 0xA290 */ - - union UINT_FLOAT PA_SC_MPASS_PS_CNTL ; /* 0xA292 */ - union UINT_FLOAT PA_SC_MODE_CNTL ; /* 0xA293 */ - - union UINT_FLOAT VGT_PRIMITIVEID_EN ; /* 0xA2A1 */ - union UINT_FLOAT VGT_DMA_NUM_INSTANCES ; /* 0xA2A2 */ - - union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_EN; /* 0xA2A5 */ - - union UINT_FLOAT VGT_INSTANCE_STEP_RATE_0 ; /* 0xA2A8 */ - union UINT_FLOAT VGT_INSTANCE_STEP_RATE_1 ; /* 0xA2A9 */ - - union UINT_FLOAT VGT_STRMOUT_EN ; /* 0xA2AC */ - union UINT_FLOAT VGT_REUSE_OFF ; /* 0xA2AD */ - - union UINT_FLOAT PA_SC_LINE_CNTL ; /* 0xA300 */ - union UINT_FLOAT PA_SC_AA_CONFIG ; /* 0xA301 */ - union UINT_FLOAT PA_SU_VTX_CNTL ; /* 0xA302 */ - union UINT_FLOAT PA_CL_GB_VERT_CLIP_ADJ ; /* 0xA303 */ - union UINT_FLOAT PA_CL_GB_VERT_DISC_ADJ ; /* 0xA304 */ - union UINT_FLOAT PA_CL_GB_HORZ_CLIP_ADJ ; /* 0xA305 */ - union UINT_FLOAT PA_CL_GB_HORZ_DISC_ADJ ; /* 0xA306 */ - union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_MCTX ; /* 0xA307 */ - union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX; /* 0xA308 */ - - union UINT_FLOAT CB_CLRCMP_CONTROL ; /* 0xA30C */ - union UINT_FLOAT CB_CLRCMP_SRC ; /* 0xA30D */ - union UINT_FLOAT CB_CLRCMP_DST ; /* 0xA30E */ - union UINT_FLOAT CB_CLRCMP_MSK ; /* 0xA30F */ - - union UINT_FLOAT PA_SC_AA_MASK ; /* 0xA312 */ - - union UINT_FLOAT DB_RENDER_CONTROL ; /* 0xA343 */ - union UINT_FLOAT DB_RENDER_OVERRIDE ; /* 0xA344 */ - - union UINT_FLOAT DB_HTILE_SURFACE ; /* 0xA349 */ - - union UINT_FLOAT DB_ALPHA_TO_MASK ; /* 0xA351 */ - - union UINT_FLOAT PA_SU_POLY_OFFSET_DB_FMT_CNTL; /* 0xA37E */ - union UINT_FLOAT PA_SU_POLY_OFFSET_CLAMP ; /* 0xA37F */ - union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_SCALE; /* 0xA380 */ - union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_OFFSET; /* 0xA381 */ - union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_SCALE; /* 0xA382 */ - union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_OFFSET; /* 0xA383 */ - - ContextState * pStateList; - - R700_TEXTURE_STATES texture_states; + union UINT_FLOAT SPI_VS_OUT_CONFIG ; /* 0xA1B1 */ + union UINT_FLOAT SPI_THREAD_GROUPING ; /* 0xA1B2 */ + union UINT_FLOAT SPI_PS_IN_CONTROL_0 ; /* 0xA1B3 */ + union UINT_FLOAT SPI_PS_IN_CONTROL_1 ; /* 0xA1B4 */ + union UINT_FLOAT SPI_INTERP_CONTROL_0 ; /* 0xA1B5 */ + union UINT_FLOAT SPI_INPUT_Z ; /* 0xA1B6 */ + union UINT_FLOAT SPI_FOG_CNTL ; /* 0xA1B7 */ + union UINT_FLOAT SQ_VTX_SEMANTIC[R700_MAX_SHADER_EXPORTS]; + union UINT_FLOAT SPI_PS_INPUT_CNTL[R700_MAX_SHADER_EXPORTS]; + + // shaders + PS_STATE_STRUCT ps; + VS_STATE_STRUCT vs; + GS_STATE_STRUCT gs; + ES_STATE_STRUCT es; + PS_STATE_STRUCT fs; + + // SQ + union UINT_FLOAT SQ_ESGS_RING_ITEMSIZE ; /* 0xA22A */ + union UINT_FLOAT SQ_GSVS_RING_ITEMSIZE ; /* 0xA22B */ + union UINT_FLOAT SQ_ESTMP_RING_ITEMSIZE ; /* 0xA22C */ + union UINT_FLOAT SQ_GSTMP_RING_ITEMSIZE ; /* 0xA22D */ + union UINT_FLOAT SQ_VSTMP_RING_ITEMSIZE ; /* 0xA22E */ + union UINT_FLOAT SQ_PSTMP_RING_ITEMSIZE ; /* 0xA22F */ + union UINT_FLOAT SQ_FBUF_RING_ITEMSIZE ; /* 0xA230 */ + union UINT_FLOAT SQ_REDUC_RING_ITEMSIZE ; /* 0xA231 */ + union UINT_FLOAT SQ_GS_VERT_ITEMSIZE ; /* 0xA232 */ + + ContextState* pStateList; + + R700_TEXTURE_STATES texture_states; + + GLboolean bEnablePerspective; - GLboolean bEnablePerspective; - } R700_CHIP_CONTEXT; #endif /* _R700_CHIP_H_ */ diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index cebb82d853..0eea2567d5 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -293,7 +293,7 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) (context->chipobj.MemUse)(context, fp->shadercode.buf->id); */ - r700->SQ_PGM_START_PS.u32All = 0; /* set from buffer obj */ + r700->ps.SQ_PGM_START_PS.u32All = 0; /* set from buffer obj */ unNumOfReg = fp->r700Shader.nRegs + 1; @@ -301,17 +301,17 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) ui = ui ? unNumOfReg : ui; - SETfield(r700->SQ_PGM_RESOURCES_PS.u32All, ui, NUM_GPRS_shift, NUM_GPRS_mask); + SETfield(r700->ps.SQ_PGM_RESOURCES_PS.u32All, ui, NUM_GPRS_shift, NUM_GPRS_mask); - CLEARbit(r700->SQ_PGM_RESOURCES_PS.u32All, UNCACHED_FIRST_INST_bit); + CLEARbit(r700->ps.SQ_PGM_RESOURCES_PS.u32All, UNCACHED_FIRST_INST_bit); if(fp->r700Shader.uStackSize) /* we don't use branch for now, it should be zero. */ { - SETfield(r700->SQ_PGM_RESOURCES_PS.u32All, fp->r700Shader.uStackSize, + SETfield(r700->ps.SQ_PGM_RESOURCES_PS.u32All, fp->r700Shader.uStackSize, STACK_SIZE_shift, STACK_SIZE_mask); } - SETfield(r700->SQ_PGM_EXPORTS_PS.u32All, fp->r700Shader.exportMode, + SETfield(r700->ps.SQ_PGM_EXPORTS_PS.u32All, fp->r700Shader.exportMode, EXPORT_MODE_shift, EXPORT_MODE_mask); if(fp->r700Shader.killIsUsed) diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 3a4328fdfe..2c67006217 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -112,17 +112,17 @@ static GLboolean r700SetupShaders(GLcontext * ctx) GLuint exportCount; - r700->SQ_PGM_RESOURCES_PS.u32All = 0; - r700->SQ_PGM_RESOURCES_VS.u32All = 0; + r700->ps.SQ_PGM_RESOURCES_PS.u32All = 0; + r700->vs.SQ_PGM_RESOURCES_VS.u32All = 0; - SETbit(r700->SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); - SETbit(r700->SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); + SETbit(r700->ps.SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); + SETbit(r700->vs.SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); r700SetupVertexProgram(ctx); r700SetupFragmentProgram(ctx); - exportCount = (r700->SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift); + exportCount = (r700->ps.SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift); r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1; return GL_TRUE; @@ -259,7 +259,7 @@ static GLboolean r700RunRender(GLcontext * ctx, r700UpdateShaders(ctx); r700SetScissor(context); - r700SetRenderTarget(context); + r700SetRenderTarget(context, 0); r700SetDepthTarget(context); if(r700SetupStreams(ctx)) @@ -287,15 +287,16 @@ static GLboolean r700RunRender(GLcontext * ctx, r700SetupShaders(ctx); - /* set a valid base address to make the command checker happy */ - r700->SQ_PGM_START_FS.u32All = r700->SQ_PGM_START_PS.u32All; - r700->SQ_PGM_START_ES.u32All = r700->SQ_PGM_START_PS.u32All; - r700->SQ_PGM_START_GS.u32All = r700->SQ_PGM_START_PS.u32All; + r700SendPSState(context); + r700SendVSState(context); /* flush vtx */ //r700SyncSurf(context); /* */ r700SendContextStates(context); + r700SendViewportState(context); + r700SendRenderTargetState(context, 0); + /* richard test code */ for (i = 0; i < vb->PrimitiveCount; i++) diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 3556d6811c..17e99bf5e1 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -522,7 +522,7 @@ static void r700StencilOpSeparate(GLcontext * ctx, GLenum face, { } -static void r700UpdateWindow(GLcontext * ctx) //-------------------- +static void r700UpdateWindow(GLcontext * ctx, int id) //-------------------- { context_t *context = R700_CONTEXT(ctx); @@ -552,14 +552,16 @@ static void r700UpdateWindow(GLcontext * ctx) //-------------------- /* TODO : Need DMA flush as well. */ - r700->PA_CL_VPORT_XSCALE.f32All = sx; - r700->PA_CL_VPORT_XOFFSET.f32All = tx; + r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx; + r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx; - r700->PA_CL_VPORT_YSCALE.f32All = sy; - r700->PA_CL_VPORT_YOFFSET.f32All = ty; + r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy; + r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty; - r700->PA_CL_VPORT_ZSCALE.f32All = sz; - r700->PA_CL_VPORT_ZOFFSET.f32All = tz; + r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz; + r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz; + + r700->viewport[id].enabled = GL_TRUE; } @@ -569,14 +571,14 @@ static void r700Viewport(GLcontext * ctx, GLsizei width, GLsizei height) //-------------------- { - r700UpdateWindow(ctx); + r700UpdateWindow(ctx, 0); radeon_viewport(ctx, x, y, width, height); } static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //------------- { - r700UpdateWindow(ctx); + r700UpdateWindow(ctx, 0); } static void r700PointSize(GLcontext * ctx, GLfloat size) //------------------- @@ -608,6 +610,7 @@ void r700SetScissor(context_t *context) //--------------- { R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); unsigned x1, y1, x2, y2; + int id = 0; struct radeon_renderbuffer *rrb; rrb = radeon_get_colorbuffer(&context->radeon); @@ -670,28 +673,22 @@ void r700SetScissor(context_t *context) //--------------- SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2, PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask); - SETbit(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit); - SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, x1, + SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit); + SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1, PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, y1, + SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, x2, + SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2, PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, y2, + SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask); - SETbit(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, WINDOW_OFFSET_DISABLE_bit); - SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, x1, - PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, y1, - PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, x2, - PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, y2, - PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask); + r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All = 0; + r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000; + r700->viewport[id].enabled = GL_TRUE; } -void r700SetRenderTarget(context_t *context) +void r700SetRenderTarget(context_t *context, int id) { R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); @@ -699,7 +696,7 @@ void r700SetRenderTarget(context_t *context) unsigned int nPitchInPixel; /* screen/window/view */ - SETfield(r700->CB_TARGET_MASK.u32All, 0xF, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask); + SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask); rrb = radeon_get_colorbuffer(&context->radeon); if (!rrb || !rrb->bo) { @@ -708,34 +705,38 @@ void r700SetRenderTarget(context_t *context) } /* color buffer */ - r700->CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset; + r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset; nPitchInPixel = rrb->pitch/rrb->cpp; - SETfield(r700->CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1, + SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1, PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); - SETfield(r700->CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1, + SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1, SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); - r700->CB_COLOR0_BASE.u32All = 0; - SETfield(r700->CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask); - SETfield(r700->CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL, + r700->render_target[id].CB_COLOR0_BASE.u32All = 0; + SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask); + SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL, CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask); if(4 == rrb->cpp) { - SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_8_8_8_8, + SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8, CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask); - SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask); + SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask); } else { - SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_5_6_5, + SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5, CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask); - SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT_REV, + SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV, COMP_SWAP_shift, COMP_SWAP_mask); } - SETbit(r700->CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit); - SETbit(r700->CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit); - SETfield(r700->CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask); + SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit); + SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit); + SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask); + + CLEARfield(r700->render_target[id].CB_BLEND0_CONTROL.u32All, COLOR_SRCBLEND_mask); /* no dst blend */ + CLEARfield(r700->render_target[id].CB_BLEND0_CONTROL.u32All, ALPHA_SRCBLEND_mask); /* no dst blend */ + r700->render_target[id].enabled = GL_TRUE; } void r700SetDepthTarget(context_t *context) @@ -746,7 +747,7 @@ void r700SetDepthTarget(context_t *context) unsigned int nPitchInPixel; /* depth buf */ - r700->DB_DEPTH_SIZE.u32All = 0; + r700->DB_DEPTH_SIZE.u32All = 0; r700->DB_DEPTH_BASE.u32All = 0; r700->DB_DEPTH_INFO.u32All = 0; @@ -819,21 +820,19 @@ void r700InitState(GLcontext * ctx) //------------------- r700->VGT_DMA_NUM_INSTANCES.u32All = 1; /* not alpha blend */ - CLEARfield(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_FUNC_mask); + CLEARfield(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_FUNC_mask); CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit); /* defualt shader connections. */ r700->SPI_VS_OUT_ID_0.u32All = 0x03020100; r700->SPI_VS_OUT_ID_1.u32All = 0x07060504; - r700->SPI_PS_INPUT_CNTL_0.u32All = 0x00000800; - r700->SPI_PS_INPUT_CNTL_1.u32All = 0x00000801; - r700->SPI_PS_INPUT_CNTL_2.u32All = 0x00000802; + r700->SPI_PS_INPUT_CNTL[0].u32All = 0x00000800; + r700->SPI_PS_INPUT_CNTL[1].u32All = 0x00000801; + r700->SPI_PS_INPUT_CNTL[2].u32All = 0x00000802; SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask); CLEARbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit); - CLEARfield(r700->CB_BLEND0_CONTROL.u32All, COLOR_SRCBLEND_mask); /* no dst blend */ - CLEARfield(r700->CB_BLEND0_CONTROL.u32All, ALPHA_SRCBLEND_mask); /* no dst blend */ r700->DB_SHADER_CONTROL.u32All = 0; SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit); @@ -897,7 +896,7 @@ void r700InitState(GLcontext * ctx) //------------------- r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000; r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000; - /* Disble color compares */ + /* Disable color compares */ SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS, CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask); SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS, @@ -924,32 +923,6 @@ void r700InitState(GLcontext * ctx) //------------------- r700->SX_MISC.u32All = 0; - /* depth buf */ - r700->DB_DEPTH_SIZE.u32All = 0; - r700->DB_DEPTH_BASE.u32All = 0; - r700->DB_DEPTH_INFO.u32All = 0; - r700->DB_DEPTH_CONTROL.u32All = 0; - r700->DB_DEPTH_CLEAR.u32All = 0x3F800000; - r700->DB_DEPTH_VIEW.u32All = 0; - r700->DB_RENDER_CONTROL.u32All = 0; - r700->DB_RENDER_OVERRIDE.u32All = 0; - SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask); - SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask); - SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask); - - /* color buffer */ - r700->CB_COLOR0_SIZE.u32All = 0; - r700->CB_COLOR0_BASE.u32All = 0; - r700->CB_COLOR0_INFO.u32All = 0; - SETbit(r700->CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit); - SETbit(r700->CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit); - SETfield(r700->CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask); - r700->CB_COLOR0_VIEW.u32All = 0; - r700->CB_COLOR0_TILE.u32All = 0; - r700->CB_COLOR0_FRAG.u32All = 0; - r700->CB_COLOR0_MASK.u32All = 0; - - r700->PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000; } void r700InitStateFuncs(struct dd_function_table *functions) //----------------- diff --git a/src/mesa/drivers/dri/r600/r700_state.h b/src/mesa/drivers/dri/r600/r700_state.h index a75c7f0188..87f0903b67 100644 --- a/src/mesa/drivers/dri/r600/r700_state.h +++ b/src/mesa/drivers/dri/r600/r700_state.h @@ -42,7 +42,7 @@ extern void r700UpdateDrawBuffer (GLcontext * ctx); extern void r700InitState (GLcontext * ctx); extern void r700InitStateFuncs (struct dd_function_table *functions); -extern void r700SetRenderTarget(context_t *context); +extern void r700SetRenderTarget(context_t *context, int id); extern void r700SetDefaultStates(context_t * context); #endif /* _R600_SCREEN_H */ diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index ecb72549fe..b83e6f16bc 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -372,14 +372,14 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) (context->chipobj.MemUse)(context, vp->shadercode.buf->id); */ - r700->SQ_PGM_START_VS.u32All = 0; /* set from buffer object. */ + r700->vs.SQ_PGM_START_VS.u32All = 0; /* set from buffer object. */ - SETfield(r700->SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.nRegs + 1, + SETfield(r700->vs.SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.nRegs + 1, NUM_GPRS_shift, NUM_GPRS_mask); if(vp->r700Shader.uStackSize) /* we don't use branch for now, it should be zero. */ { - SETfield(r700->SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.uStackSize, + SETfield(r700->vs.SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.uStackSize, STACK_SIZE_shift, STACK_SIZE_mask); } -- cgit v1.2.3 From 530e3e389dfb3957b872d08906dcea830407b0c2 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 9 Jun 2009 18:20:57 -0400 Subject: Pull in additional state setup from the DDX --- src/mesa/drivers/dri/r600/r700_chip.c | 50 ++++++ src/mesa/drivers/dri/r600/r700_chip.h | 43 +++++ src/mesa/drivers/dri/r600/r700_chipoffset.h | 11 +- src/mesa/drivers/dri/r600/r700_render.c | 2 + src/mesa/drivers/dri/r600/r700_state.c | 265 +++++++++++++++++++++++++++- 5 files changed, 366 insertions(+), 5 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 7fd557ca8e..8e7787eeef 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -57,6 +57,13 @@ GLboolean r700InitChipObject(context_t *context) r700->pStateList = (ContextState*) MALLOC (sizeof(ContextState)*sizeof(R700_CHIP_CONTEXT)/sizeof(unsigned int)); pStateListWork = r700->pStateList; + // misc + LINK_STATES(TA_CNTL_AUX); + LINK_STATES(VC_ENHANCE); + LINK_STATES(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ); + LINK_STATES(DB_DEBUG); + LINK_STATES(DB_WATERMARKS); + // DB LINK_STATES(DB_DEPTH_SIZE); LINK_STATES(DB_DEPTH_VIEW); @@ -122,18 +129,26 @@ GLboolean r700InitChipObject(context_t *context) LINK_STATES(PA_CL_GB_HORZ_DISC_ADJ); // CB + LINK_STATES(CB_CLEAR_RED_R6XX); + LINK_STATES(CB_CLEAR_GREEN_R6XX); + LINK_STATES(CB_CLEAR_BLUE_R6XX); + LINK_STATES(CB_CLEAR_ALPHA_R6XX); LINK_STATES(CB_TARGET_MASK); LINK_STATES(CB_SHADER_MASK); LINK_STATES(CB_BLEND_RED); LINK_STATES(CB_BLEND_GREEN); LINK_STATES(CB_BLEND_BLUE); LINK_STATES(CB_BLEND_ALPHA); + LINK_STATES(CB_FOG_RED_R6XX); + LINK_STATES(CB_FOG_GREEN_R6XX); + LINK_STATES(CB_FOG_BLUE_R6XX); LINK_STATES(CB_SHADER_CONTROL); LINK_STATES(CB_COLOR_CONTROL); LINK_STATES(CB_CLRCMP_CONTROL); LINK_STATES(CB_CLRCMP_SRC); LINK_STATES(CB_CLRCMP_DST); LINK_STATES(CB_CLRCMP_MSK); + LINK_STATES(CB_BLEND_CONTROL); // SX LINK_STATES(SX_MISC); @@ -145,6 +160,17 @@ GLboolean r700InitChipObject(context_t *context) LINK_STATES(VGT_INDX_OFFSET); LINK_STATES(VGT_MULTI_PRIM_IB_RESET_INDX); LINK_STATES(VGT_OUTPUT_PATH_CNTL); + LINK_STATES(VGT_HOS_CNTL); + LINK_STATES(VGT_HOS_MAX_TESS_LEVEL); + LINK_STATES(VGT_HOS_MIN_TESS_LEVEL); + LINK_STATES(VGT_HOS_REUSE_DEPTH); + LINK_STATES(VGT_GROUP_PRIM_TYPE); + LINK_STATES(VGT_GROUP_FIRST_DECR); + LINK_STATES(VGT_GROUP_DECR); + LINK_STATES(VGT_GROUP_VECT_0_CNTL); + LINK_STATES(VGT_GROUP_VECT_1_CNTL); + LINK_STATES(VGT_GROUP_VECT_0_FMT_CNTL); + LINK_STATES(VGT_GROUP_VECT_1_FMT_CNTL); LINK_STATES(VGT_GS_MODE); LINK_STATES(VGT_PRIMITIVEID_EN); LINK_STATES(VGT_DMA_NUM_INSTANCES); @@ -153,6 +179,8 @@ GLboolean r700InitChipObject(context_t *context) LINK_STATES(VGT_INSTANCE_STEP_RATE_1); LINK_STATES(VGT_STRMOUT_EN); LINK_STATES(VGT_REUSE_OFF); + LINK_STATES(VGT_VTX_CNT_EN); + LINK_STATES(VGT_STRMOUT_BUFFER_EN); // SPI LINK_STATES(SPI_VS_OUT_ID_0); @@ -172,6 +200,8 @@ GLboolean r700InitChipObject(context_t *context) LINK_STATES(SPI_INTERP_CONTROL_0); LINK_STATES(SPI_INPUT_Z); LINK_STATES(SPI_FOG_CNTL); + LINK_STATES(SPI_FOG_FUNC_SCALE); + LINK_STATES(SPI_FOG_FUNC_BIAS); // SQ LINK_STATES(SQ_ESGS_RING_ITEMSIZE); @@ -570,3 +600,23 @@ GLboolean r700SendViewportState(context_t *context, int id) return GL_TRUE; } + +GLboolean r700SendSQConfig(context_t *context) +{ + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + BATCH_LOCALS(&context->radeon); + + BEGIN_BATCH_NO_AUTOSTATE(8); + R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6); + R600_OUT_BATCH(r700->sq_config.SQ_CONFIG.u32All); + R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All); + R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All); + R600_OUT_BATCH(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All); + R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All); + R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All); + END_BATCH(); + COMMIT_BATCH(); + + return GL_TRUE; +} + diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h index 2129c0bdf4..f135b5e939 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.h +++ b/src/mesa/drivers/dri/r600/r700_chip.h @@ -247,6 +247,16 @@ typedef struct _FS_STATE_STRUCT union UINT_FLOAT SQ_PGM_CF_OFFSET_FS ; /* 0xA237 */ } FS_STATE_STRUCT; +typedef struct _SQ_CONFIG_STRUCT +{ + union UINT_FLOAT SQ_CONFIG ; /* 0x2300 */ + union UINT_FLOAT SQ_GPR_RESOURCE_MGMT_1 ; /* 0x2301 */ + union UINT_FLOAT SQ_GPR_RESOURCE_MGMT_2 ; /* 0x2302 */ + union UINT_FLOAT SQ_THREAD_RESOURCE_MGMT ; /* 0x2303 */ + union UINT_FLOAT SQ_STACK_RESOURCE_MGMT_1 ; /* 0x2304 */ + union UINT_FLOAT SQ_STACK_RESOURCE_MGMT_2 ; /* 0x2305 */ +} SQ_CONFIG_STRUCT; + typedef struct ContextState { unsigned int * puiValue; @@ -256,6 +266,13 @@ typedef struct ContextState typedef struct _R700_CHIP_CONTEXT { + // misc + union UINT_FLOAT TA_CNTL_AUX ; /* 0x2542 */ + union UINT_FLOAT VC_ENHANCE ; /* 0x25C5 */ + union UINT_FLOAT SQ_DYN_GPR_CNTL_PS_FLUSH_REQ; /* 0x2363 */ + union UINT_FLOAT DB_DEBUG ; /* 0x260C */ + union UINT_FLOAT DB_WATERMARKS ; /* 0x260E */ + // DB union UINT_FLOAT DB_DEPTH_SIZE ; /* 0xA000 */ union UINT_FLOAT DB_DEPTH_VIEW ; /* 0xA001 */ @@ -325,18 +342,26 @@ typedef struct _R700_CHIP_CONTEXT UCP_STATE_STRUCT ucp[R700_MAX_UCP]; // CB + union UINT_FLOAT CB_CLEAR_RED_R6XX ; /* 0xA048 */ + union UINT_FLOAT CB_CLEAR_GREEN_R6XX ; /* 0xA049 */ + union UINT_FLOAT CB_CLEAR_BLUE_R6XX ; /* 0xA04A */ + union UINT_FLOAT CB_CLEAR_ALPHA_R6XX ; /* 0xA04B */ union UINT_FLOAT CB_TARGET_MASK ; /* 0xA08E */ union UINT_FLOAT CB_SHADER_MASK ; /* 0xA08F */ union UINT_FLOAT CB_BLEND_RED ; /* 0xA105 */ union UINT_FLOAT CB_BLEND_GREEN ; /* 0xA106 */ union UINT_FLOAT CB_BLEND_BLUE ; /* 0xA107 */ union UINT_FLOAT CB_BLEND_ALPHA ; /* 0xA108 */ + union UINT_FLOAT CB_FOG_RED_R6XX ; /* 0xA109 */ + union UINT_FLOAT CB_FOG_GREEN_R6XX ; /* 0xA10A */ + union UINT_FLOAT CB_FOG_BLUE_R6XX ; /* 0xA10B */ union UINT_FLOAT CB_SHADER_CONTROL ; /* 0xA1E8 */ union UINT_FLOAT CB_COLOR_CONTROL ; /* 0xA202 */ union UINT_FLOAT CB_CLRCMP_CONTROL ; /* 0xA30C */ union UINT_FLOAT CB_CLRCMP_SRC ; /* 0xA30D */ union UINT_FLOAT CB_CLRCMP_DST ; /* 0xA30E */ union UINT_FLOAT CB_CLRCMP_MSK ; /* 0xA30F */ + union UINT_FLOAT CB_BLEND_CONTROL ; /* 0xABD0 */ RENDER_TARGET_STATE_STRUCT render_target[R700_MAX_RENDER_TARGETS]; // SX @@ -349,6 +374,17 @@ typedef struct _R700_CHIP_CONTEXT union UINT_FLOAT VGT_INDX_OFFSET ; /* 0xA102 */ union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_INDX; /* 0xA103 */ union UINT_FLOAT VGT_OUTPUT_PATH_CNTL ; /* 0xA284 */ + union UINT_FLOAT VGT_HOS_CNTL ; /* 0xA285 */ + union UINT_FLOAT VGT_HOS_MAX_TESS_LEVEL ; /* 0xA286 */ + union UINT_FLOAT VGT_HOS_MIN_TESS_LEVEL ; /* 0xA287 */ + union UINT_FLOAT VGT_HOS_REUSE_DEPTH ; /* 0xA288 */ + union UINT_FLOAT VGT_GROUP_PRIM_TYPE ; /* 0xA289 */ + union UINT_FLOAT VGT_GROUP_FIRST_DECR ; /* 0xA28A */ + union UINT_FLOAT VGT_GROUP_DECR ; /* 0xA28B */ + union UINT_FLOAT VGT_GROUP_VECT_0_CNTL ; /* 0xA28C */ + union UINT_FLOAT VGT_GROUP_VECT_1_CNTL ; /* 0xA28D */ + union UINT_FLOAT VGT_GROUP_VECT_0_FMT_CNTL ; /* 0xA28E */ + union UINT_FLOAT VGT_GROUP_VECT_1_FMT_CNTL ; /* 0xA28F */ union UINT_FLOAT VGT_GS_MODE ; /* 0xA290 */ union UINT_FLOAT VGT_PRIMITIVEID_EN ; /* 0xA2A1 */ union UINT_FLOAT VGT_DMA_NUM_INSTANCES ; /* 0xA2A2 */ @@ -357,6 +393,8 @@ typedef struct _R700_CHIP_CONTEXT union UINT_FLOAT VGT_INSTANCE_STEP_RATE_1 ; /* 0xA2A9 */ union UINT_FLOAT VGT_STRMOUT_EN ; /* 0xA2AC */ union UINT_FLOAT VGT_REUSE_OFF ; /* 0xA2AD */ + union UINT_FLOAT VGT_VTX_CNT_EN ; /* 0xA2AE */ + union UINT_FLOAT VGT_STRMOUT_BUFFER_EN ; /* 0xA2C8 */ // SPI union UINT_FLOAT SPI_VS_OUT_ID_0 ; /* 0xA185 */ @@ -376,6 +414,8 @@ typedef struct _R700_CHIP_CONTEXT union UINT_FLOAT SPI_INTERP_CONTROL_0 ; /* 0xA1B5 */ union UINT_FLOAT SPI_INPUT_Z ; /* 0xA1B6 */ union UINT_FLOAT SPI_FOG_CNTL ; /* 0xA1B7 */ + union UINT_FLOAT SPI_FOG_FUNC_SCALE ; /* 0xA1B8 */ + union UINT_FLOAT SPI_FOG_FUNC_BIAS ; /* 0xA1B9 */ union UINT_FLOAT SQ_VTX_SEMANTIC[R700_MAX_SHADER_EXPORTS]; union UINT_FLOAT SPI_PS_INPUT_CNTL[R700_MAX_SHADER_EXPORTS]; @@ -386,6 +426,9 @@ typedef struct _R700_CHIP_CONTEXT ES_STATE_STRUCT es; PS_STATE_STRUCT fs; + // SQ CONFIG + SQ_CONFIG_STRUCT sq_config; + // SQ union UINT_FLOAT SQ_ESGS_RING_ITEMSIZE ; /* 0xA22A */ union UINT_FLOAT SQ_GSVS_RING_ITEMSIZE ; /* 0xA22B */ diff --git a/src/mesa/drivers/dri/r600/r700_chipoffset.h b/src/mesa/drivers/dri/r600/r700_chipoffset.h index 9050b9a715..4d73fb99a7 100644 --- a/src/mesa/drivers/dri/r600/r700_chipoffset.h +++ b/src/mesa/drivers/dri/r600/r700_chipoffset.h @@ -51,6 +51,12 @@ #define mmCP_COHER_BASE 0x217E #define mmCP_COHER_STATUS 0x217F +#define mmTA_CNTL_AUX 0x2542 +#define mmVC_ENHANCE 0x25C5 +#define mmSQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x2363 +#define mmDB_DEBUG 0x260C +#define mmDB_WATERMARKS 0x260E + #define mmPA_CL_VPORT_XSCALE 0xA10F #define mmPA_CL_VPORT_XOFFSET 0xA110 #define mmPA_CL_VPORT_YSCALE 0xA111 @@ -568,7 +574,6 @@ #define mmSPI_FOG_FUNC_BIAS 0xA1B9 #define mmSX_MISC 0xA0D4 - #define mmSX_ALPHA_TEST_CONTROL 0xA104 #define mmSX_ALPHA_REF 0xA10E @@ -592,6 +597,10 @@ #define mmDB_DEPTH_CONTROL 0xA200 #define mmDB_ALPHA_TO_MASK 0xA351 +#define mmCB_CLEAR_RED_R6XX 0xA048 +#define mmCB_CLEAR_GREEN_R6XX 0xA049 +#define mmCB_CLEAR_BLUE_R6XX 0xA04A +#define mmCB_CLEAR_ALPHA_R6XX 0xA04B #define mmCB_BLEND_RED 0xA105 #define mmCB_BLEND_GREEN 0xA106 #define mmCB_BLEND_BLUE 0xA107 diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 2c67006217..4693cfbd82 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -256,6 +256,8 @@ static GLboolean r700RunRender(GLcontext * ctx, r700SyncSurf(context); /* TODO : make it light. */ + r700SendSQConfig(context); + r700UpdateShaders(ctx); r700SetScissor(context); diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 17e99bf5e1..cf1383d5eb 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -630,9 +630,6 @@ void r700SetScissor(context_t *context) //--------------- y2 = rrb->height - 1; } - /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */ - r700->PA_SC_CLIPRECT_RULE.u32All = 0x0000FFFF; - /* window */ SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit); SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1, @@ -756,10 +753,18 @@ void r700SetDepthTarget(context_t *context) r700->DB_DEPTH_VIEW.u32All = 0; r700->DB_RENDER_CONTROL.u32All = 0; r700->DB_RENDER_OVERRIDE.u32All = 0; + if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) + SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit); SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask); SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask); SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask); + r700->DB_ALPHA_TO_MASK.u32All = 0; + SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask); + SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask); + SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask); + SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask); + rrb = radeon_get_depthbuffer(&context->radeon); if (!rrb) return; @@ -796,6 +801,195 @@ void r700SetDepthTarget(context_t *context) /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */ } +static void r700InitSQConfig(GLcontext * ctx) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + int ps_prio; + int vs_prio; + int gs_prio; + int es_prio; + int num_ps_gprs; + int num_vs_gprs; + int num_gs_gprs; + int num_es_gprs; + int num_temp_gprs; + int num_ps_threads; + int num_vs_threads; + int num_gs_threads; + int num_es_threads; + int num_ps_stack_entries; + int num_vs_stack_entries; + int num_gs_stack_entries; + int num_es_stack_entries; + + // SQ + ps_prio = 0; + vs_prio = 1; + gs_prio = 2; + es_prio = 3; + switch (context->radeon.radeonScreen->chip_family) { + case CHIP_FAMILY_R600: + num_ps_gprs = 192; + num_vs_gprs = 56; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 136; + num_vs_threads = 48; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 128; + num_vs_stack_entries = 128; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + case CHIP_FAMILY_RV630: + case CHIP_FAMILY_RV635: + num_ps_gprs = 84; + num_vs_gprs = 36; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 144; + num_vs_threads = 40; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 40; + num_vs_stack_entries = 40; + num_gs_stack_entries = 32; + num_es_stack_entries = 16; + break; + case CHIP_FAMILY_RV610: + case CHIP_FAMILY_RV620: + case CHIP_FAMILY_RS780: + default: + num_ps_gprs = 84; + num_vs_gprs = 36; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 136; + num_vs_threads = 48; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 40; + num_vs_stack_entries = 40; + num_gs_stack_entries = 32; + num_es_stack_entries = 16; + break; + case CHIP_FAMILY_RV670: + num_ps_gprs = 144; + num_vs_gprs = 40; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 136; + num_vs_threads = 48; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 40; + num_vs_stack_entries = 40; + num_gs_stack_entries = 32; + num_es_stack_entries = 16; + break; + case CHIP_FAMILY_RV770: + num_ps_gprs = 192; + num_vs_gprs = 56; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 188; + num_vs_threads = 60; + num_gs_threads = 0; + num_es_threads = 0; + num_ps_stack_entries = 256; + num_vs_stack_entries = 256; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + case CHIP_FAMILY_RV730: + //case CHIP_FAMILY_RV740: + num_ps_gprs = 84; + num_vs_gprs = 36; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 188; + num_vs_threads = 60; + num_gs_threads = 0; + num_es_threads = 0; + num_ps_stack_entries = 128; + num_vs_stack_entries = 128; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + case CHIP_FAMILY_RV710: + num_ps_gprs = 192; + num_vs_gprs = 56; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 144; + num_vs_threads = 48; + num_gs_threads = 0; + num_es_threads = 0; + num_ps_stack_entries = 128; + num_vs_stack_entries = 128; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + } + + r700->sq_config.SQ_CONFIG.u32All = 0; + if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) || + (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) || + (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) || + (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710)) + CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit); + else + SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit); + SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit); + SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit); + SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask); + SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask); + SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask); + SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask); + + r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0; + SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask); + SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask); + SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs, + NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask); + + r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0; + SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask); + SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask); + + r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0; + SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads, + NUM_PS_THREADS_shift, NUM_PS_THREADS_mask); + SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads, + NUM_VS_THREADS_shift, NUM_VS_THREADS_mask); + SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads, + NUM_GS_THREADS_shift, NUM_GS_THREADS_mask); + SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads, + NUM_ES_THREADS_shift, NUM_ES_THREADS_mask); + + r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0; + SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries, + NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask); + SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries, + NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask); + + r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0; + SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries, + NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask); + SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries, + NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask); + +} + /** * Calculate initial hardware state and register state functions. * Assumes that the command buffer and state atoms have been @@ -807,6 +1001,25 @@ void r700InitState(GLcontext * ctx) //------------------- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + r700->TA_CNTL_AUX.u32All = 0; + SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask); + r700->VC_ENHANCE.u32All = 0; + r700->DB_WATERMARKS.u32All = 0; + SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask); + SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask); + SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask); + SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask); + r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0; + if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) { + SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask); + r700->DB_DEBUG.u32All = 0x82000000; + SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask); + } else { + SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask); + SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask); + SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit); + } + /* Turn off vgt reuse */ r700->VGT_REUSE_OFF.u32All = 0; SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit); @@ -823,7 +1036,7 @@ void r700InitState(GLcontext * ctx) //------------------- CLEARfield(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_FUNC_mask); CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit); - /* defualt shader connections. */ + /* default shader connections. */ r700->SPI_VS_OUT_ID_0.u32All = 0x03020100; r700->SPI_VS_OUT_ID_1.u32All = 0x07060504; @@ -831,6 +1044,10 @@ void r700InitState(GLcontext * ctx) //------------------- r700->SPI_PS_INPUT_CNTL[1].u32All = 0x00000801; r700->SPI_PS_INPUT_CNTL[2].u32All = 0x00000802; + r700->SPI_THREAD_GROUPING.u32All = 0; + if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770) + SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask); + SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask); CLEARbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit); @@ -853,6 +1070,25 @@ void r700InitState(GLcontext * ctx) //------------------- ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->height, PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask); + /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */ + r700->PA_SC_CLIPRECT_RULE.u32All = 0; + SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask); + + if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) + r700->PA_SC_EDGERULE.u32All = 0; + else + r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA; + + if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) { + r700->PA_SC_MODE_CNTL.u32All = 0; + SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit); + SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit); + } else { + r700->PA_SC_MODE_CNTL.u32All = 0x00500000; + SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit); + SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit); + } + /* Do scale XY and Z by 1/W0. */ r700->bEnablePerspective = GL_TRUE; CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit); @@ -878,6 +1114,10 @@ void r700InitState(GLcontext * ctx) //------------------- /* Set up line control */ SETfield(r700->PA_SU_LINE_CNTL.u32All, 0x8, PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask); + SETfield(r700->PA_SU_LINE_CNTL.u32All, 0x2, + PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask); + SETfield(r700->PA_SU_LINE_CNTL.u32All, 0x5, + QUANT_MODE_shift, QUANT_MODE_mask); r700->PA_SC_LINE_CNTL.u32All = 0; CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit); @@ -896,6 +1136,22 @@ void r700InitState(GLcontext * ctx) //------------------- r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000; r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000; + /* CB */ + r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only + r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only + r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only + r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only + r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only + r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only + r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only + + r700->CB_BLEND_RED.u32All = 0; + r700->CB_BLEND_GREEN.u32All = 0; + r700->CB_BLEND_BLUE.u32All = 0; + r700->CB_BLEND_ALPHA.u32All = 0; + + r700->CB_BLEND_CONTROL.u32All = 0; + /* Disable color compares */ SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS, CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask); @@ -923,6 +1179,7 @@ void r700InitState(GLcontext * ctx) //------------------- r700->SX_MISC.u32All = 0; + r700InitSQConfig(ctx); } void r700InitStateFuncs(struct dd_function_table *functions) //----------------- -- cgit v1.2.3 From 2f6451042d6c6e69fe1ea4f87814ebf2f982b034 Mon Sep 17 00:00:00 2001 From: Cooper Yuan Date: Mon, 22 Jun 2009 14:33:18 +0800 Subject: Pass viewport id to r700SendViewportState function, otherwise the radom value may beyond R700_MAX_VIEWPORTS --- src/mesa/drivers/dri/r600/r700_render.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 4693cfbd82..e46b21c85c 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -296,7 +296,7 @@ static GLboolean r700RunRender(GLcontext * ctx, //r700SyncSurf(context); /* */ r700SendContextStates(context); - r700SendViewportState(context); + r700SendViewportState(context, 0); r700SendRenderTargetState(context, 0); -- cgit v1.2.3 From d1bc9a29b9fe9400681221b38639e12536dd6dbf Mon Sep 17 00:00:00 2001 From: Cooper Yuan Date: Fri, 26 Jun 2009 17:04:53 +0800 Subject: Fix viewport issue --- src/mesa/drivers/dri/r600/r700_render.c | 4 ++++ src/mesa/drivers/dri/r600/r700_state.c | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index e46b21c85c..b496543e1d 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -44,6 +44,7 @@ #include "tnl/t_vertex.h" #include "tnl/t_pipeline.h" +#include "radeon_lock.h" #include "r600_context.h" #include "r600_cmdbuf.h" @@ -295,6 +296,9 @@ static GLboolean r700RunRender(GLcontext * ctx, /* flush vtx */ //r700SyncSurf(context); /* */ + LOCK_HARDWARE( &context->radeon ); + UNLOCK_HARDWARE( &context->radeon ); + r700SendContextStates(context); r700SendViewportState(context, 0); r700SendRenderTargetState(context, 0); diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index b22e1765a3..a98ffedba0 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -562,6 +562,8 @@ static void r700UpdateWindow(GLcontext * ctx, int id) //-------------------- r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz; r700->viewport[id].enabled = GL_TRUE; + + r700SetScissor(context); } @@ -615,7 +617,6 @@ void r700SetScissor(context_t *context) //--------------- rrb = radeon_get_colorbuffer(&context->radeon); if (!rrb || !rrb->bo) { - fprintf(stderr, "no rrb\n"); return; } if (context->radeon.state.scissor.enabled) { -- cgit v1.2.3 From d10006e67fb070f846213ef38e07df21699df5a1 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 30 Jun 2009 18:40:48 -0400 Subject: R6xx/r7xx: fix locking for clear this allows redbook hello to render correctly mostly. --- src/mesa/drivers/dri/r600/r700_clear.c | 3 +-- src/mesa/drivers/dri/r600/r700_render.c | 4 ---- 2 files changed, 1 insertion(+), 6 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c index b04441da28..7696795676 100644 --- a/src/mesa/drivers/dri/r600/r700_clear.c +++ b/src/mesa/drivers/dri/r600/r700_clear.c @@ -32,6 +32,7 @@ #include "main/mtypes.h" #include "main/enums.h" +#include "radeon_lock.h" #include "r600_context.h" #include "r700_shaderinst.h" @@ -68,14 +69,12 @@ void r700Clear(GLcontext * ctx, GLbitfield mask) return; } -#if 0 if (!context->radeon.radeonScreen->driScreen->dri2.enabled) { LOCK_HARDWARE(&context->radeon); UNLOCK_HARDWARE(&context->radeon); if (dPriv->numClipRects == 0) return; } -#endif R600_NEWPRIM(context); diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index b496543e1d..e46b21c85c 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -44,7 +44,6 @@ #include "tnl/t_vertex.h" #include "tnl/t_pipeline.h" -#include "radeon_lock.h" #include "r600_context.h" #include "r600_cmdbuf.h" @@ -296,9 +295,6 @@ static GLboolean r700RunRender(GLcontext * ctx, /* flush vtx */ //r700SyncSurf(context); /* */ - LOCK_HARDWARE( &context->radeon ); - UNLOCK_HARDWARE( &context->radeon ); - r700SendContextStates(context); r700SendViewportState(context, 0); r700SendRenderTargetState(context, 0); -- cgit v1.2.3 From da88333671b35851bd713d0de464887e00d70593 Mon Sep 17 00:00:00 2001 From: Cooper Yuan Date: Thu, 2 Jul 2009 16:49:19 +0800 Subject: R6xx/r7xx: Correct the indeices of DRAW_INDEX_IMMD --- src/mesa/drivers/dri/r600/r700_render.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index e46b21c85c..a1ad929a67 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -238,6 +238,7 @@ static GLboolean r700RunRender(GLcontext * ctx, { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + int lastIndex = 0; #if 1 BATCH_LOCALS(&context->radeon); @@ -308,7 +309,6 @@ static GLboolean r700RunRender(GLcontext * ctx, GLuint end = vb->Primitive[i].start + vb->Primitive[i].count; GLuint numIndices = vb->Primitive[i].count; GLuint numEntires; - //r300RunRenderPrimitive(rmesa, ctx, start, end, prim); unsigned int VGT_DRAW_INITIATOR = 0; unsigned int VGT_INDEX_TYPE = 0; @@ -340,10 +340,12 @@ static GLboolean r700RunRender(GLcontext * ctx, R600_OUT_BATCH(VGT_NUM_INDICES); R600_OUT_BATCH(VGT_DRAW_INITIATOR); - for (j=0; j Date: Mon, 6 Jul 2009 00:00:10 -0400 Subject: R6xx/r7xx: first pass at texture support texture bo setup isn't quite working yet --- src/mesa/drivers/dri/r600/Makefile | 3 +- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 2 +- src/mesa/drivers/dri/r600/r600_context.c | 2 +- src/mesa/drivers/dri/r600/r600_tex.c | 438 ++++++ src/mesa/drivers/dri/r600/r600_tex.h | 63 + src/mesa/drivers/dri/r600/r600_texstate.c | 795 ++++++++++ src/mesa/drivers/dri/r600/r700_chip.c | 2 +- src/mesa/drivers/dri/r600/r700_chip.h | 4 +- src/mesa/drivers/dri/r600/r700_render.c | 74 +- src/mesa/drivers/dri/r600/r700_tex.c | 1558 -------------------- src/mesa/drivers/dri/r600/r700_tex.h | 104 -- .../drivers/dri/radeon/radeon_common_context.h | 13 + src/mesa/drivers/dri/radeon/radeon_screen.c | 8 +- 13 files changed, 1365 insertions(+), 1701 deletions(-) create mode 100644 src/mesa/drivers/dri/r600/r600_tex.c create mode 100644 src/mesa/drivers/dri/r600/r600_tex.h create mode 100644 src/mesa/drivers/dri/r600/r600_texstate.c delete mode 100644 src/mesa/drivers/dri/r600/r700_tex.c delete mode 100644 src/mesa/drivers/dri/r600/r700_tex.h (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/Makefile b/src/mesa/drivers/dri/r600/Makefile index 667eb1f919..6db0154784 100644 --- a/src/mesa/drivers/dri/r600/Makefile +++ b/src/mesa/drivers/dri/r600/Makefile @@ -50,7 +50,8 @@ DRIVER_SOURCES = \ r700_state.c \ r700_clear.c \ r700_render.c \ - r700_tex.c \ + r600_tex.c \ + r600_texstate.c \ r700_debug.c \ $(RADEON_COMMON_SOURCES) \ $(EGL_SOURCES) diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 90f546edf1..4609e86bb9 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -52,7 +52,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_mipmap_tree.h" #include "radeon_reg.h" -struct r600_cs_manager_legacy +struct r600_cs_manager_legacy { struct radeon_cs_manager base; struct radeon_context *ctx; diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 526d02ed57..78bad8726b 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -251,7 +251,7 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, r700InitChipObject(r600); /* let the eag... */ r700InitStateFuncs(&functions); - r700InitTextureFuncs(&functions); + r600InitTextureFuncs(&functions); r700InitShaderFuncs(&functions); r700InitIoctlFuncs(&functions); diff --git a/src/mesa/drivers/dri/r600/r600_tex.c b/src/mesa/drivers/dri/r600/r600_tex.c new file mode 100644 index 0000000000..5845c05810 --- /dev/null +++ b/src/mesa/drivers/dri/r600/r600_tex.c @@ -0,0 +1,438 @@ +/* +Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + +The Weather Channel (TM) funded Tungsten Graphics to develop the +initial release of the Radeon 8500 driver under the XFree86 license. +This notice must be preserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +/** + * \file + * + * \author Keith Whitwell + */ + +#include "main/glheader.h" +#include "main/imports.h" +#include "main/colormac.h" +#include "main/context.h" +#include "main/enums.h" +#include "main/image.h" +#include "main/mipmap.h" +#include "main/simple_list.h" +#include "main/texformat.h" +#include "main/texstore.h" +#include "main/teximage.h" +#include "main/texobj.h" + +#include "texmem.h" + +#include "r600_context.h" +#include "r700_state.h" +#include "radeon_mipmap_tree.h" +#include "r600_tex.h" + +#include "xmlpool.h" + + +static unsigned int translate_wrap_mode(GLenum wrapmode) +{ + switch(wrapmode) { + case GL_REPEAT: return SQ_TEX_WRAP; + case GL_CLAMP: return SQ_TEX_CLAMP_HALF_BORDER; + case GL_CLAMP_TO_EDGE: return SQ_TEX_CLAMP_LAST_TEXEL; + case GL_CLAMP_TO_BORDER: return SQ_TEX_CLAMP_BORDER; + case GL_MIRRORED_REPEAT: return SQ_TEX_MIRROR_ONCE_HALF_BORDER; + case GL_MIRROR_CLAMP_EXT: return SQ_TEX_MIRROR; + case GL_MIRROR_CLAMP_TO_EDGE_EXT: return SQ_TEX_MIRROR_ONCE_BORDER; + case GL_MIRROR_CLAMP_TO_BORDER_EXT: return SQ_TEX_MIRROR_ONCE_LAST_TEXEL; + default: + _mesa_problem(NULL, "bad wrap mode in %s", __FUNCTION__); + return 0; + } +} + + +/** + * Update the cached hardware registers based on the current texture wrap modes. + * + * \param t Texture object whose wrap modes are to be set + */ +static void r600UpdateTexWrap(radeonTexObjPtr t) +{ + struct gl_texture_object *tObj = &t->base; + + SETfield(t->SQ_TEX_SAMPLER0, translate_wrap_mode(tObj->WrapS), + SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift, SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask); + + if (tObj->Target != GL_TEXTURE_1D) { + SETfield(t->SQ_TEX_SAMPLER0, translate_wrap_mode(tObj->WrapT), + CLAMP_Y_shift, CLAMP_Y_mask); + + if (tObj->Target == GL_TEXTURE_3D) + SETfield(t->SQ_TEX_SAMPLER0, translate_wrap_mode(tObj->WrapR), + CLAMP_Z_shift, CLAMP_Z_mask); + } +} + +static void r600SetTexDefaultState(radeonTexObjPtr t) +{ + /* Init text object to default states. */ + t->SQ_TEX_RESOURCE0 = 0; + SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_2D, DIM_shift, DIM_mask); + SETfield(t->SQ_TEX_RESOURCE0, ARRAY_LINEAR_GENERAL, + SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift, SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask); + CLEARbit(t->SQ_TEX_RESOURCE0, TILE_TYPE_bit); + + t->SQ_TEX_RESOURCE1 = 0; + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE2 = 0; + t->SQ_TEX_RESOURCE3 = 0; + + t->SQ_TEX_RESOURCE4 = 0; + SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED, + FORMAT_COMP_X_shift, FORMAT_COMP_X_mask); + SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED, + FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask); + SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED, + FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask); + SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED, + FORMAT_COMP_W_shift, FORMAT_COMP_W_mask); + SETfield(t->SQ_TEX_RESOURCE4, SQ_NUM_FORMAT_NORM, + SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift, SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_mask); + CLEARbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit); + CLEARbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit); + SETfield(t->SQ_TEX_RESOURCE4, SQ_ENDIAN_NONE, + SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift, SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_mask); + SETfield(t->SQ_TEX_RESOURCE4, 1, REQUEST_SIZE_shift, REQUEST_SIZE_mask); + t->SQ_TEX_RESOURCE4 |= SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift + |SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift + |SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift + |SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift; + SETfield(t->SQ_TEX_RESOURCE4, 0, BASE_LEVEL_shift, BASE_LEVEL_mask); /* mip-maps */ + + t->SQ_TEX_RESOURCE5 = 0; + t->SQ_TEX_RESOURCE6 = 0; + + SETfield(t->SQ_TEX_RESOURCE6, SQ_TEX_VTX_VALID_TEXTURE, + SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask); + + /* Initialize sampler registers */ + t->SQ_TEX_SAMPLER0 = 0; + t->SQ_TEX_SAMPLER0 |= + SQ_TEX_WRAP << SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift + |SQ_TEX_WRAP << CLAMP_Y_shift + |SQ_TEX_WRAP << CLAMP_Z_shift + |SQ_TEX_XY_FILTER_POINT << XY_MAG_FILTER_shift + |SQ_TEX_XY_FILTER_POINT << XY_MIN_FILTER_shift + |SQ_TEX_Z_FILTER_NONE << Z_FILTER_shift + |SQ_TEX_Z_FILTER_NONE << MIP_FILTER_shift + |SQ_TEX_BORDER_COLOR_TRANS_BLACK << BORDER_COLOR_TYPE_shift; + + t->SQ_TEX_SAMPLER1 = 0x7FF << MAX_LOD_shift; + + t->SQ_TEX_SAMPLER2 = 0; + SETbit(t->SQ_TEX_SAMPLER2, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit); +} + + +static GLuint aniso_filter(GLfloat anisotropy) +{ +#if 0 + if (anisotropy >= 16.0) { + return R300_TX_MAX_ANISO_16_TO_1; + } else if (anisotropy >= 8.0) { + return R300_TX_MAX_ANISO_8_TO_1; + } else if (anisotropy >= 4.0) { + return R300_TX_MAX_ANISO_4_TO_1; + } else if (anisotropy >= 2.0) { + return R300_TX_MAX_ANISO_2_TO_1; + } else { + return R300_TX_MAX_ANISO_1_TO_1; + } +#endif + return 0; +} + +/** + * Set the texture magnification and minification modes. + * + * \param t Texture whose filter modes are to be set + * \param minf Texture minification mode + * \param magf Texture magnification mode + * \param anisotropy Maximum anisotropy level + */ +static void r600SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloat anisotropy) +{ + /* Force revalidation to account for switches from/to mipmapping. */ + t->validated = GL_FALSE; + + /* Note that EXT_texture_filter_anisotropic is extremely vague about + * how anisotropic filtering interacts with the "normal" filter modes. + * When anisotropic filtering is enabled, we override min and mag + * filter settings completely. This includes driconf's settings. + */ + if (anisotropy >= 2.0 && (minf != GL_NEAREST) && (magf != GL_NEAREST)) { + /*t->pp_txfilter |= R300_TX_MAG_FILTER_ANISO + | R300_TX_MIN_FILTER_ANISO + | R300_TX_MIN_FILTER_MIP_LINEAR + | aniso_filter(anisotropy);*/ + if (RADEON_DEBUG & DEBUG_TEXTURE) + fprintf(stderr, "Using maximum anisotropy of %f\n", anisotropy); + return; + } + + switch (minf) { + case GL_NEAREST: + SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point, + XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); + SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_None, + MIP_FILTER_shift, MIP_FILTER_mask); + break; + case GL_LINEAR: + SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear, + XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); + SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_None, + MIP_FILTER_shift, MIP_FILTER_mask); + break; + case GL_NEAREST_MIPMAP_NEAREST: + SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point, + XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); + SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Point, + MIP_FILTER_shift, MIP_FILTER_mask); + break; + case GL_NEAREST_MIPMAP_LINEAR: + SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point, + XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); + SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Linear, + MIP_FILTER_shift, MIP_FILTER_mask); + break; + case GL_LINEAR_MIPMAP_NEAREST: + SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear, + XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); + SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Point, + MIP_FILTER_shift, MIP_FILTER_mask); + break; + case GL_LINEAR_MIPMAP_LINEAR: + SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear, + XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); + SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Linear, + MIP_FILTER_shift, MIP_FILTER_mask); + break; + } + + /* Note we don't have 3D mipmaps so only use the mag filter setting + * to set the 3D texture filter mode. + */ + switch (magf) { + case GL_NEAREST: + SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point, + XY_MAG_FILTER_shift, XY_MAG_FILTER_mask); + break; + case GL_LINEAR: + SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear, + XY_MAG_FILTER_shift, XY_MAG_FILTER_mask); + break; + } +} + +static void r600SetTexBorderColor(radeonTexObjPtr t, const GLfloat color[4]) +{ +#if 0 + GLubyte c[4]; + CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]); + CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]); + CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]); + CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]); + t->pp_border_color = PACK_COLOR_8888(c[3], c[0], c[1], c[2]); +#endif +} + +/** + * Changes variables and flags for a state update, which will happen at the + * next UpdateTextureState + */ + +static void r600TexParameter(GLcontext * ctx, GLenum target, + struct gl_texture_object *texObj, + GLenum pname, const GLfloat * params) +{ + radeonTexObj* t = radeon_tex_obj(texObj); + + if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { + fprintf(stderr, "%s( %s )\n", __FUNCTION__, + _mesa_lookup_enum_by_nr(pname)); + } + + switch (pname) { + case GL_TEXTURE_MIN_FILTER: + case GL_TEXTURE_MAG_FILTER: + case GL_TEXTURE_MAX_ANISOTROPY_EXT: + r600SetTexFilter(t, texObj->MinFilter, texObj->MagFilter, texObj->MaxAnisotropy); + break; + + case GL_TEXTURE_WRAP_S: + case GL_TEXTURE_WRAP_T: + case GL_TEXTURE_WRAP_R: + r600UpdateTexWrap(t); + break; + + case GL_TEXTURE_BORDER_COLOR: + r600SetTexBorderColor(t, texObj->BorderColor); + break; + + case GL_TEXTURE_BASE_LEVEL: + case GL_TEXTURE_MAX_LEVEL: + case GL_TEXTURE_MIN_LOD: + case GL_TEXTURE_MAX_LOD: + /* This isn't the most efficient solution but there doesn't appear to + * be a nice alternative. Since there's no LOD clamping, + * we just have to rely on loading the right subset of mipmap levels + * to simulate a clamped LOD. + */ + if (t->mt) { + radeon_miptree_unreference(t->mt); + t->mt = 0; + t->validated = GL_FALSE; + } + break; + + case GL_DEPTH_TEXTURE_MODE: + if (!texObj->Image[0][texObj->BaseLevel]) + return; + if (texObj->Image[0][texObj->BaseLevel]->TexFormat->BaseFormat + == GL_DEPTH_COMPONENT) { + r600SetDepthTexMode(texObj); + break; + } else { + /* If the texture isn't a depth texture, changing this + * state won't cause any changes to the hardware. + * Don't force a flush of texture state. + */ + return; + } + + default: + return; + } +} + +static void r600DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) +{ + context_t* rmesa = R700_CONTEXT(ctx); + radeonTexObj* t = radeon_tex_obj(texObj); + + if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { + fprintf(stderr, "%s( %p (target = %s) )\n", __FUNCTION__, + (void *)texObj, + _mesa_lookup_enum_by_nr(texObj->Target)); + } + + if (rmesa) { + // fixme + int i; + //radeon_firevertices(&rmesa->radeon); + + for(i = 0; i < R700_MAX_TEXTURE_UNITS; ++i) + if (rmesa->hw.textures[i] == t) + rmesa->hw.textures[i] = 0; + } + + if (t->bo) { + radeon_bo_unref(t->bo); + t->bo = NULL; + } + + if (t->mt) { + radeon_miptree_unreference(t->mt); + t->mt = 0; + } + _mesa_delete_texture_object(ctx, texObj); +} + +/** + * Allocate a new texture object. + * Called via ctx->Driver.NewTextureObject. + * Note: this function will be called during context creation to + * allocate the default texture objects. + * Fixup MaxAnisotropy according to user preference. + */ +static struct gl_texture_object *r600NewTextureObject(GLcontext * ctx, + GLuint name, + GLenum target) +{ + context_t* rmesa = R700_CONTEXT(ctx); + radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj); + + + if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { + fprintf(stderr, "%s( %p (target = %s) )\n", __FUNCTION__, + t, _mesa_lookup_enum_by_nr(target)); + } + + _mesa_initialize_texture_object(&t->base, name, target); + t->base.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy; + + /* Initialize hardware state */ + r600SetTexDefaultState(t); + r600UpdateTexWrap(t); + r600SetTexFilter(t, t->base.MinFilter, t->base.MagFilter, t->base.MaxAnisotropy); + r600SetTexBorderColor(t, t->base.BorderColor); + + return &t->base; +} + +void r600InitTextureFuncs(struct dd_function_table *functions) +{ + /* Note: we only plug in the functions we implement in the driver + * since _mesa_init_driver_functions() was already called. + */ + functions->NewTextureImage = radeonNewTextureImage; + functions->FreeTexImageData = radeonFreeTexImageData; + functions->MapTexture = radeonMapTexture; + functions->UnmapTexture = radeonUnmapTexture; + + functions->ChooseTextureFormat = radeonChooseTextureFormat_mesa; + functions->TexImage1D = radeonTexImage1D; + functions->TexImage2D = radeonTexImage2D; + functions->TexImage3D = radeonTexImage3D; + functions->TexSubImage1D = radeonTexSubImage1D; + functions->TexSubImage2D = radeonTexSubImage2D; + functions->TexSubImage3D = radeonTexSubImage3D; + functions->GetTexImage = radeonGetTexImage; + functions->GetCompressedTexImage = radeonGetCompressedTexImage; + functions->NewTextureObject = r600NewTextureObject; + functions->DeleteTexture = r600DeleteTexture; + functions->IsTextureResident = driIsTextureResident; + + functions->TexParameter = r600TexParameter; + + functions->CompressedTexImage2D = radeonCompressedTexImage2D; + functions->CompressedTexSubImage2D = radeonCompressedTexSubImage2D; + + functions->GenerateMipmap = radeonGenerateMipmap; + + driInitTextureFormats(); +} diff --git a/src/mesa/drivers/dri/r600/r600_tex.h b/src/mesa/drivers/dri/r600/r600_tex.h new file mode 100644 index 0000000000..fb0e1a023e --- /dev/null +++ b/src/mesa/drivers/dri/r600/r600_tex.h @@ -0,0 +1,63 @@ +/* +Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + +The Weather Channel (TM) funded Tungsten Graphics to develop the +initial release of the Radeon 8500 driver under the XFree86 license. +This notice must be preserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Keith Whitwell + */ + +#ifndef __r600_TEX_H__ +#define __r600_TEX_H__ + +/* TODO : review this after texture load code. */ +#define R700_BLIT_WIDTH_BYTES 1024 +/* The BASE_ADDRESS and MIP_ADDRESS fields are 256-byte-aligned */ +#define R700_TEXTURE_ALIGNMENT_MASK 0x255 +/* Texel pitch is 8 alignment. */ +#define R700_TEXEL_PITCH_ALIGNMENT_MASK 0x7 + +#define R700_MAX_TEXTURE_UNITS 8 /* TODO : should be 16, lets make it work, review later */ + +extern void r600SetDepthTexMode(struct gl_texture_object *tObj); + +extern void r600SetTexBuffer(__DRIcontext *pDRICtx, GLint target, + __DRIdrawable *dPriv); + +extern void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, + GLint format, __DRIdrawable *dPriv); + +extern void r600SetTexOffset(__DRIcontext *pDRICtx, GLint texname, + unsigned long long offset, GLint depth, + GLuint pitch); + +extern GLboolean r600ValidateBuffers(GLcontext * ctx); + +extern void r600InitTextureFuncs(struct dd_function_table *functions); + +#endif /* __r600_TEX_H__ */ diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c new file mode 100644 index 0000000000..5a249d4f14 --- /dev/null +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -0,0 +1,795 @@ +/* +Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + +The Weather Channel (TM) funded Tungsten Graphics to develop the +initial release of the Radeon 8500 driver under the XFree86 license. +This notice must be preserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/** + * \file + * + * \author Keith Whitwell + * + * \todo Enable R300 texture tiling code? + */ + +#include "main/glheader.h" +#include "main/imports.h" +#include "main/context.h" +#include "main/macros.h" +#include "main/texformat.h" +#include "main/teximage.h" +#include "main/texobj.h" +#include "main/enums.h" + +#include "r600_context.h" +#include "r700_state.h" +#include "radeon_mipmap_tree.h" +#include "r600_tex.h" + +void r600UpdateTextureState(GLcontext * ctx) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + struct gl_texture_unit *texUnit; + struct radeon_tex_obj *t; + GLuint unit; + + for (unit = 0; unit < R700_MAX_TEXTURE_UNITS; unit++) { + texUnit = &ctx->Texture.Unit[unit]; + t = radeon_tex_obj(ctx->Texture.Unit[unit]._Current); + + if (texUnit->_ReallyEnabled) { + if (!t) + continue; + r700->textures[unit] = t; + } + } +} + +static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, GLuint mesa_format) +{ + radeonTexObj *t = radeon_tex_obj(tObj); + + t->SQ_TEX_RESOURCE4 &= ~( SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask + |SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask + |SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask + |SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask ); + + switch (mesa_format) /* This is mesa format. */ + { + case MESA_FORMAT_RGBA8888: + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGBA8888_REV: + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ARGB8888: + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ARGB8888_REV: + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGB888: + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGB565: + SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGB565_REV: + SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ARGB4444: + SETfield(t->SQ_TEX_RESOURCE1, FMT_4_4_4_4, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ARGB4444_REV: + SETfield(t->SQ_TEX_RESOURCE1, FMT_4_4_4_4, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ARGB1555: + SETfield(t->SQ_TEX_RESOURCE1, FMT_1_5_5_5, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ARGB1555_REV: + SETfield(t->SQ_TEX_RESOURCE1, FMT_1_5_5_5, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_AL88: + case MESA_FORMAT_AL88_REV: /* TODO : Check this. */ + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGB332: + SETfield(t->SQ_TEX_RESOURCE1, FMT_3_3_2, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_A8: /* ZERO, ZERO, ZERO, X */ + SETfield(t->SQ_TEX_RESOURCE1, FMT_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_L8: /* X, X, X, ONE */ + SETfield(t->SQ_TEX_RESOURCE1, FMT_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_I8: /* X, X, X, X */ + case MESA_FORMAT_CI8: + SETfield(t->SQ_TEX_RESOURCE1, FMT_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + /* YUV422 TODO conversion */ /* X, Y, Z, ONE, G8R8_G8B8 */ + /* + case MESA_FORMAT_YCBCR: + t->SQ_TEX_RESOURCE1.bitfields.DATA_FORMAT = ; + break; + */ + /* VUY422 TODO conversion */ /* X, Y, Z, ONE, G8R8_G8B8 */ + /* + case MESA_FORMAT_YCBCR_REV: + t->SQ_TEX_RESOURCE1.bitfields.DATA_FORMAT = ; + break; + */ + case MESA_FORMAT_RGB_DXT1: /* not supported yet */ + + break; + case MESA_FORMAT_RGBA_DXT1: /* not supported yet */ + + break; + case MESA_FORMAT_RGBA_DXT3: /* not supported yet */ + + break; + case MESA_FORMAT_RGBA_DXT5: /* not supported yet */ + + break; + case MESA_FORMAT_RGBA_FLOAT32: + SETfield(t->SQ_TEX_RESOURCE1, FMT_32_32_32_32_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGBA_FLOAT16: + SETfield(t->SQ_TEX_RESOURCE1, FMT_16_16_16_16_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGB_FLOAT32: /* X, Y, Z, ONE */ + SETfield(t->SQ_TEX_RESOURCE1, FMT_32_32_32_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_RGB_FLOAT16: + SETfield(t->SQ_TEX_RESOURCE1, FMT_16_16_16_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ALPHA_FLOAT32: /* ZERO, ZERO, ZERO, X */ + SETfield(t->SQ_TEX_RESOURCE1, FMT_32_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_ALPHA_FLOAT16: /* ZERO, ZERO, ZERO, X */ + SETfield(t->SQ_TEX_RESOURCE1, FMT_16_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_LUMINANCE_FLOAT32: /* X, X, X, ONE */ + SETfield(t->SQ_TEX_RESOURCE1, FMT_32_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_LUMINANCE_FLOAT16: /* X, X, X, ONE */ + SETfield(t->SQ_TEX_RESOURCE1, FMT_16_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32: + SETfield(t->SQ_TEX_RESOURCE1, FMT_32_32_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16: + SETfield(t->SQ_TEX_RESOURCE1, FMT_16_16_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */ + SETfield(t->SQ_TEX_RESOURCE1, FMT_32_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */ + SETfield(t->SQ_TEX_RESOURCE1, FMT_16_FLOAT, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case MESA_FORMAT_Z16: + case MESA_FORMAT_Z24_S8: + case MESA_FORMAT_Z32: + switch (mesa_format) { + case MESA_FORMAT_Z16: + SETfield(t->SQ_TEX_RESOURCE1, FMT_16, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + break; + case MESA_FORMAT_Z24_S8: + SETfield(t->SQ_TEX_RESOURCE1, FMT_24_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + break; + case MESA_FORMAT_Z32: + SETfield(t->SQ_TEX_RESOURCE1, FMT_32, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + break; + }; + switch (tObj->DepthMode) { + case GL_LUMINANCE: /* X, X, X, ONE */ + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case GL_INTENSITY: /* X, X, X, X */ + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + case GL_ALPHA: /* ZERO, ZERO, ZERO, X */ + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + break; + default: + return GL_FALSE; + } + break; + default: + /* Not supported format */ + return GL_FALSE; + }; + + return GL_TRUE; +} + +void r600SetDepthTexMode(struct gl_texture_object *tObj) +{ + const GLuint *format; + radeonTexObjPtr t; + + if (!tObj) + return; + + t = radeon_tex_obj(tObj); + + r600GetTexFormat(tObj, tObj->Image[0][tObj->BaseLevel]->TexFormat->MesaFormat); + +} + +/** + * Compute the cached hardware register values for the given texture object. + * + * \param rmesa Context pointer + * \param t the r300 texture object + */ +static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *texObj) +{ + radeonTexObj *t = radeon_tex_obj(texObj); + const struct gl_texture_image *firstImage; + int firstlevel = t->mt ? t->mt->firstLevel : 0; + GLuint uTexelPitch; + + firstImage = t->base.Image[0][firstlevel]; + + if (!t->image_override) { + if (!r600GetTexFormat(texObj, firstImage->TexFormat->MesaFormat)) { + _mesa_problem(NULL, "unexpected texture format in %s", + __FUNCTION__); + return; + } + } + + if (t->image_override && t->bo) + return; + + switch (texObj->Target) { + case GL_TEXTURE_1D: + SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_1D, DIM_shift, DIM_mask); + SETfield(t->SQ_TEX_RESOURCE1, 0, TEX_DEPTH_shift, TEX_DEPTH_mask); + break; + case GL_TEXTURE_2D: + case GL_TEXTURE_RECTANGLE_NV: + SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_2D, DIM_shift, DIM_mask); + SETfield(t->SQ_TEX_RESOURCE1, 0, TEX_DEPTH_shift, TEX_DEPTH_mask); + break; + case GL_TEXTURE_3D: + SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_3D, DIM_shift, DIM_mask); + SETfield(t->SQ_TEX_RESOURCE1, firstImage->Depth - 1, // ??? + TEX_DEPTH_shift, TEX_DEPTH_mask); + break; + case GL_TEXTURE_CUBE_MAP: + SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_CUBEMAP, DIM_shift, DIM_mask); + SETfield(t->SQ_TEX_RESOURCE1, 0, TEX_DEPTH_shift, TEX_DEPTH_mask); + break; + default: + _mesa_problem(NULL, "unexpected texture target type in %s", __FUNCTION__); + return; + } + + uTexelPitch = (firstImage->Width + R700_TEXEL_PITCH_ALIGNMENT_MASK) + & ~R700_TEXEL_PITCH_ALIGNMENT_MASK; + + SETfield(t->SQ_TEX_RESOURCE0, (uTexelPitch/8)-1, PITCH_shift, PITCH_mask); + SETfield(t->SQ_TEX_RESOURCE0, firstImage->Width - 1, + TEX_WIDTH_shift, TEX_WIDTH_mask); + SETfield(t->SQ_TEX_RESOURCE1, firstImage->Height - 1, + TEX_HEIGHT_shift, TEX_HEIGHT_mask); + +} + +/** + * Ensure the given texture is ready for rendering. + * + * Mostly this means populating the texture object's mipmap tree. + */ +static GLboolean r600_validate_texture(GLcontext * ctx, struct gl_texture_object *texObj) +{ + context_t *rmesa = R700_CONTEXT(ctx); + radeonTexObj *t = radeon_tex_obj(texObj); + + if (!radeon_validate_texture_miptree(ctx, texObj)) + return GL_FALSE; + + /* Configure the hardware registers (more precisely, the cached version + * of the hardware registers). */ + setup_hardware_state(rmesa, texObj); + + t->validated = GL_TRUE; + return GL_TRUE; +} + +/** + * Ensure all enabled and complete textures are uploaded along with any buffers being used. + */ +GLboolean r600ValidateBuffers(GLcontext * ctx) +{ + context_t *rmesa = R700_CONTEXT(ctx); + struct radeon_renderbuffer *rrb; + int i; + + radeon_validate_reset_bos(&rmesa->radeon); + + rrb = radeon_get_colorbuffer(&rmesa->radeon); + /* color buffer */ + if (rrb && rrb->bo) { + radeon_validate_bo(&rmesa->radeon, rrb->bo, + 0, RADEON_GEM_DOMAIN_VRAM); + } + + /* depth buffer */ + rrb = radeon_get_depthbuffer(&rmesa->radeon); + if (rrb && rrb->bo) { + radeon_validate_bo(&rmesa->radeon, rrb->bo, + 0, RADEON_GEM_DOMAIN_VRAM); + } + + for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) { + radeonTexObj *t; + + if (!ctx->Texture.Unit[i]._ReallyEnabled) + continue; + + if (!r600_validate_texture(ctx, ctx->Texture.Unit[i]._Current)) { + _mesa_warning(ctx, + "failed to validate texture for unit %d.\n", + i); + } + t = radeon_tex_obj(ctx->Texture.Unit[i]._Current); + if (t->image_override && t->bo) + radeon_validate_bo(&rmesa->radeon, t->bo, + RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); + + else if (t->mt->bo) + radeon_validate_bo(&rmesa->radeon, t->mt->bo, + RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); + } + if (rmesa->radeon.dma.current) + radeon_validate_bo(&rmesa->radeon, rmesa->radeon.dma.current, RADEON_GEM_DOMAIN_GTT, 0); + + return radeon_revalidate_bos(ctx); +} + +void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname, + unsigned long long offset, GLint depth, GLuint pitch) +{ + context_t *rmesa = pDRICtx->driverPrivate; + struct gl_texture_object *tObj = + _mesa_lookup_texture(rmesa->radeon.glCtx, texname); + radeonTexObjPtr t = radeon_tex_obj(tObj); + uint32_t pitch_val; + + if (!tObj) + return; + + t->image_override = GL_TRUE; + + if (!offset) + return; + + t->bo = NULL; + t->override_offset = offset; + pitch_val = pitch; + switch (depth) { + case 32: + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + pitch_val /= 4; + break; + case 24: + default: + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + pitch_val /= 4; + break; + case 16: + SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + pitch_val /= 2; + break; + } + + pitch_val = (pitch_val + R700_TEXEL_PITCH_ALIGNMENT_MASK) + & ~R700_TEXEL_PITCH_ALIGNMENT_MASK; + SETfield(t->SQ_TEX_RESOURCE0, (pitch_val/8)-1, PITCH_shift, PITCH_mask); +} + +void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, __DRIdrawable *dPriv) +{ + struct gl_texture_unit *texUnit; + struct gl_texture_object *texObj; + struct gl_texture_image *texImage; + struct radeon_renderbuffer *rb; + radeon_texture_image *rImage; + radeonContextPtr radeon; + context_t *rmesa; + struct radeon_framebuffer *rfb; + radeonTexObjPtr t; + uint32_t pitch_val; + uint32_t internalFormat, type, format; + + type = GL_BGRA; + format = GL_UNSIGNED_BYTE; + internalFormat = (glx_texture_format == GLX_TEXTURE_FORMAT_RGB_EXT ? 3 : 4); + + radeon = pDRICtx->driverPrivate; + rmesa = pDRICtx->driverPrivate; + + rfb = dPriv->driverPrivate; + texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit]; + texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target); + texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0); + + rImage = get_radeon_texture_image(texImage); + t = radeon_tex_obj(texObj); + if (t == NULL) { + return; + } + + radeon_update_renderbuffers(pDRICtx, dPriv); + /* back & depth buffer are useless free them right away */ + rb = (void*)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = (void*)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; + if (rb && rb->bo) { + radeon_bo_unref(rb->bo); + rb->bo = NULL; + } + rb = rfb->color_rb[0]; + if (rb->bo == NULL) { + /* Failed to BO for the buffer */ + return; + } + + _mesa_lock_texture(radeon->glCtx, texObj); + if (t->bo) { + radeon_bo_unref(t->bo); + t->bo = NULL; + } + if (rImage->bo) { + radeon_bo_unref(rImage->bo); + rImage->bo = NULL; + } + if (t->mt) { + radeon_miptree_unreference(t->mt); + t->mt = NULL; + } + if (rImage->mt) { + radeon_miptree_unreference(rImage->mt); + rImage->mt = NULL; + } + _mesa_init_teximage_fields(radeon->glCtx, target, texImage, + rb->width, rb->height, 1, 0, rb->cpp); + texImage->RowStride = rb->pitch / rb->cpp; + texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx, + internalFormat, + type, format, 0); + rImage->bo = rb->bo; + radeon_bo_ref(rImage->bo); + t->bo = rb->bo; + radeon_bo_ref(t->bo); + t->image_override = GL_TRUE; + t->override_offset = 0; + pitch_val = rb->pitch; + switch (rb->cpp) { + case 4: + if (glx_texture_format == GLX_TEXTURE_FORMAT_RGB_EXT) { + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + } else { + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + } + pitch_val /= 4; + break; + case 3: + default: + // FMT_8_8_8 ??? + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + pitch_val /= 4; + break; + case 2: + SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + + t->SQ_TEX_RESOURCE4 |= + (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) + |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) + |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) + |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); + pitch_val /= 2; + break; + } + + pitch_val = (pitch_val + R700_TEXEL_PITCH_ALIGNMENT_MASK) + & ~R700_TEXEL_PITCH_ALIGNMENT_MASK; + + SETfield(t->SQ_TEX_RESOURCE0, (pitch_val/8)-1, PITCH_shift, PITCH_mask); + SETfield(t->SQ_TEX_RESOURCE0, rb->width - 1, + TEX_WIDTH_shift, TEX_WIDTH_mask); + SETfield(t->SQ_TEX_RESOURCE1, rb->height - 1, + TEX_HEIGHT_shift, TEX_HEIGHT_mask); + + t->validated = GL_TRUE; + _mesa_unlock_texture(radeon->glCtx, texObj); + return; +} + +void r600SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) +{ + r600SetTexBuffer2(pDRICtx, target, GLX_TEXTURE_FORMAT_RGBA_EXT, dPriv); +} diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 4ace9c946b..ae380d83fc 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -32,7 +32,7 @@ #include "r600_cmdbuf.h" #include "r700_state.h" -#include "r700_tex.h" +#include "r600_tex.h" #include "r700_oglprog.h" #include "r700_fragprog.h" #include "r700_vertprog.h" diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h index fc38e96cb7..41654fd563 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.h +++ b/src/mesa/drivers/dri/r600/r700_chip.h @@ -148,6 +148,7 @@ union UINT_FLOAT float f32All; }; +#if 0 typedef struct _TEXTURE_STATE_STRUCT { union UINT_FLOAT SQ_TEX_RESOURCE0; @@ -173,6 +174,7 @@ typedef struct _R700_TEXTURE_STATES TEXTURE_STATE_STRUCT *textures[R700_TEXTURE_NUMBERUNITS]; SAMPLER_STATE_STRUCT *samplers[R700_TEXTURE_NUMBERUNITS]; } R700_TEXTURE_STATES; +#endif typedef struct _RENDER_TARGET_STATE_STRUCT { @@ -506,7 +508,7 @@ typedef struct _R700_CHIP_CONTEXT ContextState* pStateList; - R700_TEXTURE_STATES texture_states; + radeonTexObj* textures[R700_TEXTURE_NUMBERUNITS]; GLboolean bEnablePerspective; diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index a1ad929a67..b29a1aa918 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -44,10 +44,11 @@ #include "tnl/t_vertex.h" #include "tnl/t_pipeline.h" +#include "radeon_mipmap_tree.h" #include "r600_context.h" #include "r600_cmdbuf.h" -#include "r700_tex.h" +#include "r600_tex.h" #include "r700_vertprog.h" #include "r700_fragprog.h" @@ -131,36 +132,46 @@ static GLboolean r700SetupShaders(GLcontext * ctx) GLboolean r700SendTextureState(context_t *context) { unsigned int i; - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); -#if 0 /* to be enabled */ - for(i=0; itexture_states.textures[i] != 0) - { - R700_CMDBUF_CHECK_SPACE(9); - R700EP3 (context, IT_SET_RESOURCE, 7); - R700E32 (context, i * 7); - R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE0.u32All); - R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE1.u32All); - R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE2.u32All); - R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE3.u32All); - R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE4.u32All); - R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE5.u32All); - R700E32 (context, r700->texture_states.textures[i]->SQ_TEX_RESOURCE6.u32All); - } + offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF}; + struct radeon_bo *bo = NULL; + BATCH_LOCALS(&context->radeon); - if(r700->texture_states.samplers[i] != 0) - { - R700_CMDBUF_CHECK_SPACE(5); - R700EP3 (context, IT_SET_SAMPLER, 3); - R700E32 (context, i * 3); // Base at 0x7000 - R700E32 (context, r700->texture_states.samplers[i]->SQ_TEX_SAMPLER0.u32All); - R700E32 (context, r700->texture_states.samplers[i]->SQ_TEX_SAMPLER1.u32All); - R700E32 (context, r700->texture_states.samplers[i]->SQ_TEX_SAMPLER2.u32All); - } + for (i=0; itextures[i]; + if (t) { + if (!t->image_override) + bo = t->mt->bo; + else + bo = t->bo; + if (bo) { + BEGIN_BATCH_NO_AUTOSTATE(14); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); + R600_OUT_BATCH(i * 7); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1); + R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2, + bo, + 0, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod); + R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3, + bo, + 0, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6); + + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3)); + R600_OUT_BATCH(i * 3); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2); + END_BATCH(); + COMMIT_BATCH(); + } + } } -#endif return GL_TRUE; } @@ -253,6 +264,9 @@ static GLboolean r700RunRender(GLcontext * ctx, fp->r700AsmCode.bR6xx = 1; } + if (!r600ValidateBuffers(ctx)) + return GL_TRUE; + r700Start3D(context); /* TODO : this is too much. */ r700SyncSurf(context); /* TODO : make it light. */ @@ -273,7 +287,7 @@ static GLboolean r700RunRender(GLcontext * ctx, /* flush TX */ //r700SyncSurf(context); /* */ - r700UpdateTextureState(context); + r600UpdateTextureState(ctx); r700SendTextureState(context); if(GL_FALSE == fp->translated) @@ -391,7 +405,7 @@ static GLboolean r700RunTCLRender(GLcontext * ctx, /*----------------------*/ /** * Ensure all enabled and complete textures are uploaded along with any buffers being used. */ - if(!r700ValidateBuffers(ctx)) + if(!r600ValidateBuffers(ctx)) { return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r600/r700_tex.c b/src/mesa/drivers/dri/r600/r700_tex.c deleted file mode 100644 index 21c9379729..0000000000 --- a/src/mesa/drivers/dri/r600/r700_tex.c +++ /dev/null @@ -1,1558 +0,0 @@ -/* - * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * Authors: - * Richard Li , - */ - -#include "main/glheader.h" -#include "main/imports.h" -#include "main/colormac.h" -#include "main/context.h" -#include "main/simple_list.h" -#include "main/texformat.h" -#include "main/texstore.h" -#include "texmem.h" -#include "main/teximage.h" -#include "main/texobj.h" -#include "main/macros.h" -#include "xmlpool.h" - -#include "radeon_common.h" - -#include "r600_context.h" - -#include "r700_state.h" - -#include "r700_tex.h" - - -/* to be enable */ -void r700SetTexBuffer(__DRIcontext *pDRICtx, GLint target, - __DRIdrawable *dPriv) -{ -} - -/* to be enable */ -void r700SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, - GLint format, __DRIdrawable *dPriv) -{ -} - -/* to be enable */ -void r700SetTexOffset(__DRIcontext *pDRICtx, GLint texname, - unsigned long long offset, GLint depth, - GLuint pitch) -{ -} - -static GLboolean r700GetTexFormat(struct gl_texture_object *tObj, GLuint mesa_format) -{ - r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; - - t->texture_state.SQ_TEX_RESOURCE4.u32All &= ~( SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask - |SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask - |SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask - |SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask ); - - switch (mesa_format) /* This is mesa format. */ - { - case MESA_FORMAT_RGBA8888: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8_8_8_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - - break; - case MESA_FORMAT_RGBA8888_REV: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8_8_8_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - - break; - case MESA_FORMAT_ARGB8888: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8_8_8_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_ARGB8888_REV: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8_8_8_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - - case MESA_FORMAT_RGB888: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8_8_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_RGB565: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_5_6_5, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_RGB565_REV: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_5_6_5, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_ARGB4444: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_4_4_4_4, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_ARGB4444_REV: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_4_4_4_4, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_ARGB1555: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_1_5_5_5, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_ARGB1555_REV: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_1_5_5_5, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_AL88: - case MESA_FORMAT_AL88_REV: /* TODO : Check this. */ - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_RGB332: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_3_3_2, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_A8: /* ZERO, ZERO, ZERO, X */ - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_L8: /* X, X, X, ONE */ - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_I8: /* X, X, X, X */ - case MESA_FORMAT_CI8: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - /* YUV422 TODO conversion */ /* X, Y, Z, ONE, G8R8_G8B8 */ - /* - case MESA_FORMAT_YCBCR: - t->texture_state.SQ_TEX_RESOURCE1.bitfields.DATA_FORMAT = ; - break; - */ - /* VUY422 TODO conversion */ /* X, Y, Z, ONE, G8R8_G8B8 */ - /* - case MESA_FORMAT_YCBCR_REV: - t->texture_state.SQ_TEX_RESOURCE1.bitfields.DATA_FORMAT = ; - break; - */ - case MESA_FORMAT_RGB_DXT1: /* not supported yet */ - - break; - case MESA_FORMAT_RGBA_DXT1: /* not supported yet */ - - break; - case MESA_FORMAT_RGBA_DXT3: /* not supported yet */ - - break; - case MESA_FORMAT_RGBA_DXT5: /* not supported yet */ - - break; - case MESA_FORMAT_RGBA_FLOAT32: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_32_32_32_32_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_RGBA_FLOAT16: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_16_16_16_16_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_RGB_FLOAT32: /* X, Y, Z, ONE */ - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_32_32_32_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_RGB_FLOAT16: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_16_16_16_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_ALPHA_FLOAT32: /* ZERO, ZERO, ZERO, X */ - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_32_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_ALPHA_FLOAT16: /* ZERO, ZERO, ZERO, X */ - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_16_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_LUMINANCE_FLOAT32: /* X, X, X, ONE */ - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_32_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_LUMINANCE_FLOAT16: /* X, X, X, ONE */ - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_16_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_32_32_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_16_16_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */ - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_32_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */ - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_16_FLOAT, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case MESA_FORMAT_Z16: - case MESA_FORMAT_Z24_S8: - case MESA_FORMAT_Z32: - switch (mesa_format) - { - case MESA_FORMAT_Z16: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_16, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - break; - case MESA_FORMAT_Z24_S8: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_24_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - break; - case MESA_FORMAT_Z32: - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_32, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - }; - switch (tObj->DepthMode) - { - case GL_LUMINANCE: /* X, X, X, ONE */ - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case GL_INTENSITY: /* X, X, X, X */ - - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - case GL_ALPHA: /* ZERO, ZERO, ZERO, X */ - t->texture_state.SQ_TEX_RESOURCE4.u32All |= - (SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) - |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) - |(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) - |(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift); - break; - default: - return GL_FALSE; - } - break; - default: - /* Not supported format */ - return GL_FALSE; - }; - - return GL_TRUE; -} - -static void compute_tex_image_offset( - struct gl_texture_object *tObj, - GLuint face, - GLint level, - GLint* curOffset) -{ - r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; - const struct gl_texture_image* texImage; - GLuint blitWidth = R700_BLIT_WIDTH_BYTES; - GLuint texelBytes; - GLuint size; - GLuint pitch; - - texImage = tObj->Image[0][level + t->base.firstLevel]; - if (!texImage) - { - return; - } - - texelBytes = texImage->TexFormat->TexelBytes; - - pitch = (texImage->Width + R700_TEXEL_PITCH_ALIGNMENT_MASK) & ~R700_TEXEL_PITCH_ALIGNMENT_MASK; - - /* find image size in bytes */ - if (texImage->IsCompressed) - { - /* not supported yet */ - } - else if (tObj->Target == GL_TEXTURE_RECTANGLE_NV) - { - if( (ARRAY_LINEAR_ALIGNED << SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift) - == (t->texture_state.SQ_TEX_RESOURCE0.u32All & SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask) ) - { - pitch = (texImage->Width * texelBytes + 255) & ~255; - } - else - { - if(0 == level) - { - pitch = (pitch * texelBytes + 63) & ~63; - } - else - { - pitch = texImage->Width * texelBytes; - } - } - size = pitch * texImage->Height; - blitWidth = 64 / texelBytes; - pitch /= texelBytes; - } - else - { - if( (ARRAY_LINEAR_ALIGNED << SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift) - == (t->texture_state.SQ_TEX_RESOURCE0.u32All & SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask) ) - { - pitch = (texImage->Width * texelBytes + 255) & ~255; - } - else - { - if(0 == level) - { - pitch = (pitch * texelBytes + 31) & ~31; - } - else - { - pitch = texImage->Width * texelBytes; - } - } - size = pitch * texImage->Height * texImage->Depth; - blitWidth = MAX2(texImage->Width, 64 / texelBytes); - pitch /= texelBytes; - } - assert(size > 0); - - if( (0 == level) || (1 == level) ) /* 0 for BASE_ADDRESS, 1 for MIP_ADDRESS */ - { - *curOffset = (*curOffset + R700_TEXTURE_ALIGNMENT_MASK) & ~R700_TEXTURE_ALIGNMENT_MASK; - } - - if (texelBytes) - { - /* fix x and y coords up later together with offset */ - t->texel_pitch[face][level] = pitch; - t->level_offset[face][level] = *curOffset; - t->byte_per_texel = texelBytes; - t->src_width_in_pexel[face][level] = texImage->Width; - t->src_hight_in_pexel[face][level] = texImage->Height; - } - else - { - /* Do it like one byte texel. */ - pitch = (size + R700_TEXEL_PITCH_ALIGNMENT_MASK) & ~R700_TEXEL_PITCH_ALIGNMENT_MASK; - t->texel_pitch[face][level] = pitch; - t->level_offset[face][level] = *curOffset; - t->byte_per_texel = 1; - t->src_width_in_pexel[face][level] = size; - t->src_hight_in_pexel[face][level] = 1; - } - - *curOffset += size; -} - -void r700DestroyTexObj(context_t context, r700TexObjPtr t) -{ - /* TODO : nuke r700 chip texture and sampler pointer. */ - //int i; - - //for (i = 0; i < rmesa->ctx->Const.MaxTextureUnits; i++) - //{ - //if (rmesa->state.texture.unit[i].texobj == t) { - // rmesa->state.texture.unit[i].texobj = NULL; - //} - //} -} - -static void r700SetTexImages(context_t *context, struct gl_texture_object *tObj) -{ -#if 0 /* to be enabled */ - r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; - const struct gl_texture_image *baseImage = tObj->Image[0][tObj->BaseLevel]; - GLint curOffset; - GLint i, texelBytes; - GLint numLevels; - GLint log2Width, log2Height, log2Depth; - GLuint uTexelPitch; - - if (!t->image_override) - { - if(GL_FALSE == r700GetTexFormat(tObj, baseImage->TexFormat->MesaFormat) ) - { - _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__); - return; - } - } - - texelBytes = baseImage->TexFormat->TexelBytes; - - switch (tObj->Target) - { - case GL_TEXTURE_1D: - SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, SQ_TEX_DIM_1D, DIM_shift, DIM_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, 0, TEX_DEPTH_shift, TEX_DEPTH_mask); - break; - case GL_TEXTURE_2D: - case GL_TEXTURE_RECTANGLE_NV: - SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, SQ_TEX_DIM_2D, DIM_shift, DIM_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, 0, TEX_DEPTH_shift, TEX_DEPTH_mask); - break; - case GL_TEXTURE_3D: - SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, SQ_TEX_DIM_3D, DIM_shift, DIM_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, tObj->Image[0][t->base.firstLevel]->Depth - 1, - TEX_DEPTH_shift, TEX_DEPTH_mask); - break; - case GL_TEXTURE_CUBE_MAP: - SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, SQ_TEX_DIM_CUBEMAP, DIM_shift, DIM_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, 0, TEX_DEPTH_shift, TEX_DEPTH_mask); - break; - default: - _mesa_problem(NULL, "unexpected texture target type in %s", __FUNCTION__); - return; - } - - /* Compute which mipmap levels we really want to send to the hardware. - */ - driCalculateTextureFirstLastLevel((driTextureObject *) t); - log2Width = tObj->Image[0][t->base.firstLevel]->WidthLog2; - log2Height = tObj->Image[0][t->base.firstLevel]->HeightLog2; - log2Depth = tObj->Image[0][t->base.firstLevel]->DepthLog2; - - numLevels = t->base.lastLevel - t->base.firstLevel + 1; - - assert(numLevels <= RADEON_MAX_TEXTURE_LEVELS); - - /* Calculate mipmap offsets and dimensions for blitting (uploading) - * The idea is that we lay out the mipmap levels within a block of - * memory organized as a rectangle of width BLIT_WIDTH_BYTES. - */ - t->tile_bits = 0; - - curOffset = 0; - - if (tObj->Target == GL_TEXTURE_CUBE_MAP) - { - ASSERT(log2Width == log2Height); - - for(i = 0; i < numLevels; i++) - { - /* i is hw level */ - GLuint face; - for(face = 0; face < 6; face++) - { - compute_tex_image_offset(tObj, face, i, &curOffset); - } - } - } - else - { - for (i = 0; i < numLevels; i++) - { - /* i is hw level */ - compute_tex_image_offset(tObj, 0, i, &curOffset); - } - } - - /* Align the total size of texture memory block. - */ - t->base.totalSize = (curOffset + R700_TEXTURE_ALIGNMENT_MASK) & ~R700_TEXTURE_ALIGNMENT_MASK; - - t->pitch = 0; - - /* TODO : baseImage->IsCompressed, tObj->Target == GL_TEXTURE_RECTANGLE_NV */ - - uTexelPitch = (tObj->Image[0][t->base.firstLevel]->Width + R700_TEXEL_PITCH_ALIGNMENT_MASK) - & ~R700_TEXEL_PITCH_ALIGNMENT_MASK; - - SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, (uTexelPitch/8)-1, PITCH_shift, PITCH_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, tObj->Image[0][t->base.firstLevel]->Width - 1, - TEX_WIDTH_shift, TEX_WIDTH_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, tObj->Image[0][t->base.firstLevel]->Height - 1, - TEX_HEIGHT_shift, TEX_HEIGHT_mask); -#endif /* to be enabled */ -} - -static void r700UploadSubImage(context_t *context, - r700TexObjPtr t, - GLint hwlevel, /* relative level to first real level. */ - GLint x, - GLint y, - GLuint face) -{ -#if 0 /* to be enabled */ - struct gl_texture_image *texImage = NULL; - GLuint offset; - GLint imageWidth, imageHeight; - GLint ret; - const int level = hwlevel + t->base.firstLevel; - - unsigned char *pSrc; - - ASSERT(face < 6); - - /* Ensure we have a valid texture to upload */ - if ((hwlevel < 0) || (hwlevel >= RADEON_MAX_TEXTURE_LEVELS)) - { - _mesa_problem(NULL, "bad texture level in %s", __FUNCTION__); - return; - } - - texImage = t->base.tObj->Image[face][level]; - - if (!texImage) - { - return; - } - if (!texImage->Data) - { - return; - } - - if (t->base.tObj->Target == GL_TEXTURE_RECTANGLE_NV) - { - /* TODO : - assert(level == 0); - assert(hwlevel == 0); - - r300UploadRectSubImage(rmesa, t, texImage, x, y, width, height); - */ - return; - } - else if (texImage->IsClientData) - { - /* TODO : - r300UploadGARTClientSubImage(rmesa, t, texImage, hwlevel, x, y, - width, height); - */ - return; - } - - imageWidth = texImage->Width; - imageHeight = texImage->Height; - - /* use hwlevel for hwsurf. */ - offset = t->bufAddr + t->level_offset[face][hwlevel]; - - pSrc = (unsigned char*)(texImage->Data); - - (context->chipobj.LoadMemSurf)(context, - offset, /* gpu addr */ - t->texel_pitch[face][hwlevel], /* dst_pitch_in_pixel */ - t->src_width_in_pexel[face][hwlevel], /*src_width_in_pixel */ - t->src_hight_in_pexel[face][hwlevel], /* height */ - t->byte_per_texel, /* byte_per_pixel */ - pSrc); /* source data */ -#endif /* to be enabled */ -} - -int r700UploadTexImages(GLcontext * ctx, struct gl_texture_object *tObj, GLuint face) -{ -#if 0 /* to be enabled */ - context_t *context = R700_CONTEXT(ctx); - r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; - - int heap; - const int numLevels = t->base.lastLevel - t->base.firstLevel + 1; - - if (t->image_override) - { - return 0; - } - - if (t->base.totalSize == 0) - { - return 0; - } - /* TODO */ - /*LOCK_HARDWARE(&rmesa->radeon);*/ - - if (t->base.memBlock == NULL) - { - heap = RADEON_LOCAL_TEX_HEAP; - if( GL_FALSE == (context->chipobj.AllocMemSurf)(context, - &(t->base.memBlock), - &(t->base.heap), - &heap, /* prefered_heap, also return the actual heap used. */ - t->base.totalSize) ) - { - /* TODO */ - /* UNLOCK_HARDWARE(&rmesa->radeon); */ - return -1; - } - - /* Set the base offset of the texture image */ - t->bufAddr = context->screen->texOffset[heap] + t->base.memBlock->ofs; - t->offset = t->bufAddr; - - /* - if (!(t->base.tObj->Image[0][0]->IsClientData)) - { - t->offset |= t->tile_bits; - } - */ - } - - /* Let the world know we've used this memory recently. - */ - driUpdateTextureLRU((driTextureObject *) t); - - /* TODO */ - /* UNLOCK_HARDWARE(&rmesa->radeon); */ - - /* Upload any images that are new */ - if (t->my_dirty_images[face]) - { - int i; - for(i = 0; i < numLevels; i++) - { - if( (t->my_dirty_images[face] & (1 << (i + t->base.firstLevel))) !=0) - { - r700UploadSubImage(context, - t, - i, /* i is hw level */ - 0, - 0, - face); - } - } - t->base.dirty_images[face] = 0; - t->my_dirty_images[face] = 0; - } - - /* TODO : 3D, CUBE */ - t->texture_state.SQ_TEX_RESOURCE2.u32All = t->bufAddr / 256; - if( (t->base.lastLevel - t->base.firstLevel) > 0 ) - { - t->texture_state.SQ_TEX_RESOURCE3.u32All = (t->bufAddr + t->level_offset[0][1]) / 256; /* MIP_ADDRESS */ - - SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, t->base.firstLevel, BASE_LEVEL_shift, BASE_LEVEL_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE5.u32All, t->base.lastLevel, LAST_LEVEL_shift, LAST_LEVEL_mask); - } -#endif /* to be enabled */ - return 0; -} - -static GLboolean r700EnableTexture2D(GLcontext * ctx, int unit) -{ - context_t *context = R700_CONTEXT(ctx); - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - struct gl_texture_object *tObj = texUnit->_Current; - r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; - - ASSERT(tObj->Target == GL_TEXTURE_2D || tObj->Target == GL_TEXTURE_1D); - - if (t->base.dirty_images[0]) - { - r700SetTexImages(context, tObj); - r700UploadTexImages(ctx, tObj, 0); - if (!t->base.memBlock && !t->image_override) - { - return GL_FALSE; - } - } - return GL_TRUE; -} - -/* try to find a format which will only need a memcopy */ -static const struct gl_texture_format *r700Choose8888TexFormat(GLenum srcFormat, - GLenum srcType) -{ - struct gl_texture_format * gtfRet; - - const GLuint ui = 1; - const GLubyte littleEndian = *((const GLubyte *)&ui); - - if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8) || - (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && !littleEndian) || - (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || - (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && littleEndian)) - { - gtfRet = &_mesa_texformat_rgba8888; - } - else if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || - (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && littleEndian) || - (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8) || - (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && !littleEndian)) - { - gtfRet = &_mesa_texformat_rgba8888_rev; - } - else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && !littleEndian) || - srcType == GL_UNSIGNED_INT_8_8_8_8)) - { - gtfRet = &_mesa_texformat_argb8888_rev; - } - else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && littleEndian) || - srcType == GL_UNSIGNED_INT_8_8_8_8_REV)) - { - gtfRet = &_mesa_texformat_argb8888; - } - else - { - gtfRet = _dri_texformat_argb8888; - } - - return gtfRet; -} - -static r700TexObjPtr r700AllocTexObj(struct gl_texture_object *texObj) -{ - r700TexObjPtr t; - - t = CALLOC_STRUCT(r700_tex_obj); - texObj->DriverData = t; - if (t != NULL) - { -#if 0 /* to be enabled */ - /* Initialize non-image-dependent parts of the state: - */ - t->base.tObj = texObj; - t->border_fallback = GL_FALSE; - - make_empty_list(&t->base); - - /* Init text object to default states. */ - t->texture_state.SQ_TEX_RESOURCE0.u32All = 0; - SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, SQ_TEX_DIM_2D, DIM_shift, DIM_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE0.u32All, ARRAY_LINEAR_GENERAL, - SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift, SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask); - CLEARbit(t->texture_state.SQ_TEX_RESOURCE0.u32All, TILE_TYPE_bit); - - t->texture_state.SQ_TEX_RESOURCE1.u32All = 0; - SETfield(t->texture_state.SQ_TEX_RESOURCE1.u32All, FMT_8_8_8_8, - SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); - - t->texture_state.SQ_TEX_RESOURCE2.u32All = 0; - t->texture_state.SQ_TEX_RESOURCE3.u32All = 0; - - t->texture_state.SQ_TEX_RESOURCE4.u32All = 0; - SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_FORMAT_COMP_UNSIGNED, - FORMAT_COMP_X_shift, FORMAT_COMP_X_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_FORMAT_COMP_UNSIGNED, - FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_FORMAT_COMP_UNSIGNED, - FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_FORMAT_COMP_UNSIGNED, - FORMAT_COMP_W_shift, FORMAT_COMP_W_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_NUM_FORMAT_NORM, - SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift, SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_mask); - CLEARbit(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit); - CLEARbit(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit); - SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, SQ_ENDIAN_NONE, - SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift, SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_mask); - SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, 1, REQUEST_SIZE_shift, REQUEST_SIZE_mask); - t->texture_state.SQ_TEX_RESOURCE4.u32All |= SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift - |SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift - |SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift - |SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift; - SETfield(t->texture_state.SQ_TEX_RESOURCE4.u32All, 0, BASE_LEVEL_shift, BASE_LEVEL_mask); /* mip-maps */ - - t->texture_state.SQ_TEX_RESOURCE5.u32All = 0; - - t->texture_state.SQ_TEX_RESOURCE6.u32All = 0; - - SETfield(t->texture_state.SQ_TEX_RESOURCE6.u32All, SQ_TEX_VTX_VALID_TEXTURE, - SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask); - - /* Initialize sampler registers */ - t->sampler_state.SQ_TEX_SAMPLER0.u32All = 0; - t->sampler_state.SQ_TEX_SAMPLER0.u32All |= - SQ_TEX_WRAP << SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift - |SQ_TEX_WRAP << CLAMP_Y_shift - |SQ_TEX_WRAP << CLAMP_Z_shift - |SQ_TEX_XY_FILTER_POINT << XY_MAG_FILTER_shift - |SQ_TEX_XY_FILTER_POINT << XY_MIN_FILTER_shift - |SQ_TEX_Z_FILTER_NONE << Z_FILTER_shift - |SQ_TEX_Z_FILTER_NONE << MIP_FILTER_shift - |SQ_TEX_BORDER_COLOR_TRANS_BLACK << BORDER_COLOR_TYPE_shift; - - t->sampler_state.SQ_TEX_SAMPLER1.u32All = 0x7FF << MAX_LOD_shift; - - t->sampler_state.SQ_TEX_SAMPLER2.u32All = 0; - SETbit(t->sampler_state.SQ_TEX_SAMPLER2.u32All, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit); -#endif /* to be enabled */ - } - - return t; -} - -static GLboolean -r700ValidateClientStorage(GLcontext * ctx, GLenum target, - GLint internalFormat, - GLint srcWidth, GLint srcHeight, - GLenum format, GLenum type, const void *pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - if (!ctx->Unpack.ClientStorage) - { - return 0; - } - - if (ctx->_ImageTransferState || - texImage->IsCompressed || texObj->GenerateMipmap) - { - return 0; - } - - /* This list is incomplete, may be different on ppc??? - */ - switch (internalFormat) - { - case GL_RGBA: - if (format == GL_BGRA && type == GL_UNSIGNED_INT_8_8_8_8_REV) - { - texImage->TexFormat = _dri_texformat_argb8888; - } - else - { - return 0; - } - break; - - case GL_RGB: - if (format == GL_RGB && type == GL_UNSIGNED_SHORT_5_6_5) - { - texImage->TexFormat = _dri_texformat_rgb565; - } - else - { - return 0; - } - break; - - case GL_YCBCR_MESA: - if (format == GL_YCBCR_MESA && - type == GL_UNSIGNED_SHORT_8_8_REV_APPLE) - { - texImage->TexFormat = &_mesa_texformat_ycbcr_rev; - } - else if( format == GL_YCBCR_MESA && - (type == GL_UNSIGNED_SHORT_8_8_APPLE || type == GL_UNSIGNED_BYTE)) - { - texImage->TexFormat = &_mesa_texformat_ycbcr; - } - else - { - return 0; - } - break; - - default: - return 0; - } - - /* Could deal with these packing issues, but currently don't: - */ - if (packing->SkipPixels || - packing->SkipRows || packing->SwapBytes || packing->LsbFirst) - { - return 0; - } - - GLint srcRowStride = _mesa_image_row_stride(packing, srcWidth, format, type); - - /* Have validated that _mesa_transfer_teximage would be a straight - * memcpy at this point. NOTE: future calls to TexSubImage will - * overwrite the client data. This is explicitly mentioned in the - * extension spec. - */ - texImage->Data = (void *)pixels; - texImage->IsClientData = GL_TRUE; - texImage->RowStride = srcRowStride / texImage->TexFormat->TexelBytes; - - return 1; -} - -static void r700TexImage1D(GLcontext * ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint border, - GLenum format, GLenum type, const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ -} - -static void r700TexImage2D(GLcontext * ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint height, GLint border, - GLenum format, GLenum type, const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ -#if 0 /* to be enabled */ - r700TexObjPtr r700t = (r700TexObjPtr) texObj->DriverData; - - driTextureObject *t = (driTextureObject *) texObj->DriverData; - GLuint face; - - /* which cube face or ordinary 2D image */ - switch (target) - { - case GL_TEXTURE_CUBE_MAP_POSITIVE_X: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_X: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Y: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y: - case GL_TEXTURE_CUBE_MAP_POSITIVE_Z: - case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z: - face = (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X; - ASSERT(face < 6); - break; - default: - face = 0; - } - - if (t != NULL) - { - driSwapOutTextureObject(t); - } - else - { - t = (driTextureObject *) r700AllocTexObj(texObj); - if (!t) - { - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage2D"); - return; - } - } - - texImage->IsClientData = GL_FALSE; - - if (r700ValidateClientStorage(ctx, target, - internalFormat, - width, height, - format, type, pixels, - packing, texObj, texImage)) - { - /* client maintained surface */ - } - else - { - /* Normal path: copy (to cached memory) and eventually upload - * via another copy to GART memory and then a blit... Could - * eliminate one copy by going straight to (permanent) GART. - * - * Note, this will call r700ChooseTextureFormat. - */ - _mesa_store_teximage2d(ctx, target, level, internalFormat, - width, height, border, format, type, - pixels, &ctx->Unpack, texObj, texImage); - - t->dirty_images[face] |= (1 << level); - - /* mesa dirty_images is not correct, so use own one for now, review it later. */ - r700t->my_dirty_images[face] |= (1 << level); - } -#endif /* to be enabled */ -} - -static void r700TexImage3D(GLcontext * ctx, GLenum target, GLint level, - GLint internalFormat, - GLint width, GLint height, GLint depth, - GLint border, - GLenum format, GLenum type, const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ -} - -static void r700TexSubImage1D(GLcontext * ctx, GLenum target, GLint level, - GLint xoffset, - GLsizei width, - GLenum format, GLenum type, - const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ - -} - -static void r700TexSubImage2D(GLcontext * ctx, GLenum target, GLint level, - GLint xoffset, GLint yoffset, - GLsizei width, GLsizei height, - GLenum format, GLenum type, - const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ -} - -static void r700TexSubImage3D(GLcontext * ctx, GLenum target, GLint level, - GLint xoffset, GLint yoffset, GLint zoffset, - GLsizei width, GLsizei height, GLsizei depth, - GLenum format, GLenum type, - const GLvoid * pixels, - const struct gl_pixelstore_attrib *packing, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ -} - -/** - * Allocate a new texture object. - * Called via ctx->Driver.NewTextureObject. - * Note: this function will be called during context creation to - * allocate the default texture objects. - * Note: we could use containment here to 'derive' the driver-specific - * texture object from the core mesa gl_texture_object. Not done at this time. - */ -static struct gl_texture_object *r700NewTextureObject(GLcontext * ctx, - GLuint name, - GLenum target) -{ - context_t *context = R700_CONTEXT(ctx); - - struct gl_texture_object *obj; - - obj = _mesa_new_texture_object(ctx, name, target); - if (!obj) - { - return NULL; - } - - //obj->MaxAnisotropy = context->initialMaxAnisotropy; - - r700AllocTexObj(obj); - - return obj; -} - -static void r700BindTexture(GLcontext * ctx, GLenum target, - struct gl_texture_object *texObj) -{ - if ((target == GL_TEXTURE_1D) - || (target == GL_TEXTURE_2D) - || (target == GL_TEXTURE_3D) - || (target == GL_TEXTURE_CUBE_MAP) - || (target == GL_TEXTURE_RECTANGLE_NV)) - { - assert(texObj->DriverData != NULL); - } -} - -static void r700DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) -{ -} - -#if 0 /* to be enabled */ -static void r700SetTexMinFilter(r700TexObjPtr t, GLenum minf) -{ - switch (minf) - { - case GL_NEAREST: - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Point, - XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_MipFilter_None, - MIP_FILTER_shift, MIP_FILTER_mask); - break; - case GL_LINEAR: - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Linear, - XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_MipFilter_None, - MIP_FILTER_shift, MIP_FILTER_mask); - break; - case GL_NEAREST_MIPMAP_NEAREST: - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Point, - XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_MipFilter_Point, - MIP_FILTER_shift, MIP_FILTER_mask); - break; - case GL_LINEAR_MIPMAP_NEAREST: - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Linear, - XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_MipFilter_Point, - MIP_FILTER_shift, MIP_FILTER_mask); - break; - case GL_NEAREST_MIPMAP_LINEAR: - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Point, - XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_MipFilter_Linear, - MIP_FILTER_shift, MIP_FILTER_mask); - break; - case GL_LINEAR_MIPMAP_LINEAR: - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Linear, - XY_MIN_FILTER_shift, XY_MIN_FILTER_mask); - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_MipFilter_Linear, - MIP_FILTER_shift, MIP_FILTER_mask); - break; - default: - /* no case */ - break; - } -} - -static void r700SetTexMagFilter(r700TexObjPtr t, GLenum magf) -{ - switch(magf) - { - case GL_NEAREST: - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Point, - XY_MAG_FILTER_shift, XY_MAG_FILTER_mask); - - break; - case GL_LINEAR: - - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, TEX_XYFilter_Linear, - XY_MAG_FILTER_shift, XY_MAG_FILTER_mask); - - break; - default: - break; - } -} - -static unsigned int r700GetWrapMode(GLenum wrapmode) -{ - switch(wrapmode) - { - case GL_REPEAT: - return SQ_TEX_WRAP; - case GL_CLAMP: - return SQ_TEX_CLAMP_HALF_BORDER; - case GL_CLAMP_TO_EDGE: - return SQ_TEX_CLAMP_LAST_TEXEL; - case GL_CLAMP_TO_BORDER: - return SQ_TEX_CLAMP_BORDER; - case GL_MIRRORED_REPEAT: - return SQ_TEX_MIRROR_ONCE_HALF_BORDER; - case GL_MIRROR_CLAMP_EXT: - return SQ_TEX_MIRROR; - case GL_MIRROR_CLAMP_TO_EDGE_EXT: - return SQ_TEX_MIRROR_ONCE_BORDER; - case GL_MIRROR_CLAMP_TO_BORDER_EXT: - return SQ_TEX_MIRROR_ONCE_LAST_TEXEL; - default: - _mesa_problem(NULL, "bad wrap mode in %s", __FUNCTION__); - return 0; - } -} -#endif /* to be enabled */ - -static void r700TexParameter(GLcontext * ctx, GLenum target, - struct gl_texture_object *texObj, - GLenum pname, const GLfloat * params) -{ - r700TexObjPtr t = (r700TexObjPtr) texObj->DriverData; -#if 0 /* to be enabled */ - switch (pname) - { - case GL_TEXTURE_MIN_FILTER: - r700SetTexMinFilter(t, texObj->MinFilter); - break; - case GL_TEXTURE_MAG_FILTER: - r700SetTexMagFilter(t, texObj->MagFilter); - break; - case GL_TEXTURE_MAX_ANISOTROPY_EXT: - - r700SetTexMinFilter(t, texObj->MinFilter); - r700SetTexMagFilter(t, texObj->MagFilter); - - break; - - case GL_TEXTURE_WRAP_S: - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, r700GetWrapMode(texObj->WrapS), - SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift, SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask); - break; - case GL_TEXTURE_WRAP_T: - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, r700GetWrapMode(texObj->WrapT), - CLAMP_Y_shift, CLAMP_Y_mask); - break; - case GL_TEXTURE_WRAP_R: - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, r700GetWrapMode(texObj->WrapR), - CLAMP_Z_shift, CLAMP_Z_mask); - break; - - case GL_TEXTURE_BORDER_COLOR: - /* TODO : set border color regs before rendering. */ - SETfield(t->sampler_state.SQ_TEX_SAMPLER0.u32All, SQ_TEX_BORDER_COLOR_REGISTER, - BORDER_COLOR_TYPE_shift, BORDER_COLOR_TYPE_mask); - break; - - case GL_TEXTURE_BASE_LEVEL: - case GL_TEXTURE_MAX_LEVEL: - case GL_TEXTURE_MIN_LOD: - case GL_TEXTURE_MAX_LOD: - /* TODO : we do support this, add it later. */ - driSwapOutTextureObject((driTextureObject *) t); - break; - - case GL_DEPTH_TEXTURE_MODE: - if (!texObj->Image[0][texObj->BaseLevel]) - { - return; - } - if (texObj->Image[0][texObj->BaseLevel]->TexFormat->BaseFormat - == GL_DEPTH_COMPONENT) - { - /* TODO : r700SetDepthTexMode(texObj); */ - break; - } - else - { - /* If not depth texture, just return. */ - return; - } - - default: - return; - } -#endif /* to be enabled */ -} - -static void r700CompressedTexImage2D(GLcontext * ctx, GLenum target, - GLint level, GLint internalFormat, - GLint width, GLint height, GLint border, - GLsizei imageSize, const GLvoid * data, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ -} - -static void r700CompressedTexSubImage2D(GLcontext * ctx, GLenum target, - GLint level, GLint xoffset, - GLint yoffset, GLsizei width, - GLsizei height, GLenum format, - GLsizei imageSize, const GLvoid * data, - struct gl_texture_object *texObj, - struct gl_texture_image *texImage) -{ -} - -static GLboolean r700UpdateTextureUnit(GLcontext * ctx, int unit) -{ - return GL_TRUE; -} - -static GLboolean r700EnableTextureRect(GLcontext * ctx, int unit) -{ - return GL_TRUE; -} - -static GLboolean r700EnableTexture3D(GLcontext * ctx, int unit) -{ - return GL_TRUE; -} - -static GLboolean r700EnableTextureCube(GLcontext * ctx, int unit) -{ - return GL_TRUE; -} - -static GLboolean r700UpdateTexture(GLcontext * ctx, int unit) -{ -#if 0 /* to be enabled */ - context_t *context = R700_CONTEXT(ctx); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj); - - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - struct gl_texture_object *tObj = texUnit->_Current; - r700TexObjPtr t = (r700TexObjPtr) tObj->DriverData; - - if( r700->texture_states.textures[unit] != &(t->texture_state) ) - { - if(NULL != r700->texture_states.textures[unit]) - { /* there is an old one. */ - } - - r700->texture_states.textures[unit] = &(t->texture_state); - r700->texture_states.samplers[unit] = &(t->sampler_state); - driUpdateTextureLRU((driTextureObject *) t); /* XXX: should be locked! */ - } -#endif /* to be enabled */ - - return GL_TRUE; -} - -void r700UpdateTextureState(context_t * context) -{ -#if 0 /* to be enabled */ - GLboolean bRet; - GLuint unit; - GLcontext * ctx = context->ctx; - struct gl_texture_unit *texUnit; - - for (unit = 0; unit < 8; unit++) - { - texUnit = &ctx->Texture.Unit[unit]; - - if (texUnit->_ReallyEnabled & (TEXTURE_RECT_BIT)) - { - bRet = (r700EnableTextureRect(ctx, unit) && - r700UpdateTexture(ctx, unit)); - } - else if (texUnit->_ReallyEnabled & (TEXTURE_1D_BIT | TEXTURE_2D_BIT)) - { - bRet = (r700EnableTexture2D(ctx, unit) && - r700UpdateTexture(ctx, unit)); - } - else if (texUnit->_ReallyEnabled & (TEXTURE_3D_BIT)) - { - bRet = (r700EnableTexture3D(ctx, unit) && - r700UpdateTexture(ctx, unit)); - } - else if (texUnit->_ReallyEnabled & (TEXTURE_CUBE_BIT)) - { - bRet = (r700EnableTextureCube(ctx, unit) && - r700UpdateTexture(ctx, unit)); - } - else if (texUnit->_ReallyEnabled) - { - bRet = GL_FALSE; - } - else - { - bRet = GL_TRUE; - } - - if (!bRet) - { - _mesa_warning(ctx, "failed to update texture state for unit %d.\n", unit); - } - } -#endif /* to be enabled */ -} - -/** - * Ensure all enabled and complete textures are uploaded along with any buffers being used. - */ -GLboolean r700ValidateBuffers(GLcontext * ctx) -{ - /* TODO */ - - return radeon_revalidate_bos(ctx); -} - -void r700InitTextureFuncs(struct dd_function_table *functions) -{ - /* Note: we only plug in the functions we implement in the driver - * since _mesa_init_driver_functions() was already called. - */ - functions->ChooseTextureFormat = radeonChooseTextureFormat_mesa; - functions->TexImage1D = r700TexImage1D; - functions->TexImage2D = r700TexImage2D; - functions->TexImage3D = r700TexImage3D; - functions->TexSubImage1D = r700TexSubImage1D; - functions->TexSubImage2D = r700TexSubImage2D; - functions->TexSubImage3D = r700TexSubImage3D; - functions->NewTextureObject = r700NewTextureObject; - functions->BindTexture = r700BindTexture; - functions->DeleteTexture = r700DeleteTexture; - functions->IsTextureResident = driIsTextureResident; - - functions->TexParameter = r700TexParameter; - - functions->CompressedTexImage2D = r700CompressedTexImage2D; - functions->CompressedTexSubImage2D = r700CompressedTexSubImage2D; - - driInitTextureFormats(); -} - - diff --git a/src/mesa/drivers/dri/r600/r700_tex.h b/src/mesa/drivers/dri/r600/r700_tex.h deleted file mode 100644 index e322bbc47d..0000000000 --- a/src/mesa/drivers/dri/r600/r700_tex.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * Authors: - * Richard Li , - */ - -#ifndef __r700_TEX_H__ -#define __r700_TEX_H__ - -#include "texmem.h" - -#include "r700_chip.h" - -/* TODO : review this after texture load code. */ -#define R700_BLIT_WIDTH_BYTES 1024 -/* The BASE_ADDRESS and MIP_ADDRESS fields are 256-byte-aligned */ -#define R700_TEXTURE_ALIGNMENT_MASK 0x255 -/* Texel pitch is 8 alignment. */ -#define R700_TEXEL_PITCH_ALIGNMENT_MASK 0x7 - -#define R700_MAX_TEXTURE_UNITS 8 /* TODO : should be 16, lets make it work, review later */ - -typedef struct r700_tex_obj r700TexObj, *r700TexObjPtr; - -/* Texture object in locally shared texture space. - */ -struct r700_tex_obj -{ - driTextureObject base; - - /* r300 tex obj */ - GLuint bufAddr; - GLboolean image_override; - GLuint pitch; - GLuint filter; - GLuint filter_1; - GLuint pitch_reg; - GLuint size; - GLuint format; - GLuint offset; - GLuint unknown4; - GLuint unknown5; - GLboolean border_fallback; - GLuint tile_bits; - - /* r700 texture states */ - TEXTURE_STATE_STRUCT texture_state; - SAMPLER_STATE_STRUCT sampler_state; - - GLuint texel_pitch[6][RADEON_MAX_TEXTURE_LEVELS]; - GLuint level_offset[6][RADEON_MAX_TEXTURE_LEVELS]; - GLuint byte_per_texel; - GLuint src_width_in_pexel[6][RADEON_MAX_TEXTURE_LEVELS]; - GLuint src_hight_in_pexel[6][RADEON_MAX_TEXTURE_LEVELS]; - - GLuint my_dirty_images[6]; /* TODO : review */ -}; - -extern void r700SetTexBuffer(__DRIcontext *pDRICtx, GLint target, - __DRIdrawable *dPriv); - -extern void r700SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, - GLint format, __DRIdrawable *dPriv); - -extern void r700SetTexOffset(__DRIcontext *pDRICtx, GLint texname, - unsigned long long offset, GLint depth, - GLuint pitch); - -extern GLuint r700GetTexObjSize(void); -extern void r700UpdateTextureState(context_t * context); - -extern void r700SetTexOffset(__DRIcontext *pDRICtx, - GLint texname, - unsigned long long offset, - GLint depth, - GLuint pitch); - -extern void r700DestroyTexObj(context_t rmesa, r700TexObjPtr t); - -extern GLboolean r700ValidateBuffers(GLcontext * ctx); - -extern void r700InitTextureFuncs(struct dd_function_table *functions); - -#endif /* __r700_TEX_H__ */ diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index 96bc685876..43e705ee59 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -227,6 +227,19 @@ struct radeon_tex_obj { GLuint pp_txfilter_1; /* r300 */ + /* r700 texture states */ + GLuint SQ_TEX_RESOURCE0; + GLuint SQ_TEX_RESOURCE1; + GLuint SQ_TEX_RESOURCE2; + GLuint SQ_TEX_RESOURCE3; + GLuint SQ_TEX_RESOURCE4; + GLuint SQ_TEX_RESOURCE5; + GLuint SQ_TEX_RESOURCE6; + + GLuint SQ_TEX_SAMPLER0; + GLuint SQ_TEX_SAMPLER1; + GLuint SQ_TEX_SAMPLER2; + GLboolean border_fallback; diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index e23d53c7a1..355fa8683a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -62,7 +62,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) #include "r600_context.h" #include "r700_driconf.h" /* +r6/r7 */ -#include "r700_tex.h" /* +r6/r7 */ +#include "r600_tex.h" /* +r6/r7 */ #endif #include "utils.h" @@ -405,13 +405,13 @@ static const __DRItexBufferExtension r300TexBufferExtension = { #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) static const __DRItexOffsetExtension r600texOffsetExtension = { { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, - r700SetTexOffset, /* +r6/r7 */ + r600SetTexOffset, /* +r6/r7 */ }; static const __DRItexBufferExtension r600TexBufferExtension = { { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, - r700SetTexBuffer, /* +r6/r7 */ - r700SetTexBuffer2, /* +r6/r7 */ + r600SetTexBuffer, /* +r6/r7 */ + r600SetTexBuffer2, /* +r6/r7 */ }; #endif -- cgit v1.2.3 From 6799bc0b6ba1c1052a247cbae0ef660ad5aba84c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 7 Jul 2009 01:02:08 -0400 Subject: tex wip --- src/mesa/drivers/dri/r600/r600_tex.c | 3 +-- src/mesa/drivers/dri/r600/r700_render.c | 3 --- 2 files changed, 1 insertion(+), 5 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r600_tex.c b/src/mesa/drivers/dri/r600/r600_tex.c index 5845c05810..43d9f641af 100644 --- a/src/mesa/drivers/dri/r600/r600_tex.c +++ b/src/mesa/drivers/dri/r600/r600_tex.c @@ -351,9 +351,8 @@ static void r600DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) } if (rmesa) { - // fixme int i; - //radeon_firevertices(&rmesa->radeon); + radeon_firevertices(&rmesa->radeon); for(i = 0; i < R700_MAX_TEXTURE_UNITS; ++i) if (rmesa->hw.textures[i] == t) diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index b29a1aa918..bcafdfbd27 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -264,9 +264,6 @@ static GLboolean r700RunRender(GLcontext * ctx, fp->r700AsmCode.bR6xx = 1; } - if (!r600ValidateBuffers(ctx)) - return GL_TRUE; - r700Start3D(context); /* TODO : this is too much. */ r700SyncSurf(context); /* TODO : make it light. */ -- cgit v1.2.3 From 0396795689dd82be31d22be83307511d223ebcf2 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 7 Jul 2009 15:40:28 -0400 Subject: R6xx/R7xx: fix texture reloc emit Textures don't look right yet, but tex demos run. --- src/mesa/drivers/dri/r600/r700_render.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index bcafdfbd27..413c611cb4 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -145,15 +145,17 @@ GLboolean r700SendTextureState(context_t *context) else bo = t->bo; if (bo) { - BEGIN_BATCH_NO_AUTOSTATE(14); + BEGIN_BATCH_NO_AUTOSTATE(9); R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); R600_OUT_BATCH(i * 7); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1); + printf("tex base\n"); R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2, bo, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod); + printf("tex mipbase\n"); R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3, bo, 0, @@ -161,7 +163,9 @@ GLboolean r700SendTextureState(context_t *context) R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6); + END_BATCH(); + BEGIN_BATCH_NO_AUTOSTATE(5); R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3)); R600_OUT_BATCH(i * 3); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0); -- cgit v1.2.3 From f9db04878bc08931766bd827417012c30887bb7c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 7 Jul 2009 15:44:44 -0400 Subject: R6xx/r7xx: remove some left over debugging --- src/mesa/drivers/dri/r600/r700_render.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 413c611cb4..6ce4c4d40c 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -150,12 +150,10 @@ GLboolean r700SendTextureState(context_t *context) R600_OUT_BATCH(i * 7); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1); - printf("tex base\n"); R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2, bo, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod); - printf("tex mipbase\n"); R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3, bo, 0, -- cgit v1.2.3 From 92a2f0164aece1584e7c4ea8c5c44af43a1de8c3 Mon Sep 17 00:00:00 2001 From: Kevin DeKorte Date: Wed, 15 Jul 2009 17:13:09 -0400 Subject: R6xx/r7xx: warning fixes --- src/mesa/drivers/dri/r600/r600_context.h | 4 ++++ src/mesa/drivers/dri/r600/r700_chip.c | 5 ++++- src/mesa/drivers/dri/r600/r700_chip.h | 1 + src/mesa/drivers/dri/r600/r700_render.c | 8 ++++++++ src/mesa/drivers/dri/r600/r700_state.h | 3 +++ 5 files changed, 20 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index d360f1a2f5..7957be6e0d 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -53,6 +53,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. struct r600_context; typedef struct r600_context context_t; +GLboolean r700SendPSState(context_t *context); +GLboolean r700SendVSState(context_t *context); +GLboolean r700SendSQConfig(context_t *context); + #include "main/mm.h" /* From http://gcc. gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html . diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index b40550d683..535f55525e 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -47,6 +47,9 @@ do \ pStateListWork++; \ }while(0) +inline GLboolean needRelocReg(context_t *context, unsigned int reg); +inline static GLboolean setRelocReg(context_t *context, unsigned int reg); + GLboolean r700InitChipObject(context_t *context) { ContextState * pStateListWork; @@ -421,7 +424,7 @@ inline GLboolean needRelocReg(context_t *context, unsigned int reg) return GL_FALSE; } -inline GLboolean setRelocReg(context_t *context, unsigned int reg) +inline static GLboolean setRelocReg(context_t *context, unsigned int reg) { BATCH_LOCALS(&context->radeon); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h index 41654fd563..691e9dd741 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.h +++ b/src/mesa/drivers/dri/r600/r700_chip.h @@ -55,6 +55,7 @@ #define ASIC_CONTEXT_BASE_INDEX 0xA000 #define ASIC_CTL_CONST_BASE_INDEX 0xF3FC + enum { SQ_ABSOLUTE = 0x00000000, diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 6ce4c4d40c..9b9d35412e 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -54,6 +54,14 @@ #include "r700_fragprog.h" #include "r700_state.h" +void r700WaitForIdle(context_t *context); +void r700WaitForIdleClean(context_t *context); +void r700Start3D(context_t *context); +GLboolean r700SendTextureState(context_t *context); +GLboolean r700SyncSurf(context_t *context); +unsigned int r700PrimitiveType(int prim); +void r600UpdateTextureState(GLcontext * ctx); + void r700WaitForIdle(context_t *context) { BATCH_LOCALS(&context->radeon); diff --git a/src/mesa/drivers/dri/r600/r700_state.h b/src/mesa/drivers/dri/r600/r700_state.h index 87f0903b67..23246367db 100644 --- a/src/mesa/drivers/dri/r600/r700_state.h +++ b/src/mesa/drivers/dri/r600/r700_state.h @@ -45,4 +45,7 @@ extern void r700InitStateFuncs (struct dd_function_table *functions); extern void r700SetRenderTarget(context_t *context, int id); extern void r700SetDefaultStates(context_t * context); +void r700SetScissor(context_t *context); +void r700SetDepthTarget(context_t *context); + #endif /* _R600_SCREEN_H */ -- cgit v1.2.3 From 6f63698d2678790bef4d4b84d52c9a15cdb2de1c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Jul 2009 17:35:44 -0400 Subject: R6xx: fix rendering on r6xx/rs780 chips You always need to emit a fetch shader (fs) even if you aren't using it. For now, just emit the fs with the vs address to make the kernel happy. --- src/mesa/drivers/dri/r600/r700_chip.c | 41 +++++++++++++++++++++++++++++++++ src/mesa/drivers/dri/r600/r700_chip.h | 2 +- src/mesa/drivers/dri/r600/r700_render.c | 1 + 3 files changed, 43 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index b944f5466e..a0506fc124 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -638,6 +638,47 @@ GLboolean r700SendVSState(context_t *context) return GL_TRUE; } +GLboolean r700SendFSState(context_t *context) +{ + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + struct radeon_renderbuffer *rrb; + struct radeon_bo * pbo; + offset_modifiers offset_mod; + BATCH_LOCALS(&context->radeon); + + /* XXX fixme + * R6xx chips require a FS be emitted, even if it's not used. + * since we aren't using FS yet, just send the VS address to make + * the kernel command checker happy + */ + pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); + r700->fs.SQ_PGM_START_FS.u32All = r700->vs.SQ_PGM_START_VS.u32All; + r700->fs.SQ_PGM_RESOURCES_FS.u32All = 0; + r700->fs.SQ_PGM_CF_OFFSET_FS.u32All = 0; + /* XXX */ + + offset_mod.shift = NO_SHIFT; + offset_mod.shiftbits = 0; + offset_mod.mask = 0xFFFFFFFF; + + BEGIN_BATCH_NO_AUTOSTATE(3); + R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1); + R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All, + pbo, + r700->fs.SQ_PGM_START_FS.u32All, + RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + END_BATCH(); + + BEGIN_BATCH_NO_AUTOSTATE(6); + R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS, r700->fs.SQ_PGM_RESOURCES_FS.u32All); + R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS, r700->fs.SQ_PGM_CF_OFFSET_FS.u32All); + END_BATCH(); + + COMMIT_BATCH(); + + return GL_TRUE; +} + GLboolean r700SendViewportState(context_t *context, int id) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h index 691e9dd741..f27d3c055f 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.h +++ b/src/mesa/drivers/dri/r600/r700_chip.h @@ -491,7 +491,7 @@ typedef struct _R700_CHIP_CONTEXT VS_STATE_STRUCT vs; GS_STATE_STRUCT gs; ES_STATE_STRUCT es; - PS_STATE_STRUCT fs; + FS_STATE_STRUCT fs; // SQ CONFIG SQ_CONFIG_STRUCT sq_config; diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 9b9d35412e..8c82f2aa5a 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -311,6 +311,7 @@ static GLboolean r700RunRender(GLcontext * ctx, r700SetupShaders(ctx); + r700SendFSState(context); // FIXME just a place holder for now r700SendPSState(context); r700SendVSState(context); -- cgit v1.2.3 From b192b9dac628665d6dc37fc98b5f635fc7a45159 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 17 Jul 2009 17:08:40 -0400 Subject: R6xx/r7xx: send depth state in it's own function --- src/mesa/drivers/dri/r600/r700_chip.c | 159 +++++++++++++------------------- src/mesa/drivers/dri/r600/r700_render.c | 2 +- 2 files changed, 65 insertions(+), 96 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index eefbe22668..383d8bfb39 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -47,9 +47,6 @@ do \ pStateListWork++; \ }while(0) -inline GLboolean needRelocReg(context_t *context, unsigned int reg); -inline static GLboolean setRelocReg(context_t *context, unsigned int reg); - GLboolean r700InitChipObject(context_t *context) { ContextState * pStateListWork; @@ -67,23 +64,6 @@ GLboolean r700InitChipObject(context_t *context) LINK_STATES(DB_DEBUG); LINK_STATES(DB_WATERMARKS); - // DB - LINK_STATES(DB_DEPTH_SIZE); - LINK_STATES(DB_DEPTH_VIEW); - LINK_STATES(DB_DEPTH_BASE); - LINK_STATES(DB_DEPTH_INFO); - LINK_STATES(DB_HTILE_DATA_BASE); - LINK_STATES(DB_STENCIL_CLEAR); - LINK_STATES(DB_DEPTH_CLEAR); - LINK_STATES(DB_STENCILREFMASK); - LINK_STATES(DB_STENCILREFMASK_BF); - LINK_STATES(DB_DEPTH_CONTROL); - LINK_STATES(DB_SHADER_CONTROL); - LINK_STATES(DB_RENDER_CONTROL); - LINK_STATES(DB_RENDER_OVERRIDE); - LINK_STATES(DB_HTILE_SURFACE); - LINK_STATES(DB_ALPHA_TO_MASK); - // SC LINK_STATES(PA_SC_SCREEN_SCISSOR_TL); LINK_STATES(PA_SC_SCREEN_SCISSOR_BR); @@ -402,65 +382,6 @@ int r700SetupStreams(GLcontext * ctx) return R600_FALLBACK_NONE; } -inline GLboolean needRelocReg(context_t *context, unsigned int reg) -{ - switch (reg + ASIC_CONTEXT_BASE_INDEX) - { - case mmCB_COLOR0_BASE: - case mmCB_COLOR1_BASE: - case mmCB_COLOR2_BASE: - case mmCB_COLOR3_BASE: - case mmCB_COLOR4_BASE: - case mmCB_COLOR5_BASE: - case mmCB_COLOR6_BASE: - case mmCB_COLOR7_BASE: - case mmDB_DEPTH_BASE: - case mmSQ_PGM_START_VS: - case mmSQ_PGM_START_FS: - case mmSQ_PGM_START_ES: - case mmSQ_PGM_START_GS: - case mmSQ_PGM_START_PS: - return GL_TRUE; - break; - } - - return GL_FALSE; -} - -inline static GLboolean setRelocReg(context_t *context, unsigned int reg) -{ - BATCH_LOCALS(&context->radeon); - R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); - - struct radeon_bo * pbo; - uint32_t voffset; - offset_modifiers offset_mod; - - switch (reg + ASIC_CONTEXT_BASE_INDEX) - { - case mmDB_DEPTH_BASE: - { - GLcontext *ctx = GL_CONTEXT(context); - struct radeon_renderbuffer *rrb; - rrb = radeon_get_depthbuffer(&context->radeon); - - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - - R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All, - rrb->bo, - r700->DB_DEPTH_BASE.u32All, - 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod); - - return GL_TRUE; - } - break; - } - - return GL_FALSE; -} - GLboolean r700SendContextStates(context_t *context) { BATCH_LOCALS(&context->radeon); @@ -478,22 +399,18 @@ GLboolean r700SendContextStates(context_t *context) pInit = pState; - if(GL_FALSE == needRelocReg(context, pState->unOffset)) - { - while(NULL != pState->pNext) - { - if( ((pState->pNext->unOffset - pState->unOffset) > 1) - || (GL_TRUE == needRelocReg(context, pState->pNext->unOffset)) ) + while(NULL != pState->pNext) + { + if ((pState->pNext->unOffset - pState->unOffset) > 1) { - break; + break; } else { - pState = pState->pNext; - toSend++; + pState = pState->pNext; + toSend++; } - }; - } + } pState = pState->pNext; @@ -501,12 +418,8 @@ GLboolean r700SendContextStates(context_t *context) R600_OUT_BATCH_REGSEQ(((pInit->unOffset + ASIC_CONTEXT_BASE_INDEX)<<2), toSend); for(ui=0; uiunOffset) ) - { - /* for not reloc reg. */ R600_OUT_BATCH(*(pInit->puiValue)); - } - pInit = pInit->pNext; + pInit = pInit->pNext; }; END_BATCH(); }; @@ -516,6 +429,62 @@ GLboolean r700SendContextStates(context_t *context) } +GLboolean r700SendDepthTargetState(context_t *context, int id) +{ + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + struct radeon_renderbuffer *rrb; + struct radeon_bo * pbo; + offset_modifiers offset_mod; + BATCH_LOCALS(&context->radeon); + + rrb = radeon_get_depthbuffer(&context->radeon); + if (!rrb || !rrb->bo) { + fprintf(stderr, "no rrb\n"); + return GL_FALSE; + } + + offset_mod.shift = NO_SHIFT; + offset_mod.shiftbits = 0; + offset_mod.mask = 0xFFFFFFFF; + + BEGIN_BATCH_NO_AUTOSTATE(9); + R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2); + R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All); + R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All); + R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 3); + R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All, + rrb->bo, + r700->DB_DEPTH_BASE.u32All, + 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod); + R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All); + R600_OUT_BATCH(r700->DB_HTILE_DATA_BASE.u32All); + END_BATCH(); + + BEGIN_BATCH_NO_AUTOSTATE(24); + R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2); + R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All); + R600_OUT_BATCH(r700->DB_DEPTH_CLEAR.u32All); + + R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2); + R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All); + R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All); + + R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, r700->DB_DEPTH_CONTROL.u32All); + R600_OUT_BATCH_REGVAL(DB_SHADER_CONTROL, r700->DB_SHADER_CONTROL.u32All); + + R600_OUT_BATCH_REGSEQ(DB_RENDER_CONTROL, 2); + R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All); + R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All); + + R600_OUT_BATCH_REGVAL(DB_HTILE_SURFACE, r700->DB_HTILE_SURFACE.u32All); + R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All); + END_BATCH(); + + COMMIT_BATCH(); + + return GL_TRUE; +} + GLboolean r700SendRenderTargetState(context_t *context, int id) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 8c82f2aa5a..532a6e07b7 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -321,7 +321,7 @@ static GLboolean r700RunRender(GLcontext * ctx, r700SendContextStates(context); r700SendViewportState(context, 0); r700SendRenderTargetState(context, 0); - + r700SendDepthTargetState(context); /* richard test code */ for (i = 0; i < vb->PrimitiveCount; i++) -- cgit v1.2.3 From f81f57e25db18b1c69f2f8076380603340fa2cda Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 17 Jul 2009 19:04:19 -0400 Subject: R6xx/R7xx: add fine grained syncing support --- src/mesa/drivers/dri/r600/r600_emit.c | 11 ------ src/mesa/drivers/dri/r600/r700_chip.c | 23 +++++++++-- src/mesa/drivers/dri/r600/r700_render.c | 68 +++++++++++++++------------------ 3 files changed, 50 insertions(+), 52 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r600_emit.c b/src/mesa/drivers/dri/r600/r600_emit.c index ed51e428e9..685f7fe473 100644 --- a/src/mesa/drivers/dri/r600/r600_emit.c +++ b/src/mesa/drivers/dri/r600/r600_emit.c @@ -50,17 +50,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. void r600EmitCacheFlush(context_t *rmesa) { BATCH_LOCALS(&rmesa->radeon); -/* - BEGIN_BATCH_NO_AUTOSTATE(4); - OUT_BATCH_REGVAL(R600_RB3D_DSTCACHE_CTLSTAT, - R600_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS | - R600_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D); - OUT_BATCH_REGVAL(R600_ZB_ZCACHE_CTLSTAT, - R600_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE | - R600_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); - END_BATCH(); - COMMIT_BATCH(); -*/ } GLboolean r600EmitShader(GLcontext * ctx, diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 383d8bfb39..087d17312e 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -294,6 +294,14 @@ void r700SetupVTXConstants(GLcontext * ctx, unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0; unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0; + if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) || + (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) || + (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) || + (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710)) + r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit); + else + r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit); + uSQ_VTX_CONSTANT_WORD0_0 = paos->offset; uSQ_VTX_CONSTANT_WORD1_0 = count * (size * 4) - 1; @@ -433,7 +441,6 @@ GLboolean r700SendDepthTargetState(context_t *context, int id) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_renderbuffer *rrb; - struct radeon_bo * pbo; offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); @@ -482,6 +489,9 @@ GLboolean r700SendDepthTargetState(context_t *context, int id) COMMIT_BATCH(); + r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM, + DB_ACTION_ENA_bit | DB_DEST_BASE_ENA_bit); + return GL_TRUE; } @@ -489,7 +499,6 @@ GLboolean r700SendRenderTargetState(context_t *context, int id) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_renderbuffer *rrb; - struct radeon_bo * pbo; offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); @@ -542,6 +551,9 @@ GLboolean r700SendRenderTargetState(context_t *context, int id) COMMIT_BATCH(); + r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM, + CB_ACTION_ENA_bit | (1 << (id + 6))); + return GL_TRUE; } @@ -559,6 +571,8 @@ GLboolean r700SendPSState(context_t *context) offset_mod.shiftbits = 0; offset_mod.mask = 0xFFFFFFFF; + r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); + BEGIN_BATCH_NO_AUTOSTATE(3); R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1); R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All, @@ -592,6 +606,8 @@ GLboolean r700SendVSState(context_t *context) offset_mod.shiftbits = 0; offset_mod.mask = 0xFFFFFFFF; + r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); + BEGIN_BATCH_NO_AUTOSTATE(3); R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1); R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All, @@ -633,6 +649,8 @@ GLboolean r700SendFSState(context_t *context) offset_mod.shiftbits = 0; offset_mod.mask = 0xFFFFFFFF; + r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); + BEGIN_BATCH_NO_AUTOSTATE(3); R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1); R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All, @@ -655,7 +673,6 @@ GLboolean r700SendViewportState(context_t *context, int id) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_renderbuffer *rrb; - struct radeon_bo * pbo; offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 532a6e07b7..f1e467a317 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -58,9 +58,13 @@ void r700WaitForIdle(context_t *context); void r700WaitForIdleClean(context_t *context); void r700Start3D(context_t *context); GLboolean r700SendTextureState(context_t *context); -GLboolean r700SyncSurf(context_t *context); unsigned int r700PrimitiveType(int prim); void r600UpdateTextureState(GLcontext * ctx); +GLboolean r700SyncSurf(context_t *context, + struct radeon_bo *pbo, + uint32_t read_domain, + uint32_t write_domain, + uint32_t sync_type); void r700WaitForIdle(context_t *context) { @@ -153,6 +157,11 @@ GLboolean r700SendTextureState(context_t *context) else bo = t->bo; if (bo) { + + r700SyncSurf(context, bo, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, + 0, TC_ACTION_ENA_bit); + BEGIN_BATCH_NO_AUTOSTATE(9); R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); R600_OUT_BATCH(i * 7); @@ -185,26 +194,33 @@ GLboolean r700SendTextureState(context_t *context) return GL_TRUE; } -GLboolean r700SyncSurf(context_t *context) +GLboolean r700SyncSurf(context_t *context, + struct radeon_bo *pbo, + uint32_t read_domain, + uint32_t write_domain, + uint32_t sync_type) { BATCH_LOCALS(&context->radeon); + uint32_t cp_coher_size; + offset_modifiers offset_mod; - /* TODO : too heavy? */ - unsigned int CP_COHER_CNTL = 0; - - CP_COHER_CNTL |= (TC_ACTION_ENA_bit - | VC_ACTION_ENA_bit - | CB_ACTION_ENA_bit - | DB_ACTION_ENA_bit - | SH_ACTION_ENA_bit - | SMX_ACTION_ENA_bit); + if (pbo->size == 0xffffffff) + cp_coher_size = 0xffffffff; + else + cp_coher_size = ((pbo->size + 255) >> 8); + offset_mod.shift = NO_SHIFT; + offset_mod.shiftbits = 0; + offset_mod.mask = 0xFFFFFFFF; BEGIN_BATCH_NO_AUTOSTATE(5); R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_SYNC, 3)); - R600_OUT_BATCH(CP_COHER_CNTL); - R600_OUT_BATCH(0xFFFFFFFF); - R600_OUT_BATCH(0x00000000); + R600_OUT_BATCH(sync_type); + R600_OUT_BATCH(cp_coher_size); + R600_OUT_BATCH_RELOC(0, + pbo, + 0, + read_domain, write_domain, 0, &offset_mod); // ??? R600_OUT_BATCH(10); END_BATCH(); @@ -276,8 +292,6 @@ static GLboolean r700RunRender(GLcontext * ctx, r700Start3D(context); /* TODO : this is too much. */ - r700SyncSurf(context); /* TODO : make it light. */ - r700SendSQConfig(context); r700UpdateShaders(ctx); @@ -291,9 +305,6 @@ static GLboolean r700RunRender(GLcontext * ctx, return GL_TRUE; } - /* flush TX */ - //r700SyncSurf(context); /* */ - r600UpdateTextureState(ctx); r700SendTextureState(context); @@ -305,19 +316,12 @@ static GLboolean r700RunRender(GLcontext * ctx, } } - /* flush SQ */ - //r700SyncSurf(context); /* */ - //r700SyncSurf(context); /* */ - r700SetupShaders(ctx); r700SendFSState(context); // FIXME just a place holder for now r700SendPSState(context); r700SendVSState(context); - /* flush vtx */ - //r700SyncSurf(context); /* */ - r700SendContextStates(context); r700SendViewportState(context, 0); r700SendRenderTargetState(context, 0); @@ -375,20 +379,8 @@ static GLboolean r700RunRender(GLcontext * ctx, /* Flush render op cached for last several quads. */ r700WaitForIdleClean(context); - /* flush dst */ - //r700SyncSurf(context); /* */ - radeonReleaseArrays(ctx, 0); - //richard test - /* test stamp, write a number to mmSCRATCH4 */ -#if 0 - BEGIN_BATCH_NO_AUTOSTATE(3); - R600_OUT_BATCH_REGVAL((0x2144 << 2), 0x56785678); - END_BATCH(); - COMMIT_BATCH(); -#endif - #endif //0 rcommonFlushCmdBuf( &context->radeon, __FUNCTION__ ); -- cgit v1.2.3 From a369963b18fc7ef75f6f5354e0d685cef9ecb70d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 20 Jul 2009 17:22:59 -0400 Subject: r600: add user clip plane support --- src/mesa/drivers/dri/r600/r700_chip.c | 22 +++++++++++++++++++++ src/mesa/drivers/dri/r600/r700_render.c | 1 + src/mesa/drivers/dri/r600/r700_state.c | 35 +++++++++++++++++++++++++++++++-- 3 files changed, 56 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 087d17312e..91aa8fc8fc 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -722,3 +722,25 @@ GLboolean r700SendSQConfig(context_t *context) return GL_TRUE; } +GLboolean r700SendUCPState(context_t *context) +{ + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + BATCH_LOCALS(&context->radeon); + int i; + + for (i = 0; i < R700_MAX_UCP; i++) { + if (r700->ucp[i].enabled) { + BEGIN_BATCH_NO_AUTOSTATE(6); + R600_OUT_BATCH_REGSEQ(PA_CL_UCP_0_X + (16 * i), 4); + R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_X.u32All); + R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Y.u32All); + R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Z.u32All); + R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_W.u32All); + END_BATCH(); + COMMIT_BATCH(); + } + } + + return GL_TRUE; +} + diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index f1e467a317..77cbe3cfd0 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -322,6 +322,7 @@ static GLboolean r700RunRender(GLcontext * ctx, r700SendPSState(context); r700SendVSState(context); + r700SendUCPState(context); r700SendContextStates(context); r700SendViewportState(context, 0); r700SendRenderTargetState(context, 0); diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 1ccd793512..1d6d398f63 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -56,6 +56,8 @@ #include "r700_vertprog.h" +static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state); + void r700SetDefaultStates(context_t *context) //-------------------- { @@ -446,7 +448,7 @@ static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //--------- case GL_CLIP_PLANE3: case GL_CLIP_PLANE4: case GL_CLIP_PLANE5: - //r700SetClipPlaneState(ctx, cap, state); + r700SetClipPlaneState(ctx, cap, state); break; case GL_DEPTH_TEST: r700SetDepthState(ctx); @@ -675,8 +677,37 @@ static void r700RenderMode(GLcontext * ctx, GLenum mode) //--------------------- { } -static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) //----------------- +static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) { + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + GLint p; + GLint *ip; + + p = (GLint) plane - (GLint) GL_CLIP_PLANE0; + ip = (GLint *)ctx->Transform._ClipUserPlane[p]; + + r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0]; + r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1]; + r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2]; + r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3]; +} + +static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + GLuint p; + + p = cap - GL_CLIP_PLANE0; + if (state) { + r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p); + r700->ucp[p].enabled = GL_TRUE; + r700ClipPlane(ctx, cap, NULL); + } else { + r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p); + r700->ucp[p].enabled = GL_FALSE; + } } void r700SetScissor(context_t *context) //--------------- -- cgit v1.2.3 From 48b2fea142af93317e095461fc1f7ef6531268c2 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 27 Jul 2009 02:07:59 -0400 Subject: r600: set VGT NUM_INSTANCES as part of the draw command set VGT NUM_INSTANCES as part of the draw command rather than as state as recommended by the pm4 guide. Also, use the NUM_INSTANCES packet. --- src/mesa/drivers/dri/r600/r700_chip.c | 1 - src/mesa/drivers/dri/r600/r700_chip.h | 1 - src/mesa/drivers/dri/r600/r700_render.c | 30 ++++++++++++++++++------------ src/mesa/drivers/dri/r600/r700_state.c | 3 --- 4 files changed, 18 insertions(+), 17 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 899b464c54..e683c8cf92 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -160,7 +160,6 @@ GLboolean r700InitChipObject(context_t *context) LINK_STATES(VGT_GROUP_VECT_1_FMT_CNTL); LINK_STATES(VGT_GS_MODE); LINK_STATES(VGT_PRIMITIVEID_EN); - LINK_STATES(VGT_DMA_NUM_INSTANCES); LINK_STATES(VGT_MULTI_PRIM_IB_RESET_EN); LINK_STATES(VGT_INSTANCE_STEP_RATE_0); LINK_STATES(VGT_INSTANCE_STEP_RATE_1); diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h index fa419aa499..ca3364bb48 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.h +++ b/src/mesa/drivers/dri/r600/r700_chip.h @@ -393,7 +393,6 @@ typedef struct _R700_CHIP_CONTEXT union UINT_FLOAT VGT_GROUP_VECT_1_FMT_CNTL ; /* 0xA28F */ union UINT_FLOAT VGT_GS_MODE ; /* 0xA290 */ union UINT_FLOAT VGT_PRIMITIVEID_EN ; /* 0xA2A1 */ - union UINT_FLOAT VGT_DMA_NUM_INSTANCES ; /* 0xA2A2 */ union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_EN; /* 0xA2A5 */ union UINT_FLOAT VGT_INSTANCE_STEP_RATE_0 ; /* 0xA2A8 */ union UINT_FLOAT VGT_INSTANCE_STEP_RATE_1 ; /* 0xA2A9 */ diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 77cbe3cfd0..0a5e041547 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -329,7 +329,7 @@ static GLboolean r700RunRender(GLcontext * ctx, r700SendDepthTargetState(context); /* richard test code */ - for (i = 0; i < vb->PrimitiveCount; i++) + for (i = 0; i < vb->PrimitiveCount; i++) { GLuint prim = _tnl_translate_prim(&vb->Primitive[i]); GLuint start = vb->Primitive[i].start; @@ -341,25 +341,31 @@ static GLboolean r700RunRender(GLcontext * ctx, unsigned int VGT_INDEX_TYPE = 0; unsigned int VGT_PRIMITIVE_TYPE = 0; unsigned int VGT_NUM_INDICES = 0; - - numEntires = 2 /* VGT_INDEX_TYPE */ - + 3 /* VGT_PRIMITIVE_TYPE */ - + numIndices + 3; /* DRAW_INDEX_IMMD */ - - BEGIN_BATCH_NO_AUTOSTATE(numEntires); - VGT_INDEX_TYPE |= DI_INDEX_SIZE_32_BIT << INDEX_TYPE_shift; - - R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); - R600_OUT_BATCH(VGT_INDEX_TYPE); + numEntires = 3 /* VGT_PRIMITIVE_TYPE */ + + 2 /* VGT_INDEX_TYPE */ + + 2 /* NUM_INSTANCES */ + + numIndices + 3; /* DRAW_INDEX_IMMD */ - VGT_NUM_INDICES = numIndices; + BEGIN_BATCH_NO_AUTOSTATE(numEntires); + // prim VGT_PRIMITIVE_TYPE |= r700PrimitiveType(prim) << VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift; R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); R600_OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); R600_OUT_BATCH(VGT_PRIMITIVE_TYPE); + // index type + VGT_INDEX_TYPE |= DI_INDEX_SIZE_32_BIT << INDEX_TYPE_shift; + R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); + R600_OUT_BATCH(VGT_INDEX_TYPE); + + // num instances + R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0)); + R600_OUT_BATCH(1); + + // draw packet + VGT_NUM_INDICES = numIndices; VGT_DRAW_INITIATOR |= DI_SRC_SEL_IMMEDIATE << SOURCE_SELECT_shift; VGT_DRAW_INITIATOR |= DI_MAJOR_MODE_0 << MAJOR_MODE_shift; diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index a2ddebb1ce..bd0abc06e3 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -1653,9 +1653,6 @@ void r700InitState(GLcontext * ctx) //------------------- r700->VGT_MIN_VTX_INDX.u32All = 0; r700->VGT_INDX_OFFSET.u32All = 0; - /* Specify the number of instances */ - r700->VGT_DMA_NUM_INSTANCES.u32All = 1; - /* default shader connections. */ r700->SPI_VS_OUT_ID_0.u32All = 0x03020100; r700->SPI_VS_OUT_ID_1.u32All = 0x07060504; -- cgit v1.2.3 From 7e6819f8430e77012d6cd9278cabaf1d4238117a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 27 Jul 2009 02:25:24 -0400 Subject: r600: don't draw when num indices is 0 fixes engine demo --- src/mesa/drivers/dri/r600/r700_render.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 0a5e041547..5a2bf84b59 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -342,6 +342,9 @@ static GLboolean r700RunRender(GLcontext * ctx, unsigned int VGT_PRIMITIVE_TYPE = 0; unsigned int VGT_NUM_INDICES = 0; + if (numIndices < 1) + continue; + numEntires = 3 /* VGT_PRIMITIVE_TYPE */ + 2 /* VGT_INDEX_TYPE */ + 2 /* NUM_INSTANCES */ -- cgit v1.2.3 From b1f7c844a38418cbf3fbcef6c2fb0606a1dd6b7e Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 28 Jul 2009 15:53:45 -0400 Subject: r600: move r700TranslateFragmentShader into r700UpdateShaders --- src/mesa/drivers/dri/r600/r700_render.c | 17 ----------------- src/mesa/drivers/dri/r600/r700_state.c | 22 +++++++++++++++++++--- 2 files changed, 19 insertions(+), 20 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 5a2bf84b59..ea8419d3d2 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -276,20 +276,12 @@ static GLboolean r700RunRender(GLcontext * ctx, context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); int lastIndex = 0; -#if 1 BATCH_LOCALS(&context->radeon); unsigned int i, j; TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; - struct r700_fragment_program *fp = (struct r700_fragment_program *) - (ctx->FragmentProgram._Current); - if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) - { - fp->r700AsmCode.bR6xx = 1; - } - r700Start3D(context); /* TODO : this is too much. */ r700SendSQConfig(context); @@ -308,14 +300,6 @@ static GLboolean r700RunRender(GLcontext * ctx, r600UpdateTextureState(ctx); r700SendTextureState(context); - if(GL_FALSE == fp->translated) - { - if( GL_FALSE == r700TranslateFragmentShader(fp, &(fp->mesa_program)) ) - { - return GL_TRUE; - } - } - r700SetupShaders(ctx); r700SendFSState(context); // FIXME just a place holder for now @@ -391,7 +375,6 @@ static GLboolean r700RunRender(GLcontext * ctx, radeonReleaseArrays(ctx, 0); -#endif //0 rcommonFlushCmdBuf( &context->radeon, __FUNCTION__ ); return GL_FALSE; diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 5563a63156..c24c859ef5 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -72,12 +72,28 @@ void r700UpdateShaders (GLcontext * ctx) //---------------------------------- GLvector4f dummy_attrib[_TNL_ATTRIB_MAX]; GLvector4f *temp_attrib[_TNL_ATTRIB_MAX]; - - struct r700_vertex_program *vp; - int i; + int i; + + if (ctx->FragmentProgram._Current) { + struct r700_fragment_program *fp = (struct r700_fragment_program *) + (ctx->FragmentProgram._Current); + if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) + { + fp->r700AsmCode.bR6xx = 1; + } + + if(GL_FALSE == fp->translated) + { + if( GL_FALSE == r700TranslateFragmentShader(fp, &(fp->mesa_program)) ) + { + //return GL_TRUE; + } + } + } if (context->radeon.NewGLState) { + struct r700_vertex_program *vp; context->radeon.NewGLState = 0; for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) -- cgit v1.2.3 From dbdb3952c16e13117891a3c52db4e05c472e96b8 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 28 Jul 2009 15:58:01 -0400 Subject: r600: don't call r700UpdateShaders twice for each render --- src/mesa/drivers/dri/r600/r700_render.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index ea8419d3d2..f2fec27eff 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -403,10 +403,6 @@ static GLboolean r700RunTCLRender(GLcontext * ctx, /*----------------------*/ return GL_TRUE; } - context_t *context = R700_CONTEXT(ctx); - - r700UpdateShaders(ctx); - bRet = r700RunRender(ctx, stage); return bRet; -- cgit v1.2.3 From e629c50e2be03144e8aeef3c51624ae8db9957b8 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 28 Jul 2009 17:59:54 -0400 Subject: r600: implement texture border color --- src/mesa/drivers/dri/r600/r600_tex.c | 14 ++++++-------- src/mesa/drivers/dri/r600/r700_render.c | 9 +++++++++ src/mesa/drivers/dri/radeon/radeon_common_context.h | 5 +++++ 3 files changed, 20 insertions(+), 8 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r600_tex.c b/src/mesa/drivers/dri/r600/r600_tex.c index a1e8945390..444024ee7e 100644 --- a/src/mesa/drivers/dri/r600/r600_tex.c +++ b/src/mesa/drivers/dri/r600/r600_tex.c @@ -269,14 +269,12 @@ static void r600SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloa static void r600SetTexBorderColor(radeonTexObjPtr t, const GLfloat color[4]) { -#if 0 - GLubyte c[4]; - CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]); - CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]); - CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]); - CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]); - t->pp_border_color = PACK_COLOR_8888(c[3], c[0], c[1], c[2]); -#endif + t->TD_PS_SAMPLER0_BORDER_ALPHA = *((uint32_t*)&(color[3])); + t->TD_PS_SAMPLER0_BORDER_RED = *((uint32_t*)&(color[2])); + t->TD_PS_SAMPLER0_BORDER_GREEN = *((uint32_t*)&(color[1])); + t->TD_PS_SAMPLER0_BORDER_BLUE = *((uint32_t*)&(color[0])); + SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_BORDER_COLOR_REGISTER, + BORDER_COLOR_TYPE_shift, BORDER_COLOR_TYPE_mask); } /** diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index f2fec27eff..4e0d5391d0 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -187,6 +187,15 @@ GLboolean r700SendTextureState(context_t *context) R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2); END_BATCH(); + + BEGIN_BATCH_NO_AUTOSTATE(2 + 4); + R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4); + R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED); + R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN); + R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE); + R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA); + END_BATCH(); + COMMIT_BATCH(); } } diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index e4a8da0596..0cdacb1c36 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -239,6 +239,11 @@ struct radeon_tex_obj { GLuint SQ_TEX_SAMPLER1; GLuint SQ_TEX_SAMPLER2; + GLuint TD_PS_SAMPLER0_BORDER_RED; + GLuint TD_PS_SAMPLER0_BORDER_GREEN; + GLuint TD_PS_SAMPLER0_BORDER_BLUE; + GLuint TD_PS_SAMPLER0_BORDER_ALPHA; + GLboolean border_fallback; -- cgit v1.2.3 From 0fdac3529c8a7f7ce41420b79e817407d19a12a2 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 30 Jul 2009 03:30:46 -0400 Subject: r600: fix mipmaps redbook mipmap works --- src/mesa/drivers/dri/r600/r600_texstate.c | 5 +++++ src/mesa/drivers/dri/r600/r700_render.c | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 6918b3b8a1..4840586858 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -610,6 +610,11 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex SETfield(t->SQ_TEX_RESOURCE1, firstImage->Height - 1, TEX_HEIGHT_shift, TEX_HEIGHT_mask); + if ((t->mt->lastLevel - t->mt->firstLevel) > 0) { + t->SQ_TEX_RESOURCE3 = t->mt->levels[0].size / 256; + SETfield(t->SQ_TEX_RESOURCE4, t->mt->firstLevel, BASE_LEVEL_shift, BASE_LEVEL_mask); + SETfield(t->SQ_TEX_RESOURCE5, t->mt->lastLevel, LAST_LEVEL_shift, LAST_LEVEL_mask); + } } /** diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 4e0d5391d0..1810f4be0e 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -173,7 +173,7 @@ GLboolean r700SendTextureState(context_t *context) RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod); R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3, bo, - 0, + r700->textures[i]->SQ_TEX_RESOURCE3, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5); -- cgit v1.2.3 From e0e51ab1eab52735f23d12c3f1a2217abc51a04e Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 30 Jul 2009 14:59:48 -0400 Subject: r600: split primitive draw into a separate function --- src/mesa/drivers/dri/r600/r700_ioctl.c | 2 +- src/mesa/drivers/dri/r600/r700_render.c | 115 ++++++++++++++++---------------- 2 files changed, 60 insertions(+), 57 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_ioctl.c b/src/mesa/drivers/dri/r600/r700_ioctl.c index c479532001..259a1d1afa 100644 --- a/src/mesa/drivers/dri/r600/r700_ioctl.c +++ b/src/mesa/drivers/dri/r600/r700_ioctl.c @@ -43,7 +43,7 @@ static void r700Flush(GLcontext *ctx) { radeonContextPtr radeon = RADEON_CONTEXT(ctx); - context_t * context = R700_CONTEXT(ctx); + context_t * context = R700_CONTEXT(ctx); if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s %d\n", __FUNCTION__, radeon->cmdbuf.cs->cdw); diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 1810f4be0e..a2e0ac338a 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -279,15 +279,68 @@ unsigned int r700PrimitiveType(int prim) } } +void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + BATCH_LOCALS(&context->radeon); + int type, i, total_emit; + int num_indices = end - start; + uint32_t vgt_draw_initiator = 0; + uint32_t vgt_index_type = 0; + uint32_t vgt_primitive_type = 0; + uint32_t vgt_num_indices = 0; + + type = r700PrimitiveType(prim); + + if (type < 0 || num_indices <= 0) + return; + + total_emit = 3 /* VGT_PRIMITIVE_TYPE */ + + 2 /* VGT_INDEX_TYPE */ + + 2 /* NUM_INSTANCES */ + + num_indices + 3; /* DRAW_INDEX_IMMD */ + + BEGIN_BATCH_NO_AUTOSTATE(total_emit); + // prim + SETfield(vgt_primitive_type, type, + VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + R600_OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); + R600_OUT_BATCH(vgt_primitive_type); + + // index type + SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask); + R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); + R600_OUT_BATCH(vgt_index_type); + + // num instances + R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0)); + R600_OUT_BATCH(1); + + // draw packet + vgt_num_indices = num_indices; + SETfield(vgt_draw_initiator, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask); + SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask); + + R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (num_indices + 1))); + R600_OUT_BATCH(vgt_num_indices); + R600_OUT_BATCH(vgt_draw_initiator); + + for (i = start; i < end; i++) { + R600_OUT_BATCH(i); + } + END_BATCH(); + COMMIT_BATCH(); + +} + static GLboolean r700RunRender(GLcontext * ctx, struct tnl_pipeline_stage *stage) { context_t *context = R700_CONTEXT(ctx); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); int lastIndex = 0; - BATCH_LOCALS(&context->radeon); - - unsigned int i, j; + unsigned int i; TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; @@ -322,61 +375,11 @@ static GLboolean r700RunRender(GLcontext * ctx, r700SendDepthTargetState(context); /* richard test code */ - for (i = 0; i < vb->PrimitiveCount; i++) - { + for (i = 0; i < vb->PrimitiveCount; i++) { GLuint prim = _tnl_translate_prim(&vb->Primitive[i]); GLuint start = vb->Primitive[i].start; GLuint end = vb->Primitive[i].start + vb->Primitive[i].count; - GLuint numIndices = vb->Primitive[i].count; - GLuint numEntires; - - unsigned int VGT_DRAW_INITIATOR = 0; - unsigned int VGT_INDEX_TYPE = 0; - unsigned int VGT_PRIMITIVE_TYPE = 0; - unsigned int VGT_NUM_INDICES = 0; - - if (numIndices < 1) - continue; - - numEntires = 3 /* VGT_PRIMITIVE_TYPE */ - + 2 /* VGT_INDEX_TYPE */ - + 2 /* NUM_INSTANCES */ - + numIndices + 3; /* DRAW_INDEX_IMMD */ - - BEGIN_BATCH_NO_AUTOSTATE(numEntires); - - // prim - VGT_PRIMITIVE_TYPE |= r700PrimitiveType(prim) << VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift; - R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); - R600_OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); - R600_OUT_BATCH(VGT_PRIMITIVE_TYPE); - - // index type - VGT_INDEX_TYPE |= DI_INDEX_SIZE_32_BIT << INDEX_TYPE_shift; - R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); - R600_OUT_BATCH(VGT_INDEX_TYPE); - - // num instances - R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0)); - R600_OUT_BATCH(1); - - // draw packet - VGT_NUM_INDICES = numIndices; - VGT_DRAW_INITIATOR |= DI_SRC_SEL_IMMEDIATE << SOURCE_SELECT_shift; - VGT_DRAW_INITIATOR |= DI_MAJOR_MODE_0 << MAJOR_MODE_shift; - - R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (numIndices + 1))); - R600_OUT_BATCH(VGT_NUM_INDICES); - R600_OUT_BATCH(VGT_DRAW_INITIATOR); - - for (j = lastIndex; j < lastIndex + numIndices; j++) - { - R600_OUT_BATCH(j); - } - lastIndex += numIndices; - - END_BATCH(); - COMMIT_BATCH(); + r700RunRenderPrimitive(ctx, start, end, prim); } /* Flush render op cached for last several quads. */ -- cgit v1.2.3 From 643d52a39443a81bbc7e9b234450754375052b20 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 30 Jul 2009 21:27:05 -0400 Subject: r600: warning fixes --- src/mesa/drivers/dri/r600/r700_chip.c | 8 +------- src/mesa/drivers/dri/r600/r700_render.c | 2 -- 2 files changed, 1 insertion(+), 9 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index c083862f36..994463fa6d 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -249,7 +249,6 @@ void r700SetupVTXConstants(GLcontext * ctx, unsigned int count) /* number of vectors in stream */ { context_t *context = R700_CONTEXT(ctx); - uint32_t *dest; struct radeon_aos * paos = (struct radeon_aos *)pAos; offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF}; @@ -417,7 +416,7 @@ GLboolean r700SendContextStates(context_t *context) return GL_TRUE; } -GLboolean r700SendDepthTargetState(context_t *context, int id) +GLboolean r700SendDepthTargetState(context_t *context) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_renderbuffer *rrb; @@ -540,7 +539,6 @@ GLboolean r700SendRenderTargetState(context_t *context, int id) GLboolean r700SendPSState(context_t *context) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); - struct radeon_renderbuffer *rrb; struct radeon_bo * pbo; offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); @@ -575,7 +573,6 @@ GLboolean r700SendPSState(context_t *context) GLboolean r700SendVSState(context_t *context) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); - struct radeon_renderbuffer *rrb; struct radeon_bo * pbo; offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); @@ -609,7 +606,6 @@ GLboolean r700SendVSState(context_t *context) GLboolean r700SendFSState(context_t *context) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); - struct radeon_renderbuffer *rrb; struct radeon_bo * pbo; offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); @@ -652,8 +648,6 @@ GLboolean r700SendFSState(context_t *context) GLboolean r700SendViewportState(context_t *context, int id) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); - struct radeon_renderbuffer *rrb; - offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); if (id > R700_MAX_VIEWPORTS) diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index a2e0ac338a..8048069619 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -282,7 +282,6 @@ unsigned int r700PrimitiveType(int prim) void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim) { context_t *context = R700_CONTEXT(ctx); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); BATCH_LOCALS(&context->radeon); int type, i, total_emit; int num_indices = end - start; @@ -339,7 +338,6 @@ static GLboolean r700RunRender(GLcontext * ctx, struct tnl_pipeline_stage *stage) { context_t *context = R700_CONTEXT(ctx); - int lastIndex = 0; unsigned int i; TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; -- cgit v1.2.3 From be1687a89271a58d7e4e6f613affa609589f5048 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 31 Jul 2009 10:53:06 -0400 Subject: r600: re-arrange state setup and emit so they are not mixed --- src/mesa/drivers/dri/r600/r700_chip.c | 64 +++++++++++++++++++++++ src/mesa/drivers/dri/r600/r700_fragprog.c | 71 +++++++++++++++----------- src/mesa/drivers/dri/r600/r700_render.c | 85 ++++--------------------------- src/mesa/drivers/dri/r600/r700_vertprog.c | 18 ++++++- 4 files changed, 130 insertions(+), 108 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 994463fa6d..beb5b70245 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -38,6 +38,8 @@ #include "r700_vertprog.h" #include "r700_ioctl.h" +#include "radeon_mipmap_tree.h" + #define LINK_STATES(reg) \ do \ { \ @@ -241,6 +243,68 @@ GLboolean r700InitChipObject(context_t *context) return GL_TRUE; } +GLboolean r700SendTextureState(context_t *context) +{ + unsigned int i; + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF}; + struct radeon_bo *bo = NULL; + BATCH_LOCALS(&context->radeon); + + for (i=0; itextures[i]; + if (t) { + if (!t->image_override) + bo = t->mt->bo; + else + bo = t->bo; + if (bo) { + + r700SyncSurf(context, bo, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, + 0, TC_ACTION_ENA_bit); + + BEGIN_BATCH_NO_AUTOSTATE(9); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); + R600_OUT_BATCH(i * 7); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1); + R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2, + bo, + 0, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod); + R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3, + bo, + r700->textures[i]->SQ_TEX_RESOURCE3, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6); + END_BATCH(); + + BEGIN_BATCH_NO_AUTOSTATE(5); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3)); + R600_OUT_BATCH(i * 3); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2); + END_BATCH(); + + BEGIN_BATCH_NO_AUTOSTATE(2 + 4); + R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4); + R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED); + R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN); + R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE); + R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA); + END_BATCH(); + + COMMIT_BATCH(); + } + } + } + return GL_TRUE; +} + void r700SetupVTXConstants(GLcontext * ctx, unsigned int nStreamID, void * pAos, diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index 180d980442..587134676b 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -338,36 +338,6 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) CLEARbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit); } - /* sent out shader constants. */ - - paramList = fp->mesa_program.Base.Parameters; - - if(NULL != paramList) - { - _mesa_load_state_parameters(ctx, paramList); - - unNumParamData = paramList->NumParameters * 4; - - BEGIN_BATCH_NO_AUTOSTATE(2 + unNumParamData); - - R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData)); - - /* assembler map const from very beginning. */ - R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4); - - unNumParamData = paramList->NumParameters; - - for(ui=0; uiParameterValues[ui][0]))); - R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1]))); - R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2]))); - R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3]))); - } - END_BATCH(); - COMMIT_BATCH(); - } - // emit ps input map unBit = 1 << FRAG_ATTRIB_COL0; if(mesa_fp->Base.InputsRead & unBit) @@ -424,5 +394,46 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) return GL_TRUE; } +GLboolean r700SendPSConstants(GLcontext * ctx) +{ + context_t *context = R700_CONTEXT(ctx); + BATCH_LOCALS(&context->radeon); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + struct r700_fragment_program *fp = (struct r700_fragment_program *) + (ctx->FragmentProgram._Current); + struct gl_program_parameter_list *paramList; + unsigned int unNumParamData; + unsigned int ui; + + /* sent out shader constants. */ + paramList = fp->mesa_program.Base.Parameters; + + if(NULL != paramList) + { + _mesa_load_state_parameters(ctx, paramList); + + unNumParamData = paramList->NumParameters * 4; + + BEGIN_BATCH_NO_AUTOSTATE(2 + unNumParamData); + + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData)); + + /* assembler map const from very beginning. */ + R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4); + unNumParamData = paramList->NumParameters; + + for(ui=0; uiParameterValues[ui][0]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3]))); + } + END_BATCH(); + COMMIT_BATCH(); + } + + return GL_TRUE; +} diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 8048069619..5bc1abdf2e 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -44,7 +44,6 @@ #include "tnl/t_vertex.h" #include "tnl/t_pipeline.h" -#include "radeon_mipmap_tree.h" #include "r600_context.h" #include "r600_cmdbuf.h" @@ -141,68 +140,6 @@ static GLboolean r700SetupShaders(GLcontext * ctx) return GL_TRUE; } -GLboolean r700SendTextureState(context_t *context) -{ - unsigned int i; - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF}; - struct radeon_bo *bo = NULL; - BATCH_LOCALS(&context->radeon); - - for (i=0; itextures[i]; - if (t) { - if (!t->image_override) - bo = t->mt->bo; - else - bo = t->bo; - if (bo) { - - r700SyncSurf(context, bo, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, - 0, TC_ACTION_ENA_bit); - - BEGIN_BATCH_NO_AUTOSTATE(9); - R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); - R600_OUT_BATCH(i * 7); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1); - R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2, - bo, - 0, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod); - R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3, - bo, - r700->textures[i]->SQ_TEX_RESOURCE3, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6); - END_BATCH(); - - BEGIN_BATCH_NO_AUTOSTATE(5); - R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3)); - R600_OUT_BATCH(i * 3); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2); - END_BATCH(); - - BEGIN_BATCH_NO_AUTOSTATE(2 + 4); - R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4); - R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED); - R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN); - R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE); - R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA); - END_BATCH(); - - COMMIT_BATCH(); - } - } - } - return GL_TRUE; -} - GLboolean r700SyncSurf(context_t *context, struct radeon_bo *pbo, uint32_t read_domain, @@ -342,29 +279,25 @@ static GLboolean r700RunRender(GLcontext * ctx, TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; - r700Start3D(context); /* TODO : this is too much. */ - - r700SendSQConfig(context); - r700UpdateShaders(ctx); - r700SetScissor(context); r700SetRenderTarget(context, 0); r700SetDepthTarget(context); - - if(r700SetupStreams(ctx)) - { - return GL_TRUE; - } - r600UpdateTextureState(ctx); - r700SendTextureState(context); - r700SetupShaders(ctx); + + r700Start3D(context); + r700SendSQConfig(context); r700SendFSState(context); // FIXME just a place holder for now r700SendPSState(context); r700SendVSState(context); + r700SendVSConstants(ctx); + r700SendPSConstants(ctx); + + r700SendTextureState(context); + if(r700SetupStreams(ctx)) + return GL_TRUE; r700SendUCPState(context); r700SendContextStates(context); diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index af6a6b8c29..fda6f75687 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -393,6 +393,20 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit); */ + return GL_TRUE; +} + +GLboolean r700SendVSConstants(GLcontext * ctx) +{ + context_t *context = R700_CONTEXT(ctx); + BATCH_LOCALS(&context->radeon); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + struct r700_vertex_program *vp + = (struct r700_vertex_program *)ctx->VertexProgram._Current; + struct gl_program_parameter_list *paramList; + unsigned int unNumParamData; + unsigned int ui; + /* sent out shader constants. */ paramList = vp->mesa_program.Base.Parameters; @@ -403,8 +417,8 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) unNumParamData = paramList->NumParameters * 4; - BEGIN_BATCH_NO_AUTOSTATE(unNumParamData + 2); - + BEGIN_BATCH_NO_AUTOSTATE(unNumParamData + 2); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData)); /* assembler map const from very beginning. */ R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4); -- cgit v1.2.3 From 54a16419235d298e4b7c1761d6abe8066e6cf393 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 31 Jul 2009 11:12:10 -0400 Subject: r600: unify state emit into one function --- src/mesa/drivers/dri/r600/r700_chip.c | 3 +- src/mesa/drivers/dri/r600/r700_ioctl.c | 3 +- src/mesa/drivers/dri/r600/r700_render.c | 56 +++++++++++++++++++-------------- 3 files changed, 34 insertions(+), 28 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index beb5b70245..f6face50db 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -373,7 +373,6 @@ void r700SetupVTXConstants(GLcontext * ctx, int r700SetupStreams(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); - BATCH_LOCALS(&context->radeon); struct r700_vertex_program *vpc @@ -387,7 +386,7 @@ int r700SetupStreams(GLcontext * ctx) BEGIN_BATCH_NO_AUTOSTATE(6); R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); - R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); + R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); R600_OUT_BATCH(0); R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); diff --git a/src/mesa/drivers/dri/r600/r700_ioctl.c b/src/mesa/drivers/dri/r600/r700_ioctl.c index 259a1d1afa..23cc128d6d 100644 --- a/src/mesa/drivers/dri/r600/r700_ioctl.c +++ b/src/mesa/drivers/dri/r600/r700_ioctl.c @@ -43,7 +43,6 @@ static void r700Flush(GLcontext *ctx) { radeonContextPtr radeon = RADEON_CONTEXT(ctx); - context_t * context = R700_CONTEXT(ctx); if (RADEON_DEBUG & DEBUG_IOCTL) fprintf(stderr, "%s %d\n", __FUNCTION__, radeon->cmdbuf.cs->cdw); @@ -59,7 +58,7 @@ static void r700Flush(GLcontext *ctx) if (radeon->dma.flush) radeon->dma.flush( ctx ); - r700SendContextStates(context); + r700EmitState(ctx); if (radeon->cmdbuf.cs->cdw) rcommonFlushCmdBuf(radeon, __FUNCTION__); diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 5bc1abdf2e..c26c20e6ee 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -57,7 +57,7 @@ void r700WaitForIdle(context_t *context); void r700WaitForIdleClean(context_t *context); void r700Start3D(context_t *context); GLboolean r700SendTextureState(context_t *context); -unsigned int r700PrimitiveType(int prim); +static unsigned int r700PrimitiveType(int prim); void r600UpdateTextureState(GLcontext * ctx); GLboolean r700SyncSurf(context_t *context, struct radeon_bo *pbo, @@ -137,6 +137,8 @@ static GLboolean r700SetupShaders(GLcontext * ctx) exportCount = (r700->ps.SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift); r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1; + r600UpdateTextureState(ctx); + return GL_TRUE; } @@ -175,7 +177,7 @@ GLboolean r700SyncSurf(context_t *context, return GL_TRUE; } -unsigned int r700PrimitiveType(int prim) +static unsigned int r700PrimitiveType(int prim) { switch (prim & PRIM_MODE_MASK) { @@ -216,7 +218,7 @@ unsigned int r700PrimitiveType(int prim) } } -void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim) +static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim) { context_t *context = R700_CONTEXT(ctx); BATCH_LOCALS(&context->radeon); @@ -271,6 +273,29 @@ void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim) } +void r700EmitState(GLcontext * ctx) +{ + context_t *context = R700_CONTEXT(ctx); + + r700Start3D(context); + r700SendSQConfig(context); + r700SendFSState(context); // FIXME just a place holder for now + r700SendPSState(context); + r700SendVSState(context); + r700SendVSConstants(ctx); + r700SendPSConstants(ctx); + + r700SendTextureState(context); + r700SetupStreams(ctx); + + r700SendUCPState(context); + r700SendContextStates(context); + r700SendViewportState(context, 0); + r700SendRenderTargetState(context, 0); + r700SendDepthTargetState(context); + +} + static GLboolean r700RunRender(GLcontext * ctx, struct tnl_pipeline_stage *stage) { @@ -281,29 +306,12 @@ static GLboolean r700RunRender(GLcontext * ctx, r700UpdateShaders(ctx); r700SetScissor(context); - r700SetRenderTarget(context, 0); - r700SetDepthTarget(context); - r600UpdateTextureState(ctx); r700SetupShaders(ctx); + r700SetRenderTarget(context, 0); + r700SetDepthTarget(context); - r700Start3D(context); - r700SendSQConfig(context); - r700SendFSState(context); // FIXME just a place holder for now - r700SendPSState(context); - r700SendVSState(context); - r700SendVSConstants(ctx); - r700SendPSConstants(ctx); - - r700SendTextureState(context); - if(r700SetupStreams(ctx)) - return GL_TRUE; - - r700SendUCPState(context); - r700SendContextStates(context); - r700SendViewportState(context, 0); - r700SendRenderTargetState(context, 0); - r700SendDepthTargetState(context); + r700EmitState(ctx); /* richard test code */ for (i = 0; i < vb->PrimitiveCount; i++) { @@ -316,7 +324,7 @@ static GLboolean r700RunRender(GLcontext * ctx, /* Flush render op cached for last several quads. */ r700WaitForIdleClean(context); - radeonReleaseArrays(ctx, 0); + radeonReleaseArrays(ctx, ~0); rcommonFlushCmdBuf( &context->radeon, __FUNCTION__ ); -- cgit v1.2.3 From 19ce428c8a08565b06795f4b8020dc6399694789 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 31 Jul 2009 11:33:16 -0400 Subject: r600: ensure we have enough room for full state emit full state is roughly 4000 dwords, but will vary depending on the rendering. Also fix some warnings. --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 3 ++- src/mesa/drivers/dri/r600/r700_fragprog.c | 4 ---- src/mesa/drivers/dri/r600/r700_render.c | 3 +++ src/mesa/drivers/dri/r600/r700_vertprog.c | 7 ------- 4 files changed, 5 insertions(+), 12 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index e9ad9ba64c..15b99926d2 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -483,8 +483,9 @@ struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_cont void r600InitCmdBuf(context_t *r600) /* from rcommonInitCmdBuf */ { radeonContextPtr rmesa = &r600->radeon; - GLuint size; + rmesa->hw.max_state_size = 4000; /* rough estimate */ + /* Initialize command buffer */ size = 256 * driQueryOptioni(&rmesa->optionCache, "command_buffer_size"); diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index 587134676b..4ac37f1dfe 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -262,15 +262,12 @@ void * r700GetActiveFpShaderBo(GLcontext * ctx) GLboolean r700SetupFragmentProgram(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); - BATCH_LOCALS(&context->radeon); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); struct r700_fragment_program *fp = (struct r700_fragment_program *) (ctx->FragmentProgram._Current); r700_AssemblerBase *pAsm = &(fp->r700AsmCode); struct gl_fragment_program *mesa_fp = &(fp->mesa_program); - struct gl_program_parameter_list *paramList; - unsigned int unNumParamData; unsigned int ui, i; unsigned int unNumOfReg; unsigned int unBit; @@ -398,7 +395,6 @@ GLboolean r700SendPSConstants(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); BATCH_LOCALS(&context->radeon); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); struct r700_fragment_program *fp = (struct r700_fragment_program *) (ctx->FragmentProgram._Current); struct gl_program_parameter_list *paramList; diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index c26c20e6ee..bd4e0bfff4 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -277,6 +277,9 @@ void r700EmitState(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); + rcommonEnsureCmdBufSpace(&context->radeon, + context->radeon.hw.max_state_size, __FUNCTION__); + r700Start3D(context); r700SendSQConfig(context); r700SendFSState(context); // FIXME just a place holder for now diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index fda6f75687..8652f1d472 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -335,18 +335,12 @@ void * r700GetActiveVpShaderBo(GLcontext * ctx) GLboolean r700SetupVertexProgram(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); - - BATCH_LOCALS(&context->radeon); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); struct r700_vertex_program *vp = (struct r700_vertex_program *)ctx->VertexProgram._Current; struct gl_program_parameter_list *paramList; - unsigned int unNumParamData; - - unsigned int ui; if(GL_FALSE == vp->loaded) { @@ -400,7 +394,6 @@ GLboolean r700SendVSConstants(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); BATCH_LOCALS(&context->radeon); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); struct r700_vertex_program *vp = (struct r700_vertex_program *)ctx->VertexProgram._Current; struct gl_program_parameter_list *paramList; -- cgit v1.2.3 From 177c33c481d84058f57e761b25cba735b9c7e6ea Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 31 Jul 2009 12:06:26 -0400 Subject: r600: remove unused offset_mod stuff this is a step in migrating to the common cs code --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 27 ++----------------- src/mesa/drivers/dri/r600/r600_cmdbuf.h | 8 +++--- src/mesa/drivers/dri/r600/r600_context.h | 7 ----- src/mesa/drivers/dri/r600/r700_chip.c | 44 ++++++------------------------- src/mesa/drivers/dri/r600/r700_render.c | 7 +---- src/mesa/drivers/dri/r600/r700_vertprog.c | 2 -- 6 files changed, 14 insertions(+), 81 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 15b99926d2..d2e75c011c 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -78,8 +78,7 @@ int r600_cs_write_reloc(struct radeon_cs *cs, struct radeon_bo *bo, uint32_t read_domain, uint32_t write_domain, - uint32_t flags, - offset_modifiers* poffset_mod) + uint32_t flags) { struct r600_cs_reloc_legacy *relocs; int i; @@ -135,10 +134,6 @@ int r600_cs_write_reloc(struct radeon_cs *cs, cs->section_ndw += 2; cs->section_cdw += 2; - relocs[i].offset_mod.shift = poffset_mod->shift; - relocs[i].offset_mod.shiftbits = poffset_mod->shiftbits; - relocs[i].offset_mod.mask = poffset_mod->mask; - return 0; } } @@ -160,9 +155,6 @@ int r600_cs_write_reloc(struct radeon_cs *cs, { return -ENOMEM; } - relocs[cs->crelocs].offset_mod.shift = poffset_mod->shift; - relocs[cs->crelocs].offset_mod.shiftbits = poffset_mod->shiftbits; - relocs[cs->crelocs].offset_mod.mask = poffset_mod->mask; relocs[cs->crelocs].indices[0] = cs->cdw - 1; relocs[cs->crelocs].reloc_indices[0] = cs->section_cdw; @@ -286,28 +278,13 @@ restart: exit(0); return -EINVAL; } - /* apply offset operator */ - switch (relocs[i].offset_mod.shift) - { - case NO_SHIFT: - asicoffset = asicoffset & relocs[i].offset_mod.mask; - break; - case LEFT_SHIFT: - asicoffset = (asicoffset << relocs[i].offset_mod.shiftbits) & relocs[i].offset_mod.mask; - break; - case RIGHT_SHIFT: - asicoffset = (asicoffset >> relocs[i].offset_mod.shiftbits) & relocs[i].offset_mod.mask; - break; - default: - break; - }; /* pkt3 nop header in ib chunk */ cs->packets[relocs[i].reloc_indices[j]] = 0xC0001000; /* reloc index in ib chunk */ cs->packets[relocs[i].reloc_indices[j] + 1] = offset_dw; - + /* asic offset in reloc chunk */ /* see alex drm r600_nomm_relocate */ reloc_chunk[offset_dw] = asicoffset; reloc_chunk[offset_dw + 3] = 0; diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.h b/src/mesa/drivers/dri/r600/r600_cmdbuf.h index bd1ed7fdff..5df0cf1ab6 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.h +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.h @@ -132,15 +132,13 @@ struct r600_cs_reloc_legacy { uint32_t cindices; uint32_t *indices; uint32_t *reloc_indices; - struct offset_modifiers offset_mod; }; extern int r600_cs_write_reloc(struct radeon_cs *cs, struct radeon_bo *bo, uint32_t read_domain, uint32_t write_domain, - uint32_t flags, - offset_modifiers* poffset_mod); + uint32_t flags); static inline void r600_cs_write_dword(struct radeon_cs *cs, uint32_t dword) { @@ -171,7 +169,7 @@ struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_cont /** * Write a relocated dword to the command buffer. */ -#define R600_OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags, offset_mod) \ +#define R600_OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) \ do { \ if (0 && offset) { \ fprintf(stderr, "(%s:%s:%d) offset : %d\n", \ @@ -179,7 +177,7 @@ struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_cont } \ r600_cs_write_dword(b_l_rmesa->cmdbuf.cs, offset); \ r600_cs_write_reloc(b_l_rmesa->cmdbuf.cs, \ - bo, rd, wd, flags, offset_mod); \ + bo, rd, wd, flags); \ } while(0) /* R600/R700 */ diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index bcb33e1386..fbb8164af5 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -128,13 +128,6 @@ enum RIGHT_SHIFT = 2, }; -typedef struct offset_modifiers -{ - GLuint shift; - GLuint shiftbits; - GLuint mask; -} offset_modifiers; - /** * \brief R600 context structure. */ diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index f6face50db..ad4f29b729 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -247,7 +247,6 @@ GLboolean r700SendTextureState(context_t *context) { unsigned int i; R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF}; struct radeon_bo *bo = NULL; BATCH_LOCALS(&context->radeon); @@ -272,11 +271,11 @@ GLboolean r700SendTextureState(context_t *context) R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2, bo, 0, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod); + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3, bo, r700->textures[i]->SQ_TEX_RESOURCE3, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod); + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6); @@ -314,8 +313,6 @@ void r700SetupVTXConstants(GLcontext * ctx, { context_t *context = R700_CONTEXT(ctx); struct radeon_aos * paos = (struct radeon_aos *)pAos; - offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF}; - BATCH_LOCALS(&context->radeon); unsigned int uSQ_VTX_CONSTANT_WORD0_0; @@ -357,7 +354,7 @@ void r700SetupVTXConstants(GLcontext * ctx, R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0, paos->bo, uSQ_VTX_CONSTANT_WORD0_0, - RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + RADEON_GEM_DOMAIN_GTT, 0, 0); R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0); R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0); R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0); @@ -483,7 +480,6 @@ GLboolean r700SendDepthTargetState(context_t *context) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_renderbuffer *rrb; - offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); rrb = radeon_get_depthbuffer(&context->radeon); @@ -492,10 +488,6 @@ GLboolean r700SendDepthTargetState(context_t *context) return GL_FALSE; } - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - BEGIN_BATCH_NO_AUTOSTATE(9); R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2); R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All); @@ -504,7 +496,7 @@ GLboolean r700SendDepthTargetState(context_t *context) R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All, rrb->bo, r700->DB_DEPTH_BASE.u32All, - 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod); + 0, RADEON_GEM_DOMAIN_VRAM, 0); R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All); R600_OUT_BATCH(r700->DB_HTILE_DATA_BASE.u32All); END_BATCH(); @@ -541,7 +533,6 @@ GLboolean r700SendRenderTargetState(context_t *context, int id) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_renderbuffer *rrb; - offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); rrb = radeon_get_colorbuffer(&context->radeon); @@ -556,16 +547,12 @@ GLboolean r700SendRenderTargetState(context_t *context, int id) if (!r700->render_target[id].enabled) return GL_FALSE; - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - BEGIN_BATCH_NO_AUTOSTATE(3); R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1); R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All, rrb->bo, r700->render_target[id].CB_COLOR0_BASE.u32All, - 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod); + 0, RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) && @@ -603,15 +590,10 @@ GLboolean r700SendPSState(context_t *context) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; - offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context)); - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); BEGIN_BATCH_NO_AUTOSTATE(3); @@ -619,7 +601,7 @@ GLboolean r700SendPSState(context_t *context) R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All, pbo, r700->ps.SQ_PGM_START_PS.u32All, - RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + RADEON_GEM_DOMAIN_GTT, 0, 0); END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(9); @@ -637,15 +619,10 @@ GLboolean r700SendVSState(context_t *context) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; - offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); BEGIN_BATCH_NO_AUTOSTATE(3); @@ -653,7 +630,7 @@ GLboolean r700SendVSState(context_t *context) R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All, pbo, r700->vs.SQ_PGM_START_VS.u32All, - RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + RADEON_GEM_DOMAIN_GTT, 0, 0); END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(6); @@ -670,7 +647,6 @@ GLboolean r700SendFSState(context_t *context) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; - offset_modifiers offset_mod; BATCH_LOCALS(&context->radeon); /* XXX fixme @@ -684,10 +660,6 @@ GLboolean r700SendFSState(context_t *context) r700->fs.SQ_PGM_CF_OFFSET_FS.u32All = 0; /* XXX */ - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); BEGIN_BATCH_NO_AUTOSTATE(3); @@ -695,7 +667,7 @@ GLboolean r700SendFSState(context_t *context) R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All, pbo, r700->fs.SQ_PGM_START_FS.u32All, - RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + RADEON_GEM_DOMAIN_GTT, 0, 0); END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(6); diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index bd4e0bfff4..5a1f04f87c 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -150,17 +150,12 @@ GLboolean r700SyncSurf(context_t *context, { BATCH_LOCALS(&context->radeon); uint32_t cp_coher_size; - offset_modifiers offset_mod; if (pbo->size == 0xffffffff) cp_coher_size = 0xffffffff; else cp_coher_size = ((pbo->size + 255) >> 8); - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - BEGIN_BATCH_NO_AUTOSTATE(5); R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_SYNC, 3)); R600_OUT_BATCH(sync_type); @@ -168,7 +163,7 @@ GLboolean r700SyncSurf(context_t *context, R600_OUT_BATCH_RELOC(0, pbo, 0, - read_domain, write_domain, 0, &offset_mod); // ??? + read_domain, write_domain, 0); // ??? R600_OUT_BATCH(10); END_BATCH(); diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index 8652f1d472..1c5c20f66e 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -340,8 +340,6 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) struct r700_vertex_program *vp = (struct r700_vertex_program *)ctx->VertexProgram._Current; - struct gl_program_parameter_list *paramList; - if(GL_FALSE == vp->loaded) { if(vp->r700Shader.bNeedsAssembly == GL_TRUE) -- cgit v1.2.3 From 95b64c0ed20725db2722314d527d63aace6b7f7a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 31 Jul 2009 15:11:41 -0400 Subject: r600: make sure bos are valid before usign that --- src/mesa/drivers/dri/r600/r700_chip.c | 12 ++++++++++++ src/mesa/drivers/dri/r600/r700_render.c | 3 +++ 2 files changed, 15 insertions(+) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index ad4f29b729..78779e841d 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -321,6 +321,9 @@ void r700SetupVTXConstants(GLcontext * ctx, unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0; unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0; + if (!paos->bo) + return GL_FALSE; + if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) || (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) || (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) || @@ -594,6 +597,9 @@ GLboolean r700SendPSState(context_t *context) pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context)); + if (!pbo) + return GL_FALSE; + r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); BEGIN_BATCH_NO_AUTOSTATE(3); @@ -623,6 +629,9 @@ GLboolean r700SendVSState(context_t *context) pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); + if (!pbo) + return GL_FALSE; + r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); BEGIN_BATCH_NO_AUTOSTATE(3); @@ -660,6 +669,9 @@ GLboolean r700SendFSState(context_t *context) r700->fs.SQ_PGM_CF_OFFSET_FS.u32All = 0; /* XXX */ + if (!pbo) + return GL_FALSE; + r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); BEGIN_BATCH_NO_AUTOSTATE(3); diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 5a1f04f87c..2592d7df14 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -151,6 +151,9 @@ GLboolean r700SyncSurf(context_t *context, BATCH_LOCALS(&context->radeon); uint32_t cp_coher_size; + if (!pbo) + return GL_FALSE; + if (pbo->size == 0xffffffff) cp_coher_size = 0xffffffff; else -- cgit v1.2.3 From 5e5190360641ad9b328b14097d912aff3496f618 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Sun, 2 Aug 2009 13:28:18 -0400 Subject: r600: fix regression in texenv Emit shader consts with the shader program itself --- src/mesa/drivers/dri/r600/r700_fragprog.c | 75 +++++++++++++------------------ src/mesa/drivers/dri/r600/r700_render.c | 2 - src/mesa/drivers/dri/r600/r700_vertprog.c | 20 +++------ 3 files changed, 37 insertions(+), 60 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index 4ac37f1dfe..f382686be4 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -263,11 +263,13 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - + BATCH_LOCALS(&context->radeon); struct r700_fragment_program *fp = (struct r700_fragment_program *) (ctx->FragmentProgram._Current); r700_AssemblerBase *pAsm = &(fp->r700AsmCode); struct gl_fragment_program *mesa_fp = &(fp->mesa_program); + struct gl_program_parameter_list *paramList; + unsigned int unNumParamData; unsigned int ui, i; unsigned int unNumOfReg; unsigned int unBit; @@ -335,6 +337,35 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) CLEARbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit); } + /* sent out shader constants. */ + paramList = fp->mesa_program.Base.Parameters; + + if(NULL != paramList) + { + _mesa_load_state_parameters(ctx, paramList); + + unNumParamData = paramList->NumParameters * 4; + + BEGIN_BATCH_NO_AUTOSTATE(2 + unNumParamData); + + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData)); + + /* assembler map const from very beginning. */ + R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4); + + unNumParamData = paramList->NumParameters; + + for(ui=0; uiParameterValues[ui][0]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2]))); + R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3]))); + } + END_BATCH(); + COMMIT_BATCH(); + } + // emit ps input map unBit = 1 << FRAG_ATTRIB_COL0; if(mesa_fp->Base.InputsRead & unBit) @@ -391,45 +422,3 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) return GL_TRUE; } -GLboolean r700SendPSConstants(GLcontext * ctx) -{ - context_t *context = R700_CONTEXT(ctx); - BATCH_LOCALS(&context->radeon); - struct r700_fragment_program *fp = (struct r700_fragment_program *) - (ctx->FragmentProgram._Current); - struct gl_program_parameter_list *paramList; - unsigned int unNumParamData; - unsigned int ui; - - /* sent out shader constants. */ - paramList = fp->mesa_program.Base.Parameters; - - if(NULL != paramList) - { - _mesa_load_state_parameters(ctx, paramList); - - unNumParamData = paramList->NumParameters * 4; - - BEGIN_BATCH_NO_AUTOSTATE(2 + unNumParamData); - - R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData)); - - /* assembler map const from very beginning. */ - R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4); - - unNumParamData = paramList->NumParameters; - - for(ui=0; uiParameterValues[ui][0]))); - R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1]))); - R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2]))); - R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3]))); - } - END_BATCH(); - COMMIT_BATCH(); - } - - return GL_TRUE; -} - diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 2592d7df14..34a4385841 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -283,8 +283,6 @@ void r700EmitState(GLcontext * ctx) r700SendFSState(context); // FIXME just a place holder for now r700SendPSState(context); r700SendVSState(context); - r700SendVSConstants(ctx); - r700SendPSConstants(ctx); r700SendTextureState(context); r700SetupStreams(ctx); diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index 1c5c20f66e..31e71cdfa3 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -336,10 +336,14 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - + BATCH_LOCALS(&context->radeon); struct r700_vertex_program *vp = (struct r700_vertex_program *)ctx->VertexProgram._Current; + struct gl_program_parameter_list *paramList; + unsigned int unNumParamData; + unsigned int ui; + if(GL_FALSE == vp->loaded) { if(vp->r700Shader.bNeedsAssembly == GL_TRUE) @@ -385,21 +389,7 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit); */ - return GL_TRUE; -} - -GLboolean r700SendVSConstants(GLcontext * ctx) -{ - context_t *context = R700_CONTEXT(ctx); - BATCH_LOCALS(&context->radeon); - struct r700_vertex_program *vp - = (struct r700_vertex_program *)ctx->VertexProgram._Current; - struct gl_program_parameter_list *paramList; - unsigned int unNumParamData; - unsigned int ui; - /* sent out shader constants. */ - paramList = vp->mesa_program.Base.Parameters; if(NULL != paramList) -- cgit v1.2.3 From d07bf2b35c1419bdef824092e509c70ffb11fd67 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Sun, 2 Aug 2009 18:26:12 -0400 Subject: r600: handle state emit better - move shader-related state with the rest of the shader setup/emit - start to track dirty state better --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 3 +++ src/mesa/drivers/dri/r600/r700_render.c | 19 +++++++++++-------- src/mesa/drivers/dri/r600/r700_state.c | 2 ++ 3 files changed, 16 insertions(+), 8 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 8debecbab9..dc2fb0144a 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -457,6 +457,9 @@ void r600InitCmdBuf(context_t *r600) /* from rcommonInitCmdBuf */ GLuint size; rmesa->hw.max_state_size = 4000; /* rough estimate */ + rmesa->hw.all_dirty = GL_TRUE; + rmesa->hw.is_dirty = GL_TRUE; + /* Initialize command buffer */ size = 256 * driQueryOptioni(&rmesa->optionCache, "command_buffer_size"); diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 34a4385841..20376d2c36 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -139,6 +139,13 @@ static GLboolean r700SetupShaders(GLcontext * ctx) r600UpdateTextureState(ctx); + r700SendFSState(context); // FIXME just a place holder for now + r700SendPSState(context); + r700SendVSState(context); + + r700SendTextureState(context); + r700SetupStreams(ctx); + return GL_TRUE; } @@ -274,18 +281,16 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim void r700EmitState(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); + radeonContextPtr radeon = &context->radeon; + + if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw.all_dirty) + return; rcommonEnsureCmdBufSpace(&context->radeon, context->radeon.hw.max_state_size, __FUNCTION__); r700Start3D(context); r700SendSQConfig(context); - r700SendFSState(context); // FIXME just a place holder for now - r700SendPSState(context); - r700SendVSState(context); - - r700SendTextureState(context); - r700SetupStreams(ctx); r700SendUCPState(context); r700SendContextStates(context); @@ -325,8 +330,6 @@ static GLboolean r700RunRender(GLcontext * ctx, radeonReleaseArrays(ctx, ~0); - rcommonFlushCmdBuf( &context->radeon, __FUNCTION__ ); - return GL_FALSE; } diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index b75f531503..e95f52400a 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -1854,6 +1854,8 @@ void r700InitState(GLcontext * ctx) //------------------- /* Set up color compare mask */ r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF; + context->radeon.hw.all_dirty = GL_TRUE; + } void r700InitStateFuncs(struct dd_function_table *functions) //----------------- -- cgit v1.2.3 From b0c191acaf0fbbfa743781908187344f5081a083 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 12 Aug 2009 15:34:24 -0400 Subject: r600: state cleanups --- src/mesa/drivers/dri/r600/r700_chip.c | 2 +- src/mesa/drivers/dri/r600/r700_render.c | 6 +-- src/mesa/drivers/dri/r600/r700_state.c | 80 +++++++++++++++------------------ src/mesa/drivers/dri/r600/r700_state.h | 4 +- 4 files changed, 40 insertions(+), 52 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 78779e841d..e5e0f556cb 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -322,7 +322,7 @@ void r700SetupVTXConstants(GLcontext * ctx, unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0; if (!paos->bo) - return GL_FALSE; + return; if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) || (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) || diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 20376d2c36..6705dbcf4b 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -289,7 +289,6 @@ void r700EmitState(GLcontext * ctx) rcommonEnsureCmdBufSpace(&context->radeon, context->radeon.hw.max_state_size, __FUNCTION__); - r700Start3D(context); r700SendSQConfig(context); r700SendUCPState(context); @@ -308,13 +307,12 @@ static GLboolean r700RunRender(GLcontext * ctx, TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; + r700Start3D(context); + r700UpdateShaders(ctx); r700SetScissor(context); r700SetupShaders(ctx); - r700SetRenderTarget(context, 0); - r700SetDepthTarget(context); - r700EmitState(ctx); /* richard test code */ diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 7f54cf9f56..835b5e18c2 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -60,6 +60,8 @@ static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state); static void r700UpdatePolygonMode(GLcontext * ctx); static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state); static void r700SetStencilState(GLcontext * ctx, GLboolean state); +static void r700SetRenderTarget(context_t *context, int id); +static void r700SetDepthTarget(context_t *context); void r700SetDefaultStates(context_t *context) //-------------------- { @@ -158,21 +160,10 @@ void r700UpdateViewportOffset(GLcontext * ctx) //------------------ */ void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //--------------------- { -#if 0 /* to be enabled */ - context_t *context = R700_CONTEXT(ctx); + context_t *context = R700_CONTEXT(ctx); - switch (ctx->DrawBuffer->_ColorDrawBufferIndexes[0]) - { - case BUFFER_FRONT_LEFT: - context->target.rt = context->screen->frontBuffer; - break; - case BUFFER_BACK_LEFT: - context->target.rt = context->screen->backBuffer; - break; - default: - memset (&context->target.rt, sizeof(context->target.rt), 0); - } -#endif /* to be enabled */ + r700SetRenderTarget(context, 0); + r700SetDepthTarget(context); } static void r700FetchStateParameter(GLcontext * ctx, @@ -1357,22 +1348,22 @@ void r700SetScissor(context_t *context) //--------------- r700->viewport[id].enabled = GL_TRUE; } -void r700SetRenderTarget(context_t *context, int id) +static void r700SetRenderTarget(context_t *context, int id) { R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); struct radeon_renderbuffer *rrb; unsigned int nPitchInPixel; + rrb = radeon_get_colorbuffer(&context->radeon); + if (!rrb || !rrb->bo) { + fprintf(stderr, "no rrb\n"); + return; + } + /* screen/window/view */ SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask); - rrb = radeon_get_colorbuffer(&context->radeon); - if (!rrb || !rrb->bo) { - fprintf(stderr, "no rrb\n"); - return; - } - /* color buffer */ r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset; @@ -1405,39 +1396,22 @@ void r700SetRenderTarget(context_t *context, int id) r700->render_target[id].enabled = GL_TRUE; } -void r700SetDepthTarget(context_t *context) +static void r700SetDepthTarget(context_t *context) { R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); struct radeon_renderbuffer *rrb; unsigned int nPitchInPixel; + rrb = radeon_get_depthbuffer(&context->radeon); + if (!rrb) + return; + /* depth buf */ r700->DB_DEPTH_SIZE.u32All = 0; r700->DB_DEPTH_BASE.u32All = 0; r700->DB_DEPTH_INFO.u32All = 0; - - r700->DB_DEPTH_CLEAR.u32All = 0x3F800000; - r700->DB_DEPTH_VIEW.u32All = 0; - r700->DB_RENDER_CONTROL.u32All = 0; - SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit); - SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit); - r700->DB_RENDER_OVERRIDE.u32All = 0; - if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) - SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit); - SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask); - SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask); - SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask); - - r700->DB_ALPHA_TO_MASK.u32All = 0; - SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask); - SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask); - SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask); - SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask); - - rrb = radeon_get_depthbuffer(&context->radeon); - if (!rrb) - return; + r700->DB_DEPTH_VIEW.u32All = 0; nPitchInPixel = rrb->pitch/rrb->cpp; @@ -1787,6 +1761,24 @@ void r700InitState(GLcontext * ctx) //------------------- r700DepthFunc(ctx, ctx->Depth.Func); SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit); + r700->DB_DEPTH_CLEAR.u32All = 0x3F800000; + + r700->DB_RENDER_CONTROL.u32All = 0; + SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit); + SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit); + r700->DB_RENDER_OVERRIDE.u32All = 0; + if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) + SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit); + SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask); + SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask); + SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask); + + r700->DB_ALPHA_TO_MASK.u32All = 0; + SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask); + SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask); + SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask); + SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask); + /* stencil */ r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled); r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]); diff --git a/src/mesa/drivers/dri/r600/r700_state.h b/src/mesa/drivers/dri/r600/r700_state.h index 23246367db..30eb54e8b0 100644 --- a/src/mesa/drivers/dri/r600/r700_state.h +++ b/src/mesa/drivers/dri/r600/r700_state.h @@ -42,10 +42,8 @@ extern void r700UpdateDrawBuffer (GLcontext * ctx); extern void r700InitState (GLcontext * ctx); extern void r700InitStateFuncs (struct dd_function_table *functions); -extern void r700SetRenderTarget(context_t *context, int id); extern void r700SetDefaultStates(context_t * context); -void r700SetScissor(context_t *context); -void r700SetDepthTarget(context_t *context); +extern void r700SetScissor(context_t *context); #endif /* _R600_SCREEN_H */ -- cgit v1.2.3 From 66c632b5a1fe165718cc1fe3f2f9030ed05e4d01 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 17 Aug 2009 17:47:27 -0400 Subject: r600: make sure the number of indices is valid make sure the number of indices is valid for the requested prim type. glxgears sends invalid quad strips with only 2 indices for example. --- src/mesa/drivers/dri/r600/r700_render.c | 55 ++++++++++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 6705dbcf4b..9e2971a343 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -223,18 +223,71 @@ static unsigned int r700PrimitiveType(int prim) } } +static int r700NumVerts(int num_verts, int prim) +{ + int verts_off = 0; + + switch (prim & PRIM_MODE_MASK) { + case GL_POINTS: + verts_off = 0; + break; + case GL_LINES: + verts_off = num_verts % 2; + break; + case GL_LINE_STRIP: + if (num_verts < 2) + verts_off = num_verts; + break; + case GL_LINE_LOOP: + if (num_verts < 2) + verts_off = num_verts; + break; + case GL_TRIANGLES: + verts_off = num_verts % 3; + break; + case GL_TRIANGLE_STRIP: + if (num_verts < 3) + verts_off = num_verts; + break; + case GL_TRIANGLE_FAN: + if (num_verts < 3) + verts_off = num_verts; + break; + case GL_QUADS: + verts_off = num_verts % 4; + break; + case GL_QUAD_STRIP: + if (num_verts < 4) + verts_off = num_verts; + else + verts_off = num_verts % 2; + break; + case GL_POLYGON: + if (num_verts < 3) + verts_off = num_verts; + break; + default: + assert(0); + return -1; + break; + } + + return num_verts - verts_off; +} + static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim) { context_t *context = R700_CONTEXT(ctx); BATCH_LOCALS(&context->radeon); int type, i, total_emit; - int num_indices = end - start; + int num_indices; uint32_t vgt_draw_initiator = 0; uint32_t vgt_index_type = 0; uint32_t vgt_primitive_type = 0; uint32_t vgt_num_indices = 0; type = r700PrimitiveType(prim); + num_indices = r700NumVerts(end - start, prim); if (type < 0 || num_indices <= 0) return; -- cgit v1.2.3 From af1dc225c2af6fd188cee8b0e2447d6b769518b3 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 17 Aug 2009 18:16:38 -0400 Subject: r600: fix counting error after the last commit --- src/mesa/drivers/dri/r600/r700_render.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 9e2971a343..6985bd4ffa 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -323,7 +323,7 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim R600_OUT_BATCH(vgt_num_indices); R600_OUT_BATCH(vgt_draw_initiator); - for (i = start; i < end; i++) { + for (i = start; i < (start + num_indices); i++) { R600_OUT_BATCH(i); } END_BATCH(); -- cgit v1.2.3 From 525ddb1f56aceee74a08764315dc6420f198ccc2 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 20 Aug 2009 03:19:58 -0400 Subject: r600: rework emit code make sure we allocate enough space for relocs --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 32 +++++++++++++------------- src/mesa/drivers/dri/r600/r600_cmdbuf.h | 4 +++- src/mesa/drivers/dri/r600/r700_chip.c | 40 +++++++++++++++++++-------------- src/mesa/drivers/dri/r600/r700_render.c | 5 +++-- 4 files changed, 44 insertions(+), 37 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index dc2fb0144a..83687bb720 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -129,10 +129,10 @@ int r600_cs_write_reloc(struct radeon_cs *cs, } relocs[i].indices = indices; relocs[i].reloc_indices = reloc_indices; - relocs[i].indices[relocs[i].cindices - 1] = cs->cdw - 1; - relocs[i].reloc_indices[relocs[i].cindices - 1] = cs->section_cdw; - cs->section_ndw += 2; + relocs[i].indices[relocs[i].cindices - 1] = cs->cdw; + relocs[i].reloc_indices[relocs[i].cindices - 1] = cs->cdw; cs->section_cdw += 2; + cs->cdw += 2; return 0; } @@ -156,10 +156,10 @@ int r600_cs_write_reloc(struct radeon_cs *cs, return -ENOMEM; } - relocs[cs->crelocs].indices[0] = cs->cdw - 1; - relocs[cs->crelocs].reloc_indices[0] = cs->section_cdw; - cs->section_ndw += 2; + relocs[cs->crelocs].indices[0] = cs->cdw; + relocs[cs->crelocs].reloc_indices[0] = cs->cdw; cs->section_cdw += 2; + cs->cdw += 2; relocs[cs->crelocs].cindices = 1; cs->relocs_total_size += radeon_bo_legacy_relocs_size(bo); cs->crelocs++; @@ -183,7 +183,14 @@ static int r600_cs_begin(struct radeon_cs *cs, return -EPIPE; } - if (cs->cdw + ndw + 32 > cs->ndw) { /* Left 32 DWORD (8 offset+pitch) spare room for reloc indices */ + cs->section = 1; + cs->section_ndw = ndw; + cs->section_cdw = 0; + cs->section_file = file; + cs->section_func = func; + cs->section_line = line; + + if (cs->cdw + ndw > cs->ndw) { uint32_t tmp, *ptr; int num = (ndw > 0x3FF) ? ndw : 0x3FF; @@ -196,13 +203,6 @@ static int r600_cs_begin(struct radeon_cs *cs, cs->ndw = tmp; } - cs->section = 1; - cs->section_ndw = 0; - cs->section_cdw = cs->cdw + ndw; /* start of reloc indices. */ - cs->section_file = file; - cs->section_func = func; - cs->section_line = line; - return 0; } @@ -219,8 +219,7 @@ static int r600_cs_end(struct radeon_cs *cs, } cs->section = 0; - if ( (cs->section_ndw + cs->cdw) != cs->section_cdw ) - { + if ( cs->section_ndw != cs->section_cdw ) { fprintf(stderr, "CS section size missmatch start at (%s,%s,%d) %d vs %d\n", cs->section_file, cs->section_func, cs->section_line, cs->section_ndw, cs->section_cdw); fprintf(stderr, "cs->section_ndw = %d, cs->cdw = %d, cs->section_cdw = %d \n", @@ -230,7 +229,6 @@ static int r600_cs_end(struct radeon_cs *cs, return -EPIPE; } - cs->cdw = cs->section_cdw; return 0; } diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.h b/src/mesa/drivers/dri/r600/r600_cmdbuf.h index 5df0cf1ab6..06eddf2eee 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.h +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.h @@ -143,6 +143,9 @@ extern int r600_cs_write_reloc(struct radeon_cs *cs, static inline void r600_cs_write_dword(struct radeon_cs *cs, uint32_t dword) { cs->packets[cs->cdw++] = dword; + if (cs->section) { + cs->section_cdw++; + } } struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_context *ctx); @@ -175,7 +178,6 @@ struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_cont fprintf(stderr, "(%s:%s:%d) offset : %d\n", \ __FILE__, __FUNCTION__, __LINE__, offset); \ } \ - r600_cs_write_dword(b_l_rmesa->cmdbuf.cs, offset); \ r600_cs_write_reloc(b_l_rmesa->cmdbuf.cs, \ bo, rd, wd, flags); \ } while(0) diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index f461d08a70..c3c0923ebb 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -276,11 +276,16 @@ GLboolean r700SendTextureState(context_t *context) RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, TC_ACTION_ENA_bit); - BEGIN_BATCH_NO_AUTOSTATE(9); + BEGIN_BATCH_NO_AUTOSTATE(9 + 4); R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); R600_OUT_BATCH(i * 7); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0); R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1); + R600_OUT_BATCH(0); /* r700->textures[i]->SQ_TEX_RESOURCE2 */ + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6); R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2, bo, 0, @@ -289,9 +294,6 @@ GLboolean r700SendTextureState(context_t *context) bo, r700->textures[i]->SQ_TEX_RESOURCE3, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6); END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(5); @@ -362,22 +364,21 @@ void r700SetupVTXConstants(GLcontext * ctx, SETfield(uSQ_VTX_CONSTANT_WORD6_0, SQ_TEX_VTX_VALID_BUFFER, SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask); - BEGIN_BATCH_NO_AUTOSTATE(9); + BEGIN_BATCH_NO_AUTOSTATE(9 + 2); R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); R600_OUT_BATCH((nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE); - - R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0, - paos->bo, - uSQ_VTX_CONSTANT_WORD0_0, - RADEON_GEM_DOMAIN_GTT, 0, 0); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0); R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0); R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0); R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0); R600_OUT_BATCH(0); R600_OUT_BATCH(0); R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0); - + R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0, + paos->bo, + uSQ_VTX_CONSTANT_WORD0_0, + RADEON_GEM_DOMAIN_GTT, 0, 0); END_BATCH(); COMMIT_BATCH(); @@ -515,16 +516,17 @@ GLboolean r700SendDepthTargetState(context_t *context) return GL_FALSE; } - BEGIN_BATCH_NO_AUTOSTATE(8); + BEGIN_BATCH_NO_AUTOSTATE(8 + 2); R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2); R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All); R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All); R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 2); + R600_OUT_BATCH(r700->DB_DEPTH_BASE.u32All); + R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All); R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All, rrb->bo, r700->DB_DEPTH_BASE.u32All, 0, RADEON_GEM_DOMAIN_VRAM, 0); - R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All); END_BATCH(); if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) && @@ -561,8 +563,9 @@ GLboolean r700SendRenderTargetState(context_t *context, int id) if (!r700->render_target[id].enabled) return GL_FALSE; - BEGIN_BATCH_NO_AUTOSTATE(3); + BEGIN_BATCH_NO_AUTOSTATE(3 + 2); R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1); + R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_BASE.u32All); R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All, rrb->bo, r700->render_target[id].CB_COLOR0_BASE.u32All, @@ -607,8 +610,9 @@ GLboolean r700SendPSState(context_t *context) r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); - BEGIN_BATCH_NO_AUTOSTATE(3); + BEGIN_BATCH_NO_AUTOSTATE(3 + 2); R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1); + R600_OUT_BATCH(r700->ps.SQ_PGM_START_PS.u32All); R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All, pbo, r700->ps.SQ_PGM_START_PS.u32All, @@ -639,8 +643,9 @@ GLboolean r700SendVSState(context_t *context) r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); - BEGIN_BATCH_NO_AUTOSTATE(3); + BEGIN_BATCH_NO_AUTOSTATE(3 + 2); R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1); + R600_OUT_BATCH(r700->vs.SQ_PGM_START_VS.u32All); R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All, pbo, r700->vs.SQ_PGM_START_VS.u32All, @@ -679,8 +684,9 @@ GLboolean r700SendFSState(context_t *context) r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); - BEGIN_BATCH_NO_AUTOSTATE(3); + BEGIN_BATCH_NO_AUTOSTATE(3 + 2); R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1); + R600_OUT_BATCH(r700->fs.SQ_PGM_START_FS.u32All); R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All, pbo, r700->fs.SQ_PGM_START_FS.u32All, diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 6985bd4ffa..58b4491d00 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -166,15 +166,16 @@ GLboolean r700SyncSurf(context_t *context, else cp_coher_size = ((pbo->size + 255) >> 8); - BEGIN_BATCH_NO_AUTOSTATE(5); + BEGIN_BATCH_NO_AUTOSTATE(5 + 2); R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_SYNC, 3)); R600_OUT_BATCH(sync_type); R600_OUT_BATCH(cp_coher_size); + R600_OUT_BATCH(0); + R600_OUT_BATCH(10); R600_OUT_BATCH_RELOC(0, pbo, 0, read_domain, write_domain, 0); // ??? - R600_OUT_BATCH(10); END_BATCH(); COMMIT_BATCH(); -- cgit v1.2.3 From 0f0a9e3ee752f1746d6dba748522fb3e15e4af1a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 20 Aug 2009 12:10:42 -0400 Subject: r600: try and get everything in the draw in one IB fixes corruption issues with apps like teapot and geartrain. --- src/mesa/drivers/dri/r600/r700_render.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 58b4491d00..80df78f123 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -341,10 +341,9 @@ void r700EmitState(GLcontext * ctx) return; rcommonEnsureCmdBufSpace(&context->radeon, - context->radeon.hw.max_state_size, __FUNCTION__); + 652, __FUNCTION__); r700SendSQConfig(context); - r700SendUCPState(context); r700SendContextStates(context); r700SendViewportState(context, 0); @@ -357,10 +356,18 @@ static GLboolean r700RunRender(GLcontext * ctx, struct tnl_pipeline_stage *stage) { context_t *context = R700_CONTEXT(ctx); - unsigned int i; + radeonContextPtr radeon = &context->radeon; + unsigned int i, ind_count = 0; TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; + for (i = 0; i < vb->PrimitiveCount; i++) + ind_count += vb->Primitive[i].count + 10; + + /* just an estimate, need to properly calculate this */ + rcommonEnsureCmdBufSpace(&context->radeon, + radeon->hw.max_state_size + ind_count, __FUNCTION__); + r700Start3D(context); r700UpdateShaders(ctx); -- cgit v1.2.3 From ad36058e21630bcb13244ff5939cb7ced44eb715 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 20 Aug 2009 16:07:07 -0400 Subject: r600: split state emit into block specific functions We probably want to go finer grained eventually, but this is a good start. --- src/mesa/drivers/dri/r600/r600_context.c | 16 - src/mesa/drivers/dri/r600/r600_context.h | 11 +- src/mesa/drivers/dri/r600/r700_chip.c | 616 +++++++++++++++------------- src/mesa/drivers/dri/r600/r700_chip.h | 45 +- src/mesa/drivers/dri/r600/r700_render.c | 9 +- src/mesa/drivers/dri/radeon/radeon_screen.c | 2 +- 6 files changed, 379 insertions(+), 320 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 7009374b0c..4489064c0d 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -247,8 +247,6 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, */ _mesa_init_driver_functions(&functions); - r700InitChipObject(r600); /* let the eag... */ - r700InitStateFuncs(&functions); r600InitTextureFuncs(&functions); r700InitShaderFuncs(&functions); @@ -386,18 +384,4 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, return GL_TRUE; } -/* Clean our own things only, radeonDestroyContext will do every thing else. */ -void -r600DestroyContext (__DRIcontextPrivate * driContextPriv) -{ - GET_CURRENT_CONTEXT (ctx); - context_t *context = ctx ? R700_CONTEXT(ctx) : NULL; - - if (context) - FREE(context->hw.pStateList); - - radeonDestroyContext(driContextPriv); -} - - diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index 4373254dd6..17ac088901 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -131,15 +131,20 @@ struct r600_context { #define R700_CONTEXT(ctx) ((context_t *)(ctx->DriverCtx)) #define GL_CONTEXT(context) ((GLcontext *)(context->radeon.glCtx)) -extern void r600DestroyContext(__DRIcontextPrivate * driContextPriv); extern GLboolean r600CreateContext(const __GLcontextModes * glVisual, __DRIcontextPrivate * driContextPriv, void *sharedContextPrivate); #define R700_CONTEXT_STATES(context) ((R700_CHIP_CONTEXT *)(&context->hw)) -extern GLboolean r700InitChipObject(context_t *context); -extern GLboolean r700SendContextStates(context_t *context); +extern GLboolean r700SendSPIState(context_t *context); +extern GLboolean r700SendVGTState(context_t *context); +extern GLboolean r700SendSXState(context_t *context); +extern GLboolean r700SendDBState(context_t *context); +extern GLboolean r700SendCBState(context_t *context); +extern GLboolean r700SendSUState(context_t *context); +extern GLboolean r700SendCLState(context_t *context); +extern GLboolean r700SendSCState(context_t *context); extern GLboolean r700SendViewportState(context_t *context, int id); extern GLboolean r700SendRenderTargetState(context_t *context, int id); extern GLboolean r700SendTextureState(context_t *context); diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 43661ec714..e67e544d53 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -40,215 +40,6 @@ #include "radeon_mipmap_tree.h" -#define LINK_STATES(reg) \ -do \ -{ \ - pStateListWork->puiValue = (unsigned int*)&(r700->reg); \ - pStateListWork->unOffset = mm##reg - ASIC_CONTEXT_BASE_INDEX; \ - pStateListWork->pNext = pStateListWork + 1; \ - pStateListWork++; \ -}while(0) - -GLboolean r700InitChipObject(context_t *context) -{ - ContextState * pStateListWork; - - R700_CHIP_CONTEXT *r700 = &context->hw; - - /* init state list */ - r700->pStateList = (ContextState*) MALLOC (sizeof(ContextState)*sizeof(R700_CHIP_CONTEXT)/sizeof(unsigned int)); - pStateListWork = r700->pStateList; - - // SC - LINK_STATES(PA_SC_SCREEN_SCISSOR_TL); - LINK_STATES(PA_SC_SCREEN_SCISSOR_BR); - LINK_STATES(PA_SC_WINDOW_OFFSET); - LINK_STATES(PA_SC_WINDOW_SCISSOR_TL); - LINK_STATES(PA_SC_WINDOW_SCISSOR_BR); - LINK_STATES(PA_SC_CLIPRECT_RULE); - LINK_STATES(PA_SC_CLIPRECT_0_TL); - LINK_STATES(PA_SC_CLIPRECT_0_BR); - LINK_STATES(PA_SC_CLIPRECT_1_TL); - LINK_STATES(PA_SC_CLIPRECT_1_BR); - LINK_STATES(PA_SC_CLIPRECT_2_TL); - LINK_STATES(PA_SC_CLIPRECT_2_BR); - LINK_STATES(PA_SC_CLIPRECT_3_TL); - LINK_STATES(PA_SC_CLIPRECT_3_BR); - LINK_STATES(PA_SC_EDGERULE); - LINK_STATES(PA_SC_GENERIC_SCISSOR_TL); - LINK_STATES(PA_SC_GENERIC_SCISSOR_BR); - LINK_STATES(PA_SC_LINE_STIPPLE); - LINK_STATES(PA_SC_MPASS_PS_CNTL); - LINK_STATES(PA_SC_MODE_CNTL); - LINK_STATES(PA_SC_LINE_CNTL); - LINK_STATES(PA_SC_AA_CONFIG); - LINK_STATES(PA_SC_AA_SAMPLE_LOCS_MCTX); - LINK_STATES(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX); - LINK_STATES(PA_SC_AA_MASK); - - // SU - LINK_STATES(PA_SU_POINT_SIZE); - LINK_STATES(PA_SU_POINT_MINMAX); - LINK_STATES(PA_SU_LINE_CNTL); - LINK_STATES(PA_SU_SC_MODE_CNTL); - LINK_STATES(PA_SU_VTX_CNTL); - LINK_STATES(PA_SU_POLY_OFFSET_DB_FMT_CNTL); - LINK_STATES(PA_SU_POLY_OFFSET_CLAMP); - LINK_STATES(PA_SU_POLY_OFFSET_FRONT_SCALE); - LINK_STATES(PA_SU_POLY_OFFSET_FRONT_OFFSET); - LINK_STATES(PA_SU_POLY_OFFSET_BACK_SCALE); - LINK_STATES(PA_SU_POLY_OFFSET_BACK_OFFSET); - - // CL - LINK_STATES(PA_CL_CLIP_CNTL); - LINK_STATES(PA_CL_VTE_CNTL); - LINK_STATES(PA_CL_VS_OUT_CNTL); - LINK_STATES(PA_CL_NANINF_CNTL); - LINK_STATES(PA_CL_GB_VERT_CLIP_ADJ); - LINK_STATES(PA_CL_GB_VERT_DISC_ADJ); - LINK_STATES(PA_CL_GB_HORZ_CLIP_ADJ); - LINK_STATES(PA_CL_GB_HORZ_DISC_ADJ); - - // CB - LINK_STATES(CB_CLEAR_RED_R6XX); - LINK_STATES(CB_CLEAR_GREEN_R6XX); - LINK_STATES(CB_CLEAR_BLUE_R6XX); - LINK_STATES(CB_CLEAR_ALPHA_R6XX); - LINK_STATES(CB_TARGET_MASK); - LINK_STATES(CB_SHADER_MASK); - LINK_STATES(CB_BLEND_RED); - LINK_STATES(CB_BLEND_GREEN); - LINK_STATES(CB_BLEND_BLUE); - LINK_STATES(CB_BLEND_ALPHA); - LINK_STATES(CB_FOG_RED_R6XX); - LINK_STATES(CB_FOG_GREEN_R6XX); - LINK_STATES(CB_FOG_BLUE_R6XX); - LINK_STATES(CB_SHADER_CONTROL); - LINK_STATES(CB_COLOR_CONTROL); - LINK_STATES(CB_CLRCMP_CONTROL); - LINK_STATES(CB_CLRCMP_SRC); - LINK_STATES(CB_CLRCMP_DST); - LINK_STATES(CB_CLRCMP_MSK); - LINK_STATES(CB_BLEND_CONTROL); - - //DB - LINK_STATES(DB_HTILE_DATA_BASE); - LINK_STATES(DB_STENCIL_CLEAR); - LINK_STATES(DB_DEPTH_CLEAR); - LINK_STATES(DB_STENCILREFMASK); - LINK_STATES(DB_STENCILREFMASK_BF); - LINK_STATES(DB_DEPTH_CONTROL); - LINK_STATES(DB_SHADER_CONTROL); - LINK_STATES(DB_RENDER_CONTROL); - LINK_STATES(DB_RENDER_OVERRIDE); - LINK_STATES(DB_HTILE_SURFACE); - LINK_STATES(DB_ALPHA_TO_MASK); - - // SX - LINK_STATES(SX_MISC); - LINK_STATES(SX_ALPHA_TEST_CONTROL); - LINK_STATES(SX_ALPHA_REF); - - // VGT - LINK_STATES(VGT_MAX_VTX_INDX); - LINK_STATES(VGT_MIN_VTX_INDX); - LINK_STATES(VGT_INDX_OFFSET); - LINK_STATES(VGT_MULTI_PRIM_IB_RESET_INDX); - LINK_STATES(VGT_OUTPUT_PATH_CNTL); - LINK_STATES(VGT_HOS_CNTL); - LINK_STATES(VGT_HOS_MAX_TESS_LEVEL); - LINK_STATES(VGT_HOS_MIN_TESS_LEVEL); - LINK_STATES(VGT_HOS_REUSE_DEPTH); - LINK_STATES(VGT_GROUP_PRIM_TYPE); - LINK_STATES(VGT_GROUP_FIRST_DECR); - LINK_STATES(VGT_GROUP_DECR); - LINK_STATES(VGT_GROUP_VECT_0_CNTL); - LINK_STATES(VGT_GROUP_VECT_1_CNTL); - LINK_STATES(VGT_GROUP_VECT_0_FMT_CNTL); - LINK_STATES(VGT_GROUP_VECT_1_FMT_CNTL); - LINK_STATES(VGT_GS_MODE); - LINK_STATES(VGT_PRIMITIVEID_EN); - LINK_STATES(VGT_MULTI_PRIM_IB_RESET_EN); - LINK_STATES(VGT_INSTANCE_STEP_RATE_0); - LINK_STATES(VGT_INSTANCE_STEP_RATE_1); - LINK_STATES(VGT_STRMOUT_EN); - LINK_STATES(VGT_REUSE_OFF); - LINK_STATES(VGT_VTX_CNT_EN); - LINK_STATES(VGT_STRMOUT_BUFFER_EN); - - LINK_STATES(SQ_VTX_SEMANTIC_0); - LINK_STATES(SQ_VTX_SEMANTIC_1); - LINK_STATES(SQ_VTX_SEMANTIC_2); - LINK_STATES(SQ_VTX_SEMANTIC_3); - LINK_STATES(SQ_VTX_SEMANTIC_4); - LINK_STATES(SQ_VTX_SEMANTIC_5); - LINK_STATES(SQ_VTX_SEMANTIC_6); - LINK_STATES(SQ_VTX_SEMANTIC_7); - LINK_STATES(SQ_VTX_SEMANTIC_8); - LINK_STATES(SQ_VTX_SEMANTIC_9); - LINK_STATES(SQ_VTX_SEMANTIC_10); - LINK_STATES(SQ_VTX_SEMANTIC_11); - LINK_STATES(SQ_VTX_SEMANTIC_12); - LINK_STATES(SQ_VTX_SEMANTIC_13); - LINK_STATES(SQ_VTX_SEMANTIC_14); - LINK_STATES(SQ_VTX_SEMANTIC_15); - LINK_STATES(SQ_VTX_SEMANTIC_16); - LINK_STATES(SQ_VTX_SEMANTIC_17); - LINK_STATES(SQ_VTX_SEMANTIC_18); - LINK_STATES(SQ_VTX_SEMANTIC_19); - LINK_STATES(SQ_VTX_SEMANTIC_20); - LINK_STATES(SQ_VTX_SEMANTIC_21); - LINK_STATES(SQ_VTX_SEMANTIC_22); - LINK_STATES(SQ_VTX_SEMANTIC_23); - LINK_STATES(SQ_VTX_SEMANTIC_24); - LINK_STATES(SQ_VTX_SEMANTIC_25); - LINK_STATES(SQ_VTX_SEMANTIC_26); - LINK_STATES(SQ_VTX_SEMANTIC_27); - LINK_STATES(SQ_VTX_SEMANTIC_28); - LINK_STATES(SQ_VTX_SEMANTIC_29); - LINK_STATES(SQ_VTX_SEMANTIC_30); - LINK_STATES(SQ_VTX_SEMANTIC_31); - - // SPI - LINK_STATES(SPI_VS_OUT_ID_0); - LINK_STATES(SPI_VS_OUT_ID_1); - LINK_STATES(SPI_VS_OUT_ID_2); - LINK_STATES(SPI_VS_OUT_ID_3); - LINK_STATES(SPI_VS_OUT_ID_4); - LINK_STATES(SPI_VS_OUT_ID_5); - LINK_STATES(SPI_VS_OUT_ID_6); - LINK_STATES(SPI_VS_OUT_ID_7); - LINK_STATES(SPI_VS_OUT_ID_8); - LINK_STATES(SPI_VS_OUT_ID_9); - - LINK_STATES(SPI_VS_OUT_CONFIG); - LINK_STATES(SPI_THREAD_GROUPING); - LINK_STATES(SPI_PS_IN_CONTROL_0); - LINK_STATES(SPI_PS_IN_CONTROL_1); - LINK_STATES(SPI_INTERP_CONTROL_0); - LINK_STATES(SPI_INPUT_Z); - LINK_STATES(SPI_FOG_CNTL); - LINK_STATES(SPI_FOG_FUNC_SCALE); - LINK_STATES(SPI_FOG_FUNC_BIAS); - - // SQ - LINK_STATES(SQ_ESGS_RING_ITEMSIZE); - LINK_STATES(SQ_GSVS_RING_ITEMSIZE); - LINK_STATES(SQ_ESTMP_RING_ITEMSIZE); - LINK_STATES(SQ_GSTMP_RING_ITEMSIZE); - LINK_STATES(SQ_VSTMP_RING_ITEMSIZE); - LINK_STATES(SQ_PSTMP_RING_ITEMSIZE); - LINK_STATES(SQ_FBUF_RING_ITEMSIZE); - LINK_STATES(SQ_REDUC_RING_ITEMSIZE); - //LINK_STATES(SQ_GS_VERT_ITEMSIZE); - - pStateListWork->puiValue = (unsigned int*)&(r700->SQ_GS_VERT_ITEMSIZE); - pStateListWork->unOffset = mmSQ_GS_VERT_ITEMSIZE - ASIC_CONTEXT_BASE_INDEX; - pStateListWork->pNext = NULL; /* END OF STATE LIST */ - - return GL_TRUE; -} - GLboolean r700SendTextureState(context_t *context) { unsigned int i; @@ -429,74 +220,6 @@ int r700SetupStreams(GLcontext * ctx) return R600_FALLBACK_NONE; } -GLboolean r700SendContextStates(context_t *context) -{ - BATCH_LOCALS(&context->radeon); - - R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); - - ContextState * pState = r700->pStateList; - ContextState * pInit; - unsigned int toSend; - unsigned int ui; - - while(NULL != pState) - { - toSend = 1; - - pInit = pState; - - while(NULL != pState->pNext) - { - if ((pState->pNext->unOffset - pState->unOffset) > 1) - { - break; - } - else - { - pState = pState->pNext; - toSend++; - } - } - - pState = pState->pNext; - - BEGIN_BATCH_NO_AUTOSTATE(toSend + 2); - R600_OUT_BATCH_REGSEQ(((pInit->unOffset + ASIC_CONTEXT_BASE_INDEX)<<2), toSend); - for(ui=0; uipuiValue)); - pInit = pInit->pNext; - }; - END_BATCH(); - }; - - /* todo: - * - split this into a separate function? - * - only emit the ones we use - */ - BEGIN_BATCH_NO_AUTOSTATE(2 + R700_MAX_SHADER_EXPORTS); - R600_OUT_BATCH_REGSEQ(SPI_PS_INPUT_CNTL_0, R700_MAX_SHADER_EXPORTS); - for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++) - R600_OUT_BATCH(r700->SPI_PS_INPUT_CNTL[ui].u32All); - END_BATCH(); - - if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) { - for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) { - if (r700->render_target[ui].enabled) { - BEGIN_BATCH_NO_AUTOSTATE(3); - R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * ui), - r700->render_target[ui].CB_BLEND0_CONTROL.u32All); - END_BATCH(); - } - } - } - - COMMIT_BATCH(); - - return GL_TRUE; -} - GLboolean r700SendDepthTargetState(context_t *context) { R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); @@ -733,7 +456,7 @@ GLboolean r700SendSQConfig(context_t *context) R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); - BEGIN_BATCH_NO_AUTOSTATE(8); + BEGIN_BATCH_NO_AUTOSTATE(34); R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6); R600_OUT_BATCH(r700->sq_config.SQ_CONFIG.u32All); R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All); @@ -741,14 +464,23 @@ GLboolean r700SendSQConfig(context_t *context) R600_OUT_BATCH(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All); R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All); R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All); - END_BATCH(); - BEGIN_BATCH_NO_AUTOSTATE(15); R600_OUT_BATCH_REGVAL(TA_CNTL_AUX, r700->TA_CNTL_AUX.u32All); R600_OUT_BATCH_REGVAL(VC_ENHANCE, r700->VC_ENHANCE.u32All); R600_OUT_BATCH_REGVAL(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All); R600_OUT_BATCH_REGVAL(DB_DEBUG, r700->DB_DEBUG.u32All); R600_OUT_BATCH_REGVAL(DB_WATERMARKS, r700->DB_WATERMARKS.u32All); + + R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE, 9); + R600_OUT_BATCH(r700->SQ_ESGS_RING_ITEMSIZE.u32All); + R600_OUT_BATCH(r700->SQ_GSVS_RING_ITEMSIZE.u32All); + R600_OUT_BATCH(r700->SQ_ESTMP_RING_ITEMSIZE.u32All); + R600_OUT_BATCH(r700->SQ_GSTMP_RING_ITEMSIZE.u32All); + R600_OUT_BATCH(r700->SQ_VSTMP_RING_ITEMSIZE.u32All); + R600_OUT_BATCH(r700->SQ_PSTMP_RING_ITEMSIZE.u32All); + R600_OUT_BATCH(r700->SQ_FBUF_RING_ITEMSIZE.u32All); + R600_OUT_BATCH(r700->SQ_REDUC_RING_ITEMSIZE.u32All); + R600_OUT_BATCH(r700->SQ_GS_VERT_ITEMSIZE.u32All); END_BATCH(); COMMIT_BATCH(); @@ -778,3 +510,327 @@ GLboolean r700SendUCPState(context_t *context) return GL_TRUE; } +GLboolean r700SendSPIState(context_t *context) +{ + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + BATCH_LOCALS(&context->radeon); + unsigned int ui; + + BEGIN_BATCH_NO_AUTOSTATE(59 + R700_MAX_SHADER_EXPORTS); + + R600_OUT_BATCH_REGSEQ(SQ_VTX_SEMANTIC_0, 32); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_0.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_1.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_2.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_3.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_4.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_5.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_6.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_7.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_8.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_9.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_10.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_11.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_12.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_13.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_14.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_15.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_16.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_17.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_18.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_19.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_20.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_21.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_22.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_23.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_24.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_25.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_26.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_27.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_28.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_29.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_30.u32All); + R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_31.u32All); + + R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_ID_0, 10); + R600_OUT_BATCH(r700->SPI_VS_OUT_ID_0.u32All); + R600_OUT_BATCH(r700->SPI_VS_OUT_ID_1.u32All); + R600_OUT_BATCH(r700->SPI_VS_OUT_ID_2.u32All); + R600_OUT_BATCH(r700->SPI_VS_OUT_ID_3.u32All); + R600_OUT_BATCH(r700->SPI_VS_OUT_ID_4.u32All); + R600_OUT_BATCH(r700->SPI_VS_OUT_ID_5.u32All); + R600_OUT_BATCH(r700->SPI_VS_OUT_ID_6.u32All); + R600_OUT_BATCH(r700->SPI_VS_OUT_ID_7.u32All); + R600_OUT_BATCH(r700->SPI_VS_OUT_ID_8.u32All); + R600_OUT_BATCH(r700->SPI_VS_OUT_ID_9.u32All); + + R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_CONFIG, 9); + R600_OUT_BATCH(r700->SPI_VS_OUT_CONFIG.u32All); + R600_OUT_BATCH(r700->SPI_THREAD_GROUPING.u32All); + R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_0.u32All); + R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_1.u32All); + R600_OUT_BATCH(r700->SPI_INTERP_CONTROL_0.u32All); + R600_OUT_BATCH(r700->SPI_INPUT_Z.u32All); + R600_OUT_BATCH(r700->SPI_FOG_CNTL.u32All); + R600_OUT_BATCH(r700->SPI_FOG_FUNC_SCALE.u32All); + R600_OUT_BATCH(r700->SPI_FOG_FUNC_BIAS.u32All); + + R600_OUT_BATCH_REGSEQ(SPI_PS_INPUT_CNTL_0, R700_MAX_SHADER_EXPORTS); + for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++) + R600_OUT_BATCH(r700->SPI_PS_INPUT_CNTL[ui].u32All); + + END_BATCH(); + COMMIT_BATCH(); + + return GL_TRUE; +} + +GLboolean r700SendVGTState(context_t *context) +{ + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + BATCH_LOCALS(&context->radeon); + + BEGIN_BATCH_NO_AUTOSTATE(41); + + R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX, 4); + R600_OUT_BATCH(r700->VGT_MAX_VTX_INDX.u32All); + R600_OUT_BATCH(r700->VGT_MIN_VTX_INDX.u32All); + R600_OUT_BATCH(r700->VGT_INDX_OFFSET.u32All); + R600_OUT_BATCH(r700->VGT_MULTI_PRIM_IB_RESET_INDX.u32All); + + R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL, 13); + R600_OUT_BATCH(r700->VGT_OUTPUT_PATH_CNTL.u32All); + R600_OUT_BATCH(r700->VGT_HOS_CNTL.u32All); + R600_OUT_BATCH(r700->VGT_HOS_MAX_TESS_LEVEL.u32All); + R600_OUT_BATCH(r700->VGT_HOS_MIN_TESS_LEVEL.u32All); + R600_OUT_BATCH(r700->VGT_HOS_REUSE_DEPTH.u32All); + R600_OUT_BATCH(r700->VGT_GROUP_PRIM_TYPE.u32All); + R600_OUT_BATCH(r700->VGT_GROUP_FIRST_DECR.u32All); + R600_OUT_BATCH(r700->VGT_GROUP_DECR.u32All); + R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_CNTL.u32All); + R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_CNTL.u32All); + R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_FMT_CNTL.u32All); + R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_FMT_CNTL.u32All); + R600_OUT_BATCH(r700->VGT_GS_MODE.u32All); + + R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN, r700->VGT_PRIMITIVEID_EN.u32All); + R600_OUT_BATCH_REGVAL(VGT_MULTI_PRIM_IB_RESET_EN, r700->VGT_MULTI_PRIM_IB_RESET_EN.u32All); + R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_0, r700->VGT_INSTANCE_STEP_RATE_0.u32All); + R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1, r700->VGT_INSTANCE_STEP_RATE_1.u32All); + + R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN, 3); + R600_OUT_BATCH(r700->VGT_STRMOUT_EN.u32All); + R600_OUT_BATCH(r700->VGT_REUSE_OFF.u32All); + R600_OUT_BATCH(r700->VGT_VTX_CNT_EN.u32All); + + R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN, r700->VGT_STRMOUT_BUFFER_EN.u32All); + + END_BATCH(); + COMMIT_BATCH(); + + return GL_TRUE; +} + +GLboolean r700SendSXState(context_t *context) +{ + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + BATCH_LOCALS(&context->radeon); + + BEGIN_BATCH_NO_AUTOSTATE(9); + R600_OUT_BATCH_REGVAL(SX_MISC, r700->SX_MISC.u32All); + R600_OUT_BATCH_REGVAL(SX_ALPHA_TEST_CONTROL, r700->SX_ALPHA_TEST_CONTROL.u32All); + R600_OUT_BATCH_REGVAL(SX_ALPHA_REF, r700->SX_ALPHA_REF.u32All); + END_BATCH(); + COMMIT_BATCH(); + + return GL_TRUE; +} + +GLboolean r700SendDBState(context_t *context) +{ + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + BATCH_LOCALS(&context->radeon); + + BEGIN_BATCH_NO_AUTOSTATE(27); + R600_OUT_BATCH_REGVAL(DB_HTILE_DATA_BASE, r700->DB_HTILE_DATA_BASE.u32All); + + R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2); + R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All); + R600_OUT_BATCH(r700->DB_DEPTH_CLEAR.u32All); + + R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2); + R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All); + R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All); + + R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, r700->DB_DEPTH_CONTROL.u32All); + R600_OUT_BATCH_REGVAL(DB_SHADER_CONTROL, r700->DB_SHADER_CONTROL.u32All); + + R600_OUT_BATCH_REGSEQ(DB_RENDER_CONTROL, 2); + R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All); + R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All); + + R600_OUT_BATCH_REGVAL(DB_HTILE_SURFACE, r700->DB_HTILE_SURFACE.u32All); + R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All); + + END_BATCH(); + COMMIT_BATCH(); + + return GL_TRUE; +} + +GLboolean r700SendCBState(context_t *context) +{ + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + BATCH_LOCALS(&context->radeon); + unsigned int ui; + + if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) { + BEGIN_BATCH_NO_AUTOSTATE(14); + R600_OUT_BATCH_REGSEQ(CB_CLEAR_RED, 4); + R600_OUT_BATCH(r700->CB_CLEAR_RED_R6XX.u32All); + R600_OUT_BATCH(r700->CB_CLEAR_GREEN_R6XX.u32All); + R600_OUT_BATCH(r700->CB_CLEAR_BLUE_R6XX.u32All); + R600_OUT_BATCH(r700->CB_CLEAR_ALPHA_R6XX.u32All); + R600_OUT_BATCH_REGSEQ(CB_FOG_RED, 3); + R600_OUT_BATCH(r700->CB_FOG_RED_R6XX.u32All); + R600_OUT_BATCH(r700->CB_FOG_GREEN_R6XX.u32All); + R600_OUT_BATCH(r700->CB_FOG_BLUE_R6XX.u32All); + /* R600 does not have per-MRT blend */ + R600_OUT_BATCH_REGVAL(CB_BLEND_CONTROL, r700->CB_BLEND_CONTROL.u32All); + END_BATCH(); + } + + BEGIN_BATCH_NO_AUTOSTATE(22); + R600_OUT_BATCH_REGSEQ(CB_TARGET_MASK, 2); + R600_OUT_BATCH(r700->CB_TARGET_MASK.u32All); + R600_OUT_BATCH(r700->CB_SHADER_MASK.u32All); + + R600_OUT_BATCH_REGSEQ(CB_BLEND_RED, 4); + R600_OUT_BATCH(r700->CB_BLEND_RED.u32All); + R600_OUT_BATCH(r700->CB_BLEND_GREEN.u32All); + R600_OUT_BATCH(r700->CB_BLEND_BLUE.u32All); + R600_OUT_BATCH(r700->CB_BLEND_ALPHA.u32All); + + R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL, r700->CB_SHADER_CONTROL.u32All); + R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL, r700->CB_COLOR_CONTROL.u32All); + + R600_OUT_BATCH_REGSEQ(CB_CLRCMP_CONTROL, 4); + R600_OUT_BATCH(r700->CB_CLRCMP_CONTROL.u32All); + R600_OUT_BATCH(r700->CB_CLRCMP_SRC.u32All); + R600_OUT_BATCH(r700->CB_CLRCMP_DST.u32All); + R600_OUT_BATCH(r700->CB_CLRCMP_MSK.u32All); + END_BATCH(); + + if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) { + for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) { + if (r700->render_target[ui].enabled) { + BEGIN_BATCH_NO_AUTOSTATE(3); + R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * ui), + r700->render_target[ui].CB_BLEND0_CONTROL.u32All); + END_BATCH(); + } + } + } + + COMMIT_BATCH(); + + return GL_TRUE; +} + +GLboolean r700SendSUState(context_t *context) +{ + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + BATCH_LOCALS(&context->radeon); + + BEGIN_BATCH_NO_AUTOSTATE(19); + R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL, r700->PA_SU_SC_MODE_CNTL.u32All); + + R600_OUT_BATCH_REGSEQ(PA_SU_POINT_SIZE, 4); + R600_OUT_BATCH(r700->PA_SU_POINT_SIZE.u32All); + R600_OUT_BATCH(r700->PA_SU_POINT_MINMAX.u32All); + R600_OUT_BATCH(r700->PA_SU_LINE_CNTL.u32All); + R600_OUT_BATCH(r700->PA_SU_VTX_CNTL.u32All); + + R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 2); + R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All); + R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_CLAMP.u32All); + + R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_FRONT_SCALE, 4); + R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All); + R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All); + R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_SCALE.u32All); + R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All); + + END_BATCH(); + COMMIT_BATCH(); + + return GL_TRUE; +} + +GLboolean r700SendCLState(context_t *context) +{ + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + BATCH_LOCALS(&context->radeon); + + BEGIN_BATCH_NO_AUTOSTATE(18); + R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, r700->PA_CL_CLIP_CNTL.u32All); + R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL, r700->PA_CL_VTE_CNTL.u32All); + R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL, r700->PA_CL_VS_OUT_CNTL.u32All); + R600_OUT_BATCH_REGVAL(PA_CL_NANINF_CNTL, r700->PA_CL_NANINF_CNTL.u32All); + + R600_OUT_BATCH_REGSEQ(PA_CL_GB_VERT_CLIP_ADJ, 4); + R600_OUT_BATCH(r700->PA_CL_GB_VERT_CLIP_ADJ.u32All); + R600_OUT_BATCH(r700->PA_CL_GB_VERT_DISC_ADJ.u32All); + R600_OUT_BATCH(r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All); + R600_OUT_BATCH(r700->PA_CL_GB_HORZ_DISC_ADJ.u32All); + + END_BATCH(); + COMMIT_BATCH(); + + return GL_TRUE; +} + +// XXX need to split this up +GLboolean r700SendSCState(context_t *context) +{ + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + BATCH_LOCALS(&context->radeon); + + BEGIN_BATCH_NO_AUTOSTATE(47); + R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2); + R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_TL.u32All); + R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_BR.u32All); + + R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 13); + R600_OUT_BATCH(r700->PA_SC_WINDOW_OFFSET.u32All); + R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_TL.u32All); + R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_BR.u32All); + R600_OUT_BATCH(r700->PA_SC_CLIPRECT_RULE.u32All); + R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_TL.u32All); + R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_BR.u32All); + R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_TL.u32All); + R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_BR.u32All); + R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_TL.u32All); + R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_BR.u32All); + R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_TL.u32All); + R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_BR.u32All); + R600_OUT_BATCH(r700->PA_SC_EDGERULE.u32All); + + R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2); + R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_TL.u32All); + R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_BR.u32All); + + R600_OUT_BATCH_REGVAL(PA_SC_LINE_STIPPLE, r700->PA_SC_LINE_STIPPLE.u32All); + R600_OUT_BATCH_REGVAL(PA_SC_MPASS_PS_CNTL, r700->PA_SC_MPASS_PS_CNTL.u32All); + R600_OUT_BATCH_REGVAL(PA_SC_MODE_CNTL, r700->PA_SC_MODE_CNTL.u32All); + R600_OUT_BATCH_REGVAL(PA_SC_LINE_CNTL, r700->PA_SC_LINE_CNTL.u32All); + R600_OUT_BATCH_REGVAL(PA_SC_AA_CONFIG, r700->PA_SC_AA_CONFIG.u32All); + R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_MCTX.u32All); + R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX.u32All); + R600_OUT_BATCH_REGVAL(PA_SC_AA_MASK, r700->PA_SC_AA_MASK.u32All); + + END_BATCH(); + COMMIT_BATCH(); + + return GL_TRUE; +} diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h index 4e89c75f2f..545e4a188a 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.h +++ b/src/mesa/drivers/dri/r600/r700_chip.h @@ -188,6 +188,7 @@ typedef struct _RENDER_TARGET_STATE_STRUCT union UINT_FLOAT CB_COLOR0_MASK; /* 0xA040 */ union UINT_FLOAT CB_BLEND0_CONTROL; /* 0xA1E0 */ GLboolean enabled; + GLboolean dirty; } RENDER_TARGET_STATE_STRUCT; typedef struct _VIEWPORT_STATE_STRUCT @@ -203,6 +204,7 @@ typedef struct _VIEWPORT_STATE_STRUCT union UINT_FLOAT PA_CL_VPORT_ZSCALE; /* 0xA113 */ union UINT_FLOAT PA_CL_VPORT_ZOFFSET; /* 0xA114 */ GLboolean enabled; + GLboolean dirty; } VIEWPORT_STATE_STRUCT; typedef struct _UCP_STATE_STRUCT @@ -212,6 +214,7 @@ typedef struct _UCP_STATE_STRUCT union UINT_FLOAT PA_CL_UCP_0_Z; union UINT_FLOAT PA_CL_UCP_0_W; GLboolean enabled; + GLboolean dirty; } UCP_STATE_STRUCT; typedef struct _PS_STATE_STRUCT @@ -220,6 +223,7 @@ typedef struct _PS_STATE_STRUCT union UINT_FLOAT SQ_PGM_RESOURCES_PS ; /* 0xA214 */ union UINT_FLOAT SQ_PGM_EXPORTS_PS ; /* 0xA215 */ union UINT_FLOAT SQ_PGM_CF_OFFSET_PS ; /* 0xA233 */ + GLboolean dirty; } PS_STATE_STRUCT; typedef struct _VS_STATE_STRUCT @@ -227,6 +231,7 @@ typedef struct _VS_STATE_STRUCT union UINT_FLOAT SQ_PGM_START_VS ; /* 0xA216 */ union UINT_FLOAT SQ_PGM_RESOURCES_VS ; /* 0xA21A */ union UINT_FLOAT SQ_PGM_CF_OFFSET_VS ; /* 0xA234 */ + GLboolean dirty; } VS_STATE_STRUCT; typedef struct _GS_STATE_STRUCT @@ -234,6 +239,7 @@ typedef struct _GS_STATE_STRUCT union UINT_FLOAT SQ_PGM_START_GS ; /* 0xA21B */ union UINT_FLOAT SQ_PGM_RESOURCES_GS ; /* 0xA21F */ union UINT_FLOAT SQ_PGM_CF_OFFSET_GS ; /* 0xA235 */ + GLboolean dirty; } GS_STATE_STRUCT; typedef struct _ES_STATE_STRUCT @@ -241,6 +247,7 @@ typedef struct _ES_STATE_STRUCT union UINT_FLOAT SQ_PGM_START_ES ; /* 0xA220 */ union UINT_FLOAT SQ_PGM_RESOURCES_ES ; /* 0xA224 */ union UINT_FLOAT SQ_PGM_CF_OFFSET_ES ; /* 0xA236 */ + GLboolean dirty; } ES_STATE_STRUCT; typedef struct _FS_STATE_STRUCT @@ -248,6 +255,7 @@ typedef struct _FS_STATE_STRUCT union UINT_FLOAT SQ_PGM_START_FS ; /* 0xA225 */ union UINT_FLOAT SQ_PGM_RESOURCES_FS ; /* 0xA229 */ union UINT_FLOAT SQ_PGM_CF_OFFSET_FS ; /* 0xA237 */ + GLboolean dirty; } FS_STATE_STRUCT; typedef struct _SQ_CONFIG_STRUCT @@ -260,22 +268,8 @@ typedef struct _SQ_CONFIG_STRUCT union UINT_FLOAT SQ_STACK_RESOURCE_MGMT_2 ; /* 0x2305 */ } SQ_CONFIG_STRUCT; -typedef struct ContextState -{ - unsigned int * puiValue; - unsigned int unOffset; - struct ContextState * pNext; -} ContextState; - typedef struct _R700_CHIP_CONTEXT { - // misc - union UINT_FLOAT TA_CNTL_AUX ; /* 0x2542 */ - union UINT_FLOAT VC_ENHANCE ; /* 0x25C5 */ - union UINT_FLOAT SQ_DYN_GPR_CNTL_PS_FLUSH_REQ; /* 0x2363 */ - union UINT_FLOAT DB_DEBUG ; /* 0x260C */ - union UINT_FLOAT DB_WATERMARKS ; /* 0x260E */ - // DB union UINT_FLOAT DB_DEPTH_SIZE ; /* 0xA000 */ union UINT_FLOAT DB_DEPTH_VIEW ; /* 0xA001 */ @@ -292,6 +286,7 @@ typedef struct _R700_CHIP_CONTEXT union UINT_FLOAT DB_ALPHA_TO_MASK ; /* 0xA351 */ union UINT_FLOAT DB_DEPTH_CONTROL ; /* 0xA200 */ union UINT_FLOAT DB_SHADER_CONTROL ; /* 0xA203 */ + GLboolean db_dirty; // SC union UINT_FLOAT PA_SC_SCREEN_SCISSOR_TL ; /* 0xA00C */ @@ -311,6 +306,8 @@ typedef struct _R700_CHIP_CONTEXT union UINT_FLOAT PA_SC_EDGERULE ; /* 0xA08C */ union UINT_FLOAT PA_SC_GENERIC_SCISSOR_TL ; /* 0xA090 */ union UINT_FLOAT PA_SC_GENERIC_SCISSOR_BR ; /* 0xA091 */ + GLboolean scissor_dirty; + union UINT_FLOAT PA_SC_LINE_STIPPLE ; /* 0xA283 */ union UINT_FLOAT PA_SC_LINE_CNTL ; /* 0xA300 */ union UINT_FLOAT PA_SC_AA_CONFIG ; /* 0xA301 */ @@ -319,6 +316,7 @@ typedef struct _R700_CHIP_CONTEXT union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_MCTX ; /* 0xA307 */ union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX; /* 0xA308 */ union UINT_FLOAT PA_SC_AA_MASK ; /* 0xA312 */ + GLboolean sc_dirty; // CL union UINT_FLOAT PA_CL_CLIP_CNTL ; /* 0xA204 */ @@ -329,6 +327,7 @@ typedef struct _R700_CHIP_CONTEXT union UINT_FLOAT PA_CL_GB_VERT_DISC_ADJ ; /* 0xA304 */ union UINT_FLOAT PA_CL_GB_HORZ_CLIP_ADJ ; /* 0xA305 */ union UINT_FLOAT PA_CL_GB_HORZ_DISC_ADJ ; /* 0xA306 */ + GLboolean cl_dirty; // SU union UINT_FLOAT PA_SU_SC_MODE_CNTL ; /* 0xA205 */ @@ -342,6 +341,7 @@ typedef struct _R700_CHIP_CONTEXT union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_OFFSET; /* 0xA381 */ union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_SCALE; /* 0xA382 */ union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_OFFSET; /* 0xA383 */ + GLboolean su_dirty; VIEWPORT_STATE_STRUCT viewport[R700_MAX_VIEWPORTS]; UCP_STATE_STRUCT ucp[R700_MAX_UCP]; @@ -367,12 +367,14 @@ typedef struct _R700_CHIP_CONTEXT union UINT_FLOAT CB_CLRCMP_DST ; /* 0xA30E */ union UINT_FLOAT CB_CLRCMP_MSK ; /* 0xA30F */ union UINT_FLOAT CB_BLEND_CONTROL ; /* 0xABD0 */ + GLboolean cb_dirty; RENDER_TARGET_STATE_STRUCT render_target[R700_MAX_RENDER_TARGETS]; // SX union UINT_FLOAT SX_MISC ; /* 0xA0D4 */ union UINT_FLOAT SX_ALPHA_TEST_CONTROL ; /* 0xA104 */ union UINT_FLOAT SX_ALPHA_REF ; /* 0xA10E */ + GLboolean sx_dirty; // VGT union UINT_FLOAT VGT_MAX_VTX_INDX ; /* 0xA100 */ @@ -400,6 +402,7 @@ typedef struct _R700_CHIP_CONTEXT union UINT_FLOAT VGT_REUSE_OFF ; /* 0xA2AD */ union UINT_FLOAT VGT_VTX_CNT_EN ; /* 0xA2AE */ union UINT_FLOAT VGT_STRMOUT_BUFFER_EN ; /* 0xA2C8 */ + GLboolean vgt_dirty; // SPI union UINT_FLOAT SPI_VS_OUT_ID_0 ; /* 0xA185 */ @@ -454,8 +457,8 @@ typedef struct _R700_CHIP_CONTEXT union UINT_FLOAT SQ_VTX_SEMANTIC_29 ; /* 0xA0FD */ union UINT_FLOAT SQ_VTX_SEMANTIC_30 ; /* 0xA0FE */ union UINT_FLOAT SQ_VTX_SEMANTIC_31 ; /* 0xA0FF */ - - union UINT_FLOAT SPI_PS_INPUT_CNTL[R700_MAX_SHADER_EXPORTS]; + union UINT_FLOAT SPI_PS_INPUT_CNTL[R700_MAX_SHADER_EXPORTS]; + GLboolean spi_dirty; // shaders PS_STATE_STRUCT ps; @@ -466,7 +469,12 @@ typedef struct _R700_CHIP_CONTEXT // SQ CONFIG SQ_CONFIG_STRUCT sq_config; - + // misc + union UINT_FLOAT TA_CNTL_AUX ; /* 0x2542 */ + union UINT_FLOAT VC_ENHANCE ; /* 0x25C5 */ + union UINT_FLOAT SQ_DYN_GPR_CNTL_PS_FLUSH_REQ; /* 0x2363 */ + union UINT_FLOAT DB_DEBUG ; /* 0x260C */ + union UINT_FLOAT DB_WATERMARKS ; /* 0x260E */ // SQ union UINT_FLOAT SQ_ESGS_RING_ITEMSIZE ; /* 0xA22A */ union UINT_FLOAT SQ_GSVS_RING_ITEMSIZE ; /* 0xA22B */ @@ -477,8 +485,7 @@ typedef struct _R700_CHIP_CONTEXT union UINT_FLOAT SQ_FBUF_RING_ITEMSIZE ; /* 0xA230 */ union UINT_FLOAT SQ_REDUC_RING_ITEMSIZE ; /* 0xA231 */ union UINT_FLOAT SQ_GS_VERT_ITEMSIZE ; /* 0xA232 */ - - ContextState* pStateList; + GLboolean sq_dirty; radeonTexObj* textures[R700_TEXTURE_NUMBERUNITS]; diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 80df78f123..1cc886d5e9 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -345,7 +345,14 @@ void r700EmitState(GLcontext * ctx) r700SendSQConfig(context); r700SendUCPState(context); - r700SendContextStates(context); + r700SendSCState(context); + r700SendSUState(context); + r700SendCLState(context); + r700SendCBState(context); + r700SendDBState(context); + r700SendSXState(context); + r700SendVGTState(context); + r700SendSPIState(context); r700SendViewportState(context, 0); r700SendRenderTargetState(context, 0); r700SendDepthTargetState(context); diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index c8d491621a..e28543d855 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -1797,7 +1797,7 @@ const struct __DriverAPIRec driDriverAPI = { .DestroyContext = r200DestroyContext, #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) .CreateContext = r600CreateContext, - .DestroyContext = r600DestroyContext, + .DestroyContext = radeonDestroyContext, #else .CreateContext = radeonCreateContext, .DestroyContext = radeonDestroyContext, -- cgit v1.2.3 From a47bb56d45af07b8cf1461c4c00620ec0b6aca41 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 20 Aug 2009 17:20:27 -0400 Subject: r600: improve state emission Slowing migrating to atom based system like the other radeon drivers. --- src/mesa/drivers/dri/r600/r600_context.h | 13 +++++ src/mesa/drivers/dri/r600/r700_chip.c | 33 +++++++++++- src/mesa/drivers/dri/r600/r700_chip.h | 1 + src/mesa/drivers/dri/r600/r700_clear.c | 6 --- src/mesa/drivers/dri/r600/r700_render.c | 66 ++++++++++++++++++----- src/mesa/drivers/dri/r600/r700_state.c | 93 ++++++++++++++++++++++++++++---- 6 files changed, 182 insertions(+), 30 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index 17ac088901..0cf2eb2daa 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -137,6 +137,19 @@ extern GLboolean r600CreateContext(const __GLcontextModes * glVisual, #define R700_CONTEXT_STATES(context) ((R700_CHIP_CONTEXT *)(&context->hw)) +#define R600_NEWPRIM( rmesa ) \ +do { \ + if ( rmesa->radeon.dma.flush ) \ + rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \ +} while (0) + +#define R600_STATECHANGE(r600, atom) \ +do { \ + R600_NEWPRIM(r600); \ + (atom) = GL_TRUE; \ + r600->radeon.hw.is_dirty = GL_TRUE; \ +} while(0) + extern GLboolean r700SendSPIState(context_t *context); extern GLboolean r700SendVGTState(context_t *context); extern GLboolean r700SendSXState(context_t *context); diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index e67e544d53..7f46b0c468 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -258,6 +258,8 @@ GLboolean r700SendDepthTargetState(context_t *context) r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM, DB_ACTION_ENA_bit | DB_DEST_BASE_ENA_bit); + r700->db_target_dirty = GL_FALSE; + return GL_TRUE; } @@ -310,6 +312,8 @@ GLboolean r700SendRenderTargetState(context_t *context, int id) r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM, CB_ACTION_ENA_bit | (1 << (id + 6))); + r700->render_target[id].dirty = GL_FALSE; + return GL_TRUE; } @@ -343,6 +347,8 @@ GLboolean r700SendPSState(context_t *context) COMMIT_BATCH(); + r700->ps.dirty = GL_FALSE; + return GL_TRUE; } @@ -375,6 +381,8 @@ GLboolean r700SendVSState(context_t *context) COMMIT_BATCH(); + r700->vs.dirty = GL_FALSE; + return GL_TRUE; } @@ -416,6 +424,8 @@ GLboolean r700SendFSState(context_t *context) COMMIT_BATCH(); + r700->fs.dirty = GL_FALSE; + return GL_TRUE; } @@ -448,6 +458,8 @@ GLboolean r700SendViewportState(context_t *context, int id) COMMIT_BATCH(); + r700->viewport[id].dirty = GL_FALSE; + return GL_TRUE; } @@ -485,6 +497,8 @@ GLboolean r700SendSQConfig(context_t *context) COMMIT_BATCH(); + r700->sq_dirty = GL_FALSE; + return GL_TRUE; } @@ -495,7 +509,7 @@ GLboolean r700SendUCPState(context_t *context) int i; for (i = 0; i < R700_MAX_UCP; i++) { - if (r700->ucp[i].enabled) { + if (r700->ucp[i].enabled && r700->ucp[i].dirty) { BEGIN_BATCH_NO_AUTOSTATE(6); R600_OUT_BATCH_REGSEQ(PA_CL_UCP_0_X + (16 * i), 4); R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_X.u32All); @@ -504,6 +518,7 @@ GLboolean r700SendUCPState(context_t *context) R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_W.u32All); END_BATCH(); COMMIT_BATCH(); + r700->ucp[i].dirty = GL_FALSE; } } @@ -582,6 +597,8 @@ GLboolean r700SendSPIState(context_t *context) END_BATCH(); COMMIT_BATCH(); + r700->spi_dirty = GL_FALSE; + return GL_TRUE; } @@ -628,6 +645,8 @@ GLboolean r700SendVGTState(context_t *context) END_BATCH(); COMMIT_BATCH(); + r700->vgt_dirty = GL_FALSE; + return GL_TRUE; } @@ -643,6 +662,8 @@ GLboolean r700SendSXState(context_t *context) END_BATCH(); COMMIT_BATCH(); + r700->sx_dirty = GL_FALSE; + return GL_TRUE; } @@ -675,6 +696,8 @@ GLboolean r700SendDBState(context_t *context) END_BATCH(); COMMIT_BATCH(); + r700->db_dirty = GL_FALSE; + return GL_TRUE; } @@ -734,6 +757,8 @@ GLboolean r700SendCBState(context_t *context) COMMIT_BATCH(); + r700->cb_dirty = GL_FALSE; + return GL_TRUE; } @@ -764,6 +789,8 @@ GLboolean r700SendSUState(context_t *context) END_BATCH(); COMMIT_BATCH(); + r700->su_dirty = GL_FALSE; + return GL_TRUE; } @@ -787,6 +814,8 @@ GLboolean r700SendCLState(context_t *context) END_BATCH(); COMMIT_BATCH(); + r700->cl_dirty = GL_FALSE; + return GL_TRUE; } @@ -832,5 +861,7 @@ GLboolean r700SendSCState(context_t *context) END_BATCH(); COMMIT_BATCH(); + r700->sc_dirty = GL_FALSE; + return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h index 545e4a188a..c0ec4b0dd5 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.h +++ b/src/mesa/drivers/dri/r600/r700_chip.h @@ -275,6 +275,7 @@ typedef struct _R700_CHIP_CONTEXT union UINT_FLOAT DB_DEPTH_VIEW ; /* 0xA001 */ union UINT_FLOAT DB_DEPTH_BASE ; /* 0xA003 */ union UINT_FLOAT DB_DEPTH_INFO ; /* 0xA004 */ + GLboolean db_target_dirty; union UINT_FLOAT DB_HTILE_DATA_BASE ; /* 0xA005 */ union UINT_FLOAT DB_STENCIL_CLEAR ; /* 0xA00A */ union UINT_FLOAT DB_DEPTH_CLEAR ; /* 0xA00B */ diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c index 05d4af331e..6d4ea90ccc 100644 --- a/src/mesa/drivers/dri/r600/r700_clear.c +++ b/src/mesa/drivers/dri/r600/r700_clear.c @@ -46,12 +46,6 @@ static GLboolean r700ClearFast(context_t *context, GLbitfield mask) return GL_FALSE; } -#define R600_NEWPRIM( rmesa ) \ - do { \ - if ( rmesa->radeon.dma.flush ) \ - rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \ - } while (0) - void r700Clear(GLcontext * ctx, GLbitfield mask) { context_t *context = R700_CONTEXT(ctx); diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 1cc886d5e9..52f8f90dad 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -332,30 +332,70 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim } +static void r700EmitAtoms(GLcontext * ctx, GLboolean dirty) +{ + context_t *context = R700_CONTEXT(ctx); + radeonContextPtr radeon = &context->radeon; + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + + if ((r700->sq_dirty || radeon->hw.all_dirty) == dirty) + r700SendSQConfig(context); + r700SendUCPState(context); + if ((r700->sc_dirty || radeon->hw.all_dirty) == dirty) + r700SendSCState(context); + if ((r700->su_dirty || radeon->hw.all_dirty) == dirty) + r700SendSUState(context); + if ((r700->cl_dirty || radeon->hw.all_dirty) == dirty) + r700SendCLState(context); + if ((r700->cb_dirty || radeon->hw.all_dirty) == dirty) + r700SendCBState(context); + if ((r700->db_dirty || radeon->hw.all_dirty) == dirty) + r700SendDBState(context); + if ((r700->sx_dirty || radeon->hw.all_dirty) == dirty) + r700SendSXState(context); + if ((r700->vgt_dirty || radeon->hw.all_dirty) == dirty) + r700SendVGTState(context); + if ((r700->spi_dirty || radeon->hw.all_dirty) == dirty) + r700SendSPIState(context); + if ((r700->viewport[0].dirty || radeon->hw.all_dirty) == dirty) + r700SendViewportState(context, 0); + if ((r700->render_target[0].dirty || radeon->hw.all_dirty) == dirty) + r700SendRenderTargetState(context, 0); + if ((r700->db_target_dirty || radeon->hw.all_dirty) == dirty) + r700SendDepthTargetState(context); + +} + void r700EmitState(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); radeonContextPtr radeon = &context->radeon; + if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS)) + fprintf(stderr, "%s\n", __FUNCTION__); + + if (radeon->vtbl.pre_emit_state) + radeon->vtbl.pre_emit_state(radeon); + if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw.all_dirty) return; rcommonEnsureCmdBufSpace(&context->radeon, 652, __FUNCTION__); - r700SendSQConfig(context); - r700SendUCPState(context); - r700SendSCState(context); - r700SendSUState(context); - r700SendCLState(context); - r700SendCBState(context); - r700SendDBState(context); - r700SendSXState(context); - r700SendVGTState(context); - r700SendSPIState(context); - r700SendViewportState(context, 0); - r700SendRenderTargetState(context, 0); - r700SendDepthTargetState(context); + if (!radeon->cmdbuf.cs->cdw) { + if (RADEON_DEBUG & DEBUG_STATE) + fprintf(stderr, "Begin reemit state\n"); + + r700EmitAtoms(ctx, GL_FALSE); + } + + if (RADEON_DEBUG & DEBUG_STATE) + fprintf(stderr, "Begin dirty state\n"); + + r700EmitAtoms(ctx, GL_TRUE); + radeon->hw.is_dirty = GL_FALSE; + radeon->hw.all_dirty = GL_FALSE; } diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 835b5e18c2..ada394ec61 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -148,8 +148,15 @@ void r700UpdateViewportOffset(GLcontext * ctx) //------------------ GLfloat tx = v[MAT_TX] + xoffset; GLfloat ty = (-v[MAT_TY]) + yoffset; - r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx; - r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty; + if (r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All != tx || + r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All != ty) { + /* Note: this should also modify whatever data the context reset + * code uses... + */ + R600_STATECHANGE(context, r700->viewport[id].dirty); + r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx; + r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty; + } radeonUpdateScissor(ctx); } @@ -161,6 +168,10 @@ void r700UpdateViewportOffset(GLcontext * ctx) //------------------ void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //--------------------- { context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + + R600_STATECHANGE(context, r700->render_target[0].dirty); + R600_STATECHANGE(context, r700->db_target_dirty); r700SetRenderTarget(context, 0); r700SetDepthTarget(context); @@ -233,6 +244,9 @@ static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //----------- r700UpdateStateParameters(ctx, new_state); + R600_STATECHANGE(context, r700->cl_dirty); + R600_STATECHANGE(context, r700->spi_dirty); + if(GL_TRUE == r700->bEnablePerspective) { /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */ @@ -256,14 +270,15 @@ static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //----------- SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit); } - context->radeon.NewGLState |= new_state; + context->radeon.NewGLState |= new_state; } static void r700SetDepthState(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + R600_STATECHANGE(context, r700->db_dirty); if (ctx->Depth.Test) { @@ -331,6 +346,8 @@ static void r700SetAlphaState(GLcontext * ctx) uint32_t alpha_func = REF_ALWAYS; GLboolean really_enabled = ctx->Color.AlphaEnabled; + R600_STATECHANGE(context, r700->sx_dirty); + switch (ctx->Color.AlphaFunc) { case GL_NEVER: alpha_func = REF_NEVER; @@ -383,6 +400,8 @@ static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //------------- context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + R600_STATECHANGE(context, r700->cb_dirty); + r700->CB_BLEND_RED.f32All = cf[0]; r700->CB_BLEND_GREEN.f32All = cf[1]; r700->CB_BLEND_BLUE.f32All = cf[2]; @@ -451,6 +470,8 @@ static void r700SetBlendState(GLcontext * ctx) int id = 0; uint32_t blend_reg = 0, eqn, eqnA; + R600_STATECHANGE(context, r700->cb_dirty); + if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) { SETfield(blend_reg, BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask); @@ -637,8 +658,11 @@ static GLuint translate_logicop(GLenum logicop) */ static void r700SetLogicOpState(GLcontext *ctx) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw); + R600_STATECHANGE(context, r700->cb_dirty); + if (RGBA_LOGICOP_ENABLED(ctx)) SETfield(r700->CB_COLOR_CONTROL.u32All, translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask); @@ -658,7 +682,10 @@ static void r700LogicOpcode(GLcontext *ctx, GLenum logicop) static void r700UpdateCulling(GLcontext * ctx) { - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw); + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw); + + R600_STATECHANGE(context, r700->su_dirty); CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit); @@ -703,7 +730,11 @@ static void r700UpdateCulling(GLcontext * ctx) static void r700UpdateLineStipple(GLcontext * ctx) { - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw); + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw); + + R600_STATECHANGE(context, r700->sc_dirty); + if (ctx->Line.StippleFlag) { SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit); @@ -778,14 +809,17 @@ static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //--------- static void r700ColorMask(GLcontext * ctx, GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------ { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw); unsigned int mask = ((r ? 1 : 0) | (g ? 2 : 0) | (b ? 4 : 0) | (a ? 8 : 0)); - if (mask != r700->CB_SHADER_MASK.u32All) + if (mask != r700->CB_SHADER_MASK.u32All) { + R600_STATECHANGE(context, r700->cb_dirty); SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask); + } } /** @@ -841,6 +875,8 @@ static void r700ShadeModel(GLcontext * ctx, GLenum mode) //-------------------- context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + R600_STATECHANGE(context, r700->spi_dirty); + /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */ switch (mode) { case GL_FLAT: @@ -862,6 +898,8 @@ static void r700PointSize(GLcontext * ctx, GLfloat size) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + R600_STATECHANGE(context, r700->su_dirty); + /* We need to clamp to user defined range here, because * the HW clamping happens only for per vertex point size. */ size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize); @@ -882,6 +920,8 @@ static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * pa context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + R600_STATECHANGE(context, r700->su_dirty); + /* format is 12.4 fixed point */ switch (pname) { case GL_POINT_SIZE_MIN: @@ -966,6 +1006,7 @@ static void r700SetStencilState(GLcontext * ctx, GLboolean state) } if (hw_stencil) { + R600_STATECHANGE(context, r700->db_dirty); if (state) SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit); else @@ -983,6 +1024,8 @@ static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face, //fixme //r300CatchStencilFallback(ctx); + R600_STATECHANGE(context, r700->db_dirty); + //front SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0], STENCILREF_shift, STENCILREF_mask); @@ -1012,6 +1055,8 @@ static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) / //fixme //r300CatchStencilFallback(ctx); + R600_STATECHANGE(context, r700->db_dirty); + // front SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0], STENCILWRITEMASK_shift, STENCILWRITEMASK_mask); @@ -1032,6 +1077,8 @@ static void r700StencilOpSeparate(GLcontext * ctx, GLenum face, //fixme //r300CatchStencilFallback(ctx); + R600_STATECHANGE(context, r700->db_dirty); + SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]), STENCILFAIL_shift, STENCILFAIL_mask); SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]), @@ -1074,7 +1121,7 @@ static void r700UpdateWindow(GLcontext * ctx, int id) //-------------------- GLfloat sz = v[MAT_SZ] * depthScale; GLfloat tz = v[MAT_TZ] * depthScale; - /* TODO : Need DMA flush as well. */ + R600_STATECHANGE(context, r700->viewport[id].dirty); r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx; r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx; @@ -1112,10 +1159,13 @@ static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //--------------- context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4)); + + R600_STATECHANGE(context, r700->su_dirty); + if (lineWidth > 0xFFFF) - lineWidth = 0xFFFF; + lineWidth = 0xFFFF; SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth, - PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask); + PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask); } static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern) @@ -1123,6 +1173,8 @@ static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + R600_STATECHANGE(context, r700->sc_dirty); + SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask); SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask); SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask); @@ -1133,6 +1185,8 @@ static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + R600_STATECHANGE(context, r700->su_dirty); + if (state) { SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit); SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit); @@ -1161,6 +1215,8 @@ static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) // factor *= 12.0; + R600_STATECHANGE(context, r700->su_dirty); + r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor; r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant; r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor; @@ -1172,6 +1228,8 @@ static void r700UpdatePolygonMode(GLcontext * ctx) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + R600_STATECHANGE(context, r700->su_dirty); + SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask); /* Only do something if a polygon mode is wanted, default is GL_FILL */ @@ -1247,6 +1305,8 @@ static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) p = (GLint) plane - (GLint) GL_CLIP_PLANE0; ip = (GLint *)ctx->Transform._ClipUserPlane[p]; + R600_STATECHANGE(context, r700->ucp[p].dirty); + r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0]; r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1]; r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2]; @@ -1260,6 +1320,9 @@ static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state) GLuint p; p = cap - GL_CLIP_PLANE0; + + R600_STATECHANGE(context, r700->cl_dirty); + if (state) { r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p); r700->ucp[p].enabled = GL_TRUE; @@ -1293,6 +1356,8 @@ void r700SetScissor(context_t *context) //--------------- y2 = rrb->dPriv->y + rrb->dPriv->h; } + R600_STATECHANGE(context, r700->sc_dirty); + /* window */ SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit); SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1, @@ -1361,6 +1426,9 @@ static void r700SetRenderTarget(context_t *context, int id) return; } + R600_STATECHANGE(context, r700->render_target[id].dirty); + R600_STATECHANGE(context, r700->cb_dirty); + /* screen/window/view */ SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask); @@ -1407,6 +1475,9 @@ static void r700SetDepthTarget(context_t *context) if (!rrb) return; + R600_STATECHANGE(context, r700->db_target_dirty); + R600_STATECHANGE(context, r700->db_dirty); + /* depth buf */ r700->DB_DEPTH_SIZE.u32All = 0; r700->DB_DEPTH_BASE.u32All = 0; @@ -1467,6 +1538,8 @@ static void r700InitSQConfig(GLcontext * ctx) int num_gs_stack_entries; int num_es_stack_entries; + R600_STATECHANGE(context, r700->sq_dirty); + // SQ ps_prio = 0; vs_prio = 1; -- cgit v1.2.3 From ba48e78b1f7cf307d505583f758c65b158f5aae0 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 20 Aug 2009 18:55:41 -0400 Subject: r600: convert to using common radeon state atoms switches more state handling to common code. We need should be more fine grained with the state atoms eventually. --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 10 +- src/mesa/drivers/dri/r600/r600_context.h | 44 +++--- src/mesa/drivers/dri/r600/r600_emit.c | 1 - src/mesa/drivers/dri/r600/r700_chip.c | 147 +++++++++++---------- src/mesa/drivers/dri/r600/r700_ioctl.c | 25 +--- src/mesa/drivers/dri/r600/r700_render.c | 86 ++---------- src/mesa/drivers/dri/r600/r700_state.c | 67 +++++----- .../drivers/dri/radeon/radeon_common_context.c | 7 - 8 files changed, 154 insertions(+), 233 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 83687bb720..38814b6d71 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -451,12 +451,10 @@ struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_cont void r600InitCmdBuf(context_t *r600) /* from rcommonInitCmdBuf */ { - radeonContextPtr rmesa = &r600->radeon; - GLuint size; - rmesa->hw.max_state_size = 4000; /* rough estimate */ + radeonContextPtr rmesa = &r600->radeon; + GLuint size; - rmesa->hw.all_dirty = GL_TRUE; - rmesa->hw.is_dirty = GL_TRUE; + r600InitAtoms(r600); /* Initialize command buffer */ size = 256 * driQueryOptioni(&rmesa->optionCache, @@ -480,7 +478,7 @@ void r600InitCmdBuf(context_t *r600) /* from rcommonInitCmdBuf */ rmesa->cmdbuf.cs = radeon_cs_create(rmesa->cmdbuf.csm, size); assert(rmesa->cmdbuf.cs != NULL); rmesa->cmdbuf.size = size; - + if (!rmesa->radeonScreen->kernel_mm) { radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]); radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, rmesa->radeonScreen->gartTextures.size); diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index 0cf2eb2daa..a9b080baa3 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -55,9 +55,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. struct r600_context; typedef struct r600_context context_t; -GLboolean r700SendPSState(context_t *context); -GLboolean r700SendVSState(context_t *context); -GLboolean r700SendSQConfig(context_t *context); +extern GLboolean r700SendPSState(context_t *context); +extern GLboolean r700SendVSState(context_t *context); +extern GLboolean r700SendFSState(context_t *context); #include "main/mm.h" @@ -112,6 +112,22 @@ enum RIGHT_SHIFT = 2, }; +struct r600_hw_state { + struct radeon_state_atom sq; + struct radeon_state_atom db; + struct radeon_state_atom db_target; + struct radeon_state_atom sc; + struct radeon_state_atom cl; + struct radeon_state_atom ucp; + struct radeon_state_atom su; + struct radeon_state_atom cb; + struct radeon_state_atom cb_target; + struct radeon_state_atom sx; + struct radeon_state_atom vgt; + struct radeon_state_atom spi; + struct radeon_state_atom vpt; +}; + /** * \brief R600 context structure. */ @@ -121,6 +137,8 @@ struct r600_context { /* ------ */ R700_CHIP_CONTEXT hw; + struct r600_hw_state atoms; + /* Vertex buffers */ GLvector4f dummy_attrib[_TNL_ATTRIB_MAX]; @@ -143,28 +161,14 @@ do { \ rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \ } while (0) -#define R600_STATECHANGE(r600, atom) \ +#define R600_STATECHANGE(r600, ATOM) \ do { \ R600_NEWPRIM(r600); \ - (atom) = GL_TRUE; \ + r600->atoms.ATOM.dirty = GL_TRUE; \ r600->radeon.hw.is_dirty = GL_TRUE; \ } while(0) -extern GLboolean r700SendSPIState(context_t *context); -extern GLboolean r700SendVGTState(context_t *context); -extern GLboolean r700SendSXState(context_t *context); -extern GLboolean r700SendDBState(context_t *context); -extern GLboolean r700SendCBState(context_t *context); -extern GLboolean r700SendSUState(context_t *context); -extern GLboolean r700SendCLState(context_t *context); -extern GLboolean r700SendSCState(context_t *context); -extern GLboolean r700SendViewportState(context_t *context, int id); -extern GLboolean r700SendRenderTargetState(context_t *context, int id); extern GLboolean r700SendTextureState(context_t *context); -extern GLboolean r700SendDepthTargetState(context_t *context); -extern GLboolean r700SendUCPState(context_t *context); -extern GLboolean r700SendFSState(context_t *context); -extern void r700EmitState(GLcontext * ctx); extern GLboolean r700SyncSurf(context_t *context, struct radeon_bo *pbo, @@ -180,6 +184,8 @@ extern void r700SetupVTXConstants(GLcontext * ctx, unsigned int stride, unsigned int Count); /* number of vectors in stream */ +extern void r600InitAtoms(context_t *context); + #define RADEON_D_CAPTURE 0 #define RADEON_D_PLAYBACK 1 #define RADEON_D_PLAYBACK_RAW 2 diff --git a/src/mesa/drivers/dri/r600/r600_emit.c b/src/mesa/drivers/dri/r600/r600_emit.c index b695ed9583..b0c7294682 100644 --- a/src/mesa/drivers/dri/r600/r600_emit.c +++ b/src/mesa/drivers/dri/r600/r600_emit.c @@ -49,7 +49,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. void r600EmitCacheFlush(context_t *rmesa) { - BATCH_LOCALS(&rmesa->radeon); } GLboolean r600EmitShader(GLcontext * ctx, diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 7f46b0c468..2d68f021df 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -27,6 +27,7 @@ #include "main/imports.h" #include "main/glheader.h" +#include "main/simple_list.h" #include "r600_context.h" #include "r600_cmdbuf.h" @@ -220,8 +221,9 @@ int r700SetupStreams(GLcontext * ctx) return R600_FALLBACK_NONE; } -GLboolean r700SendDepthTargetState(context_t *context) +static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_renderbuffer *rrb; BATCH_LOCALS(&context->radeon); @@ -229,7 +231,7 @@ GLboolean r700SendDepthTargetState(context_t *context) rrb = radeon_get_depthbuffer(&context->radeon); if (!rrb || !rrb->bo) { fprintf(stderr, "no rrb\n"); - return GL_FALSE; + return; } BEGIN_BATCH_NO_AUTOSTATE(8 + 2); @@ -255,31 +257,27 @@ GLboolean r700SendDepthTargetState(context_t *context) COMMIT_BATCH(); - r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM, - DB_ACTION_ENA_bit | DB_DEST_BASE_ENA_bit); - - r700->db_target_dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendRenderTargetState(context_t *context, int id) +static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_renderbuffer *rrb; BATCH_LOCALS(&context->radeon); + int id = 0; rrb = radeon_get_colorbuffer(&context->radeon); if (!rrb || !rrb->bo) { fprintf(stderr, "no rrb\n"); - return GL_FALSE; + return; } if (id > R700_MAX_RENDER_TARGETS) - return GL_FALSE; + return; if (!r700->render_target[id].enabled) - return GL_FALSE; + return; BEGIN_BATCH_NO_AUTOSTATE(3 + 2); R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1); @@ -309,12 +307,6 @@ GLboolean r700SendRenderTargetState(context_t *context, int id) COMMIT_BATCH(); - r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM, - CB_ACTION_ENA_bit | (1 << (id + 6))); - - r700->render_target[id].dirty = GL_FALSE; - - return GL_TRUE; } GLboolean r700SendPSState(context_t *context) @@ -429,16 +421,18 @@ GLboolean r700SendFSState(context_t *context) return GL_TRUE; } -GLboolean r700SendViewportState(context_t *context, int id) +static void r700SendViewportState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); + int id = 0; if (id > R700_MAX_VIEWPORTS) - return GL_FALSE; + return; if (!r700->viewport[id].enabled) - return GL_FALSE; + return; BEGIN_BATCH_NO_AUTOSTATE(16); R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL + (8 * id), 2); @@ -458,13 +452,11 @@ GLboolean r700SendViewportState(context_t *context, int id) COMMIT_BATCH(); - r700->viewport[id].dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendSQConfig(context_t *context) +static void r700SendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); @@ -496,20 +488,17 @@ GLboolean r700SendSQConfig(context_t *context) END_BATCH(); COMMIT_BATCH(); - - r700->sq_dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendUCPState(context_t *context) +static void r700SendUCPState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); int i; for (i = 0; i < R700_MAX_UCP; i++) { - if (r700->ucp[i].enabled && r700->ucp[i].dirty) { + if (r700->ucp[i].enabled) { BEGIN_BATCH_NO_AUTOSTATE(6); R600_OUT_BATCH_REGSEQ(PA_CL_UCP_0_X + (16 * i), 4); R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_X.u32All); @@ -518,15 +507,13 @@ GLboolean r700SendUCPState(context_t *context) R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_W.u32All); END_BATCH(); COMMIT_BATCH(); - r700->ucp[i].dirty = GL_FALSE; } } - - return GL_TRUE; } -GLboolean r700SendSPIState(context_t *context) +static void r700SendSPIState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); unsigned int ui; @@ -596,14 +583,11 @@ GLboolean r700SendSPIState(context_t *context) END_BATCH(); COMMIT_BATCH(); - - r700->spi_dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendVGTState(context_t *context) +static void r700SendVGTState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); @@ -644,14 +628,11 @@ GLboolean r700SendVGTState(context_t *context) END_BATCH(); COMMIT_BATCH(); - - r700->vgt_dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendSXState(context_t *context) +static void r700SendSXState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); @@ -661,14 +642,11 @@ GLboolean r700SendSXState(context_t *context) R600_OUT_BATCH_REGVAL(SX_ALPHA_REF, r700->SX_ALPHA_REF.u32All); END_BATCH(); COMMIT_BATCH(); - - r700->sx_dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendDBState(context_t *context) +static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); @@ -695,14 +673,11 @@ GLboolean r700SendDBState(context_t *context) END_BATCH(); COMMIT_BATCH(); - - r700->db_dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendCBState(context_t *context) +static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); unsigned int ui; @@ -757,13 +732,11 @@ GLboolean r700SendCBState(context_t *context) COMMIT_BATCH(); - r700->cb_dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendSUState(context_t *context) +static void r700SendSUState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); @@ -789,13 +762,11 @@ GLboolean r700SendSUState(context_t *context) END_BATCH(); COMMIT_BATCH(); - r700->su_dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendCLState(context_t *context) +static void r700SendCLState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); @@ -813,15 +784,12 @@ GLboolean r700SendCLState(context_t *context) END_BATCH(); COMMIT_BATCH(); - - r700->cl_dirty = GL_FALSE; - - return GL_TRUE; } // XXX need to split this up -GLboolean r700SendSCState(context_t *context) +static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); @@ -860,8 +828,47 @@ GLboolean r700SendSCState(context_t *context) END_BATCH(); COMMIT_BATCH(); +} - r700->sc_dirty = GL_FALSE; +static int check_always(GLcontext *ctx, struct radeon_state_atom *atom) +{ + return atom->cmd_size; +} - return GL_TRUE; +#define ALLOC_STATE( ATOM, SZ, EMIT ) \ +do { \ + context->atoms.ATOM.cmd_size = (SZ); \ + context->atoms.ATOM.cmd = NULL; \ + context->atoms.ATOM.name = #ATOM; \ + context->atoms.ATOM.idx = 0; \ + context->atoms.ATOM.check = check_always; \ + context->atoms.ATOM.dirty = GL_FALSE; \ + context->atoms.ATOM.emit = (EMIT); \ + context->radeon.hw.max_state_size += (SZ); \ + insert_at_tail(&context->radeon.hw.atomlist, &context->atoms.ATOM); \ +} while (0) + +void r600InitAtoms(context_t *context) +{ + + /* Setup the atom linked list */ + make_empty_list(&context->radeon.hw.atomlist); + context->radeon.hw.atomlist.name = "atom-list"; + + ALLOC_STATE(sq, 34, r700SendSQConfig); + ALLOC_STATE(db, 27, r700SendDBState); + ALLOC_STATE(db_target, 19, r700SendDepthTargetState); + ALLOC_STATE(sc, 47, r700SendSCState); + ALLOC_STATE(cl, 18, r700SendCLState); + ALLOC_STATE(ucp, 36, r700SendUCPState); + ALLOC_STATE(su, 19, r700SendSUState); + ALLOC_STATE(cb, 39, r700SendCBState); + ALLOC_STATE(cb_target, 32, r700SendRenderTargetState); + ALLOC_STATE(sx, 9, r700SendSXState); + ALLOC_STATE(vgt, 41, r700SendVGTState); + ALLOC_STATE(spi, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState); + ALLOC_STATE(vpt, 16, r700SendViewportState); + + context->radeon.hw.is_dirty = GL_TRUE; + context->radeon.hw.all_dirty = GL_TRUE; } diff --git a/src/mesa/drivers/dri/r600/r700_ioctl.c b/src/mesa/drivers/dri/r600/r700_ioctl.c index e0e506d665..72a8978976 100644 --- a/src/mesa/drivers/dri/r600/r700_ioctl.c +++ b/src/mesa/drivers/dri/r600/r700_ioctl.c @@ -41,33 +41,10 @@ #include "r700_ioctl.h" #include "r700_clear.h" -static void r700Flush(GLcontext *ctx) -{ - radeonContextPtr radeon = RADEON_CONTEXT(ctx); - - if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s %d\n", __FUNCTION__, radeon->cmdbuf.cs->cdw); - - /* okay if we have no cmds in the buffer && - we have no DMA flush && - we have no DMA buffer allocated. - then no point flushing anything at all. - */ - if (!radeon->dma.flush && !radeon->cmdbuf.cs->cdw && is_empty_list(&radeon->dma.reserved)) - return; - - if (radeon->dma.flush) - radeon->dma.flush( ctx ); - - r700EmitState(ctx); - - if (radeon->cmdbuf.cs->cdw) - rcommonFlushCmdBuf(radeon, __FUNCTION__); -} void r700InitIoctlFuncs(struct dd_function_table *functions) { functions->Clear = r700Clear; functions->Finish = radeonFinish; - functions->Flush = r700Flush; + functions->Flush = radeonFlush; } diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 52f8f90dad..f0cd357c76 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -332,96 +332,28 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim } -static void r700EmitAtoms(GLcontext * ctx, GLboolean dirty) -{ - context_t *context = R700_CONTEXT(ctx); - radeonContextPtr radeon = &context->radeon; - R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); - - if ((r700->sq_dirty || radeon->hw.all_dirty) == dirty) - r700SendSQConfig(context); - r700SendUCPState(context); - if ((r700->sc_dirty || radeon->hw.all_dirty) == dirty) - r700SendSCState(context); - if ((r700->su_dirty || radeon->hw.all_dirty) == dirty) - r700SendSUState(context); - if ((r700->cl_dirty || radeon->hw.all_dirty) == dirty) - r700SendCLState(context); - if ((r700->cb_dirty || radeon->hw.all_dirty) == dirty) - r700SendCBState(context); - if ((r700->db_dirty || radeon->hw.all_dirty) == dirty) - r700SendDBState(context); - if ((r700->sx_dirty || radeon->hw.all_dirty) == dirty) - r700SendSXState(context); - if ((r700->vgt_dirty || radeon->hw.all_dirty) == dirty) - r700SendVGTState(context); - if ((r700->spi_dirty || radeon->hw.all_dirty) == dirty) - r700SendSPIState(context); - if ((r700->viewport[0].dirty || radeon->hw.all_dirty) == dirty) - r700SendViewportState(context, 0); - if ((r700->render_target[0].dirty || radeon->hw.all_dirty) == dirty) - r700SendRenderTargetState(context, 0); - if ((r700->db_target_dirty || radeon->hw.all_dirty) == dirty) - r700SendDepthTargetState(context); - -} - -void r700EmitState(GLcontext * ctx) -{ - context_t *context = R700_CONTEXT(ctx); - radeonContextPtr radeon = &context->radeon; - - if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS)) - fprintf(stderr, "%s\n", __FUNCTION__); - - if (radeon->vtbl.pre_emit_state) - radeon->vtbl.pre_emit_state(radeon); - - if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw.all_dirty) - return; - - rcommonEnsureCmdBufSpace(&context->radeon, - 652, __FUNCTION__); - - if (!radeon->cmdbuf.cs->cdw) { - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Begin reemit state\n"); - - r700EmitAtoms(ctx, GL_FALSE); - } - - if (RADEON_DEBUG & DEBUG_STATE) - fprintf(stderr, "Begin dirty state\n"); - - r700EmitAtoms(ctx, GL_TRUE); - radeon->hw.is_dirty = GL_FALSE; - radeon->hw.all_dirty = GL_FALSE; - -} - static GLboolean r700RunRender(GLcontext * ctx, struct tnl_pipeline_stage *stage) { context_t *context = R700_CONTEXT(ctx); radeonContextPtr radeon = &context->radeon; - unsigned int i, ind_count = 0; + unsigned int i, ind_count = 0, id = 0; TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; + struct radeon_renderbuffer *rrb; for (i = 0; i < vb->PrimitiveCount; i++) ind_count += vb->Primitive[i].count + 10; /* just an estimate, need to properly calculate this */ rcommonEnsureCmdBufSpace(&context->radeon, - radeon->hw.max_state_size + ind_count, __FUNCTION__); + radeon->hw.max_state_size + ind_count + 1000, __FUNCTION__); r700Start3D(context); - r700UpdateShaders(ctx); r700SetScissor(context); r700SetupShaders(ctx); - - r700EmitState(ctx); + radeonEmitState(radeon); /* richard test code */ for (i = 0; i < vb->PrimitiveCount; i++) { @@ -434,6 +366,16 @@ static GLboolean r700RunRender(GLcontext * ctx, /* Flush render op cached for last several quads. */ r700WaitForIdleClean(context); + rrb = radeon_get_colorbuffer(&context->radeon); + if (!rrb || !rrb->bo) + r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM, + CB_ACTION_ENA_bit | (1 << (id + 6))); + + rrb = radeon_get_depthbuffer(&context->radeon); + if (!rrb || !rrb->bo) + r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM, + DB_ACTION_ENA_bit | DB_DEST_BASE_ENA_bit); + radeonReleaseArrays(ctx, ~0); return GL_FALSE; diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index ada394ec61..6b44cc0ceb 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -153,7 +153,7 @@ void r700UpdateViewportOffset(GLcontext * ctx) //------------------ /* Note: this should also modify whatever data the context reset * code uses... */ - R600_STATECHANGE(context, r700->viewport[id].dirty); + R600_STATECHANGE(context, vpt); r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx; r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty; } @@ -170,8 +170,8 @@ void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //--------------------- context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - R600_STATECHANGE(context, r700->render_target[0].dirty); - R600_STATECHANGE(context, r700->db_target_dirty); + R600_STATECHANGE(context, cb_target); + R600_STATECHANGE(context, db_target); r700SetRenderTarget(context, 0); r700SetDepthTarget(context); @@ -244,8 +244,8 @@ static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //----------- r700UpdateStateParameters(ctx, new_state); - R600_STATECHANGE(context, r700->cl_dirty); - R600_STATECHANGE(context, r700->spi_dirty); + R600_STATECHANGE(context, cl); + R600_STATECHANGE(context, spi); if(GL_TRUE == r700->bEnablePerspective) { @@ -278,7 +278,7 @@ static void r700SetDepthState(GLcontext * ctx) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - R600_STATECHANGE(context, r700->db_dirty); + R600_STATECHANGE(context, db); if (ctx->Depth.Test) { @@ -346,7 +346,7 @@ static void r700SetAlphaState(GLcontext * ctx) uint32_t alpha_func = REF_ALWAYS; GLboolean really_enabled = ctx->Color.AlphaEnabled; - R600_STATECHANGE(context, r700->sx_dirty); + R600_STATECHANGE(context, sx); switch (ctx->Color.AlphaFunc) { case GL_NEVER: @@ -400,7 +400,7 @@ static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //------------- context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - R600_STATECHANGE(context, r700->cb_dirty); + R600_STATECHANGE(context, cb); r700->CB_BLEND_RED.f32All = cf[0]; r700->CB_BLEND_GREEN.f32All = cf[1]; @@ -470,7 +470,7 @@ static void r700SetBlendState(GLcontext * ctx) int id = 0; uint32_t blend_reg = 0, eqn, eqnA; - R600_STATECHANGE(context, r700->cb_dirty); + R600_STATECHANGE(context, cb); if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) { SETfield(blend_reg, @@ -661,7 +661,7 @@ static void r700SetLogicOpState(GLcontext *ctx) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw); - R600_STATECHANGE(context, r700->cb_dirty); + R600_STATECHANGE(context, cb); if (RGBA_LOGICOP_ENABLED(ctx)) SETfield(r700->CB_COLOR_CONTROL.u32All, @@ -685,7 +685,7 @@ static void r700UpdateCulling(GLcontext * ctx) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw); - R600_STATECHANGE(context, r700->su_dirty); + R600_STATECHANGE(context, su); CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit); @@ -733,7 +733,7 @@ static void r700UpdateLineStipple(GLcontext * ctx) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw); - R600_STATECHANGE(context, r700->sc_dirty); + R600_STATECHANGE(context, sc); if (ctx->Line.StippleFlag) { @@ -817,7 +817,7 @@ static void r700ColorMask(GLcontext * ctx, (a ? 8 : 0)); if (mask != r700->CB_SHADER_MASK.u32All) { - R600_STATECHANGE(context, r700->cb_dirty); + R600_STATECHANGE(context, cb); SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask); } } @@ -875,7 +875,7 @@ static void r700ShadeModel(GLcontext * ctx, GLenum mode) //-------------------- context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - R600_STATECHANGE(context, r700->spi_dirty); + R600_STATECHANGE(context, spi); /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */ switch (mode) { @@ -898,7 +898,7 @@ static void r700PointSize(GLcontext * ctx, GLfloat size) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - R600_STATECHANGE(context, r700->su_dirty); + R600_STATECHANGE(context, su); /* We need to clamp to user defined range here, because * the HW clamping happens only for per vertex point size. */ @@ -920,7 +920,7 @@ static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * pa context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - R600_STATECHANGE(context, r700->su_dirty); + R600_STATECHANGE(context, su); /* format is 12.4 fixed point */ switch (pname) { @@ -1006,7 +1006,7 @@ static void r700SetStencilState(GLcontext * ctx, GLboolean state) } if (hw_stencil) { - R600_STATECHANGE(context, r700->db_dirty); + R600_STATECHANGE(context, db); if (state) SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit); else @@ -1024,7 +1024,7 @@ static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face, //fixme //r300CatchStencilFallback(ctx); - R600_STATECHANGE(context, r700->db_dirty); + R600_STATECHANGE(context, db); //front SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0], @@ -1055,7 +1055,7 @@ static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) / //fixme //r300CatchStencilFallback(ctx); - R600_STATECHANGE(context, r700->db_dirty); + R600_STATECHANGE(context, db); // front SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0], @@ -1077,7 +1077,7 @@ static void r700StencilOpSeparate(GLcontext * ctx, GLenum face, //fixme //r300CatchStencilFallback(ctx); - R600_STATECHANGE(context, r700->db_dirty); + R600_STATECHANGE(context, db); SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]), STENCILFAIL_shift, STENCILFAIL_mask); @@ -1121,7 +1121,7 @@ static void r700UpdateWindow(GLcontext * ctx, int id) //-------------------- GLfloat sz = v[MAT_SZ] * depthScale; GLfloat tz = v[MAT_TZ] * depthScale; - R600_STATECHANGE(context, r700->viewport[id].dirty); + R600_STATECHANGE(context, vpt); r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx; r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx; @@ -1160,7 +1160,7 @@ static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //--------------- R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4)); - R600_STATECHANGE(context, r700->su_dirty); + R600_STATECHANGE(context, su); if (lineWidth > 0xFFFF) lineWidth = 0xFFFF; @@ -1173,7 +1173,7 @@ static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - R600_STATECHANGE(context, r700->sc_dirty); + R600_STATECHANGE(context, sc); SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask); SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask); @@ -1185,7 +1185,7 @@ static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - R600_STATECHANGE(context, r700->su_dirty); + R600_STATECHANGE(context, su); if (state) { SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit); @@ -1215,7 +1215,7 @@ static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) // factor *= 12.0; - R600_STATECHANGE(context, r700->su_dirty); + R600_STATECHANGE(context, su); r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor; r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant; @@ -1228,7 +1228,7 @@ static void r700UpdatePolygonMode(GLcontext * ctx) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - R600_STATECHANGE(context, r700->su_dirty); + R600_STATECHANGE(context, su); SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask); @@ -1305,7 +1305,7 @@ static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) p = (GLint) plane - (GLint) GL_CLIP_PLANE0; ip = (GLint *)ctx->Transform._ClipUserPlane[p]; - R600_STATECHANGE(context, r700->ucp[p].dirty); + R600_STATECHANGE(context, ucp); r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0]; r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1]; @@ -1321,7 +1321,7 @@ static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state) p = cap - GL_CLIP_PLANE0; - R600_STATECHANGE(context, r700->cl_dirty); + R600_STATECHANGE(context, cl); if (state) { r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p); @@ -1356,7 +1356,7 @@ void r700SetScissor(context_t *context) //--------------- y2 = rrb->dPriv->y + rrb->dPriv->h; } - R600_STATECHANGE(context, r700->sc_dirty); + R600_STATECHANGE(context, sc); /* window */ SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit); @@ -1426,8 +1426,8 @@ static void r700SetRenderTarget(context_t *context, int id) return; } - R600_STATECHANGE(context, r700->render_target[id].dirty); - R600_STATECHANGE(context, r700->cb_dirty); + R600_STATECHANGE(context, cb_target); + R600_STATECHANGE(context, cb); /* screen/window/view */ SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask); @@ -1475,8 +1475,7 @@ static void r700SetDepthTarget(context_t *context) if (!rrb) return; - R600_STATECHANGE(context, r700->db_target_dirty); - R600_STATECHANGE(context, r700->db_dirty); + R600_STATECHANGE(context, db_target); /* depth buf */ r700->DB_DEPTH_SIZE.u32All = 0; @@ -1538,7 +1537,7 @@ static void r700InitSQConfig(GLcontext * ctx) int num_gs_stack_entries; int num_es_stack_entries; - R600_STATECHANGE(context, r700->sq_dirty); + R600_STATECHANGE(context, sq); // SQ ps_prio = 0; diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index 13711963e2..ad4584a2bd 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -298,10 +298,6 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv ) GET_CURRENT_CONTEXT(ctx); radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL; -#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) /* +r6/r7 */ - __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; - radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); -#endif if (radeon == current) { radeon_firevertices(radeon); @@ -338,9 +334,6 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv ) rcommonDestroyCmdBuf(radeon); -#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) /* +r6/r7 */ - if (!IS_R600_CLASS(screen)) -#endif radeon_destroy_atom_list(radeon); if (radeon->state.scissor.pClipRects) { -- cgit v1.2.3 From 180c304943537210b2f6459ea21e9bff85f9827e Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Sat, 22 Aug 2009 15:03:41 -0400 Subject: r600: move full state to radeon state atoms --- src/mesa/drivers/dri/r600/r600_context.c | 2 +- src/mesa/drivers/dri/r600/r600_context.h | 26 ++-- src/mesa/drivers/dri/r600/r600_texstate.c | 2 + src/mesa/drivers/dri/r600/r700_chip.c | 242 +++++++++++++++++++++--------- src/mesa/drivers/dri/r600/r700_chip.h | 5 + src/mesa/drivers/dri/r600/r700_fragprog.c | 74 ++++----- src/mesa/drivers/dri/r600/r700_render.c | 45 +----- src/mesa/drivers/dri/r600/r700_state.c | 2 - src/mesa/drivers/dri/r600/r700_vertprog.c | 56 ++++--- 9 files changed, 262 insertions(+), 192 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 4489064c0d..6a066f3510 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -185,7 +185,7 @@ static void r600_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmes static void r600_vtbl_pre_emit_atoms(radeonContextPtr radeon) { - /* to be enabled */ + r700Start3D((context_t *)radeon); } static void r600_fallback(GLcontext *ctx, GLuint bit, GLboolean mode) diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index a9b080baa3..48be89b638 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -55,10 +55,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. struct r600_context; typedef struct r600_context context_t; -extern GLboolean r700SendPSState(context_t *context); -extern GLboolean r700SendVSState(context_t *context); -extern GLboolean r700SendFSState(context_t *context); - #include "main/mm.h" /************ DMA BUFFERS **************/ @@ -126,6 +122,16 @@ struct r600_hw_state { struct radeon_state_atom vgt; struct radeon_state_atom spi; struct radeon_state_atom vpt; + + struct radeon_state_atom fs; + struct radeon_state_atom vs; + struct radeon_state_atom ps; + + struct radeon_state_atom vs_consts; + struct radeon_state_atom ps_consts; + + struct radeon_state_atom vtx; + struct radeon_state_atom tx; }; /** @@ -168,22 +174,14 @@ do { \ r600->radeon.hw.is_dirty = GL_TRUE; \ } while(0) -extern GLboolean r700SendTextureState(context_t *context); - extern GLboolean r700SyncSurf(context_t *context, struct radeon_bo *pbo, uint32_t read_domain, uint32_t write_domain, uint32_t sync_type); -extern int r700SetupStreams(GLcontext * ctx); -extern void r700SetupVTXConstants(GLcontext * ctx, - unsigned int nStreamID, - void * pAos, - unsigned int size, /* number of elements in vector */ - unsigned int stride, - unsigned int Count); /* number of vectors in stream */ - +extern void r700SetupStreams(GLcontext * ctx); +extern void r700Start3D(context_t *context); extern void r600InitAtoms(context_t *context); #define RADEON_D_CAPTURE 0 diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 1057d7d8bb..7486d73760 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -60,6 +60,8 @@ void r600UpdateTextureState(GLcontext * ctx) struct radeon_tex_obj *t; GLuint unit; + R600_STATECHANGE(context, tx); + for (unit = 0; unit < R700_MAX_TEXTURE_UNITS; unit++) { texUnit = &ctx->Texture.Unit[unit]; t = radeon_tex_obj(ctx->Texture.Unit[unit]._Current); diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 550fb73d53..b7c2be16ff 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -41,11 +41,12 @@ #include "radeon_mipmap_tree.h" -GLboolean r700SendTextureState(context_t *context) +static void r700SendTextureState(GLcontext *ctx, struct radeon_state_atom *atom) { - unsigned int i; + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); struct radeon_bo *bo = NULL; + unsigned int i; BATCH_LOCALS(&context->radeon); for (i=0; iradeon); - - struct r700_vertex_program *vpc + struct r700_vertex_program *vpc = (struct r700_vertex_program *)ctx->VertexProgram._Current; - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *vb = &tnl->vb; + struct vertex_buffer *vb = &tnl->vb; + unsigned int i, j = 0; + + R600_STATECHANGE(context, vtx); + + for(i=0; imesa_program.Base.InputsRead & (1 << i)) { + rcommon_emit_vector(ctx, + &context->radeon.tcl.aos[j], + vb->AttribPtr[i]->data, + vb->AttribPtr[i]->size, + vb->AttribPtr[i]->stride, + vb->Count); + j++; + } + } + context->radeon.tcl.aos_count = j; +} - unsigned int unBit; +static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + struct r700_vertex_program *vpc + = (struct r700_vertex_program *)ctx->VertexProgram._Current; unsigned int i, j = 0; + BATCH_LOCALS(&context->radeon); BEGIN_BATCH_NO_AUTOSTATE(6); R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); @@ -195,31 +214,18 @@ int r700SetupStreams(GLcontext * ctx) END_BATCH(); COMMIT_BATCH(); - for(i=0; imesa_program.Base.InputsRead & unBit) - { - rcommon_emit_vector(ctx, - &context->radeon.tcl.aos[j], - vb->AttribPtr[i]->data, - vb->AttribPtr[i]->size, - vb->AttribPtr[i]->stride, - vb->Count); - - /* currently aos are packed */ - r700SetupVTXConstants(ctx, - i, - (void*)(&context->radeon.tcl.aos[j]), - (unsigned int)context->radeon.tcl.aos[j].components, - (unsigned int)context->radeon.tcl.aos[j].stride * 4, - (unsigned int)context->radeon.tcl.aos[j].count); - j++; - } - } - context->radeon.tcl.aos_count = j; - - return R600_FALLBACK_NONE; + for(i=0; imesa_program.Base.InputsRead & (1 << i)) { + /* currently aos are packed */ + r700SetupVTXConstants(ctx, + i, + (void*)(&context->radeon.tcl.aos[j]), + (unsigned int)context->radeon.tcl.aos[j].components, + (unsigned int)context->radeon.tcl.aos[j].stride * 4, + (unsigned int)context->radeon.tcl.aos[j].count); + j++; + } + } } static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *atom) @@ -310,8 +316,9 @@ static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom * } -GLboolean r700SendPSState(context_t *context) +static void r700SendPSState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; BATCH_LOCALS(&context->radeon); @@ -319,7 +326,7 @@ GLboolean r700SendPSState(context_t *context) pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context)); if (!pbo) - return GL_FALSE; + return; r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); @@ -340,13 +347,11 @@ GLboolean r700SendPSState(context_t *context) COMMIT_BATCH(); - r700->ps.dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendVSState(context_t *context) +static void r700SendVSState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; BATCH_LOCALS(&context->radeon); @@ -354,7 +359,7 @@ GLboolean r700SendVSState(context_t *context) pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); if (!pbo) - return GL_FALSE; + return; r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); @@ -373,14 +378,11 @@ GLboolean r700SendVSState(context_t *context) END_BATCH(); COMMIT_BATCH(); - - r700->vs.dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendFSState(context_t *context) +static void r700SendFSState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; BATCH_LOCALS(&context->radeon); @@ -397,7 +399,7 @@ GLboolean r700SendFSState(context_t *context) /* XXX */ if (!pbo) - return GL_FALSE; + return; r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); @@ -417,9 +419,6 @@ GLboolean r700SendFSState(context_t *context) COMMIT_BATCH(); - r700->fs.dirty = GL_FALSE; - - return GL_TRUE; } static void r700SendViewportState(GLcontext *ctx, struct radeon_state_atom *atom) @@ -831,18 +830,103 @@ static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); } +static void r700SendPSConsts(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + int i; + BATCH_LOCALS(&context->radeon); + + if (r700->ps.num_consts == 0) + return; + + BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->ps.num_consts * 4)); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->ps.num_consts * 4))); + /* assembler map const from very beginning. */ + R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4); + for (i = 0; i < r700->ps.num_consts; i++) { + R600_OUT_BATCH(r700->ps.consts[i][0].u32All); + R600_OUT_BATCH(r700->ps.consts[i][1].u32All); + R600_OUT_BATCH(r700->ps.consts[i][2].u32All); + R600_OUT_BATCH(r700->ps.consts[i][3].u32All); + } + END_BATCH(); + COMMIT_BATCH(); +} + +static void r700SendVSConsts(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + int i; + BATCH_LOCALS(&context->radeon); + + if (r700->vs.num_consts == 0) + return; + + BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->vs.num_consts * 4)); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->vs.num_consts * 4))); + /* assembler map const from very beginning. */ + R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4); + for (i = 0; i < r700->vs.num_consts; i++) { + R600_OUT_BATCH(r700->vs.consts[i][0].u32All); + R600_OUT_BATCH(r700->vs.consts[i][1].u32All); + R600_OUT_BATCH(r700->vs.consts[i][2].u32All); + R600_OUT_BATCH(r700->vs.consts[i][3].u32All); + } + END_BATCH(); + COMMIT_BATCH(); +} + static int check_always(GLcontext *ctx, struct radeon_state_atom *atom) { return atom->cmd_size; } -#define ALLOC_STATE( ATOM, SZ, EMIT ) \ +static int check_vtx(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + + return context->radeon.tcl.aos_count * 18; +} + +static int check_tx(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + unsigned int i, count = 0; + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + + for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) { + radeonTexObj *t = r700->textures[i]; + if (t) + count++; + } + return count * 31; +} + +static int check_ps_consts(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + + return 2 + (r700->ps.num_consts * 4); +} + +static int check_vs_consts(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + + return 2 + (r700->vs.num_consts * 4); +} + +#define ALLOC_STATE( ATOM, CHK, SZ, EMIT ) \ do { \ context->atoms.ATOM.cmd_size = (SZ); \ context->atoms.ATOM.cmd = NULL; \ context->atoms.ATOM.name = #ATOM; \ context->atoms.ATOM.idx = 0; \ - context->atoms.ATOM.check = check_always; \ + context->atoms.ATOM.check = check_##CHK; \ context->atoms.ATOM.dirty = GL_FALSE; \ context->atoms.ATOM.emit = (EMIT); \ context->radeon.hw.max_state_size += (SZ); \ @@ -851,26 +935,36 @@ do { \ void r600InitAtoms(context_t *context) { - /* FIXME: rough estimate for "large" const and shader state */ - context->radeon.hw.max_state_size = 7500; + context->radeon.hw.max_state_size = 10 + 5 + 14; /* start 3d, idle, cb/db flush */ /* Setup the atom linked list */ make_empty_list(&context->radeon.hw.atomlist); context->radeon.hw.atomlist.name = "atom-list"; - ALLOC_STATE(sq, 34, r700SendSQConfig); - ALLOC_STATE(db, 27, r700SendDBState); - ALLOC_STATE(db_target, 19, r700SendDepthTargetState); - ALLOC_STATE(sc, 47, r700SendSCState); - ALLOC_STATE(cl, 18, r700SendCLState); - ALLOC_STATE(ucp, 36, r700SendUCPState); - ALLOC_STATE(su, 19, r700SendSUState); - ALLOC_STATE(cb, 39, r700SendCBState); - ALLOC_STATE(cb_target, 32, r700SendRenderTargetState); - ALLOC_STATE(sx, 9, r700SendSXState); - ALLOC_STATE(vgt, 41, r700SendVGTState); - ALLOC_STATE(spi, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState); - ALLOC_STATE(vpt, 16, r700SendViewportState); + ALLOC_STATE(sq, always, 34, r700SendSQConfig); + + ALLOC_STATE(db, always, 27, r700SendDBState); + ALLOC_STATE(db_target, always, 19, r700SendDepthTargetState); + ALLOC_STATE(sc, always, 47, r700SendSCState); + ALLOC_STATE(cl, always, 18, r700SendCLState); + ALLOC_STATE(ucp, always, 36, r700SendUCPState); + ALLOC_STATE(su, always, 19, r700SendSUState); + ALLOC_STATE(cb, always, 39, r700SendCBState); + ALLOC_STATE(cb_target, always, 32, r700SendRenderTargetState); + ALLOC_STATE(sx, always, 9, r700SendSXState); + ALLOC_STATE(vgt, always, 41, r700SendVGTState); + ALLOC_STATE(spi, always, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState); + ALLOC_STATE(vpt, always, 16, r700SendViewportState); + + ALLOC_STATE(fs, always, 18, r700SendFSState); + ALLOC_STATE(vs, always, 18, r700SendVSState); + ALLOC_STATE(ps, always, 21, r700SendPSState); + + ALLOC_STATE(vs_consts, vs_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendVSConsts); + ALLOC_STATE(ps_consts, ps_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendPSConsts); + + ALLOC_STATE(vtx, vtx, (VERT_ATTRIB_MAX * 18), r700SendVTXState); + ALLOC_STATE(tx, tx, (R700_TEXTURE_NUMBERUNITS * 31), r700SendTextureState); context->radeon.hw.is_dirty = GL_TRUE; context->radeon.hw.all_dirty = GL_TRUE; diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h index c0ec4b0dd5..ae249e15fd 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.h +++ b/src/mesa/drivers/dri/r600/r700_chip.h @@ -46,6 +46,7 @@ #define R700_MAX_VIEWPORTS 16 #define R700_MAX_SHADER_EXPORTS 32 #define R700_MAX_UCP 6 +#define R700_MAX_DX9_CONSTS 256 /* Enum not show in r600_*.h */ @@ -224,6 +225,8 @@ typedef struct _PS_STATE_STRUCT union UINT_FLOAT SQ_PGM_EXPORTS_PS ; /* 0xA215 */ union UINT_FLOAT SQ_PGM_CF_OFFSET_PS ; /* 0xA233 */ GLboolean dirty; + int num_consts; + union UINT_FLOAT consts[R700_MAX_DX9_CONSTS][4]; } PS_STATE_STRUCT; typedef struct _VS_STATE_STRUCT @@ -232,6 +235,8 @@ typedef struct _VS_STATE_STRUCT union UINT_FLOAT SQ_PGM_RESOURCES_VS ; /* 0xA21A */ union UINT_FLOAT SQ_PGM_CF_OFFSET_VS ; /* 0xA234 */ GLboolean dirty; + int num_consts; + union UINT_FLOAT consts[R700_MAX_DX9_CONSTS][4]; } VS_STATE_STRUCT; typedef struct _GS_STATE_STRUCT diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index 394482594e..098b420dfc 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -270,7 +270,6 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - BATCH_LOCALS(&context->radeon); struct r700_fragment_program *fp = (struct r700_fragment_program *) (ctx->FragmentProgram._Current); r700_AssemblerBase *pAsm = &(fp->r700AsmCode); @@ -280,6 +279,7 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) unsigned int ui, i; unsigned int unNumOfReg; unsigned int unBit; + GLuint exportCount; if(GL_FALSE == fp->loaded) { @@ -305,10 +305,15 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) (context->chipobj.MemUse)(context, fp->shadercode.buf->id); */ - R600_STATECHANGE(context, spi); + R600_STATECHANGE(context, ps); + + r700->ps.SQ_PGM_RESOURCES_PS.u32All = 0; + SETbit(r700->ps.SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); r700->ps.SQ_PGM_START_PS.u32All = 0; /* set from buffer obj */ + R600_STATECHANGE(context, spi); + unNumOfReg = fp->r700Shader.nRegs + 1; ui = (r700->SPI_PS_IN_CONTROL_0.u32All & NUM_INTERP_mask) / (1 << NUM_INTERP_shift); @@ -325,8 +330,8 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) ui = (unNumOfReg < ui) ? ui : unNumOfReg; - SETfield(r700->ps.SQ_PGM_RESOURCES_PS.u32All, ui, NUM_GPRS_shift, NUM_GPRS_mask); - + SETfield(r700->ps.SQ_PGM_RESOURCES_PS.u32All, ui, NUM_GPRS_shift, NUM_GPRS_mask); + CLEARbit(r700->ps.SQ_PGM_RESOURCES_PS.u32All, UNCACHED_FIRST_INST_bit); if(fp->r700Shader.uStackSize) /* we don't use branch for now, it should be zero. */ @@ -338,6 +343,8 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) SETfield(r700->ps.SQ_PGM_EXPORTS_PS.u32All, fp->r700Shader.exportMode, EXPORT_MODE_shift, EXPORT_MODE_mask); + R600_STATECHANGE(context, db); + if(fp->r700Shader.killIsUsed) { SETbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit); @@ -349,42 +356,13 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) if(fp->r700Shader.depthIsExported) { - SETbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit); + SETbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit); } else { CLEARbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit); } - /* sent out shader constants. */ - paramList = fp->mesa_program.Base.Parameters; - - if(NULL != paramList) - { - _mesa_load_state_parameters(ctx, paramList); - - unNumParamData = paramList->NumParameters * 4; - - BEGIN_BATCH_NO_AUTOSTATE(2 + unNumParamData); - - R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData)); - - /* assembler map const from very beginning. */ - R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4); - - unNumParamData = paramList->NumParameters; - - for(ui=0; uiParameterValues[ui][0]))); - R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1]))); - R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2]))); - R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3]))); - } - END_BATCH(); - COMMIT_BATCH(); - } - // emit ps input map unBit = 1 << FRAG_ATTRIB_WPOS; if(mesa_fp->Base.InputsRead & unBit) @@ -451,6 +429,34 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) } } + R600_STATECHANGE(context, cb); + exportCount = (r700->ps.SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift); + r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1; + + /* sent out shader constants. */ + paramList = fp->mesa_program.Base.Parameters; + + if(NULL != paramList) { + _mesa_load_state_parameters(ctx, paramList); + + if (paramList->NumParameters > R700_MAX_DX9_CONSTS) + return GL_FALSE; + + R600_STATECHANGE(context, ps_consts); + + r700->ps.num_consts = paramList->NumParameters; + + unNumParamData = paramList->NumParameters; + + for(ui=0; uips.consts[ui][0].f32All = paramList->ParameterValues[ui][0]; + r700->ps.consts[ui][1].f32All = paramList->ParameterValues[ui][1]; + r700->ps.consts[ui][2].f32All = paramList->ParameterValues[ui][2]; + r700->ps.consts[ui][3].f32All = paramList->ParameterValues[ui][3]; + } + } else + r700->ps.num_consts = 0; + return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index f0cd357c76..c8b405f555 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -55,7 +55,6 @@ void r700WaitForIdle(context_t *context); void r700WaitForIdleClean(context_t *context); -void r700Start3D(context_t *context); GLboolean r700SendTextureState(context_t *context); static unsigned int r700PrimitiveType(int prim); void r600UpdateTextureState(GLcontext * ctx); @@ -116,39 +115,6 @@ void r700Start3D(context_t *context) r700WaitForIdleClean(context); } -static GLboolean r700SetupShaders(GLcontext * ctx) -{ - context_t *context = R700_CONTEXT(ctx); - - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - - GLuint exportCount; - - r700->ps.SQ_PGM_RESOURCES_PS.u32All = 0; - r700->vs.SQ_PGM_RESOURCES_VS.u32All = 0; - - SETbit(r700->ps.SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); - SETbit(r700->vs.SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); - - r700SetupVertexProgram(ctx); - - r700SetupFragmentProgram(ctx); - - exportCount = (r700->ps.SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift); - r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1; - - r600UpdateTextureState(ctx); - - r700SendFSState(context); // FIXME just a place holder for now - r700SendPSState(context); - r700SendVSState(context); - - r700SendTextureState(context); - r700SetupStreams(ctx); - - return GL_TRUE; -} - GLboolean r700SyncSurf(context_t *context, struct radeon_bo *pbo, uint32_t read_domain, @@ -333,7 +299,7 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim } static GLboolean r700RunRender(GLcontext * ctx, - struct tnl_pipeline_stage *stage) + struct tnl_pipeline_stage *stage) { context_t *context = R700_CONTEXT(ctx); radeonContextPtr radeon = &context->radeon; @@ -347,12 +313,15 @@ static GLboolean r700RunRender(GLcontext * ctx, /* just an estimate, need to properly calculate this */ rcommonEnsureCmdBufSpace(&context->radeon, - radeon->hw.max_state_size + ind_count + 1000, __FUNCTION__); + radeon->hw.max_state_size + ind_count, __FUNCTION__); - r700Start3D(context); r700UpdateShaders(ctx); r700SetScissor(context); - r700SetupShaders(ctx); + r700SetupVertexProgram(ctx); + r700SetupFragmentProgram(ctx); + r600UpdateTextureState(ctx); + r700SetupStreams(ctx); + radeonEmitState(radeon); /* richard test code */ diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 97c7d7c385..0f25102a79 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -168,7 +168,6 @@ void r700UpdateViewportOffset(GLcontext * ctx) //------------------ void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //--------------------- { context_t *context = R700_CONTEXT(ctx); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); R600_STATECHANGE(context, cb_target); R600_STATECHANGE(context, db_target); @@ -1422,7 +1421,6 @@ static void r700SetRenderTarget(context_t *context, int id) rrb = radeon_get_colorbuffer(&context->radeon); if (!rrb || !rrb->bo) { - fprintf(stderr, "no rrb\n"); return; } diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index 14da4ed1d3..550594e9df 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -336,7 +336,6 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - BATCH_LOCALS(&context->radeon); struct r700_vertex_program *vp = (struct r700_vertex_program *)ctx->VertexProgram._Current; @@ -368,10 +367,14 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) (context->chipobj.MemUse)(context, vp->shadercode.buf->id); */ - R600_STATECHANGE(context, spi); + R600_STATECHANGE(context, vs); + R600_STATECHANGE(context, fs); /* hack */ + + r700->vs.SQ_PGM_RESOURCES_VS.u32All = 0; + SETbit(r700->vs.SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); + + r700->vs.SQ_PGM_START_VS.u32All = 0; /* set from buffer object. */ - r700->vs.SQ_PGM_START_VS.u32All = 0; /* set from buffer object. */ - SETfield(r700->vs.SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.nRegs + 1, NUM_GPRS_shift, NUM_GPRS_mask); @@ -381,9 +384,12 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) STACK_SIZE_shift, STACK_SIZE_mask); } - SETfield(r700->SPI_VS_OUT_CONFIG.u32All, vp->r700Shader.nParamExports ? (vp->r700Shader.nParamExports - 1) : 0, + R600_STATECHANGE(context, spi); + + SETfield(r700->SPI_VS_OUT_CONFIG.u32All, + vp->r700Shader.nParamExports ? (vp->r700Shader.nParamExports - 1) : 0, VS_EXPORT_COUNT_shift, VS_EXPORT_COUNT_mask); - SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, vp->r700Shader.nParamExports, + SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, vp->r700Shader.nParamExports, NUM_INTERP_shift, NUM_INTERP_mask); /* @@ -394,34 +400,26 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) /* sent out shader constants. */ paramList = vp->mesa_program.Base.Parameters; - if(NULL != paramList) - { - _mesa_load_state_parameters(ctx, paramList); + if(NULL != paramList) { + _mesa_load_state_parameters(ctx, paramList); - unNumParamData = paramList->NumParameters * 4; + if (paramList->NumParameters > R700_MAX_DX9_CONSTS) + return GL_FALSE; - BEGIN_BATCH_NO_AUTOSTATE(unNumParamData + 2); + R600_STATECHANGE(context, vs_consts); - R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData)); - /* assembler map const from very beginning. */ - R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4); + r700->vs.num_consts = paramList->NumParameters; - unNumParamData = paramList->NumParameters; + unNumParamData = paramList->NumParameters; - for(ui=0; uiParameterValues[ui][0]))); - R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1]))); - R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2]))); - R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3]))); - } - END_BATCH(); - COMMIT_BATCH(); - } + for(ui=0; uivs.consts[ui][0].f32All = paramList->ParameterValues[ui][0]; + r700->vs.consts[ui][1].f32All = paramList->ParameterValues[ui][1]; + r700->vs.consts[ui][2].f32All = paramList->ParameterValues[ui][2]; + r700->vs.consts[ui][3].f32All = paramList->ParameterValues[ui][3]; + } + } else + r700->vs.num_consts = 0; return GL_TRUE; } - - - - -- cgit v1.2.3 From 885906840d1b60650fe49d282046fc775bbcdcf1 Mon Sep 17 00:00:00 2001 From: Pauli Nieminen Date: Mon, 24 Aug 2009 02:01:15 +0300 Subject: r600: Predict emit size for next rendering. --- src/mesa/drivers/dri/r600/r700_render.c | 38 +++++++++++++++++++++++++++------ 1 file changed, 32 insertions(+), 6 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index c8b405f555..a6a9728d78 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -298,28 +298,54 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim } +/* FIXME: radom values fix with correct */ +#define PRE_EMIT_STATE_BUFSZ 30 + +static GLuint r700PredictRenderSize(GLcontext* ctx) +{ + context_t *context = R700_CONTEXT(ctx); + TNLcontext *tnl = TNL_CONTEXT(ctx); + struct vertex_buffer *vb = &tnl->vb; + GLboolean flushed; + GLuint dwords, i; + GLuint state_size; + + dwords = PRE_EMIT_STATE_BUFSZ; + for (i = 0; i < vb->PrimitiveCount; i++) + dwords += vb->Primitive[i].count + 10; + state_size = radeonCountStateEmitSize(&context->radeon); + flushed = rcommonEnsureCmdBufSpace(&context->radeon, + dwords + state_size, __FUNCTION__); + + if (flushed) + dwords += radeonCountStateEmitSize(&context->radeon); + else + dwords += state_size; + + if (RADEON_DEBUG & DEBUG_PRIMS) + fprintf(stderr, "%s: total prediction size is %d.\n", __FUNCTION__, dwords); + return dwords; +} + static GLboolean r700RunRender(GLcontext * ctx, struct tnl_pipeline_stage *stage) { context_t *context = R700_CONTEXT(ctx); radeonContextPtr radeon = &context->radeon; - unsigned int i, ind_count = 0, id = 0; + unsigned int i, id = 0; TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; struct radeon_renderbuffer *rrb; - for (i = 0; i < vb->PrimitiveCount; i++) - ind_count += vb->Primitive[i].count + 10; - /* just an estimate, need to properly calculate this */ - rcommonEnsureCmdBufSpace(&context->radeon, - radeon->hw.max_state_size + ind_count, __FUNCTION__); r700UpdateShaders(ctx); r700SetScissor(context); r700SetupVertexProgram(ctx); r700SetupFragmentProgram(ctx); r600UpdateTextureState(ctx); + + r700PredictRenderSize(ctx); r700SetupStreams(ctx); radeonEmitState(radeon); -- cgit v1.2.3 From fe42b4b7577feb5a0f10be2faf34da191e34c135 Mon Sep 17 00:00:00 2001 From: Pauli Nieminen Date: Mon, 24 Aug 2009 02:44:27 +0300 Subject: r600: Improve emit prediction. --- src/mesa/drivers/dri/r600/r700_render.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index a6a9728d78..897c0fc8ee 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -298,17 +298,21 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim } -/* FIXME: radom values fix with correct */ -#define PRE_EMIT_STATE_BUFSZ 30 +/* start 3d, idle, cb/db flush */ +#define PRE_EMIT_STATE_BUFSZ 10 + 5 + 14 static GLuint r700PredictRenderSize(GLcontext* ctx) { context_t *context = R700_CONTEXT(ctx); TNLcontext *tnl = TNL_CONTEXT(ctx); + struct r700_vertex_program *vpc + = (struct r700_vertex_program *)ctx->VertexProgram._Current; struct vertex_buffer *vb = &tnl->vb; GLboolean flushed; GLuint dwords, i; GLuint state_size; + /* pre calculate aos count so state prediction works */ + context->radeon.tcl.aos_count = _mesa_bitcount(vpc->mesa_program.Base.InputsRead); dwords = PRE_EMIT_STATE_BUFSZ; for (i = 0; i < vb->PrimitiveCount; i++) @@ -337,7 +341,9 @@ static GLboolean r700RunRender(GLcontext * ctx, struct vertex_buffer *vb = &tnl->vb; struct radeon_renderbuffer *rrb; - /* just an estimate, need to properly calculate this */ + if (RADEON_DEBUG & DEBUG_PRIMS) + fprintf(stderr, "%s: cs begin at %d\n", + __func__, context->radeon.cmdbuf.cs->cdw); r700UpdateShaders(ctx); r700SetScissor(context); @@ -345,7 +351,8 @@ static GLboolean r700RunRender(GLcontext * ctx, r700SetupFragmentProgram(ctx); r600UpdateTextureState(ctx); - r700PredictRenderSize(ctx); + GLuint emit_end = r700PredictRenderSize(ctx) + + context->radeon.cmdbuf.cs->cdw; r700SetupStreams(ctx); radeonEmitState(radeon); @@ -355,7 +362,7 @@ static GLboolean r700RunRender(GLcontext * ctx, GLuint prim = _tnl_translate_prim(&vb->Primitive[i]); GLuint start = vb->Primitive[i].start; GLuint end = vb->Primitive[i].start + vb->Primitive[i].count; - r700RunRenderPrimitive(ctx, start, end, prim); + r700RunRenderPrimitive(ctx, start, end, prim); } /* Flush render op cached for last several quads. */ @@ -372,6 +379,7 @@ static GLboolean r700RunRender(GLcontext * ctx, DB_ACTION_ENA_bit | DB_DEST_BASE_ENA_bit); radeonReleaseArrays(ctx, ~0); + assert(context->radeon.cmdbuf.cs->cdw <= emit_end); return GL_FALSE; } -- cgit v1.2.3 From d6f7ebd60352c9bb44549329e9ab61b727c7179e Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Sun, 23 Aug 2009 23:56:45 -0400 Subject: r600: fix logic copy paste error Spotted by airlied. --- src/mesa/drivers/dri/r600/r700_render.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index c8b405f555..9c4be37aac 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -336,12 +336,12 @@ static GLboolean r700RunRender(GLcontext * ctx, r700WaitForIdleClean(context); rrb = radeon_get_colorbuffer(&context->radeon); - if (!rrb || !rrb->bo) + if (rrb && rrb->bo) r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM, CB_ACTION_ENA_bit | (1 << (id + 6))); rrb = radeon_get_depthbuffer(&context->radeon); - if (!rrb || !rrb->bo) + if (rrb && rrb->bo) r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM, DB_ACTION_ENA_bit | DB_DEST_BASE_ENA_bit); -- cgit v1.2.3 From ec61f677c322c30771c351c5f0b79c917caf2a49 Mon Sep 17 00:00:00 2001 From: Pauli Nieminen Date: Mon, 24 Aug 2009 18:06:25 +0300 Subject: r600: Fix indetion and add useful debug output. --- src/mesa/drivers/dri/r600/r700_render.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index e03b060fd9..899c2cf05c 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -305,8 +305,8 @@ static GLuint r700PredictRenderSize(GLcontext* ctx) { context_t *context = R700_CONTEXT(ctx); TNLcontext *tnl = TNL_CONTEXT(ctx); - struct r700_vertex_program *vpc - = (struct r700_vertex_program *)ctx->VertexProgram._Current; + struct r700_vertex_program *vpc + = (struct r700_vertex_program *)ctx->VertexProgram._Current; struct vertex_buffer *vb = &tnl->vb; GLboolean flushed; GLuint dwords, i; @@ -316,18 +316,18 @@ static GLuint r700PredictRenderSize(GLcontext* ctx) dwords = PRE_EMIT_STATE_BUFSZ; for (i = 0; i < vb->PrimitiveCount; i++) - dwords += vb->Primitive[i].count + 10; + dwords += vb->Primitive[i].count + 10; state_size = radeonCountStateEmitSize(&context->radeon); flushed = rcommonEnsureCmdBufSpace(&context->radeon, - dwords + state_size, __FUNCTION__); + dwords + state_size, __FUNCTION__); if (flushed) - dwords += radeonCountStateEmitSize(&context->radeon); + dwords += radeonCountStateEmitSize(&context->radeon); else - dwords += state_size; + dwords += state_size; if (RADEON_DEBUG & DEBUG_PRIMS) - fprintf(stderr, "%s: total prediction size is %d.\n", __FUNCTION__, dwords); + fprintf(stderr, "%s: total prediction size is %d.\n", __FUNCTION__, dwords); return dwords; } @@ -341,8 +341,8 @@ static GLboolean r700RunRender(GLcontext * ctx, struct vertex_buffer *vb = &tnl->vb; struct radeon_renderbuffer *rrb; - if (RADEON_DEBUG & DEBUG_PRIMS) - fprintf(stderr, "%s: cs begin at %d\n", + if (RADEON_DEBUG & DEBUG_PRIMS) + fprintf(stderr, "%s: cs begin at %d\n", __func__, context->radeon.cmdbuf.cs->cdw); r700UpdateShaders(ctx); @@ -379,6 +379,11 @@ static GLboolean r700RunRender(GLcontext * ctx, DB_ACTION_ENA_bit | DB_DEST_BASE_ENA_bit); radeonReleaseArrays(ctx, ~0); + + if (RADEON_DEBUG & DEBUG_PRIMS) + fprintf(stderr, "%s: cs end at %d\n", + __func__, context->radeon.cmdbuf.cs->cdw); + assert(context->radeon.cmdbuf.cs->cdw <= emit_end); return GL_FALSE; -- cgit v1.2.3 From 29473d25a34d24ce20564af93514a8d3b096966c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 24 Aug 2009 14:39:25 -0400 Subject: r600: fix state emit sizes --- src/mesa/drivers/dri/r600/r600_context.c | 8 +--- src/mesa/drivers/dri/r600/r700_chip.c | 74 +++++++++++++++++++++++++++++--- src/mesa/drivers/dri/r600/r700_render.c | 7 +++ 3 files changed, 75 insertions(+), 14 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 0b0c4f5049..6a066f3510 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -185,13 +185,7 @@ static void r600_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmes static void r600_vtbl_pre_emit_atoms(radeonContextPtr radeon) { - context_t *context = (context_t *)radeon; - - /* always emit CB base to prevent - * lock ups on some chips. - */ - R600_STATECHANGE(context, cb_target); - r700Start3D(context); + r700Start3D((context_t *)radeon); } static void r600_fallback(GLcontext *ctx, GLuint bit, GLboolean mode) diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 3f11cf2c98..16f1a3df36 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -230,6 +230,9 @@ static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom) unsigned int i, j = 0; BATCH_LOCALS(&context->radeon); + if (context->radeon.tcl.aos_count == 0) + return; + BEGIN_BATCH_NO_AUTOSTATE(6); R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX); @@ -989,11 +992,60 @@ static int check_always(GLcontext *ctx, struct radeon_state_atom *atom) return atom->cmd_size; } +static int check_cb(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + int count = 7; + + if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) + count += 11; + + return count; +} + +static int check_blnd(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + unsigned int ui; + int count = 3; + + if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) + count += 3; + + if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) { + for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) { + if (r700->render_target[ui].enabled) + count += 3; + } + } + + return count; +} + +static int check_ucp(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + int i; + int count = 0; + + for (i = 0; i < R700_MAX_UCP; i++) { + if (r700->ucp[i].enabled) + count += 6; + } + return count; +} + static int check_vtx(GLcontext *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); + int count = context->radeon.tcl.aos_count * 18; + + if (count) + count += 6; - return context->radeon.tcl.aos_count * 18; + return count; } static int check_tx(GLcontext *ctx, struct radeon_state_atom *atom) @@ -1014,16 +1066,24 @@ static int check_ps_consts(GLcontext *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + int count = r700->ps.num_consts * 4; - return 2 + (r700->ps.num_consts * 4); + if (count) + count += 2; + + return count; } static int check_vs_consts(GLcontext *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + int count = r700->vs.num_consts * 4; + + if (count) + count += 2; - return 2 + (r700->vs.num_consts * 4); + return count; } #define ALLOC_STATE( ATOM, CHK, SZ, EMIT ) \ @@ -1056,12 +1116,12 @@ void r600InitAtoms(context_t *context) ALLOC_STATE(aa, always, 12, r700SendAAState); ALLOC_STATE(cl, always, 12, r700SendCLState); ALLOC_STATE(gb, always, 6, r700SendGBState); - ALLOC_STATE(ucp, always, 36, r700SendUCPState); + ALLOC_STATE(ucp, ucp, (R700_MAX_UCP * 6), r700SendUCPState); ALLOC_STATE(su, always, 9, r700SendSUState); ALLOC_STATE(poly, always, 10, r700SendPolyState); - ALLOC_STATE(cb, always, 18, r700SendCBState); + ALLOC_STATE(cb, cb, 18, r700SendCBState); ALLOC_STATE(clrcmp, always, 6, r700SendCBCLRCMPState); - ALLOC_STATE(blnd, always, 30, r700SendCBBlendState); + ALLOC_STATE(blnd, blnd, (6 + (R700_MAX_RENDER_TARGETS * 3)), r700SendCBBlendState); ALLOC_STATE(blnd_clr, always, 6, r700SendCBBlendColorState); ALLOC_STATE(cb_target, always, 25, r700SendRenderTargetState); ALLOC_STATE(sx, always, 9, r700SendSXState); @@ -1073,7 +1133,7 @@ void r600InitAtoms(context_t *context) ALLOC_STATE(ps, always, 21, r700SendPSState); ALLOC_STATE(vs_consts, vs_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendVSConsts); ALLOC_STATE(ps_consts, ps_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendPSConsts); - ALLOC_STATE(vtx, vtx, (VERT_ATTRIB_MAX * 18), r700SendVTXState); + ALLOC_STATE(vtx, vtx, (6 + (VERT_ATTRIB_MAX * 18)), r700SendVTXState); ALLOC_STATE(tx, tx, (R700_TEXTURE_NUMBERUNITS * 20), r700SendTexState); ALLOC_STATE(tx_smplr, tx, (R700_TEXTURE_NUMBERUNITS * 5), r700SendTexSamplerState); ALLOC_STATE(tx_brdr_clr, tx, (R700_TEXTURE_NUMBERUNITS * 6), r700SendTexBorderColorState); diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 9c4be37aac..cdf3220a7f 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -315,6 +315,13 @@ static GLboolean r700RunRender(GLcontext * ctx, rcommonEnsureCmdBufSpace(&context->radeon, radeon->hw.max_state_size + ind_count, __FUNCTION__); + /* always emit CB base to prevent + * lock ups on some chips. + */ + R600_STATECHANGE(context, cb_target); + /* mark vtx as dirty since it changes per-draw */ + R600_STATECHANGE(context, vtx); + r700UpdateShaders(ctx); r700SetScissor(context); r700SetupVertexProgram(ctx); -- cgit v1.2.3 From 4297f32c246cc5b726d02745456c06952322958d Mon Sep 17 00:00:00 2001 From: Pauli Nieminen Date: Tue, 25 Aug 2009 02:23:52 +0300 Subject: radeon/r200/r300/r600: Warn if we emit more than prediction was. Prediction code making too small prediction may cause space check aserttion failure later in rendering. So warning about any failure to predict correctly should be fixed. --- src/mesa/drivers/dri/r200/r200_tcl.c | 21 ++++++++++++++++----- src/mesa/drivers/dri/r300/r300_draw.c | 8 +++++++- src/mesa/drivers/dri/r600/r700_render.c | 6 +++++- src/mesa/drivers/dri/radeon/radeon_tcl.c | 21 ++++++++++++++++----- 4 files changed, 44 insertions(+), 12 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index 0f5e501c1a..7b3a9fc859 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -51,6 +51,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r200_swtcl.h" #include "r200_maos.h" +#include "radeon_common_context.h" + #define HAVE_POINTS 1 @@ -368,12 +370,13 @@ r200ComputeFogBlendFactor( GLcontext *ctx, GLfloat fogcoord ) * Predict total emit size for next rendering operation so there is no flush in middle of rendering * Prediction has to aim towards the best possible value that is worse than worst case scenario */ -static void r200EnsureEmitSize( GLcontext * ctx , GLubyte* vimap_rev ) +static GLuint r200EnsureEmitSize( GLcontext * ctx , GLubyte* vimap_rev ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *VB = &tnl->vb; GLuint space_required; + GLuint state_size; GLuint nr_aos = 0; int i; /* predict number of aos to emit */ @@ -387,10 +390,11 @@ static void r200EnsureEmitSize( GLcontext * ctx , GLubyte* vimap_rev ) { /* count the prediction for state size */ - space_required = radeonCountStateEmitSize( &rmesa->radeon ); + space_required = 0; + state_size = radeonCountStateEmitSize( &rmesa->radeon ); /* vtx may be changed in r200EmitArrays so account for it if not dirty */ if (!rmesa->hw.vtx.dirty) - space_required += rmesa->hw.vtx.check(rmesa->radeon.glCtx, &rmesa->hw.vtx); + state_size += rmesa->hw.vtx.check(rmesa->radeon.glCtx, &rmesa->hw.vtx); /* predict size for elements */ for (i = 0; i < VB->PrimitiveCount; ++i) { @@ -413,7 +417,10 @@ static void r200EnsureEmitSize( GLcontext * ctx , GLubyte* vimap_rev ) space_required += SCISSOR_BUFSZ; } /* flush the buffer in case we need more than is left. */ - rcommonEnsureCmdBufSpace(&rmesa->radeon, space_required, __FUNCTION__); + if (rcommonEnsureCmdBufSpace(&rmesa->radeon, space_required + state_size, __FUNCTION__)) + return space_required + radeonCountStateEmitSize( &rmesa->radeon ); + else + return space_required + state_size; } @@ -530,7 +537,8 @@ static GLboolean r200_run_tcl_render( GLcontext *ctx, /* Do the actual work: */ radeonReleaseArrays( ctx, ~0 /* stage->changed_inputs */ ); - r200EnsureEmitSize( ctx, vimap_rev ); + GLuint emit_end = r200EnsureEmitSize( ctx, vimap_rev ) + + rmesa->radeon.cmdbuf.cs->cdw; r200EmitArrays( ctx, vimap_rev ); for (i = 0 ; i < VB->PrimitiveCount ; i++) @@ -547,6 +555,9 @@ static GLboolean r200_run_tcl_render( GLcontext *ctx, else r200EmitPrimitive( ctx, start, start+length, prim ); } + if ( emit_end < rmesa->radeon.cmdbuf.cs->cdw ) + WARN_ONCE("Rendering was %d commands larger than predicted size." + " We might overflow command buffer.\n", rmesa->radeon.cmdbuf.cs->cdw - emit_end); return GL_FALSE; /* finished the pipe */ } diff --git a/src/mesa/drivers/dri/r300/r300_draw.c b/src/mesa/drivers/dri/r300/r300_draw.c index 2ac898bd59..56680516c8 100644 --- a/src/mesa/drivers/dri/r300/r300_draw.c +++ b/src/mesa/drivers/dri/r300/r300_draw.c @@ -42,6 +42,7 @@ #include "r300_cmdbuf.h" #include "radeon_buffer_objects.h" +#include "radeon_common_context.h" #include "tnl/tnl.h" #include "tnl/t_vp_build.h" @@ -632,7 +633,8 @@ static GLboolean r300TryDrawPrims(GLcontext *ctx, /* ensure we have the cmd buf space in advance to cover * the state + DMA AOS pointers */ - r300PredictTryDrawPrimsSize(ctx, nr_prims); + GLuint emit_end = r300PredictTryDrawPrimsSize(ctx, nr_prims) + + r300->radeon.cmdbuf.cs->cdw; r300SetupIndexBuffer(ctx, ib); @@ -656,6 +658,10 @@ static GLboolean r300TryDrawPrims(GLcontext *ctx, fprintf(stderr, "%s: %u (%d-%d) cs ending at %d\n", __FUNCTION__, nr_prims, min_index, max_index, r300->radeon.cmdbuf.cs->cdw ); + if (emit_end < r300->radeon.cmdbuf.cs->cdw) + WARN_ONCE("Rendering was %d commands larger than predicted size." + " We might overflow command buffer.\n", r300->radeon.cmdbuf.cs->cdw - emit_end); + return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 899c2cf05c..9b0b5443d6 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -53,6 +53,8 @@ #include "r700_fragprog.h" #include "r700_state.h" +#include "radeon_common_context.h" + void r700WaitForIdle(context_t *context); void r700WaitForIdleClean(context_t *context); GLboolean r700SendTextureState(context_t *context); @@ -384,7 +386,9 @@ static GLboolean r700RunRender(GLcontext * ctx, fprintf(stderr, "%s: cs end at %d\n", __func__, context->radeon.cmdbuf.cs->cdw); - assert(context->radeon.cmdbuf.cs->cdw <= emit_end); + if ( emit_end < context->radeon.cmdbuf.cs->cdw ) + WARN_ONCE("Rendering was %d commands larger than predicted size." + " We might overflow command buffer.\n", context->radeon.cmdbuf.cs->cdw - emit_end); return GL_FALSE; } diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.c b/src/mesa/drivers/dri/radeon/radeon_tcl.c index 908b3c9f06..2404f28450 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_tcl.c @@ -50,6 +50,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_tcl.h" #include "radeon_swtcl.h" #include "radeon_maos.h" +#include "radeon_common_context.h" @@ -359,12 +360,13 @@ radeonComputeFogBlendFactor( GLcontext *ctx, GLfloat fogcoord ) * Predict total emit size for next rendering operation so there is no flush in middle of rendering * Prediction has to aim towards the best possible value that is worse than worst case scenario */ -static void radeonEnsureEmitSize( GLcontext * ctx , GLuint inputs ) +static GLuint radeonEnsureEmitSize( GLcontext * ctx , GLuint inputs ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *VB = &tnl->vb; GLuint space_required; + GLuint state_size; GLuint nr_aos = 1; /* radeonEmitArrays does always emit one */ int i; /* list of flags that are allocating aos object */ @@ -388,10 +390,11 @@ static void radeonEnsureEmitSize( GLcontext * ctx , GLuint inputs ) { /* count the prediction for state size */ - space_required = radeonCountStateEmitSize( &rmesa->radeon ); + space_required = 0; + state_size = radeonCountStateEmitSize( &rmesa->radeon ); /* tcl may be changed in radeonEmitArrays so account for it if not dirty */ if (!rmesa->hw.tcl.dirty) - space_required += rmesa->hw.tcl.check( rmesa->radeon.glCtx, &rmesa->hw.tcl ); + state_size += rmesa->hw.tcl.check( rmesa->radeon.glCtx, &rmesa->hw.tcl ); /* predict size for elements */ for (i = 0; i < VB->PrimitiveCount; ++i) { @@ -414,7 +417,10 @@ static void radeonEnsureEmitSize( GLcontext * ctx , GLuint inputs ) space_required += SCISSOR_BUFSZ; } /* flush the buffer in case we need more than is left. */ - rcommonEnsureCmdBufSpace(&rmesa->radeon, space_required, __FUNCTION__); + if (rcommonEnsureCmdBufSpace(&rmesa->radeon, space_required, __FUNCTION__)) + return space_required + radeonCountStateEmitSize( &rmesa->radeon ); + else + return space_required + state_size; } /**********************************************************************/ @@ -467,7 +473,8 @@ static GLboolean radeon_run_tcl_render( GLcontext *ctx, } radeonReleaseArrays( ctx, ~0 ); - radeonEnsureEmitSize( ctx, inputs ); + GLuint emit_end = radeonEnsureEmitSize( ctx, inputs ) + + rmesa->radeon.cmdbuf.cs->cdw; radeonEmitArrays( ctx, inputs ); rmesa->tcl.Elts = VB->Elts; @@ -487,6 +494,10 @@ static GLboolean radeon_run_tcl_render( GLcontext *ctx, radeonEmitPrimitive( ctx, start, start+length, prim ); } + if (emit_end < rmesa->radeon.cmdbuf.cs->cdw) + WARN_ONCE("Rendering was %d commands larger than predicted size." + " We might overflow command buffer.\n", rmesa->radeon.cmdbuf.cs->cdw - emit_end); + return GL_FALSE; /* finished the pipe */ } -- cgit v1.2.3 From 490f640cd58d215281076ae6e0e70649db6b0ed5 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 26 Aug 2009 12:17:44 -0400 Subject: r600: make reloc_chunk size dynamic --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 12 +++++++++--- src/mesa/drivers/dri/r600/r700_render.c | 3 +-- 2 files changed, 10 insertions(+), 5 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 050d7bc6d0..1734b0a89f 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -324,7 +324,7 @@ static int r600_cs_emit(struct radeon_cs *cs) struct drm_radeon_cs_chunk cs_chunk[2]; uint32_t length_dw_reloc_chunk; uint64_t chunk_ptrs[2]; - uint32_t reloc_chunk[256]; + uint32_t *reloc_chunk; int r; int retry = 0; @@ -333,8 +333,11 @@ static int r600_cs_emit(struct radeon_cs *cs) csm->pending_count = 1; - r = r600_cs_process_relocs(cs, &(reloc_chunk[0]), &length_dw_reloc_chunk); + reloc_chunk = (uint32_t*)calloc(1, cs->crelocs * 4 * 4); + + r = r600_cs_process_relocs(cs, reloc_chunk, &length_dw_reloc_chunk); if (r) { + free(reloc_chunk); return 0; } @@ -346,7 +349,7 @@ static int r600_cs_emit(struct radeon_cs *cs) /* reloc chaunk */ cs_chunk[1].chunk_id = RADEON_CHUNK_ID_RELOCS; cs_chunk[1].length_dw = length_dw_reloc_chunk; - cs_chunk[1].chunk_data = (unsigned long)&(reloc_chunk[0]); + cs_chunk[1].chunk_data = (unsigned long)reloc_chunk; chunk_ptrs[0] = (uint64_t)(unsigned long)&(cs_chunk[0]); chunk_ptrs[1] = (uint64_t)(unsigned long)&(cs_chunk[1]); @@ -364,6 +367,7 @@ static int r600_cs_emit(struct radeon_cs *cs) } while (r == -EAGAIN && retry < 1000); if (r) { + free(reloc_chunk); return r; } @@ -375,6 +379,8 @@ static int r600_cs_emit(struct radeon_cs *cs) cs->csm->vram_write_used = 0; cs->csm->gart_write_used = 0; + free(reloc_chunk); + return 0; } diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index d64e921bda..0b3ceb01ba 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -143,8 +143,7 @@ GLboolean r700SyncSurf(context_t *context, R600_OUT_BATCH_RELOC(0, pbo, 0, - read_domain, write_domain, 0); // ??? - + read_domain, write_domain, 0); END_BATCH(); COMMIT_BATCH(); -- cgit v1.2.3 From aabb36fdd58ff891e3a0946e2326d458f5a4d832 Mon Sep 17 00:00:00 2001 From: Pauli Nieminen Date: Sun, 30 Aug 2009 22:08:38 +0300 Subject: r600: Convert to shared debug code and add a few new debug messages. There is only a few functions that have debugging enabled now. --- src/mesa/drivers/dri/r600/Makefile | 9 ++-- src/mesa/drivers/dri/r600/r600_context.c | 10 +++- src/mesa/drivers/dri/r600/r600_emit.c | 28 ++++++----- src/mesa/drivers/dri/r600/r600_tex.c | 20 ++++---- src/mesa/drivers/dri/r600/r600_texstate.c | 8 ++-- src/mesa/drivers/dri/r600/r700_assembler.c | 72 ++++++++++++++--------------- src/mesa/drivers/dri/r600/r700_chip.c | 34 ++++++++++++++ src/mesa/drivers/dri/r600/r700_clear.c | 5 +- src/mesa/drivers/dri/r600/r700_debug.c | 35 +++----------- src/mesa/drivers/dri/r600/r700_debug.h | 60 ++---------------------- src/mesa/drivers/dri/r600/r700_oglprog.c | 6 +++ src/mesa/drivers/dri/r600/r700_render.c | 10 ++-- src/mesa/drivers/dri/r600/r700_shaderinst.c | 14 +++--- src/mesa/drivers/dri/r600/r700_vertprog.c | 3 +- 14 files changed, 141 insertions(+), 173 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/Makefile b/src/mesa/drivers/dri/r600/Makefile index 3c3100ab91..d925a2dfe3 100644 --- a/src/mesa/drivers/dri/r600/Makefile +++ b/src/mesa/drivers/dri/r600/Makefile @@ -27,16 +27,17 @@ COMMON_SOURCES = \ ../common/dri_util.c RADEON_COMMON_SOURCES = \ - radeon_texture.c \ + radeon_bo_legacy.c \ radeon_common_context.c \ radeon_common.c \ + radeon_cs_legacy.c \ radeon_dma.c \ + radeon_debug.c \ + radeon_fbo.c \ radeon_lock.c \ - radeon_bo_legacy.c \ - radeon_cs_legacy.c \ radeon_mipmap_tree.c \ radeon_span.c \ - radeon_fbo.c \ + radeon_texture.c \ radeon_queryobj.c DRIVER_SOURCES = \ diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 6a066f3510..251c124cbf 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -56,6 +56,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drivers/common/driverfuncs.h" +#include "radeon_debug.h" #include "r600_context.h" #include "radeon_common_context.h" #include "radeon_span.h" @@ -225,8 +226,10 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, /* Allocate the R600 context */ r600 = (context_t*) CALLOC(sizeof(*r600)); - if (!r600) + if (!r600) { + radeon_error("Failed to allocate memory for context.\n"); return GL_FALSE; + } if (!(screen->chip_flags & RADEON_CHIPSET_TCL)) hw_tcl_on = future_hw_tcl_on = 0; @@ -255,6 +258,7 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, if (!radeonInitContext(&r600->radeon, &functions, glVisual, driContextPriv, sharedContextPrivate)) { + radeon_error("Initializing context failed.\n"); FREE(r600); return GL_FALSE; } @@ -347,6 +351,8 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, ctx->VertexProgram._MaintainTnlProgram = GL_TRUE; ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE; + radeon_init_debug(); + driInitExtensions(ctx, card_extensions, GL_TRUE); if (r600->radeon.radeonScreen->kernel_mm) driInitExtensions(ctx, mm_extensions, GL_FALSE); @@ -375,7 +381,7 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, TNL_CONTEXT(ctx)->Driver.RunPipeline = r600RunPipeline; if (driQueryOptionb(&r600->radeon.optionCache, "no_rast")) { - fprintf(stderr, "disabling 3D acceleration\n"); + radeon_warning("disabling 3D acceleration\n"); #if R200_MERGED FALLBACK(&r600->radeon, RADEON_FALLBACK_DISABLE, 1); #endif diff --git a/src/mesa/drivers/dri/r600/r600_emit.c b/src/mesa/drivers/dri/r600/r600_emit.c index f8c56e7774..5c250c2418 100644 --- a/src/mesa/drivers/dri/r600/r600_emit.c +++ b/src/mesa/drivers/dri/r600/r600_emit.c @@ -60,28 +60,30 @@ GLboolean r600EmitShader(GLcontext * ctx, radeonContextPtr radeonctx = RADEON_CONTEXT(ctx); struct radeon_bo * pbo; uint32_t *out; - shader_again_alloc: pbo = radeon_bo_open(radeonctx->radeonScreen->bom, - 0, - sizeinDWORD * 4, - 256, - RADEON_GEM_DOMAIN_GTT, - 0); + 0, + sizeinDWORD * 4, + 256, + RADEON_GEM_DOMAIN_GTT, + 0); + + radeon_print(RADEON_SHADER, RADEON_NORMAL, "%s %p size %d: %s\n", __func__, pbo, sizeinDWORD, szShaderUsage); if (!pbo) { + radeon_print(RADEON_MEMORY | RADEON_CS, RADEON_IMPORTANT, "No memory for buffer object. Flushing command buffer.\n"); rcommonFlushCmdBuf(radeonctx, __FUNCTION__); goto shader_again_alloc; } radeon_cs_space_add_persistent_bo(radeonctx->cmdbuf.cs, - pbo, - RADEON_GEM_DOMAIN_GTT, 0); + pbo, + RADEON_GEM_DOMAIN_GTT, 0); - if (radeon_cs_space_check_with_bo(radeonctx->cmdbuf.cs, - pbo, - RADEON_GEM_DOMAIN_GTT, 0)) { - fprintf(stderr,"failure to revalidate BOs - badness\n"); + if (radeon_cs_space_check_with_bo(radeonctx->cmdbuf.cs, + pbo, + RADEON_GEM_DOMAIN_GTT, 0)) { + radeon_error("failure to revalidate BOs - badness\n"); return GL_FALSE; } @@ -103,6 +105,8 @@ GLboolean r600DeleteShader(GLcontext * ctx, { struct radeon_bo * pbo = (struct radeon_bo *)shaderbo; + radeon_print(RADEON_SHADER, RADEON_NORMAL, "%s: %p\n", __func__, pbo); + if (pbo) { if (pbo->ptr) radeon_bo_unmap(pbo); diff --git a/src/mesa/drivers/dri/r600/r600_tex.c b/src/mesa/drivers/dri/r600/r600_tex.c index a06a1fa921..d105b90cd1 100644 --- a/src/mesa/drivers/dri/r600/r600_tex.c +++ b/src/mesa/drivers/dri/r600/r600_tex.c @@ -67,7 +67,7 @@ static unsigned int translate_wrap_mode(GLenum wrapmode) case GL_MIRROR_CLAMP_TO_EDGE_EXT: return SQ_TEX_MIRROR_ONCE_LAST_TEXEL; case GL_MIRROR_CLAMP_TO_BORDER_EXT: return SQ_TEX_MIRROR_ONCE_BORDER; default: - _mesa_problem(NULL, "bad wrap mode in %s", __FUNCTION__); + radeon_error("bad wrap mode in %s", __FUNCTION__); return 0; } } @@ -208,8 +208,7 @@ static void r600SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloa | R300_TX_MIN_FILTER_ANISO | R300_TX_MIN_FILTER_MIP_LINEAR | aniso_filter(anisotropy);*/ - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "Using maximum anisotropy of %f\n", anisotropy); + radeon_print(RADEON_TEXTURE, RADEON_NORMAL, "Using maximum anisotropy of %f\n", anisotropy); return; } @@ -288,10 +287,9 @@ static void r600TexParameter(GLcontext * ctx, GLenum target, { radeonTexObj* t = radeon_tex_obj(texObj); - if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { - fprintf(stderr, "%s( %s )\n", __FUNCTION__, + radeon_print(RADEON_STATE | RADEON_TEXTURE, RADEON_VERBOSE, + "%s( %s )\n", __FUNCTION__, _mesa_lookup_enum_by_nr(pname)); - } switch (pname) { case GL_TEXTURE_MIN_FILTER: @@ -351,11 +349,10 @@ static void r600DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) context_t* rmesa = R700_CONTEXT(ctx); radeonTexObj* t = radeon_tex_obj(texObj); - if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { - fprintf(stderr, "%s( %p (target = %s) )\n", __FUNCTION__, + radeon_print(RADEON_STATE | RADEON_TEXTURE, RADEON_NORMAL, + "%s( %p (target = %s) )\n", __FUNCTION__, (void *)texObj, _mesa_lookup_enum_by_nr(texObj->Target)); - } if (rmesa) { int i; @@ -393,10 +390,9 @@ static struct gl_texture_object *r600NewTextureObject(GLcontext * ctx, radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj); - if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { - fprintf(stderr, "%s( %p (target = %s) )\n", __FUNCTION__, + radeon_print(RADEON_STATE | RADEON_TEXTURE, RADEON_NORMAL, + "%s( %p (target = %s) )\n", __FUNCTION__, t, _mesa_lookup_enum_by_nr(target)); - } _mesa_initialize_texture_object(&t->base, name, target); t->base.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy; diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 9f1bf45246..237eaa8249 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -567,7 +567,7 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex if (!t->image_override) { if (!r600GetTexFormat(texObj, firstImage->TexFormat->MesaFormat)) { - _mesa_problem(NULL, "unexpected texture format in %s", + radeon_error("unexpected texture format in %s\n", __FUNCTION__); return; } @@ -593,7 +593,7 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex SETfield(t->SQ_TEX_RESOURCE1, 0, TEX_DEPTH_shift, TEX_DEPTH_mask); break; default: - _mesa_problem(NULL, "unexpected texture target type in %s", __FUNCTION__); + radeon_error("unexpected texture target type in %s\n", __FUNCTION__); return; } @@ -675,9 +675,7 @@ GLboolean r600ValidateBuffers(GLcontext * ctx) continue; if (!r600_validate_texture(ctx, ctx->Texture.Unit[i]._Current)) { - _mesa_warning(ctx, - "failed to validate texture for unit %d.\n", - i); + radeon_warning("failed to validate texture for unit %d.\n", i); } t = radeon_tex_obj(ctx->Texture.Unit[i]._Current); if (t->image_override && t->bo) diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 834c23593b..2d8480daaf 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -33,8 +33,8 @@ #include "main/mtypes.h" #include "main/imports.h" +#include "radeon_debug.h" #include "r600_context.h" -#include "r700_debug.h" #include "r700_assembler.h" @@ -366,8 +366,8 @@ unsigned int r700GetNumOperands(r700_AssemblerBase* pAsm) case SQ_OP2_INST_COS: return 1; - default: r700_error(TODO_ASM_NEEDIMPINST, - "Need instruction operand number. \n");; + default: radeon_error( + "Need instruction operand number for %x.\n", pAsm->D.dst.opcode); }; return 3; @@ -531,7 +531,7 @@ int check_current_clause(r700_AssemblerBase* pAsm, case CF_EMPTY_CLAUSE: break; default: - r700_error(ERROR_ASM_VTX_CLAUSE, + radeon_error( "Unknown CF_CLAUSE_TYPE (%d) in check_current_clause. \n", (int) new_clause_type); return GL_FALSE; } @@ -565,7 +565,7 @@ int check_current_clause(r700_AssemblerBase* pAsm, } else { - r700_error(ERROR_ASM_ALLOCEXPORTCF, + radeon_error( "Error allocating new EXPORT CF instruction in check_current_clause. \n"); return GL_FALSE; } @@ -578,7 +578,7 @@ int check_current_clause(r700_AssemblerBase* pAsm, pAsm->cf_current_clause_type = CF_OTHER_CLAUSE; break; default: - r700_error(ERROR_ASM_UNKOWNCLAUSE, + radeon_error( "Unknown CF_CLAUSE_TYPE (%d) in check_current_clause. \n", (int) new_clause_type); return GL_FALSE; } @@ -611,7 +611,7 @@ GLboolean add_vfetch_instruction(r700_AssemblerBase* pAsm, } else { - r700_error(ERROR_ASM_ALLOCVTXCF, "Could not allocate a new VFetch CF instruction."); + radeon_error("Could not allocate a new VFetch CF instruction.\n"); return GL_FALSE; } @@ -661,7 +661,7 @@ GLboolean add_tex_instruction(r700_AssemblerBase* pAsm, } else { - r700_error(ERROR_ASM_ALLOCTEXCF, "Could not allocate a new TEX CF instruction."); + radeon_error("Could not allocate a new TEX CF instruction.\n"); return GL_FALSE; } @@ -1047,7 +1047,7 @@ GLboolean assemble_src(r700_AssemblerBase *pAsm, } break; default: - r700_error(ERROR_ASM_SRCARGUMENT, "Invalid source argument type"); + radeon_error("Invalid source argument type\n"); return GL_FALSE; } } @@ -1094,7 +1094,7 @@ GLboolean assemble_dst(r700_AssemblerBase *pAsm) } break; default: - r700_error(ERROR_ASM_DSTARGUMENT, "Invalid destination output argument type"); + radeon_error("Invalid destination output argument type\n"); return GL_FALSE; } @@ -1134,7 +1134,7 @@ GLboolean tex_dst(r700_AssemblerBase *pAsm) } else { - r700_error(ERROR_ASM_DSTARGUMENT, "Invalid destination output argument type"); + radeon_error("Invalid destination output argument type\n"); return GL_FALSE; } @@ -1188,7 +1188,7 @@ GLboolean tex_src(r700_AssemblerBase *pAsm) } else { - r700_error(ERROR_ASM_BADTEXSRC, "Invalid source texcoord for TEX instruction"); + radeon_error("Invalid source texcoord for TEX instruction\n"); return GL_FALSE; } @@ -1269,7 +1269,7 @@ GLboolean assemble_tex_instruction(r700_AssemblerBase *pAsm, GLboolean normalize } else { - r700_error(ERROR_ASM_TEXDSTBADTYPE, "Only temp destination registers supported for TEX dest regs."); + radeon_error("Only temp destination registers supported for TEX dest regs.\n"); return GL_FALSE; } @@ -1362,7 +1362,7 @@ GLboolean assemble_alu_src(R700ALUInstruction* alu_instruction_ptr, } else { - r700_error(ERROR_ASM_ALUSRCBADTYPE, "Source (%d) register type (%d) not one of TEMP, INPUT, or CONSTANT.", + radeon_error("Source (%d) register type (%d) not one of TEMP, INPUT, or CONSTANT.\n", source_index, pSource->rtype); return GL_FALSE; } @@ -1397,7 +1397,7 @@ GLboolean assemble_alu_src(R700ALUInstruction* alu_instruction_ptr, src_chan = SQ_CHAN_X; break; default: - r700_error(ERROR_ASM_ALUSRCSELECT, "Unknown source select value (%d) in assemble_alu_src()."); + radeon_error("Unknown source select value (%d) in assemble_alu_src().\n", channel_swizzle); return GL_FALSE; break; } @@ -1432,7 +1432,7 @@ GLboolean assemble_alu_src(R700ALUInstruction* alu_instruction_ptr, alu_instruction_ptr->m_Word1_OP3.f.src2_neg = src_neg; break; default: - r700_error(ERROR_ASM_ALUSRCNUMBER, "Only three sources allowed in ALU opcodes."); + radeon_error("Only three sources allowed in ALU opcodes.\n"); return GL_FALSE; break; } @@ -1467,7 +1467,7 @@ GLboolean add_alu_instruction(r700_AssemblerBase* pAsm, } else { - r700_error(ERROR_ASM_ALLOCALUCF, "Could not allocate a new ALU CF instruction."); + radeon_error("Could not allocate a new ALU CF instruction.\n"); return GL_FALSE; } @@ -1635,7 +1635,7 @@ GLboolean reserve_cfile(r700_AssemblerBase* pAsm, } else { - r700_error(ERROR_ASM_CONSTCHANNEL, "All cfile read ports are used, cannot reference C$sel, channel $chan."); + radeon_error("All cfile read ports are used, cannot reference C$sel, channel $chan.\n"); return GL_FALSE; } return GL_TRUE; @@ -1649,7 +1649,7 @@ GLboolean reserve_gpr(r700_AssemblerBase* pAsm, GLuint sel, GLuint chan, GLuint } else if(pAsm->hw_gpr[cycle][chan] != (int)sel) { - r700_error(ERROR_ASM_BADGPRRESERVE, "Another scalar operation has already used GPR read port for given channel"); + radeon_error("Another scalar operation has already used GPR read port for given channel\n"); return GL_FALSE; } @@ -1689,7 +1689,7 @@ GLboolean cycle_for_scalar_bank_swizzle(const int swiz, const int sel, GLuint* p } break; default: - r700_error(ERROR_ASM_BADSCALARBZ, "Bad Scalar bank swizzle value"); + radeon_error("Bad Scalar bank swizzle value\n"); break; } @@ -1737,7 +1737,7 @@ GLboolean cycle_for_vector_bank_swizzle(const int swiz, const int sel, GLuint* p } break; default: - r700_error(ERROR_ASM_BADVECTORBZ, "Bad Vec bank swizzle value"); + radeon_error("Bad Vec bank swizzle value\n"); return GL_FALSE; break; } @@ -2056,7 +2056,7 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) } else { - r700_error(ERROR_ASM_ALUDSTBADTYPE, "Only temp destination registers supported for ALU dest regs."); + radeon_error("Only temp destination registers supported for ALU dest regs.\n"); return GL_FALSE; } @@ -2207,13 +2207,13 @@ GLboolean next_ins(r700_AssemblerBase *pAsm) if (pILInst->TexSrcTarget == TEXTURE_RECT_INDEX) { if( GL_FALSE == assemble_tex_instruction(pAsm, GL_FALSE) ) { - r700_error(ERROR_ASM_TEXINSTRUCTION, "Error assembling TEX instruction"); + radeon_error("Error assembling TEX instruction\n"); return GL_FALSE; } } else { if( GL_FALSE == assemble_tex_instruction(pAsm, GL_TRUE) ) { - r700_error(ERROR_ASM_TEXINSTRUCTION, "Error assembling TEX instruction"); + radeon_error("Error assembling TEX instruction\n"); return GL_FALSE; } } @@ -2222,7 +2222,7 @@ GLboolean next_ins(r700_AssemblerBase *pAsm) { //ALU if( GL_FALSE == assemble_alu_instruction(pAsm) ) { - r700_error(ERROR_ASM_TEXINSTRUCTION, "Error assembling ALU instruction"); + radeon_error("Error assembling ALU instruction\n"); return GL_FALSE; } } @@ -2367,7 +2367,7 @@ GLboolean assemble_ADD(r700_AssemblerBase *pAsm) GLboolean assemble_BAD(char *opcode_str) { - r700_error(TODO_ASM_NEEDIMPINST, "Not yet implemented instruction (%s)", opcode_str); + radeon_error("Not yet implemented instruction (%s)\n", opcode_str); return GL_FALSE; } @@ -3381,7 +3381,7 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) if (GL_TRUE == src_const) { - r700_error(TODO_ASM_CONSTTEXADDR, "TODO: Texture coordinates from a constant register not supported."); + radeon_error("TODO: Texture coordinates from a constant register not supported.\n"); return GL_FALSE; } @@ -3391,7 +3391,7 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE; break; case OPCODE_TXB: - r700_error(TODO_ASM_TXB, "do not support TXB yet"); + radeon_error("do not support TXB yet\n"); return GL_FALSE; break; case OPCODE_TXP: @@ -3399,7 +3399,7 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE; break; default: - r700_error(ERROR_ASM_BADTEXINST, "Internal error: bad texture op (not TEX)"); + radeon_error("Internal error: bad texture op (not TEX)\n"); return GL_FALSE; break; } @@ -3581,12 +3581,12 @@ GLboolean AssembleInstr(GLuint uiNumberInsts, break; case OPCODE_ARL: - r700_error(TODO_ASM_NEEDIMPINST, "Not yet implemented instruction OPCODE_ARL "); + radeon_error("Not yet implemented instruction OPCODE_ARL \n"); //if ( GL_FALSE == assemble_BAD("ARL") ) return GL_FALSE; break; case OPCODE_ARR: - r700_error(TODO_ASM_NEEDIMPINST, "Not yet implemented instruction OPCODE_ARR "); + radeon_error("Not yet implemented instruction OPCODE_ARR \n"); //if ( GL_FALSE == assemble_BAD("ARR") ) return GL_FALSE; break; @@ -3617,7 +3617,7 @@ GLboolean AssembleInstr(GLuint uiNumberInsts, return GL_FALSE; break; case OPCODE_EXP: - r700_error(TODO_ASM_NEEDIMPINST, "Not yet implemented instruction OPCODE_EXP "); + radeon_error("Not yet implemented instruction OPCODE_EXP \n"); //if ( GL_FALSE == assemble_BAD("EXP") ) return GL_FALSE; break; // approx of EX2 @@ -3653,7 +3653,7 @@ GLboolean AssembleInstr(GLuint uiNumberInsts, return GL_FALSE; break; case OPCODE_LOG: - r700_error(TODO_ASM_NEEDIMPINST, "Not yet implemented instruction OPCODE_LOG "); + radeon_error("Not yet implemented instruction OPCODE_LOG \n"); //if ( GL_FALSE == assemble_BAD("LOG") ) return GL_FALSE; break; // approx of LG2 @@ -3752,7 +3752,7 @@ GLboolean AssembleInstr(GLuint uiNumberInsts, return GL_FALSE; break; case OPCODE_ELSE : - r700_error(TODO_ASM_NEEDIMPINST, "Not yet implemented instruction OPCODE_ELSE "); + radeon_error("Not yet implemented instruction OPCODE_ELSE \n"); //if ( GL_FALSE == assemble_BAD("ELSE") ) return GL_FALSE; break; @@ -3774,7 +3774,7 @@ GLboolean AssembleInstr(GLuint uiNumberInsts, return GL_TRUE; default: - r700_error(ERROR_ASM_UNKNOWNILINST, "internal: unknown instruction"); + radeon_error("internal: unknown instruction\n"); return GL_FALSE; } } @@ -3818,7 +3818,7 @@ GLboolean Process_Export(r700_AssemblerBase* pAsm, break; default: - r700_error(ERROR_ASM_BADEXPORTTYPE, "Unknown export type: %d", type); + radeon_error("Unknown export type: %d\n", type); return GL_FALSE; break; } diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 16f1a3df36..4fc624ed0b 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -49,6 +49,8 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom) unsigned int i; BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); + for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) { radeonTexObj *t = r700->textures[i]; if (t) { @@ -93,6 +95,7 @@ static void r700SendTexSamplerState(GLcontext *ctx, struct radeon_state_atom *at R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); unsigned int i; BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) { radeonTexObj *t = r700->textures[i]; @@ -115,6 +118,7 @@ static void r700SendTexBorderColorState(GLcontext *ctx, struct radeon_state_atom R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); unsigned int i; BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) { radeonTexObj *t = r700->textures[i]; @@ -141,6 +145,7 @@ static void r700SetupVTXConstants(GLcontext * ctx, context_t *context = R700_CONTEXT(ctx); struct radeon_aos * paos = (struct radeon_aos *)pAos; BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); unsigned int uSQ_VTX_CONSTANT_WORD0_0; unsigned int uSQ_VTX_CONSTANT_WORD1_0; @@ -205,6 +210,7 @@ void r700SetupStreams(GLcontext *ctx) TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; unsigned int i, j = 0; + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); R600_STATECHANGE(context, vtx); @@ -229,6 +235,7 @@ static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom) = (struct r700_vertex_program *)ctx->VertexProgram._Current; unsigned int i, j = 0; BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); if (context->radeon.tcl.aos_count == 0) return; @@ -264,6 +271,7 @@ static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *a R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_renderbuffer *rrb; BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); rrb = radeon_get_depthbuffer(&context->radeon); if (!rrb || !rrb->bo) { @@ -303,6 +311,7 @@ static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom * struct radeon_renderbuffer *rrb; BATCH_LOCALS(&context->radeon); int id = 0; + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); rrb = radeon_get_colorbuffer(&context->radeon); if (!rrb || !rrb->bo) { @@ -352,6 +361,7 @@ static void r700SendPSState(GLcontext *ctx, struct radeon_state_atom *atom) R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context)); @@ -385,6 +395,7 @@ static void r700SendVSState(GLcontext *ctx, struct radeon_state_atom *atom) R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); @@ -416,6 +427,7 @@ static void r700SendFSState(GLcontext *ctx, struct radeon_state_atom *atom) R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); /* XXX fixme * R6xx chips require a FS be emitted, even if it's not used. @@ -457,6 +469,7 @@ static void r700SendViewportState(GLcontext *ctx, struct radeon_state_atom *atom R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); int id = 0; + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); if (id > R700_MAX_VIEWPORTS) return; @@ -489,6 +502,7 @@ static void r700SendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); BEGIN_BATCH_NO_AUTOSTATE(34); R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6); @@ -526,6 +540,7 @@ static void r700SendUCPState(GLcontext *ctx, struct radeon_state_atom *atom) R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); int i; + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); for (i = 0; i < R700_MAX_UCP; i++) { if (r700->ucp[i].enabled) { @@ -547,6 +562,7 @@ static void r700SendSPIState(GLcontext *ctx, struct radeon_state_atom *atom) R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); unsigned int ui; + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); BEGIN_BATCH_NO_AUTOSTATE(59 + R700_MAX_SHADER_EXPORTS); @@ -620,6 +636,7 @@ static void r700SendVGTState(GLcontext *ctx, struct radeon_state_atom *atom) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); BEGIN_BATCH_NO_AUTOSTATE(41); @@ -665,6 +682,7 @@ static void r700SendSXState(GLcontext *ctx, struct radeon_state_atom *atom) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); BEGIN_BATCH_NO_AUTOSTATE(9); R600_OUT_BATCH_REGVAL(SX_MISC, r700->SX_MISC.u32All); @@ -679,6 +697,7 @@ static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); BEGIN_BATCH_NO_AUTOSTATE(23); R600_OUT_BATCH_REGVAL(DB_HTILE_DATA_BASE, r700->DB_HTILE_DATA_BASE.u32All); @@ -720,6 +739,7 @@ static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) { BEGIN_BATCH_NO_AUTOSTATE(11); @@ -766,6 +786,7 @@ static void r700SendCBBlendState(GLcontext *ctx, struct radeon_state_atom *atom) R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); unsigned int ui; + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) { BEGIN_BATCH_NO_AUTOSTATE(3); @@ -796,6 +817,7 @@ static void r700SendCBBlendColorState(GLcontext *ctx, struct radeon_state_atom * context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); BEGIN_BATCH_NO_AUTOSTATE(6); R600_OUT_BATCH_REGSEQ(CB_BLEND_RED, 4); @@ -850,6 +872,7 @@ static void r700SendCLState(GLcontext *ctx, struct radeon_state_atom *atom) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); BEGIN_BATCH_NO_AUTOSTATE(12); R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, r700->PA_CL_CLIP_CNTL.u32All); @@ -881,6 +904,7 @@ static void r700SendScissorState(GLcontext *ctx, struct radeon_state_atom *atom) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); BEGIN_BATCH_NO_AUTOSTATE(22); R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2); @@ -913,6 +937,7 @@ static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); BEGIN_BATCH_NO_AUTOSTATE(15); R600_OUT_BATCH_REGVAL(R7xx_PA_SC_EDGERULE, r700->PA_SC_EDGERULE.u32All); @@ -969,6 +994,7 @@ static void r700SendVSConsts(GLcontext *ctx, struct radeon_state_atom *atom) R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); int i; BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); if (r700->vs.num_consts == 0) return; @@ -999,6 +1025,7 @@ static int check_cb(GLcontext *ctx, struct radeon_state_atom *atom) if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) count += 11; + radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count); return count; } @@ -1019,6 +1046,7 @@ static int check_blnd(GLcontext *ctx, struct radeon_state_atom *atom) count += 3; } } + radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count); return count; } @@ -1034,6 +1062,7 @@ static int check_ucp(GLcontext *ctx, struct radeon_state_atom *atom) if (r700->ucp[i].enabled) count += 6; } + radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count); return count; } @@ -1045,6 +1074,7 @@ static int check_vtx(GLcontext *ctx, struct radeon_state_atom *atom) if (count) count += 6; + radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count); return count; } @@ -1059,6 +1089,7 @@ static int check_tx(GLcontext *ctx, struct radeon_state_atom *atom) if (t) count++; } + radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count); return count * 31; } @@ -1070,6 +1101,7 @@ static int check_ps_consts(GLcontext *ctx, struct radeon_state_atom *atom) if (count) count += 2; + radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count); return count; } @@ -1082,6 +1114,7 @@ static int check_vs_consts(GLcontext *ctx, struct radeon_state_atom *atom) if (count) count += 2; + radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count); return count; } @@ -1101,6 +1134,7 @@ do { \ void r600InitAtoms(context_t *context) { + radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context); context->radeon.hw.max_state_size = 10 + 5 + 14; /* start 3d, idle, cb/db flush */ /* Setup the atom linked list */ diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c index 6d4ea90ccc..c6546ab00c 100644 --- a/src/mesa/drivers/dri/r600/r700_clear.c +++ b/src/mesa/drivers/dri/r600/r700_clear.c @@ -55,6 +55,8 @@ void r700Clear(GLcontext * ctx, GLbitfield mask) int i; struct gl_framebuffer *fb = ctx->DrawBuffer; + radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s %x\n", __func__, mask); + if( GL_TRUE == r700ClearFast(context, mask) ) { return; @@ -106,8 +108,7 @@ void r700Clear(GLcontext * ctx, GLbitfield mask) } if (swrast_mask) { - if (RADEON_DEBUG & DEBUG_FALLBACKS) - fprintf(stderr, "%s: swrast clear, mask: %x\n", + radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT, "%s: swrast clear, mask: %x\n", __FUNCTION__, swrast_mask); _swrast_Clear(ctx, swrast_mask); } diff --git a/src/mesa/drivers/dri/r600/r700_debug.c b/src/mesa/drivers/dri/r600/r700_debug.c index dabd0d2c25..cd1ba9eca3 100644 --- a/src/mesa/drivers/dri/r600/r700_debug.c +++ b/src/mesa/drivers/dri/r600/r700_debug.c @@ -25,31 +25,8 @@ * CooperYuan , */ -#include -#include -#include -#include - -#include "main/glheader.h" - #include "r700_debug.h" -#include "r600_context.h" - -void NormalizeLogErrorCode(int nError) -{ - //TODO -} - -void r700_error(int nLocalError, char* fmt, ...) -{ - va_list args; - - NormalizeLogErrorCode(nLocalError); - - va_start(args, fmt); - fprintf(stderr, fmt, args); - va_end(args); -} +#include "radeon_debug.h" void DumpHwBinary(int type, void *addr, int size) { @@ -61,21 +38,21 @@ void DumpHwBinary(int type, void *addr, int size) switch (type) { case DUMP_PIXEL_SHADER: - DEBUGF("Pixel Shader\n"); + radeon_print(RADEON_SHADER, RADEON_TRACE, "Pixel Shader\n"); break; case DUMP_VERTEX_SHADER: - DEBUGF("Vertex Shader\n"); + radeon_print(RADEON_SHADER, RADEON_TRACE, "Vertex Shader\n"); break; case DUMP_FETCH_SHADER: - DEBUGF("Fetch Shader\n"); + radeon_print(RADEON_SHADER, RADEON_TRACE, "Fetch Shader\n"); break; } for (i = 0; i < size; i++) { - DEBUGP("0x%08x,\t", *pHw); + radeon_print(RADEON_SHADER, RADEON_TRACE, "0x%08x,\t", *pHw); if (i%4 == 3) - DEBUGP("0x%08x\n", *pHw); + radeon_print(RADEON_SHADER, RADEON_TRACE, "0x%08x\n", *pHw); pHw++; } diff --git a/src/mesa/drivers/dri/r600/r700_debug.h b/src/mesa/drivers/dri/r600/r700_debug.h index e810e6da08..c0921bf610 100644 --- a/src/mesa/drivers/dri/r600/r700_debug.h +++ b/src/mesa/drivers/dri/r600/r700_debug.h @@ -27,67 +27,13 @@ #ifndef _R700_DEBUG_H_ #define _R700_DEBUG_H_ - -enum R700_ERROR -{ - ERROR_ASM_VTX_CLAUSE = 0x1000, - ERROR_ASM_UNKOWNCLAUSE = 0x1001, - ERROR_ASM_ALLOCEXPORTCF = 0x1002, - ERROR_ASM_ALLOCVTXCF = 0x1003, - ERROR_ASM_ALLOCTEXCF = 0x1004, - ERROR_ASM_ALLOCALUCF = 0x1005, - ERROR_ASM_UNKNOWNILINST = 0x1006, - ERROR_ASM_SRCARGUMENT = 0x1007, - ERROR_ASM_DSTARGUMENT = 0x1008, - ERROR_ASM_TEXINSTRUCTION = 0x1009, - ERROR_ASM_ALUINSTRUCTION = 0x100A, - ERROR_ASM_INSTDSTTRACK = 0x100B, - ERROR_ASM_TEXDSTBADTYPE = 0x100C, - ERROR_ASM_ALUSRCBADTYPE = 0x100D, - ERROR_ASM_ALUSRCSELECT = 0x100E, - ERROR_ASM_ALUSRCNUMBER = 0x100F, - ERROR_ASM_ALUDSTBADTYPE = 0x1010, - ERROR_ASM_CONSTCHANNEL = 0x1011, - ERROR_ASM_BADSCALARBZ = 0x1012, - ERROR_ASM_BADGPRRESERVE = 0x1013, - ERROR_ASM_BADVECTORBZ = 0x1014, - ERROR_ASM_BADTEXINST = 0x1015, - ERROR_ASM_BADTEXSRC = 0x1016, - ERROR_ASM_BADEXPORTTYPE = 0x1017, - - - TODO_ASM_CONSTTEXADDR = 0x8000, - TODO_ASM_NEEDIMPINST = 0x8001, - TODO_ASM_TXB = 0x8002, - TODO_ASM_TXP = 0x8003 -}; - enum R700_DUMP_TYPE { - DUMP_VERTEX_SHADER = 0x1, - DUMP_PIXEL_SHADER = 0x2, - DUMP_FETCH_SHADER = 0x4, + DUMP_VERTEX_SHADER = 0x1, + DUMP_PIXEL_SHADER = 0x2, + DUMP_FETCH_SHADER = 0x4, }; -#define DEBUGF printf -#define DEBUGP printf - -void NormalizeLogErrorCode(int nError); -/*NormalizeLogErrorCode(nLocalError); */ -void r700_error(int nLocalError, char *fmt, ...); extern void DumpHwBinary(int, void *, int); -#ifdef STANDALONE_COMPILER -#ifdef __cplusplus -extern "C" -{ -#endif //__cplusplus - -void LogString(char* szStr); - -#ifdef __cplusplus -} -#endif //__cplusplus -#endif /*STANDALONE_COMPILER*/ - #endif /*_R700_DEBUG_H_*/ diff --git a/src/mesa/drivers/dri/r600/r700_oglprog.c b/src/mesa/drivers/dri/r600/r700_oglprog.c index c49b90c1cc..3c8c1fd7a3 100644 --- a/src/mesa/drivers/dri/r600/r700_oglprog.c +++ b/src/mesa/drivers/dri/r600/r700_oglprog.c @@ -49,6 +49,9 @@ static struct gl_program *r700NewProgram(GLcontext * ctx, struct r700_vertex_program *vp; struct r700_fragment_program *fp; + radeon_print(RADEON_SHADER, RADEON_VERBOSE, + "%s %u, %u\n", __func__, target, id); + switch (target) { case GL_VERTEX_STATE_PROGRAM_NV: @@ -89,6 +92,9 @@ static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) struct r700_vertex_program * vp; struct r700_fragment_program * fp; + radeon_print(RADEON_SHADER, RADEON_VERBOSE, + "%s %p\n", __func__, prog); + switch (prog->Target) { case GL_VERTEX_STATE_PROGRAM_NV: diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 0b3ceb01ba..4753c757a1 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -327,8 +327,8 @@ static GLuint r700PredictRenderSize(GLcontext* ctx) else dwords += state_size; - if (RADEON_DEBUG & DEBUG_PRIMS) - fprintf(stderr, "%s: total prediction size is %d.\n", __FUNCTION__, dwords); + radeon_print(RADEON_RENDER, RADEON_VERBOSE, + "%s: total prediction size is %d.\n", __FUNCTION__, dwords); return dwords; } @@ -342,8 +342,7 @@ static GLboolean r700RunRender(GLcontext * ctx, struct vertex_buffer *vb = &tnl->vb; struct radeon_renderbuffer *rrb; - if (RADEON_DEBUG & DEBUG_PRIMS) - fprintf(stderr, "%s: cs begin at %d\n", + radeon_print(RADEON_RENDER, RADEON_NORMAL, "%s: cs begin at %d\n", __func__, context->radeon.cmdbuf.cs->cdw); /* always emit CB base to prevent @@ -388,8 +387,7 @@ static GLboolean r700RunRender(GLcontext * ctx, radeonReleaseArrays(ctx, ~0); - if (RADEON_DEBUG & DEBUG_PRIMS) - fprintf(stderr, "%s: cs end at %d\n", + radeon_print(RADEON_RENDER, RADEON_TRACE, "%s: cs end at %d\n", __func__, context->radeon.cmdbuf.cs->cdw); if ( emit_end < context->radeon.cmdbuf.cs->cdw ) diff --git a/src/mesa/drivers/dri/r600/r700_shaderinst.c b/src/mesa/drivers/dri/r600/r700_shaderinst.c index c1bffee91f..f120d9f941 100644 --- a/src/mesa/drivers/dri/r600/r700_shaderinst.c +++ b/src/mesa/drivers/dri/r600/r700_shaderinst.c @@ -27,7 +27,7 @@ #include "main/mtypes.h" -#include "r700_debug.h" +#include "radeon_debug.h" #include "r700_shaderinst.h" void Init_R700ControlFlowGenericClause(R700ControlFlowGenericClause* pInst) @@ -208,16 +208,16 @@ unsigned int GetCFMaxInstructions(ShaderInstType instType) GLboolean LinkVertexInstruction(R700ControlFlowGenericClause *pCFGeneric, R700VertexInstruction *pVTXInstruction) { - if (pCFGeneric->m_pLinkedTEXInstruction != 0) - { - r700_error(ERROR_ASM_VTX_CLAUSE, "This instruction is already linked to a texture instruction"); - return GL_FALSE; + if (pCFGeneric->m_pLinkedTEXInstruction != 0) + { + radeon_error("This instruction is already linked to a texture instruction.\n"); + return GL_FALSE; } pCFGeneric->m_pLinkedVTXInstruction = pVTXInstruction; - pVTXInstruction->m_pLinkedGenericClause = pCFGeneric; + pVTXInstruction->m_pLinkedGenericClause = pCFGeneric; - return GL_TRUE; + return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index 86a67ab766..d107f99e7b 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -38,6 +38,7 @@ #include "shader/prog_parameter.h" #include "shader/prog_statevars.h" +#include "radeon_debug.h" #include "r600_context.h" #include "r600_cmdbuf.h" @@ -174,7 +175,7 @@ void Map_Vertex_Program(struct r700_vertex_program *vp, // Create VFETCH instructions for inputs if (GL_TRUE != Process_Vertex_Program_Vfetch_Instructions(vp, mesa_vp) ) { - r700_error(ERROR_ASM_VTX_CLAUSE, "Calling Process_Vertex_Program_Vfetch_Instructions return error. \n"); + radeon_error("Calling Process_Vertex_Program_Vfetch_Instructions return error. \n"); return; //error } -- cgit v1.2.3 From d028cf9313aa0d2c43566acec4bbf4f6167f060e Mon Sep 17 00:00:00 2001 From: Pauli Nieminen Date: Mon, 31 Aug 2009 20:44:11 +0300 Subject: r600: Add more trace debug output to rendering pipeline. --- src/mesa/drivers/dri/r600/r700_render.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 4753c757a1..e1bbbfef35 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -69,6 +69,7 @@ GLboolean r700SyncSurf(context_t *context, void r700WaitForIdle(context_t *context) { BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__); BEGIN_BATCH_NO_AUTOSTATE(3); R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); @@ -82,6 +83,7 @@ void r700WaitForIdle(context_t *context) void r700WaitForIdleClean(context_t *context) { BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__); BEGIN_BATCH_NO_AUTOSTATE(5); R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); @@ -98,6 +100,7 @@ void r700WaitForIdleClean(context_t *context) void r700Start3D(context_t *context) { BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__); if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) { BEGIN_BATCH_NO_AUTOSTATE(2); @@ -124,6 +127,7 @@ GLboolean r700SyncSurf(context_t *context, uint32_t sync_type) { BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_RENDER | RADEON_STATE, RADEON_TRACE, "%s\n", __func__); uint32_t cp_coher_size; if (!pbo) @@ -257,6 +261,10 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim type = r700PrimitiveType(prim); num_indices = r700NumVerts(end - start, prim); + radeon_print(RADEON_RENDER, RADEON_TRACE, + "%s type %x num_indices %d\n", + __func__, type, num_indices); + if (type < 0 || num_indices <= 0) return; @@ -364,6 +372,7 @@ static GLboolean r700RunRender(GLcontext * ctx, radeonEmitState(radeon); + radeon_debug_add_indent(); /* richard test code */ for (i = 0; i < vb->PrimitiveCount; i++) { GLuint prim = _tnl_translate_prim(&vb->Primitive[i]); @@ -371,6 +380,7 @@ static GLboolean r700RunRender(GLcontext * ctx, GLuint end = vb->Primitive[i].start + vb->Primitive[i].count; r700RunRenderPrimitive(ctx, start, end, prim); } + radeon_debug_remove_indent(); /* Flush render op cached for last several quads. */ r700WaitForIdleClean(context); -- cgit v1.2.3 From b13a553dd419cc6997725d4bce956daa7eb64806 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 4 Sep 2009 14:03:51 -0400 Subject: r600: fix Elts handling Patch from taiu on IRC. fixes bug 23585 --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 12 ++++++++++-- src/mesa/drivers/dri/r600/r700_render.c | 7 ++++++- 2 files changed, 16 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 65930ff589..3cfe03a45f 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -192,9 +192,9 @@ static int r600_cs_begin(struct radeon_cs *cs, if (cs->cdw + ndw > cs->ndw) { uint32_t tmp, *ptr; - int num = (ndw > 0x3FF) ? ndw : 0x3FF; + int num = (ndw > 0x400) ? ndw : 0x400; - tmp = (cs->cdw + 1 + num) & (~num); + tmp = (cs->cdw + num + 0x3FF) & (~0x3FF); ptr = (uint32_t*)realloc(cs->packets, 4 * tmp); if (ptr == NULL) { return -ENOMEM; @@ -229,6 +229,14 @@ static int r600_cs_end(struct radeon_cs *cs, return -EPIPE; } + if (cs->cdw > cs->ndw) { + fprintf(stderr, "CS section overflow at (%s,%s,%d) cdw %d ndw %d\n", + cs->section_file, cs->section_func, cs->section_line,cs->cdw,cs->ndw); + fprintf(stderr, "CS section end at (%s,%s,%d)\n", + file, func, line); + assert(0); + } + return 0; } diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index e1bbbfef35..3566bf3ca7 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -257,6 +257,8 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim uint32_t vgt_index_type = 0; uint32_t vgt_primitive_type = 0; uint32_t vgt_num_indices = 0; + TNLcontext *tnl = TNL_CONTEXT(ctx); + struct vertex_buffer *vb = &tnl->vb; type = r700PrimitiveType(prim); num_indices = r700NumVerts(end - start, prim); @@ -300,7 +302,10 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim R600_OUT_BATCH(vgt_draw_initiator); for (i = start; i < (start + num_indices); i++) { - R600_OUT_BATCH(i); + if(vb->Elts) + R600_OUT_BATCH(vb->Elts[i]); + else + R600_OUT_BATCH(i); } END_BATCH(); COMMIT_BATCH(); -- cgit v1.2.3 From 4108ed7e806e4ad1b2706a107a10f4eebd255ddc Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Fri, 11 Sep 2009 10:59:05 -0400 Subject: r600: enable caching of vertex programs --- src/mesa/drivers/dri/r600/r600_context.h | 3 + src/mesa/drivers/dri/r600/r700_chip.c | 10 ++- src/mesa/drivers/dri/r600/r700_oglprog.c | 36 ++++++----- src/mesa/drivers/dri/r600/r700_render.c | 9 +-- src/mesa/drivers/dri/r600/r700_vertprog.c | 103 ++++++++++++++++++++---------- src/mesa/drivers/dri/r600/r700_vertprog.h | 11 +++- 6 files changed, 110 insertions(+), 62 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_render.c') diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index 8ae05a301c..c59df7505a 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -51,6 +51,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r700_chip.h" #include "r600_tex.h" #include "r700_oglprog.h" +#include "r700_vertprog.h" struct r600_context; typedef struct r600_context context_t; @@ -155,6 +156,8 @@ struct r600_context { struct r600_hw_state atoms; + struct r700_vertex_program *selected_vp; + /* Vertex buffers */ GLvector4f dummy_attrib[_TNL_ATTRIB_MAX]; diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 312cacffda..1b56059197 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -211,8 +211,7 @@ static void r700SetupVTXConstants(GLcontext * ctx, void r700SetupStreams(GLcontext *ctx) { context_t *context = R700_CONTEXT(ctx); - struct r700_vertex_program *vpc - = (struct r700_vertex_program *)ctx->VertexProgram._Current; + struct r700_vertex_program *vp = context->selected_vp; TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; unsigned int i, j = 0; @@ -221,7 +220,7 @@ void r700SetupStreams(GLcontext *ctx) R600_STATECHANGE(context, vtx); for(i=0; imesa_program.Base.InputsRead & (1 << i)) { + if(vp->mesa_program->Base.InputsRead & (1 << i)) { rcommon_emit_vector(ctx, &context->radeon.tcl.aos[j], vb->AttribPtr[i]->data, @@ -237,8 +236,7 @@ void r700SetupStreams(GLcontext *ctx) static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); - struct r700_vertex_program *vpc - = (struct r700_vertex_program *)ctx->VertexProgram._Current; + struct r700_vertex_program *vp = context->selected_vp; unsigned int i, j = 0; BATCH_LOCALS(&context->radeon); radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); @@ -258,7 +256,7 @@ static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); for(i=0; imesa_program.Base.InputsRead & (1 << i)) { + if(vp->mesa_program->Base.InputsRead & (1 << i)) { /* currently aos are packed */ r700SetupVTXConstants(ctx, i, diff --git a/src/mesa/drivers/dri/r600/r700_oglprog.c b/src/mesa/drivers/dri/r600/r700_oglprog.c index 3c8c1fd7a3..5290ef31be 100644 --- a/src/mesa/drivers/dri/r600/r700_oglprog.c +++ b/src/mesa/drivers/dri/r600/r700_oglprog.c @@ -46,7 +46,7 @@ static struct gl_program *r700NewProgram(GLcontext * ctx, { struct gl_program *pProgram = NULL; - struct r700_vertex_program *vp; + struct r700_vertex_program_cont *vpc; struct r700_fragment_program *fp; radeon_print(RADEON_SHADER, RADEON_VERBOSE, @@ -56,16 +56,11 @@ static struct gl_program *r700NewProgram(GLcontext * ctx, { case GL_VERTEX_STATE_PROGRAM_NV: case GL_VERTEX_PROGRAM_ARB: - vp = CALLOC_STRUCT(r700_vertex_program); + vpc = CALLOC_STRUCT(r700_vertex_program_cont); pProgram = _mesa_init_vertex_program(ctx, - &vp->mesa_program, + &vpc->mesa_program, target, id); - vp->translated = GL_FALSE; - vp->loaded = GL_FALSE; - - vp->shaderbo = NULL; - break; case GL_FRAGMENT_PROGRAM_NV: case GL_FRAGMENT_PROGRAM_ARB: @@ -89,7 +84,8 @@ static struct gl_program *r700NewProgram(GLcontext * ctx, static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) { - struct r700_vertex_program * vp; + struct r700_vertex_program_cont * vpc; + struct r700_vertex_program *vp, *tmp; struct r700_fragment_program * fp; radeon_print(RADEON_SHADER, RADEON_VERBOSE, @@ -99,14 +95,20 @@ static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) { case GL_VERTEX_STATE_PROGRAM_NV: case GL_VERTEX_PROGRAM_ARB: - vp = (struct r700_vertex_program*)prog; - /* Release DMA region */ - - r600DeleteShader(ctx, vp->shaderbo); - - /* Clean up */ - Clean_Up_Assembler(&(vp->r700AsmCode)); - Clean_Up_Shader(&(vp->r700Shader)); + vpc = (struct r700_vertex_program_cont*)prog; + vp = vpc->progs; + while (vp) { + tmp = vp->next; + /* Release DMA region */ + + r600DeleteShader(ctx, vp->shaderbo); + + /* Clean up */ + Clean_Up_Assembler(&(vp->r700AsmCode)); + Clean_Up_Shader(&(vp->r700Shader)); + _mesa_free(vp); + vp = tmp; + } break; case GL_FRAGMENT_PROGRAM_NV: case GL_FRAGMENT_PROGRAM_ARB: diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 3566bf3ca7..b1c3648ca5 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -319,14 +319,13 @@ static GLuint r700PredictRenderSize(GLcontext* ctx) { context_t *context = R700_CONTEXT(ctx); TNLcontext *tnl = TNL_CONTEXT(ctx); - struct r700_vertex_program *vpc - = (struct r700_vertex_program *)ctx->VertexProgram._Current; + struct r700_vertex_program *vp = context->selected_vp; struct vertex_buffer *vb = &tnl->vb; GLboolean flushed; GLuint dwords, i; GLuint state_size; /* pre calculate aos count so state prediction works */ - context->radeon.tcl.aos_count = _mesa_bitcount(vpc->mesa_program.Base.InputsRead); + context->radeon.tcl.aos_count = _mesa_bitcount(vp->mesa_program->Base.InputsRead); dwords = PRE_EMIT_STATE_BUFSZ; for (i = 0; i < vb->PrimitiveCount; i++) @@ -365,7 +364,6 @@ static GLboolean r700RunRender(GLcontext * ctx, /* mark vtx as dirty since it changes per-draw */ R600_STATECHANGE(context, vtx); - r700UpdateShaders(ctx); r700SetScissor(context); r700SetupVertexProgram(ctx); r700SetupFragmentProgram(ctx); @@ -427,7 +425,10 @@ static GLboolean r700RunTCLRender(GLcontext * ctx, /*----------------------*/ /* TODO : sw fallback */ + /* Need shader bo's setup before bo check */ + r700UpdateShaders(ctx); /** + * Ensure all enabled and complete textures are uploaded along with any buffers being used. */ if(!r600ValidateBuffers(ctx)) diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index d107f99e7b..8c2b0071df 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -35,6 +35,7 @@ #include "main/mtypes.h" #include "tnl/t_context.h" +#include "shader/program.h" #include "shader/prog_parameter.h" #include "shader/prog_statevars.h" @@ -258,28 +259,54 @@ GLboolean Find_Instruction_Dependencies_vp(struct r700_vertex_program *vp, return GL_TRUE; } -GLboolean r700TranslateVertexShader(struct r700_vertex_program *vp, - struct gl_vertex_program *mesa_vp) +struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, + struct gl_vertex_program *mesa_vp) { + context_t *context = R700_CONTEXT(ctx); + struct r700_vertex_program *vp; + TNLcontext *tnl = TNL_CONTEXT(ctx); + struct vertex_buffer *vb = &tnl->vb; + unsigned int unBit; + unsigned int i; + + vp = _mesa_calloc(sizeof(*vp)); + vp->mesa_program = (struct gl_vertex_program *)_mesa_clone_program(ctx, &mesa_vp->Base); + + for(i=0; imesa_program->Base.InputsRead & unBit) /* ctx->Array.ArrayObj->xxxxxxx */ + { + vp->aos_desc[i].size = vb->AttribPtr[i]->size; + vp->aos_desc[i].stride = vb->AttribPtr[i]->size * sizeof(GL_FLOAT);/* when emit array, data is packed. vb->AttribPtr[i]->stride;*/ + vp->aos_desc[i].type = GL_FLOAT; + } + } + + if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) + { + vp->r700AsmCode.bR6xx = 1; + } + //Init_Program Init_r700_AssemblerBase(SPT_VP, &(vp->r700AsmCode), &(vp->r700Shader) ); Map_Vertex_Program( vp, mesa_vp ); if(GL_FALSE == Find_Instruction_Dependencies_vp(vp, mesa_vp)) { - return GL_FALSE; + return NULL; } if(GL_FALSE == AssembleInstr(mesa_vp->Base.NumInstructions, &(mesa_vp->Base.Instructions[0]), &(vp->r700AsmCode)) ) { - return GL_FALSE; + return NULL; } if(GL_FALSE == Process_Vertex_Exports(&(vp->r700AsmCode), mesa_vp->Base.OutputsWritten) ) { - return GL_FALSE; + return NULL; } vp->r700Shader.nRegs = (vp->r700AsmCode.number_used_registers == 0) ? 0 @@ -289,72 +316,82 @@ GLboolean r700TranslateVertexShader(struct r700_vertex_program *vp, vp->translated = GL_TRUE; - return GL_TRUE; + return vp; } void r700SelectVertexShader(GLcontext *ctx) { context_t *context = R700_CONTEXT(ctx); - struct r700_vertex_program *vpc - = (struct r700_vertex_program *)ctx->VertexProgram._Current; + struct r700_vertex_program_cont *vpc; + struct r700_vertex_program *vp; TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; unsigned int unBit; unsigned int i; + GLboolean match; + vpc = (struct r700_vertex_program_cont *)ctx->VertexProgram._Current; + +#if 0 if (context->radeon.NewGLState & (_NEW_PROGRAM_CONSTANTS|_NEW_PROGRAM)) { vpc->needUpdateVF = 1; } +#endif - if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) + for (vp = vpc->progs; vp; vp = vp->next) { - vpc->r700AsmCode.bR6xx = 1; - } - + match = GL_TRUE; for(i=0; imesa_program.Base.InputsRead & unBit) /* ctx->Array.ArrayObj->xxxxxxx */ + if(vpc->mesa_program.Base.InputsRead & unBit) { - vpc->aos_desc[i].size = vb->AttribPtr[i]->size; - vpc->aos_desc[i].stride = vb->AttribPtr[i]->size * sizeof(GL_FLOAT);/* when emit array, data is packed. vb->AttribPtr[i]->stride;*/ - vpc->aos_desc[i].type = GL_FLOAT; + if (vp->aos_desc[i].size != vb->AttribPtr[i]->size) + match = GL_FALSE; + break; } } - - if(GL_FALSE == vpc->translated) { - r700TranslateVertexShader(vpc, &(vpc->mesa_program) ); + if (match) + { + context->selected_vp = vp; + return; } + } + + vp = r700TranslateVertexShader(ctx, &(vpc->mesa_program) ); + if(!vp) + { + radeon_error("Failed to translate vertex shader. \n"); + return; + } + vp->next = vpc->progs; + vpc->progs = vp; + context->selected_vp = vp; + return; } void * r700GetActiveVpShaderBo(GLcontext * ctx) { - struct r700_vertex_program *vp - = (struct r700_vertex_program *)ctx->VertexProgram._Current; + context_t *context = R700_CONTEXT(ctx); + struct r700_vertex_program *vp = context->selected_vp;; - return vp->shaderbo; + if (vp) + return vp->shaderbo; + else + return NULL; } GLboolean r700SetupVertexProgram(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - struct r700_vertex_program *vp - = (struct r700_vertex_program *)ctx->VertexProgram._Current; + struct r700_vertex_program *vp = context->selected_vp; struct gl_program_parameter_list *paramList; unsigned int unNumParamData; unsigned int ui; - if (vp->needUpdateVF) - { - vp->loaded = GL_FALSE; - vp->r700Shader.bNeedsAssembly = GL_TRUE; - Process_Vertex_Program_Vfetch_Instructions(vp, &(vp->mesa_program)); - r600DeleteShader(ctx, vp->shaderbo); - } - if(GL_FALSE == vp->loaded) { if(vp->r700Shader.bNeedsAssembly == GL_TRUE) @@ -410,7 +447,7 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) */ /* sent out shader constants. */ - paramList = vp->mesa_program.Base.Parameters; + paramList = vp->mesa_program->Base.Parameters; if(NULL != paramList) { _mesa_load_state_parameters(ctx, paramList); diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.h b/src/mesa/drivers/dri/r600/r700_vertprog.h index e2e65021fd..c48764c43b 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.h +++ b/src/mesa/drivers/dri/r600/r700_vertprog.h @@ -43,7 +43,7 @@ typedef struct ArrayDesc //TEMP struct r700_vertex_program { - struct gl_vertex_program mesa_program; /* Must be first */ + struct gl_vertex_program *mesa_program; /* Must be first */ struct r700_vertex_program *next; @@ -59,6 +59,13 @@ struct r700_vertex_program ArrayDesc aos_desc[VERT_ATTRIB_MAX]; }; +struct r700_vertex_program_cont +{ + struct gl_vertex_program mesa_program; + + struct r700_vertex_program *progs; +}; + //Internal unsigned int Map_Vertex_Output(r700_AssemblerBase *pAsm, struct gl_vertex_program *mesa_vp, @@ -74,7 +81,7 @@ void Map_Vertex_Program(struct r700_vertex_program *vp, GLboolean Find_Instruction_Dependencies_vp(struct r700_vertex_program *vp, struct gl_vertex_program *mesa_vp); -GLboolean r700TranslateVertexShader(struct r700_vertex_program *vp, +struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, struct gl_vertex_program *mesa_vp); /* Interface */ -- cgit v1.2.3