From 17813931db4cc114262d306f4c1484cd353a13f9 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Sat, 22 Aug 2009 11:44:05 -0400 Subject: r600: add support for RS880 --- src/mesa/drivers/dri/r600/r700_state.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mesa/drivers/dri/r600/r700_state.c') diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 6b44cc0ceb..97c7d7c385 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -1579,6 +1579,7 @@ static void r700InitSQConfig(GLcontext * ctx) case CHIP_FAMILY_RV610: case CHIP_FAMILY_RV620: case CHIP_FAMILY_RS780: + case CHIP_FAMILY_RS880: default: num_ps_gprs = 84; num_vs_gprs = 36; @@ -1661,6 +1662,7 @@ static void r700InitSQConfig(GLcontext * ctx) if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) || (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) || (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) || + (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) || (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710)) CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit); else -- cgit v1.2.3 From 180c304943537210b2f6459ea21e9bff85f9827e Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Sat, 22 Aug 2009 15:03:41 -0400 Subject: r600: move full state to radeon state atoms --- src/mesa/drivers/dri/r600/r600_context.c | 2 +- src/mesa/drivers/dri/r600/r600_context.h | 26 ++-- src/mesa/drivers/dri/r600/r600_texstate.c | 2 + src/mesa/drivers/dri/r600/r700_chip.c | 242 +++++++++++++++++++++--------- src/mesa/drivers/dri/r600/r700_chip.h | 5 + src/mesa/drivers/dri/r600/r700_fragprog.c | 74 ++++----- src/mesa/drivers/dri/r600/r700_render.c | 45 +----- src/mesa/drivers/dri/r600/r700_state.c | 2 - src/mesa/drivers/dri/r600/r700_vertprog.c | 56 ++++--- 9 files changed, 262 insertions(+), 192 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_state.c') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 4489064c0d..6a066f3510 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -185,7 +185,7 @@ static void r600_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmes static void r600_vtbl_pre_emit_atoms(radeonContextPtr radeon) { - /* to be enabled */ + r700Start3D((context_t *)radeon); } static void r600_fallback(GLcontext *ctx, GLuint bit, GLboolean mode) diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index a9b080baa3..48be89b638 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -55,10 +55,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. struct r600_context; typedef struct r600_context context_t; -extern GLboolean r700SendPSState(context_t *context); -extern GLboolean r700SendVSState(context_t *context); -extern GLboolean r700SendFSState(context_t *context); - #include "main/mm.h" /************ DMA BUFFERS **************/ @@ -126,6 +122,16 @@ struct r600_hw_state { struct radeon_state_atom vgt; struct radeon_state_atom spi; struct radeon_state_atom vpt; + + struct radeon_state_atom fs; + struct radeon_state_atom vs; + struct radeon_state_atom ps; + + struct radeon_state_atom vs_consts; + struct radeon_state_atom ps_consts; + + struct radeon_state_atom vtx; + struct radeon_state_atom tx; }; /** @@ -168,22 +174,14 @@ do { \ r600->radeon.hw.is_dirty = GL_TRUE; \ } while(0) -extern GLboolean r700SendTextureState(context_t *context); - extern GLboolean r700SyncSurf(context_t *context, struct radeon_bo *pbo, uint32_t read_domain, uint32_t write_domain, uint32_t sync_type); -extern int r700SetupStreams(GLcontext * ctx); -extern void r700SetupVTXConstants(GLcontext * ctx, - unsigned int nStreamID, - void * pAos, - unsigned int size, /* number of elements in vector */ - unsigned int stride, - unsigned int Count); /* number of vectors in stream */ - +extern void r700SetupStreams(GLcontext * ctx); +extern void r700Start3D(context_t *context); extern void r600InitAtoms(context_t *context); #define RADEON_D_CAPTURE 0 diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 1057d7d8bb..7486d73760 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -60,6 +60,8 @@ void r600UpdateTextureState(GLcontext * ctx) struct radeon_tex_obj *t; GLuint unit; + R600_STATECHANGE(context, tx); + for (unit = 0; unit < R700_MAX_TEXTURE_UNITS; unit++) { texUnit = &ctx->Texture.Unit[unit]; t = radeon_tex_obj(ctx->Texture.Unit[unit]._Current); diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 550fb73d53..b7c2be16ff 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -41,11 +41,12 @@ #include "radeon_mipmap_tree.h" -GLboolean r700SendTextureState(context_t *context) +static void r700SendTextureState(GLcontext *ctx, struct radeon_state_atom *atom) { - unsigned int i; + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); struct radeon_bo *bo = NULL; + unsigned int i; BATCH_LOCALS(&context->radeon); for (i=0; iradeon); - - struct r700_vertex_program *vpc + struct r700_vertex_program *vpc = (struct r700_vertex_program *)ctx->VertexProgram._Current; - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *vb = &tnl->vb; + struct vertex_buffer *vb = &tnl->vb; + unsigned int i, j = 0; + + R600_STATECHANGE(context, vtx); + + for(i=0; imesa_program.Base.InputsRead & (1 << i)) { + rcommon_emit_vector(ctx, + &context->radeon.tcl.aos[j], + vb->AttribPtr[i]->data, + vb->AttribPtr[i]->size, + vb->AttribPtr[i]->stride, + vb->Count); + j++; + } + } + context->radeon.tcl.aos_count = j; +} - unsigned int unBit; +static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + struct r700_vertex_program *vpc + = (struct r700_vertex_program *)ctx->VertexProgram._Current; unsigned int i, j = 0; + BATCH_LOCALS(&context->radeon); BEGIN_BATCH_NO_AUTOSTATE(6); R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1)); @@ -195,31 +214,18 @@ int r700SetupStreams(GLcontext * ctx) END_BATCH(); COMMIT_BATCH(); - for(i=0; imesa_program.Base.InputsRead & unBit) - { - rcommon_emit_vector(ctx, - &context->radeon.tcl.aos[j], - vb->AttribPtr[i]->data, - vb->AttribPtr[i]->size, - vb->AttribPtr[i]->stride, - vb->Count); - - /* currently aos are packed */ - r700SetupVTXConstants(ctx, - i, - (void*)(&context->radeon.tcl.aos[j]), - (unsigned int)context->radeon.tcl.aos[j].components, - (unsigned int)context->radeon.tcl.aos[j].stride * 4, - (unsigned int)context->radeon.tcl.aos[j].count); - j++; - } - } - context->radeon.tcl.aos_count = j; - - return R600_FALLBACK_NONE; + for(i=0; imesa_program.Base.InputsRead & (1 << i)) { + /* currently aos are packed */ + r700SetupVTXConstants(ctx, + i, + (void*)(&context->radeon.tcl.aos[j]), + (unsigned int)context->radeon.tcl.aos[j].components, + (unsigned int)context->radeon.tcl.aos[j].stride * 4, + (unsigned int)context->radeon.tcl.aos[j].count); + j++; + } + } } static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *atom) @@ -310,8 +316,9 @@ static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom * } -GLboolean r700SendPSState(context_t *context) +static void r700SendPSState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; BATCH_LOCALS(&context->radeon); @@ -319,7 +326,7 @@ GLboolean r700SendPSState(context_t *context) pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context)); if (!pbo) - return GL_FALSE; + return; r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); @@ -340,13 +347,11 @@ GLboolean r700SendPSState(context_t *context) COMMIT_BATCH(); - r700->ps.dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendVSState(context_t *context) +static void r700SendVSState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; BATCH_LOCALS(&context->radeon); @@ -354,7 +359,7 @@ GLboolean r700SendVSState(context_t *context) pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); if (!pbo) - return GL_FALSE; + return; r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); @@ -373,14 +378,11 @@ GLboolean r700SendVSState(context_t *context) END_BATCH(); COMMIT_BATCH(); - - r700->vs.dirty = GL_FALSE; - - return GL_TRUE; } -GLboolean r700SendFSState(context_t *context) +static void r700SendFSState(GLcontext *ctx, struct radeon_state_atom *atom) { + context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; BATCH_LOCALS(&context->radeon); @@ -397,7 +399,7 @@ GLboolean r700SendFSState(context_t *context) /* XXX */ if (!pbo) - return GL_FALSE; + return; r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); @@ -417,9 +419,6 @@ GLboolean r700SendFSState(context_t *context) COMMIT_BATCH(); - r700->fs.dirty = GL_FALSE; - - return GL_TRUE; } static void r700SendViewportState(GLcontext *ctx, struct radeon_state_atom *atom) @@ -831,18 +830,103 @@ static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); } +static void r700SendPSConsts(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + int i; + BATCH_LOCALS(&context->radeon); + + if (r700->ps.num_consts == 0) + return; + + BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->ps.num_consts * 4)); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->ps.num_consts * 4))); + /* assembler map const from very beginning. */ + R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4); + for (i = 0; i < r700->ps.num_consts; i++) { + R600_OUT_BATCH(r700->ps.consts[i][0].u32All); + R600_OUT_BATCH(r700->ps.consts[i][1].u32All); + R600_OUT_BATCH(r700->ps.consts[i][2].u32All); + R600_OUT_BATCH(r700->ps.consts[i][3].u32All); + } + END_BATCH(); + COMMIT_BATCH(); +} + +static void r700SendVSConsts(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + int i; + BATCH_LOCALS(&context->radeon); + + if (r700->vs.num_consts == 0) + return; + + BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->vs.num_consts * 4)); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->vs.num_consts * 4))); + /* assembler map const from very beginning. */ + R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4); + for (i = 0; i < r700->vs.num_consts; i++) { + R600_OUT_BATCH(r700->vs.consts[i][0].u32All); + R600_OUT_BATCH(r700->vs.consts[i][1].u32All); + R600_OUT_BATCH(r700->vs.consts[i][2].u32All); + R600_OUT_BATCH(r700->vs.consts[i][3].u32All); + } + END_BATCH(); + COMMIT_BATCH(); +} + static int check_always(GLcontext *ctx, struct radeon_state_atom *atom) { return atom->cmd_size; } -#define ALLOC_STATE( ATOM, SZ, EMIT ) \ +static int check_vtx(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + + return context->radeon.tcl.aos_count * 18; +} + +static int check_tx(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + unsigned int i, count = 0; + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + + for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) { + radeonTexObj *t = r700->textures[i]; + if (t) + count++; + } + return count * 31; +} + +static int check_ps_consts(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + + return 2 + (r700->ps.num_consts * 4); +} + +static int check_vs_consts(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + + return 2 + (r700->vs.num_consts * 4); +} + +#define ALLOC_STATE( ATOM, CHK, SZ, EMIT ) \ do { \ context->atoms.ATOM.cmd_size = (SZ); \ context->atoms.ATOM.cmd = NULL; \ context->atoms.ATOM.name = #ATOM; \ context->atoms.ATOM.idx = 0; \ - context->atoms.ATOM.check = check_always; \ + context->atoms.ATOM.check = check_##CHK; \ context->atoms.ATOM.dirty = GL_FALSE; \ context->atoms.ATOM.emit = (EMIT); \ context->radeon.hw.max_state_size += (SZ); \ @@ -851,26 +935,36 @@ do { \ void r600InitAtoms(context_t *context) { - /* FIXME: rough estimate for "large" const and shader state */ - context->radeon.hw.max_state_size = 7500; + context->radeon.hw.max_state_size = 10 + 5 + 14; /* start 3d, idle, cb/db flush */ /* Setup the atom linked list */ make_empty_list(&context->radeon.hw.atomlist); context->radeon.hw.atomlist.name = "atom-list"; - ALLOC_STATE(sq, 34, r700SendSQConfig); - ALLOC_STATE(db, 27, r700SendDBState); - ALLOC_STATE(db_target, 19, r700SendDepthTargetState); - ALLOC_STATE(sc, 47, r700SendSCState); - ALLOC_STATE(cl, 18, r700SendCLState); - ALLOC_STATE(ucp, 36, r700SendUCPState); - ALLOC_STATE(su, 19, r700SendSUState); - ALLOC_STATE(cb, 39, r700SendCBState); - ALLOC_STATE(cb_target, 32, r700SendRenderTargetState); - ALLOC_STATE(sx, 9, r700SendSXState); - ALLOC_STATE(vgt, 41, r700SendVGTState); - ALLOC_STATE(spi, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState); - ALLOC_STATE(vpt, 16, r700SendViewportState); + ALLOC_STATE(sq, always, 34, r700SendSQConfig); + + ALLOC_STATE(db, always, 27, r700SendDBState); + ALLOC_STATE(db_target, always, 19, r700SendDepthTargetState); + ALLOC_STATE(sc, always, 47, r700SendSCState); + ALLOC_STATE(cl, always, 18, r700SendCLState); + ALLOC_STATE(ucp, always, 36, r700SendUCPState); + ALLOC_STATE(su, always, 19, r700SendSUState); + ALLOC_STATE(cb, always, 39, r700SendCBState); + ALLOC_STATE(cb_target, always, 32, r700SendRenderTargetState); + ALLOC_STATE(sx, always, 9, r700SendSXState); + ALLOC_STATE(vgt, always, 41, r700SendVGTState); + ALLOC_STATE(spi, always, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState); + ALLOC_STATE(vpt, always, 16, r700SendViewportState); + + ALLOC_STATE(fs, always, 18, r700SendFSState); + ALLOC_STATE(vs, always, 18, r700SendVSState); + ALLOC_STATE(ps, always, 21, r700SendPSState); + + ALLOC_STATE(vs_consts, vs_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendVSConsts); + ALLOC_STATE(ps_consts, ps_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendPSConsts); + + ALLOC_STATE(vtx, vtx, (VERT_ATTRIB_MAX * 18), r700SendVTXState); + ALLOC_STATE(tx, tx, (R700_TEXTURE_NUMBERUNITS * 31), r700SendTextureState); context->radeon.hw.is_dirty = GL_TRUE; context->radeon.hw.all_dirty = GL_TRUE; diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h index c0ec4b0dd5..ae249e15fd 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.h +++ b/src/mesa/drivers/dri/r600/r700_chip.h @@ -46,6 +46,7 @@ #define R700_MAX_VIEWPORTS 16 #define R700_MAX_SHADER_EXPORTS 32 #define R700_MAX_UCP 6 +#define R700_MAX_DX9_CONSTS 256 /* Enum not show in r600_*.h */ @@ -224,6 +225,8 @@ typedef struct _PS_STATE_STRUCT union UINT_FLOAT SQ_PGM_EXPORTS_PS ; /* 0xA215 */ union UINT_FLOAT SQ_PGM_CF_OFFSET_PS ; /* 0xA233 */ GLboolean dirty; + int num_consts; + union UINT_FLOAT consts[R700_MAX_DX9_CONSTS][4]; } PS_STATE_STRUCT; typedef struct _VS_STATE_STRUCT @@ -232,6 +235,8 @@ typedef struct _VS_STATE_STRUCT union UINT_FLOAT SQ_PGM_RESOURCES_VS ; /* 0xA21A */ union UINT_FLOAT SQ_PGM_CF_OFFSET_VS ; /* 0xA234 */ GLboolean dirty; + int num_consts; + union UINT_FLOAT consts[R700_MAX_DX9_CONSTS][4]; } VS_STATE_STRUCT; typedef struct _GS_STATE_STRUCT diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index 394482594e..098b420dfc 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -270,7 +270,6 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - BATCH_LOCALS(&context->radeon); struct r700_fragment_program *fp = (struct r700_fragment_program *) (ctx->FragmentProgram._Current); r700_AssemblerBase *pAsm = &(fp->r700AsmCode); @@ -280,6 +279,7 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) unsigned int ui, i; unsigned int unNumOfReg; unsigned int unBit; + GLuint exportCount; if(GL_FALSE == fp->loaded) { @@ -305,10 +305,15 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) (context->chipobj.MemUse)(context, fp->shadercode.buf->id); */ - R600_STATECHANGE(context, spi); + R600_STATECHANGE(context, ps); + + r700->ps.SQ_PGM_RESOURCES_PS.u32All = 0; + SETbit(r700->ps.SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); r700->ps.SQ_PGM_START_PS.u32All = 0; /* set from buffer obj */ + R600_STATECHANGE(context, spi); + unNumOfReg = fp->r700Shader.nRegs + 1; ui = (r700->SPI_PS_IN_CONTROL_0.u32All & NUM_INTERP_mask) / (1 << NUM_INTERP_shift); @@ -325,8 +330,8 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) ui = (unNumOfReg < ui) ? ui : unNumOfReg; - SETfield(r700->ps.SQ_PGM_RESOURCES_PS.u32All, ui, NUM_GPRS_shift, NUM_GPRS_mask); - + SETfield(r700->ps.SQ_PGM_RESOURCES_PS.u32All, ui, NUM_GPRS_shift, NUM_GPRS_mask); + CLEARbit(r700->ps.SQ_PGM_RESOURCES_PS.u32All, UNCACHED_FIRST_INST_bit); if(fp->r700Shader.uStackSize) /* we don't use branch for now, it should be zero. */ @@ -338,6 +343,8 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) SETfield(r700->ps.SQ_PGM_EXPORTS_PS.u32All, fp->r700Shader.exportMode, EXPORT_MODE_shift, EXPORT_MODE_mask); + R600_STATECHANGE(context, db); + if(fp->r700Shader.killIsUsed) { SETbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit); @@ -349,42 +356,13 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) if(fp->r700Shader.depthIsExported) { - SETbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit); + SETbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit); } else { CLEARbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit); } - /* sent out shader constants. */ - paramList = fp->mesa_program.Base.Parameters; - - if(NULL != paramList) - { - _mesa_load_state_parameters(ctx, paramList); - - unNumParamData = paramList->NumParameters * 4; - - BEGIN_BATCH_NO_AUTOSTATE(2 + unNumParamData); - - R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData)); - - /* assembler map const from very beginning. */ - R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4); - - unNumParamData = paramList->NumParameters; - - for(ui=0; uiParameterValues[ui][0]))); - R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1]))); - R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2]))); - R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3]))); - } - END_BATCH(); - COMMIT_BATCH(); - } - // emit ps input map unBit = 1 << FRAG_ATTRIB_WPOS; if(mesa_fp->Base.InputsRead & unBit) @@ -451,6 +429,34 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) } } + R600_STATECHANGE(context, cb); + exportCount = (r700->ps.SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift); + r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1; + + /* sent out shader constants. */ + paramList = fp->mesa_program.Base.Parameters; + + if(NULL != paramList) { + _mesa_load_state_parameters(ctx, paramList); + + if (paramList->NumParameters > R700_MAX_DX9_CONSTS) + return GL_FALSE; + + R600_STATECHANGE(context, ps_consts); + + r700->ps.num_consts = paramList->NumParameters; + + unNumParamData = paramList->NumParameters; + + for(ui=0; uips.consts[ui][0].f32All = paramList->ParameterValues[ui][0]; + r700->ps.consts[ui][1].f32All = paramList->ParameterValues[ui][1]; + r700->ps.consts[ui][2].f32All = paramList->ParameterValues[ui][2]; + r700->ps.consts[ui][3].f32All = paramList->ParameterValues[ui][3]; + } + } else + r700->ps.num_consts = 0; + return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index f0cd357c76..c8b405f555 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -55,7 +55,6 @@ void r700WaitForIdle(context_t *context); void r700WaitForIdleClean(context_t *context); -void r700Start3D(context_t *context); GLboolean r700SendTextureState(context_t *context); static unsigned int r700PrimitiveType(int prim); void r600UpdateTextureState(GLcontext * ctx); @@ -116,39 +115,6 @@ void r700Start3D(context_t *context) r700WaitForIdleClean(context); } -static GLboolean r700SetupShaders(GLcontext * ctx) -{ - context_t *context = R700_CONTEXT(ctx); - - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - - GLuint exportCount; - - r700->ps.SQ_PGM_RESOURCES_PS.u32All = 0; - r700->vs.SQ_PGM_RESOURCES_VS.u32All = 0; - - SETbit(r700->ps.SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); - SETbit(r700->vs.SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); - - r700SetupVertexProgram(ctx); - - r700SetupFragmentProgram(ctx); - - exportCount = (r700->ps.SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift); - r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1; - - r600UpdateTextureState(ctx); - - r700SendFSState(context); // FIXME just a place holder for now - r700SendPSState(context); - r700SendVSState(context); - - r700SendTextureState(context); - r700SetupStreams(ctx); - - return GL_TRUE; -} - GLboolean r700SyncSurf(context_t *context, struct radeon_bo *pbo, uint32_t read_domain, @@ -333,7 +299,7 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim } static GLboolean r700RunRender(GLcontext * ctx, - struct tnl_pipeline_stage *stage) + struct tnl_pipeline_stage *stage) { context_t *context = R700_CONTEXT(ctx); radeonContextPtr radeon = &context->radeon; @@ -347,12 +313,15 @@ static GLboolean r700RunRender(GLcontext * ctx, /* just an estimate, need to properly calculate this */ rcommonEnsureCmdBufSpace(&context->radeon, - radeon->hw.max_state_size + ind_count + 1000, __FUNCTION__); + radeon->hw.max_state_size + ind_count, __FUNCTION__); - r700Start3D(context); r700UpdateShaders(ctx); r700SetScissor(context); - r700SetupShaders(ctx); + r700SetupVertexProgram(ctx); + r700SetupFragmentProgram(ctx); + r600UpdateTextureState(ctx); + r700SetupStreams(ctx); + radeonEmitState(radeon); /* richard test code */ diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 97c7d7c385..0f25102a79 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -168,7 +168,6 @@ void r700UpdateViewportOffset(GLcontext * ctx) //------------------ void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //--------------------- { context_t *context = R700_CONTEXT(ctx); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); R600_STATECHANGE(context, cb_target); R600_STATECHANGE(context, db_target); @@ -1422,7 +1421,6 @@ static void r700SetRenderTarget(context_t *context, int id) rrb = radeon_get_colorbuffer(&context->radeon); if (!rrb || !rrb->bo) { - fprintf(stderr, "no rrb\n"); return; } diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index 14da4ed1d3..550594e9df 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -336,7 +336,6 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - BATCH_LOCALS(&context->radeon); struct r700_vertex_program *vp = (struct r700_vertex_program *)ctx->VertexProgram._Current; @@ -368,10 +367,14 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) (context->chipobj.MemUse)(context, vp->shadercode.buf->id); */ - R600_STATECHANGE(context, spi); + R600_STATECHANGE(context, vs); + R600_STATECHANGE(context, fs); /* hack */ + + r700->vs.SQ_PGM_RESOURCES_VS.u32All = 0; + SETbit(r700->vs.SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); + + r700->vs.SQ_PGM_START_VS.u32All = 0; /* set from buffer object. */ - r700->vs.SQ_PGM_START_VS.u32All = 0; /* set from buffer object. */ - SETfield(r700->vs.SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.nRegs + 1, NUM_GPRS_shift, NUM_GPRS_mask); @@ -381,9 +384,12 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) STACK_SIZE_shift, STACK_SIZE_mask); } - SETfield(r700->SPI_VS_OUT_CONFIG.u32All, vp->r700Shader.nParamExports ? (vp->r700Shader.nParamExports - 1) : 0, + R600_STATECHANGE(context, spi); + + SETfield(r700->SPI_VS_OUT_CONFIG.u32All, + vp->r700Shader.nParamExports ? (vp->r700Shader.nParamExports - 1) : 0, VS_EXPORT_COUNT_shift, VS_EXPORT_COUNT_mask); - SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, vp->r700Shader.nParamExports, + SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, vp->r700Shader.nParamExports, NUM_INTERP_shift, NUM_INTERP_mask); /* @@ -394,34 +400,26 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) /* sent out shader constants. */ paramList = vp->mesa_program.Base.Parameters; - if(NULL != paramList) - { - _mesa_load_state_parameters(ctx, paramList); + if(NULL != paramList) { + _mesa_load_state_parameters(ctx, paramList); - unNumParamData = paramList->NumParameters * 4; + if (paramList->NumParameters > R700_MAX_DX9_CONSTS) + return GL_FALSE; - BEGIN_BATCH_NO_AUTOSTATE(unNumParamData + 2); + R600_STATECHANGE(context, vs_consts); - R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData)); - /* assembler map const from very beginning. */ - R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4); + r700->vs.num_consts = paramList->NumParameters; - unNumParamData = paramList->NumParameters; + unNumParamData = paramList->NumParameters; - for(ui=0; uiParameterValues[ui][0]))); - R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1]))); - R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2]))); - R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3]))); - } - END_BATCH(); - COMMIT_BATCH(); - } + for(ui=0; uivs.consts[ui][0].f32All = paramList->ParameterValues[ui][0]; + r700->vs.consts[ui][1].f32All = paramList->ParameterValues[ui][1]; + r700->vs.consts[ui][2].f32All = paramList->ParameterValues[ui][2]; + r700->vs.consts[ui][3].f32All = paramList->ParameterValues[ui][3]; + } + } else + r700->vs.num_consts = 0; return GL_TRUE; } - - - - -- cgit v1.2.3 From bf6d0ae5980a48b24ace49030eca221dcbec163f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Sat, 22 Aug 2009 18:02:03 -0400 Subject: r600: make state emit more fine grained Gives a nice speed boost in most apps since we only emit what state we need. --- src/mesa/drivers/dri/r600/r600_context.h | 10 + src/mesa/drivers/dri/r600/r600_texstate.c | 2 + src/mesa/drivers/dri/r600/r700_chip.c | 310 ++++++++++++++++++++---------- src/mesa/drivers/dri/r600/r700_state.c | 14 +- 4 files changed, 230 insertions(+), 106 deletions(-) (limited to 'src/mesa/drivers/dri/r600/r700_state.c') diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index 48be89b638..8ae05a301c 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -111,12 +111,20 @@ enum struct r600_hw_state { struct radeon_state_atom sq; struct radeon_state_atom db; + struct radeon_state_atom stencil; struct radeon_state_atom db_target; struct radeon_state_atom sc; + struct radeon_state_atom scissor; + struct radeon_state_atom aa; struct radeon_state_atom cl; + struct radeon_state_atom gb; struct radeon_state_atom ucp; struct radeon_state_atom su; + struct radeon_state_atom poly; struct radeon_state_atom cb; + struct radeon_state_atom clrcmp; + struct radeon_state_atom blnd; + struct radeon_state_atom blnd_clr; struct radeon_state_atom cb_target; struct radeon_state_atom sx; struct radeon_state_atom vgt; @@ -132,6 +140,8 @@ struct r600_hw_state { struct radeon_state_atom vtx; struct radeon_state_atom tx; + struct radeon_state_atom tx_smplr; + struct radeon_state_atom tx_brdr_clr; }; /** diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 7486d73760..9f1bf45246 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -61,6 +61,8 @@ void r600UpdateTextureState(GLcontext * ctx) GLuint unit; R600_STATECHANGE(context, tx); + R600_STATECHANGE(context, tx_smplr); + R600_STATECHANGE(context, tx_brdr_clr); for (unit = 0; unit < R700_MAX_TEXTURE_UNITS; unit++) { texUnit = &ctx->Texture.Unit[unit]; diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index b7c2be16ff..9985562620 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -41,67 +41,94 @@ #include "radeon_mipmap_tree.h" -static void r700SendTextureState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom) { - context_t *context = R700_CONTEXT(ctx); - R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - struct radeon_bo *bo = NULL; - unsigned int i; - BATCH_LOCALS(&context->radeon); + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + struct radeon_bo *bo = NULL; + unsigned int i; + BATCH_LOCALS(&context->radeon); - for (i=0; itextures[i]; - if (t) { - if (!t->image_override) - bo = t->mt->bo; - else - bo = t->bo; - if (bo) { - - r700SyncSurf(context, bo, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, - 0, TC_ACTION_ENA_bit); - - BEGIN_BATCH_NO_AUTOSTATE(9 + 4); - R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); - R600_OUT_BATCH(i * 7); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1); - R600_OUT_BATCH(0); /* r700->textures[i]->SQ_TEX_RESOURCE2 */ - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6); - R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2, - bo, - 0, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3, - bo, - r700->textures[i]->SQ_TEX_RESOURCE3, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - END_BATCH(); - - BEGIN_BATCH_NO_AUTOSTATE(5); - R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3)); - R600_OUT_BATCH(i * 3); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2); - END_BATCH(); - - BEGIN_BATCH_NO_AUTOSTATE(2 + 4); - R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4); - R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED); - R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN); - R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE); - R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA); - END_BATCH(); - - COMMIT_BATCH(); - } - } - } + for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) { + radeonTexObj *t = r700->textures[i]; + if (t) { + if (!t->image_override) + bo = t->mt->bo; + else + bo = t->bo; + if (bo) { + + r700SyncSurf(context, bo, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, + 0, TC_ACTION_ENA_bit); + + BEGIN_BATCH_NO_AUTOSTATE(9 + 4); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); + R600_OUT_BATCH(i * 7); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE2); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6); + R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2, + bo, + 0, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3, + bo, + r700->textures[i]->SQ_TEX_RESOURCE3, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + END_BATCH(); + COMMIT_BATCH(); + } + } + } +} + +static void r700SendTexSamplerState(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + unsigned int i; + BATCH_LOCALS(&context->radeon); + + for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) { + radeonTexObj *t = r700->textures[i]; + if (t) { + BEGIN_BATCH_NO_AUTOSTATE(5); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3)); + R600_OUT_BATCH(i * 3); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2); + END_BATCH(); + COMMIT_BATCH(); + } + } +} + +static void r700SendTexBorderColorState(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + unsigned int i; + BATCH_LOCALS(&context->radeon); + + for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) { + radeonTexObj *t = r700->textures[i]; + if (t) { + BEGIN_BATCH_NO_AUTOSTATE(2 + 4); + R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4); + R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED); + R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN); + R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE); + R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA); + END_BATCH(); + COMMIT_BATCH(); + } + } } static void r700SetupVTXConstants(GLcontext * ctx, @@ -650,17 +677,13 @@ static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom) R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); - BEGIN_BATCH_NO_AUTOSTATE(27); + BEGIN_BATCH_NO_AUTOSTATE(23); R600_OUT_BATCH_REGVAL(DB_HTILE_DATA_BASE, r700->DB_HTILE_DATA_BASE.u32All); R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2); R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All); R600_OUT_BATCH(r700->DB_DEPTH_CLEAR.u32All); - R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2); - R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All); - R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All); - R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, r700->DB_DEPTH_CONTROL.u32All); R600_OUT_BATCH_REGVAL(DB_SHADER_CONTROL, r700->DB_SHADER_CONTROL.u32All); @@ -675,15 +698,28 @@ static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); } +static void r700SendStencilState(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + BATCH_LOCALS(&context->radeon); + + BEGIN_BATCH_NO_AUTOSTATE(4); + R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2); + R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All); + R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All); + END_BATCH(); + COMMIT_BATCH(); +} + static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); - unsigned int ui; if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) { - BEGIN_BATCH_NO_AUTOSTATE(14); + BEGIN_BATCH_NO_AUTOSTATE(11); R600_OUT_BATCH_REGSEQ(CB_CLEAR_RED, 4); R600_OUT_BATCH(r700->CB_CLEAR_RED_R6XX.u32All); R600_OUT_BATCH(r700->CB_CLEAR_GREEN_R6XX.u32All); @@ -693,31 +729,50 @@ static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom) R600_OUT_BATCH(r700->CB_FOG_RED_R6XX.u32All); R600_OUT_BATCH(r700->CB_FOG_GREEN_R6XX.u32All); R600_OUT_BATCH(r700->CB_FOG_BLUE_R6XX.u32All); - /* R600 does not have per-MRT blend */ - R600_OUT_BATCH_REGVAL(CB_BLEND_CONTROL, r700->CB_BLEND_CONTROL.u32All); END_BATCH(); } - BEGIN_BATCH_NO_AUTOSTATE(22); + BEGIN_BATCH_NO_AUTOSTATE(7); R600_OUT_BATCH_REGSEQ(CB_TARGET_MASK, 2); R600_OUT_BATCH(r700->CB_TARGET_MASK.u32All); R600_OUT_BATCH(r700->CB_SHADER_MASK.u32All); - - R600_OUT_BATCH_REGSEQ(CB_BLEND_RED, 4); - R600_OUT_BATCH(r700->CB_BLEND_RED.u32All); - R600_OUT_BATCH(r700->CB_BLEND_GREEN.u32All); - R600_OUT_BATCH(r700->CB_BLEND_BLUE.u32All); - R600_OUT_BATCH(r700->CB_BLEND_ALPHA.u32All); - R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL, r700->CB_SHADER_CONTROL.u32All); - R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL, r700->CB_COLOR_CONTROL.u32All); + END_BATCH(); + COMMIT_BATCH(); +} +static void r700SendCBCLRCMPState(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + BATCH_LOCALS(&context->radeon); + + BEGIN_BATCH_NO_AUTOSTATE(6); R600_OUT_BATCH_REGSEQ(CB_CLRCMP_CONTROL, 4); R600_OUT_BATCH(r700->CB_CLRCMP_CONTROL.u32All); R600_OUT_BATCH(r700->CB_CLRCMP_SRC.u32All); R600_OUT_BATCH(r700->CB_CLRCMP_DST.u32All); R600_OUT_BATCH(r700->CB_CLRCMP_MSK.u32All); END_BATCH(); + COMMIT_BATCH(); +} + +static void r700SendCBBlendState(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + BATCH_LOCALS(&context->radeon); + unsigned int ui; + + if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) { + BEGIN_BATCH_NO_AUTOSTATE(3); + R600_OUT_BATCH_REGVAL(CB_BLEND_CONTROL, r700->CB_BLEND_CONTROL.u32All); + END_BATCH(); + } + + BEGIN_BATCH_NO_AUTOSTATE(3); + R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL, r700->CB_COLOR_CONTROL.u32All); + END_BATCH(); if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) { for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) { @@ -731,7 +786,22 @@ static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom) } COMMIT_BATCH(); +} +static void r700SendCBBlendColorState(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + BATCH_LOCALS(&context->radeon); + + BEGIN_BATCH_NO_AUTOSTATE(6); + R600_OUT_BATCH_REGSEQ(CB_BLEND_RED, 4); + R600_OUT_BATCH(r700->CB_BLEND_RED.u32All); + R600_OUT_BATCH(r700->CB_BLEND_GREEN.u32All); + R600_OUT_BATCH(r700->CB_BLEND_BLUE.u32All); + R600_OUT_BATCH(r700->CB_BLEND_ALPHA.u32All); + END_BATCH(); + COMMIT_BATCH(); } static void r700SendSUState(GLcontext *ctx, struct radeon_state_atom *atom) @@ -740,25 +810,33 @@ static void r700SendSUState(GLcontext *ctx, struct radeon_state_atom *atom) R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); - BEGIN_BATCH_NO_AUTOSTATE(19); + BEGIN_BATCH_NO_AUTOSTATE(9); R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL, r700->PA_SU_SC_MODE_CNTL.u32All); - R600_OUT_BATCH_REGSEQ(PA_SU_POINT_SIZE, 4); R600_OUT_BATCH(r700->PA_SU_POINT_SIZE.u32All); R600_OUT_BATCH(r700->PA_SU_POINT_MINMAX.u32All); R600_OUT_BATCH(r700->PA_SU_LINE_CNTL.u32All); R600_OUT_BATCH(r700->PA_SU_VTX_CNTL.u32All); + END_BATCH(); + COMMIT_BATCH(); + +} + +static void r700SendPolyState(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + BATCH_LOCALS(&context->radeon); + BEGIN_BATCH_NO_AUTOSTATE(10); R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 2); R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All); R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_CLAMP.u32All); - R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_FRONT_SCALE, 4); R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All); R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All); R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_SCALE.u32All); R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All); - END_BATCH(); COMMIT_BATCH(); @@ -770,35 +848,43 @@ static void r700SendCLState(GLcontext *ctx, struct radeon_state_atom *atom) R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); - BEGIN_BATCH_NO_AUTOSTATE(18); + BEGIN_BATCH_NO_AUTOSTATE(12); R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, r700->PA_CL_CLIP_CNTL.u32All); R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL, r700->PA_CL_VTE_CNTL.u32All); R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL, r700->PA_CL_VS_OUT_CNTL.u32All); R600_OUT_BATCH_REGVAL(PA_CL_NANINF_CNTL, r700->PA_CL_NANINF_CNTL.u32All); + END_BATCH(); + COMMIT_BATCH(); +} + +static void r700SendGBState(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + BATCH_LOCALS(&context->radeon); + BEGIN_BATCH_NO_AUTOSTATE(6); R600_OUT_BATCH_REGSEQ(PA_CL_GB_VERT_CLIP_ADJ, 4); R600_OUT_BATCH(r700->PA_CL_GB_VERT_CLIP_ADJ.u32All); R600_OUT_BATCH(r700->PA_CL_GB_VERT_DISC_ADJ.u32All); R600_OUT_BATCH(r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All); R600_OUT_BATCH(r700->PA_CL_GB_HORZ_DISC_ADJ.u32All); - END_BATCH(); COMMIT_BATCH(); } -// XXX need to split this up -static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom) +static void r700SendScissorState(GLcontext *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); - BEGIN_BATCH_NO_AUTOSTATE(47); + BEGIN_BATCH_NO_AUTOSTATE(22); R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2); R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_TL.u32All); R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_BR.u32All); - R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 13); + R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 12); R600_OUT_BATCH(r700->PA_SC_WINDOW_OFFSET.u32All); R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_TL.u32All); R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_BR.u32All); @@ -811,21 +897,41 @@ static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom) R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_BR.u32All); R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_TL.u32All); R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_BR.u32All); - R600_OUT_BATCH(r700->PA_SC_EDGERULE.u32All); R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2); R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_TL.u32All); R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_BR.u32All); + END_BATCH(); + COMMIT_BATCH(); +} + +static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + BATCH_LOCALS(&context->radeon); + BEGIN_BATCH_NO_AUTOSTATE(15); + R600_OUT_BATCH_REGVAL(R7xx_PA_SC_EDGERULE, r700->PA_SC_EDGERULE.u32All); R600_OUT_BATCH_REGVAL(PA_SC_LINE_STIPPLE, r700->PA_SC_LINE_STIPPLE.u32All); R600_OUT_BATCH_REGVAL(PA_SC_MPASS_PS_CNTL, r700->PA_SC_MPASS_PS_CNTL.u32All); R600_OUT_BATCH_REGVAL(PA_SC_MODE_CNTL, r700->PA_SC_MODE_CNTL.u32All); R600_OUT_BATCH_REGVAL(PA_SC_LINE_CNTL, r700->PA_SC_LINE_CNTL.u32All); + END_BATCH(); + COMMIT_BATCH(); +} + +static void r700SendAAState(GLcontext *ctx, struct radeon_state_atom *atom) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + BATCH_LOCALS(&context->radeon); + + BEGIN_BATCH_NO_AUTOSTATE(12); R600_OUT_BATCH_REGVAL(PA_SC_AA_CONFIG, r700->PA_SC_AA_CONFIG.u32All); R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_MCTX.u32All); R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX.u32All); R600_OUT_BATCH_REGVAL(PA_SC_AA_MASK, r700->PA_SC_AA_MASK.u32All); - END_BATCH(); COMMIT_BATCH(); } @@ -942,29 +1048,35 @@ void r600InitAtoms(context_t *context) context->radeon.hw.atomlist.name = "atom-list"; ALLOC_STATE(sq, always, 34, r700SendSQConfig); - - ALLOC_STATE(db, always, 27, r700SendDBState); + ALLOC_STATE(db, always, 23, r700SendDBState); + ALLOC_STATE(stencil, always, 4, r700SendStencilState); ALLOC_STATE(db_target, always, 19, r700SendDepthTargetState); - ALLOC_STATE(sc, always, 47, r700SendSCState); - ALLOC_STATE(cl, always, 18, r700SendCLState); + ALLOC_STATE(sc, always, 15, r700SendSCState); + ALLOC_STATE(scissor, always, 22, r700SendScissorState); + ALLOC_STATE(aa, always, 12, r700SendAAState); + ALLOC_STATE(cl, always, 12, r700SendCLState); + ALLOC_STATE(gb, always, 6, r700SendGBState); ALLOC_STATE(ucp, always, 36, r700SendUCPState); - ALLOC_STATE(su, always, 19, r700SendSUState); - ALLOC_STATE(cb, always, 39, r700SendCBState); + ALLOC_STATE(su, always, 9, r700SendSUState); + ALLOC_STATE(poly, always, 10, r700SendPolyState); + ALLOC_STATE(cb, always, 18, r700SendCBState); + ALLOC_STATE(clrcmp, always, 6, r700SendCBCLRCMPState); + ALLOC_STATE(blnd, always, 30, r700SendCBBlendState); + ALLOC_STATE(blnd_clr, always, 6, r700SendCBBlendColorState); ALLOC_STATE(cb_target, always, 32, r700SendRenderTargetState); ALLOC_STATE(sx, always, 9, r700SendSXState); ALLOC_STATE(vgt, always, 41, r700SendVGTState); ALLOC_STATE(spi, always, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState); ALLOC_STATE(vpt, always, 16, r700SendViewportState); - ALLOC_STATE(fs, always, 18, r700SendFSState); ALLOC_STATE(vs, always, 18, r700SendVSState); ALLOC_STATE(ps, always, 21, r700SendPSState); - ALLOC_STATE(vs_consts, vs_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendVSConsts); ALLOC_STATE(ps_consts, ps_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendPSConsts); - ALLOC_STATE(vtx, vtx, (VERT_ATTRIB_MAX * 18), r700SendVTXState); - ALLOC_STATE(tx, tx, (R700_TEXTURE_NUMBERUNITS * 31), r700SendTextureState); + ALLOC_STATE(tx, tx, (R700_TEXTURE_NUMBERUNITS * 20), r700SendTexState); + ALLOC_STATE(tx_smplr, tx, (R700_TEXTURE_NUMBERUNITS * 5), r700SendTexSamplerState); + ALLOC_STATE(tx_brdr_clr, tx, (R700_TEXTURE_NUMBERUNITS * 6), r700SendTexBorderColorState); context->radeon.hw.is_dirty = GL_TRUE; context->radeon.hw.all_dirty = GL_TRUE; diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 0f25102a79..75b2b72eb9 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -399,7 +399,7 @@ static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //------------- context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - R600_STATECHANGE(context, cb); + R600_STATECHANGE(context, blnd_clr); r700->CB_BLEND_RED.f32All = cf[0]; r700->CB_BLEND_GREEN.f32All = cf[1]; @@ -469,7 +469,7 @@ static void r700SetBlendState(GLcontext * ctx) int id = 0; uint32_t blend_reg = 0, eqn, eqnA; - R600_STATECHANGE(context, cb); + R600_STATECHANGE(context, blnd); if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) { SETfield(blend_reg, @@ -660,7 +660,7 @@ static void r700SetLogicOpState(GLcontext *ctx) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw); - R600_STATECHANGE(context, cb); + R600_STATECHANGE(context, blnd); if (RGBA_LOGICOP_ENABLED(ctx)) SETfield(r700->CB_COLOR_CONTROL.u32All, @@ -1023,7 +1023,7 @@ static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face, //fixme //r300CatchStencilFallback(ctx); - R600_STATECHANGE(context, db); + R600_STATECHANGE(context, stencil); //front SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0], @@ -1054,7 +1054,7 @@ static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) / //fixme //r300CatchStencilFallback(ctx); - R600_STATECHANGE(context, db); + R600_STATECHANGE(context, stencil); // front SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0], @@ -1214,7 +1214,7 @@ static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) // factor *= 12.0; - R600_STATECHANGE(context, su); + R600_STATECHANGE(context, poly); r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor; r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant; @@ -1355,7 +1355,7 @@ void r700SetScissor(context_t *context) //--------------- y2 = rrb->dPriv->y + rrb->dPriv->h; } - R600_STATECHANGE(context, sc); + R600_STATECHANGE(context, scissor); /* window */ SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit); -- cgit v1.2.3