From ce9c5a1a27b4e59dbf49b066baaae6ef371b04bc Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Mon, 20 Jul 2009 15:27:28 -0400
Subject: r600: add logicop support

---
 src/mesa/drivers/dri/r600/r700_state.c | 43 ++++++++++++++++++++++++++++++++--
 1 file changed, 41 insertions(+), 2 deletions(-)

(limited to 'src/mesa/drivers/dri/r600/r700_state.c')

diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index eda224def3..1ccd793512 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -30,6 +30,7 @@
 #include "main/imports.h"
 #include "main/enums.h"
 #include "main/macros.h"
+#include "main/context.h"
 #include "main/dd.h"
 #include "main/simple_list.h"
 
@@ -322,6 +323,43 @@ static void r700BlendFuncSeparate(GLcontext * ctx,
 {
 }
 
+/**
+ * Translate LogicOp enums into hardware representation.
+ * Both use a very logical bit-wise layout, but unfortunately the order
+ * of bits is reversed.
+ */
+static GLuint translate_logicop(GLenum logicop)
+{
+	GLuint bits = logicop - GL_CLEAR;
+	bits = ((bits & 1) << 3) | ((bits & 2) << 1) | ((bits & 4) >> 1) | ((bits & 8) >> 3);
+	return bits;
+}
+
+/**
+ * Used internally to update the r300->hw hardware state to match the
+ * current OpenGL state.
+ */
+static void r700SetLogicOpState(GLcontext *ctx)
+{
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
+
+	if (RGBA_LOGICOP_ENABLED(ctx))
+		SETfield(r700->CB_COLOR_CONTROL.u32All,
+			 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
+	else
+		SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
+}
+
+/**
+ * Called by Mesa when an application program changes the LogicOp state
+ * via glLogicOp.
+ */
+static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
+{
+	if (RGBA_LOGICOP_ENABLED(ctx))
+		r700SetLogicOpState(ctx);
+}
+
 static void r700UpdateCulling(GLcontext * ctx)
 {
     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
@@ -397,7 +435,7 @@ static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //---------
 		//r700SetAlphaState(ctx);
 		break;
 	case GL_COLOR_LOGIC_OP:
-		//r700SetLogicOpState(ctx);
+		r700SetLogicOpState(ctx);
 		/* fall-through, because logic op overrides blending */
 	case GL_BLEND:
 		//r700SetBlendState(ctx);
@@ -1083,7 +1121,7 @@ void r700InitState(GLcontext * ctx) //-------------------
     if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
 	    SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
 
-    SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
+    r700SetLogicOpState(ctx);
     CLEARbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
 
     r700->DB_SHADER_CONTROL.u32All = 0;
@@ -1228,6 +1266,7 @@ void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
 	functions->Fogfv = r700Fogfv;
 	functions->FrontFace = r700FrontFace;
 	functions->ShadeModel = r700ShadeModel;
+	functions->LogicOpcode = r700LogicOpcode;
 
 	/* ARB_point_parameters */
 	functions->PointParameterfv = r700PointParameter;
-- 
cgit v1.2.3


From a369963b18fc7ef75f6f5354e0d685cef9ecb70d Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Mon, 20 Jul 2009 17:22:59 -0400
Subject: r600: add user clip plane support

---
 src/mesa/drivers/dri/r600/r700_chip.c   | 22 +++++++++++++++++++++
 src/mesa/drivers/dri/r600/r700_render.c |  1 +
 src/mesa/drivers/dri/r600/r700_state.c  | 35 +++++++++++++++++++++++++++++++--
 3 files changed, 56 insertions(+), 2 deletions(-)

(limited to 'src/mesa/drivers/dri/r600/r700_state.c')

diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 087d17312e..91aa8fc8fc 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -722,3 +722,25 @@ GLboolean r700SendSQConfig(context_t *context)
 	return GL_TRUE;
 }
 
+GLboolean r700SendUCPState(context_t *context)
+{
+	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
+	BATCH_LOCALS(&context->radeon);
+	int i;
+
+	for (i = 0; i < R700_MAX_UCP; i++) {
+		if (r700->ucp[i].enabled) {
+			BEGIN_BATCH_NO_AUTOSTATE(6);
+			R600_OUT_BATCH_REGSEQ(PA_CL_UCP_0_X + (16 * i), 4);
+			R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_X.u32All);
+			R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Y.u32All);
+			R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Z.u32All);
+			R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_W.u32All);
+			END_BATCH();
+			COMMIT_BATCH();
+		}
+	}
+
+	return GL_TRUE;
+}
+
diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index f1e467a317..77cbe3cfd0 100644
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -322,6 +322,7 @@ static GLboolean r700RunRender(GLcontext * ctx,
     r700SendPSState(context);
     r700SendVSState(context);
 
+    r700SendUCPState(context);
     r700SendContextStates(context);
     r700SendViewportState(context, 0);
     r700SendRenderTargetState(context, 0);
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 1ccd793512..1d6d398f63 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -56,6 +56,8 @@
 #include "r700_vertprog.h"
 
 
+static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
+
 void r700SetDefaultStates(context_t *context) //--------------------
 {
     
@@ -446,7 +448,7 @@ static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //---------
 	case GL_CLIP_PLANE3:
 	case GL_CLIP_PLANE4:
 	case GL_CLIP_PLANE5:
-		//r700SetClipPlaneState(ctx, cap, state);
+		r700SetClipPlaneState(ctx, cap, state);
 		break;
 	case GL_DEPTH_TEST:
 		r700SetDepthState(ctx);
@@ -675,8 +677,37 @@ static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
 {
 }
 
-static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) //-----------------
+static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
 {
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	GLint p;
+	GLint *ip;
+
+	p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
+	ip = (GLint *)ctx->Transform._ClipUserPlane[p];
+
+	r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
+	r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
+	r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
+	r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
+}
+
+static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	GLuint p;
+
+	p = cap - GL_CLIP_PLANE0;
+	if (state) {
+		r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
+		r700->ucp[p].enabled = GL_TRUE;
+		r700ClipPlane(ctx, cap, NULL);
+	} else {
+		r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
+		r700->ucp[p].enabled = GL_FALSE;
+	}
 }
 
 void r700SetScissor(context_t *context) //---------------
-- 
cgit v1.2.3


From 265d5eba658f38f5a9d12d57b701e4ffe49100eb Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Mon, 20 Jul 2009 18:50:59 -0400
Subject: r600: add blending support

---
 src/mesa/drivers/dri/r600/r700_state.c | 210 +++++++++++++++++++++++++++++++--
 1 file changed, 197 insertions(+), 13 deletions(-)

(limited to 'src/mesa/drivers/dri/r600/r700_state.c')

diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 1d6d398f63..070cea56f8 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -312,17 +312,211 @@ static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------
 
 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
 {
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+
+	r700->CB_BLEND_RED.f32All = cf[0];
+	r700->CB_BLEND_GREEN.f32All = cf[1];
+	r700->CB_BLEND_BLUE.f32All = cf[2];
+	r700->CB_BLEND_ALPHA.f32All = cf[3];
+}
+
+static int blend_factor(GLenum factor, GLboolean is_src)
+{
+	switch (factor) {
+	case GL_ZERO:
+		return BLEND_ZERO;
+		break;
+	case GL_ONE:
+		return BLEND_ONE;
+		break;
+	case GL_DST_COLOR:
+		return BLEND_DST_COLOR;
+		break;
+	case GL_ONE_MINUS_DST_COLOR:
+		return BLEND_ONE_MINUS_DST_COLOR;
+		break;
+	case GL_SRC_COLOR:
+		return BLEND_SRC_COLOR;
+		break;
+	case GL_ONE_MINUS_SRC_COLOR:
+		return BLEND_ONE_MINUS_SRC_COLOR;
+		break;
+	case GL_SRC_ALPHA:
+		return BLEND_SRC_ALPHA;
+		break;
+	case GL_ONE_MINUS_SRC_ALPHA:
+		return BLEND_ONE_MINUS_SRC_ALPHA;
+		break;
+	case GL_DST_ALPHA:
+		return BLEND_DST_ALPHA;
+		break;
+	case GL_ONE_MINUS_DST_ALPHA:
+		return BLEND_ONE_MINUS_DST_ALPHA;
+		break;
+	case GL_SRC_ALPHA_SATURATE:
+		return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
+		break;
+	case GL_CONSTANT_COLOR:
+		return BLEND_CONSTANT_COLOR;
+		break;
+	case GL_ONE_MINUS_CONSTANT_COLOR:
+		return BLEND_ONE_MINUS_CONSTANT_COLOR;
+		break;
+	case GL_CONSTANT_ALPHA:
+		return BLEND_CONSTANT_ALPHA;
+		break;
+	case GL_ONE_MINUS_CONSTANT_ALPHA:
+		return BLEND_ONE_MINUS_CONSTANT_ALPHA;
+		break;
+	default:
+		fprintf(stderr, "unknown blend factor %x\n", factor);
+		return (is_src) ? BLEND_ONE : BLEND_ZERO;
+		break;
+	}
+}
+
+static void r700SetBlendState(GLcontext * ctx)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	int id = 0;
+	uint32_t blend_reg = 0, eqn, eqnA;
+
+	if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
+		SETfield(blend_reg,
+			 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
+		SETfield(blend_reg,
+			 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
+		SETfield(blend_reg,
+			 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
+		SETfield(blend_reg,
+			 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
+		SETfield(blend_reg,
+			 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
+		SETfield(blend_reg,
+			 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
+		if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
+			r700->CB_BLEND_CONTROL.u32All = blend_reg;
+		else
+			r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
+		return;
+	}
+
+	SETfield(blend_reg,
+		 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
+		 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
+	SETfield(blend_reg,
+		 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
+		 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
+
+	switch (ctx->Color.BlendEquationRGB) {
+	case GL_FUNC_ADD:
+		eqn = COMB_DST_PLUS_SRC;
+		break;
+	case GL_FUNC_SUBTRACT:
+		eqn = COMB_SRC_MINUS_DST;
+		break;
+	case GL_FUNC_REVERSE_SUBTRACT:
+		eqn = COMB_DST_MINUS_SRC;
+		break;
+	case GL_MIN:
+		eqn = COMB_MIN_DST_SRC;
+		SETfield(blend_reg,
+			 BLEND_ONE,
+			 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
+		SETfield(blend_reg,
+			 BLEND_ONE,
+			 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
+		break;
+	case GL_MAX:
+		eqn = COMB_MAX_DST_SRC;
+		SETfield(blend_reg,
+			 BLEND_ONE,
+			 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
+		SETfield(blend_reg,
+			 BLEND_ONE,
+			 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
+		break;
+
+	default:
+		fprintf(stderr,
+			"[%s:%u] Invalid RGB blend equation (0x%04x).\n",
+			__FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
+		return;
+	}
+	SETfield(blend_reg,
+		 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
+
+	SETfield(blend_reg,
+		 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
+		 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
+	SETfield(blend_reg,
+		 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
+		 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
+
+	switch (ctx->Color.BlendEquationA) {
+	case GL_FUNC_ADD:
+		eqnA = COMB_DST_PLUS_SRC;
+		break;
+	case GL_FUNC_SUBTRACT:
+		eqnA = COMB_SRC_MINUS_DST;
+		break;
+	case GL_FUNC_REVERSE_SUBTRACT:
+		eqnA = COMB_DST_MINUS_SRC;
+		break;
+	case GL_MIN:
+		eqnA = COMB_MIN_DST_SRC;
+		SETfield(blend_reg,
+			 BLEND_ONE,
+			 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
+		SETfield(blend_reg,
+			 BLEND_ONE,
+			 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
+		break;
+	case GL_MAX:
+		eqnA = COMB_MAX_DST_SRC;
+		SETfield(blend_reg,
+			 BLEND_ONE,
+			 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
+		SETfield(blend_reg,
+			 BLEND_ONE,
+			 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
+		break;
+	default:
+		fprintf(stderr,
+			"[%s:%u] Invalid A blend equation (0x%04x).\n",
+			__FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
+		return;
+	}
+
+	SETfield(blend_reg,
+		 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
+
+	SETbit(r700->render_target[id].CB_BLEND0_CONTROL.u32All, SEPARATE_ALPHA_BLEND_bit);
+
+	if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
+		r700->CB_BLEND_CONTROL.u32All = blend_reg;
+	else {
+		r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
+		SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
+	}
+	SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
+		 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
+
 }
 
 static void r700BlendEquationSeparate(GLcontext * ctx,
 				                      GLenum modeRGB, GLenum modeA) //-----------------
 {
+	r700SetBlendState(ctx);
 }
 
 static void r700BlendFuncSeparate(GLcontext * ctx,
 				  GLenum sfactorRGB, GLenum dfactorRGB,
 				  GLenum sfactorA, GLenum dfactorA) //------------------------
 {
+	r700SetBlendState(ctx);
 }
 
 /**
@@ -440,7 +634,7 @@ static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //---------
 		r700SetLogicOpState(ctx);
 		/* fall-through, because logic op overrides blending */
 	case GL_BLEND:
-		//r700SetBlendState(ctx);
+		r700SetBlendState(ctx);
 		break;
 	case GL_CLIP_PLANE0:
 	case GL_CLIP_PLANE1:
@@ -471,7 +665,7 @@ static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //---------
 		break;
 	case GL_LINE_STIPPLE:
 		r700UpdateLineStipple(ctx);
-		break;	
+		break;
 	default:
 		break;
 	}
@@ -833,9 +1027,6 @@ void r700SetRenderTarget(context_t *context, int id)
     SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
     SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 
-    CLEARfield(r700->render_target[id].CB_BLEND0_CONTROL.u32All, COLOR_SRCBLEND_mask); /* no dst blend */
-    CLEARfield(r700->render_target[id].CB_BLEND0_CONTROL.u32All, ALPHA_SRCBLEND_mask); /* no dst blend */
-
     r700->render_target[id].enabled = GL_TRUE;
 }
 
@@ -1152,8 +1343,8 @@ void r700InitState(GLcontext * ctx) //-------------------
     if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
 	    SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
 
+    r700SetBlendState(ctx);
     r700SetLogicOpState(ctx);
-    CLEARbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
 
     r700->DB_SHADER_CONTROL.u32All = 0;
     SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
@@ -1245,13 +1436,6 @@ void r700InitState(GLcontext * ctx) //-------------------
     r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
     r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
 
-    r700->CB_BLEND_RED.u32All = 0;
-    r700->CB_BLEND_GREEN.u32All = 0;
-    r700->CB_BLEND_BLUE.u32All = 0;
-    r700->CB_BLEND_ALPHA.u32All = 0;
-
-    r700->CB_BLEND_CONTROL.u32All = 0;
-
     /* Disable color compares */
     SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
              CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
-- 
cgit v1.2.3


From 6617fa6fab2df5d3d8085affac019f90101bb7a8 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Mon, 20 Jul 2009 19:33:05 -0400
Subject: r600: fix typo in blend code

---
 src/mesa/drivers/dri/r600/r700_state.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/r600/r700_state.c')

diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 070cea56f8..4458443003 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -493,7 +493,7 @@ static void r700SetBlendState(GLcontext * ctx)
 	SETfield(blend_reg,
 		 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
 
-	SETbit(r700->render_target[id].CB_BLEND0_CONTROL.u32All, SEPARATE_ALPHA_BLEND_bit);
+	SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
 
 	if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
 		r700->CB_BLEND_CONTROL.u32All = blend_reg;
-- 
cgit v1.2.3


From 9e6d38f8a2cc89e3d45ef2bb169b72c3c41fc27b Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Tue, 21 Jul 2009 01:58:05 -0400
Subject: r600: add alpha test support

---
 src/mesa/drivers/dri/r600/r700_chip.c  |  1 +
 src/mesa/drivers/dri/r600/r700_chip.h  |  3 +-
 src/mesa/drivers/dri/r600/r700_state.c | 55 +++++++++++++++++++++++++++++++---
 3 files changed, 54 insertions(+), 5 deletions(-)

(limited to 'src/mesa/drivers/dri/r600/r700_state.c')

diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 91aa8fc8fc..635dd58e72 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -139,6 +139,7 @@ GLboolean r700InitChipObject(context_t *context)
     // SX
     LINK_STATES(SX_MISC);
     LINK_STATES(SX_ALPHA_TEST_CONTROL);
+    LINK_STATES(SX_ALPHA_REF);
 
     // VGT
     LINK_STATES(VGT_MAX_VTX_INDX);
diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h
index 04af4bc3b9..fa419aa499 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.h
+++ b/src/mesa/drivers/dri/r600/r700_chip.h
@@ -372,6 +372,7 @@ typedef struct _R700_CHIP_CONTEXT
 	// SX
 	union UINT_FLOAT                SX_MISC                   ;  /* 0xA0D4 */
 	union UINT_FLOAT     	        SX_ALPHA_TEST_CONTROL     ;  /* 0xA104 */
+	union UINT_FLOAT     	        SX_ALPHA_REF              ;  /* 0xA10E */
 
 	// VGT
 	union UINT_FLOAT          	VGT_MAX_VTX_INDX          ;  /* 0xA100 */
@@ -422,7 +423,7 @@ typedef struct _R700_CHIP_CONTEXT
 	union UINT_FLOAT              	SPI_FOG_FUNC_SCALE        ;  /* 0xA1B8 */
 	union UINT_FLOAT              	SPI_FOG_FUNC_BIAS         ;  /* 0xA1B9 */
 
-    union UINT_FLOAT         	SQ_VTX_SEMANTIC_0         ;  /* 0xA0E0 */
+	union UINT_FLOAT         	SQ_VTX_SEMANTIC_0         ;  /* 0xA0E0 */
 	union UINT_FLOAT         	SQ_VTX_SEMANTIC_1         ;  /* 0xA0E1 */
 	union UINT_FLOAT         	SQ_VTX_SEMANTIC_2         ;  /* 0xA0E2 */
 	union UINT_FLOAT         	SQ_VTX_SEMANTIC_3         ;  /* 0xA0E3 */
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 4458443003..5fe4b36b71 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -305,8 +305,57 @@ static void r700SetDepthState(GLcontext * ctx)
     }
 }
 
+static void r700SetAlphaState(GLcontext * ctx)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	uint32_t alpha_func;
+	GLboolean really_enabled = ctx->Color.AlphaEnabled;
+
+	switch (ctx->Color.AlphaFunc) {
+	case GL_NEVER:
+		alpha_func = REF_NEVER;
+		break;
+	case GL_LESS:
+		alpha_func = REF_LESS;
+		break;
+	case GL_EQUAL:
+		alpha_func = REF_EQUAL;
+		break;
+	case GL_LEQUAL:
+		alpha_func = REF_LEQUAL;
+		break;
+	case GL_GREATER:
+		alpha_func = REF_GREATER;
+		break;
+	case GL_NOTEQUAL:
+		alpha_func = REF_NOTEQUAL;
+		break;
+	case GL_GEQUAL:
+		alpha_func = REF_GEQUAL;
+		break;
+	case GL_ALWAYS:
+		/*alpha_func = REF_ALWAYS; */
+		really_enabled = GL_FALSE;
+		break;
+	}
+
+	if (really_enabled) {
+		SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
+			 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
+		SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
+		r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
+	} else {
+		CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
+	}
+
+}
+
 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
 {
+	(void)func;
+	(void)ref;
+	r700SetAlphaState(ctx);
 }
 
 
@@ -628,7 +677,7 @@ static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //---------
 		/* empty */
 		break;
 	case GL_ALPHA_TEST:
-		//r700SetAlphaState(ctx);
+		r700SetAlphaState(ctx);
 		break;
 	case GL_COLOR_LOGIC_OP:
 		r700SetLogicOpState(ctx);
@@ -1327,9 +1376,7 @@ void r700InitState(GLcontext * ctx) //-------------------
     /* Specify the number of instances */
     r700->VGT_DMA_NUM_INSTANCES.u32All = 1;
 
-    /* not alpha blend */
-    CLEARfield(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_FUNC_mask);
-    CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
+    r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
 
     /* default shader connections. */
     r700->SPI_VS_OUT_ID_0.u32All  = 0x03020100;
-- 
cgit v1.2.3


From 549b8e6f1a372b6cce4a9013854b3c97ba95af2b Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Tue, 21 Jul 2009 13:10:26 -0400
Subject: r600: first pass at polyoffset support

not working yet
---
 src/mesa/drivers/dri/r600/r700_state.c | 119 +++++++++++++++++++++++++++++----
 1 file changed, 106 insertions(+), 13 deletions(-)

(limited to 'src/mesa/drivers/dri/r600/r700_state.c')

diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 5fe4b36b71..eee14b076c 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -57,6 +57,8 @@
 
 
 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
+static void r700UpdatePolygonMode(GLcontext * ctx);
+static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
 
 void r700SetDefaultStates(context_t *context) //--------------------
 {
@@ -613,11 +615,11 @@ static void r700UpdateCulling(GLcontext * ctx)
     CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
     CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
 
-    if (ctx->Polygon.CullFlag) 
+    if (ctx->Polygon.CullFlag)
     {
-        switch (ctx->Polygon.CullFaceMode) 
+        switch (ctx->Polygon.CullFaceMode)
         {
-        case GL_FRONT:            
+        case GL_FRONT:
             SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
             CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
             break;
@@ -636,13 +638,13 @@ static void r700UpdateCulling(GLcontext * ctx)
         }
     }
 
-    switch (ctx->Polygon.FrontFace) 
+    switch (ctx->Polygon.FrontFace)
     {
         case GL_CW:
             SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
             break;
         case GL_CCW:
-            CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); 
+            CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
             break;
         default:
             CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
@@ -705,7 +707,7 @@ static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //---------
 	case GL_POLYGON_OFFSET_POINT:
 	case GL_POLYGON_OFFSET_LINE:
 	case GL_POLYGON_OFFSET_FILL:
-		//r700SetPolygonOffsetState(ctx, state);
+		r700SetPolygonOffsetState(ctx, state);
 		break;
 	case GL_SCISSOR_TEST:
 		radeon_firevertices(&context->radeon);
@@ -782,6 +784,7 @@ static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--
 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
 {
     r700UpdateCulling(ctx);
+    r700UpdatePolygonMode(ctx);
 }
 
 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
@@ -907,15 +910,111 @@ static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
     SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
 }
 
+static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+
+	if (state) {
+		SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
+		SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
+		SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
+	} else {
+		CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
+		CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
+		CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
+	}
+}
+
 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
 {
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	GLfloat constant = units;
+
+	switch (ctx->Visual.depthBits) {
+	case 16:
+		constant *= 4.0;
+		break;
+	case 24:
+		constant *= 2.0;
+		break;
+	}
+
+	factor *= 12.0;
+
+	r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
+	r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
+	r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
+	r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
 }
 
+static void r700UpdatePolygonMode(GLcontext * ctx)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+
+	SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
+
+	/* Only do something if a polygon mode is wanted, default is GL_FILL */
+	if (ctx->Polygon.FrontMode != GL_FILL ||
+	    ctx->Polygon.BackMode != GL_FILL) {
+		GLenum f, b;
+
+		/* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
+		 * correctly by selecting the correct front and back face
+		 */
+		if (ctx->Polygon.FrontFace == GL_CCW) {
+			f = ctx->Polygon.FrontMode;
+			b = ctx->Polygon.BackMode;
+		} else {
+			f = ctx->Polygon.BackMode;
+			b = ctx->Polygon.FrontMode;
+		}
+
+		/* Enable polygon mode */
+		SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
+
+		switch (f) {
+		case GL_LINE:
+			SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
+				 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
+			break;
+		case GL_POINT:
+			SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
+				 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
+			break;
+		case GL_FILL:
+			SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
+				 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
+			break;
+		}
+
+		switch (b) {
+		case GL_LINE:
+			SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
+				 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
+			break;
+		case GL_POINT:
+			SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
+				 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
+			break;
+		case GL_FILL:
+			SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
+				 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
+			break;
+		}
+	}
+}
 
 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
 {
+	(void)face;
+	(void)mode;
+
+	r700UpdatePolygonMode(ctx);
 }
- 
+
 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
 {
 }
@@ -1396,12 +1495,6 @@ void r700InitState(GLcontext * ctx) //-------------------
     r700->DB_SHADER_CONTROL.u32All = 0;
     SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
 
-    /* Set up the culling control register */
-    SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
-             POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
-    SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
-             POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
-
     /* screen */
     r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0;
 
-- 
cgit v1.2.3


From 60787df1e549436557393bbeae5951d8f27c1976 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Tue, 21 Jul 2009 13:19:46 -0400
Subject: r600: fill in r700UpdateViewportOffset

---
 src/mesa/drivers/dri/r600/r700_state.c | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

(limited to 'src/mesa/drivers/dri/r600/r700_state.c')

diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index eee14b076c..d54c6e5c14 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -118,10 +118,21 @@ void r700UpdateShaders (GLcontext * ctx)  //----------------------------------
  */
 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
 {
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	__DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
+	GLfloat xoffset = (GLfloat) dPriv->x;
+	GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
+	const GLfloat *v = ctx->Viewport._WindowMap.m;
+	int id = 0;
 
-	//radeonUpdateScissor(ctx);
+	GLfloat tx = v[MAT_TX] + xoffset;
+	GLfloat ty = (-v[MAT_TY]) + yoffset;
+
+	r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
+	r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
 
-    return;
+	radeonUpdateScissor(ctx);
 }
 
 /**
@@ -311,7 +322,7 @@ static void r700SetAlphaState(GLcontext * ctx)
 {
 	context_t *context = R700_CONTEXT(ctx);
 	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-	uint32_t alpha_func;
+	uint32_t alpha_func = REF_ALWAYS;
 	GLboolean really_enabled = ctx->Color.AlphaEnabled;
 
 	switch (ctx->Color.AlphaFunc) {
-- 
cgit v1.2.3


From 5a615e7e653c1aeab280c6ddfdba3ecb763302ec Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Tue, 21 Jul 2009 13:28:12 -0400
Subject: r600: set provoking vertex to last vertex for OGL

---
 src/mesa/drivers/dri/r600/r700_state.c | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/mesa/drivers/dri/r600/r700_state.c')

diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index d54c6e5c14..9f7e45a4b7 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -1557,6 +1557,9 @@ void r700InitState(GLcontext * ctx) //-------------------
     CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
     SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
 
+    /* GL uses last vtx for flat shading components */
+    SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
+
     /* Set up line control */
     SETfield(r700->PA_SU_LINE_CNTL.u32All, 0x8,
              PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
-- 
cgit v1.2.3


From bd62cd735f8ccf1c983d57440e41a6959260cf9f Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Tue, 21 Jul 2009 13:46:15 -0400
Subject: r600: fill in point functions

---
 src/mesa/drivers/dri/r600/r700_state.c | 53 +++++++++++++++++++++++++++++-----
 1 file changed, 45 insertions(+), 8 deletions(-)

(limited to 'src/mesa/drivers/dri/r600/r700_state.c')

diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 9f7e45a4b7..6b0aa686e7 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -816,8 +816,51 @@ static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
 	}
 }
 
+/* =============================================================
+ * Point state
+ */
+static void r700PointSize(GLcontext * ctx, GLfloat size)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+
+	/* We need to clamp to user defined range here, because
+	 * the HW clamping happens only for per vertex point size. */
+	size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
+
+	/* same size limits for AA, non-AA points */
+	size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
+
+	/* format is 12.4 fixed point */
+	SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
+		 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
+	SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
+		 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
+
+}
+
 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
 {
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+
+	/* format is 12.4 fixed point */
+	switch (pname) {
+	case GL_POINT_SIZE_MIN:
+		SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 16.0),
+			 MIN_SIZE_shift, MIN_SIZE_mask);
+		break;
+	case GL_POINT_SIZE_MAX:
+		SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 16.0),
+			 MAX_SIZE_shift, MAX_SIZE_mask);
+		break;
+	case GL_POINT_DISTANCE_ATTENUATION:
+		break;
+	case GL_POINT_FADE_THRESHOLD_SIZE:
+		break;
+	default:
+		break;
+	}
 }
 
 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
@@ -896,10 +939,6 @@ static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) /
 	r700UpdateWindow(ctx, 0);
 }
 
-static void r700PointSize(GLcontext * ctx, GLfloat size) //-------------------
-{
-}
-
 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
 {
     context_t *context = R700_CONTEXT(ctx);
@@ -1550,10 +1589,8 @@ void r700InitState(GLcontext * ctx) //-------------------
     SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
 
     /* Set up point sizes and min/max values */
-    SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8,
-             PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
-    SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8,
-             PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
+    r700PointSize(ctx, 1.0);
+
     CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
     SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
 
-- 
cgit v1.2.3


From db0160bb9d80843c28965890814f0e957e8bf975 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Tue, 21 Jul 2009 14:06:47 -0400
Subject: r600: use state functions to set default state

---
 src/mesa/drivers/dri/r600/r700_state.c | 92 ++++++++++++++++++++++------------
 1 file changed, 59 insertions(+), 33 deletions(-)

(limited to 'src/mesa/drivers/dri/r600/r700_state.c')

diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 6b0aa686e7..186b811cc3 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -1525,8 +1525,6 @@ void r700InitState(GLcontext * ctx) //-------------------
     /* Specify the number of instances */
     r700->VGT_DMA_NUM_INSTANCES.u32All = 1;
 
-    r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
-
     /* default shader connections. */
     r700->SPI_VS_OUT_ID_0.u32All  = 0x03020100;
     r700->SPI_VS_OUT_ID_1.u32All  = 0x07060504;
@@ -1539,12 +1537,6 @@ void r700InitState(GLcontext * ctx) //-------------------
     if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
 	    SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
 
-    r700SetBlendState(ctx);
-    r700SetLogicOpState(ctx);
-
-    r700->DB_SHADER_CONTROL.u32All = 0;
-    SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
-
     /* screen */
     r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0;
 
@@ -1588,23 +1580,9 @@ void r700InitState(GLcontext * ctx) //-------------------
     SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
     SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
 
-    /* Set up point sizes and min/max values */
-    r700PointSize(ctx, 1.0);
-
-    CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
-    SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
-
     /* GL uses last vtx for flat shading components */
     SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
 
-    /* Set up line control */
-    SETfield(r700->PA_SU_LINE_CNTL.u32All, 0x8,
-             PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
-
-    r700->PA_SC_LINE_CNTL.u32All = 0;
-    CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
-    SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
-
     /* Set up vertex control */
     r700->PA_SU_VTX_CNTL.u32All = 0;
     CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
@@ -1618,7 +1596,66 @@ void r700InitState(GLcontext * ctx) //-------------------
     r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All  = 0x3F800000;
     r700->PA_CL_GB_HORZ_DISC_ADJ.u32All  = 0x3F800000;
 
+    /* Enable all samples for multi-sample anti-aliasing */
+    r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
+    /* Turn off AA */
+    r700->PA_SC_AA_CONFIG.u32All = 0;
+
+    r700->SX_MISC.u32All = 0;
+
+    r700InitSQConfig(ctx);
+
+    r700ColorMask(ctx,
+		  ctx->Color.ColorMask[RCOMP],
+		  ctx->Color.ColorMask[GCOMP],
+		  ctx->Color.ColorMask[BCOMP],
+		  ctx->Color.ColorMask[ACOMP]);
+
+    r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
+    r700DepthMask(ctx, ctx->Depth.Mask);
+    r700DepthFunc(ctx, ctx->Depth.Func);
+    SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
+
+    /* stencil */
+    r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
+    r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
+    r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
+			    ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
+    r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
+			  ctx->Stencil.ZFailFunc[0],
+			  ctx->Stencil.ZPassFunc[0]);
+
+    r700UpdateCulling(ctx);
+
+    r700SetBlendState(ctx);
+    r700SetLogicOpState(ctx);
+
+    r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
+    r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
+
+    r700PointSize(ctx, 1.0);
+
+    CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
+    SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
+
+    r700LineWidth(ctx, 1.0);
+
+    r700->PA_SC_LINE_CNTL.u32All = 0;
+    CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
+    SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
+
+    r700ShadeModel(ctx, ctx->Light.ShadeModel);
+    r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
+    r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
+    r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
+		      ctx->Polygon.OffsetUnits);
+    r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
+    r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
+    r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
+
     /* CB */
+    r700BlendColor(ctx, ctx->Color.BlendColor);
+
     r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
     r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
     r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
@@ -1644,17 +1681,6 @@ void r700InitState(GLcontext * ctx) //-------------------
     /* Set up color compare mask */
     r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
 
-    /* default color mask */
-    SETfield(r700->CB_SHADER_MASK.u32All, 0xF, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
-
-    /* Enable all samples for multi-sample anti-aliasing */
-    r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
-    /* Turn off AA */
-    r700->PA_SC_AA_CONFIG.u32All = 0;
-
-    r700->SX_MISC.u32All = 0;
-
-    r700InitSQConfig(ctx);
 }
 
 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
-- 
cgit v1.2.3


From 72a3d8845f55b4a82f7e3734c8b3aa51b65e220d Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Tue, 21 Jul 2009 17:07:17 -0400
Subject: r600: add stencil support

---
 src/mesa/drivers/dri/r600/r700_state.c | 161 ++++++++++++++++++++++++++++++---
 1 file changed, 146 insertions(+), 15 deletions(-)

(limited to 'src/mesa/drivers/dri/r600/r700_state.c')

diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 186b811cc3..a2ddebb1ce 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -59,6 +59,7 @@
 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
 static void r700UpdatePolygonMode(GLcontext * ctx);
 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
+static void r700SetStencilState(GLcontext * ctx, GLboolean state);
 
 void r700SetDefaultStates(context_t *context) //--------------------
 {
@@ -273,40 +274,40 @@ static void r700SetDepthState(GLcontext * ctx)
 
         switch (ctx->Depth.Func)
         {
-        case GL_NEVER:            
-            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER, 
+        case GL_NEVER:
+            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
                      ZFUNC_shift, ZFUNC_mask);
             break;
         case GL_LESS:
-            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS, 
-                     ZFUNC_shift, ZFUNC_mask);            
+            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
+                     ZFUNC_shift, ZFUNC_mask);
             break;
         case GL_EQUAL:
-            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL, 
+            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
                      ZFUNC_shift, ZFUNC_mask);
             break;
         case GL_LEQUAL:
-            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,  
+            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
                      ZFUNC_shift, ZFUNC_mask);
             break;
         case GL_GREATER:
-            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,  
-                     ZFUNC_shift, ZFUNC_mask);           
+            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
+                     ZFUNC_shift, ZFUNC_mask);
             break;
         case GL_NOTEQUAL:
-            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,  
+            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
                      ZFUNC_shift, ZFUNC_mask);
             break;
         case GL_GEQUAL:
-            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,  
+            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
                      ZFUNC_shift, ZFUNC_mask);
             break;
         case GL_ALWAYS:
-            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,  
+            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
                      ZFUNC_shift, ZFUNC_mask);
             break;
         default:
-            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,  
+            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
                      ZFUNC_shift, ZFUNC_mask);
             break;
         }
@@ -710,7 +711,7 @@ static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //---------
 		r700SetDepthState(ctx);
 		break;
 	case GL_STENCIL_TEST:
-		//r700SetStencilState(ctx, state);
+		r700SetStencilState(ctx, state);
 		break;
 	case GL_CULL_FACE:
 		r700UpdateCulling(ctx);
@@ -863,24 +864,154 @@ static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * pa
 	}
 }
 
+static int translate_stencil_func(int func)
+{
+	switch (func) {
+	case GL_NEVER:
+		return REF_NEVER;
+	case GL_LESS:
+		return REF_LESS;
+	case GL_EQUAL:
+		return REF_EQUAL;
+	case GL_LEQUAL:
+		return REF_LEQUAL;
+	case GL_GREATER:
+		return REF_GREATER;
+	case GL_NOTEQUAL:
+		return REF_NOTEQUAL;
+	case GL_GEQUAL:
+		return REF_GEQUAL;
+	case GL_ALWAYS:
+		return REF_ALWAYS;
+	}
+	return 0;
+}
+
+static int translate_stencil_op(int op)
+{
+	switch (op) {
+	case GL_KEEP:
+		return STENCIL_KEEP;
+	case GL_ZERO:
+		return STENCIL_ZERO;
+	case GL_REPLACE:
+		return STENCIL_REPLACE;
+	case GL_INCR:
+		return STENCIL_INCR_CLAMP;
+	case GL_DECR:
+		return STENCIL_DECR_CLAMP;
+	case GL_INCR_WRAP_EXT:
+		return STENCIL_INCR_WRAP;
+	case GL_DECR_WRAP_EXT:
+		return STENCIL_DECR_WRAP;
+	case GL_INVERT:
+		return STENCIL_INVERT;
+	default:
+		WARN_ONCE("Do not know how to translate stencil op");
+		return STENCIL_KEEP;
+	}
+	return 0;
+}
+
+static void r700SetStencilState(GLcontext * ctx, GLboolean state)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	GLboolean hw_stencil = GL_FALSE;
+
+	//fixme
+	//r300CatchStencilFallback(ctx);
+
+	if (ctx->DrawBuffer) {
+		struct radeon_renderbuffer *rrbStencil
+			= radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
+		hw_stencil = (rrbStencil && rrbStencil->bo);
+	}
+
+	if (hw_stencil) {
+		if (state)
+			SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
+		else
+			CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
+	}
+}
+
 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
 				    GLenum func, GLint ref, GLuint mask) //---------------------
 {
-}
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	const unsigned back = ctx->Stencil._BackFace;
+
+	//fixme
+	//r300CatchStencilFallback(ctx);
+
+	//front
+	SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
+		 STENCILREF_shift, STENCILREF_mask);
+	SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
+		 STENCILMASK_shift, STENCILMASK_mask);
+
+	SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
+		 STENCILFUNC_shift, STENCILFUNC_mask);
 
+	//back
+	SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
+		 STENCILREF_BF_shift, STENCILREF_BF_mask);
+	SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
+		 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
+
+	SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
+		 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
+
+}
 
 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
 {
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	const unsigned back = ctx->Stencil._BackFace;
+
+	//fixme
+	//r300CatchStencilFallback(ctx);
+
+	// front
+	SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
+		 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
+
+	// back
+	SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
+		 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
+
 }
 
 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
 				  GLenum fail, GLenum zfail, GLenum zpass) //--------------------
 {
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	const unsigned back = ctx->Stencil._BackFace;
+
+	//fixme
+	//r300CatchStencilFallback(ctx);
+
+	SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
+		 STENCILFAIL_shift, STENCILFAIL_mask);
+	SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
+		 STENCILZFAIL_shift, STENCILZFAIL_mask);
+	SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
+		 STENCILZPASS_shift, STENCILZPASS_mask);
+
+	SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
+		 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
+	SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
+		 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
+	SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
+		 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
 }
 
 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
 {
-
 	context_t *context = R700_CONTEXT(ctx);
 	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 	__DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
-- 
cgit v1.2.3


From 48b2fea142af93317e095461fc1f7ef6531268c2 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Mon, 27 Jul 2009 02:07:59 -0400
Subject: r600: set VGT NUM_INSTANCES as part of the draw command

set VGT NUM_INSTANCES as part of the draw command rather
than as state as recommended by the pm4 guide.  Also,
use the NUM_INSTANCES packet.
---
 src/mesa/drivers/dri/r600/r700_chip.c   |  1 -
 src/mesa/drivers/dri/r600/r700_chip.h   |  1 -
 src/mesa/drivers/dri/r600/r700_render.c | 30 ++++++++++++++++++------------
 src/mesa/drivers/dri/r600/r700_state.c  |  3 ---
 4 files changed, 18 insertions(+), 17 deletions(-)

(limited to 'src/mesa/drivers/dri/r600/r700_state.c')

diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 899b464c54..e683c8cf92 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -160,7 +160,6 @@ GLboolean r700InitChipObject(context_t *context)
     LINK_STATES(VGT_GROUP_VECT_1_FMT_CNTL);
     LINK_STATES(VGT_GS_MODE);
     LINK_STATES(VGT_PRIMITIVEID_EN);
-    LINK_STATES(VGT_DMA_NUM_INSTANCES);
     LINK_STATES(VGT_MULTI_PRIM_IB_RESET_EN);
     LINK_STATES(VGT_INSTANCE_STEP_RATE_0);
     LINK_STATES(VGT_INSTANCE_STEP_RATE_1);
diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h
index fa419aa499..ca3364bb48 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.h
+++ b/src/mesa/drivers/dri/r600/r700_chip.h
@@ -393,7 +393,6 @@ typedef struct _R700_CHIP_CONTEXT
 	union UINT_FLOAT      	        VGT_GROUP_VECT_1_FMT_CNTL ;  /* 0xA28F */
 	union UINT_FLOAT               	VGT_GS_MODE               ;  /* 0xA290 */
 	union UINT_FLOAT        	VGT_PRIMITIVEID_EN        ;  /* 0xA2A1 */
-	union UINT_FLOAT     	        VGT_DMA_NUM_INSTANCES     ;  /* 0xA2A2 */
 	union UINT_FLOAT	        VGT_MULTI_PRIM_IB_RESET_EN;  /* 0xA2A5 */
 	union UINT_FLOAT  	        VGT_INSTANCE_STEP_RATE_0  ;  /* 0xA2A8 */
 	union UINT_FLOAT  	        VGT_INSTANCE_STEP_RATE_1  ;  /* 0xA2A9 */
diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index 77cbe3cfd0..0a5e041547 100644
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -329,7 +329,7 @@ static GLboolean r700RunRender(GLcontext * ctx,
     r700SendDepthTargetState(context);
 
     /* richard test code */
-    for (i = 0; i < vb->PrimitiveCount; i++) 
+    for (i = 0; i < vb->PrimitiveCount; i++)
     {
         GLuint prim = _tnl_translate_prim(&vb->Primitive[i]);
         GLuint start = vb->Primitive[i].start;
@@ -341,25 +341,31 @@ static GLboolean r700RunRender(GLcontext * ctx,
         unsigned int VGT_INDEX_TYPE     = 0;
         unsigned int VGT_PRIMITIVE_TYPE = 0;
         unsigned int VGT_NUM_INDICES    = 0;
-        
-        numEntires = 2 /* VGT_INDEX_TYPE */
-                     + 3 /* VGT_PRIMITIVE_TYPE */
-                     + numIndices + 3; /* DRAW_INDEX_IMMD */                  
-                     
-        BEGIN_BATCH_NO_AUTOSTATE(numEntires);  
 
-        VGT_INDEX_TYPE |= DI_INDEX_SIZE_32_BIT << INDEX_TYPE_shift;
-
-        R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
-        R600_OUT_BATCH(VGT_INDEX_TYPE);
+        numEntires =   3 /* VGT_PRIMITIVE_TYPE */
+		     + 2 /* VGT_INDEX_TYPE */
+		     + 2 /* NUM_INSTANCES */
+                     + numIndices + 3; /* DRAW_INDEX_IMMD */
 
-        VGT_NUM_INDICES = numIndices;
+        BEGIN_BATCH_NO_AUTOSTATE(numEntires);
 
+	// prim
         VGT_PRIMITIVE_TYPE |= r700PrimitiveType(prim) << VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift;
         R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
         R600_OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX);
         R600_OUT_BATCH(VGT_PRIMITIVE_TYPE);
 
+	// index type
+        VGT_INDEX_TYPE |= DI_INDEX_SIZE_32_BIT << INDEX_TYPE_shift;
+        R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
+        R600_OUT_BATCH(VGT_INDEX_TYPE);
+
+	// num instances
+	R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
+        R600_OUT_BATCH(1);
+
+	// draw packet
+        VGT_NUM_INDICES = numIndices;
         VGT_DRAW_INITIATOR |= DI_SRC_SEL_IMMEDIATE << SOURCE_SELECT_shift;
         VGT_DRAW_INITIATOR |= DI_MAJOR_MODE_0 << MAJOR_MODE_shift;
 
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index a2ddebb1ce..bd0abc06e3 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -1653,9 +1653,6 @@ void r700InitState(GLcontext * ctx) //-------------------
     r700->VGT_MIN_VTX_INDX.u32All      = 0;
     r700->VGT_INDX_OFFSET.u32All    = 0;
 
-    /* Specify the number of instances */
-    r700->VGT_DMA_NUM_INSTANCES.u32All = 1;
-
     /* default shader connections. */
     r700->SPI_VS_OUT_ID_0.u32All  = 0x03020100;
     r700->SPI_VS_OUT_ID_1.u32All  = 0x07060504;
-- 
cgit v1.2.3


From 506bacb8e40b0a170a4b620113506925d2333735 Mon Sep 17 00:00:00 2001
From: Cooper Yuan <cooperyuan@gmail.com>
Date: Tue, 28 Jul 2009 13:57:07 +0800
Subject: R6xx/r7xx: enable flat shading, this can fix quadric/accanti/accpersp

---
 src/mesa/drivers/dri/r600/r700_state.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/mesa/drivers/dri/r600/r700_state.c')

diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index bd0abc06e3..3812b26e13 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -808,9 +808,11 @@ static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
 	switch (mode) {
 	case GL_FLAT:
 		SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
+		SETbit(r700->SPI_PS_INPUT_CNTL_0.u32All, FLAT_SHADE_bit);
 		break;
 	case GL_SMOOTH:
 		CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
+		CLEARbit(r700->SPI_PS_INPUT_CNTL_0.u32All, FLAT_SHADE_bit);
 		break;
 	default:
 		return;
-- 
cgit v1.2.3


From 4d648523aa01af3c9111f5d6394866396ebfb7a2 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Tue, 28 Jul 2009 11:10:38 -0400
Subject: r600: disable flat shade fix in
 506bacb8e40b0a170a4b620113506925d2333735

This breaks textures.  We need to only set this bit for
attributes that that need flat shading.
---
 src/mesa/drivers/dri/r600/r700_state.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/mesa/drivers/dri/r600/r700_state.c')

diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 3812b26e13..5563a63156 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -808,11 +808,11 @@ static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
 	switch (mode) {
 	case GL_FLAT:
 		SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
-		SETbit(r700->SPI_PS_INPUT_CNTL_0.u32All, FLAT_SHADE_bit);
+		//SETbit(r700->SPI_PS_INPUT_CNTL_0.u32All, FLAT_SHADE_bit);
 		break;
 	case GL_SMOOTH:
 		CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
-		CLEARbit(r700->SPI_PS_INPUT_CNTL_0.u32All, FLAT_SHADE_bit);
+		//CLEARbit(r700->SPI_PS_INPUT_CNTL_0.u32All, FLAT_SHADE_bit);
 		break;
 	default:
 		return;
-- 
cgit v1.2.3


From b1f7c844a38418cbf3fbcef6c2fb0606a1dd6b7e Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Tue, 28 Jul 2009 15:53:45 -0400
Subject: r600: move r700TranslateFragmentShader into r700UpdateShaders

---
 src/mesa/drivers/dri/r600/r700_render.c | 17 -----------------
 src/mesa/drivers/dri/r600/r700_state.c  | 22 +++++++++++++++++++---
 2 files changed, 19 insertions(+), 20 deletions(-)

(limited to 'src/mesa/drivers/dri/r600/r700_state.c')

diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index 5a2bf84b59..ea8419d3d2 100644
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -276,20 +276,12 @@ static GLboolean r700RunRender(GLcontext * ctx,
     context_t *context = R700_CONTEXT(ctx);
     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
     int lastIndex = 0;
-#if 1
     BATCH_LOCALS(&context->radeon);
 
     unsigned int i, j;
     TNLcontext *tnl = TNL_CONTEXT(ctx);
     struct vertex_buffer *vb = &tnl->vb;
 
-    struct r700_fragment_program *fp = (struct r700_fragment_program *)
-	                                   (ctx->FragmentProgram._Current);
-    if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
-    {
-        fp->r700AsmCode.bR6xx = 1;
-    }
-
     r700Start3D(context); /* TODO : this is too much. */
 
     r700SendSQConfig(context);
@@ -308,14 +300,6 @@ static GLboolean r700RunRender(GLcontext * ctx,
     r600UpdateTextureState(ctx);
     r700SendTextureState(context);
 
-    if(GL_FALSE == fp->translated)
-    {
-        if( GL_FALSE == r700TranslateFragmentShader(fp, &(fp->mesa_program)) )
-        {
-            return GL_TRUE;
-        }
-    }
-
     r700SetupShaders(ctx);
 
     r700SendFSState(context); // FIXME just a place holder for now
@@ -391,7 +375,6 @@ static GLboolean r700RunRender(GLcontext * ctx,
 
     radeonReleaseArrays(ctx, 0);
 
-#endif //0
     rcommonFlushCmdBuf( &context->radeon, __FUNCTION__ );
 
     return GL_FALSE;
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 5563a63156..c24c859ef5 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -72,12 +72,28 @@ void r700UpdateShaders (GLcontext * ctx)  //----------------------------------
 
     GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
     GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
-
-    struct r700_vertex_program *vp;
-	int i;
+    int i;
+
+    if (ctx->FragmentProgram._Current) {
+	    struct r700_fragment_program *fp = (struct r700_fragment_program *)
+		    (ctx->FragmentProgram._Current);
+	    if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
+	    {
+		    fp->r700AsmCode.bR6xx = 1;
+	    }
+
+	    if(GL_FALSE == fp->translated)
+	    {
+		    if( GL_FALSE == r700TranslateFragmentShader(fp, &(fp->mesa_program)) )
+		    {
+			    //return GL_TRUE;
+		    }
+	    }
+    }
 
     if (context->radeon.NewGLState) 
     {
+	struct r700_vertex_program *vp;
         context->radeon.NewGLState = 0;
 
         for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) 
-- 
cgit v1.2.3


From 719abd7fc088c5ebc567e9ea20bdd6fc9fe1af3b Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Tue, 28 Jul 2009 16:58:41 -0400
Subject: r600: fix flat shading

Set the flat shading bit on the appropriate PS input
depending on the type of attribute it is.  The VS output
and PS input routing should probably be made more dynamic
at some point.  We may want to use semantic ids to make
it easier.
---
 src/mesa/drivers/dri/r600/r700_chip.c     | 44 ++++++-----------------
 src/mesa/drivers/dri/r600/r700_chip.h     | 33 +-----------------
 src/mesa/drivers/dri/r600/r700_fragprog.c | 58 ++++++++++++++++++++++++++-----
 src/mesa/drivers/dri/r600/r700_state.c    |  6 ----
 4 files changed, 60 insertions(+), 81 deletions(-)

(limited to 'src/mesa/drivers/dri/r600/r700_state.c')

diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index e683c8cf92..c083862f36 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -213,39 +213,6 @@ GLboolean r700InitChipObject(context_t *context)
     LINK_STATES(SPI_VS_OUT_ID_8);
     LINK_STATES(SPI_VS_OUT_ID_9);
 
-    LINK_STATES(SPI_PS_INPUT_CNTL_0);
-    LINK_STATES(SPI_PS_INPUT_CNTL_1);
-    LINK_STATES(SPI_PS_INPUT_CNTL_2);
-    LINK_STATES(SPI_PS_INPUT_CNTL_3);
-    LINK_STATES(SPI_PS_INPUT_CNTL_4);
-    LINK_STATES(SPI_PS_INPUT_CNTL_5);
-    LINK_STATES(SPI_PS_INPUT_CNTL_6);
-    LINK_STATES(SPI_PS_INPUT_CNTL_7);
-    LINK_STATES(SPI_PS_INPUT_CNTL_8);
-    LINK_STATES(SPI_PS_INPUT_CNTL_9);
-    LINK_STATES(SPI_PS_INPUT_CNTL_10);
-    LINK_STATES(SPI_PS_INPUT_CNTL_11);
-    LINK_STATES(SPI_PS_INPUT_CNTL_12);
-    LINK_STATES(SPI_PS_INPUT_CNTL_13);
-    LINK_STATES(SPI_PS_INPUT_CNTL_14);
-    LINK_STATES(SPI_PS_INPUT_CNTL_15);
-    LINK_STATES(SPI_PS_INPUT_CNTL_16);
-    LINK_STATES(SPI_PS_INPUT_CNTL_17);
-    LINK_STATES(SPI_PS_INPUT_CNTL_18);
-    LINK_STATES(SPI_PS_INPUT_CNTL_19);
-    LINK_STATES(SPI_PS_INPUT_CNTL_20);
-    LINK_STATES(SPI_PS_INPUT_CNTL_21);
-    LINK_STATES(SPI_PS_INPUT_CNTL_22);
-    LINK_STATES(SPI_PS_INPUT_CNTL_23);
-    LINK_STATES(SPI_PS_INPUT_CNTL_24);
-    LINK_STATES(SPI_PS_INPUT_CNTL_25);
-    LINK_STATES(SPI_PS_INPUT_CNTL_26);
-    LINK_STATES(SPI_PS_INPUT_CNTL_27);
-    LINK_STATES(SPI_PS_INPUT_CNTL_28);
-    LINK_STATES(SPI_PS_INPUT_CNTL_29);
-    LINK_STATES(SPI_PS_INPUT_CNTL_30);
-    LINK_STATES(SPI_PS_INPUT_CNTL_31);
-
     LINK_STATES(SPI_VS_OUT_CONFIG);
     LINK_STATES(SPI_THREAD_GROUPING);
     LINK_STATES(SPI_PS_IN_CONTROL_0);
@@ -435,12 +402,21 @@ GLboolean r700SendContextStates(context_t *context)
         };
         END_BATCH();
     };
+
+    /* todo:
+     * - split this into a separate function?
+     * - only emit the ones we use
+     */
+    BEGIN_BATCH_NO_AUTOSTATE(2 + R700_MAX_SHADER_EXPORTS);
+    R600_OUT_BATCH_REGSEQ(SPI_PS_INPUT_CNTL_0, R700_MAX_SHADER_EXPORTS);
+    for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++)
+	    R600_OUT_BATCH(r700->SPI_PS_INPUT_CNTL[ui].u32All);
+    END_BATCH();
     COMMIT_BATCH();
 
     return GL_TRUE;
 }
 
-
 GLboolean r700SendDepthTargetState(context_t *context, int id)
 {
 	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h
index ca3364bb48..4e89c75f2f 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.h
+++ b/src/mesa/drivers/dri/r600/r700_chip.h
@@ -455,38 +455,7 @@ typedef struct _R700_CHIP_CONTEXT
 	union UINT_FLOAT        	SQ_VTX_SEMANTIC_30        ;  /* 0xA0FE */
 	union UINT_FLOAT        	SQ_VTX_SEMANTIC_31        ;  /* 0xA0FF */
 
-	union UINT_FLOAT       	SPI_PS_INPUT_CNTL_0       ;  /* 0xA191 */
-	union UINT_FLOAT       	SPI_PS_INPUT_CNTL_1       ;  /* 0xA192 */
-	union UINT_FLOAT       	SPI_PS_INPUT_CNTL_2       ;  /* 0xA193 */
-	union UINT_FLOAT       	SPI_PS_INPUT_CNTL_3       ;  /* 0xA194 */
-	union UINT_FLOAT       	SPI_PS_INPUT_CNTL_4       ;  /* 0xA195 */
-	union UINT_FLOAT       	SPI_PS_INPUT_CNTL_5       ;  /* 0xA196 */
-	union UINT_FLOAT       	SPI_PS_INPUT_CNTL_6       ;  /* 0xA197 */
-	union UINT_FLOAT       	SPI_PS_INPUT_CNTL_7       ;  /* 0xA198 */
-	union UINT_FLOAT       	SPI_PS_INPUT_CNTL_8       ;  /* 0xA199 */
-	union UINT_FLOAT       	SPI_PS_INPUT_CNTL_9       ;  /* 0xA19A */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_10      ;  /* 0xA19B */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_11      ;  /* 0xA19C */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_12      ;  /* 0xA19D */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_13      ;  /* 0xA19E */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_14      ;  /* 0xA19F */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_15      ;  /* 0xA1A0 */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_16      ;  /* 0xA1A1 */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_17      ;  /* 0xA1A2 */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_18      ;  /* 0xA1A3 */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_19      ;  /* 0xA1A4 */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_20      ;  /* 0xA1A5 */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_21      ;  /* 0xA1A6 */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_22      ;  /* 0xA1A7 */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_23      ;  /* 0xA1A8 */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_24      ;  /* 0xA1A9 */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_25      ;  /* 0xA1AA */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_26      ;  /* 0xA1AB */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_27      ;  /* 0xA1AC */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_28      ;  /* 0xA1AD */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_29      ;  /* 0xA1AE */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_30      ;  /* 0xA1AF */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_31      ;  /* 0xA1B0 */
+	union UINT_FLOAT       	SPI_PS_INPUT_CNTL[R700_MAX_SHADER_EXPORTS];
 
 	// shaders
 	PS_STATE_STRUCT                 ps;
diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c
index 3afd0b0528..88e66491ba 100644
--- a/src/mesa/drivers/dri/r600/r700_fragprog.c
+++ b/src/mesa/drivers/dri/r600/r700_fragprog.c
@@ -255,20 +255,20 @@ void * r700GetActiveFpShaderBo(GLcontext * ctx)
 
 GLboolean r700SetupFragmentProgram(GLcontext * ctx)
 {
-    context_t *context = R700_CONTEXT(ctx);   
+    context_t *context = R700_CONTEXT(ctx);
     BATCH_LOCALS(&context->radeon);
-    
     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 
     struct r700_fragment_program *fp = (struct r700_fragment_program *)
 	                                   (ctx->FragmentProgram._Current);
-
+    r700_AssemblerBase         *pAsm = &(fp->r700AsmCode);
+    struct gl_fragment_program *mesa_fp = &(fp->mesa_program);
     struct gl_program_parameter_list *paramList;
     unsigned int unNumParamData;
-    unsigned int ui;
-
+    unsigned int ui, i;
     unsigned int unNumOfReg;
-    
+    unsigned int unBit;
+
     if(GL_FALSE == fp->loaded)
     {
         if(fp->r700Shader.bNeedsAssembly == GL_TRUE)
@@ -277,11 +277,11 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
 	    }
 
         /* Load fp to gpu */
-        r600EmitShader(ctx, 
-                       &(fp->shaderbo), 
+        r600EmitShader(ctx,
+                       &(fp->shaderbo),
                        (GLvoid *)(fp->r700Shader.pProgram),
                        fp->r700Shader.uShaderBinaryDWORDSize,
-                       "FS");    			                
+                       "FS");
 
         fp->loaded = GL_TRUE;
     }
@@ -362,6 +362,46 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
         COMMIT_BATCH();
     }
 
+    // emit ps input map
+    unBit = 1 << FRAG_ATTRIB_COL0;
+    if(mesa_fp->Base.InputsRead & unBit)
+    {
+	    ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL0];
+	    SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
+	    SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
+		     SEMANTIC_shift, SEMANTIC_mask);
+	    if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
+		    SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
+	    else
+		    CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
+    }
+
+    unBit = 1 << FRAG_ATTRIB_COL1;
+    if(mesa_fp->Base.InputsRead & unBit)
+    {
+	    ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1];
+	    SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
+	    SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
+		     SEMANTIC_shift, SEMANTIC_mask);
+	    if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
+		    SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
+	    else
+		    CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
+    }
+
+    for(i=0; i<8; i++)
+    {
+	    unBit = 1 << (FRAG_ATTRIB_TEX0 + i);
+	    if(mesa_fp->Base.InputsRead & unBit)
+	    {
+		    ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_TEX0 + i];
+		    SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
+		    SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
+			     SEMANTIC_shift, SEMANTIC_mask);
+		    CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
+	    }
+    }
+
     return GL_TRUE;
 }
 
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index c24c859ef5..87ea1719c4 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -824,11 +824,9 @@ static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
 	switch (mode) {
 	case GL_FLAT:
 		SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
-		//SETbit(r700->SPI_PS_INPUT_CNTL_0.u32All, FLAT_SHADE_bit);
 		break;
 	case GL_SMOOTH:
 		CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
-		//CLEARbit(r700->SPI_PS_INPUT_CNTL_0.u32All, FLAT_SHADE_bit);
 		break;
 	default:
 		return;
@@ -1675,10 +1673,6 @@ void r700InitState(GLcontext * ctx) //-------------------
     r700->SPI_VS_OUT_ID_0.u32All  = 0x03020100;
     r700->SPI_VS_OUT_ID_1.u32All  = 0x07060504;
 
-    r700->SPI_PS_INPUT_CNTL_0.u32All  = 0x00000800;
-    r700->SPI_PS_INPUT_CNTL_1.u32All  = 0x00000801;
-    r700->SPI_PS_INPUT_CNTL_2.u32All  = 0x00000802;
-
     r700->SPI_THREAD_GROUPING.u32All = 0;
     if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
 	    SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
-- 
cgit v1.2.3


From 1e207ba9c127d12feff3e1c2e8e29da26182e0bb Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Wed, 29 Jul 2009 15:15:36 -0400
Subject: r600: minor fixes

- set MAX_LOD properly
- min texel pitch is 8 texels
- emit old command buffer when re-initing base state
---
 src/mesa/drivers/dri/r600/r600_tex.c      |  2 +-
 src/mesa/drivers/dri/r600/r600_texstate.c | 13 +++++++++++++
 src/mesa/drivers/dri/r600/r700_state.c    |  3 ++-
 3 files changed, 16 insertions(+), 2 deletions(-)

(limited to 'src/mesa/drivers/dri/r600/r700_state.c')

diff --git a/src/mesa/drivers/dri/r600/r600_tex.c b/src/mesa/drivers/dri/r600/r600_tex.c
index 853f824b2c..6d531bf0f9 100644
--- a/src/mesa/drivers/dri/r600/r600_tex.c
+++ b/src/mesa/drivers/dri/r600/r600_tex.c
@@ -160,7 +160,7 @@ static void r600SetTexDefaultState(radeonTexObjPtr t)
         SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_BORDER_COLOR_TRANS_BLACK, BORDER_COLOR_TYPE_shift, BORDER_COLOR_TYPE_mask);
 
         t->SQ_TEX_SAMPLER1                           = 0;
-        SETfield(t->SQ_TEX_SAMPLER1, MAX_LOD_mask, MAX_LOD_shift, MAX_LOD_mask);
+        SETfield(t->SQ_TEX_SAMPLER1, 0x3ff, MAX_LOD_shift, MAX_LOD_mask);
 
         t->SQ_TEX_SAMPLER2                          = 0;
         SETbit(t->SQ_TEX_SAMPLER2, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit);
diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c
index 1cf3b484ae..70dd540481 100644
--- a/src/mesa/drivers/dri/r600/r600_texstate.c
+++ b/src/mesa/drivers/dri/r600/r600_texstate.c
@@ -598,6 +598,10 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex
 	uTexelPitch = (firstImage->Width + R700_TEXEL_PITCH_ALIGNMENT_MASK)
 		& ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
 
+	/* min pitch is 8 */
+	if (uTexelPitch < 8)
+		uTexelPitch = 8;
+
 	SETfield(t->SQ_TEX_RESOURCE0, (uTexelPitch/8)-1, PITCH_shift, PITCH_mask);
 	SETfield(t->SQ_TEX_RESOURCE0, firstImage->Width - 1,
 		 TEX_WIDTH_shift, TEX_WIDTH_mask);
@@ -751,6 +755,11 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
 
 	pitch_val = (pitch_val + R700_TEXEL_PITCH_ALIGNMENT_MASK)
 		& ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
+
+	/* min pitch is 8 */
+	if (pitch_val < 8)
+		pitch_val = 8;
+
 	SETfield(t->SQ_TEX_RESOURCE0, (pitch_val/8)-1, PITCH_shift, PITCH_mask);
 }
 
@@ -898,6 +907,10 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
 	pitch_val = (pitch_val + R700_TEXEL_PITCH_ALIGNMENT_MASK)
 		& ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
 
+	/* min pitch is 8 */
+	if (pitch_val < 8)
+		pitch_val = 8;
+
 	SETfield(t->SQ_TEX_RESOURCE0, (pitch_val/8)-1, PITCH_shift, PITCH_mask);
 	SETfield(t->SQ_TEX_RESOURCE0, rb->base.Width - 1,
 		 TEX_WIDTH_shift, TEX_WIDTH_mask);
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 87ea1719c4..e0a5742591 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -1638,9 +1638,10 @@ static void r700InitSQConfig(GLcontext * ctx)
 void r700InitState(GLcontext * ctx) //-------------------
 {
     context_t *context = R700_CONTEXT(ctx);
-
     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 
+    radeon_firevertices(&context->radeon);
+
     r700->TA_CNTL_AUX.u32All = 0;
     SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
     r700->VC_ENHANCE.u32All = 0;
-- 
cgit v1.2.3


From 562ca4961186954d3abf216bcfb1e835b562b234 Mon Sep 17 00:00:00 2001
From: vehemens <vehemens@verizon.net>
Date: Sun, 2 Aug 2009 18:03:58 -0400
Subject: r600: Logic Operations Fix

fixes bug 23087
---
 src/mesa/drivers/dri/r600/r700_state.c | 42 ++++++++++++++++++++++++++++++----
 1 file changed, 37 insertions(+), 5 deletions(-)

(limited to 'src/mesa/drivers/dri/r600/r700_state.c')

diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index e0a5742591..b75f531503 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -600,14 +600,46 @@ static void r700BlendFuncSeparate(GLcontext * ctx,
 
 /**
  * Translate LogicOp enums into hardware representation.
- * Both use a very logical bit-wise layout, but unfortunately the order
- * of bits is reversed.
  */
 static GLuint translate_logicop(GLenum logicop)
 {
-	GLuint bits = logicop - GL_CLEAR;
-	bits = ((bits & 1) << 3) | ((bits & 2) << 1) | ((bits & 4) >> 1) | ((bits & 8) >> 3);
-	return bits;
+	switch (logicop) {
+	case GL_CLEAR:
+		return 0x00;
+	case GL_SET:
+		return 0xff;
+	case GL_COPY:
+		return 0xcc;
+	case GL_COPY_INVERTED:
+		return 0x33;
+	case GL_NOOP:
+		return 0xaa;
+	case GL_INVERT:
+		return 0x55;
+	case GL_AND:
+		return 0x88;
+	case GL_NAND:
+		return 0x77;
+	case GL_OR:
+		return 0xee;
+	case GL_NOR:
+		return 0x11;
+	case GL_XOR:
+		return 0x66;
+	case GL_EQUIV:
+		return 0xaa;
+	case GL_AND_REVERSE:
+		return 0x44;
+	case GL_AND_INVERTED:
+		return 0x22;
+	case GL_OR_REVERSE:
+		return 0xdd;
+	case GL_OR_INVERTED:
+		return 0xbb;
+	default:
+		fprintf(stderr, "unknown blend logic operation %x\n", logicop);
+		return 0xcc;
+	}
 }
 
 /**
-- 
cgit v1.2.3


From d07bf2b35c1419bdef824092e509c70ffb11fd67 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Sun, 2 Aug 2009 18:26:12 -0400
Subject: r600: handle state emit better

- move shader-related state with the rest of the shader setup/emit
- start to track dirty state better
---
 src/mesa/drivers/dri/r600/r600_cmdbuf.c |  3 +++
 src/mesa/drivers/dri/r600/r700_render.c | 19 +++++++++++--------
 src/mesa/drivers/dri/r600/r700_state.c  |  2 ++
 3 files changed, 16 insertions(+), 8 deletions(-)

(limited to 'src/mesa/drivers/dri/r600/r700_state.c')

diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c
index 8debecbab9..dc2fb0144a 100644
--- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c
+++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c
@@ -457,6 +457,9 @@ void r600InitCmdBuf(context_t *r600) /* from rcommonInitCmdBuf */
     GLuint size;
     rmesa->hw.max_state_size = 4000; /* rough estimate */
 
+    rmesa->hw.all_dirty = GL_TRUE;
+    rmesa->hw.is_dirty = GL_TRUE;
+
 	/* Initialize command buffer */
 	size = 256 * driQueryOptioni(&rmesa->optionCache,
 				     "command_buffer_size");
diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index 34a4385841..20376d2c36 100644
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -139,6 +139,13 @@ static GLboolean r700SetupShaders(GLcontext * ctx)
 
     r600UpdateTextureState(ctx);
 
+    r700SendFSState(context); // FIXME just a place holder for now
+    r700SendPSState(context);
+    r700SendVSState(context);
+
+    r700SendTextureState(context);
+    r700SetupStreams(ctx);
+
     return GL_TRUE;
 }
 
@@ -274,18 +281,16 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim
 void r700EmitState(GLcontext * ctx)
 {
 	context_t *context = R700_CONTEXT(ctx);
+	radeonContextPtr radeon = &context->radeon;
+
+	if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw.all_dirty)
+		return;
 
 	rcommonEnsureCmdBufSpace(&context->radeon,
 				 context->radeon.hw.max_state_size, __FUNCTION__);
 
 	r700Start3D(context);
 	r700SendSQConfig(context);
-	r700SendFSState(context); // FIXME just a place holder for now
-	r700SendPSState(context);
-	r700SendVSState(context);
-
-	r700SendTextureState(context);
-	r700SetupStreams(ctx);
 
 	r700SendUCPState(context);
 	r700SendContextStates(context);
@@ -325,8 +330,6 @@ static GLboolean r700RunRender(GLcontext * ctx,
 
     radeonReleaseArrays(ctx, ~0);
 
-    rcommonFlushCmdBuf( &context->radeon, __FUNCTION__ );
-
     return GL_FALSE;
 }
 
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index b75f531503..e95f52400a 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -1854,6 +1854,8 @@ void r700InitState(GLcontext * ctx) //-------------------
     /* Set up color compare mask */
     r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
 
+    context->radeon.hw.all_dirty = GL_TRUE;
+
 }
 
 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
-- 
cgit v1.2.3


From ef3ad412c746203727324edbd4cbe04079332d7c Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 12 Aug 2009 11:12:46 -0700
Subject: radeon: Minor warnings cleanup.

---
 src/mesa/drivers/dri/r600/r600_context.h            | 11 +++++++++++
 src/mesa/drivers/dri/r600/r700_clear.c              |  1 +
 src/mesa/drivers/dri/r600/r700_oglprog.c            |  2 +-
 src/mesa/drivers/dri/r600/r700_state.c              |  2 --
 src/mesa/drivers/dri/radeon/radeon_common_context.c |  7 +++----
 5 files changed, 16 insertions(+), 7 deletions(-)

(limited to 'src/mesa/drivers/dri/r600/r700_state.c')

diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h
index fbb8164af5..30ddce682c 100644
--- a/src/mesa/drivers/dri/r600/r600_context.h
+++ b/src/mesa/drivers/dri/r600/r600_context.h
@@ -158,6 +158,17 @@ extern GLboolean r700InitChipObject(context_t *context);
 extern GLboolean r700SendContextStates(context_t *context);
 extern GLboolean r700SendViewportState(context_t *context, int id);
 extern GLboolean r700SendRenderTargetState(context_t *context, int id);
+extern GLboolean r700SendTextureState(context_t *context);
+extern GLboolean r700SendDepthTargetState(context_t *context);
+extern GLboolean r700SendUCPState(context_t *context);
+extern GLboolean r700SendFSState(context_t *context);
+extern void r700EmitState(GLcontext * ctx);
+
+extern GLboolean r700SyncSurf(context_t *context,
+			      struct radeon_bo *pbo,
+			      uint32_t read_domain,
+			      uint32_t write_domain,
+			      uint32_t sync_type);
 
 extern int       r700SetupStreams(GLcontext * ctx);
 extern void      r700SetupVTXConstants(GLcontext  * ctx, 
diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c
index e84be38622..05d4af331e 100644
--- a/src/mesa/drivers/dri/r600/r700_clear.c
+++ b/src/mesa/drivers/dri/r600/r700_clear.c
@@ -31,6 +31,7 @@
 #include "main/imports.h"
 #include "main/mtypes.h"
 #include "main/enums.h"
+#include "swrast/swrast.h"
 
 #include "radeon_lock.h"
 #include "r600_context.h"
diff --git a/src/mesa/drivers/dri/r600/r700_oglprog.c b/src/mesa/drivers/dri/r600/r700_oglprog.c
index 36de143b1a..c49b90c1cc 100644
--- a/src/mesa/drivers/dri/r600/r700_oglprog.c
+++ b/src/mesa/drivers/dri/r600/r700_oglprog.c
@@ -33,6 +33,7 @@
 #include "tnl/tnl.h"
 
 #include "r600_context.h"
+#include "r600_emit.h"
 
 #include "r700_oglprog.h"
 #include "r700_fragprog.h"
@@ -87,7 +88,6 @@ static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog)
 {
     struct r700_vertex_program   * vp;
     struct r700_fragment_program * fp;
-    context_t *context = R700_CONTEXT(ctx);
 
     switch (prog->Target) 
     {
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index e95f52400a..7f54cf9f56 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -179,8 +179,6 @@ static void r700FetchStateParameter(GLcontext * ctx,
 			                        const gl_state_index state[STATE_LENGTH],
 			                        GLfloat * value)
 {
-	context_t *context = R700_CONTEXT(ctx);
-
     /* TODO */
 }
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index d68aa2bd62..3a9468e88d 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -295,11 +295,10 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv )
 	GET_CURRENT_CONTEXT(ctx);
 	radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
 	radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL;
-
-    /* +r6/r7 */
-    __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
+#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) /* +r6/r7 */
+	__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
 	radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
-    /* --------- */
+#endif
 
 	if (radeon == current) {
 		radeon_firevertices(radeon);
-- 
cgit v1.2.3


From b0c191acaf0fbbfa743781908187344f5081a083 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Wed, 12 Aug 2009 15:34:24 -0400
Subject: r600: state cleanups

---
 src/mesa/drivers/dri/r600/r700_chip.c   |  2 +-
 src/mesa/drivers/dri/r600/r700_render.c |  6 +--
 src/mesa/drivers/dri/r600/r700_state.c  | 80 +++++++++++++++------------------
 src/mesa/drivers/dri/r600/r700_state.h  |  4 +-
 4 files changed, 40 insertions(+), 52 deletions(-)

(limited to 'src/mesa/drivers/dri/r600/r700_state.c')

diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 78779e841d..e5e0f556cb 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -322,7 +322,7 @@ void r700SetupVTXConstants(GLcontext  * ctx,
     unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0;
 
     if (!paos->bo)
-	    return GL_FALSE;
+	    return;
 
     if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
 	(context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index 20376d2c36..6705dbcf4b 100644
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -289,7 +289,6 @@ void r700EmitState(GLcontext * ctx)
 	rcommonEnsureCmdBufSpace(&context->radeon,
 				 context->radeon.hw.max_state_size, __FUNCTION__);
 
-	r700Start3D(context);
 	r700SendSQConfig(context);
 
 	r700SendUCPState(context);
@@ -308,13 +307,12 @@ static GLboolean r700RunRender(GLcontext * ctx,
     TNLcontext *tnl = TNL_CONTEXT(ctx);
     struct vertex_buffer *vb = &tnl->vb;
 
+    r700Start3D(context);
+
     r700UpdateShaders(ctx);
     r700SetScissor(context);
     r700SetupShaders(ctx);
 
-    r700SetRenderTarget(context, 0);
-    r700SetDepthTarget(context);
-
     r700EmitState(ctx);
 
     /* richard test code */
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 7f54cf9f56..835b5e18c2 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -60,6 +60,8 @@ static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
 static void r700UpdatePolygonMode(GLcontext * ctx);
 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
 static void r700SetStencilState(GLcontext * ctx, GLboolean state);
+static void r700SetRenderTarget(context_t *context, int id);
+static void r700SetDepthTarget(context_t *context);
 
 void r700SetDefaultStates(context_t *context) //--------------------
 {
@@ -158,21 +160,10 @@ void r700UpdateViewportOffset(GLcontext * ctx) //------------------
  */
 void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
 {
-#if 0 /* to be enabled */
-    context_t *context = R700_CONTEXT(ctx);
+	context_t *context = R700_CONTEXT(ctx);
 
-    switch (ctx->DrawBuffer->_ColorDrawBufferIndexes[0]) 
-    {
-	case BUFFER_FRONT_LEFT:
-	    context->target.rt = context->screen->frontBuffer;
-	    break;
-	case BUFFER_BACK_LEFT:
-	    context->target.rt = context->screen->backBuffer;
-	    break;
-	default:
-	    memset (&context->target.rt, sizeof(context->target.rt), 0);
-	}
-#endif /* to be enabled */
+	r700SetRenderTarget(context, 0);
+	r700SetDepthTarget(context);
 }
 
 static void r700FetchStateParameter(GLcontext * ctx,
@@ -1357,22 +1348,22 @@ void r700SetScissor(context_t *context) //---------------
 	r700->viewport[id].enabled = GL_TRUE;
 }
 
-void r700SetRenderTarget(context_t *context, int id)
+static void r700SetRenderTarget(context_t *context, int id)
 {
     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 
     struct radeon_renderbuffer *rrb;
     unsigned int nPitchInPixel;
 
+    rrb = radeon_get_colorbuffer(&context->radeon);
+    if (!rrb || !rrb->bo) {
+	    fprintf(stderr, "no rrb\n");
+	    return;
+    }
+
     /* screen/window/view */
     SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
 
-    rrb = radeon_get_colorbuffer(&context->radeon);
-	if (!rrb || !rrb->bo) {
-		fprintf(stderr, "no rrb\n");
-		return;
-	}
-
     /* color buffer */
     r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
 
@@ -1405,39 +1396,22 @@ void r700SetRenderTarget(context_t *context, int id)
     r700->render_target[id].enabled = GL_TRUE;
 }
 
-void r700SetDepthTarget(context_t *context)
+static void r700SetDepthTarget(context_t *context)
 {
     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 
     struct radeon_renderbuffer *rrb;
     unsigned int nPitchInPixel;
 
+    rrb = radeon_get_depthbuffer(&context->radeon);
+    if (!rrb)
+	    return;
+
     /* depth buf */
     r700->DB_DEPTH_SIZE.u32All = 0;
     r700->DB_DEPTH_BASE.u32All = 0;
     r700->DB_DEPTH_INFO.u32All = 0;
-
-    r700->DB_DEPTH_CLEAR.u32All     = 0x3F800000;
-    r700->DB_DEPTH_VIEW.u32All      = 0;
-    r700->DB_RENDER_CONTROL.u32All  = 0;
-    SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
-    SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
-    r700->DB_RENDER_OVERRIDE.u32All = 0;
-    if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
-	    SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
-    SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
-    SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
-    SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
-
-    r700->DB_ALPHA_TO_MASK.u32All = 0;
-    SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
-    SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
-    SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
-    SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
-
-    rrb = radeon_get_depthbuffer(&context->radeon);
-	if (!rrb)
-		return;
+    r700->DB_DEPTH_VIEW.u32All = 0;
 
     nPitchInPixel = rrb->pitch/rrb->cpp;
 
@@ -1787,6 +1761,24 @@ void r700InitState(GLcontext * ctx) //-------------------
     r700DepthFunc(ctx, ctx->Depth.Func);
     SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
 
+    r700->DB_DEPTH_CLEAR.u32All     = 0x3F800000;
+
+    r700->DB_RENDER_CONTROL.u32All  = 0;
+    SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
+    SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
+    r700->DB_RENDER_OVERRIDE.u32All = 0;
+    if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
+	    SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
+    SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
+    SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
+    SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
+
+    r700->DB_ALPHA_TO_MASK.u32All = 0;
+    SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
+    SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
+    SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
+    SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
+
     /* stencil */
     r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
     r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
diff --git a/src/mesa/drivers/dri/r600/r700_state.h b/src/mesa/drivers/dri/r600/r700_state.h
index 23246367db..30eb54e8b0 100644
--- a/src/mesa/drivers/dri/r600/r700_state.h
+++ b/src/mesa/drivers/dri/r600/r700_state.h
@@ -42,10 +42,8 @@ extern void r700UpdateDrawBuffer (GLcontext * ctx);
 extern void r700InitState (GLcontext * ctx);
 extern void r700InitStateFuncs (struct dd_function_table *functions);
 
-extern void r700SetRenderTarget(context_t *context, int id);
 extern void r700SetDefaultStates(context_t * context);
 
-void r700SetScissor(context_t *context);
-void r700SetDepthTarget(context_t *context);
+extern void r700SetScissor(context_t *context);
 
 #endif	/* _R600_SCREEN_H */
-- 
cgit v1.2.3