From 368fb578f86c53d888324f9bb25369216b3187b1 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Sat, 19 Sep 2009 14:46:06 -0400 Subject: r600: fix polygon offset --- src/mesa/drivers/dri/r600/r700_state.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index e91aa43118..8477c88c58 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -1130,20 +1130,25 @@ static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) // context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); GLfloat constant = units; + GLchar depth = 0; + + R600_STATECHANGE(context, poly); switch (ctx->Visual.depthBits) { case 16: constant *= 4.0; + depth = -16; break; case 24: constant *= 2.0; + depth = -24; break; } factor *= 12.0; - - R600_STATECHANGE(context, poly); - + SETfield(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All, depth, + POLY_OFFSET_NEG_NUM_DB_BITS_shift, POLY_OFFSET_NEG_NUM_DB_BITS_mask); + //r700->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //??? r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor; r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant; r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor; -- cgit v1.2.3 From b8477f079bd72d15b2d4e9c1453374d744da5ce7 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Sat, 19 Sep 2009 15:18:42 -0400 Subject: r600: fix point sizes registers takes radius --- src/mesa/drivers/dri/r600/r700_state.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 8477c88c58..fc0b511684 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -845,9 +845,9 @@ static void r700PointSize(GLcontext * ctx, GLfloat size) size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize); /* format is 12.4 fixed point */ - SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16), + SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0), PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask); - SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16), + SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0), PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask); } @@ -862,11 +862,11 @@ static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * pa /* format is 12.4 fixed point */ switch (pname) { case GL_POINT_SIZE_MIN: - SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 16.0), + SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 8.0), MIN_SIZE_shift, MIN_SIZE_mask); break; case GL_POINT_SIZE_MAX: - SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 16.0), + SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 8.0), MAX_SIZE_shift, MAX_SIZE_mask); break; case GL_POINT_DISTANCE_ATTENUATION: -- cgit v1.2.3 From 2d729e6e3bcb0af84790cafb9824a3937954e078 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 21 Sep 2009 10:14:25 -0400 Subject: r600: fix some issues with LIT instruction - MUL_LIT is ALU.Trans instruction - some Trans instructions can take 3 arguments - don't clobber dst.x, use dst.z as temp, it'll get written correct value in last insn - respect source swizzles --- src/mesa/drivers/dri/r600/r700_assembler.c | 69 ++++++++++++++++-------------- 1 file changed, 36 insertions(+), 33 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index efeccb25f1..f46bc32201 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -2024,7 +2024,7 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) return GL_FALSE; } - if (pAsm->D.dst.math == 0) + if (uNumSrc > 1) { // Process source 1 current_source_index = 1; @@ -2880,6 +2880,11 @@ GLboolean assemble_LIT(r700_AssemblerBase *pAsm) return GL_FALSE; } + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + /* dst.y = max(src.x, 0.0) */ pAsm->D.dst.opcode = SQ_OP2_INST_MAX; pAsm->D.dst.rtype = dstType; @@ -2891,11 +2896,6 @@ GLboolean assemble_LIT(r700_AssemblerBase *pAsm) pAsm->S[0].src.rtype = srcType; pAsm->S[0].src.reg = srcReg; setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); - noneg_PVSSRC(&(pAsm->S[0].src)); - pAsm->S[0].src.swizzlex = SQ_SEL_X; - pAsm->S[0].src.swizzley = SQ_SEL_X; - pAsm->S[0].src.swizzlez = SQ_SEL_X; - pAsm->S[0].src.swizzlew = SQ_SEL_X; pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; pAsm->S[1].src.reg = tmp; setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); @@ -2909,34 +2909,47 @@ GLboolean assemble_LIT(r700_AssemblerBase *pAsm) return GL_FALSE; } - /* before: dst.w = log(src.y) - * after : dst.x = log(src.y) - * why change dest register is that dst.w has been initialized as 1 before - */ + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_Y, SQ_SEL_Y, SQ_SEL_Y, SQ_SEL_Y); + + /* dst.z = log(src.y) */ pAsm->D.dst.opcode = SQ_OP2_INST_LOG_CLAMPED; pAsm->D.dst.math = 1; pAsm->D.dst.rtype = dstType; pAsm->D.dst.reg = dstReg; - pAsm->D.dst.writex = 1; + pAsm->D.dst.writex = 0; pAsm->D.dst.writey = 0; - pAsm->D.dst.writez = 0; + pAsm->D.dst.writez = 1; pAsm->D.dst.writew = 0; pAsm->S[0].src.rtype = srcType; pAsm->S[0].src.reg = srcReg; setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); - noneg_PVSSRC(&(pAsm->S[0].src)); - pAsm->S[0].src.swizzlex = SQ_SEL_Y; - pAsm->S[0].src.swizzley = SQ_SEL_Y; - pAsm->S[0].src.swizzlez = SQ_SEL_Y; - pAsm->S[0].src.swizzlew = SQ_SEL_Y; if( GL_FALSE == next_ins(pAsm) ) { return GL_FALSE; } - /* before: tmp.x = amd MUL_LIT(src.w, dst.w, src.x ) */ - /* after : tmp.x = amd MUL_LIT(src.w, dst.x, src.x ) */ + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 0, 2) ) + { + return GL_FALSE; + } + + swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_W, SQ_SEL_W, SQ_SEL_W, SQ_SEL_W); + + swizzleagain_PVSSRC(&(pAsm->S[2].src), SQ_SEL_X, SQ_SEL_X, SQ_SEL_X, SQ_SEL_X); + + /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */ pAsm->D.dst.opcode = SQ_OP3_INST_MUL_LIT; + pAsm->D.dst.math = 1; pAsm->D.dst.op3 = 1; pAsm->D.dst.rtype = DST_REG_TEMPORARY; pAsm->D.dst.reg = tmp; @@ -2948,29 +2961,19 @@ GLboolean assemble_LIT(r700_AssemblerBase *pAsm) pAsm->S[0].src.rtype = srcType; pAsm->S[0].src.reg = srcReg; setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); - noneg_PVSSRC(&(pAsm->S[0].src)); - pAsm->S[0].src.swizzlex = SQ_SEL_W; - pAsm->S[0].src.swizzley = SQ_SEL_W; - pAsm->S[0].src.swizzlez = SQ_SEL_W; - pAsm->S[0].src.swizzlew = SQ_SEL_W; pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; pAsm->S[1].src.reg = dstReg; setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); noneg_PVSSRC(&(pAsm->S[1].src)); - pAsm->S[1].src.swizzlex = SQ_SEL_X; - pAsm->S[1].src.swizzley = SQ_SEL_X; - pAsm->S[1].src.swizzlez = SQ_SEL_X; - pAsm->S[1].src.swizzlew = SQ_SEL_X; + pAsm->S[1].src.swizzlex = SQ_SEL_Z; + pAsm->S[1].src.swizzley = SQ_SEL_Z; + pAsm->S[1].src.swizzlez = SQ_SEL_Z; + pAsm->S[1].src.swizzlew = SQ_SEL_Z; pAsm->S[2].src.rtype = srcType; pAsm->S[2].src.reg = srcReg; setaddrmode_PVSSRC(&(pAsm->S[2].src), ADDR_ABSOLUTE); - noneg_PVSSRC(&(pAsm->S[2].src)); - pAsm->S[2].src.swizzlex = SQ_SEL_X; - pAsm->S[2].src.swizzley = SQ_SEL_X; - pAsm->S[2].src.swizzlez = SQ_SEL_X; - pAsm->S[2].src.swizzlew = SQ_SEL_X; if( GL_FALSE == next_ins(pAsm) ) { -- cgit v1.2.3 From 1869bdabbac0926c7da8bfd9e22616cab9457126 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 21 Sep 2009 16:30:14 -0400 Subject: r600: various cleanups - max texture size is 8k, but mesa doesn't support that at the moment. - attempt to set shader limits to what the hw actually supports - clean up some old r300 cruft - no need to explicitly disable irqs. This is fixed in the drm now. Signed-off-by: Alex Deucher --- src/mesa/drivers/dri/r600/r600_context.c | 43 +++++++++++----------- src/mesa/drivers/dri/r600/r600_context.h | 19 ---------- .../drivers/dri/radeon/radeon_common_context.c | 7 +--- 3 files changed, 24 insertions(+), 45 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index f8fd9c13d7..6a90a5bcd1 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -284,8 +284,8 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, ctx->Const.MaxTextureMaxAnisotropy = 16.0; ctx->Const.MaxTextureLodBias = 16.0; - ctx->Const.MaxTextureLevels = 13; - ctx->Const.MaxTextureRectSize = 4096; + ctx->Const.MaxTextureLevels = 13; /* hw support 14 */ + ctx->Const.MaxTextureRectSize = 4096; /* hw support 8192 */ ctx->Const.MinPointSize = 0x0001 / 8.0; ctx->Const.MinPointSizeAA = 0x0001 / 8.0; @@ -331,25 +331,26 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, _tnl_allow_vertex_fog(ctx, GL_TRUE); /* currently bogus data */ - ctx->Const.VertexProgram.MaxInstructions = VSF_MAX_FRAGMENT_LENGTH / 4; - ctx->Const.VertexProgram.MaxNativeInstructions = - VSF_MAX_FRAGMENT_LENGTH / 4; - ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */ - ctx->Const.VertexProgram.MaxTemps = 32; - ctx->Const.VertexProgram.MaxNativeTemps = - /*VSF_MAX_FRAGMENT_TEMPS */ 32; - ctx->Const.VertexProgram.MaxNativeParameters = 256; /* r420 */ - ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; - - ctx->Const.FragmentProgram.MaxNativeTemps = PFS_NUM_TEMP_REGS; - ctx->Const.FragmentProgram.MaxNativeAttribs = 11; /* copy i915... */ - ctx->Const.FragmentProgram.MaxNativeParameters = PFS_NUM_CONST_REGS; - ctx->Const.FragmentProgram.MaxNativeAluInstructions = PFS_MAX_ALU_INST; - ctx->Const.FragmentProgram.MaxNativeTexInstructions = PFS_MAX_TEX_INST; - ctx->Const.FragmentProgram.MaxNativeInstructions = - PFS_MAX_ALU_INST + PFS_MAX_TEX_INST; - ctx->Const.FragmentProgram.MaxNativeTexIndirections = - PFS_MAX_TEX_INDIRECT; + ctx->Const.VertexProgram.MaxInstructions = 8192; /* in theory no limit */ + ctx->Const.VertexProgram.MaxNativeInstructions = 8192; + ctx->Const.VertexProgram.MaxNativeAttribs = 160; + ctx->Const.VertexProgram.MaxTemps = 256; /* 256 for reg-based constants, inline consts also supported */ + ctx->Const.VertexProgram.MaxNativeTemps = 256; + ctx->Const.VertexProgram.MaxNativeParameters = 256; /* ??? */ + ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; /* ??? */ + + ctx->Const.FragmentProgram.MaxNativeTemps = 256; + ctx->Const.FragmentProgram.MaxNativeAttribs = 32; + ctx->Const.FragmentProgram.MaxNativeParameters = 256; + ctx->Const.FragmentProgram.MaxNativeAluInstructions = 8192; + /* 8 per clause on r6xx, 16 on rv670/r7xx */ + if ((screen->chip_family == CHIP_FAMILY_RV670) || + (screen->chip_family >= CHIP_FAMILY_RV770)) + ctx->Const.FragmentProgram.MaxNativeTexInstructions = 16; + else + ctx->Const.FragmentProgram.MaxNativeTexInstructions = 8; + ctx->Const.FragmentProgram.MaxNativeInstructions = 8192; + ctx->Const.FragmentProgram.MaxNativeTexIndirections = 8; /* ??? */ ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0; /* and these are?? */ ctx->VertexProgram._MaintainTnlProgram = GL_TRUE; ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE; diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index c59df7505a..9397ecde81 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -86,29 +86,10 @@ extern int hw_tcl_on; #include "tnl_dd/t_dd_vertex.h" #undef TAG -#define PFS_MAX_ALU_INST 64 -#define PFS_MAX_TEX_INST 64 -#define PFS_MAX_TEX_INDIRECT 4 -#define PFS_NUM_TEMP_REGS 32 -#define PFS_NUM_CONST_REGS 16 - -#define R600_MAX_AOS_ARRAYS 16 - -#define REG_COORDS 0 -#define REG_COLOR0 1 -#define REG_TEX0 2 - #define R600_FALLBACK_NONE 0 #define R600_FALLBACK_TCL 1 #define R600_FALLBACK_RAST 2 -enum -{ - NO_SHIFT = 0, - LEFT_SHIFT = 1, - RIGHT_SHIFT = 2, -}; - struct r600_hw_state { struct radeon_state_atom sq; struct radeon_state_atom db; diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index 1c53c04da7..6b9b1e3c5e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -227,11 +227,8 @@ GLboolean radeonInitContext(radeonContextPtr radeon, fthrottle_mode = driQueryOptioni(&radeon->optionCache, "fthrottle_mode"); radeon->iw.irq_seq = -1; radeon->irqsEmitted = 0; - if (IS_R600_CLASS(radeon->radeonScreen)) - radeon->do_irqs = 0; - else - radeon->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS && - radeon->radeonScreen->irq); + radeon->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS && + radeon->radeonScreen->irq); radeon->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); -- cgit v1.2.3 From c63e78b3e583e39ef296f1c2c9a34c90eb221503 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 21 Sep 2009 16:48:55 -0400 Subject: r600: fix typo in the last commit 128 gprs, 256 reg-based consts --- src/mesa/drivers/dri/r600/r600_context.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 6a90a5bcd1..354b263f5c 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -330,16 +330,16 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, _tnl_allow_pixel_fog(ctx, GL_FALSE); _tnl_allow_vertex_fog(ctx, GL_TRUE); - /* currently bogus data */ + /* 256 for reg-based consts, inline consts also supported */ ctx->Const.VertexProgram.MaxInstructions = 8192; /* in theory no limit */ ctx->Const.VertexProgram.MaxNativeInstructions = 8192; ctx->Const.VertexProgram.MaxNativeAttribs = 160; - ctx->Const.VertexProgram.MaxTemps = 256; /* 256 for reg-based constants, inline consts also supported */ - ctx->Const.VertexProgram.MaxNativeTemps = 256; - ctx->Const.VertexProgram.MaxNativeParameters = 256; /* ??? */ + ctx->Const.VertexProgram.MaxTemps = 128; + ctx->Const.VertexProgram.MaxNativeTemps = 128; + ctx->Const.VertexProgram.MaxNativeParameters = 256; ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; /* ??? */ - ctx->Const.FragmentProgram.MaxNativeTemps = 256; + ctx->Const.FragmentProgram.MaxNativeTemps = 128; ctx->Const.FragmentProgram.MaxNativeAttribs = 32; ctx->Const.FragmentProgram.MaxNativeParameters = 256; ctx->Const.FragmentProgram.MaxNativeAluInstructions = 8192; -- cgit v1.2.3 From 81283b0bf0a8f7b31517adc224c20531e27fab42 Mon Sep 17 00:00:00 2001 From: Richard Li Date: Tue, 22 Sep 2009 16:39:11 -0400 Subject: r600 : add draw_prim support. --- src/mesa/drivers/dri/r600/Makefile | 1 + src/mesa/drivers/dri/r600/r600_context.c | 3 + src/mesa/drivers/dri/r600/r600_context.h | 32 ++ src/mesa/drivers/dri/r600/r700_assembler.c | 127 ++++ src/mesa/drivers/dri/r600/r700_assembler.h | 8 + src/mesa/drivers/dri/r600/r700_chip.c | 100 +++- src/mesa/drivers/dri/r600/r700_render.c | 667 +++++++++++++++++++++- src/mesa/drivers/dri/r600/r700_shader.c | 90 +++ src/mesa/drivers/dri/r600/r700_shader.h | 1 + src/mesa/drivers/dri/r600/r700_state.c | 20 +- src/mesa/drivers/dri/r600/r700_state.h | 1 + src/mesa/drivers/dri/r600/r700_vertprog.c | 195 ++++++- src/mesa/drivers/dri/r600/r700_vertprog.h | 17 +- src/mesa/drivers/dri/r600/radeon_buffer_objects.c | 1 + src/mesa/drivers/dri/r600/radeon_buffer_objects.h | 1 + 15 files changed, 1217 insertions(+), 47 deletions(-) create mode 120000 src/mesa/drivers/dri/r600/radeon_buffer_objects.c create mode 120000 src/mesa/drivers/dri/r600/radeon_buffer_objects.h (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/Makefile b/src/mesa/drivers/dri/r600/Makefile index 36bf773c05..7d5a7b1ab6 100644 --- a/src/mesa/drivers/dri/r600/Makefile +++ b/src/mesa/drivers/dri/r600/Makefile @@ -29,6 +29,7 @@ COMMON_SOURCES = \ RADEON_COMMON_SOURCES = \ radeon_bo_legacy.c \ radeon_common_context.c \ + radeon_buffer_objects.c \ radeon_common.c \ radeon_cs_legacy.c \ radeon_dma.c \ diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 354b263f5c..6fc6d9d7bf 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -257,6 +257,7 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, r600InitTextureFuncs(&functions); r700InitShaderFuncs(&functions); r700InitIoctlFuncs(&functions); + radeonInitBufferObjectFuncs(&functions); if (!radeonInitContext(&r600->radeon, &functions, glVisual, driContextPriv, @@ -375,6 +376,8 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc"); } + r700InitDraw(ctx); + radeon_fbo_init(&r600->radeon); radeonInitSpanFuncs( ctx ); diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index 9397ecde81..a296ea23fa 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -126,6 +126,34 @@ struct r600_hw_state { struct radeon_state_atom tx_brdr_clr; }; +typedef struct StreamDesc +{ + GLint size; //number of data element + GLenum type; //data element type + GLsizei stride; + + struct radeon_bo *bo; + GLint bo_offset; + + GLuint dwords; + GLuint dst_loc; + GLuint _signed; + GLboolean normalize; + GLboolean is_named_bo; + GLubyte element; +} StreamDesc; + +typedef struct r700_index_buffer +{ + struct radeon_bo *bo; + int bo_offset; + + GLboolean is_32bit; + GLuint count; + + GLboolean bHostIb; +} r700_index_buffer; + /** * \brief R600 context structure. */ @@ -144,6 +172,9 @@ struct r600_context { GLvector4f dummy_attrib[_TNL_ATTRIB_MAX]; GLvector4f *temp_attrib[_TNL_ATTRIB_MAX]; + GLint nNumActiveAos; + StreamDesc stream_desc[VERT_ATTRIB_MAX]; + struct r700_index_buffer ind_buf; }; #define R700_CONTEXT(ctx) ((context_t *)(ctx->DriverCtx)) @@ -177,6 +208,7 @@ extern GLboolean r700SyncSurf(context_t *context, extern void r700SetupStreams(GLcontext * ctx); extern void r700Start3D(context_t *context); extern void r600InitAtoms(context_t *context); +extern void r700InitDraw(GLcontext *ctx); #define RADEON_D_CAPTURE 0 #define RADEON_D_PLAYBACK 1 diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index f46bc32201..81269350e4 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -786,6 +786,133 @@ GLboolean assemble_vfetch_instruction(r700_AssemblerBase* pAsm, return GL_TRUE; } +GLboolean assemble_vfetch_instruction2(r700_AssemblerBase* pAsm, + GLuint destination_register, + GLenum type, + GLint size, + GLubyte element, + GLuint _signed, + GLboolean normalize, + VTX_FETCH_METHOD * pFetchMethod) +{ + GLuint client_size_inbyte; + GLuint data_format; + GLuint mega_fetch_count; + GLuint is_mega_fetch_flag; + + R700VertexGenericFetch* vfetch_instruction_ptr; + R700VertexGenericFetch* assembled_vfetch_instruction_ptr + = pAsm->vfetch_instruction_ptr_array[element]; + + if (assembled_vfetch_instruction_ptr == NULL) + { + vfetch_instruction_ptr = (R700VertexGenericFetch*) CALLOC_STRUCT(R700VertexGenericFetch); + if (vfetch_instruction_ptr == NULL) + { + return GL_FALSE; + } + Init_R700VertexGenericFetch(vfetch_instruction_ptr); + } + else + { + vfetch_instruction_ptr = assembled_vfetch_instruction_ptr; + } + + data_format = GetSurfaceFormat(type, size, &client_size_inbyte); + + if(GL_TRUE == pFetchMethod->bEnableMini) //More conditions here + { + //TODO : mini fetch + } + else + { + mega_fetch_count = MEGA_FETCH_BYTES - 1; + is_mega_fetch_flag = 0x1; + pFetchMethod->mega_fetch_remainder = MEGA_FETCH_BYTES - client_size_inbyte; + } + + vfetch_instruction_ptr->m_Word0.f.vtx_inst = SQ_VTX_INST_FETCH; + vfetch_instruction_ptr->m_Word0.f.fetch_type = SQ_VTX_FETCH_VERTEX_DATA; + vfetch_instruction_ptr->m_Word0.f.fetch_whole_quad = 0x0; + + vfetch_instruction_ptr->m_Word0.f.buffer_id = element; + vfetch_instruction_ptr->m_Word0.f.src_gpr = 0x0; + vfetch_instruction_ptr->m_Word0.f.src_rel = SQ_ABSOLUTE; + vfetch_instruction_ptr->m_Word0.f.src_sel_x = SQ_SEL_X; + vfetch_instruction_ptr->m_Word0.f.mega_fetch_count = mega_fetch_count; + + vfetch_instruction_ptr->m_Word1.f.dst_sel_x = (size < 1) ? SQ_SEL_0 : SQ_SEL_X; + vfetch_instruction_ptr->m_Word1.f.dst_sel_y = (size < 2) ? SQ_SEL_0 : SQ_SEL_Y; + vfetch_instruction_ptr->m_Word1.f.dst_sel_z = (size < 3) ? SQ_SEL_0 : SQ_SEL_Z; + vfetch_instruction_ptr->m_Word1.f.dst_sel_w = (size < 4) ? SQ_SEL_1 : SQ_SEL_W; + + vfetch_instruction_ptr->m_Word1.f.use_const_fields = 1; + vfetch_instruction_ptr->m_Word1.f.data_format = data_format; + vfetch_instruction_ptr->m_Word2.f.endian_swap = SQ_ENDIAN_NONE; + + if(1 == _signed) + { + vfetch_instruction_ptr->m_Word1.f.format_comp_all = SQ_FORMAT_COMP_SIGNED; + } + else + { + vfetch_instruction_ptr->m_Word1.f.format_comp_all = SQ_FORMAT_COMP_UNSIGNED; + } + + if(GL_TRUE == normalize) + { + vfetch_instruction_ptr->m_Word1.f.num_format_all = SQ_NUM_FORMAT_NORM; + } + else + { + vfetch_instruction_ptr->m_Word1.f.num_format_all = SQ_NUM_FORMAT_INT; + } + + // Destination register + vfetch_instruction_ptr->m_Word1_GPR.f.dst_gpr = destination_register; + vfetch_instruction_ptr->m_Word1_GPR.f.dst_rel = SQ_ABSOLUTE; + + vfetch_instruction_ptr->m_Word2.f.offset = 0; + vfetch_instruction_ptr->m_Word2.f.const_buf_no_stride = 0x0; + + vfetch_instruction_ptr->m_Word2.f.mega_fetch = is_mega_fetch_flag; + + if (assembled_vfetch_instruction_ptr == NULL) + { + if ( GL_FALSE == add_vfetch_instruction(pAsm, (R700VertexInstruction *)vfetch_instruction_ptr) ) + { + return GL_FALSE; + } + + if (pAsm->vfetch_instruction_ptr_array[element] != NULL) + { + return GL_FALSE; + } + else + { + pAsm->vfetch_instruction_ptr_array[element] = vfetch_instruction_ptr; + } + } + + return GL_TRUE; +} + +GLboolean cleanup_vfetch_instructions(r700_AssemblerBase* pAsm) +{ + GLint i; + pAsm->cf_current_clause_type = CF_EMPTY_CLAUSE; + pAsm->cf_current_vtx_clause_ptr = NULL; + + for (i=0; ivfetch_instruction_ptr_array[ i ] = NULL; + } + + cleanup_vfetch_shaderinst(pAsm->pR700Shader); + + return GL_TRUE; +} + GLuint gethelpr(r700_AssemblerBase* pAsm) { GLuint r = pAsm->uHelpReg; diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index f9c4d849c6..4e6e20011a 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -411,6 +411,14 @@ GLboolean assemble_vfetch_instruction(r700_AssemblerBase* pAsm, GLuint number_of_elements, GLenum dataElementType, VTX_FETCH_METHOD* pFetchMethod); +GLboolean assemble_vfetch_instruction2(r700_AssemblerBase* pAsm, + GLuint destination_register, + GLenum type, + GLint size, + GLubyte element, + GLuint _signed, + GLboolean normalize, + VTX_FETCH_METHOD * pFetchMethod); GLuint gethelpr(r700_AssemblerBase* pAsm); void resethelpr(r700_AssemblerBase* pAsm); void checkop_init(r700_AssemblerBase* pAsm); diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 06d7e9c9ab..783427a94c 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -208,6 +208,80 @@ static void r700SetupVTXConstants(GLcontext * ctx, } +extern int getTypeSize(GLenum type); +static void r700SetupVTXConstants2(GLcontext * ctx, + void * pAos, + StreamDesc * pStreamDesc) +{ + context_t *context = R700_CONTEXT(ctx); + struct radeon_aos * paos = (struct radeon_aos *)pAos; + unsigned int nVBsize; + BATCH_LOCALS(&context->radeon); + + unsigned int uSQ_VTX_CONSTANT_WORD0_0; + unsigned int uSQ_VTX_CONSTANT_WORD1_0; + unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0; + unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0; + unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0; + + if (!paos->bo) + return; + + if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) || + (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) || + (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) || + (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) || + (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710)) + r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit); + else + r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit); + + if(0 == pStreamDesc->stride) + { + nVBsize = paos->count * pStreamDesc->size * getTypeSize(pStreamDesc->type); + } + else + { + nVBsize = paos->count * pStreamDesc->stride; + } + + uSQ_VTX_CONSTANT_WORD0_0 = paos->offset; + uSQ_VTX_CONSTANT_WORD1_0 = nVBsize - 1; + + SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); /* TODO */ + SETfield(uSQ_VTX_CONSTANT_WORD2_0, pStreamDesc->stride, SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift, + SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask); + SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(pStreamDesc->type, pStreamDesc->size, NULL), + SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift, + SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); /* TODO : trace back api for initial data type, not only GL_FLOAT */ + SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_SCALED, + SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask); + SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit); + + SETfield(uSQ_VTX_CONSTANT_WORD3_0, 1, MEM_REQUEST_SIZE_shift, MEM_REQUEST_SIZE_mask); + SETfield(uSQ_VTX_CONSTANT_WORD6_0, SQ_TEX_VTX_VALID_BUFFER, + SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask); + + BEGIN_BATCH_NO_AUTOSTATE(9 + 2); + + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); + R600_OUT_BATCH((pStreamDesc->element + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0); + R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0, + paos->bo, + uSQ_VTX_CONSTANT_WORD0_0, + RADEON_GEM_DOMAIN_GTT, 0, 0); + END_BATCH(); + COMMIT_BATCH(); + +} + void r700SetupStreams(GLcontext *ctx) { context_t *context = R700_CONTEXT(ctx); @@ -256,14 +330,24 @@ static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); for(i=0; imesa_program->Base.InputsRead & (1 << i)) { - /* currently aos are packed */ - r700SetupVTXConstants(ctx, - i, - (void*)(&context->radeon.tcl.aos[j]), - (unsigned int)context->radeon.tcl.aos[j].components, - (unsigned int)context->radeon.tcl.aos[j].stride * 4, - (unsigned int)context->radeon.tcl.aos[j].count); + if(vp->mesa_program->Base.InputsRead & (1 << i)) + { + if(1 == context->selected_vp->uiVersion) + { + /* currently aos are packed */ + r700SetupVTXConstants(ctx, + i, + (void*)(&context->radeon.tcl.aos[j]), + (unsigned int)context->radeon.tcl.aos[j].components, + (unsigned int)context->radeon.tcl.aos[j].stride * 4, + (unsigned int)context->radeon.tcl.aos[j].count); + } + else + { /* context->selected_vp->uiVersion == 2 : aos not always packed */ + r700SetupVTXConstants2(ctx, + (void*)(&context->radeon.tcl.aos[j]), + &(context->stream_desc[j])); + } j++; } } diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index b1c3648ca5..b58859b6ba 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -43,6 +43,7 @@ #include "tnl/t_context.h" #include "tnl/t_vertex.h" #include "tnl/t_pipeline.h" +#include "vbo/vbo_context.h" #include "r600_context.h" #include "r600_cmdbuf.h" @@ -53,6 +54,7 @@ #include "r700_fragprog.h" #include "r700_state.h" +#include "radeon_buffer_objects.h" #include "radeon_common_context.h" void r700WaitForIdle(context_t *context); @@ -270,46 +272,82 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim if (type < 0 || num_indices <= 0) return; - total_emit = 3 /* VGT_PRIMITIVE_TYPE */ - + 2 /* VGT_INDEX_TYPE */ - + 2 /* NUM_INSTANCES */ - + num_indices + 3; /* DRAW_INDEX_IMMD */ + total_emit = 3 /* VGT_PRIMITIVE_TYPE */ + + 2 /* VGT_INDEX_TYPE */ + + 2 /* NUM_INSTANCES */ + + num_indices + 3; /* DRAW_INDEX_IMMD */ - BEGIN_BATCH_NO_AUTOSTATE(total_emit); + BEGIN_BATCH_NO_AUTOSTATE(total_emit); // prim - SETfield(vgt_primitive_type, type, - VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask); - R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); - R600_OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); - R600_OUT_BATCH(vgt_primitive_type); + SETfield(vgt_primitive_type, type, + VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + R600_OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); + R600_OUT_BATCH(vgt_primitive_type); // index type - SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask); - R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); - R600_OUT_BATCH(vgt_index_type); + SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask); + R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); + R600_OUT_BATCH(vgt_index_type); // num instances R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0)); R600_OUT_BATCH(1); // draw packet - vgt_num_indices = num_indices; - SETfield(vgt_draw_initiator, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask); + vgt_num_indices = num_indices; + SETfield(vgt_draw_initiator, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask); SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask); - R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (num_indices + 1))); - R600_OUT_BATCH(vgt_num_indices); - R600_OUT_BATCH(vgt_draw_initiator); + R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (num_indices + 1))); + R600_OUT_BATCH(vgt_num_indices); + R600_OUT_BATCH(vgt_draw_initiator); + if(NULL == context->ind_buf.bo) + { for (i = start; i < (start + num_indices); i++) { - if(vb->Elts) - R600_OUT_BATCH(vb->Elts[i]); - else - R600_OUT_BATCH(i); + if(vb->Elts) + { + R600_OUT_BATCH(vb->Elts[i]); + } + else + R600_OUT_BATCH(i); } - END_BATCH(); - COMMIT_BATCH(); + } + else + { + if(GL_TRUE == context->ind_buf.bHostIb) + { + if(GL_TRUE != context->ind_buf.is_32bit) + { + GLushort * pIndex = (GLushort*)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset); + pIndex += start; + for (i = 0; i < num_indices; i++) + { + R600_OUT_BATCH(*pIndex); + pIndex++; + } + } + else + { + GLuint * pIndex = (GLuint*)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset); + pIndex += start; + + for (i = 0; i < num_indices; i++) + { + R600_OUT_BATCH(*pIndex); + pIndex++; + } + } + } + else + { + /* TODO : hw ib draw */ + } + } + END_BATCH(); + COMMIT_BATCH(); } /* start 3d, idle, cb/db flush */ @@ -477,4 +515,585 @@ const struct tnl_pipeline_stage *r700_pipeline[] = 0, }; +#define CONVERT( TYPE, MACRO ) do { \ + GLuint i, j, sz; \ + sz = input->Size; \ + if (input->Normalized) { \ + for (i = 0; i < count; i++) { \ + const TYPE *in = (TYPE *)src_ptr; \ + for (j = 0; j < sz; j++) { \ + *dst_ptr++ = MACRO(*in); \ + in++; \ + } \ + src_ptr += stride; \ + } \ + } else { \ + for (i = 0; i < count; i++) { \ + const TYPE *in = (TYPE *)src_ptr; \ + for (j = 0; j < sz; j++) { \ + *dst_ptr++ = (GLfloat)(*in); \ + in++; \ + } \ + src_ptr += stride; \ + } \ + } \ +} while (0) + +/** + * Convert attribute data type to float + * If the attribute uses named buffer object replace the bo with newly allocated bo + */ +static void r700ConvertAttrib(GLcontext *ctx, int count, + const struct gl_client_array *input, + struct StreamDesc *attr) +{ + context_t *context = R700_CONTEXT(ctx); + const GLvoid *src_ptr; + GLboolean mapped_named_bo = GL_FALSE; + GLfloat *dst_ptr; + GLuint stride; + + stride = (input->StrideB == 0) ? getTypeSize(input->Type) * input->Size : input->StrideB; + + /* Convert value for first element only */ + if (input->StrideB == 0) + { + count = 1; + } + + if (input->BufferObj->Name) + { + if (!input->BufferObj->Pointer) + { + ctx->Driver.MapBuffer(ctx, GL_ARRAY_BUFFER, GL_READ_ONLY_ARB, input->BufferObj); + mapped_named_bo = GL_TRUE; + } + + src_ptr = ADD_POINTERS(input->BufferObj->Pointer, input->Ptr); + } + else + { + src_ptr = input->Ptr; + } + + radeonAllocDmaRegion(&context->radeon, &attr->bo, &attr->bo_offset, + sizeof(GLfloat) * input->Size * count, 32); + dst_ptr = (GLfloat *)ADD_POINTERS(attr->bo->ptr, attr->bo_offset); + + assert(src_ptr != NULL); + + switch (input->Type) + { + case GL_DOUBLE: + CONVERT(GLdouble, (GLfloat)); + break; + case GL_UNSIGNED_INT: + CONVERT(GLuint, UINT_TO_FLOAT); + break; + case GL_INT: + CONVERT(GLint, INT_TO_FLOAT); + break; + case GL_UNSIGNED_SHORT: + CONVERT(GLushort, USHORT_TO_FLOAT); + break; + case GL_SHORT: + CONVERT(GLshort, SHORT_TO_FLOAT); + break; + case GL_UNSIGNED_BYTE: + assert(input->Format != GL_BGRA); + CONVERT(GLubyte, UBYTE_TO_FLOAT); + break; + case GL_BYTE: + CONVERT(GLbyte, BYTE_TO_FLOAT); + break; + default: + assert(0); + break; + } + + if (mapped_named_bo) + { + ctx->Driver.UnmapBuffer(ctx, GL_ARRAY_BUFFER, input->BufferObj); + } +} + +static void r700AlignDataToDword(GLcontext *ctx, + const struct gl_client_array *input, + int count, + struct StreamDesc *attr) +{ + context_t *context = R700_CONTEXT(ctx); + const int dst_stride = (input->StrideB + 3) & ~3; + const int size = getTypeSize(input->Type) * input->Size * count; + GLboolean mapped_named_bo = GL_FALSE; + + radeonAllocDmaRegion(&context->radeon, &attr->bo, &attr->bo_offset, size, 32); + + if (!input->BufferObj->Pointer) + { + ctx->Driver.MapBuffer(ctx, GL_ARRAY_BUFFER, GL_READ_ONLY_ARB, input->BufferObj); + mapped_named_bo = GL_TRUE; + } + + { + GLvoid *src_ptr = ADD_POINTERS(input->BufferObj->Pointer, input->Ptr); + GLvoid *dst_ptr = ADD_POINTERS(attr->bo->ptr, attr->bo_offset); + int i; + + for (i = 0; i < count; ++i) + { + _mesa_memcpy(dst_ptr, src_ptr, input->StrideB); + src_ptr += input->StrideB; + dst_ptr += dst_stride; + } + } + + if (mapped_named_bo) + { + ctx->Driver.UnmapBuffer(ctx, GL_ARRAY_BUFFER, input->BufferObj); + } + + attr->stride = dst_stride; +} + +static void r700SetupStreams2(GLcontext *ctx, const struct gl_client_array *input[], int count) +{ + context_t *context = R700_CONTEXT(ctx); + GLuint stride; + int ret; + int i, index; + + R600_STATECHANGE(context, vtx); + + for(index = 0; index < context->nNumActiveAos; index++) + { + struct radeon_aos *aos = &context->radeon.tcl.aos[index]; + i = context->stream_desc[index].element; + + stride = (input[i]->StrideB == 0) ? getTypeSize(input[i]->Type) * input[i]->Size : input[i]->StrideB; + + if (input[i]->Type == GL_DOUBLE || input[i]->Type == GL_UNSIGNED_INT || input[i]->Type == GL_INT || +#if MESA_BIG_ENDIAN + getTypeSize(input[i]->Type) != 4 || +#endif + stride < 4) + { + r700ConvertAttrib(ctx, count, input[i], &context->stream_desc[index]); + } + else + { + if (input[i]->BufferObj->Name) + { + if (stride % 4 != 0) + { + assert(((intptr_t) input[i]->Ptr) % input[i]->StrideB == 0); + r700AlignDataToDword(ctx, input[i], count, &context->stream_desc[index]); + context->stream_desc[index].is_named_bo = GL_FALSE; + } + else + { + context->stream_desc[index].stride = input[i]->StrideB; + context->stream_desc[index].bo_offset = (intptr_t) input[i]->Ptr; + context->stream_desc[index].bo = get_radeon_buffer_object(input[i]->BufferObj)->bo; + context->stream_desc[index].is_named_bo = GL_TRUE; + } + } + else + { + int size; + int local_count = count; + uint32_t *dst; + + if (input[i]->StrideB == 0) + { + size = getTypeSize(input[i]->Type) * input[i]->Size; + local_count = 1; + } + else + { + size = getTypeSize(input[i]->Type) * input[i]->Size * local_count; + } + + radeonAllocDmaRegion(&context->radeon, &context->stream_desc[index].bo, + &context->stream_desc[index].bo_offset, size, 32); + assert(context->stream_desc[index].bo->ptr != NULL); + dst = (uint32_t *)ADD_POINTERS(context->stream_desc[index].bo->ptr, + context->stream_desc[index].bo_offset); + + switch (context->stream_desc[index].dwords) + { + case 1: + radeonEmitVec4(dst, input[i]->Ptr, input[i]->StrideB, local_count); + context->stream_desc[index].stride = 4; + break; + case 2: + radeonEmitVec8(dst, input[i]->Ptr, input[i]->StrideB, local_count); + context->stream_desc[index].stride = 8; + break; + case 3: + radeonEmitVec12(dst, input[i]->Ptr, input[i]->StrideB, local_count); + context->stream_desc[index].stride = 12; + break; + case 4: + radeonEmitVec16(dst, input[i]->Ptr, input[i]->StrideB, local_count); + context->stream_desc[index].stride = 16; + break; + default: + assert(0); + break; + } + } + } + + aos->count = context->stream_desc[index].stride == 0 ? 1 : count; + aos->stride = context->stream_desc[index].stride / sizeof(float); + aos->components = context->stream_desc[index].dwords; + aos->bo = context->stream_desc[index].bo; + aos->offset = context->stream_desc[index].bo_offset; + + if(context->stream_desc[index].is_named_bo) + { + radeon_cs_space_add_persistent_bo(context->radeon.cmdbuf.cs, + context->stream_desc[index].bo, + RADEON_GEM_DOMAIN_GTT, 0); + } + } + + context->radeon.tcl.aos_count = context->nNumActiveAos; + ret = radeon_cs_space_check_with_bo(context->radeon.cmdbuf.cs, + first_elem(&context->radeon.dma.reserved)->bo, + RADEON_GEM_DOMAIN_GTT, 0); +} + +static void r700FreeData(GLcontext *ctx) +{ + /* Need to zero tcl.aos[n].bo and tcl.elt_dma_bo + * to prevent double unref in radeonReleaseArrays + * called during context destroy + */ + context_t *context = R700_CONTEXT(ctx); + + int i; + + for (i = 0; i < context->nNumActiveAos; i++) + { + if (!context->stream_desc[i].is_named_bo) + { + radeon_bo_unref(context->stream_desc[i].bo); + } + context->radeon.tcl.aos[i].bo = NULL; + } + + if (context->ind_buf.bo != NULL) + { + if(context->ind_buf.bHostIb != GL_TRUE) + { + radeon_bo_unref(context->ind_buf.bo); + } + else + { + FREE(context->ind_buf.bo->ptr); + FREE(context->ind_buf.bo); + context->ind_buf.bo = NULL; + } + } +} + +static void r700FixupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer *mesa_ind_buf) +{ + context_t *context = R700_CONTEXT(ctx); + GLvoid *src_ptr; + GLuint *out; + int i; + GLboolean mapped_named_bo = GL_FALSE; + + if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer) + { + ctx->Driver.MapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, GL_READ_ONLY_ARB, mesa_ind_buf->obj); + mapped_named_bo = GL_TRUE; + assert(mesa_ind_buf->obj->Pointer != NULL); + } + src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr); + + if (mesa_ind_buf->type == GL_UNSIGNED_BYTE) + { + GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1); + GLubyte *in = (GLubyte *)src_ptr; + + if(context->ind_buf.bHostIb != GL_TRUE) + { + radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo, + &context->ind_buf.bo_offset, size, 4); + + assert(context->ind_buf.bo->ptr != NULL); + out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset); + } + else + { + context->ind_buf.bo = MALLOC_STRUCT(radeon_bo); + context->ind_buf.bo->ptr = ALIGN_MALLOC(size, 4); + context->ind_buf.bo_offset = 0; + out = (GLuint *)context->ind_buf.bo->ptr; + } + + for (i = 0; i + 1 < mesa_ind_buf->count; i += 2) + { + *out++ = in[i] | in[i + 1] << 16; + } + + if (i < mesa_ind_buf->count) + { + *out++ = in[i]; + } + +#if MESA_BIG_ENDIAN + } + else + { /* if (mesa_ind_buf->type == GL_UNSIGNED_SHORT) */ + GLushort *in = (GLushort *)src_ptr; + GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1); + + if(context->ind_buf.bHostIb != GL_TRUE) + { + radeonAllocDmaRegion(&context->radeon, &r300->ind_buf.bo, + &context->ind_buf.bo_offset, size, 4); + + assert(context->ind_buf.bo->ptr != NULL); + out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset); + } + else + { + context->ind_buf.bo = MALLOC_STRUCT(radeon_bo); + context->ind_buf.bo->ptr = ALIGN_MALLOC(size, 4); + context->ind_buf.bo_offset = 0; + out = (GLuint *)context->ind_buf.bo->ptr; + } + + for (i = 0; i + 1 < mesa_ind_buf->count; i += 2) + { + *out++ = in[i] | in[i + 1] << 16; + } + + if (i < mesa_ind_buf->count) + { + *out++ = in[i]; + } +#endif + } + + context->ind_buf.is_32bit = GL_FALSE; + context->ind_buf.count = mesa_ind_buf->count; + + if (mapped_named_bo) + { + ctx->Driver.UnmapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, mesa_ind_buf->obj); + } +} + +static void r700SetupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer *mesa_ind_buf) +{ + context_t *context = R700_CONTEXT(ctx); + + if (!mesa_ind_buf) { + context->ind_buf.bo = NULL; + return; + } + + context->ind_buf.bHostIb = GL_TRUE; + +#if MESA_BIG_ENDIAN + if (mesa_ind_buf->type == GL_UNSIGNED_INT) + { +#else + if (mesa_ind_buf->type != GL_UNSIGNED_BYTE) + { +#endif + const GLvoid *src_ptr; + GLvoid *dst_ptr; + GLboolean mapped_named_bo = GL_FALSE; + + if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer) + { + ctx->Driver.MapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, GL_READ_ONLY_ARB, mesa_ind_buf->obj); + assert(mesa_ind_buf->obj->Pointer != NULL); + mapped_named_bo = GL_TRUE; + } + + src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr); + + const GLuint size = mesa_ind_buf->count * getTypeSize(mesa_ind_buf->type); + + if(context->ind_buf.bHostIb != GL_TRUE) + { + radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo, + &context->ind_buf.bo_offset, size, 4); + assert(context->ind_buf.bo->ptr != NULL); + dst_ptr = ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset); + } + else + { + context->ind_buf.bo = MALLOC_STRUCT(radeon_bo); + context->ind_buf.bo->ptr = ALIGN_MALLOC(size, 4); + context->ind_buf.bo_offset = 0; + dst_ptr = context->ind_buf.bo->ptr; + } + + _mesa_memcpy(dst_ptr, src_ptr, size); + + context->ind_buf.is_32bit = (mesa_ind_buf->type == GL_UNSIGNED_INT); + context->ind_buf.count = mesa_ind_buf->count; + + if (mapped_named_bo) + { + ctx->Driver.UnmapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, mesa_ind_buf->obj); + } + } + else + { + r700FixupIndexBuffer(ctx, mesa_ind_buf); + } +} + +static GLboolean r700TryDrawPrims(GLcontext *ctx, + const struct gl_client_array *arrays[], + const struct _mesa_prim *prim, + GLuint nr_prims, + const struct _mesa_index_buffer *ib, + GLuint min_index, + GLuint max_index ) +{ + context_t *context = R700_CONTEXT(ctx); + radeonContextPtr radeon = &context->radeon; + GLuint i, id = 0; + GLboolean bValidedbuffer; + struct radeon_renderbuffer *rrb; + + if (ctx->NewState) + { + _mesa_update_state( ctx ); + } + + bValidedbuffer = r600ValidateBuffers(ctx); + + /* always emit CB base to prevent + * lock ups on some chips. + */ + R600_STATECHANGE(context, cb_target); + /* mark vtx as dirty since it changes per-draw */ + R600_STATECHANGE(context, vtx); + + _tnl_UpdateFixedFunctionProgram(ctx); + r700SetVertexFormat(ctx, arrays, max_index + 1); + r700SetupStreams2(ctx, arrays, max_index + 1); + r700UpdateShaders2(ctx); + + r700SetScissor(context); + + r700SetupVertexProgram(ctx); + + r700SetupFragmentProgram(ctx); + + r600UpdateTextureState(ctx); + + GLuint emit_end = r700PredictRenderSize(ctx) + + context->radeon.cmdbuf.cs->cdw; + + r700SetupIndexBuffer(ctx, ib); + + radeonEmitState(radeon); + + for (i = 0; i < nr_prims; ++i) + { + r700RunRenderPrimitive(ctx, + prim[i].start, + prim[i].start + prim[i].count, + prim[i].mode); + } + + /* Flush render op cached for last several quads. */ + r700WaitForIdleClean(context); + + rrb = radeon_get_colorbuffer(&context->radeon); + if (rrb && rrb->bo) + r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM, + CB_ACTION_ENA_bit | (1 << (id + 6))); + + rrb = radeon_get_depthbuffer(&context->radeon); + if (rrb && rrb->bo) + r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM, + DB_ACTION_ENA_bit | DB_DEST_BASE_ENA_bit); + + r700FreeData(ctx); + + if (emit_end < context->radeon.cmdbuf.cs->cdw) + { + WARN_ONCE("Rendering was %d commands larger than predicted size." + " We might overflow command buffer.\n", context->radeon.cmdbuf.cs->cdw - emit_end); + } + + return GL_TRUE; +} + +static void r700DrawPrimsRe(GLcontext *ctx, + const struct gl_client_array *arrays[], + const struct _mesa_prim *prim, + GLuint nr_prims, + const struct _mesa_index_buffer *ib, + GLboolean index_bounds_valid, + GLuint min_index, + GLuint max_index) +{ + GLboolean retval = GL_FALSE; + + /* This check should get folded into just the places that + * min/max index are really needed. + */ + if (!index_bounds_valid) { + vbo_get_minmax_index(ctx, prim, ib, &min_index, &max_index); + } + + if (min_index) { + vbo_rebase_prims( ctx, arrays, prim, nr_prims, ib, min_index, max_index, r700DrawPrimsRe ); + return; + } + + /* Make an attempt at drawing */ + retval = r700TryDrawPrims(ctx, arrays, prim, nr_prims, ib, min_index, max_index); + + /* If failed run tnl pipeline - it should take care of fallbacks */ + if (!retval) + _tnl_draw_prims(ctx, arrays, prim, nr_prims, ib, min_index, max_index); +} + +static void r700DrawPrims(GLcontext *ctx, + const struct gl_client_array *arrays[], + const struct _mesa_prim *prim, + GLuint nr_prims, + const struct _mesa_index_buffer *ib, + GLboolean index_bounds_valid, + GLuint min_index, + GLuint max_index) +{ + context_t *context = R700_CONTEXT(ctx); + + /* For non indexed drawing, using tnl pipe. */ + if(!ib) + { + context->ind_buf.bo = NULL; + + _tnl_vbo_draw_prims(ctx, arrays, prim, nr_prims, ib, + index_bounds_valid, min_index, max_index); + return; + } + + r700DrawPrimsRe(ctx, arrays, prim, nr_prims, ib, index_bounds_valid, min_index, max_index); +} + +void r700InitDraw(GLcontext *ctx) +{ + struct vbo_context *vbo = vbo_context(ctx); + + vbo->draw_prims = r700DrawPrims; +} + diff --git a/src/mesa/drivers/dri/r600/r700_shader.c b/src/mesa/drivers/dri/r600/r700_shader.c index b4fd51c137..955ea4e4e1 100644 --- a/src/mesa/drivers/dri/r600/r700_shader.c +++ b/src/mesa/drivers/dri/r600/r700_shader.c @@ -60,6 +60,55 @@ void AddInstToList(TypedShaderList * plstCFInstructions, R700ShaderInstruction * plstCFInstructions->uNumOfNode++; } +void TakeInstOutFromList(TypedShaderList * plstCFInstructions, R700ShaderInstruction * pInst) +{ + GLuint ulIndex = 0; + GLboolean bFound = GL_FALSE; + R700ShaderInstruction * pPrevInst = NULL; + R700ShaderInstruction * pCurInst = plstCFInstructions->pHead; + + /* Need go thro list to make sure pInst is there. */ + while(NULL != pCurInst) + { + if(pCurInst == pInst) + { + bFound = GL_TRUE; + break; + } + + pPrevInst = pCurInst; + pCurInst = pCurInst->pNextInst; + } + if(GL_TRUE == bFound) + { + plstCFInstructions->uNumOfNode--; + + pCurInst = pInst->pNextInst; + ulIndex = pInst->m_uIndex; + while(NULL != pCurInst) + { + pCurInst->m_uIndex = ulIndex; + ulIndex++; + pCurInst = pCurInst->pNextInst; + } + + if(plstCFInstructions->pHead == pInst) + { + plstCFInstructions->pHead = pInst->pNextInst; + } + if(plstCFInstructions->pTail == pInst) + { + plstCFInstructions->pTail = pPrevInst; + } + if(NULL != pPrevInst) + { + pPrevInst->pNextInst = pInst->pNextInst; + } + + FREE(pInst); + } +} + void Init_R700_Shader(R700_Shader * pShader) { pShader->Type = R700_SHADER_INVALID; @@ -488,6 +537,47 @@ void DebugPrint(void) { } +void cleanup_vfetch_shaderinst(R700_Shader *pShader) +{ + R700ShaderInstruction *pInst; + R700ShaderInstruction *pInstToFree; + R700VertexInstruction *pVTXInst; + R700ControlFlowInstruction *pCFInst; + + pInst = pShader->lstVTXInstructions.pHead; + while(NULL != pInst) + { + pVTXInst = (R700VertexInstruction *)pInst; + pShader->uShaderBinaryDWORDSize -= GetInstructionSize(pVTXInst->m_ShaderInstType); + + if(NULL != pVTXInst->m_pLinkedGenericClause) + { + pCFInst = (R700ControlFlowInstruction*)(pVTXInst->m_pLinkedGenericClause); + + TakeInstOutFromList(&(pShader->lstCFInstructions), + (R700ShaderInstruction*)pCFInst); + + pShader->uShaderBinaryDWORDSize -= GetInstructionSize(pCFInst->m_ShaderInstType); + } + + pInst = pInst->pNextInst; + }; + + //destroy each item in pShader->lstVTXInstructions; + pInst = pShader->lstVTXInstructions.pHead; + while(NULL != pInst) + { + pInstToFree = pInst; + pInst = pInst->pNextInst; + FREE(pInstToFree); + }; + + //set NULL pShader->lstVTXInstructions + pShader->lstVTXInstructions.pHead=NULL; + pShader->lstVTXInstructions.pTail=NULL; + pShader->lstVTXInstructions.uNumOfNode=0; +} + void Clean_Up_Shader(R700_Shader *pShader) { FREE(pShader->pProgram); diff --git a/src/mesa/drivers/dri/r600/r700_shader.h b/src/mesa/drivers/dri/r600/r700_shader.h index bfd01e1a93..997cb05aaf 100644 --- a/src/mesa/drivers/dri/r600/r700_shader.h +++ b/src/mesa/drivers/dri/r600/r700_shader.h @@ -143,6 +143,7 @@ void LoadProgram(R700_Shader *pShader); void UpdateShaderRegisters(R700_Shader *pShader); void DeleteInstructions(R700_Shader *pShader); void DebugPrint(void); +void cleanup_vfetch_shaderinst(R700_Shader *pShader); void Clean_Up_Shader(R700_Shader *pShader); diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index fc0b511684..1043eabb14 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -92,7 +92,25 @@ void r700UpdateShaders (GLcontext * ctx) //---------------------------------- } } - r700SelectVertexShader(ctx); + r700SelectVertexShader(ctx, 1); + r700UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS); + context->radeon.NewGLState = 0; +} + +void r700UpdateShaders2(GLcontext * ctx) +{ + context_t *context = R700_CONTEXT(ctx); + + /* should only happenen once, just after context is created */ + /* TODO: shouldn't we fallback to sw here? */ + if (!ctx->FragmentProgram._Current) { + _mesa_fprintf(stderr, "No ctx->FragmentProgram._Current!!\n"); + return; + } + + r700SelectFragmentShader(ctx); + + r700SelectVertexShader(ctx, 2); r700UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS); context->radeon.NewGLState = 0; } diff --git a/src/mesa/drivers/dri/r600/r700_state.h b/src/mesa/drivers/dri/r600/r700_state.h index 0f53d5b4c5..209189d8d7 100644 --- a/src/mesa/drivers/dri/r600/r700_state.h +++ b/src/mesa/drivers/dri/r600/r700_state.h @@ -35,6 +35,7 @@ extern void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state); extern void r700UpdateShaders (GLcontext * ctx); +extern void r700UpdateShaders2(GLcontext * ctx); extern void r700UpdateViewportOffset(GLcontext * ctx); diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index 9ee26286d9..e7a209be9d 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -159,7 +159,35 @@ GLboolean Process_Vertex_Program_Vfetch_Instructions( return GL_TRUE; } -void Map_Vertex_Program(struct r700_vertex_program *vp, +GLboolean Process_Vertex_Program_Vfetch_Instructions2( + GLcontext *ctx, + struct r700_vertex_program *vp, + struct gl_vertex_program *mesa_vp) +{ + int i; + context_t *context = R700_CONTEXT(ctx); + + VTX_FETCH_METHOD vtxFetchMethod; + vtxFetchMethod.bEnableMini = GL_FALSE; + vtxFetchMethod.mega_fetch_remainder = 0; + + for(i=0; inNumActiveAos; i++) + { + assemble_vfetch_instruction2(&vp->r700AsmCode, + vp->r700AsmCode.ucVP_AttributeMap[context->stream_desc[i].element], + context->stream_desc[i].type, + context->stream_desc[i].size, + context->stream_desc[i].element, + context->stream_desc[i]._signed, + context->stream_desc[i].normalize, + &vtxFetchMethod); + } + + return GL_TRUE; +} + +void Map_Vertex_Program(GLcontext *ctx, + struct r700_vertex_program *vp, struct gl_vertex_program *mesa_vp) { GLuint ui; @@ -175,11 +203,22 @@ void Map_Vertex_Program(struct r700_vertex_program *vp, pAsm->number_used_registers += num_inputs; // Create VFETCH instructions for inputs - if (GL_TRUE != Process_Vertex_Program_Vfetch_Instructions(vp, mesa_vp) ) - { - radeon_error("Calling Process_Vertex_Program_Vfetch_Instructions return error. \n"); - return; //error - } + if(1 == vp->uiVersion) + { + if (GL_TRUE != Process_Vertex_Program_Vfetch_Instructions(vp, mesa_vp) ) + { + radeon_error("Calling Process_Vertex_Program_Vfetch_Instructions return error. \n"); + return; + } + } + else + { + if (GL_TRUE != Process_Vertex_Program_Vfetch_Instructions2(ctx, vp, mesa_vp) ) + { + radeon_error("Calling Process_Vertex_Program_Vfetch_Instructions2 return error. \n"); + return; + } + } // Map Outputs pAsm->number_of_exports = Map_Vertex_Output(pAsm, mesa_vp, pAsm->number_used_registers); @@ -261,7 +300,8 @@ GLboolean Find_Instruction_Dependencies_vp(struct r700_vertex_program *vp, } struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, - struct gl_vertex_program *mesa_vp) + struct gl_vertex_program *mesa_vp, + GLint nVer) { context_t *context = R700_CONTEXT(ctx); struct r700_vertex_program *vp; @@ -271,6 +311,7 @@ struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, unsigned int i; vp = _mesa_calloc(sizeof(*vp)); + vp->uiVersion = nVer; vp->mesa_program = (struct gl_vertex_program *)_mesa_clone_program(ctx, &mesa_vp->Base); if (mesa_vp->IsPositionInvariant) @@ -296,7 +337,7 @@ struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, //Init_Program Init_r700_AssemblerBase(SPT_VP, &(vp->r700AsmCode), &(vp->r700Shader) ); - Map_Vertex_Program( vp, vp->mesa_program ); + Map_Vertex_Program(ctx, vp, vp->mesa_program ); if(GL_FALSE == Find_Instruction_Dependencies_vp(vp, vp->mesa_program)) { @@ -325,7 +366,7 @@ struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, return vp; } -void r700SelectVertexShader(GLcontext *ctx) +void r700SelectVertexShader(GLcontext *ctx, GLint nVersion) { context_t *context = R700_CONTEXT(ctx); struct r700_vertex_program_cont *vpc; @@ -365,7 +406,7 @@ void r700SelectVertexShader(GLcontext *ctx) } } - vp = r700TranslateVertexShader(ctx, &(vpc->mesa_program) ); + vp = r700TranslateVertexShader(ctx, &(vpc->mesa_program), nVersion); if(!vp) { radeon_error("Failed to translate vertex shader. \n"); @@ -377,6 +418,140 @@ void r700SelectVertexShader(GLcontext *ctx) return; } +int getTypeSize(GLenum type) +{ + switch (type) + { + case GL_DOUBLE: + return sizeof(GLdouble); + case GL_FLOAT: + return sizeof(GLfloat); + case GL_INT: + return sizeof(GLint); + case GL_UNSIGNED_INT: + return sizeof(GLuint); + case GL_SHORT: + return sizeof(GLshort); + case GL_UNSIGNED_SHORT: + return sizeof(GLushort); + case GL_BYTE: + return sizeof(GLbyte); + case GL_UNSIGNED_BYTE: + return sizeof(GLubyte); + default: + assert(0); + return 0; + } +} + +static void r700TranslateAttrib(GLcontext *ctx, GLuint unLoc, int count, const struct gl_client_array *input) +{ + context_t *context = R700_CONTEXT(ctx); + + StreamDesc * pStreamDesc = &(context->stream_desc[context->nNumActiveAos]); + + GLuint stride; + + stride = (input->StrideB == 0) ? getTypeSize(input->Type) * input->Size + : input->StrideB; + + if (input->Type == GL_DOUBLE || input->Type == GL_UNSIGNED_INT || input->Type == GL_INT || +#if MESA_BIG_ENDIAN + getTypeSize(input->Type) != 4 || +#endif + stride < 4) + { + pStreamDesc->type = GL_FLOAT; + + if (input->StrideB == 0) + { + pStreamDesc->stride = 0; + } + else + { + pStreamDesc->stride = sizeof(GLfloat) * input->Size; + } + pStreamDesc->dwords = input->Size; + pStreamDesc->is_named_bo = GL_FALSE; + } + else + { + pStreamDesc->type = input->Type; + pStreamDesc->dwords = (getTypeSize(input->Type) * input->Size + 3)/ 4; + if (!input->BufferObj->Name) + { + if (input->StrideB == 0) + { + pStreamDesc->stride = 0; + } + else + { + pStreamDesc->stride = (getTypeSize(pStreamDesc->type) * input->Size + 3) & ~3; + } + + pStreamDesc->is_named_bo = GL_FALSE; + } + } + + pStreamDesc->size = input->Size; + pStreamDesc->dst_loc = context->nNumActiveAos; + pStreamDesc->element = unLoc; + + switch (pStreamDesc->type) + { //GetSurfaceFormat + case GL_FLOAT: + pStreamDesc->_signed = 0; + pStreamDesc->normalize = GL_FALSE; + break; + case GL_SHORT: + pStreamDesc->_signed = 1; + pStreamDesc->normalize = input->Normalized; + break; + case GL_BYTE: + pStreamDesc->_signed = 1; + pStreamDesc->normalize = input->Normalized; + break; + case GL_UNSIGNED_SHORT: + pStreamDesc->_signed = 0; + pStreamDesc->normalize = input->Normalized; + break; + case GL_UNSIGNED_BYTE: + pStreamDesc->_signed = 0; + pStreamDesc->normalize = input->Normalized; + break; + default: + case GL_INT: + case GL_UNSIGNED_INT: + case GL_DOUBLE: + assert(0); + break; + } + context->nNumActiveAos++; +} + +void r700SetVertexFormat(GLcontext *ctx, const struct gl_client_array *arrays[], int count) +{ + context_t *context = R700_CONTEXT(ctx); + struct r700_vertex_program *vpc + = (struct r700_vertex_program *)ctx->VertexProgram._Current; + + struct gl_vertex_program * mesa_vp = (struct gl_vertex_program *)&(vpc->mesa_program); + unsigned int unLoc = 0; + unsigned int unBit = mesa_vp->Base.InputsRead; + context->nNumActiveAos = 0; + + while(unBit) + { + if(unBit & 1) + { + r700TranslateAttrib(ctx, unLoc, count, arrays[unLoc]); + } + + unBit >>= 1; + ++unLoc; + } +} + void * r700GetActiveVpShaderBo(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.h b/src/mesa/drivers/dri/r600/r700_vertprog.h index c48764c43b..f9a3e395ee 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.h +++ b/src/mesa/drivers/dri/r600/r700_vertprog.h @@ -52,7 +52,7 @@ struct r700_vertex_program GLboolean translated; GLboolean loaded; - GLboolean needUpdateVF; + GLint uiVersion; void * shaderbo; @@ -76,19 +76,28 @@ unsigned int Map_Vertex_Input(r700_AssemblerBase *pAsm, GLboolean Process_Vertex_Program_Vfetch_Instructions( struct r700_vertex_program *vp, struct gl_vertex_program *mesa_vp); -void Map_Vertex_Program(struct r700_vertex_program *vp, +GLboolean Process_Vertex_Program_Vfetch_Instructions2( + GLcontext *ctx, + struct r700_vertex_program *vp, + struct gl_vertex_program *mesa_vp); +void Map_Vertex_Program(GLcontext *ctx, + struct r700_vertex_program *vp, struct gl_vertex_program *mesa_vp); GLboolean Find_Instruction_Dependencies_vp(struct r700_vertex_program *vp, struct gl_vertex_program *mesa_vp); struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, - struct gl_vertex_program *mesa_vp); + struct gl_vertex_program *mesa_vp, + GLint nVer); /* Interface */ -extern void r700SelectVertexShader(GLcontext *ctx); +extern void r700SelectVertexShader(GLcontext *ctx, GLint nVersion); +extern void r700SetVertexFormat(GLcontext *ctx, const struct gl_client_array *arrays[], int count); extern GLboolean r700SetupVertexProgram(GLcontext * ctx); extern void * r700GetActiveVpShaderBo(GLcontext * ctx); +extern int getTypeSize(GLenum type); + #endif /* _R700_VERTPROG_H_ */ diff --git a/src/mesa/drivers/dri/r600/radeon_buffer_objects.c b/src/mesa/drivers/dri/r600/radeon_buffer_objects.c new file mode 120000 index 0000000000..f6a5f66470 --- /dev/null +++ b/src/mesa/drivers/dri/r600/radeon_buffer_objects.c @@ -0,0 +1 @@ +../radeon/radeon_buffer_objects.c \ No newline at end of file diff --git a/src/mesa/drivers/dri/r600/radeon_buffer_objects.h b/src/mesa/drivers/dri/r600/radeon_buffer_objects.h new file mode 120000 index 0000000000..2f134fd17b --- /dev/null +++ b/src/mesa/drivers/dri/r600/radeon_buffer_objects.h @@ -0,0 +1 @@ +../radeon/radeon_buffer_objects.h \ No newline at end of file -- cgit v1.2.3 From 98d5ec10d0918f6619e7b2285278b83e9de6d86f Mon Sep 17 00:00:00 2001 From: Richard Li Date: Tue, 22 Sep 2009 17:26:23 -0400 Subject: r600 : add draw_prim support, make up one lost change. --- src/mesa/drivers/dri/r600/r600_context.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 6fc6d9d7bf..969144ba12 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -59,6 +59,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_debug.h" #include "r600_context.h" #include "radeon_common_context.h" +#include "radeon_buffer_objects.h" #include "radeon_span.h" #include "r600_cmdbuf.h" #include "r600_emit.h" -- cgit v1.2.3 From 2d2f49c91952e18f3362346e19b45c72b1f6db32 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Wed, 23 Sep 2009 14:20:59 +0300 Subject: r600: add support for CUBE textures, also TXP seems to work here ... --- src/mesa/drivers/dri/r600/r700_assembler.c | 306 ++++++++++++++++++++++++----- src/mesa/drivers/dri/r600/r700_assembler.h | 4 + 2 files changed, 263 insertions(+), 47 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 81269350e4..dc25f3b418 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -213,7 +213,7 @@ GLboolean is_reduction_opcode(PVSDWORD* dest) { if (dest->dst.op3 == 0) { - if ( (dest->dst.opcode == SQ_OP2_INST_DOT4 || dest->dst.opcode == SQ_OP2_INST_DOT4_IEEE) ) + if ( (dest->dst.opcode == SQ_OP2_INST_DOT4 || dest->dst.opcode == SQ_OP2_INST_DOT4_IEEE || dest->dst.opcode == SQ_OP2_INST_CUBE) ) { return GL_TRUE; } @@ -350,6 +350,7 @@ unsigned int r700GetNumOperands(r700_AssemblerBase* pAsm) case SQ_OP2_INST_PRED_SETNE: case SQ_OP2_INST_DOT4: case SQ_OP2_INST_DOT4_IEEE: + case SQ_OP2_INST_CUBE: return 2; case SQ_OP2_INST_MOV: @@ -469,6 +470,9 @@ int Init_r700_AssemblerBase(SHADER_PIPE_TYPE spt, r700_AssemblerBase* pAsm, R700 pAsm->number_of_inputs = 0; + pAsm->is_tex = GL_FALSE; + pAsm->need_tex_barrier = GL_FALSE; + return 0; } @@ -682,7 +686,7 @@ GLboolean add_tex_instruction(r700_AssemblerBase* pAsm, // If this clause constains any TEX instruction that is dependent on a previous instruction, // set the barrier bit - if( pAsm->pInstDeps[pAsm->uiCurInst].nDstDep > (-1) ) + if( pAsm->pInstDeps[pAsm->uiCurInst].nDstDep > (-1) || pAsm->need_tex_barrier == GL_TRUE ) { pAsm->cf_current_tex_clause_ptr->m_Word1.f.barrier = 0x1; } @@ -1279,42 +1283,48 @@ GLboolean tex_src(r700_AssemblerBase *pAsm) GLboolean bValidTexCoord = GL_FALSE; + if(pAsm->aArgSubst[1] >= 0) + { + bValidTexCoord = GL_TRUE; + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = pAsm->aArgSubst[1]; + } + else + { switch (pILInst->SrcReg[0].File) { - case PROGRAM_CONSTANT: - case PROGRAM_LOCAL_PARAM: - case PROGRAM_ENV_PARAM: - case PROGRAM_STATE_VAR: - bValidTexCoord = GL_TRUE; - setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); - pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; - pAsm->S[0].src.reg = pAsm->aArgSubst[1]; - break; - case PROGRAM_TEMPORARY: - bValidTexCoord = GL_TRUE; - pAsm->S[0].src.reg = pILInst->SrcReg[0].Index + - pAsm->starting_temp_register_number; - pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; - break; - case PROGRAM_INPUT: - switch (pILInst->SrcReg[0].Index) - { - case FRAG_ATTRIB_COL0: - case FRAG_ATTRIB_COL1: - case FRAG_ATTRIB_TEX0: - case FRAG_ATTRIB_TEX1: - case FRAG_ATTRIB_TEX2: - case FRAG_ATTRIB_TEX3: - case FRAG_ATTRIB_TEX4: - case FRAG_ATTRIB_TEX5: - case FRAG_ATTRIB_TEX6: - case FRAG_ATTRIB_TEX7: - bValidTexCoord = GL_TRUE; - pAsm->S[0].src.reg = - pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index]; - pAsm->S[0].src.rtype = SRC_REG_INPUT; - break; - } - break; + case PROGRAM_CONSTANT: + case PROGRAM_LOCAL_PARAM: + case PROGRAM_ENV_PARAM: + case PROGRAM_STATE_VAR: + break; + case PROGRAM_TEMPORARY: + bValidTexCoord = GL_TRUE; + pAsm->S[0].src.reg = pILInst->SrcReg[0].Index + + pAsm->starting_temp_register_number; + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + break; + case PROGRAM_INPUT: + switch (pILInst->SrcReg[0].Index) + { + case FRAG_ATTRIB_COL0: + case FRAG_ATTRIB_COL1: + case FRAG_ATTRIB_TEX0: + case FRAG_ATTRIB_TEX1: + case FRAG_ATTRIB_TEX2: + case FRAG_ATTRIB_TEX3: + case FRAG_ATTRIB_TEX4: + case FRAG_ATTRIB_TEX5: + case FRAG_ATTRIB_TEX6: + case FRAG_ATTRIB_TEX7: + bValidTexCoord = GL_TRUE; + pAsm->S[0].src.reg = + pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index]; + pAsm->S[0].src.rtype = SRC_REG_INPUT; + break; + } + break; + } } if(GL_TRUE == bValidTexCoord) @@ -2082,7 +2092,9 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) { is_single_scalar_operation = GL_FALSE; number_of_scalar_operations = 4; - + +/* current assembler doesn't do more than 1 register per source */ +#if 0 /* check read port, only very preliminary algorithm, not count in src0/1 same comp case and prev slot repeat case; also not count relative addressing. TODO: improve performance. */ @@ -2117,6 +2129,7 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) { bSplitInst = GL_TRUE; } +#endif } contiguous_slots_needed = 0; @@ -2337,9 +2350,7 @@ GLboolean next_ins(r700_AssemblerBase *pAsm) { struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); - if( GL_TRUE == IsTex(pILInst->Opcode) && - /* handle const moves to temp register */ - !(pAsm->D.dst.opcode == SQ_OP2_INST_MOV) ) + if( GL_TRUE == pAsm->is_tex ) { if (pILInst->TexSrcTarget == TEXTURE_RECT_INDEX) { if( GL_FALSE == assemble_tex_instruction(pAsm, GL_FALSE) ) @@ -2383,7 +2394,8 @@ GLboolean next_ins(r700_AssemblerBase *pAsm) pAsm->S[0].bits = 0; pAsm->S[1].bits = 0; pAsm->S[2].bits = 0; - + pAsm->is_tex = GL_FALSE; + pAsm->need_tex_barrier = GL_FALSE; return GL_TRUE; } @@ -3506,7 +3518,10 @@ GLboolean assemble_STP(r700_AssemblerBase *pAsm) GLboolean assemble_TEX(r700_AssemblerBase *pAsm) { GLboolean src_const; + GLboolean need_barrier = GL_FALSE; + checkop1(pAsm); + switch (pAsm->pILInst[pAsm->uiCurInst].SrcReg[0].File) { case PROGRAM_CONSTANT: @@ -3526,20 +3541,18 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) { if ( GL_FALSE == mov_temp(pAsm, 0) ) return GL_FALSE; + need_barrier = GL_TRUE; } switch (pAsm->pILInst[pAsm->uiCurInst].Opcode) { case OPCODE_TEX: - pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE; break; case OPCODE_TXB: radeon_error("do not support TXB yet\n"); return GL_FALSE; break; case OPCODE_TXP: - /* TODO : tex proj version : divid first 3 components by 4th */ - pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE; break; default: radeon_error("Internal error: bad texture op (not TEX)\n"); @@ -3547,6 +3560,190 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) break; } + if (pAsm->pILInst[pAsm->uiCurInst].Opcode == OPCODE_TXP) + { + GLuint tmp = gethelpr(pAsm); + pAsm->D.dst.opcode = SQ_OP2_INST_RECIP_IEEE; + pAsm->D.dst.math = 1; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + pAsm->D.dst.writew = 1; + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_W, SQ_SEL_W, SQ_SEL_W, SQ_SEL_W); + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP2_INST_MUL; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + pAsm->D.dst.writex = 1; + pAsm->D.dst.writey = 1; + pAsm->D.dst.writez = 1; + pAsm->D.dst.writew = 0; + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); + pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[1].src.reg = tmp; + setswizzle_PVSSRC(&(pAsm->S[1].src), SQ_SEL_W); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + pAsm->aArgSubst[1] = tmp; + need_barrier = GL_TRUE; + } + + if (pAsm->pILInst[pAsm->uiCurInst].TexSrcTarget == TEXTURE_CUBE_INDEX ) + { + GLuint tmp1 = gethelpr(pAsm); + GLuint tmp2 = gethelpr(pAsm); + + /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */ + pAsm->D.dst.opcode = SQ_OP2_INST_CUBE; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp1; + nomask_PVSDST(&(pAsm->D.dst)); + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 0, 1) ) + { + return GL_FALSE; + } + + swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_Z, SQ_SEL_Z, SQ_SEL_X, SQ_SEL_Y); + swizzleagain_PVSSRC(&(pAsm->S[1].src), SQ_SEL_Y, SQ_SEL_X, SQ_SEL_Z, SQ_SEL_Z); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + /* tmp1.z = ABS(tmp1.z) dont have abs support in assembler currently + * have to do explicit instruction + */ + pAsm->D.dst.opcode = SQ_OP2_INST_MAX; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp1; + pAsm->D.dst.writez = 1; + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp1; + noswizzle_PVSSRC(&(pAsm->S[0].src)); + pAsm->S[1].bits = pAsm->S[0].bits; + flipneg_PVSSRC(&(pAsm->S[1].src)); + + next_ins(pAsm); + + /* tmp1.z = RCP_e(|tmp1.z|) */ + pAsm->D.dst.opcode = SQ_OP2_INST_RECIP_IEEE; + pAsm->D.dst.math = 1; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp1; + pAsm->D.dst.writez = 1; + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp1; + pAsm->S[0].src.swizzlex = SQ_SEL_Z; + + next_ins(pAsm); + + /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x + * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x + * muladd has no writemask, have to use another temp + * also no support for imm constants, so add 1 here + */ + pAsm->D.dst.opcode = SQ_OP3_INST_MULADD; + pAsm->D.dst.op3 = 1; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp2; + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp1; + noswizzle_PVSSRC(&(pAsm->S[0].src)); + setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); + pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[1].src.reg = tmp1; + setswizzle_PVSSRC(&(pAsm->S[1].src), SQ_SEL_Z); + setaddrmode_PVSSRC(&(pAsm->S[2].src), ADDR_ABSOLUTE); + pAsm->S[2].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[2].src.reg = tmp1; + setswizzle_PVSSRC(&(pAsm->S[2].src), SQ_SEL_1); + + next_ins(pAsm); + + /* ADD the remaining .5 */ + pAsm->D.dst.opcode = SQ_OP2_INST_ADD; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp2; + pAsm->D.dst.writex = 1; + pAsm->D.dst.writey = 1; + pAsm->D.dst.writez = 0; + pAsm->D.dst.writew = 0; + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp2; + noswizzle_PVSSRC(&(pAsm->S[0].src)); + setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); + pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[1].src.reg = 252; // SQ_ALU_SRC_0_5 + noswizzle_PVSSRC(&(pAsm->S[1].src)); + + next_ins(pAsm); + + /* tmp1.xy = temp2.xy */ + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp1; + pAsm->D.dst.writex = 1; + pAsm->D.dst.writey = 1; + pAsm->D.dst.writez = 0; + pAsm->D.dst.writew = 0; + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp2; + noswizzle_PVSSRC(&(pAsm->S[0].src)); + + next_ins(pAsm); + pAsm->aArgSubst[1] = tmp1; + need_barrier = GL_TRUE; + + } + + pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE; + pAsm->is_tex = GL_TRUE; + if ( GL_TRUE == need_barrier ) + { + pAsm->need_tex_barrier = GL_TRUE; + } // Set src1 to tex unit id pAsm->S[1].src.reg = pAsm->pILInst[pAsm->uiCurInst].TexSrcUnit; pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; @@ -3567,10 +3764,25 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) return GL_FALSE; } - if ( GL_FALSE == next_ins(pAsm) ) + if(pAsm->pILInst[pAsm->uiCurInst].Opcode == OPCODE_TXP) { - return GL_FALSE; + /* hopefully did swizzles before */ + noswizzle_PVSSRC(&(pAsm->S[0].src)); } + + if(pAsm->pILInst[pAsm->uiCurInst].TexSrcTarget == TEXTURE_CUBE_INDEX) + { + /* SAMPLE dst, tmp.yxwy, CUBE */ + pAsm->S[0].src.swizzlex = SQ_SEL_Y; + pAsm->S[0].src.swizzley = SQ_SEL_X; + pAsm->S[0].src.swizzlez = SQ_SEL_W; + pAsm->S[0].src.swizzlew = SQ_SEL_Y; + } + + if ( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index 4e6e20011a..bd6df94ff9 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -374,6 +374,10 @@ typedef struct r700_AssemblerBase struct prog_instruction * pILInst; GLuint uiCurInst; GLboolean bR6xx; + /* helper to decide which type of instruction to assemble */ + GLboolean is_tex; + /* we inserted helper intructions and need barrier on next TEX ins */ + GLboolean need_tex_barrier; } r700_AssemblerBase; //Internal use -- cgit v1.2.3 From ec205bbd577a2619e4b1910527e5e5d1d7426ddb Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 23 Sep 2009 14:56:56 -0400 Subject: r600: fix some warnings --- src/mesa/drivers/dri/r600/r700_assembler.c | 6 +++--- src/mesa/drivers/dri/r600/r700_assembler.h | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index dc25f3b418..903b6968be 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -2078,9 +2078,9 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) GLuint contiguous_slots_needed; GLuint uNumSrc = r700GetNumOperands(pAsm); - GLuint channel_swizzle, j; - GLuint chan_counter[4] = {0, 0, 0, 0}; - PVSSRC * pSource[3]; + //GLuint channel_swizzle, j; + //GLuint chan_counter[4] = {0, 0, 0, 0}; + //PVSSRC * pSource[3]; GLboolean bSplitInst = GL_FALSE; if (1 == pAsm->D.dst.math) diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index bd6df94ff9..0d4283e4ba 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -423,6 +423,7 @@ GLboolean assemble_vfetch_instruction2(r700_AssemblerBase* pAsm, GLuint _signed, GLboolean normalize, VTX_FETCH_METHOD * pFetchMethod); +GLboolean cleanup_vfetch_instructions(r700_AssemblerBase* pAsm); GLuint gethelpr(r700_AssemblerBase* pAsm); void resethelpr(r700_AssemblerBase* pAsm); void checkop_init(r700_AssemblerBase* pAsm); -- cgit v1.2.3 From 53051b8cb5b4804e3eab21262c91ea59f1ea24b8 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 23 Sep 2009 15:02:19 -0400 Subject: r600: fix copy/paste typo --- src/mesa/drivers/dri/r600/r700_render.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index b58859b6ba..daa05f653d 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -855,7 +855,7 @@ static void r700FixupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer if(context->ind_buf.bHostIb != GL_TRUE) { - radeonAllocDmaRegion(&context->radeon, &r300->ind_buf.bo, + radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo, &context->ind_buf.bo_offset, size, 4); assert(context->ind_buf.bo->ptr != NULL); -- cgit v1.2.3 From 8a2b0f6415654c03cd399e59b0946ab90dc44331 Mon Sep 17 00:00:00 2001 From: Richard Li Date: Wed, 23 Sep 2009 16:10:20 -0400 Subject: r600 : add hw index buffer draw support. --- src/mesa/drivers/dri/r600/r700_render.c | 73 +++++++++++++++++++++++++++------ 1 file changed, 61 insertions(+), 12 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index daa05f653d..1f7a76e538 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -262,6 +262,16 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; + GLboolean bUseDrawIndex; + if( (NULL != context->ind_buf.bo) && (GL_TRUE != context->ind_buf.bHostIb) ) + { + bUseDrawIndex = GL_TRUE; + } + else + { + bUseDrawIndex = GL_FALSE; + } + type = r700PrimitiveType(prim); num_indices = r700NumVerts(end - start, prim); @@ -272,10 +282,20 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim if (type < 0 || num_indices <= 0) return; - total_emit = 3 /* VGT_PRIMITIVE_TYPE */ - + 2 /* VGT_INDEX_TYPE */ - + 2 /* NUM_INSTANCES */ + if(GL_TRUE == bUseDrawIndex) + { + total_emit = 3 /* VGT_PRIMITIVE_TYPE */ + + 2 /* VGT_INDEX_TYPE */ + + 2 /* NUM_INSTANCES */ + + 5+2; /* DRAW_INDEX */ + } + else + { + total_emit = 3 /* VGT_PRIMITIVE_TYPE */ + + 2 /* VGT_INDEX_TYPE */ + + 2 /* NUM_INSTANCES */ + num_indices + 3; /* DRAW_INDEX_IMMD */ + } BEGIN_BATCH_NO_AUTOSTATE(total_emit); // prim @@ -287,6 +307,15 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim // index type SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask); + + if(GL_TRUE == bUseDrawIndex) + { + if(GL_TRUE != context->ind_buf.is_32bit) + { + SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask); + } + } + R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); R600_OUT_BATCH(vgt_index_type); @@ -296,12 +325,36 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim // draw packet vgt_num_indices = num_indices; - SETfield(vgt_draw_initiator, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask); + + if(GL_TRUE == bUseDrawIndex) + { + SETfield(vgt_draw_initiator, DI_SRC_SEL_DMA, SOURCE_SELECT_shift, SOURCE_SELECT_mask); + } + else + { + SETfield(vgt_draw_initiator, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask); + } + SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask); - R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (num_indices + 1))); - R600_OUT_BATCH(vgt_num_indices); - R600_OUT_BATCH(vgt_draw_initiator); + if(GL_TRUE == bUseDrawIndex) + { + R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX, 3)); + R600_OUT_BATCH(context->ind_buf.bo_offset); + R600_OUT_BATCH(0); + R600_OUT_BATCH(vgt_num_indices); + R600_OUT_BATCH(vgt_draw_initiator); + R600_OUT_BATCH_RELOC(context->ind_buf.bo_offset, + context->ind_buf.bo, + context->ind_buf.bo_offset, + RADEON_GEM_DOMAIN_GTT, 0, 0); + } + else + { + R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (num_indices + 1))); + R600_OUT_BATCH(vgt_num_indices); + R600_OUT_BATCH(vgt_draw_initiator); + } if(NULL == context->ind_buf.bo) { @@ -340,10 +393,6 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim } } } - else - { - /* TODO : hw ib draw */ - } } END_BATCH(); @@ -899,7 +948,7 @@ static void r700SetupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer return; } - context->ind_buf.bHostIb = GL_TRUE; + context->ind_buf.bHostIb = GL_FALSE; #if MESA_BIG_ENDIAN if (mesa_ind_buf->type == GL_UNSIGNED_INT) -- cgit v1.2.3 From 20e77382935b24e9e2be89cd2b686fa2f1f67635 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 23 Sep 2009 16:54:12 -0400 Subject: r600: fix r700PredictRenderSize for draw prims path --- src/mesa/drivers/dri/r600/r700_render.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 1f7a76e538..bdf0bfc0e4 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -402,12 +402,10 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim /* start 3d, idle, cb/db flush */ #define PRE_EMIT_STATE_BUFSZ 10 + 5 + 14 -static GLuint r700PredictRenderSize(GLcontext* ctx) +static GLuint r700PredictRenderSize(GLcontext* ctx, GLuint nr_prims) { context_t *context = R700_CONTEXT(ctx); - TNLcontext *tnl = TNL_CONTEXT(ctx); struct r700_vertex_program *vp = context->selected_vp; - struct vertex_buffer *vb = &tnl->vb; GLboolean flushed; GLuint dwords, i; GLuint state_size; @@ -415,8 +413,15 @@ static GLuint r700PredictRenderSize(GLcontext* ctx) context->radeon.tcl.aos_count = _mesa_bitcount(vp->mesa_program->Base.InputsRead); dwords = PRE_EMIT_STATE_BUFSZ; - for (i = 0; i < vb->PrimitiveCount; i++) - dwords += vb->Primitive[i].count + 10; + if (nr_prims) + dwords += nr_prims * 14; + else { + TNLcontext *tnl = TNL_CONTEXT(ctx); + struct vertex_buffer *vb = &tnl->vb; + + for (i = 0; i < vb->PrimitiveCount; i++) + dwords += vb->Primitive[i].count + 10; + } state_size = radeonCountStateEmitSize(&context->radeon); flushed = rcommonEnsureCmdBufSpace(&context->radeon, dwords + state_size, __FUNCTION__); @@ -456,7 +461,7 @@ static GLboolean r700RunRender(GLcontext * ctx, r700SetupFragmentProgram(ctx); r600UpdateTextureState(ctx); - GLuint emit_end = r700PredictRenderSize(ctx) + GLuint emit_end = r700PredictRenderSize(ctx, 0) + context->radeon.cmdbuf.cs->cdw; r700SetupStreams(ctx); @@ -1044,7 +1049,7 @@ static GLboolean r700TryDrawPrims(GLcontext *ctx, r600UpdateTextureState(ctx); - GLuint emit_end = r700PredictRenderSize(ctx) + GLuint emit_end = r700PredictRenderSize(ctx, nr_prims) + context->radeon.cmdbuf.cs->cdw; r700SetupIndexBuffer(ctx, ib); -- cgit v1.2.3 From 1bf0651d9b58a5c150fcf37016ae1bda425bb05a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 23 Sep 2009 19:42:07 -0400 Subject: r600: fix up ordering of functions in draw prims path Shaders and IB need to be updated and allocated before calling validatebuffers. --- src/mesa/drivers/dri/r600/r700_render.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index bdf0bfc0e4..bbe364bc6a 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -1019,7 +1019,6 @@ static GLboolean r700TryDrawPrims(GLcontext *ctx, context_t *context = R700_CONTEXT(ctx); radeonContextPtr radeon = &context->radeon; GLuint i, id = 0; - GLboolean bValidedbuffer; struct radeon_renderbuffer *rrb; if (ctx->NewState) @@ -1027,7 +1026,13 @@ static GLboolean r700TryDrawPrims(GLcontext *ctx, _mesa_update_state( ctx ); } - bValidedbuffer = r600ValidateBuffers(ctx); + _tnl_UpdateFixedFunctionProgram(ctx); + r700SetVertexFormat(ctx, arrays, max_index + 1); + r700SetupIndexBuffer(ctx, ib); + /* shaders need to be updated before buffers are validated */ + r700UpdateShaders2(ctx); + if (!r600ValidateBuffers(ctx)) + return GL_FALSE; /* always emit CB base to prevent * lock ups on some chips. @@ -1036,34 +1041,28 @@ static GLboolean r700TryDrawPrims(GLcontext *ctx, /* mark vtx as dirty since it changes per-draw */ R600_STATECHANGE(context, vtx); - _tnl_UpdateFixedFunctionProgram(ctx); - r700SetVertexFormat(ctx, arrays, max_index + 1); - r700SetupStreams2(ctx, arrays, max_index + 1); - r700UpdateShaders2(ctx); - r700SetScissor(context); - r700SetupVertexProgram(ctx); - r700SetupFragmentProgram(ctx); - r600UpdateTextureState(ctx); GLuint emit_end = r700PredictRenderSize(ctx, nr_prims) + context->radeon.cmdbuf.cs->cdw; - r700SetupIndexBuffer(ctx, ib); + r700SetupStreams2(ctx, arrays, max_index + 1); radeonEmitState(radeon); - for (i = 0; i < nr_prims; ++i) + radeon_debug_add_indent(); + for (i = 0; i < nr_prims; ++i) { - r700RunRenderPrimitive(ctx, - prim[i].start, - prim[i].start + prim[i].count, + r700RunRenderPrimitive(ctx, + prim[i].start, + prim[i].start + prim[i].count, prim[i].mode); } - + radeon_debug_remove_indent(); + /* Flush render op cached for last several quads. */ r700WaitForIdleClean(context); -- cgit v1.2.3 From cbab3d7f2a77f187fb688593c17396d4967c75b5 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 8 Sep 2009 16:03:25 -0400 Subject: r600: fix dri2 clipping --- src/mesa/drivers/dri/r600/r700_state.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 1f4724e838..2a0b419256 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -1272,8 +1272,8 @@ void r700SetScissor(context_t *context) //--------------- if (context->radeon.radeonScreen->driScreen->dri2.enabled) { x1 = 0; y1 = 0; - x2 = rrb->base.Width - 1; - y2 = rrb->base.Height - 1; + x2 = rrb->base.Width; + y2 = rrb->base.Height; } else { x1 = rrb->dPriv->x; y1 = rrb->dPriv->y; -- cgit v1.2.3 From b1e417413f2da8aad1872fa009949da101156431 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 9 Sep 2009 15:02:16 +1000 Subject: r600: don't setup hardware state if TFP if we have a BO here it means TFP and we should have set it up already. tested by b0le on #radeon --- src/mesa/drivers/dri/r600/r600_texstate.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 49b603b65e..6436a5d7e9 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -565,6 +565,10 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex int firstlevel = t->mt ? t->mt->firstLevel : 0; GLuint uTexelPitch, row_align; + if ( t->bo ) { + return GL_TRUE; + } + firstImage = t->base.Image[0][firstlevel]; if (!t->image_override) { -- cgit v1.2.3 From 65b01d449cc594e1c7e1a44c5d87fdc698300e9a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 9 Sep 2009 01:41:46 -0400 Subject: r600: fix ftp for dri1 We use t->bo for dri1 since r600 uses CS for dri1. --- src/mesa/drivers/dri/r600/r600_texstate.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 6436a5d7e9..f30dd11230 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -565,9 +565,10 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex int firstlevel = t->mt ? t->mt->firstLevel : 0; GLuint uTexelPitch, row_align; - if ( t->bo ) { - return GL_TRUE; - } + if (rmesa->radeon.radeonScreen->driScreen->dri2.enabled && + t->image_override && + t->bo) + return; firstImage = t->base.Image[0][firstlevel]; -- cgit v1.2.3 From 6552a103f903a2b767464cd2d267f706a6baf7d5 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 9 Sep 2009 11:14:17 -0400 Subject: r600: check if textures are actually enabled before submission noticed by taiu on IRC. --- src/mesa/drivers/dri/r600/r600_texstate.c | 2 +- src/mesa/drivers/dri/r600/r700_chip.c | 118 ++++++++++++++++-------------- 2 files changed, 64 insertions(+), 56 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index f30dd11230..bcb8d7c73d 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -69,7 +69,7 @@ void r600UpdateTextureState(GLcontext * ctx) for (unit = 0; unit < R700_MAX_TEXTURE_UNITS; unit++) { texUnit = &ctx->Texture.Unit[unit]; t = radeon_tex_obj(ctx->Texture.Unit[unit]._Current); - + r700->textures[unit] = NULL; if (texUnit->_ReallyEnabled) { if (!t) continue; diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 37bff56f5a..312cacffda 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -52,38 +52,40 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom) radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) { - radeonTexObj *t = r700->textures[i]; - if (t) { - if (!t->image_override) - bo = t->mt->bo; - else - bo = t->bo; - if (bo) { - - r700SyncSurf(context, bo, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, - 0, TC_ACTION_ENA_bit); - - BEGIN_BATCH_NO_AUTOSTATE(9 + 4); - R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); - R600_OUT_BATCH(i * 7); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE2); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6); - R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2, - bo, - 0, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3, - bo, - r700->textures[i]->SQ_TEX_RESOURCE3, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - END_BATCH(); - COMMIT_BATCH(); + if (ctx->Texture.Unit[i]._ReallyEnabled) { + radeonTexObj *t = r700->textures[i]; + if (t) { + if (!t->image_override) + bo = t->mt->bo; + else + bo = t->bo; + if (bo) { + + r700SyncSurf(context, bo, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, + 0, TC_ACTION_ENA_bit); + + BEGIN_BATCH_NO_AUTOSTATE(9 + 4); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); + R600_OUT_BATCH(i * 7); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE2); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6); + R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2, + bo, + 0, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3, + bo, + r700->textures[i]->SQ_TEX_RESOURCE3, + RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); + END_BATCH(); + COMMIT_BATCH(); + } } } } @@ -98,16 +100,18 @@ static void r700SendTexSamplerState(GLcontext *ctx, struct radeon_state_atom *at radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) { - radeonTexObj *t = r700->textures[i]; - if (t) { - BEGIN_BATCH_NO_AUTOSTATE(5); - R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3)); - R600_OUT_BATCH(i * 3); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1); - R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2); - END_BATCH(); - COMMIT_BATCH(); + if (ctx->Texture.Unit[i]._ReallyEnabled) { + radeonTexObj *t = r700->textures[i]; + if (t) { + BEGIN_BATCH_NO_AUTOSTATE(5); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3)); + R600_OUT_BATCH(i * 3); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1); + R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2); + END_BATCH(); + COMMIT_BATCH(); + } } } } @@ -121,16 +125,18 @@ static void r700SendTexBorderColorState(GLcontext *ctx, struct radeon_state_atom radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) { - radeonTexObj *t = r700->textures[i]; - if (t) { - BEGIN_BATCH_NO_AUTOSTATE(2 + 4); - R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4); - R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED); - R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN); - R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE); - R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA); - END_BATCH(); - COMMIT_BATCH(); + if (ctx->Texture.Unit[i]._ReallyEnabled) { + radeonTexObj *t = r700->textures[i]; + if (t) { + BEGIN_BATCH_NO_AUTOSTATE(2 + 4); + R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4); + R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED); + R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN); + R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE); + R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA); + END_BATCH(); + COMMIT_BATCH(); + } } } } @@ -1176,9 +1182,11 @@ static int check_tx(GLcontext *ctx, struct radeon_state_atom *atom) R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) { - radeonTexObj *t = r700->textures[i]; - if (t) - count++; + if (ctx->Texture.Unit[i]._ReallyEnabled) { + radeonTexObj *t = r700->textures[i]; + if (t) + count++; + } } radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count); return count * 31; -- cgit v1.2.3 From 9edd1a441c3c0c3f018ae561cd5711398ca56f95 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Fri, 11 Sep 2009 10:59:05 -0400 Subject: r600: enable caching of vertex programs --- src/mesa/drivers/dri/r600/r600_context.h | 3 + src/mesa/drivers/dri/r600/r700_chip.c | 10 ++- src/mesa/drivers/dri/r600/r700_oglprog.c | 36 ++++++----- src/mesa/drivers/dri/r600/r700_render.c | 9 +-- src/mesa/drivers/dri/r600/r700_vertprog.c | 103 ++++++++++++++++++++---------- src/mesa/drivers/dri/r600/r700_vertprog.h | 11 +++- 6 files changed, 110 insertions(+), 62 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index 8ae05a301c..c59df7505a 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -51,6 +51,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r700_chip.h" #include "r600_tex.h" #include "r700_oglprog.h" +#include "r700_vertprog.h" struct r600_context; typedef struct r600_context context_t; @@ -155,6 +156,8 @@ struct r600_context { struct r600_hw_state atoms; + struct r700_vertex_program *selected_vp; + /* Vertex buffers */ GLvector4f dummy_attrib[_TNL_ATTRIB_MAX]; diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 312cacffda..1b56059197 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -211,8 +211,7 @@ static void r700SetupVTXConstants(GLcontext * ctx, void r700SetupStreams(GLcontext *ctx) { context_t *context = R700_CONTEXT(ctx); - struct r700_vertex_program *vpc - = (struct r700_vertex_program *)ctx->VertexProgram._Current; + struct r700_vertex_program *vp = context->selected_vp; TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; unsigned int i, j = 0; @@ -221,7 +220,7 @@ void r700SetupStreams(GLcontext *ctx) R600_STATECHANGE(context, vtx); for(i=0; imesa_program.Base.InputsRead & (1 << i)) { + if(vp->mesa_program->Base.InputsRead & (1 << i)) { rcommon_emit_vector(ctx, &context->radeon.tcl.aos[j], vb->AttribPtr[i]->data, @@ -237,8 +236,7 @@ void r700SetupStreams(GLcontext *ctx) static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); - struct r700_vertex_program *vpc - = (struct r700_vertex_program *)ctx->VertexProgram._Current; + struct r700_vertex_program *vp = context->selected_vp; unsigned int i, j = 0; BATCH_LOCALS(&context->radeon); radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); @@ -258,7 +256,7 @@ static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); for(i=0; imesa_program.Base.InputsRead & (1 << i)) { + if(vp->mesa_program->Base.InputsRead & (1 << i)) { /* currently aos are packed */ r700SetupVTXConstants(ctx, i, diff --git a/src/mesa/drivers/dri/r600/r700_oglprog.c b/src/mesa/drivers/dri/r600/r700_oglprog.c index 3c8c1fd7a3..5290ef31be 100644 --- a/src/mesa/drivers/dri/r600/r700_oglprog.c +++ b/src/mesa/drivers/dri/r600/r700_oglprog.c @@ -46,7 +46,7 @@ static struct gl_program *r700NewProgram(GLcontext * ctx, { struct gl_program *pProgram = NULL; - struct r700_vertex_program *vp; + struct r700_vertex_program_cont *vpc; struct r700_fragment_program *fp; radeon_print(RADEON_SHADER, RADEON_VERBOSE, @@ -56,16 +56,11 @@ static struct gl_program *r700NewProgram(GLcontext * ctx, { case GL_VERTEX_STATE_PROGRAM_NV: case GL_VERTEX_PROGRAM_ARB: - vp = CALLOC_STRUCT(r700_vertex_program); + vpc = CALLOC_STRUCT(r700_vertex_program_cont); pProgram = _mesa_init_vertex_program(ctx, - &vp->mesa_program, + &vpc->mesa_program, target, id); - vp->translated = GL_FALSE; - vp->loaded = GL_FALSE; - - vp->shaderbo = NULL; - break; case GL_FRAGMENT_PROGRAM_NV: case GL_FRAGMENT_PROGRAM_ARB: @@ -89,7 +84,8 @@ static struct gl_program *r700NewProgram(GLcontext * ctx, static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) { - struct r700_vertex_program * vp; + struct r700_vertex_program_cont * vpc; + struct r700_vertex_program *vp, *tmp; struct r700_fragment_program * fp; radeon_print(RADEON_SHADER, RADEON_VERBOSE, @@ -99,14 +95,20 @@ static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) { case GL_VERTEX_STATE_PROGRAM_NV: case GL_VERTEX_PROGRAM_ARB: - vp = (struct r700_vertex_program*)prog; - /* Release DMA region */ - - r600DeleteShader(ctx, vp->shaderbo); - - /* Clean up */ - Clean_Up_Assembler(&(vp->r700AsmCode)); - Clean_Up_Shader(&(vp->r700Shader)); + vpc = (struct r700_vertex_program_cont*)prog; + vp = vpc->progs; + while (vp) { + tmp = vp->next; + /* Release DMA region */ + + r600DeleteShader(ctx, vp->shaderbo); + + /* Clean up */ + Clean_Up_Assembler(&(vp->r700AsmCode)); + Clean_Up_Shader(&(vp->r700Shader)); + _mesa_free(vp); + vp = tmp; + } break; case GL_FRAGMENT_PROGRAM_NV: case GL_FRAGMENT_PROGRAM_ARB: diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 3566bf3ca7..b1c3648ca5 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -319,14 +319,13 @@ static GLuint r700PredictRenderSize(GLcontext* ctx) { context_t *context = R700_CONTEXT(ctx); TNLcontext *tnl = TNL_CONTEXT(ctx); - struct r700_vertex_program *vpc - = (struct r700_vertex_program *)ctx->VertexProgram._Current; + struct r700_vertex_program *vp = context->selected_vp; struct vertex_buffer *vb = &tnl->vb; GLboolean flushed; GLuint dwords, i; GLuint state_size; /* pre calculate aos count so state prediction works */ - context->radeon.tcl.aos_count = _mesa_bitcount(vpc->mesa_program.Base.InputsRead); + context->radeon.tcl.aos_count = _mesa_bitcount(vp->mesa_program->Base.InputsRead); dwords = PRE_EMIT_STATE_BUFSZ; for (i = 0; i < vb->PrimitiveCount; i++) @@ -365,7 +364,6 @@ static GLboolean r700RunRender(GLcontext * ctx, /* mark vtx as dirty since it changes per-draw */ R600_STATECHANGE(context, vtx); - r700UpdateShaders(ctx); r700SetScissor(context); r700SetupVertexProgram(ctx); r700SetupFragmentProgram(ctx); @@ -427,7 +425,10 @@ static GLboolean r700RunTCLRender(GLcontext * ctx, /*----------------------*/ /* TODO : sw fallback */ + /* Need shader bo's setup before bo check */ + r700UpdateShaders(ctx); /** + * Ensure all enabled and complete textures are uploaded along with any buffers being used. */ if(!r600ValidateBuffers(ctx)) diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index d107f99e7b..8c2b0071df 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -35,6 +35,7 @@ #include "main/mtypes.h" #include "tnl/t_context.h" +#include "shader/program.h" #include "shader/prog_parameter.h" #include "shader/prog_statevars.h" @@ -258,28 +259,54 @@ GLboolean Find_Instruction_Dependencies_vp(struct r700_vertex_program *vp, return GL_TRUE; } -GLboolean r700TranslateVertexShader(struct r700_vertex_program *vp, - struct gl_vertex_program *mesa_vp) +struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, + struct gl_vertex_program *mesa_vp) { + context_t *context = R700_CONTEXT(ctx); + struct r700_vertex_program *vp; + TNLcontext *tnl = TNL_CONTEXT(ctx); + struct vertex_buffer *vb = &tnl->vb; + unsigned int unBit; + unsigned int i; + + vp = _mesa_calloc(sizeof(*vp)); + vp->mesa_program = (struct gl_vertex_program *)_mesa_clone_program(ctx, &mesa_vp->Base); + + for(i=0; imesa_program->Base.InputsRead & unBit) /* ctx->Array.ArrayObj->xxxxxxx */ + { + vp->aos_desc[i].size = vb->AttribPtr[i]->size; + vp->aos_desc[i].stride = vb->AttribPtr[i]->size * sizeof(GL_FLOAT);/* when emit array, data is packed. vb->AttribPtr[i]->stride;*/ + vp->aos_desc[i].type = GL_FLOAT; + } + } + + if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) + { + vp->r700AsmCode.bR6xx = 1; + } + //Init_Program Init_r700_AssemblerBase(SPT_VP, &(vp->r700AsmCode), &(vp->r700Shader) ); Map_Vertex_Program( vp, mesa_vp ); if(GL_FALSE == Find_Instruction_Dependencies_vp(vp, mesa_vp)) { - return GL_FALSE; + return NULL; } if(GL_FALSE == AssembleInstr(mesa_vp->Base.NumInstructions, &(mesa_vp->Base.Instructions[0]), &(vp->r700AsmCode)) ) { - return GL_FALSE; + return NULL; } if(GL_FALSE == Process_Vertex_Exports(&(vp->r700AsmCode), mesa_vp->Base.OutputsWritten) ) { - return GL_FALSE; + return NULL; } vp->r700Shader.nRegs = (vp->r700AsmCode.number_used_registers == 0) ? 0 @@ -289,72 +316,82 @@ GLboolean r700TranslateVertexShader(struct r700_vertex_program *vp, vp->translated = GL_TRUE; - return GL_TRUE; + return vp; } void r700SelectVertexShader(GLcontext *ctx) { context_t *context = R700_CONTEXT(ctx); - struct r700_vertex_program *vpc - = (struct r700_vertex_program *)ctx->VertexProgram._Current; + struct r700_vertex_program_cont *vpc; + struct r700_vertex_program *vp; TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; unsigned int unBit; unsigned int i; + GLboolean match; + vpc = (struct r700_vertex_program_cont *)ctx->VertexProgram._Current; + +#if 0 if (context->radeon.NewGLState & (_NEW_PROGRAM_CONSTANTS|_NEW_PROGRAM)) { vpc->needUpdateVF = 1; } +#endif - if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) + for (vp = vpc->progs; vp; vp = vp->next) { - vpc->r700AsmCode.bR6xx = 1; - } - + match = GL_TRUE; for(i=0; imesa_program.Base.InputsRead & unBit) /* ctx->Array.ArrayObj->xxxxxxx */ + if(vpc->mesa_program.Base.InputsRead & unBit) { - vpc->aos_desc[i].size = vb->AttribPtr[i]->size; - vpc->aos_desc[i].stride = vb->AttribPtr[i]->size * sizeof(GL_FLOAT);/* when emit array, data is packed. vb->AttribPtr[i]->stride;*/ - vpc->aos_desc[i].type = GL_FLOAT; + if (vp->aos_desc[i].size != vb->AttribPtr[i]->size) + match = GL_FALSE; + break; } } - - if(GL_FALSE == vpc->translated) { - r700TranslateVertexShader(vpc, &(vpc->mesa_program) ); + if (match) + { + context->selected_vp = vp; + return; } + } + + vp = r700TranslateVertexShader(ctx, &(vpc->mesa_program) ); + if(!vp) + { + radeon_error("Failed to translate vertex shader. \n"); + return; + } + vp->next = vpc->progs; + vpc->progs = vp; + context->selected_vp = vp; + return; } void * r700GetActiveVpShaderBo(GLcontext * ctx) { - struct r700_vertex_program *vp - = (struct r700_vertex_program *)ctx->VertexProgram._Current; + context_t *context = R700_CONTEXT(ctx); + struct r700_vertex_program *vp = context->selected_vp;; - return vp->shaderbo; + if (vp) + return vp->shaderbo; + else + return NULL; } GLboolean r700SetupVertexProgram(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - struct r700_vertex_program *vp - = (struct r700_vertex_program *)ctx->VertexProgram._Current; + struct r700_vertex_program *vp = context->selected_vp; struct gl_program_parameter_list *paramList; unsigned int unNumParamData; unsigned int ui; - if (vp->needUpdateVF) - { - vp->loaded = GL_FALSE; - vp->r700Shader.bNeedsAssembly = GL_TRUE; - Process_Vertex_Program_Vfetch_Instructions(vp, &(vp->mesa_program)); - r600DeleteShader(ctx, vp->shaderbo); - } - if(GL_FALSE == vp->loaded) { if(vp->r700Shader.bNeedsAssembly == GL_TRUE) @@ -410,7 +447,7 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) */ /* sent out shader constants. */ - paramList = vp->mesa_program.Base.Parameters; + paramList = vp->mesa_program->Base.Parameters; if(NULL != paramList) { _mesa_load_state_parameters(ctx, paramList); diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.h b/src/mesa/drivers/dri/r600/r700_vertprog.h index e2e65021fd..c48764c43b 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.h +++ b/src/mesa/drivers/dri/r600/r700_vertprog.h @@ -43,7 +43,7 @@ typedef struct ArrayDesc //TEMP struct r700_vertex_program { - struct gl_vertex_program mesa_program; /* Must be first */ + struct gl_vertex_program *mesa_program; /* Must be first */ struct r700_vertex_program *next; @@ -59,6 +59,13 @@ struct r700_vertex_program ArrayDesc aos_desc[VERT_ATTRIB_MAX]; }; +struct r700_vertex_program_cont +{ + struct gl_vertex_program mesa_program; + + struct r700_vertex_program *progs; +}; + //Internal unsigned int Map_Vertex_Output(r700_AssemblerBase *pAsm, struct gl_vertex_program *mesa_vp, @@ -74,7 +81,7 @@ void Map_Vertex_Program(struct r700_vertex_program *vp, GLboolean Find_Instruction_Dependencies_vp(struct r700_vertex_program *vp, struct gl_vertex_program *mesa_vp); -GLboolean r700TranslateVertexShader(struct r700_vertex_program *vp, +struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, struct gl_vertex_program *mesa_vp); /* Interface */ -- cgit v1.2.3 From 7f5a958c80f0fcd7681d515fd1c1b8bc00524a7a Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Fri, 11 Sep 2009 15:59:55 -0400 Subject: r600: fix texcoords from constants with some minor updates from Richard. --- src/mesa/drivers/dri/r600/r700_assembler.c | 92 +++++++++++++++++------------- 1 file changed, 52 insertions(+), 40 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 2d8480daaf..fda6692725 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -1149,41 +1149,49 @@ GLboolean tex_dst(r700_AssemblerBase *pAsm) GLboolean tex_src(r700_AssemblerBase *pAsm) { struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); - + GLboolean bValidTexCoord = GL_FALSE; - switch (pILInst->SrcReg[0].File) - { + switch (pILInst->SrcReg[0].File) { + case PROGRAM_CONSTANT: + case PROGRAM_LOCAL_PARAM: + case PROGRAM_ENV_PARAM: + case PROGRAM_STATE_VAR: + bValidTexCoord = GL_TRUE; + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = pAsm->aArgSubst[1]; + break; case PROGRAM_TEMPORARY: - bValidTexCoord = GL_TRUE; - - pAsm->S[0].src.reg = pILInst->SrcReg[0].Index + pAsm->starting_temp_register_number; - pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; - - break; + bValidTexCoord = GL_TRUE; + pAsm->S[0].src.reg = pILInst->SrcReg[0].Index + + pAsm->starting_temp_register_number; + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + break; case PROGRAM_INPUT: - switch (pILInst->SrcReg[0].Index) - { - case FRAG_ATTRIB_COL0: - case FRAG_ATTRIB_COL1: - case FRAG_ATTRIB_TEX0: - case FRAG_ATTRIB_TEX1: - case FRAG_ATTRIB_TEX2: - case FRAG_ATTRIB_TEX3: - case FRAG_ATTRIB_TEX4: - case FRAG_ATTRIB_TEX5: - case FRAG_ATTRIB_TEX6: - case FRAG_ATTRIB_TEX7: - bValidTexCoord = GL_TRUE; - - pAsm->S[0].src.reg = pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index]; - pAsm->S[0].src.rtype = SRC_REG_INPUT; - } - break; + switch (pILInst->SrcReg[0].Index) + { + case FRAG_ATTRIB_COL0: + case FRAG_ATTRIB_COL1: + case FRAG_ATTRIB_TEX0: + case FRAG_ATTRIB_TEX1: + case FRAG_ATTRIB_TEX2: + case FRAG_ATTRIB_TEX3: + case FRAG_ATTRIB_TEX4: + case FRAG_ATTRIB_TEX5: + case FRAG_ATTRIB_TEX6: + case FRAG_ATTRIB_TEX7: + bValidTexCoord = GL_TRUE; + pAsm->S[0].src.reg = + pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index]; + pAsm->S[0].src.rtype = SRC_REG_INPUT; + break; + } + break; } if(GL_TRUE == bValidTexCoord) - { + { setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); } else @@ -1201,7 +1209,7 @@ GLboolean tex_src(r700_AssemblerBase *pAsm) pAsm->S[0].src.negy = (pILInst->SrcReg[0].Negate >> 1) & 0x1; pAsm->S[0].src.negz = (pILInst->SrcReg[0].Negate >> 2) & 0x1; pAsm->S[0].src.negw = (pILInst->SrcReg[0].Negate >> 3) & 0x1; - + return GL_TRUE; } @@ -2202,7 +2210,9 @@ GLboolean next_ins(r700_AssemblerBase *pAsm) { struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); - if( GL_TRUE == IsTex(pILInst->Opcode) ) + if( GL_TRUE == IsTex(pILInst->Opcode) && + /* handle const moves to temp register */ + !(pAsm->D.dst.opcode == SQ_OP2_INST_MOV) ) { if (pILInst->TexSrcTarget == TEXTURE_RECT_INDEX) { if( GL_FALSE == assemble_tex_instruction(pAsm, GL_FALSE) ) @@ -3374,28 +3384,30 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) case PROGRAM_ENV_PARAM: case PROGRAM_STATE_VAR: src_const = GL_TRUE; + break; case PROGRAM_TEMPORARY: case PROGRAM_INPUT: src_const = GL_FALSE; + break; } - if (GL_TRUE == src_const) + if (GL_TRUE == src_const) { - radeon_error("TODO: Texture coordinates from a constant register not supported.\n"); - return GL_FALSE; + if ( GL_FALSE == mov_temp(pAsm, 0) ) + return GL_FALSE; } - switch (pAsm->pILInst[pAsm->uiCurInst].Opcode) + switch (pAsm->pILInst[pAsm->uiCurInst].Opcode) { case OPCODE_TEX: - pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE; + pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE; break; - case OPCODE_TXB: + case OPCODE_TXB: radeon_error("do not support TXB yet\n"); return GL_FALSE; break; - case OPCODE_TXP: - /* TODO : tex proj version : divid first 3 components by 4th */ + case OPCODE_TXP: + /* TODO : tex proj version : divid first 3 components by 4th */ pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE; break; default: @@ -3418,13 +3430,13 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) { return GL_FALSE; } - + if( GL_FALSE == tex_src(pAsm) ) { return GL_FALSE; } - if ( GL_FALSE == next_ins(pAsm) ) + if ( GL_FALSE == next_ins(pAsm) ) { return GL_FALSE; } -- cgit v1.2.3 From 93a7ea6ba0d5700e18b28c23da226e055f7c2fa1 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 14 Sep 2009 17:08:26 -0400 Subject: r600: fix warning Noticed by rnoland on IRC. --- src/mesa/drivers/dri/r600/r700_assembler.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index fda6692725..efeccb25f1 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -3387,6 +3387,7 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) break; case PROGRAM_TEMPORARY: case PROGRAM_INPUT: + default: src_const = GL_FALSE; break; } -- cgit v1.2.3 From 9437ac9bccd294bd5a8b838e7ca7597e5dc6d5b0 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 14 Sep 2009 18:05:15 -0400 Subject: r600: add span support for 1D tiles 1D tile span support for depth/stencil/color/textures Z and stencil buffers are always tiled, so this fixes sw access to Z and stencil buffers. color and textures are currently linear, but this adds span support when we implement 1D tiling. This fixes the text in progs/demos/engine and progs/tests/z* --- src/mesa/drivers/dri/r600/r600_reg_auto_r6xx.h | 2 + src/mesa/drivers/dri/r600/r700_chip.c | 2 +- src/mesa/drivers/dri/radeon/radeon_span.c | 220 +++++++++++++++++++++++++ 3 files changed, 223 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_reg_auto_r6xx.h b/src/mesa/drivers/dri/r600/r600_reg_auto_r6xx.h index 9d5aa3c7e4..edd85b0fac 100644 --- a/src/mesa/drivers/dri/r600/r600_reg_auto_r6xx.h +++ b/src/mesa/drivers/dri/r600/r600_reg_auto_r6xx.h @@ -1366,6 +1366,7 @@ enum { DB_DEPTH_INFO__READ_SIZE_bit = 1 << 3, DB_DEPTH_INFO__ARRAY_MODE_mask = 0x0f << 15, DB_DEPTH_INFO__ARRAY_MODE_shift = 15, + ARRAY_1D_TILED_THIN1 = 0x02, ARRAY_2D_TILED_THIN1 = 0x04, TILE_SURFACE_ENABLE_bit = 1 << 25, TILE_COMPACT_bit = 1 << 26, @@ -1449,6 +1450,7 @@ enum { CB_COLOR0_INFO__ARRAY_MODE_shift = 8, ARRAY_LINEAR_GENERAL = 0x00, ARRAY_LINEAR_ALIGNED = 0x01, +/* ARRAY_1D_TILED_THIN1 = 0x02, */ /* ARRAY_2D_TILED_THIN1 = 0x04, */ NUMBER_TYPE_mask = 0x07 << 12, NUMBER_TYPE_shift = 12, diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 1b56059197..06d7e9c9ab 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -351,7 +351,7 @@ static void r700SetDepthTarget(context_t *context) SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16, DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask); } - SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1, + SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_1D_TILED_THIN1, DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask); /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */ } diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 4e100d854e..aa2035338c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -106,6 +106,142 @@ static GLubyte *r200_depth_4byte(const struct radeon_renderbuffer * rrb, } #endif +/* r600 tiling + * two main types: + * - 1D (akin to macro-linear/micro-tiled on older asics) + * - 2D (akin to macro-tiled/micro-tiled on older asics) + * only 1D tiling is implemented below + */ +#if defined(RADEON_COMMON_FOR_R600) +static GLint r600_1d_tile_helper(const struct radeon_renderbuffer * rrb, + GLint x, GLint y, GLint is_depth, GLint is_stencil) +{ + GLint element_bytes = rrb->cpp; + GLint num_samples = 1; + GLint tile_width = 8; + GLint tile_height = 8; + GLint tile_thickness = 1; + GLint pitch_elements = rrb->pitch / element_bytes; + GLint height = rrb->base.Height; + GLint z = 0; + GLint sample_number = 0; + /* */ + GLint tile_bytes; + GLint tiles_per_row; + GLint tiles_per_slice; + GLint slice_offset; + GLint tile_row_index; + GLint tile_column_index; + GLint tile_offset; + GLint pixel_number = 0; + GLint element_offset; + GLint offset = 0; + + tile_bytes = tile_width * tile_height * tile_thickness * element_bytes * num_samples; + tiles_per_row = pitch_elements /tile_width; + tiles_per_slice = tiles_per_row * (height / tile_height); + slice_offset = (z / tile_thickness) * tiles_per_slice * tile_bytes; + tile_row_index = y / tile_height; + tile_column_index = x / tile_width; + tile_offset = ((tile_row_index * tiles_per_row) + tile_column_index) * tile_bytes; + + if (is_depth) { + GLint pixel_offset = 0; + + pixel_number |= ((x >> 0) & 1) << 0; // pn[0] = x[0] + pixel_number |= ((y >> 0) & 1) << 1; // pn[1] = y[0] + pixel_number |= ((x >> 1) & 1) << 2; // pn[2] = x[1] + pixel_number |= ((y >> 1) & 1) << 3; // pn[3] = y[1] + pixel_number |= ((x >> 2) & 1) << 4; // pn[4] = x[2] + pixel_number |= ((y >> 2) & 1) << 5; // pn[5] = y[2] + switch (element_bytes) { + case 2: + pixel_offset = pixel_number * element_bytes * num_samples; + element_offset = pixel_offset + (sample_number * element_bytes); + break; + case 4: + /* stencil and depth data are stored separately within a tile. + * stencil is stored in a contiguous tile before the depth tile. + * stencil element is 1 byte, depth element is 3 bytes. + * stencil tile is 64 bytes. + */ + if (is_stencil) + pixel_offset = pixel_number * 1 * num_samples; + else + pixel_offset = (pixel_number * 3 * num_samples) + 64; + break; + } + element_offset = pixel_offset + (sample_number * element_bytes); + } else { + GLint sample_offset; + + switch (element_bytes) { + case 1: + pixel_number |= ((x >> 0) & 1) << 0; // pn[0] = x[0] + pixel_number |= ((x >> 1) & 1) << 1; // pn[1] = x[1] + pixel_number |= ((x >> 2) & 1) << 2; // pn[2] = x[2] + pixel_number |= ((y >> 1) & 1) << 3; // pn[3] = y[1] + pixel_number |= ((y >> 0) & 1) << 4; // pn[4] = y[0] + pixel_number |= ((y >> 2) & 1) << 5; // pn[5] = y[2] + break; + case 2: + pixel_number |= ((x >> 0) & 1) << 0; // pn[0] = x[0] + pixel_number |= ((x >> 1) & 1) << 1; // pn[1] = x[1] + pixel_number |= ((x >> 2) & 1) << 2; // pn[2] = x[2] + pixel_number |= ((y >> 0) & 1) << 3; // pn[3] = y[0] + pixel_number |= ((y >> 1) & 1) << 4; // pn[4] = y[1] + pixel_number |= ((y >> 2) & 1) << 5; // pn[5] = y[2] + break; + case 4: + pixel_number |= ((x >> 0) & 1) << 0; // pn[0] = x[0] + pixel_number |= ((x >> 1) & 1) << 1; // pn[1] = x[1] + pixel_number |= ((y >> 0) & 1) << 2; // pn[2] = y[0] + pixel_number |= ((x >> 2) & 1) << 3; // pn[3] = x[2] + pixel_number |= ((y >> 1) & 1) << 4; // pn[4] = y[1] + pixel_number |= ((y >> 2) & 1) << 5; // pn[5] = y[2] + break; + } + sample_offset = sample_number * (tile_bytes / num_samples); + element_offset = sample_offset + (pixel_number * element_bytes); + } + offset = slice_offset + tile_offset + element_offset; + return offset; +} + +/* depth buffers */ +static GLubyte *r600_ptr_depth(const struct radeon_renderbuffer * rrb, + GLint x, GLint y) +{ + GLubyte *ptr = rrb->bo->ptr; + GLint offset = r600_1d_tile_helper(rrb, x, y, 1, 0); + return &ptr[offset]; +} + +static GLubyte *r600_ptr_stencil(const struct radeon_renderbuffer * rrb, + GLint x, GLint y) +{ + GLubyte *ptr = rrb->bo->ptr; + GLint offset = r600_1d_tile_helper(rrb, x, y, 1, 1); + return &ptr[offset]; +} + +static GLubyte *r600_ptr_color(const struct radeon_renderbuffer * rrb, + GLint x, GLint y) +{ + GLubyte *ptr = rrb->bo->ptr; + uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE; + GLint offset; + + if (rrb->has_surface || !(rrb->bo->flags & mask)) { + offset = x * rrb->cpp + y * rrb->pitch; + } else { + offset = r600_1d_tile_helper(rrb, x, y, 0, 0); + } + return &ptr[offset]; +} + +#endif + /* radeon tiling on r300-r500 has 4 states, macro-linear/micro-linear macro-linear/micro-tiled @@ -270,7 +406,11 @@ s8z24_to_z24s8(uint32_t val) #define TAG(x) radeon##x##_RGB565 #define TAG2(x,y) radeon##x##_RGB565##y +#if defined(RADEON_COMMON_FOR_R600) +#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off) +#else #define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off) +#endif #include "spantmp2.h" /* 16 bit, ARGB1555 color spanline and pixel functions @@ -280,7 +420,11 @@ s8z24_to_z24s8(uint32_t val) #define TAG(x) radeon##x##_ARGB1555 #define TAG2(x,y) radeon##x##_ARGB1555##y +#if defined(RADEON_COMMON_FOR_R600) +#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off) +#else #define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off) +#endif #include "spantmp2.h" /* 16 bit, RGBA4 color spanline and pixel functions @@ -290,7 +434,11 @@ s8z24_to_z24s8(uint32_t val) #define TAG(x) radeon##x##_ARGB4444 #define TAG2(x,y) radeon##x##_ARGB4444##y +#if defined(RADEON_COMMON_FOR_R600) +#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off) +#else #define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off) +#endif #include "spantmp2.h" /* 32 bit, xRGB8888 color spanline and pixel functions @@ -300,11 +448,19 @@ s8z24_to_z24s8(uint32_t val) #define TAG(x) radeon##x##_xRGB8888 #define TAG2(x,y) radeon##x##_xRGB8888##y +#if defined(RADEON_COMMON_FOR_R600) +#define GET_VALUE(_x, _y) ((*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off)) | 0xff000000)) +#define PUT_VALUE(_x, _y, d) { \ + GLuint *_ptr = (GLuint*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \ + *_ptr = d; \ +} while (0) +#else #define GET_VALUE(_x, _y) ((*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)) | 0xff000000)) #define PUT_VALUE(_x, _y, d) { \ GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \ *_ptr = d; \ } while (0) +#endif #include "spantmp2.h" /* 32 bit, ARGB8888 color spanline and pixel functions @@ -314,11 +470,19 @@ s8z24_to_z24s8(uint32_t val) #define TAG(x) radeon##x##_ARGB8888 #define TAG2(x,y) radeon##x##_ARGB8888##y +#if defined(RADEON_COMMON_FOR_R600) +#define GET_VALUE(_x, _y) (*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off))) +#define PUT_VALUE(_x, _y, d) { \ + GLuint *_ptr = (GLuint*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \ + *_ptr = d; \ +} while (0) +#else #define GET_VALUE(_x, _y) (*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off))) #define PUT_VALUE(_x, _y, d) { \ GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \ *_ptr = d; \ } while (0) +#endif #include "spantmp2.h" /* ================================================================ @@ -342,6 +506,9 @@ s8z24_to_z24s8(uint32_t val) #if defined(RADEON_COMMON_FOR_R200) #define WRITE_DEPTH( _x, _y, d ) \ *(GLushort *)r200_depth_2byte(rrb, _x + x_off, _y + y_off) = d +#elif defined(RADEON_COMMON_FOR_R600) +#define WRITE_DEPTH( _x, _y, d ) \ + *(GLushort *)r600_ptr_depth(rrb, _x + x_off, _y + y_off) = d #else #define WRITE_DEPTH( _x, _y, d ) \ *(GLushort *)radeon_ptr_2byte_8x2(rrb, _x + x_off, _y + y_off) = d @@ -350,6 +517,9 @@ s8z24_to_z24s8(uint32_t val) #if defined(RADEON_COMMON_FOR_R200) #define READ_DEPTH( d, _x, _y ) \ d = *(GLushort *)r200_depth_2byte(rrb, _x + x_off, _y + y_off) +#elif defined(RADEON_COMMON_FOR_R600) +#define READ_DEPTH( d, _x, _y ) \ + d = *(GLushort *)r600_ptr_depth(rrb, _x + x_off, _y + y_off) #else #define READ_DEPTH( d, _x, _y ) \ d = *(GLushort *)radeon_ptr_2byte_8x2(rrb, _x + x_off, _y + y_off) @@ -374,6 +544,15 @@ do { \ tmp |= ((d << 8) & 0xffffff00); \ *_ptr = tmp; \ } while (0) +#elif defined(RADEON_COMMON_FOR_R600) +#define WRITE_DEPTH( _x, _y, d ) \ +do { \ + GLuint *_ptr = (GLuint*)r600_ptr_depth( rrb, _x + x_off, _y + y_off ); \ + GLuint tmp = *_ptr; \ + tmp &= 0xff000000; \ + tmp |= ((d) & 0x00ffffff); \ + *_ptr = tmp; \ +} while (0) #elif defined(RADEON_COMMON_FOR_R200) #define WRITE_DEPTH( _x, _y, d ) \ do { \ @@ -399,6 +578,11 @@ do { \ do { \ d = (*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)) & 0xffffff00) >> 8; \ }while(0) +#elif defined(RADEON_COMMON_FOR_R600) +#define READ_DEPTH( d, _x, _y ) \ + do { \ + d = (*(GLuint*)(r600_ptr_depth(rrb, _x + x_off, _y + y_off)) & 0x00ffffff); \ + }while(0) #elif defined(RADEON_COMMON_FOR_R200) #define READ_DEPTH( d, _x, _y ) \ do { \ @@ -426,6 +610,20 @@ do { \ GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \ *_ptr = d; \ } while (0) +#elif defined(RADEON_COMMON_FOR_R600) +#define WRITE_DEPTH( _x, _y, d ) \ +do { \ + GLuint *_ptr = (GLuint*)r600_ptr_depth( rrb, _x + x_off, _y + y_off ); \ + GLuint tmp = *_ptr; \ + tmp &= 0xff000000; \ + tmp |= (((d) >> 8) & 0x00ffffff); \ + *_ptr = tmp; \ + _ptr = (GLuint*)r600_ptr_stencil(rrb, _x + x_off, _y + y_off); \ + tmp = *_ptr; \ + tmp &= 0xffffff00; \ + tmp |= (d) & 0xff; \ + *_ptr = tmp; \ +} while (0) #elif defined(RADEON_COMMON_FOR_R200) #define WRITE_DEPTH( _x, _y, d ) \ do { \ @@ -447,6 +645,12 @@ do { \ do { \ d = (*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off))); \ }while(0) +#elif defined(RADEON_COMMON_FOR_R600) +#define READ_DEPTH( d, _x, _y ) \ + do { \ + d = ((*(GLuint*)(r600_ptr_depth(rrb, _x + x_off, _y + y_off))) << 8) & 0xffffff00; \ + d |= (*(GLuint*)(r600_ptr_stencil(rrb, _x + x_off, _y + y_off))) & 0x000000ff; \ + }while(0) #elif defined(RADEON_COMMON_FOR_R200) #define READ_DEPTH( d, _x, _y ) \ do { \ @@ -476,6 +680,15 @@ do { \ tmp |= (d) & 0xff; \ *_ptr = tmp; \ } while (0) +#elif defined(RADEON_COMMON_FOR_R600) +#define WRITE_STENCIL( _x, _y, d ) \ +do { \ + GLuint *_ptr = (GLuint*)r600_ptr_stencil(rrb, _x + x_off, _y + y_off); \ + GLuint tmp = *_ptr; \ + tmp &= 0xffffff00; \ + tmp |= (d) & 0xff; \ + *_ptr = tmp; \ +} while (0) #elif defined(RADEON_COMMON_FOR_R200) #define WRITE_STENCIL( _x, _y, d ) \ do { \ @@ -503,6 +716,13 @@ do { \ GLuint tmp = *_ptr; \ d = tmp & 0x000000ff; \ } while (0) +#elif defined(RADEON_COMMON_FOR_R600) +#define READ_STENCIL( d, _x, _y ) \ +do { \ + GLuint *_ptr = (GLuint*)r600_ptr_stencil( rrb, _x + x_off, _y + y_off ); \ + GLuint tmp = *_ptr; \ + d = tmp & 0x000000ff; \ +} while (0) #elif defined(RADEON_COMMON_FOR_R200) #define READ_STENCIL( d, _x, _y ) \ do { \ -- cgit v1.2.3 From 2cd2dc34ac93dd929ec8f01cf1f7f8dfa6b34d0d Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Tue, 15 Sep 2009 11:27:51 -0400 Subject: r600: support position_invariant programs --- src/mesa/drivers/dri/r600/r700_vertprog.c | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index 8c2b0071df..9ee26286d9 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -42,6 +42,7 @@ #include "radeon_debug.h" #include "r600_context.h" #include "r600_cmdbuf.h" +#include "shader/programopt.c" #include "r700_debug.h" #include "r700_vertprog.h" @@ -272,6 +273,11 @@ struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, vp = _mesa_calloc(sizeof(*vp)); vp->mesa_program = (struct gl_vertex_program *)_mesa_clone_program(ctx, &mesa_vp->Base); + if (mesa_vp->IsPositionInvariant) + { + _mesa_insert_mvp_code(ctx, vp->mesa_program); + } + for(i=0; ir700AsmCode), &(vp->r700Shader) ); - Map_Vertex_Program( vp, mesa_vp ); + Map_Vertex_Program( vp, vp->mesa_program ); - if(GL_FALSE == Find_Instruction_Dependencies_vp(vp, mesa_vp)) + if(GL_FALSE == Find_Instruction_Dependencies_vp(vp, vp->mesa_program)) { return NULL; } - if(GL_FALSE == AssembleInstr(mesa_vp->Base.NumInstructions, - &(mesa_vp->Base.Instructions[0]), + if(GL_FALSE == AssembleInstr(vp->mesa_program->Base.NumInstructions, + &(vp->mesa_program->Base.Instructions[0]), &(vp->r700AsmCode)) ) { return NULL; } - if(GL_FALSE == Process_Vertex_Exports(&(vp->r700AsmCode), mesa_vp->Base.OutputsWritten) ) + if(GL_FALSE == Process_Vertex_Exports(&(vp->r700AsmCode), vp->mesa_program->Base.OutputsWritten) ) { return NULL; } @@ -329,23 +335,23 @@ void r700SelectVertexShader(GLcontext *ctx) unsigned int unBit; unsigned int i; GLboolean match; + GLbitfield InputsRead; vpc = (struct r700_vertex_program_cont *)ctx->VertexProgram._Current; -#if 0 - if (context->radeon.NewGLState & (_NEW_PROGRAM_CONSTANTS|_NEW_PROGRAM)) + InputsRead = vpc->mesa_program.Base.InputsRead; + if (vpc->mesa_program.IsPositionInvariant) { - vpc->needUpdateVF = 1; - } -#endif - + InputsRead |= VERT_BIT_POS; + } + for (vp = vpc->progs; vp; vp = vp->next) { match = GL_TRUE; for(i=0; imesa_program.Base.InputsRead & unBit) + if(InputsRead & unBit) { if (vp->aos_desc[i].size != vb->AttribPtr[i]->size) match = GL_FALSE; -- cgit v1.2.3 From 095db818c6c7ed5706b5f31d17d0cb19c03cb67a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Sat, 19 Sep 2009 14:46:06 -0400 Subject: r600: fix polygon offset --- src/mesa/drivers/dri/r600/r700_state.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 2a0b419256..d8190efe47 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -1122,20 +1122,25 @@ static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) // context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); GLfloat constant = units; + GLchar depth = 0; + + R600_STATECHANGE(context, poly); switch (ctx->Visual.depthBits) { case 16: constant *= 4.0; + depth = -16; break; case 24: constant *= 2.0; + depth = -24; break; } factor *= 12.0; - - R600_STATECHANGE(context, poly); - + SETfield(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All, depth, + POLY_OFFSET_NEG_NUM_DB_BITS_shift, POLY_OFFSET_NEG_NUM_DB_BITS_mask); + //r700->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //??? r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor; r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant; r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor; -- cgit v1.2.3 From 48559c76056e09ca4f9e4f39e9008f6d32ecd5b0 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Sat, 19 Sep 2009 15:18:42 -0400 Subject: r600: fix point sizes registers takes radius --- src/mesa/drivers/dri/r600/r700_state.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index d8190efe47..8571563149 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -837,9 +837,9 @@ static void r700PointSize(GLcontext * ctx, GLfloat size) size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize); /* format is 12.4 fixed point */ - SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16), + SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0), PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask); - SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16), + SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0), PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask); } @@ -854,11 +854,11 @@ static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * pa /* format is 12.4 fixed point */ switch (pname) { case GL_POINT_SIZE_MIN: - SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 16.0), + SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 8.0), MIN_SIZE_shift, MIN_SIZE_mask); break; case GL_POINT_SIZE_MAX: - SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 16.0), + SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 8.0), MAX_SIZE_shift, MAX_SIZE_mask); break; case GL_POINT_DISTANCE_ATTENUATION: -- cgit v1.2.3 From ed91d103477d563f73be3555d1022ec9af073467 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 21 Sep 2009 10:14:25 -0400 Subject: r600: fix some issues with LIT instruction - MUL_LIT is ALU.Trans instruction - some Trans instructions can take 3 arguments - don't clobber dst.x, use dst.z as temp, it'll get written correct value in last insn - respect source swizzles --- src/mesa/drivers/dri/r600/r700_assembler.c | 69 ++++++++++++++++-------------- 1 file changed, 36 insertions(+), 33 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index efeccb25f1..f46bc32201 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -2024,7 +2024,7 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) return GL_FALSE; } - if (pAsm->D.dst.math == 0) + if (uNumSrc > 1) { // Process source 1 current_source_index = 1; @@ -2880,6 +2880,11 @@ GLboolean assemble_LIT(r700_AssemblerBase *pAsm) return GL_FALSE; } + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + /* dst.y = max(src.x, 0.0) */ pAsm->D.dst.opcode = SQ_OP2_INST_MAX; pAsm->D.dst.rtype = dstType; @@ -2891,11 +2896,6 @@ GLboolean assemble_LIT(r700_AssemblerBase *pAsm) pAsm->S[0].src.rtype = srcType; pAsm->S[0].src.reg = srcReg; setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); - noneg_PVSSRC(&(pAsm->S[0].src)); - pAsm->S[0].src.swizzlex = SQ_SEL_X; - pAsm->S[0].src.swizzley = SQ_SEL_X; - pAsm->S[0].src.swizzlez = SQ_SEL_X; - pAsm->S[0].src.swizzlew = SQ_SEL_X; pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; pAsm->S[1].src.reg = tmp; setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); @@ -2909,34 +2909,47 @@ GLboolean assemble_LIT(r700_AssemblerBase *pAsm) return GL_FALSE; } - /* before: dst.w = log(src.y) - * after : dst.x = log(src.y) - * why change dest register is that dst.w has been initialized as 1 before - */ + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_Y, SQ_SEL_Y, SQ_SEL_Y, SQ_SEL_Y); + + /* dst.z = log(src.y) */ pAsm->D.dst.opcode = SQ_OP2_INST_LOG_CLAMPED; pAsm->D.dst.math = 1; pAsm->D.dst.rtype = dstType; pAsm->D.dst.reg = dstReg; - pAsm->D.dst.writex = 1; + pAsm->D.dst.writex = 0; pAsm->D.dst.writey = 0; - pAsm->D.dst.writez = 0; + pAsm->D.dst.writez = 1; pAsm->D.dst.writew = 0; pAsm->S[0].src.rtype = srcType; pAsm->S[0].src.reg = srcReg; setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); - noneg_PVSSRC(&(pAsm->S[0].src)); - pAsm->S[0].src.swizzlex = SQ_SEL_Y; - pAsm->S[0].src.swizzley = SQ_SEL_Y; - pAsm->S[0].src.swizzlez = SQ_SEL_Y; - pAsm->S[0].src.swizzlew = SQ_SEL_Y; if( GL_FALSE == next_ins(pAsm) ) { return GL_FALSE; } - /* before: tmp.x = amd MUL_LIT(src.w, dst.w, src.x ) */ - /* after : tmp.x = amd MUL_LIT(src.w, dst.x, src.x ) */ + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 0, 2) ) + { + return GL_FALSE; + } + + swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_W, SQ_SEL_W, SQ_SEL_W, SQ_SEL_W); + + swizzleagain_PVSSRC(&(pAsm->S[2].src), SQ_SEL_X, SQ_SEL_X, SQ_SEL_X, SQ_SEL_X); + + /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */ pAsm->D.dst.opcode = SQ_OP3_INST_MUL_LIT; + pAsm->D.dst.math = 1; pAsm->D.dst.op3 = 1; pAsm->D.dst.rtype = DST_REG_TEMPORARY; pAsm->D.dst.reg = tmp; @@ -2948,29 +2961,19 @@ GLboolean assemble_LIT(r700_AssemblerBase *pAsm) pAsm->S[0].src.rtype = srcType; pAsm->S[0].src.reg = srcReg; setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); - noneg_PVSSRC(&(pAsm->S[0].src)); - pAsm->S[0].src.swizzlex = SQ_SEL_W; - pAsm->S[0].src.swizzley = SQ_SEL_W; - pAsm->S[0].src.swizzlez = SQ_SEL_W; - pAsm->S[0].src.swizzlew = SQ_SEL_W; pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; pAsm->S[1].src.reg = dstReg; setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); noneg_PVSSRC(&(pAsm->S[1].src)); - pAsm->S[1].src.swizzlex = SQ_SEL_X; - pAsm->S[1].src.swizzley = SQ_SEL_X; - pAsm->S[1].src.swizzlez = SQ_SEL_X; - pAsm->S[1].src.swizzlew = SQ_SEL_X; + pAsm->S[1].src.swizzlex = SQ_SEL_Z; + pAsm->S[1].src.swizzley = SQ_SEL_Z; + pAsm->S[1].src.swizzlez = SQ_SEL_Z; + pAsm->S[1].src.swizzlew = SQ_SEL_Z; pAsm->S[2].src.rtype = srcType; pAsm->S[2].src.reg = srcReg; setaddrmode_PVSSRC(&(pAsm->S[2].src), ADDR_ABSOLUTE); - noneg_PVSSRC(&(pAsm->S[2].src)); - pAsm->S[2].src.swizzlex = SQ_SEL_X; - pAsm->S[2].src.swizzley = SQ_SEL_X; - pAsm->S[2].src.swizzlez = SQ_SEL_X; - pAsm->S[2].src.swizzlew = SQ_SEL_X; if( GL_FALSE == next_ins(pAsm) ) { -- cgit v1.2.3 From 28308c92605229129a12a2273dda47c6a2ca4790 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 21 Sep 2009 16:30:14 -0400 Subject: r600: various cleanups - max texture size is 8k, but mesa doesn't support that at the moment. - attempt to set shader limits to what the hw actually supports - clean up some old r300 cruft - no need to explicitly disable irqs. This is fixed in the drm now. Signed-off-by: Alex Deucher --- src/mesa/drivers/dri/r600/r600_context.c | 43 +++++++++++----------- src/mesa/drivers/dri/r600/r600_context.h | 19 ---------- .../drivers/dri/radeon/radeon_common_context.c | 7 +--- 3 files changed, 24 insertions(+), 45 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 251c124cbf..414c5aec59 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -281,8 +281,8 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, ctx->Const.MaxTextureMaxAnisotropy = 16.0; ctx->Const.MaxTextureLodBias = 16.0; - ctx->Const.MaxTextureLevels = 13; - ctx->Const.MaxTextureRectSize = 4096; + ctx->Const.MaxTextureLevels = 13; /* hw support 14 */ + ctx->Const.MaxTextureRectSize = 4096; /* hw support 8192 */ ctx->Const.MinPointSize = 0x0001 / 8.0; ctx->Const.MinPointSizeAA = 0x0001 / 8.0; @@ -328,25 +328,26 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, _tnl_allow_vertex_fog(ctx, GL_TRUE); /* currently bogus data */ - ctx->Const.VertexProgram.MaxInstructions = VSF_MAX_FRAGMENT_LENGTH / 4; - ctx->Const.VertexProgram.MaxNativeInstructions = - VSF_MAX_FRAGMENT_LENGTH / 4; - ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */ - ctx->Const.VertexProgram.MaxTemps = 32; - ctx->Const.VertexProgram.MaxNativeTemps = - /*VSF_MAX_FRAGMENT_TEMPS */ 32; - ctx->Const.VertexProgram.MaxNativeParameters = 256; /* r420 */ - ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; - - ctx->Const.FragmentProgram.MaxNativeTemps = PFS_NUM_TEMP_REGS; - ctx->Const.FragmentProgram.MaxNativeAttribs = 11; /* copy i915... */ - ctx->Const.FragmentProgram.MaxNativeParameters = PFS_NUM_CONST_REGS; - ctx->Const.FragmentProgram.MaxNativeAluInstructions = PFS_MAX_ALU_INST; - ctx->Const.FragmentProgram.MaxNativeTexInstructions = PFS_MAX_TEX_INST; - ctx->Const.FragmentProgram.MaxNativeInstructions = - PFS_MAX_ALU_INST + PFS_MAX_TEX_INST; - ctx->Const.FragmentProgram.MaxNativeTexIndirections = - PFS_MAX_TEX_INDIRECT; + ctx->Const.VertexProgram.MaxInstructions = 8192; /* in theory no limit */ + ctx->Const.VertexProgram.MaxNativeInstructions = 8192; + ctx->Const.VertexProgram.MaxNativeAttribs = 160; + ctx->Const.VertexProgram.MaxTemps = 256; /* 256 for reg-based constants, inline consts also supported */ + ctx->Const.VertexProgram.MaxNativeTemps = 256; + ctx->Const.VertexProgram.MaxNativeParameters = 256; /* ??? */ + ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; /* ??? */ + + ctx->Const.FragmentProgram.MaxNativeTemps = 256; + ctx->Const.FragmentProgram.MaxNativeAttribs = 32; + ctx->Const.FragmentProgram.MaxNativeParameters = 256; + ctx->Const.FragmentProgram.MaxNativeAluInstructions = 8192; + /* 8 per clause on r6xx, 16 on rv670/r7xx */ + if ((screen->chip_family == CHIP_FAMILY_RV670) || + (screen->chip_family >= CHIP_FAMILY_RV770)) + ctx->Const.FragmentProgram.MaxNativeTexInstructions = 16; + else + ctx->Const.FragmentProgram.MaxNativeTexInstructions = 8; + ctx->Const.FragmentProgram.MaxNativeInstructions = 8192; + ctx->Const.FragmentProgram.MaxNativeTexIndirections = 8; /* ??? */ ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0; /* and these are?? */ ctx->VertexProgram._MaintainTnlProgram = GL_TRUE; ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE; diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index c59df7505a..9397ecde81 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -86,29 +86,10 @@ extern int hw_tcl_on; #include "tnl_dd/t_dd_vertex.h" #undef TAG -#define PFS_MAX_ALU_INST 64 -#define PFS_MAX_TEX_INST 64 -#define PFS_MAX_TEX_INDIRECT 4 -#define PFS_NUM_TEMP_REGS 32 -#define PFS_NUM_CONST_REGS 16 - -#define R600_MAX_AOS_ARRAYS 16 - -#define REG_COORDS 0 -#define REG_COLOR0 1 -#define REG_TEX0 2 - #define R600_FALLBACK_NONE 0 #define R600_FALLBACK_TCL 1 #define R600_FALLBACK_RAST 2 -enum -{ - NO_SHIFT = 0, - LEFT_SHIFT = 1, - RIGHT_SHIFT = 2, -}; - struct r600_hw_state { struct radeon_state_atom sq; struct radeon_state_atom db; diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index 71ee06d9a7..330721acee 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -227,11 +227,8 @@ GLboolean radeonInitContext(radeonContextPtr radeon, fthrottle_mode = driQueryOptioni(&radeon->optionCache, "fthrottle_mode"); radeon->iw.irq_seq = -1; radeon->irqsEmitted = 0; - if (IS_R600_CLASS(radeon->radeonScreen)) - radeon->do_irqs = 0; - else - radeon->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS && - radeon->radeonScreen->irq); + radeon->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS && + radeon->radeonScreen->irq); radeon->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); -- cgit v1.2.3 From 639fb1472d09281a8df3792c9bcbc59cd4424688 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 21 Sep 2009 16:48:55 -0400 Subject: r600: fix typo in the last commit 128 gprs, 256 reg-based consts --- src/mesa/drivers/dri/r600/r600_context.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 414c5aec59..e0b77d4385 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -327,16 +327,16 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, _tnl_allow_pixel_fog(ctx, GL_FALSE); _tnl_allow_vertex_fog(ctx, GL_TRUE); - /* currently bogus data */ + /* 256 for reg-based consts, inline consts also supported */ ctx->Const.VertexProgram.MaxInstructions = 8192; /* in theory no limit */ ctx->Const.VertexProgram.MaxNativeInstructions = 8192; ctx->Const.VertexProgram.MaxNativeAttribs = 160; - ctx->Const.VertexProgram.MaxTemps = 256; /* 256 for reg-based constants, inline consts also supported */ - ctx->Const.VertexProgram.MaxNativeTemps = 256; - ctx->Const.VertexProgram.MaxNativeParameters = 256; /* ??? */ + ctx->Const.VertexProgram.MaxTemps = 128; + ctx->Const.VertexProgram.MaxNativeTemps = 128; + ctx->Const.VertexProgram.MaxNativeParameters = 256; ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; /* ??? */ - ctx->Const.FragmentProgram.MaxNativeTemps = 256; + ctx->Const.FragmentProgram.MaxNativeTemps = 128; ctx->Const.FragmentProgram.MaxNativeAttribs = 32; ctx->Const.FragmentProgram.MaxNativeParameters = 256; ctx->Const.FragmentProgram.MaxNativeAluInstructions = 8192; -- cgit v1.2.3 From 2058dfaa47704abc62aa5aa9719013624f26764d Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Wed, 23 Sep 2009 14:20:59 +0300 Subject: r600: add support for CUBE textures, also TXP seems to work here ... --- src/mesa/drivers/dri/r600/r700_assembler.c | 306 ++++++++++++++++++++++++----- src/mesa/drivers/dri/r600/r700_assembler.h | 4 + 2 files changed, 263 insertions(+), 47 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index f46bc32201..00eda544d4 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -213,7 +213,7 @@ GLboolean is_reduction_opcode(PVSDWORD* dest) { if (dest->dst.op3 == 0) { - if ( (dest->dst.opcode == SQ_OP2_INST_DOT4 || dest->dst.opcode == SQ_OP2_INST_DOT4_IEEE) ) + if ( (dest->dst.opcode == SQ_OP2_INST_DOT4 || dest->dst.opcode == SQ_OP2_INST_DOT4_IEEE || dest->dst.opcode == SQ_OP2_INST_CUBE) ) { return GL_TRUE; } @@ -350,6 +350,7 @@ unsigned int r700GetNumOperands(r700_AssemblerBase* pAsm) case SQ_OP2_INST_PRED_SETNE: case SQ_OP2_INST_DOT4: case SQ_OP2_INST_DOT4_IEEE: + case SQ_OP2_INST_CUBE: return 2; case SQ_OP2_INST_MOV: @@ -469,6 +470,9 @@ int Init_r700_AssemblerBase(SHADER_PIPE_TYPE spt, r700_AssemblerBase* pAsm, R700 pAsm->number_of_inputs = 0; + pAsm->is_tex = GL_FALSE; + pAsm->need_tex_barrier = GL_FALSE; + return 0; } @@ -682,7 +686,7 @@ GLboolean add_tex_instruction(r700_AssemblerBase* pAsm, // If this clause constains any TEX instruction that is dependent on a previous instruction, // set the barrier bit - if( pAsm->pInstDeps[pAsm->uiCurInst].nDstDep > (-1) ) + if( pAsm->pInstDeps[pAsm->uiCurInst].nDstDep > (-1) || pAsm->need_tex_barrier == GL_TRUE ) { pAsm->cf_current_tex_clause_ptr->m_Word1.f.barrier = 0x1; } @@ -1152,42 +1156,48 @@ GLboolean tex_src(r700_AssemblerBase *pAsm) GLboolean bValidTexCoord = GL_FALSE; + if(pAsm->aArgSubst[1] >= 0) + { + bValidTexCoord = GL_TRUE; + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = pAsm->aArgSubst[1]; + } + else + { switch (pILInst->SrcReg[0].File) { - case PROGRAM_CONSTANT: - case PROGRAM_LOCAL_PARAM: - case PROGRAM_ENV_PARAM: - case PROGRAM_STATE_VAR: - bValidTexCoord = GL_TRUE; - setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); - pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; - pAsm->S[0].src.reg = pAsm->aArgSubst[1]; - break; - case PROGRAM_TEMPORARY: - bValidTexCoord = GL_TRUE; - pAsm->S[0].src.reg = pILInst->SrcReg[0].Index + - pAsm->starting_temp_register_number; - pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; - break; - case PROGRAM_INPUT: - switch (pILInst->SrcReg[0].Index) - { - case FRAG_ATTRIB_COL0: - case FRAG_ATTRIB_COL1: - case FRAG_ATTRIB_TEX0: - case FRAG_ATTRIB_TEX1: - case FRAG_ATTRIB_TEX2: - case FRAG_ATTRIB_TEX3: - case FRAG_ATTRIB_TEX4: - case FRAG_ATTRIB_TEX5: - case FRAG_ATTRIB_TEX6: - case FRAG_ATTRIB_TEX7: - bValidTexCoord = GL_TRUE; - pAsm->S[0].src.reg = - pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index]; - pAsm->S[0].src.rtype = SRC_REG_INPUT; - break; - } - break; + case PROGRAM_CONSTANT: + case PROGRAM_LOCAL_PARAM: + case PROGRAM_ENV_PARAM: + case PROGRAM_STATE_VAR: + break; + case PROGRAM_TEMPORARY: + bValidTexCoord = GL_TRUE; + pAsm->S[0].src.reg = pILInst->SrcReg[0].Index + + pAsm->starting_temp_register_number; + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + break; + case PROGRAM_INPUT: + switch (pILInst->SrcReg[0].Index) + { + case FRAG_ATTRIB_COL0: + case FRAG_ATTRIB_COL1: + case FRAG_ATTRIB_TEX0: + case FRAG_ATTRIB_TEX1: + case FRAG_ATTRIB_TEX2: + case FRAG_ATTRIB_TEX3: + case FRAG_ATTRIB_TEX4: + case FRAG_ATTRIB_TEX5: + case FRAG_ATTRIB_TEX6: + case FRAG_ATTRIB_TEX7: + bValidTexCoord = GL_TRUE; + pAsm->S[0].src.reg = + pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index]; + pAsm->S[0].src.rtype = SRC_REG_INPUT; + break; + } + break; + } } if(GL_TRUE == bValidTexCoord) @@ -1955,7 +1965,9 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) { is_single_scalar_operation = GL_FALSE; number_of_scalar_operations = 4; - + +/* current assembler doesn't do more than 1 register per source */ +#if 0 /* check read port, only very preliminary algorithm, not count in src0/1 same comp case and prev slot repeat case; also not count relative addressing. TODO: improve performance. */ @@ -1990,6 +2002,7 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) { bSplitInst = GL_TRUE; } +#endif } contiguous_slots_needed = 0; @@ -2210,9 +2223,7 @@ GLboolean next_ins(r700_AssemblerBase *pAsm) { struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); - if( GL_TRUE == IsTex(pILInst->Opcode) && - /* handle const moves to temp register */ - !(pAsm->D.dst.opcode == SQ_OP2_INST_MOV) ) + if( GL_TRUE == pAsm->is_tex ) { if (pILInst->TexSrcTarget == TEXTURE_RECT_INDEX) { if( GL_FALSE == assemble_tex_instruction(pAsm, GL_FALSE) ) @@ -2256,7 +2267,8 @@ GLboolean next_ins(r700_AssemblerBase *pAsm) pAsm->S[0].bits = 0; pAsm->S[1].bits = 0; pAsm->S[2].bits = 0; - + pAsm->is_tex = GL_FALSE; + pAsm->need_tex_barrier = GL_FALSE; return GL_TRUE; } @@ -3379,7 +3391,10 @@ GLboolean assemble_STP(r700_AssemblerBase *pAsm) GLboolean assemble_TEX(r700_AssemblerBase *pAsm) { GLboolean src_const; + GLboolean need_barrier = GL_FALSE; + checkop1(pAsm); + switch (pAsm->pILInst[pAsm->uiCurInst].SrcReg[0].File) { case PROGRAM_CONSTANT: @@ -3399,20 +3414,18 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) { if ( GL_FALSE == mov_temp(pAsm, 0) ) return GL_FALSE; + need_barrier = GL_TRUE; } switch (pAsm->pILInst[pAsm->uiCurInst].Opcode) { case OPCODE_TEX: - pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE; break; case OPCODE_TXB: radeon_error("do not support TXB yet\n"); return GL_FALSE; break; case OPCODE_TXP: - /* TODO : tex proj version : divid first 3 components by 4th */ - pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE; break; default: radeon_error("Internal error: bad texture op (not TEX)\n"); @@ -3420,6 +3433,190 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) break; } + if (pAsm->pILInst[pAsm->uiCurInst].Opcode == OPCODE_TXP) + { + GLuint tmp = gethelpr(pAsm); + pAsm->D.dst.opcode = SQ_OP2_INST_RECIP_IEEE; + pAsm->D.dst.math = 1; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + pAsm->D.dst.writew = 1; + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_W, SQ_SEL_W, SQ_SEL_W, SQ_SEL_W); + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP2_INST_MUL; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + pAsm->D.dst.writex = 1; + pAsm->D.dst.writey = 1; + pAsm->D.dst.writez = 1; + pAsm->D.dst.writew = 0; + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); + pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[1].src.reg = tmp; + setswizzle_PVSSRC(&(pAsm->S[1].src), SQ_SEL_W); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + pAsm->aArgSubst[1] = tmp; + need_barrier = GL_TRUE; + } + + if (pAsm->pILInst[pAsm->uiCurInst].TexSrcTarget == TEXTURE_CUBE_INDEX ) + { + GLuint tmp1 = gethelpr(pAsm); + GLuint tmp2 = gethelpr(pAsm); + + /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */ + pAsm->D.dst.opcode = SQ_OP2_INST_CUBE; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp1; + nomask_PVSDST(&(pAsm->D.dst)); + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 0, 1) ) + { + return GL_FALSE; + } + + swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_Z, SQ_SEL_Z, SQ_SEL_X, SQ_SEL_Y); + swizzleagain_PVSSRC(&(pAsm->S[1].src), SQ_SEL_Y, SQ_SEL_X, SQ_SEL_Z, SQ_SEL_Z); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + /* tmp1.z = ABS(tmp1.z) dont have abs support in assembler currently + * have to do explicit instruction + */ + pAsm->D.dst.opcode = SQ_OP2_INST_MAX; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp1; + pAsm->D.dst.writez = 1; + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp1; + noswizzle_PVSSRC(&(pAsm->S[0].src)); + pAsm->S[1].bits = pAsm->S[0].bits; + flipneg_PVSSRC(&(pAsm->S[1].src)); + + next_ins(pAsm); + + /* tmp1.z = RCP_e(|tmp1.z|) */ + pAsm->D.dst.opcode = SQ_OP2_INST_RECIP_IEEE; + pAsm->D.dst.math = 1; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp1; + pAsm->D.dst.writez = 1; + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp1; + pAsm->S[0].src.swizzlex = SQ_SEL_Z; + + next_ins(pAsm); + + /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x + * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x + * muladd has no writemask, have to use another temp + * also no support for imm constants, so add 1 here + */ + pAsm->D.dst.opcode = SQ_OP3_INST_MULADD; + pAsm->D.dst.op3 = 1; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp2; + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp1; + noswizzle_PVSSRC(&(pAsm->S[0].src)); + setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); + pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[1].src.reg = tmp1; + setswizzle_PVSSRC(&(pAsm->S[1].src), SQ_SEL_Z); + setaddrmode_PVSSRC(&(pAsm->S[2].src), ADDR_ABSOLUTE); + pAsm->S[2].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[2].src.reg = tmp1; + setswizzle_PVSSRC(&(pAsm->S[2].src), SQ_SEL_1); + + next_ins(pAsm); + + /* ADD the remaining .5 */ + pAsm->D.dst.opcode = SQ_OP2_INST_ADD; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp2; + pAsm->D.dst.writex = 1; + pAsm->D.dst.writey = 1; + pAsm->D.dst.writez = 0; + pAsm->D.dst.writew = 0; + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp2; + noswizzle_PVSSRC(&(pAsm->S[0].src)); + setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); + pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[1].src.reg = 252; // SQ_ALU_SRC_0_5 + noswizzle_PVSSRC(&(pAsm->S[1].src)); + + next_ins(pAsm); + + /* tmp1.xy = temp2.xy */ + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp1; + pAsm->D.dst.writex = 1; + pAsm->D.dst.writey = 1; + pAsm->D.dst.writez = 0; + pAsm->D.dst.writew = 0; + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp2; + noswizzle_PVSSRC(&(pAsm->S[0].src)); + + next_ins(pAsm); + pAsm->aArgSubst[1] = tmp1; + need_barrier = GL_TRUE; + + } + + pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE; + pAsm->is_tex = GL_TRUE; + if ( GL_TRUE == need_barrier ) + { + pAsm->need_tex_barrier = GL_TRUE; + } // Set src1 to tex unit id pAsm->S[1].src.reg = pAsm->pILInst[pAsm->uiCurInst].TexSrcUnit; pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; @@ -3440,10 +3637,25 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) return GL_FALSE; } - if ( GL_FALSE == next_ins(pAsm) ) + if(pAsm->pILInst[pAsm->uiCurInst].Opcode == OPCODE_TXP) { - return GL_FALSE; + /* hopefully did swizzles before */ + noswizzle_PVSSRC(&(pAsm->S[0].src)); } + + if(pAsm->pILInst[pAsm->uiCurInst].TexSrcTarget == TEXTURE_CUBE_INDEX) + { + /* SAMPLE dst, tmp.yxwy, CUBE */ + pAsm->S[0].src.swizzlex = SQ_SEL_Y; + pAsm->S[0].src.swizzley = SQ_SEL_X; + pAsm->S[0].src.swizzlez = SQ_SEL_W; + pAsm->S[0].src.swizzlew = SQ_SEL_Y; + } + + if ( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index f9c4d849c6..73bb8bac55 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -374,6 +374,10 @@ typedef struct r700_AssemblerBase struct prog_instruction * pILInst; GLuint uiCurInst; GLboolean bR6xx; + /* helper to decide which type of instruction to assemble */ + GLboolean is_tex; + /* we inserted helper intructions and need barrier on next TEX ins */ + GLboolean need_tex_barrier; } r700_AssemblerBase; //Internal use -- cgit v1.2.3 From 41c5f113b5d41649db2027c3f32deaf4d38035ce Mon Sep 17 00:00:00 2001 From: Richard Li Date: Thu, 24 Sep 2009 10:12:40 -0400 Subject: r600 : disable draw_prim for now. --- src/mesa/drivers/dri/r600/r700_render.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index bbe364bc6a..5627984cf9 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -1145,8 +1145,11 @@ static void r700DrawPrims(GLcontext *ctx, void r700InitDraw(GLcontext *ctx) { struct vbo_context *vbo = vbo_context(ctx); - + + /* to be enabled */ + /* vbo->draw_prims = r700DrawPrims; + */ } -- cgit v1.2.3 From 5f06064b616099712dbb2854351d0740c1dbfc60 Mon Sep 17 00:00:00 2001 From: Richard Li Date: Thu, 24 Sep 2009 11:26:15 -0400 Subject: r600 : fix draw_prim bug: vertex fetcher setting. --- src/mesa/drivers/dri/r600/r700_chip.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 783427a94c..e3b8a4081a 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -254,9 +254,22 @@ static void r700SetupVTXConstants2(GLcontext * ctx, SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(pStreamDesc->type, pStreamDesc->size, NULL), SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift, SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); /* TODO : trace back api for initial data type, not only GL_FLOAT */ - SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_SCALED, - SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask); - SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit); + + if(GL_TRUE == pStreamDesc->normalize) + { + SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM, + SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask); + } + //else + //{ + // SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_INT, + // SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask); + //} + + if(1 == pStreamDesc->_signed) + { + SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit); + } SETfield(uSQ_VTX_CONSTANT_WORD3_0, 1, MEM_REQUEST_SIZE_shift, MEM_REQUEST_SIZE_mask); SETfield(uSQ_VTX_CONSTANT_WORD6_0, SQ_TEX_VTX_VALID_BUFFER, -- cgit v1.2.3 From 1d2dca194cebe6e25735b6820f85b8d1231aae63 Mon Sep 17 00:00:00 2001 From: Pauli Nieminen Date: Thu, 24 Sep 2009 19:58:09 +0300 Subject: radeon: Fix scissors for r600 KMS. Radeon generic scissors code had problem that some of code was using exclusive and some inclusive bottom right corner. Only r600 driver is using exclusive coordinate so changed generic code to pass inclusive coordinate and r600 driver changes BR coordinate to be exclusive. --- src/mesa/drivers/dri/r600/r700_state.c | 5 +++-- src/mesa/drivers/dri/radeon/radeon_common.c | 8 ++++---- 2 files changed, 7 insertions(+), 6 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 8571563149..124469b5a6 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -1269,10 +1269,11 @@ void r700SetScissor(context_t *context) //--------------- return; } if (context->radeon.state.scissor.enabled) { + /* r600 has exclusive scissors */ x1 = context->radeon.state.scissor.rect.x1; y1 = context->radeon.state.scissor.rect.y1; - x2 = context->radeon.state.scissor.rect.x2; - y2 = context->radeon.state.scissor.rect.y2; + x2 = context->radeon.state.scissor.rect.x2 + 1; + y2 = context->radeon.state.scissor.rect.y2 + 1; } else { if (context->radeon.radeonScreen->driScreen->dri2.enabled) { x1 = 0; diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index a4c7b40798..9817ff856b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -232,13 +232,13 @@ void radeonUpdateScissor( GLcontext *ctx ) __DRIdrawablePrivate *dPriv = radeon_get_drawable(rmesa); x1 += dPriv->x; - x2 += dPriv->x + 1; + x2 += dPriv->x; min_x += dPriv->x; - max_x += dPriv->x + 1; + max_x += dPriv->x; y1 += dPriv->y; - y2 += dPriv->y + 1; + y2 += dPriv->y; min_y += dPriv->y; - max_y += dPriv->y + 1; + max_y += dPriv->y; } rmesa->state.scissor.rect.x1 = CLAMP(x1, min_x, max_x); -- cgit v1.2.3 From 02b81187dcf606ebf064ac23888e5c57d0528edf Mon Sep 17 00:00:00 2001 From: Michal Krol Date: Fri, 25 Sep 2009 18:51:55 +0200 Subject: radeon: Fix newlines. --- src/mesa/drivers/dri/r600/r700_chip.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index e3b8a4081a..3b7f6fffe0 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -255,20 +255,20 @@ static void r700SetupVTXConstants2(GLcontext * ctx, SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift, SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); /* TODO : trace back api for initial data type, not only GL_FLOAT */ - if(GL_TRUE == pStreamDesc->normalize) - { - SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM, - SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask); - } - //else - //{ - // SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_INT, - // SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask); - //} - - if(1 == pStreamDesc->_signed) - { - SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit); + if(GL_TRUE == pStreamDesc->normalize) + { + SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM, + SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask); + } + //else + //{ + // SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_INT, + // SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask); + //} + + if(1 == pStreamDesc->_signed) + { + SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit); } SETfield(uSQ_VTX_CONSTANT_WORD3_0, 1, MEM_REQUEST_SIZE_shift, MEM_REQUEST_SIZE_mask); -- cgit v1.2.3 From eea30906de37ea3b2f8a594c2b33b643d3dde987 Mon Sep 17 00:00:00 2001 From: Richard Li Date: Sun, 27 Sep 2009 14:47:12 -0400 Subject: r600 : Enable draw_prim. --- src/mesa/drivers/dri/r600/r700_render.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 5627984cf9..4949bf013d 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -1147,9 +1147,7 @@ void r700InitDraw(GLcontext *ctx) struct vbo_context *vbo = vbo_context(ctx); /* to be enabled */ - /* vbo->draw_prims = r700DrawPrims; - */ } -- cgit v1.2.3 From ddffe4546a81216cde4376ee49cbaa021f4d04bb Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Sun, 27 Sep 2009 20:40:35 -0600 Subject: drivers: use more mesa format functions --- src/mesa/drivers/dri/intel/intel_fbo.c | 15 +++++++++------ src/mesa/drivers/dri/intel/intel_tex_image.c | 5 ++--- src/mesa/drivers/dri/r300/r300_tex.c | 7 +++++-- src/mesa/drivers/dri/r300/r300_texstate.c | 2 +- src/mesa/drivers/dri/r600/r600_tex.c | 6 ++++-- src/mesa/drivers/dri/radeon/radeon_fbo.c | 19 +++++++++++-------- 6 files changed, 32 insertions(+), 22 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 8dfb24290d..0a3d0654d7 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -466,6 +466,7 @@ intel_update_wrapper(GLcontext *ctx, struct intel_renderbuffer *irb, struct gl_texture_image *texImage) { irb->texformat = texImage->TexFormat; + gl_format texFormat; if (texImage->TexFormat == &_mesa_texformat_argb8888) { irb->Base._ActualFormat = GL_RGBA8; @@ -509,15 +510,17 @@ intel_update_wrapper(GLcontext *ctx, struct intel_renderbuffer *irb, return GL_FALSE; } + texFormat = texImage->TexFormat->MesaFormat; + irb->Base.InternalFormat = irb->Base._ActualFormat; irb->Base.Width = texImage->Width; irb->Base.Height = texImage->Height; - irb->Base.RedBits = texImage->TexFormat->RedBits; - irb->Base.GreenBits = texImage->TexFormat->GreenBits; - irb->Base.BlueBits = texImage->TexFormat->BlueBits; - irb->Base.AlphaBits = texImage->TexFormat->AlphaBits; - irb->Base.DepthBits = texImage->TexFormat->DepthBits; - irb->Base.StencilBits = texImage->TexFormat->StencilBits; + irb->Base.RedBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_RED_SIZE); + irb->Base.GreenBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_GREEN_SIZE); + irb->Base.BlueBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_BLUE_SIZE); + irb->Base.AlphaBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_ALPHA_SIZE); + irb->Base.DepthBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_DEPTH_SIZE_ARB); + irb->Base.StencilBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_STENCIL_SIZE_EXT); irb->Base.Delete = intel_delete_renderbuffer; irb->Base.AllocStorage = intel_nop_alloc_storage; diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c index 3bafbba371..a9f031a3cb 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_image.c +++ b/src/mesa/drivers/dri/intel/intel_tex_image.c @@ -404,19 +404,18 @@ intelTexImage(GLcontext * ctx, } else if (intelImage->base.Border == 0) { int comp_byte = 0; GLuint texelBytes = _mesa_get_format_bytes(intelImage->base.TexFormat->MesaFormat); - + GLenum baseFormat = _mesa_get_format_base_format(intelImage->base.TexFormat->MesaFormat); if (intelImage->base.IsCompressed) { comp_byte = intel_compressed_num_bytes(intelImage->base.TexFormat->MesaFormat); } - /* Didn't fit in the object miptree, but it's suitable for inclusion in * a miptree, so create one just for our level and store it in the image. * It'll get moved into the object miptree at validate time. */ intelImage->mt = intel_miptree_create(intel, target, - intelImage->base.TexFormat->BaseFormat, + baseFormat, internalFormat, level, level, width, height, depth, diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c index 433e5a87d4..10daeca9e6 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.c +++ b/src/mesa/drivers/dri/r300/r300_tex.c @@ -196,6 +196,7 @@ static void r300TexParameter(GLcontext * ctx, GLenum target, GLenum pname, const GLfloat * params) { radeonTexObj* t = radeon_tex_obj(texObj); + GLenum texBaseFormat; if (RADEON_DEBUG & (RADEON_STATE | RADEON_TEXTURE)) { fprintf(stderr, "%s( %s )\n", __FUNCTION__, @@ -238,8 +239,10 @@ static void r300TexParameter(GLcontext * ctx, GLenum target, case GL_DEPTH_TEXTURE_MODE: if (!texObj->Image[0][texObj->BaseLevel]) return; - if (texObj->Image[0][texObj->BaseLevel]->TexFormat->BaseFormat - == GL_DEPTH_COMPONENT) { + texBaseFormat = texObj->Image[0][texObj->BaseLevel]->_BaseFormat; + + if (texBaseFormat == GL_DEPTH_COMPONENT || + texBaseFormat == GL_DEPTH_STENCIL) { r300SetDepthTexMode(texObj); break; } else { diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index f030451b28..cc40e0d1dc 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -209,7 +209,7 @@ static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t) if (!t->image_override && VALID_FORMAT(firstImage->TexFormat->MesaFormat)) { - if (firstImage->TexFormat->BaseFormat == GL_DEPTH_COMPONENT) { + if (firstImage->_BaseFormat == GL_DEPTH_COMPONENT) { r300SetDepthTexMode(&t->base); } else { t->pp_txformat = tx_table[firstImage->TexFormat->MesaFormat].format; diff --git a/src/mesa/drivers/dri/r600/r600_tex.c b/src/mesa/drivers/dri/r600/r600_tex.c index d105b90cd1..47081c968e 100644 --- a/src/mesa/drivers/dri/r600/r600_tex.c +++ b/src/mesa/drivers/dri/r600/r600_tex.c @@ -286,6 +286,7 @@ static void r600TexParameter(GLcontext * ctx, GLenum target, GLenum pname, const GLfloat * params) { radeonTexObj* t = radeon_tex_obj(texObj); + GLenum baseFormat; radeon_print(RADEON_STATE | RADEON_TEXTURE, RADEON_VERBOSE, "%s( %s )\n", __FUNCTION__, @@ -327,8 +328,9 @@ static void r600TexParameter(GLcontext * ctx, GLenum target, case GL_DEPTH_TEXTURE_MODE: if (!texObj->Image[0][texObj->BaseLevel]) return; - if (texObj->Image[0][texObj->BaseLevel]->TexFormat->BaseFormat - == GL_DEPTH_COMPONENT) { + baseFormat = texObj->Image[0][texObj->BaseLevel]->_BaseFormat; + if (baseFormat == GL_DEPTH_COMPONENT || + baseFormat == GL_DEPTH_STENCIL) { r600SetDepthTexMode(texObj); break; } else { diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index 7ac53ec0ca..f19170b612 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -387,6 +387,8 @@ radeon_update_wrapper(GLcontext *ctx, struct radeon_renderbuffer *rrb, struct gl_texture_image *texImage) { int retry = 0; + gl_format texFormat; + restart: if (texImage->TexFormat == &_mesa_texformat_argb8888) { rrb->cpp = 4; @@ -438,24 +440,25 @@ restart: return GL_FALSE; } texImage->TexFormat = radeonChooseTextureFormat(ctx, texImage->InternalFormat, 0, - texImage->TexFormat->DataType, + _mesa_get_format_datatype(texImage->TexFormat->MesaFormat), 1); retry++; goto restart; } + texFormat = texImage->TexFormat->MesaFormat; + rrb->pitch = texImage->Width * rrb->cpp; rrb->base.InternalFormat = rrb->base._ActualFormat; rrb->base.Width = texImage->Width; rrb->base.Height = texImage->Height; - rrb->base.RedBits = texImage->TexFormat->RedBits; - rrb->base.GreenBits = texImage->TexFormat->GreenBits; - rrb->base.BlueBits = texImage->TexFormat->BlueBits; - rrb->base.AlphaBits = texImage->TexFormat->AlphaBits; - rrb->base.DepthBits = texImage->TexFormat->DepthBits; - rrb->base.StencilBits = texImage->TexFormat->StencilBits; - + rrb->Base.RedBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_RED_SIZE); + rrb->Base.GreenBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_GREEN_SIZE); + rrb->Base.BlueBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_BLUE_SIZE); + rrb->Base.AlphaBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_ALPHA_SIZE); + rrb->Base.DepthBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_DEPTH_SIZE_ARB); + rrb->Base.StencilBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_STENCIL_SIZE_EXT); rrb->base.Delete = radeon_delete_renderbuffer; rrb->base.AllocStorage = radeon_nop_alloc_storage; -- cgit v1.2.3 From a230ad2bc440e9d332482ea453e7ab7f4a5b8bd2 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Tue, 29 Sep 2009 09:46:29 +0300 Subject: r600: clear position enable bit when when wpos is not used by FP Makes doom3 alot nicer.. --- src/mesa/drivers/dri/r600/r700_fragprog.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index 78ce3ae436..62a1ea1a22 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -341,6 +341,11 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, POSITION_ENA_bit); SETbit(r700->SPI_INPUT_Z.u32All, PROVIDE_Z_TO_SPI_bit); } + else + { + CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, POSITION_ENA_bit); + CLEARbit(r700->SPI_INPUT_Z.u32All, PROVIDE_Z_TO_SPI_bit); + } ui = (unNumOfReg < ui) ? ui : unNumOfReg; -- cgit v1.2.3 From 7c5f3c3d8a63b0feee154092153e958fa4f24abd Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 28 Sep 2009 10:42:35 +0300 Subject: r600: user correct alpha blend factor Signed-off-by: Dave Airlie --- src/mesa/drivers/dri/r600/r700_state.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index fbff109455..3ad6d74f53 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -493,10 +493,10 @@ static void r700SetBlendState(GLcontext * ctx) eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask); SETfield(blend_reg, - blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE), + blend_factor(ctx->Color.BlendSrcA, GL_TRUE), ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask); SETfield(blend_reg, - blend_factor(ctx->Color.BlendDstRGB, GL_FALSE), + blend_factor(ctx->Color.BlendDstA, GL_FALSE), ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask); switch (ctx->Color.BlendEquationA) { -- cgit v1.2.3 From ac9c8b6359be770f1ed3e97100c497bd91338874 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 28 Sep 2009 11:23:49 +0300 Subject: r600: use CB_TARGET_MASK instead of CB_SHADER_MASK for setting color mask makes blend functions work better Signed-off-by: Dave Airlie --- src/mesa/drivers/dri/r600/r700_state.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 3ad6d74f53..7e8b48f91e 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -771,9 +771,9 @@ static void r700ColorMask(GLcontext * ctx, (b ? 4 : 0) | (a ? 8 : 0)); - if (mask != r700->CB_SHADER_MASK.u32All) { + if (mask != r700->CB_TARGET_MASK.u32All) { R600_STATECHANGE(context, cb); - SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask); + SETfield(r700->CB_TARGET_MASK.u32All, mask, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask); } } @@ -1780,7 +1780,7 @@ void r700InitState(GLcontext * ctx) //------------------- r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF; /* screen/window/view */ - SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask); + SETfield(r700->CB_SHADER_MASK.u32All, 0xF, (4 * id), OUTPUT0_ENABLE_mask); context->radeon.hw.all_dirty = GL_TRUE; -- cgit v1.2.3 From 1f7c914ad0beea8a29c1a171c7cd1a12f2efe0fa Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Wed, 30 Sep 2009 20:28:45 -0600 Subject: mesa: replace gl_texture_format with gl_format Now gl_texture_image::TexFormat is a simple MESA_FORMAT_x enum. ctx->Driver.ChooseTexture format also returns a MESA_FORMAT_x. gl_texture_format will go away next. --- src/mesa/drivers/common/meta.c | 2 +- src/mesa/drivers/dri/common/texmem.c | 44 ++-- src/mesa/drivers/dri/common/texmem.h | 21 +- src/mesa/drivers/dri/i810/i810tex.c | 18 +- src/mesa/drivers/dri/i810/i810texmem.c | 2 +- src/mesa/drivers/dri/i810/i810texstate.c | 2 +- src/mesa/drivers/dri/i915/i830_texstate.c | 2 +- src/mesa/drivers/dri/i915/i830_vtbl.c | 4 +- src/mesa/drivers/dri/i915/i915_texstate.c | 6 +- src/mesa/drivers/dri/i915/i915_vtbl.c | 4 +- src/mesa/drivers/dri/i965/brw_wm.c | 2 +- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 7 +- src/mesa/drivers/dri/intel/intel_blit.c | 4 +- src/mesa/drivers/dri/intel/intel_fbo.c | 47 ++-- src/mesa/drivers/dri/intel/intel_fbo.h | 3 +- src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 2 +- src/mesa/drivers/dri/intel/intel_span.c | 2 +- src/mesa/drivers/dri/intel/intel_tex.h | 7 +- src/mesa/drivers/dri/intel/intel_tex_format.c | 72 ++--- src/mesa/drivers/dri/intel/intel_tex_image.c | 24 +- src/mesa/drivers/dri/intel/intel_tex_subimage.c | 4 +- src/mesa/drivers/dri/intel/intel_tex_validate.c | 4 +- src/mesa/drivers/dri/mach64/mach64_tex.c | 34 +-- src/mesa/drivers/dri/mach64/mach64_texmem.c | 4 +- src/mesa/drivers/dri/mach64/mach64_texstate.c | 4 +- src/mesa/drivers/dri/mga/mga_texstate.c | 8 +- src/mesa/drivers/dri/mga/mgatex.c | 46 ++-- src/mesa/drivers/dri/mga/mgatexmem.c | 2 +- src/mesa/drivers/dri/r128/r128_tex.c | 8 +- src/mesa/drivers/dri/r128/r128_texmem.c | 4 +- src/mesa/drivers/dri/r128/r128_texstate.c | 4 +- src/mesa/drivers/dri/r200/r200_texstate.c | 8 +- src/mesa/drivers/dri/r300/r300_texstate.c | 8 +- src/mesa/drivers/dri/r600/r600_texstate.c | 4 +- src/mesa/drivers/dri/radeon/radeon_fbo.c | 31 +-- src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 10 +- src/mesa/drivers/dri/radeon/radeon_texstate.c | 8 +- src/mesa/drivers/dri/radeon/radeon_texture.c | 104 ++++---- src/mesa/drivers/dri/radeon/radeon_texture.h | 22 +- src/mesa/drivers/dri/savage/savagetex.c | 127 +++++---- src/mesa/drivers/dri/sis/sis_tex.c | 57 ++-- src/mesa/drivers/dri/tdfx/tdfx_tex.c | 81 +++--- src/mesa/drivers/dri/unichrome/via_tex.c | 68 ++--- src/mesa/drivers/glide/fxddtex.c | 48 ++-- src/mesa/drivers/x11/xm_dd.c | 6 +- src/mesa/main/dd.h | 4 +- src/mesa/main/debug.c | 2 +- src/mesa/main/fbobject.c | 4 +- src/mesa/main/mipmap.c | 8 +- src/mesa/main/mtypes.h | 2 +- src/mesa/main/texcompress_fxt1.c | 12 +- src/mesa/main/texcompress_s3tc.c | 24 +- src/mesa/main/texformat.c | 147 ++++++----- src/mesa/main/texformat.h | 6 +- src/mesa/main/texformat_tmp.h | 4 +- src/mesa/main/texgetimage.c | 14 +- src/mesa/main/teximage.c | 14 +- src/mesa/main/texparam.c | 2 +- src/mesa/main/texrender.c | 10 +- src/mesa/main/texstore.c | 322 +++++++++++------------ src/mesa/main/texstore.h | 2 +- src/mesa/state_tracker/st_cb_drawpixels.c | 4 +- src/mesa/state_tracker/st_cb_texture.c | 30 +-- src/mesa/state_tracker/st_format.c | 62 ++--- src/mesa/state_tracker/st_format.h | 3 +- src/mesa/state_tracker/st_gen_mipmap.c | 2 +- src/mesa/state_tracker/st_texture.c | 2 +- src/mesa/swrast/s_texfilter.c | 28 +- src/mesa/swrast/s_triangle.c | 4 +- 69 files changed, 869 insertions(+), 822 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c index 94cfdfe533..6b35dbb5ad 100644 --- a/src/mesa/drivers/common/meta.c +++ b/src/mesa/drivers/common/meta.c @@ -2407,7 +2407,7 @@ copy_tex_sub_image(GLcontext *ctx, GLuint dims, GLenum target, GLint level, texObj = _mesa_select_tex_object(ctx, texUnit, target); texImage = _mesa_select_tex_image(ctx, texObj, target, level); - format = _mesa_get_format_base_format(texImage->TexFormat->MesaFormat); + format = _mesa_get_format_base_format(texImage->TexFormat); type = get_temp_image_type(ctx, format); bpp = _mesa_bytes_per_pixel(format, type); if (bpp <= 0) { diff --git a/src/mesa/drivers/dri/common/texmem.c b/src/mesa/drivers/dri/common/texmem.c index b64618a03c..c9c3324ed9 100644 --- a/src/mesa/drivers/dri/common/texmem.c +++ b/src/mesa/drivers/dri/common/texmem.c @@ -1306,16 +1306,16 @@ driCalculateTextureFirstLastLevel( driTextureObject * t ) * little-endian Mesa formats. */ /*@{*/ -const struct gl_texture_format *_dri_texformat_rgba8888 = NULL; -const struct gl_texture_format *_dri_texformat_argb8888 = NULL; -const struct gl_texture_format *_dri_texformat_rgb565 = NULL; -const struct gl_texture_format *_dri_texformat_argb4444 = NULL; -const struct gl_texture_format *_dri_texformat_argb1555 = NULL; -const struct gl_texture_format *_dri_texformat_al88 = NULL; -const struct gl_texture_format *_dri_texformat_a8 = &_mesa_texformat_a8; -const struct gl_texture_format *_dri_texformat_ci8 = &_mesa_texformat_ci8; -const struct gl_texture_format *_dri_texformat_i8 = &_mesa_texformat_i8; -const struct gl_texture_format *_dri_texformat_l8 = &_mesa_texformat_l8; +gl_format _dri_texformat_rgba8888 = MESA_FORMAT_NONE; +gl_format _dri_texformat_argb8888 = MESA_FORMAT_NONE; +gl_format _dri_texformat_rgb565 = MESA_FORMAT_NONE; +gl_format _dri_texformat_argb4444 = MESA_FORMAT_NONE; +gl_format _dri_texformat_argb1555 = MESA_FORMAT_NONE; +gl_format _dri_texformat_al88 = MESA_FORMAT_NONE; +gl_format _dri_texformat_a8 = MESA_FORMAT_NONE; +gl_format _dri_texformat_ci8 = MESA_FORMAT_NONE; +gl_format _dri_texformat_i8 = MESA_FORMAT_NONE; +gl_format _dri_texformat_l8 = MESA_FORMAT_NONE; /*@}*/ @@ -1329,19 +1329,19 @@ driInitTextureFormats(void) const GLubyte littleEndian = *((const GLubyte *) &ui); if (littleEndian) { - _dri_texformat_rgba8888 = &_mesa_texformat_rgba8888; - _dri_texformat_argb8888 = &_mesa_texformat_argb8888; - _dri_texformat_rgb565 = &_mesa_texformat_rgb565; - _dri_texformat_argb4444 = &_mesa_texformat_argb4444; - _dri_texformat_argb1555 = &_mesa_texformat_argb1555; - _dri_texformat_al88 = &_mesa_texformat_al88; + _dri_texformat_rgba8888 = MESA_FORMAT_RGBA8888; + _dri_texformat_argb8888 = MESA_FORMAT_ARGB8888; + _dri_texformat_rgb565 = MESA_FORMAT_RGB565; + _dri_texformat_argb4444 = MESA_FORMAT_ARGB4444; + _dri_texformat_argb1555 = MESA_FORMAT_ARGB1555; + _dri_texformat_al88 = MESA_FORMAT_AL88; } else { - _dri_texformat_rgba8888 = &_mesa_texformat_rgba8888_rev; - _dri_texformat_argb8888 = &_mesa_texformat_argb8888_rev; - _dri_texformat_rgb565 = &_mesa_texformat_rgb565_rev; - _dri_texformat_argb4444 = &_mesa_texformat_argb4444_rev; - _dri_texformat_argb1555 = &_mesa_texformat_argb1555_rev; - _dri_texformat_al88 = &_mesa_texformat_al88_rev; + _dri_texformat_rgba8888 = MESA_FORMAT_RGBA8888_REV; + _dri_texformat_argb8888 = MESA_FORMAT_ARGB8888_REV; + _dri_texformat_rgb565 = MESA_FORMAT_RGB565_REV; + _dri_texformat_argb4444 = MESA_FORMAT_ARGB4444_REV; + _dri_texformat_argb1555 = MESA_FORMAT_ARGB1555_REV; + _dri_texformat_al88 = MESA_FORMAT_AL88_REV; } } diff --git a/src/mesa/drivers/dri/common/texmem.h b/src/mesa/drivers/dri/common/texmem.h index 9c065da8b4..725ba2e119 100644 --- a/src/mesa/drivers/dri/common/texmem.h +++ b/src/mesa/drivers/dri/common/texmem.h @@ -39,6 +39,7 @@ #define DRI_TEXMEM_H #include "main/mtypes.h" +#include "main/formats.h" #include "main/mm.h" #include "xf86drm.h" @@ -317,16 +318,16 @@ GLboolean driValidateTextureHeaps( driTexHeap * const * texture_heaps, extern void driCalculateTextureFirstLastLevel( driTextureObject * t ); -extern const struct gl_texture_format *_dri_texformat_rgba8888; -extern const struct gl_texture_format *_dri_texformat_argb8888; -extern const struct gl_texture_format *_dri_texformat_rgb565; -extern const struct gl_texture_format *_dri_texformat_argb4444; -extern const struct gl_texture_format *_dri_texformat_argb1555; -extern const struct gl_texture_format *_dri_texformat_al88; -extern const struct gl_texture_format *_dri_texformat_a8; -extern const struct gl_texture_format *_dri_texformat_ci8; -extern const struct gl_texture_format *_dri_texformat_i8; -extern const struct gl_texture_format *_dri_texformat_l8; +extern gl_format _dri_texformat_rgba8888; +extern gl_format _dri_texformat_argb8888; +extern gl_format _dri_texformat_rgb565; +extern gl_format _dri_texformat_argb4444; +extern gl_format _dri_texformat_argb1555; +extern gl_format _dri_texformat_al88; +extern gl_format _dri_texformat_a8; +extern gl_format _dri_texformat_ci8; +extern gl_format _dri_texformat_i8; +extern gl_format _dri_texformat_l8; extern void driInitTextureFormats( void ); diff --git a/src/mesa/drivers/dri/i810/i810tex.c b/src/mesa/drivers/dri/i810/i810tex.c index cd6e1a8e6e..8166393eb1 100644 --- a/src/mesa/drivers/dri/i810/i810tex.c +++ b/src/mesa/drivers/dri/i810/i810tex.c @@ -440,7 +440,7 @@ static void i810DeleteTexture( GLcontext *ctx, struct gl_texture_object *tObj ) * The i810 only supports 5 texture modes that are useful to Mesa. That * makes this routine pretty simple. */ -static const struct gl_texture_format * +static gl_format i810ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type ) { @@ -458,9 +458,9 @@ i810ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, if ( ((format == GL_BGRA) && (type == GL_UNSIGNED_SHORT_1_5_5_5_REV)) || ((format == GL_RGBA) && (type == GL_UNSIGNED_SHORT_5_5_5_1)) || (internalFormat == GL_RGB5_A1) ) { - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; } - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case 3: case GL_RGB: @@ -472,7 +472,7 @@ i810ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_RGB10: case GL_RGB12: case GL_RGB16: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; case GL_ALPHA: case GL_ALPHA4: @@ -502,21 +502,21 @@ i810ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_INTENSITY12: case GL_INTENSITY16: case GL_COMPRESSED_INTENSITY: - return &_mesa_texformat_al88; + return MESA_FORMAT_AL88; case GL_YCBCR_MESA: if (type == GL_UNSIGNED_SHORT_8_8_MESA || type == GL_UNSIGNED_BYTE) - return &_mesa_texformat_ycbcr; + return MESA_FORMAT_YCBCR; else - return &_mesa_texformat_ycbcr_rev; + return MESA_FORMAT_YCBCR_REV; default: fprintf(stderr, "unexpected texture format in %s\n", __FUNCTION__); - return NULL; + return MESA_FORMAT_NONE; } - return NULL; /* never get here */ + return MESA_FORMAT_NONE; /* never get here */ } /** diff --git a/src/mesa/drivers/dri/i810/i810texmem.c b/src/mesa/drivers/dri/i810/i810texmem.c index 8cbe38f5fc..c2a5d95fc7 100644 --- a/src/mesa/drivers/dri/i810/i810texmem.c +++ b/src/mesa/drivers/dri/i810/i810texmem.c @@ -97,7 +97,7 @@ static void i810UploadTexLevel( i810ContextPtr imesa, if (!image || !image->Data) return; - texelBytes = _mesa_get_format_bytes(image->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(image->TexFormat); if (image->Width * texelBytes == t->Pitch) { GLubyte *dst = (GLubyte *)(t->BufAddr + t->image[hwlevel].offset); diff --git a/src/mesa/drivers/dri/i810/i810texstate.c b/src/mesa/drivers/dri/i810/i810texstate.c index 0e09f54c41..b873ddbecb 100644 --- a/src/mesa/drivers/dri/i810/i810texstate.c +++ b/src/mesa/drivers/dri/i810/i810texstate.c @@ -53,7 +53,7 @@ static void i810SetTexImages( i810ContextPtr imesa, /* fprintf(stderr, "%s\n", __FUNCTION__); */ t->texelBytes = 2; - switch (baseImage->TexFormat->MesaFormat) { + switch (baseImage->TexFormat) { case MESA_FORMAT_ARGB1555: textureFormat = MI1_FMT_16BPP | MI1_PF_16BPP_ARGB1555; break; diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c index 6f998fa6f7..837ae57074 100644 --- a/src/mesa/drivers/dri/i915/i830_texstate.c +++ b/src/mesa/drivers/dri/i915/i830_texstate.c @@ -166,7 +166,7 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) 0, intelObj-> firstLevel); - format = translate_texture_format(firstImage->TexFormat->MesaFormat, + format = translate_texture_format(firstImage->TexFormat, firstImage->InternalFormat); pitch = intelObj->mt->pitch * intelObj->mt->cpp; } diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c index 983f6724c9..d53900b329 100644 --- a/src/mesa/drivers/dri/i915/i830_vtbl.c +++ b/src/mesa/drivers/dri/i915/i830_vtbl.c @@ -646,7 +646,7 @@ i830_state_draw_region(struct intel_context *intel, DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z); /* .5 */ if (irb != NULL) { - switch (irb->texformat->MesaFormat) { + switch (irb->texformat) { case MESA_FORMAT_ARGB8888: value |= DV_PF_8888; break; @@ -661,7 +661,7 @@ i830_state_draw_region(struct intel_context *intel, break; default: _mesa_problem(ctx, "Bad renderbuffer format: %d\n", - irb->texformat->MesaFormat); + irb->texformat); } } diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index 32d4b30cf9..d6f6cfdb49 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -177,7 +177,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) 0, intelObj-> firstLevel); - format = translate_texture_format(firstImage->TexFormat->MesaFormat, + format = translate_texture_format(firstImage->TexFormat, firstImage->InternalFormat, tObj->DepthMode); pitch = intelObj->mt->pitch * intelObj->mt->cpp; @@ -263,8 +263,8 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) /* YUV conversion: */ - if (firstImage->TexFormat->MesaFormat == MESA_FORMAT_YCBCR || - firstImage->TexFormat->MesaFormat == MESA_FORMAT_YCBCR_REV) + if (firstImage->TexFormat == MESA_FORMAT_YCBCR || + firstImage->TexFormat == MESA_FORMAT_YCBCR_REV) state[I915_TEXREG_SS2] |= SS2_COLORSPACE_CONVERSION; /* Shadow: diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index 9a723d3cd7..1c3da63da9 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -589,7 +589,7 @@ i915_state_draw_region(struct intel_context *intel, DSTORG_VERT_BIAS(0x8) | /* .5 */ LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL); if (irb != NULL) { - switch (irb->texformat->MesaFormat) { + switch (irb->texformat) { case MESA_FORMAT_ARGB8888: value |= DV_PF_8888; break; @@ -604,7 +604,7 @@ i915_state_draw_region(struct intel_context *intel, break; default: _mesa_problem(ctx, "Bad renderbuffer format: %d\n", - irb->texformat->MesaFormat); + irb->texformat); } } diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 2292de94c4..46df778bee 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -288,7 +288,7 @@ static void brw_wm_populate_key( struct brw_context *brw, const struct gl_texture_image *img = t->Image[0][t->BaseLevel]; if (img->InternalFormat == GL_YCBCR_MESA) { key->yuvtex_mask |= 1 << i; - if (img->TexFormat->MesaFormat == MESA_FORMAT_YCBCR) + if (img->TexFormat == MESA_FORMAT_YCBCR) key->yuvtex_swap_mask |= 1 << i; } diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 51539ac1e7..855fe7593d 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -287,7 +287,7 @@ brw_update_texture_surface( GLcontext *ctx, GLuint unit ) key.bo = NULL; key.offset = intelObj->textureOffset; } else { - key.format = firstImage->TexFormat->MesaFormat; + key.format = firstImage->TexFormat; key.internal_format = firstImage->InternalFormat; key.pitch = intelObj->mt->pitch; key.depth = firstImage->Depth; @@ -527,7 +527,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw, region_bo = region->buffer; key.surface_type = BRW_SURFACE_2D; - switch (irb->texformat->MesaFormat) { + switch (irb->texformat) { case MESA_FORMAT_ARGB8888: key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; break; @@ -541,8 +541,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw, key.surface_format = BRW_SURFACEFORMAT_B4G4R4A4_UNORM; break; default: - _mesa_problem(ctx, "Bad renderbuffer format: %d\n", - irb->texformat->MesaFormat); + _mesa_problem(ctx, "Bad renderbuffer format: %d\n", irb->texformat); } key.tiling = region->tiling; if (brw->intel.intelScreen->driScrnPriv->dri2.enabled) { diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index 43141c509c..799b22cc90 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -496,7 +496,7 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]); CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]); - switch (irb->texformat->MesaFormat) { + switch (irb->texformat) { case MESA_FORMAT_ARGB8888: clearVal = intel->ClearColor8888; break; @@ -513,7 +513,7 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) break; default: _mesa_problem(ctx, "Unexpected renderbuffer format: %d\n", - irb->texformat->MesaFormat); + irb->texformat); clearVal = 0; } } diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 0a3d0654d7..1be381b9ea 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -120,7 +120,7 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, rb->RedBits = 5; rb->GreenBits = 6; rb->BlueBits = 5; - irb->texformat = &_mesa_texformat_rgb565; + irb->texformat = MESA_FORMAT_RGB565; cpp = 2; break; case GL_RGB: @@ -134,7 +134,7 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, rb->GreenBits = 8; rb->BlueBits = 8; rb->AlphaBits = 0; - irb->texformat = &_mesa_texformat_argb8888; /* XXX: Need xrgb8888 */ + irb->texformat = MESA_FORMAT_ARGB8888; /* XXX: Need xrgb8888 */ cpp = 4; break; case GL_RGBA: @@ -151,7 +151,7 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, rb->GreenBits = 8; rb->BlueBits = 8; rb->AlphaBits = 8; - irb->texformat = &_mesa_texformat_argb8888; + irb->texformat = MESA_FORMAT_ARGB8888; cpp = 4; break; case GL_STENCIL_INDEX: @@ -164,14 +164,14 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, rb->DataType = GL_UNSIGNED_INT_24_8_EXT; rb->StencilBits = 8; cpp = 4; - irb->texformat = &_mesa_texformat_s8_z24; + irb->texformat = MESA_FORMAT_S8_Z24; break; case GL_DEPTH_COMPONENT16: rb->_ActualFormat = GL_DEPTH_COMPONENT16; rb->DataType = GL_UNSIGNED_SHORT; rb->DepthBits = 16; cpp = 2; - irb->texformat = &_mesa_texformat_z16; + irb->texformat = MESA_FORMAT_Z16; break; case GL_DEPTH_COMPONENT: case GL_DEPTH_COMPONENT24: @@ -180,7 +180,7 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, rb->DataType = GL_UNSIGNED_INT_24_8_EXT; rb->DepthBits = 24; cpp = 4; - irb->texformat = &_mesa_texformat_s8_z24; + irb->texformat = MESA_FORMAT_S8_Z24; break; case GL_DEPTH_STENCIL_EXT: case GL_DEPTH24_STENCIL8_EXT: @@ -189,7 +189,7 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, rb->DepthBits = 24; rb->StencilBits = 8; cpp = 4; - irb->texformat = &_mesa_texformat_s8_z24; + irb->texformat = MESA_FORMAT_S8_Z24; break; default: _mesa_problem(ctx, @@ -331,7 +331,7 @@ intel_create_renderbuffer(GLenum intFormat) irb->Base.GreenBits = 6; irb->Base.BlueBits = 5; irb->Base.DataType = GL_UNSIGNED_BYTE; - irb->texformat = &_mesa_texformat_rgb565; + irb->texformat = MESA_FORMAT_RGB565; break; case GL_RGB8: irb->Base._ActualFormat = GL_RGB8; @@ -341,7 +341,7 @@ intel_create_renderbuffer(GLenum intFormat) irb->Base.BlueBits = 8; irb->Base.AlphaBits = 0; irb->Base.DataType = GL_UNSIGNED_BYTE; - irb->texformat = &_mesa_texformat_argb8888; /* XXX: Need xrgb8888 */ + irb->texformat = MESA_FORMAT_ARGB8888; /* XXX: NEED XRGB8888 */ break; case GL_RGBA8: irb->Base._ActualFormat = GL_RGBA8; @@ -351,28 +351,28 @@ intel_create_renderbuffer(GLenum intFormat) irb->Base.BlueBits = 8; irb->Base.AlphaBits = 8; irb->Base.DataType = GL_UNSIGNED_BYTE; - irb->texformat = &_mesa_texformat_argb8888; + irb->texformat = MESA_FORMAT_ARGB8888; break; case GL_STENCIL_INDEX8_EXT: irb->Base._ActualFormat = GL_STENCIL_INDEX8_EXT; irb->Base._BaseFormat = GL_STENCIL_INDEX; irb->Base.StencilBits = 8; irb->Base.DataType = GL_UNSIGNED_BYTE; - irb->texformat = &_mesa_texformat_s8_z24; + irb->texformat = MESA_FORMAT_S8_Z24; break; case GL_DEPTH_COMPONENT16: irb->Base._ActualFormat = GL_DEPTH_COMPONENT16; irb->Base._BaseFormat = GL_DEPTH_COMPONENT; irb->Base.DepthBits = 16; irb->Base.DataType = GL_UNSIGNED_SHORT; - irb->texformat = &_mesa_texformat_z16; + irb->texformat = MESA_FORMAT_Z16; break; case GL_DEPTH_COMPONENT24: irb->Base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; irb->Base._BaseFormat = GL_DEPTH_COMPONENT; irb->Base.DepthBits = 24; irb->Base.DataType = GL_UNSIGNED_INT; - irb->texformat = &_mesa_texformat_s8_z24; + irb->texformat = MESA_FORMAT_S8_Z24; break; case GL_DEPTH24_STENCIL8_EXT: irb->Base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; @@ -380,7 +380,7 @@ intel_create_renderbuffer(GLenum intFormat) irb->Base.DepthBits = 24; irb->Base.StencilBits = 8; irb->Base.DataType = GL_UNSIGNED_INT_24_8_EXT; - irb->texformat = &_mesa_texformat_s8_z24; + irb->texformat = MESA_FORMAT_S8_Z24; break; default: _mesa_problem(NULL, @@ -468,49 +468,48 @@ intel_update_wrapper(GLcontext *ctx, struct intel_renderbuffer *irb, irb->texformat = texImage->TexFormat; gl_format texFormat; - if (texImage->TexFormat == &_mesa_texformat_argb8888) { + if (texImage->TexFormat == MESA_FORMAT_ARGB8888) { irb->Base._ActualFormat = GL_RGBA8; irb->Base._BaseFormat = GL_RGBA; irb->Base.DataType = GL_UNSIGNED_BYTE; DBG("Render to RGBA8 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_rgb565) { + else if (texImage->TexFormat == MESA_FORMAT_RGB565) { irb->Base._ActualFormat = GL_RGB5; irb->Base._BaseFormat = GL_RGB; irb->Base.DataType = GL_UNSIGNED_BYTE; DBG("Render to RGB5 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_argb1555) { + else if (texImage->TexFormat == MESA_FORMAT_ARGB1555) { irb->Base._ActualFormat = GL_RGB5_A1; irb->Base._BaseFormat = GL_RGBA; irb->Base.DataType = GL_UNSIGNED_BYTE; DBG("Render to ARGB1555 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_argb4444) { + else if (texImage->TexFormat == MESA_FORMAT_ARGB4444) { irb->Base._ActualFormat = GL_RGBA4; irb->Base._BaseFormat = GL_RGBA; irb->Base.DataType = GL_UNSIGNED_BYTE; DBG("Render to ARGB4444 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_z16) { + else if (texImage->TexFormat == MESA_FORMAT_Z16) { irb->Base._ActualFormat = GL_DEPTH_COMPONENT16; irb->Base._BaseFormat = GL_DEPTH_COMPONENT; irb->Base.DataType = GL_UNSIGNED_SHORT; DBG("Render to DEPTH16 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_s8_z24) { + else if (texImage->TexFormat == MESA_FORMAT_S8_Z24) { irb->Base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; irb->Base._BaseFormat = GL_DEPTH_STENCIL_EXT; irb->Base.DataType = GL_UNSIGNED_INT_24_8_EXT; DBG("Render to DEPTH_STENCIL texture OK\n"); } else { - DBG("Render to texture BAD FORMAT %d\n", - texImage->TexFormat->MesaFormat); + DBG("Render to texture BAD FORMAT %d\n", texImage->TexFormat); return GL_FALSE; } - texFormat = texImage->TexFormat->MesaFormat; + texFormat = texImage->TexFormat; irb->Base.InternalFormat = irb->Base._ActualFormat; irb->Base.Width = texImage->Width; @@ -690,7 +689,7 @@ intel_validate_framebuffer(GLcontext *ctx, struct gl_framebuffer *fb) continue; } - switch (irb->texformat->MesaFormat) { + switch (irb->texformat) { case MESA_FORMAT_ARGB8888: case MESA_FORMAT_RGB565: case MESA_FORMAT_ARGB1555: diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h index f0665af482..e0584e3494 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.h +++ b/src/mesa/drivers/dri/intel/intel_fbo.h @@ -28,6 +28,7 @@ #ifndef INTEL_FBO_H #define INTEL_FBO_H +#include "main/formats.h" #include "intel_screen.h" struct intel_context; @@ -61,7 +62,7 @@ struct intel_renderbuffer struct gl_renderbuffer Base; struct intel_region *region; - const struct gl_texture_format *texformat; + gl_format texformat; GLuint vbl_pending; /**< vblank sequence number of pending flip */ diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index 188333c75f..6bb7481ae4 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -307,7 +307,7 @@ intel_miptree_match_image(struct intel_mipmap_tree *mt, if (!image->IsCompressed && !mt->compressed && - _mesa_get_format_bytes(image->TexFormat->MesaFormat) != mt->cpp) + _mesa_get_format_bytes(image->TexFormat) != mt->cpp) return GL_FALSE; /* Test image dimensions against the base level image adjusted for diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index 28eabbc005..f754ce0cd1 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -578,7 +578,7 @@ intel_set_span_functions(struct intel_context *intel, else tiling = I915_TILING_NONE; - switch (irb->texformat->MesaFormat) { + switch (irb->texformat) { case MESA_FORMAT_RGB565: switch (tiling) { case I915_TILING_NONE: diff --git a/src/mesa/drivers/dri/intel/intel_tex.h b/src/mesa/drivers/dri/intel/intel_tex.h index 471aa2a240..f67e1db9e3 100644 --- a/src/mesa/drivers/dri/intel/intel_tex.h +++ b/src/mesa/drivers/dri/intel/intel_tex.h @@ -29,6 +29,7 @@ #define INTELTEX_INC #include "main/mtypes.h" +#include "main/formats.h" #include "intel_context.h" #include "texmem.h" @@ -41,10 +42,8 @@ void intelInitTextureSubImageFuncs(struct dd_function_table *functions); void intelInitTextureCopyImageFuncs(struct dd_function_table *functions); -const struct gl_texture_format *intelChooseTextureFormat(GLcontext * ctx, - GLint internalFormat, - GLenum format, - GLenum type); +gl_format intelChooseTextureFormat(GLcontext *ctx, GLint internalFormat, + GLenum format, GLenum type); void intelSetTexOffset(__DRIcontext *pDRICtx, GLint texname, unsigned long long offset, GLint depth, GLuint pitch); diff --git a/src/mesa/drivers/dri/intel/intel_tex_format.c b/src/mesa/drivers/dri/intel/intel_tex_format.c index 3322a71130..22c010bbd7 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_format.c +++ b/src/mesa/drivers/dri/intel/intel_tex_format.c @@ -16,7 +16,7 @@ * these if we take the step of simply swizzling the colors * immediately after sampling... */ -const struct gl_texture_format * +gl_format intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, GLenum format, GLenum type) { @@ -34,48 +34,48 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, case GL_COMPRESSED_RGBA: if (format == GL_BGRA) { if (type == GL_UNSIGNED_BYTE || type == GL_UNSIGNED_INT_8_8_8_8_REV) { - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; } else if (type == GL_UNSIGNED_SHORT_4_4_4_4_REV) { - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; } else if (type == GL_UNSIGNED_SHORT_1_5_5_5_REV) { - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; } } - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; case 3: case GL_RGB: case GL_COMPRESSED_RGB: if (format == GL_RGB && type == GL_UNSIGNED_SHORT_5_6_5) { - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; } - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_rgb565; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_RGB565; case GL_RGBA8: case GL_RGB10_A2: case GL_RGBA12: case GL_RGBA16: - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; case GL_RGBA4: case GL_RGBA2: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_RGB5_A1: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case GL_RGB8: case GL_RGB10: case GL_RGB12: case GL_RGB16: - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; case GL_RGB5: case GL_RGB4: case GL_R3_G3_B2: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; case GL_ALPHA: case GL_ALPHA4: @@ -83,7 +83,7 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, case GL_ALPHA12: case GL_ALPHA16: case GL_COMPRESSED_ALPHA: - return &_mesa_texformat_a8; + return MESA_FORMAT_A8; case 1: case GL_LUMINANCE: @@ -92,7 +92,7 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, case GL_LUMINANCE12: case GL_LUMINANCE16: case GL_COMPRESSED_LUMINANCE: - return &_mesa_texformat_l8; + return MESA_FORMAT_L8; case 2: case GL_LUMINANCE_ALPHA: @@ -103,7 +103,7 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, case GL_LUMINANCE12_ALPHA12: case GL_LUMINANCE16_ALPHA16: case GL_COMPRESSED_LUMINANCE_ALPHA: - return &_mesa_texformat_al88; + return MESA_FORMAT_AL88; case GL_INTENSITY: case GL_INTENSITY4: @@ -111,41 +111,41 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, case GL_INTENSITY12: case GL_INTENSITY16: case GL_COMPRESSED_INTENSITY: - return &_mesa_texformat_i8; + return MESA_FORMAT_I8; case GL_YCBCR_MESA: if (type == GL_UNSIGNED_SHORT_8_8_MESA || type == GL_UNSIGNED_BYTE) - return &_mesa_texformat_ycbcr; + return MESA_FORMAT_YCBCR; else - return &_mesa_texformat_ycbcr_rev; + return MESA_FORMAT_YCBCR_REV; case GL_COMPRESSED_RGB_FXT1_3DFX: - return &_mesa_texformat_rgb_fxt1; + return MESA_FORMAT_RGB_FXT1; case GL_COMPRESSED_RGBA_FXT1_3DFX: - return &_mesa_texformat_rgba_fxt1; + return MESA_FORMAT_RGBA_FXT1; case GL_RGB_S3TC: case GL_RGB4_S3TC: case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: - return &_mesa_texformat_rgb_dxt1; + return MESA_FORMAT_RGB_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: - return &_mesa_texformat_rgba_dxt1; + return MESA_FORMAT_RGBA_DXT1; case GL_RGBA_S3TC: case GL_RGBA4_S3TC: case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: - return &_mesa_texformat_rgba_dxt3; + return MESA_FORMAT_RGBA_DXT3; case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: - return &_mesa_texformat_rgba_dxt5; + return MESA_FORMAT_RGBA_DXT5; case GL_DEPTH_COMPONENT: case GL_DEPTH_COMPONENT16: case GL_DEPTH_COMPONENT24: case GL_DEPTH_COMPONENT32: #if 0 - return &_mesa_texformat_z16; + return MESA_FORMAT_Z16; #else /* fall-through. * 16bpp depth texture can't be paired with a stencil buffer so @@ -154,7 +154,7 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, #endif case GL_DEPTH_STENCIL_EXT: case GL_DEPTH24_STENCIL8_EXT: - return &_mesa_texformat_s8_z24; + return MESA_FORMAT_S8_Z24; #ifndef I915 case GL_SRGB_EXT: @@ -165,41 +165,41 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, case GL_COMPRESSED_SRGB_ALPHA_EXT: case GL_COMPRESSED_SLUMINANCE_EXT: case GL_COMPRESSED_SLUMINANCE_ALPHA_EXT: - return &_mesa_texformat_sargb8; + return MESA_FORMAT_SARGB8; case GL_SLUMINANCE_EXT: case GL_SLUMINANCE8_EXT: if (IS_G4X(intel->intelScreen->deviceID)) - return &_mesa_texformat_sl8; + return MESA_FORMAT_SL8; else - return &_mesa_texformat_sargb8; + return MESA_FORMAT_SARGB8; case GL_SLUMINANCE_ALPHA_EXT: case GL_SLUMINANCE8_ALPHA8_EXT: if (IS_G4X(intel->intelScreen->deviceID)) - return &_mesa_texformat_sla8; + return MESA_FORMAT_SLA8; else - return &_mesa_texformat_sargb8; + return MESA_FORMAT_SARGB8; case GL_COMPRESSED_SRGB_S3TC_DXT1_EXT: case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT1_EXT: case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT3_EXT: case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT5_EXT: - return &_mesa_texformat_srgb_dxt1; + return MESA_FORMAT_SRGB_DXT1; /* i915 could also do this */ case GL_DUDV_ATI: case GL_DU8DV8_ATI: - return &_mesa_texformat_dudv8; + return MESA_FORMAT_DUDV8; case GL_RGBA_SNORM: case GL_RGBA8_SNORM: - return &_mesa_texformat_signed_rgba8888_rev; + return MESA_FORMAT_SIGNED_RGBA8888_REV; #endif default: fprintf(stderr, "unexpected texture format %s in %s\n", _mesa_lookup_enum_by_nr(internalFormat), __FUNCTION__); - return NULL; + return MESA_FORMAT_NONE; } - return NULL; /* never get here */ + return MESA_FORMAT_NONE; /* never get here */ } int intel_compressed_num_bytes(GLuint mesaFormat) diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c index 0e13f600a6..bbbeac8f7f 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_image.c +++ b/src/mesa/drivers/dri/intel/intel_tex_image.c @@ -126,9 +126,9 @@ guess_and_alloc_mipmap_tree(struct intel_context *intel, assert(!intelObj->mt); if (intelImage->base.IsCompressed) - comp_byte = intel_compressed_num_bytes(intelImage->base.TexFormat->MesaFormat); + comp_byte = intel_compressed_num_bytes(intelImage->base.TexFormat); - texelBytes = _mesa_get_format_bytes(intelImage->base.TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(intelImage->base.TexFormat); intelObj->mt = intel_miptree_create(intel, intelObj->base.Target, @@ -171,7 +171,7 @@ target_to_face(GLenum target) static GLboolean check_pbo_format(GLint internalFormat, GLenum format, GLenum type, - const struct gl_texture_format *mesa_format) + gl_format mesa_format) { switch (internalFormat) { case 4: @@ -179,12 +179,12 @@ check_pbo_format(GLint internalFormat, return (format == GL_BGRA && (type == GL_UNSIGNED_BYTE || type == GL_UNSIGNED_INT_8_8_8_8_REV) && - mesa_format == &_mesa_texformat_argb8888); + mesa_format == MESA_FORMAT_ARGB8888); case 3: case GL_RGB: return (format == GL_RGB && type == GL_UNSIGNED_SHORT_5_6_5 && - mesa_format == &_mesa_texformat_rgb565); + mesa_format == MESA_FORMAT_RGB565); case GL_YCBCR_MESA: return (type == GL_UNSIGNED_SHORT_8_8_MESA || type == GL_UNSIGNED_BYTE); default: @@ -337,15 +337,15 @@ intelTexImage(GLcontext * ctx, _mesa_set_fetch_functions(texImage, dims); - if (_mesa_is_format_compressed(texImage->TexFormat->MesaFormat)) { + if (_mesa_is_format_compressed(texImage->TexFormat)) { texelBytes = 0; texImage->IsCompressed = GL_TRUE; texImage->CompressedSize = ctx->Driver.CompressedTextureSize(ctx, texImage->Width, texImage->Height, texImage->Depth, - texImage->TexFormat->MesaFormat); + texImage->TexFormat); } else { - texelBytes = _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); /* Minimum pitch of 32 bytes */ if (postConvWidth * texelBytes < 32) { @@ -403,11 +403,11 @@ intelTexImage(GLcontext * ctx, assert(intelImage->mt); } else if (intelImage->base.Border == 0) { int comp_byte = 0; - GLuint texelBytes = _mesa_get_format_bytes(intelImage->base.TexFormat->MesaFormat); - GLenum baseFormat = _mesa_get_format_base_format(intelImage->base.TexFormat->MesaFormat); + GLuint texelBytes = _mesa_get_format_bytes(intelImage->base.TexFormat); + GLenum baseFormat = _mesa_get_format_base_format(intelImage->base.TexFormat); if (intelImage->base.IsCompressed) { comp_byte = - intel_compressed_num_bytes(intelImage->base.TexFormat->MesaFormat); + intel_compressed_num_bytes(intelImage->base.TexFormat); } /* Didn't fit in the object miptree, but it's suitable for inclusion in @@ -497,7 +497,7 @@ intelTexImage(GLcontext * ctx, if (texImage->IsCompressed) { sizeInBytes = texImage->CompressedSize; dstRowStride = - _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width); + _mesa_compressed_row_stride(texImage->TexFormat, width); assert(dims != 3); } else { diff --git a/src/mesa/drivers/dri/intel/intel_tex_subimage.c b/src/mesa/drivers/dri/intel/intel_tex_subimage.c index ad5c2271a1..bba1b53009 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_subimage.c +++ b/src/mesa/drivers/dri/intel/intel_tex_subimage.c @@ -87,11 +87,11 @@ intelTexSubimage(GLcontext * ctx, else { if (texImage->IsCompressed) { dstRowStride = - _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width); + _mesa_compressed_row_stride(texImage->TexFormat, width); assert(dims != 3); } else { - dstRowStride = texImage->RowStride * _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + dstRowStride = texImage->RowStride * _mesa_get_format_bytes(texImage->TexFormat); } } diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c b/src/mesa/drivers/dri/intel/intel_tex_validate.c index 0393d7915a..0296c92523 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_validate.c +++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c @@ -166,11 +166,11 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit) } if (firstImage->base.IsCompressed) { - comp_byte = intel_compressed_num_bytes(firstImage->base.TexFormat->MesaFormat); + comp_byte = intel_compressed_num_bytes(firstImage->base.TexFormat); cpp = comp_byte; } else - cpp = _mesa_get_format_bytes(firstImage->base.TexFormat->MesaFormat); + cpp = _mesa_get_format_bytes(firstImage->base.TexFormat); /* Check tree can hold all active levels. Check tree matches * target, imageFormat, etc. diff --git a/src/mesa/drivers/dri/mach64/mach64_tex.c b/src/mesa/drivers/dri/mach64/mach64_tex.c index 225d23179e..02433e5dd8 100644 --- a/src/mesa/drivers/dri/mach64/mach64_tex.c +++ b/src/mesa/drivers/dri/mach64/mach64_tex.c @@ -138,7 +138,7 @@ mach64AllocTexObj( struct gl_texture_object *texObj ) /* Called by the _mesa_store_teximage[123]d() functions. */ -static const struct gl_texture_format * +static gl_format mach64ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type ) { @@ -167,15 +167,15 @@ mach64ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_RGBA2: case GL_COMPRESSED_RGBA: if (mmesa->mach64Screen->cpp == 4) - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; else - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_RGB5_A1: if (mmesa->mach64Screen->cpp == 4) - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; else - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case GL_RGBA8: case GL_RGB10_A2: @@ -183,9 +183,9 @@ mach64ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_RGBA16: case GL_RGBA4: if (mmesa->mach64Screen->cpp == 4) - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; else - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case 3: case GL_RGB: @@ -198,9 +198,9 @@ mach64ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_RGB16: case GL_COMPRESSED_RGB: if (mmesa->mach64Screen->cpp == 4) - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; else - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; case 1: case GL_LUMINANCE: @@ -210,9 +210,9 @@ mach64ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE16: case GL_COMPRESSED_LUMINANCE: if (mmesa->mach64Screen->cpp == 4) - return &_mesa_texformat_argb8888; /* inefficient but accurate */ + return MESA_FORMAT_ARGB8888; /* inefficient but accurate */ else - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case GL_INTENSITY4: case GL_INTENSITY: @@ -221,9 +221,9 @@ mach64ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_INTENSITY16: case GL_COMPRESSED_INTENSITY: if (mmesa->mach64Screen->cpp == 4) - return &_mesa_texformat_argb8888; /* inefficient but accurate */ + return MESA_FORMAT_ARGB8888; /* inefficient but accurate */ else - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_COLOR_INDEX: case GL_COLOR_INDEX1_EXT: @@ -232,18 +232,18 @@ mach64ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_COLOR_INDEX8_EXT: case GL_COLOR_INDEX12_EXT: case GL_COLOR_INDEX16_EXT: - return &_mesa_texformat_ci8; + return MESA_FORMAT_CI8; case GL_YCBCR_MESA: if (type == GL_UNSIGNED_SHORT_8_8_APPLE || type == GL_UNSIGNED_BYTE) - return &_mesa_texformat_ycbcr; + return MESA_FORMAT_YCBCR; else - return &_mesa_texformat_ycbcr_rev; + return MESA_FORMAT_YCBCR_REV; default: _mesa_problem( ctx, "unexpected format in %s", __FUNCTION__ ); - return NULL; + return MESA_FORMAT_NONE; } } diff --git a/src/mesa/drivers/dri/mach64/mach64_texmem.c b/src/mesa/drivers/dri/mach64/mach64_texmem.c index 843b231051..e83aeae3e1 100644 --- a/src/mesa/drivers/dri/mach64/mach64_texmem.c +++ b/src/mesa/drivers/dri/mach64/mach64_texmem.c @@ -86,7 +86,7 @@ static void mach64UploadAGPSubImage( mach64ContextPtr mmesa, if ( !image ) return; - texelBytes = _mesa_get_format_bytes(image->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(image->TexFormat); switch ( texelBytes ) { case 1: texelsPerDword = 4; break; @@ -153,7 +153,7 @@ static void mach64UploadLocalSubImage( mach64ContextPtr mmesa, if ( !image ) return; - texelBytes = _mesa_get_format_bytes(image->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(image->TexFormat); switch ( texelBytes ) { case 1: texelsPerDword = 4; break; diff --git a/src/mesa/drivers/dri/mach64/mach64_texstate.c b/src/mesa/drivers/dri/mach64/mach64_texstate.c index ff03b0c40a..c333355324 100644 --- a/src/mesa/drivers/dri/mach64/mach64_texstate.c +++ b/src/mesa/drivers/dri/mach64/mach64_texstate.c @@ -55,7 +55,7 @@ static void mach64SetTexImages( mach64ContextPtr mmesa, if ( MACH64_DEBUG & DEBUG_VERBOSE_API ) fprintf( stderr, "%s( %p )\n", __FUNCTION__, tObj ); - switch (baseImage->TexFormat->MesaFormat) { + switch (baseImage->TexFormat) { case MESA_FORMAT_ARGB8888: t->textureFormat = MACH64_DATATYPE_ARGB8888; break; @@ -89,7 +89,7 @@ static void mach64SetTexImages( mach64ContextPtr mmesa, totalSize = ( baseImage->Height * baseImage->Width * - _mesa_get_format_bytes(baseImage->TexFormat->MesaFormat) ); + _mesa_get_format_bytes(baseImage->TexFormat) ); totalSize = (totalSize + 31) & ~31; diff --git a/src/mesa/drivers/dri/mga/mga_texstate.c b/src/mesa/drivers/dri/mga/mga_texstate.c index 8f78ab9bd4..d52f0fac75 100644 --- a/src/mesa/drivers/dri/mga/mga_texstate.c +++ b/src/mesa/drivers/dri/mga/mga_texstate.c @@ -94,14 +94,14 @@ mgaSetTexImages( mgaContextPtr mmesa, return; } #else - if ( (baseImage->TexFormat->MesaFormat >= TMC_nr_tformat) - || (TMC_tformat[ baseImage->TexFormat->MesaFormat ] == 0) ) + if ( (baseImage->TexFormat >= TMC_nr_tformat) + || (TMC_tformat[ baseImage->TexFormat ] == 0) ) { _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__); return; } - txformat = TMC_tformat[ baseImage->TexFormat->MesaFormat ]; + txformat = TMC_tformat[ baseImage->TexFormat ]; #endif /* MGA_USE_TABLE_FOR_FORMAT */ @@ -131,7 +131,7 @@ mgaSetTexImages( mgaContextPtr mmesa, break; size = texImage->Width * texImage->Height * - _mesa_get_format_bytes(baseImage->TexFormat->MesaFormat); + _mesa_get_format_bytes(baseImage->TexFormat); t->offsets[i] = totalSize; t->base.dirty_images[0] |= (1<TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); length = texImage->Width * texImage->Height * texelBytes; if ( t->base.heap->heapId == MGA_CARD_HEAP ) { unsigned tex_offset = 0; diff --git a/src/mesa/drivers/dri/r128/r128_tex.c b/src/mesa/drivers/dri/r128/r128_tex.c index 0920270d7b..6acda445f7 100644 --- a/src/mesa/drivers/dri/r128/r128_tex.c +++ b/src/mesa/drivers/dri/r128/r128_tex.c @@ -178,7 +178,7 @@ static r128TexObjPtr r128AllocTexObj( struct gl_texture_object *texObj ) /* Called by the _mesa_store_teximage[123]d() functions. */ -static const struct gl_texture_format * +static gl_format r128ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type ) { @@ -282,13 +282,13 @@ r128ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_YCBCR_MESA: if (type == GL_UNSIGNED_SHORT_8_8_APPLE || type == GL_UNSIGNED_BYTE) - return &_mesa_texformat_ycbcr; + return MESA_FORMAT_YCBCR; else - return &_mesa_texformat_ycbcr_rev; + return MESA_FORMAT_YCBCR_REV; default: _mesa_problem( ctx, "unexpected format in %s", __FUNCTION__ ); - return NULL; + return MESA_FORMAT_NONE; } } diff --git a/src/mesa/drivers/dri/r128/r128_texmem.c b/src/mesa/drivers/dri/r128/r128_texmem.c index c369e14bd5..84f8563b89 100644 --- a/src/mesa/drivers/dri/r128/r128_texmem.c +++ b/src/mesa/drivers/dri/r128/r128_texmem.c @@ -95,7 +95,7 @@ static void uploadSubImage( r128ContextPtr rmesa, r128TexObjPtr t, if ( !image ) return; - switch ( _mesa_get_format_bytes(image->TexFormat->MesaFormat) ) { + switch ( _mesa_get_format_bytes(image->TexFormat) ) { case 1: texelsPerDword = 4; break; case 2: texelsPerDword = 2; break; case 4: texelsPerDword = 1; break; @@ -216,7 +216,7 @@ static void uploadSubImage( r128ContextPtr rmesa, r128TexObjPtr t, /* Copy the next chunck of the texture image into the blit buffer */ { const GLuint texelBytes = - _mesa_get_format_bytes(image->TexFormat->MesaFormat); + _mesa_get_format_bytes(image->TexFormat); const GLubyte *src = (const GLubyte *) image->Data + (y * image->Width + x) * texelBytes; const GLuint bytes = width * height * texelBytes; diff --git a/src/mesa/drivers/dri/r128/r128_texstate.c b/src/mesa/drivers/dri/r128/r128_texstate.c index 9f4f9aea2d..2e71c25861 100644 --- a/src/mesa/drivers/dri/r128/r128_texstate.c +++ b/src/mesa/drivers/dri/r128/r128_texstate.c @@ -61,7 +61,7 @@ static void r128SetTexImages( r128ContextPtr rmesa, if ( R128_DEBUG & DEBUG_VERBOSE_API ) fprintf( stderr, "%s( %p )\n", __FUNCTION__, (void *) tObj ); - switch (baseImage->TexFormat->MesaFormat) { + switch (baseImage->TexFormat) { case MESA_FORMAT_ARGB8888: case MESA_FORMAT_ARGB8888_REV: t->textureFormat = R128_DATATYPE_ARGB8888; @@ -123,7 +123,7 @@ static void r128SetTexImages( r128ContextPtr rmesa, totalSize += (tObj->Image[0][i]->Height * tObj->Image[0][i]->Width * - _mesa_get_format_bytes(tObj->Image[0][i]->TexFormat->MesaFormat)); + _mesa_get_format_bytes(tObj->Image[0][i]->TexFormat)); /* Offsets must be 32-byte aligned for host data blits and tiling */ totalSize = (totalSize + 31) & ~31; diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index 03f0613e7a..daca318684 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -1437,11 +1437,11 @@ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t) log2Width = firstImage->WidthLog2; log2Height = firstImage->HeightLog2; log2Depth = firstImage->DepthLog2; - texelBytes = _mesa_get_format_bytes(firstImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(firstImage->TexFormat); if (!t->image_override) { - if (VALID_FORMAT(firstImage->TexFormat->MesaFormat)) { + if (VALID_FORMAT(firstImage->TexFormat)) { const struct tx_table *table = _mesa_little_endian() ? tx_table_le : tx_table_be; @@ -1449,8 +1449,8 @@ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t) R200_TXFORMAT_ALPHA_IN_MAP); t->pp_txfilter &= ~R200_YUV_TO_RGB; - t->pp_txformat |= table[ firstImage->TexFormat->MesaFormat ].format; - t->pp_txfilter |= table[ firstImage->TexFormat->MesaFormat ].filter; + t->pp_txformat |= table[ firstImage->TexFormat ].format; + t->pp_txfilter |= table[ firstImage->TexFormat ].filter; } else { _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__); diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index cc40e0d1dc..cb826248f3 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -156,7 +156,7 @@ void r300SetDepthTexMode(struct gl_texture_object *tObj) t = radeon_tex_obj(tObj); - switch (tObj->Image[0][tObj->BaseLevel]->TexFormat->MesaFormat) { + switch (tObj->Image[0][tObj->BaseLevel]->TexFormat) { case MESA_FORMAT_Z16: format = formats[0]; break; @@ -208,14 +208,14 @@ static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t) firstImage = t->base.Image[0][firstlevel]; if (!t->image_override - && VALID_FORMAT(firstImage->TexFormat->MesaFormat)) { + && VALID_FORMAT(firstImage->TexFormat)) { if (firstImage->_BaseFormat == GL_DEPTH_COMPONENT) { r300SetDepthTexMode(&t->base); } else { - t->pp_txformat = tx_table[firstImage->TexFormat->MesaFormat].format; + t->pp_txformat = tx_table[firstImage->TexFormat].format; } - t->pp_txfilter |= tx_table[firstImage->TexFormat->MesaFormat].filter; + t->pp_txfilter |= tx_table[firstImage->TexFormat].filter; } else if (!t->image_override) { _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__); diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 7d7e77d355..55b455edc0 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -591,7 +591,7 @@ void r600SetDepthTexMode(struct gl_texture_object *tObj) t = radeon_tex_obj(tObj); - r600GetTexFormat(tObj, tObj->Image[0][tObj->BaseLevel]->TexFormat->MesaFormat); + r600GetTexFormat(tObj, tObj->Image[0][tObj->BaseLevel]->TexFormat); } @@ -616,7 +616,7 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex firstImage = t->base.Image[0][firstlevel]; if (!t->image_override) { - if (!r600GetTexFormat(texObj, firstImage->TexFormat->MesaFormat)) { + if (!r600GetTexFormat(texObj, firstImage->TexFormat)) { radeon_error("unexpected texture format in %s\n", __FUNCTION__); return; diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index f19170b612..90ea2ec335 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -390,42 +390,42 @@ radeon_update_wrapper(GLcontext *ctx, struct radeon_renderbuffer *rrb, gl_format texFormat; restart: - if (texImage->TexFormat == &_mesa_texformat_argb8888) { + if (texImage->TexFormat == MESA_FORMAT_ARGB8888) { rrb->cpp = 4; rrb->base._ActualFormat = GL_RGBA8; rrb->base._BaseFormat = GL_RGBA; rrb->base.DataType = GL_UNSIGNED_BYTE; DBG("Render to RGBA8 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_rgb565) { + else if (texImage->TexFormat == MESA_FORMAT_RGB565) { rrb->cpp = 2; rrb->base._ActualFormat = GL_RGB5; rrb->base._BaseFormat = GL_RGB; rrb->base.DataType = GL_UNSIGNED_BYTE; DBG("Render to RGB5 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_argb1555) { + else if (texImage->TexFormat == MESA_FORMAT_ARGB1555) { rrb->cpp = 2; rrb->base._ActualFormat = GL_RGB5_A1; rrb->base._BaseFormat = GL_RGBA; rrb->base.DataType = GL_UNSIGNED_BYTE; DBG("Render to ARGB1555 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_argb4444) { + else if (texImage->TexFormat == MESA_FORMAT_ARGB4444) { rrb->cpp = 2; rrb->base._ActualFormat = GL_RGBA4; rrb->base._BaseFormat = GL_RGBA; rrb->base.DataType = GL_UNSIGNED_BYTE; DBG("Render to ARGB1555 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_z16) { + else if (texImage->TexFormat == MESA_FORMAT_Z16) { rrb->cpp = 2; rrb->base._ActualFormat = GL_DEPTH_COMPONENT16; rrb->base._BaseFormat = GL_DEPTH_COMPONENT; rrb->base.DataType = GL_UNSIGNED_SHORT; DBG("Render to DEPTH16 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_s8_z24) { + else if (texImage->TexFormat == MESA_FORMAT_S8_Z24) { rrb->cpp = 4; rrb->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; rrb->base._BaseFormat = GL_DEPTH_STENCIL_EXT; @@ -436,29 +436,30 @@ restart: /* try redoing the FBO */ if (retry == 1) { DBG("Render to texture BAD FORMAT %d\n", - texImage->TexFormat->MesaFormat); + texImage->TexFormat); return GL_FALSE; } texImage->TexFormat = radeonChooseTextureFormat(ctx, texImage->InternalFormat, 0, - _mesa_get_format_datatype(texImage->TexFormat->MesaFormat), + _mesa_get_format_datatype(texImage->TexFormat), 1); retry++; goto restart; } - texFormat = texImage->TexFormat->MesaFormat; + texFormat = texImage->TexFormat; rrb->pitch = texImage->Width * rrb->cpp; rrb->base.InternalFormat = rrb->base._ActualFormat; rrb->base.Width = texImage->Width; rrb->base.Height = texImage->Height; - rrb->Base.RedBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_RED_SIZE); - rrb->Base.GreenBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_GREEN_SIZE); - rrb->Base.BlueBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_BLUE_SIZE); - rrb->Base.AlphaBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_ALPHA_SIZE); - rrb->Base.DepthBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_DEPTH_SIZE_ARB); - rrb->Base.StencilBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_STENCIL_SIZE_EXT); + rrb->base.RedBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_RED_SIZE); + rrb->base.GreenBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_GREEN_SIZE); + rrb->base.BlueBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_BLUE_SIZE); + rrb->base.AlphaBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_ALPHA_SIZE); + rrb->base.DepthBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_DEPTH_SIZE_ARB); + rrb->base.StencilBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_STENCIL_SIZE_EXT); + rrb->base.Delete = radeon_delete_renderbuffer; rrb->base.AllocStorage = radeon_nop_alloc_storage; diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index 851474f871..b602bfb4b0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -325,7 +325,7 @@ GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt, if (!texImage->IsCompressed && !mt->compressed && - _mesa_get_format_bytes(texImage->TexFormat->MesaFormat) != mt->bpp) + _mesa_get_format_bytes(texImage->TexFormat) != mt->bpp) return GL_FALSE; lvl = &mt->levels[level - mt->firstLevel]; @@ -354,8 +354,8 @@ GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_textu numfaces = 6; firstImage = texObj->Image[0][firstLevel]; - compressed = firstImage->IsCompressed ? firstImage->TexFormat->MesaFormat : 0; - texelBytes = _mesa_get_format_bytes(firstImage->TexFormat->MesaFormat); + compressed = firstImage->IsCompressed ? firstImage->TexFormat : 0; + texelBytes = _mesa_get_format_bytes(firstImage->TexFormat); return (mt->firstLevel == firstLevel && mt->lastLevel == lastLevel && @@ -374,7 +374,7 @@ GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_textu void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t, radeon_texture_image *image, GLuint face, GLuint level) { - GLuint compressed = image->base.IsCompressed ? image->base.TexFormat->MesaFormat : 0; + GLuint compressed = image->base.IsCompressed ? image->base.TexFormat : 0; GLuint numfaces = 1; GLuint firstLevel, lastLevel; GLuint texelBytes; @@ -388,7 +388,7 @@ void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t, if (level != firstLevel || face >= numfaces) return; - texelBytes = _mesa_get_format_bytes(image->base.TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(image->base.TexFormat); t->mt = radeon_miptree_create(rmesa, t, t->base.Target, image->base.InternalFormat, diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index a00497a8f9..1064602504 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -1031,18 +1031,18 @@ static GLboolean setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t, int log2Width = firstImage->WidthLog2; log2Height = firstImage->HeightLog2; log2Depth = firstImage->DepthLog2; - texelBytes = _mesa_get_format_bytes(firstImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(firstImage->TexFormat); if (!t->image_override) { - if (VALID_FORMAT(firstImage->TexFormat->MesaFormat)) { + if (VALID_FORMAT(firstImage->TexFormat)) { const struct tx_table *table = tx_table; t->pp_txformat &= ~(RADEON_TXFORMAT_FORMAT_MASK | RADEON_TXFORMAT_ALPHA_IN_MAP); t->pp_txfilter &= ~RADEON_YUV_TO_RGB; - t->pp_txformat |= table[ firstImage->TexFormat->MesaFormat ].format; - t->pp_txfilter |= table[ firstImage->TexFormat->MesaFormat ].filter; + t->pp_txformat |= table[ firstImage->TexFormat ].format; + t->pp_txfilter |= table[ firstImage->TexFormat ].filter; } else { _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__); diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index 3ff8cad93e..0378b3c9fc 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -256,9 +256,9 @@ void radeonGenerateMipmap(GLcontext* ctx, GLenum target, struct gl_texture_objec /* try to find a format which will only need a memcopy */ -static const struct gl_texture_format *radeonChoose8888TexFormat(radeonContextPtr rmesa, - GLenum srcFormat, - GLenum srcType, GLboolean fbo) +static gl_format radeonChoose8888TexFormat(radeonContextPtr rmesa, + GLenum srcFormat, + GLenum srcType, GLboolean fbo) { const GLuint ui = 1; const GLubyte littleEndian = *((const GLubyte *)&ui); @@ -271,37 +271,37 @@ static const struct gl_texture_format *radeonChoose8888TexFormat(radeonContextPt (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && !littleEndian) || (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && littleEndian)) { - return &_mesa_texformat_rgba8888; + return MESA_FORMAT_RGBA8888; } else if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && littleEndian) || (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8) || (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && !littleEndian)) { - return &_mesa_texformat_rgba8888_rev; + return MESA_FORMAT_RGBA8888_REV; } else if (IS_R200_CLASS(rmesa->radeonScreen)) { return _dri_texformat_argb8888; } else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && !littleEndian) || srcType == GL_UNSIGNED_INT_8_8_8_8)) { - return &_mesa_texformat_argb8888_rev; + return MESA_FORMAT_ARGB8888_REV; } else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && littleEndian) || srcType == GL_UNSIGNED_INT_8_8_8_8_REV)) { - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; } else return _dri_texformat_argb8888; } -const struct gl_texture_format *radeonChooseTextureFormat_mesa(GLcontext * ctx, - GLint internalFormat, - GLenum format, - GLenum type) +gl_format radeonChooseTextureFormat_mesa(GLcontext * ctx, + GLint internalFormat, + GLenum format, + GLenum type) { return radeonChooseTextureFormat(ctx, internalFormat, format, type, 0); } -const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, - GLint internalFormat, - GLenum format, - GLenum type, GLboolean fbo) +gl_format radeonChooseTextureFormat(GLcontext * ctx, + GLint internalFormat, + GLenum format, + GLenum type, GLboolean fbo) { radeonContextPtr rmesa = RADEON_CONTEXT(ctx); const GLboolean do32bpt = @@ -425,50 +425,50 @@ const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, case GL_YCBCR_MESA: if (type == GL_UNSIGNED_SHORT_8_8_APPLE || type == GL_UNSIGNED_BYTE) - return &_mesa_texformat_ycbcr; + return MESA_FORMAT_YCBCR; else - return &_mesa_texformat_ycbcr_rev; + return MESA_FORMAT_YCBCR_REV; case GL_RGB_S3TC: case GL_RGB4_S3TC: case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: - return &_mesa_texformat_rgb_dxt1; + return MESA_FORMAT_RGB_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: - return &_mesa_texformat_rgba_dxt1; + return MESA_FORMAT_RGBA_DXT1; case GL_RGBA_S3TC: case GL_RGBA4_S3TC: case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: - return &_mesa_texformat_rgba_dxt3; + return MESA_FORMAT_RGBA_DXT3; case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: - return &_mesa_texformat_rgba_dxt5; + return MESA_FORMAT_RGBA_DXT5; case GL_ALPHA16F_ARB: - return &_mesa_texformat_alpha_float16; + return MESA_FORMAT_ALPHA_FLOAT16; case GL_ALPHA32F_ARB: - return &_mesa_texformat_alpha_float32; + return MESA_FORMAT_ALPHA_FLOAT32; case GL_LUMINANCE16F_ARB: - return &_mesa_texformat_luminance_float16; + return MESA_FORMAT_LUMINANCE_FLOAT16; case GL_LUMINANCE32F_ARB: - return &_mesa_texformat_luminance_float32; + return MESA_FORMAT_LUMINANCE_FLOAT32; case GL_LUMINANCE_ALPHA16F_ARB: - return &_mesa_texformat_luminance_alpha_float16; + return MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16; case GL_LUMINANCE_ALPHA32F_ARB: - return &_mesa_texformat_luminance_alpha_float32; + return MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32; case GL_INTENSITY16F_ARB: - return &_mesa_texformat_intensity_float16; + return MESA_FORMAT_INTENSITY_FLOAT16; case GL_INTENSITY32F_ARB: - return &_mesa_texformat_intensity_float32; + return MESA_FORMAT_INTENSITY_FLOAT32; case GL_RGB16F_ARB: - return &_mesa_texformat_rgba_float16; + return MESA_FORMAT_RGBA_FLOAT16; case GL_RGB32F_ARB: - return &_mesa_texformat_rgba_float32; + return MESA_FORMAT_RGBA_FLOAT32; case GL_RGBA16F_ARB: - return &_mesa_texformat_rgba_float16; + return MESA_FORMAT_RGBA_FLOAT16; case GL_RGBA32F_ARB: - return &_mesa_texformat_rgba_float32; + return MESA_FORMAT_RGBA_FLOAT32; case GL_DEPTH_COMPONENT: case GL_DEPTH_COMPONENT16: @@ -476,7 +476,7 @@ const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, case GL_DEPTH_COMPONENT32: case GL_DEPTH_STENCIL_EXT: case GL_DEPTH24_STENCIL8_EXT: - return &_mesa_texformat_s8_z24; + return MESA_FORMAT_S8_Z24; /* EXT_texture_sRGB */ case GL_SRGB: @@ -485,26 +485,26 @@ const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, case GL_SRGB8_ALPHA8: case GL_COMPRESSED_SRGB: case GL_COMPRESSED_SRGB_ALPHA: - return &_mesa_texformat_srgba8; + return MESA_FORMAT_SRGBA8; case GL_SLUMINANCE: case GL_SLUMINANCE8: case GL_COMPRESSED_SLUMINANCE: - return &_mesa_texformat_sl8; + return MESA_FORMAT_SL8; case GL_SLUMINANCE_ALPHA: case GL_SLUMINANCE8_ALPHA8: case GL_COMPRESSED_SLUMINANCE_ALPHA: - return &_mesa_texformat_sla8; + return MESA_FORMAT_SLA8; default: _mesa_problem(ctx, "unexpected internalFormat 0x%x in %s", (int)internalFormat, __func__); - return NULL; + return MESA_FORMAT_NONE; } - return NULL; /* never get here */ + return MESA_FORMAT_NONE; /* never get here */ } /** @@ -544,18 +544,18 @@ static void radeon_teximage( texImage->TexFormat = radeonChooseTextureFormat(ctx, internalFormat, format, type, 0); _mesa_set_fetch_functions(texImage, dims); - if (_mesa_is_format_compressed(texImage->TexFormat->MesaFormat)) { + if (_mesa_is_format_compressed(texImage->TexFormat)) { texelBytes = 0; texImage->IsCompressed = GL_TRUE; texImage->CompressedSize = ctx->Driver.CompressedTextureSize(ctx, texImage->Width, texImage->Height, texImage->Depth, - texImage->TexFormat->MesaFormat); + texImage->TexFormat); } else { texImage->IsCompressed = GL_FALSE; texImage->CompressedSize = 0; - texelBytes = _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); /* Minimum pitch of 32 bytes */ if (postConvWidth * texelBytes < 32) { postConvWidth = 32 / texelBytes; @@ -593,7 +593,7 @@ static void radeon_teximage( if (texImage->IsCompressed) { size = texImage->CompressedSize; } else { - size = texImage->Width * texImage->Height * texImage->Depth * _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + size = texImage->Width * texImage->Height * texImage->Depth * _mesa_get_format_bytes(texImage->TexFormat); } texImage->Data = _mesa_alloc_texmemory(size); } @@ -613,7 +613,7 @@ static void radeon_teximage( if (compressed) { if (image->mt) { uint32_t srcRowStride, bytesPerRow, rows; - srcRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width); + srcRowStride = _mesa_compressed_row_stride(texImage->TexFormat, width); bytesPerRow = srcRowStride; rows = (height + 3) / 4; copy_rows(texImage->Data, image->mt->levels[level].rowstride, @@ -629,7 +629,7 @@ static void radeon_teximage( radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; dstRowStride = lvl->rowstride; } else { - dstRowStride = texImage->Width * _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + dstRowStride = texImage->Width * _mesa_get_format_bytes(texImage->TexFormat); } if (dims == 3) { @@ -640,7 +640,7 @@ static void radeon_teximage( _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage"); for (i = 0; i < depth; ++i) { - dstImageOffsets[i] = dstRowStride/_mesa_get_format_bytes(texImage->TexFormat->MesaFormat) * height * i; + dstImageOffsets[i] = dstRowStride/_mesa_get_format_bytes(texImage->TexFormat) * height * i; } } else { dstImageOffsets = texImage->ImageOffsets; @@ -756,23 +756,23 @@ static void radeon_texsubimage(GLcontext* ctx, int dims, GLenum target, int leve radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; dstRowStride = lvl->rowstride; } else { - dstRowStride = texImage->RowStride * _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + dstRowStride = texImage->RowStride * _mesa_get_format_bytes(texImage->TexFormat); } if (compressed) { uint32_t srcRowStride, bytesPerRow, rows; GLubyte *img_start; if (!image->mt) { - dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, texImage->Width); + dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat, texImage->Width); img_start = _mesa_compressed_image_address(xoffset, yoffset, 0, - texImage->TexFormat->MesaFormat, + texImage->TexFormat, texImage->Width, texImage->Data); } else { uint32_t blocks_x = dstRowStride / (image->mt->bpp * 4); img_start = texImage->Data + image->mt->bpp * 4 * (blocks_x * (yoffset / 4) + xoffset / 4); } - srcRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width); + srcRowStride = _mesa_compressed_row_stride(texImage->TexFormat, width); bytesPerRow = srcRowStride; rows = (height + 3) / 4; @@ -895,10 +895,10 @@ static void migrate_image_to_miptree(radeon_mipmap_tree *mt, radeon_texture_imag /* need to confirm this value is correct */ if (mt->compressed) { height = (image->base.Height + 3) / 4; - srcrowstride = _mesa_compressed_row_stride(image->base.TexFormat->MesaFormat, image->base.Width); + srcrowstride = _mesa_compressed_row_stride(image->base.TexFormat, image->base.Width); } else { height = image->base.Height * image->base.Depth; - srcrowstride = image->base.Width * _mesa_get_format_bytes(image->base.TexFormat->MesaFormat); + srcrowstride = image->base.Width * _mesa_get_format_bytes(image->base.TexFormat); } // if (mt->tilebits) diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.h b/src/mesa/drivers/dri/radeon/radeon_texture.h index 888a55ba91..8995546d77 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.h +++ b/src/mesa/drivers/dri/radeon/radeon_texture.h @@ -30,6 +30,10 @@ #ifndef RADEON_TEXTURE_H #define RADEON_TEXTURE_H + +#include "main/formats.h" + + struct gl_texture_image *radeonNewTextureImage(GLcontext *ctx); void radeonFreeTexImageData(GLcontext *ctx, struct gl_texture_image *timage); @@ -40,14 +44,16 @@ void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj); void radeonGenerateMipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj); int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj); GLuint radeon_face_for_target(GLenum target); -const struct gl_texture_format *radeonChooseTextureFormat_mesa(GLcontext * ctx, - GLint internalFormat, - GLenum format, - GLenum type); -const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, - GLint internalFormat, - GLenum format, - GLenum type, GLboolean fbo); + +gl_format radeonChooseTextureFormat_mesa(GLcontext * ctx, + GLint internalFormat, + GLenum format, + GLenum type); + +gl_format radeonChooseTextureFormat(GLcontext * ctx, + GLint internalFormat, + GLenum format, + GLenum type, GLboolean fbo); void radeonTexImage1D(GLcontext * ctx, GLenum target, GLint level, GLint internalFormat, diff --git a/src/mesa/drivers/dri/savage/savagetex.c b/src/mesa/drivers/dri/savage/savagetex.c index fe239e1b05..796da4fc0d 100644 --- a/src/mesa/drivers/dri/savage/savagetex.c +++ b/src/mesa/drivers/dri/savage/savagetex.c @@ -527,6 +527,11 @@ savageAllocTexObj( struct gl_texture_object *texObj ) * components to white. This way we get the correct result. */ +#if 0 +/* Using MESA_FORMAT_RGBA8888 to store alpha-only textures should + * work but is space inefficient. + */ + static GLboolean _savage_texstore_a1114444(TEXSTORE_PARAMS); @@ -590,10 +595,11 @@ _savage_texstore_a1114444(TEXSTORE_PARAMS) return GL_FALSE; _mesa_adjust_image_for_convolution(ctx, dims, &srcWidth, &srcHeight); for (img = 0; img < srcDepth; img++) { + GLuint texelBytes = _mesa_get_format_bytes(dstFormat); GLubyte *dstRow = (GLubyte *) dstAddr - + dstImageOffsets[dstZoffset + img] * dstFormat->TexelBytes + + dstImageOffsets[dstZoffset + img] * texelBytes + dstYoffset * dstRowStride - + dstXoffset * dstFormat->TexelBytes; + + dstXoffset * texelBytes; for (row = 0; row < srcHeight; row++) { GLushort *dstUI = (GLushort *) dstRow; for (col = 0; col < srcWidth; col++) { @@ -629,10 +635,11 @@ _savage_texstore_a1118888(TEXSTORE_PARAMS) return GL_FALSE; _mesa_adjust_image_for_convolution(ctx, dims, &srcWidth, &srcHeight); for (img = 0; img < srcDepth; img++) { + GLuint texelBytes = _mesa_get_format_bytes(dstFormat); GLubyte *dstRow = (GLubyte *) dstAddr - + dstImageOffsets[dstZoffset + img] * dstFormat->TexelBytes + + dstImageOffsets[dstZoffset + img] * texelBytes + dstYoffset * dstRowStride - + dstXoffset * dstFormat->TexelBytes; + + dstXoffset * texelBytes; for (row = 0; row < srcHeight; row++) { GLuint *dstUI = (GLuint *) dstRow; for (col = 0; col < srcWidth; col++) { @@ -647,10 +654,11 @@ _savage_texstore_a1118888(TEXSTORE_PARAMS) return GL_TRUE; } +#endif /* Called by the _mesa_store_teximage[123]d() functions. */ -static const struct gl_texture_format * +static gl_format savageChooseTextureFormat( GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type ) { @@ -669,15 +677,15 @@ savageChooseTextureFormat( GLcontext *ctx, GLint internalFormat, switch ( type ) { case GL_UNSIGNED_INT_10_10_10_2: case GL_UNSIGNED_INT_2_10_10_10_REV: - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb1555; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB1555; case GL_UNSIGNED_SHORT_4_4_4_4: case GL_UNSIGNED_SHORT_4_4_4_4_REV: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_UNSIGNED_SHORT_5_5_5_1: case GL_UNSIGNED_SHORT_1_5_5_5_REV: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; default: - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; } case 3: @@ -686,129 +694,152 @@ savageChooseTextureFormat( GLcontext *ctx, GLint internalFormat, switch ( type ) { case GL_UNSIGNED_SHORT_4_4_4_4: case GL_UNSIGNED_SHORT_4_4_4_4_REV: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_UNSIGNED_SHORT_5_5_5_1: case GL_UNSIGNED_SHORT_1_5_5_5_REV: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case GL_UNSIGNED_SHORT_5_6_5: case GL_UNSIGNED_SHORT_5_6_5_REV: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; default: - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_rgb565; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_RGB565; } case GL_RGBA8: case GL_RGBA12: case GL_RGBA16: return !force16bpt ? - &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444; + MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; case GL_RGB10_A2: return !force16bpt ? - &_mesa_texformat_argb8888 : &_mesa_texformat_argb1555; + MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB1555; case GL_RGBA4: case GL_RGBA2: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_RGB5_A1: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case GL_RGB8: case GL_RGB10: case GL_RGB12: case GL_RGB16: - return !force16bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_rgb565; + return !force16bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_RGB565; case GL_RGB5: case GL_RGB4: case GL_R3_G3_B2: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; case GL_ALPHA: case GL_COMPRESSED_ALPHA: - return isSavage4 ? &_mesa_texformat_a8 : ( +#if 0 + return isSavage4 ? MESA_FORMAT_a8 : ( do32bpt ? &_savage_texformat_a1118888 : &_savage_texformat_a1114444); +#else + if (isSavage4) + return MESA_FORMAT_A8; + else if (do32bpt) + return MESA_FORMAT_ARGB8888; + else + return MESA_FORMAT_ARGB4444; +#endif case GL_ALPHA4: - return isSavage4 ? &_mesa_texformat_a8 : &_savage_texformat_a1114444; +#if 0 + return isSavage4 ? MESA_FORMAT_a8 : &_savage_texformat_a1114444; +#else + if (isSavage4) + return MESA_FORMAT_A8; + else + return MESA_FORMAT_ARGB4444; +#endif case GL_ALPHA8: case GL_ALPHA12: case GL_ALPHA16: - return isSavage4 ? &_mesa_texformat_a8 : ( +#if 0 + return isSavage4 ? MESA_FORMAT_a8 : ( !force16bpt ? &_savage_texformat_a1118888 : &_savage_texformat_a1114444); - +#else + if (isSavage4) + return MESA_FORMAT_A8; + else if (force16bpt) + return MESA_FORMAT_ARGB4444; + else + return MESA_FORMAT_ARGB8888; +#endif case 1: case GL_LUMINANCE: case GL_COMPRESSED_LUMINANCE: /* no alpha, but use argb1555 in 16bit case to get pure grey values */ - return isSavage4 ? &_mesa_texformat_l8 : ( - do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb1555); + return isSavage4 ? MESA_FORMAT_L8 : ( + do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB1555); case GL_LUMINANCE4: - return isSavage4 ? &_mesa_texformat_l8 : &_mesa_texformat_argb1555; + return isSavage4 ? MESA_FORMAT_L8 : MESA_FORMAT_ARGB1555; case GL_LUMINANCE8: case GL_LUMINANCE12: case GL_LUMINANCE16: - return isSavage4 ? &_mesa_texformat_l8 : ( - !force16bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb1555); + return isSavage4 ? MESA_FORMAT_L8 : ( + !force16bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB1555); case 2: case GL_LUMINANCE_ALPHA: case GL_COMPRESSED_LUMINANCE_ALPHA: /* Savage4 has a al44 texture format. But it's not supported by Mesa. */ - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; case GL_LUMINANCE4_ALPHA4: case GL_LUMINANCE6_ALPHA2: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_LUMINANCE8_ALPHA8: case GL_LUMINANCE12_ALPHA4: case GL_LUMINANCE12_ALPHA12: case GL_LUMINANCE16_ALPHA16: - return !force16bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444; + return !force16bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; #if 0 /* TFT_I8 produces garbage on ProSavageDDR and subsequent texture * disable keeps rendering garbage. Disabled for now. */ case GL_INTENSITY: case GL_COMPRESSED_INTENSITY: - return isSavage4 ? &_mesa_texformat_i8 : ( - do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444); + return isSavage4 ? MESA_FORMAT_i8 : ( + do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444); case GL_INTENSITY4: - return isSavage4 ? &_mesa_texformat_i8 : &_mesa_texformat_argb4444; + return isSavage4 ? MESA_FORMAT_i8 : MESA_FORMAT_ARGB4444; case GL_INTENSITY8: case GL_INTENSITY12: case GL_INTENSITY16: - return isSavage4 ? &_mesa_texformat_i8 : ( - !force16bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444); + return isSavage4 ? MESA_FORMAT_i8 : ( + !force16bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444); #else case GL_INTENSITY: case GL_COMPRESSED_INTENSITY: - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; case GL_INTENSITY4: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_INTENSITY8: case GL_INTENSITY12: case GL_INTENSITY16: - return !force16bpt ? &_mesa_texformat_argb8888 : - &_mesa_texformat_argb4444; + return !force16bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; #endif case GL_RGB_S3TC: case GL_RGB4_S3TC: case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: - return &_mesa_texformat_rgb_dxt1; + return MESA_FORMAT_RGB_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: - return &_mesa_texformat_rgba_dxt1; + return MESA_FORMAT_RGBA_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: - return &_mesa_texformat_rgba_dxt3; + return MESA_FORMAT_RGBA_DXT3; case GL_RGBA_S3TC: case GL_RGBA4_S3TC: if (!isSavage4) /* Not the best choice but Savage3D/MX/IX don't support DXT3 or DXT5. */ - return &_mesa_texformat_rgba_dxt1; + return MESA_FORMAT_RGBA_DXT1; /* fall through */ case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: - return &_mesa_texformat_rgba_dxt5; + return MESA_FORMAT_RGBA_DXT5; /* case GL_COLOR_INDEX: @@ -822,7 +853,7 @@ savageChooseTextureFormat( GLcontext *ctx, GLint internalFormat, */ default: _mesa_problem(ctx, "unexpected texture format in %s", __FUNCTION__); - return NULL; + return MESA_FORMAT_NONE; } } @@ -837,7 +868,7 @@ static void savageSetTexImages( savageContextPtr imesa, assert(t); assert(image); - switch (image->TexFormat->MesaFormat) { + switch (image->TexFormat) { case MESA_FORMAT_ARGB8888: textureFormat = TFT_ARGB8888; t->texelBytes = tileIndex = 4; @@ -2083,6 +2114,7 @@ void savageDDInitTextureFuncs( struct dd_function_table *functions ) /* Texel fetching with our custom texture formats works just like * the standard argb formats. */ +#if 0 _savage_texformat_a1114444.FetchTexel1D = _mesa_texformat_argb4444.FetchTexel1D; _savage_texformat_a1114444.FetchTexel2D = _mesa_texformat_argb4444.FetchTexel2D; _savage_texformat_a1114444.FetchTexel3D = _mesa_texformat_argb4444.FetchTexel3D; @@ -2096,4 +2128,5 @@ void savageDDInitTextureFuncs( struct dd_function_table *functions ) _savage_texformat_a1118888.FetchTexel1Df= _mesa_texformat_argb8888.FetchTexel1Df; _savage_texformat_a1118888.FetchTexel2Df= _mesa_texformat_argb8888.FetchTexel2Df; _savage_texformat_a1118888.FetchTexel3Df= _mesa_texformat_argb8888.FetchTexel3Df; +#endif } diff --git a/src/mesa/drivers/dri/sis/sis_tex.c b/src/mesa/drivers/dri/sis/sis_tex.c index 38a309d41f..5dc05146b1 100644 --- a/src/mesa/drivers/dri/sis/sis_tex.c +++ b/src/mesa/drivers/dri/sis/sis_tex.c @@ -65,7 +65,7 @@ sisAllocTexImage( sisContextPtr smesa, sisTexObjPtr t, int level, if (t->format == 0) { t->format = image->_BaseFormat; - switch (image->TexFormat->MesaFormat) + switch (image->TexFormat) { case MESA_FORMAT_ARGB8888: t->hwformat = TEXEL_ARGB_8888_32; @@ -101,13 +101,12 @@ sisAllocTexImage( sisContextPtr smesa, sisTexObjPtr t, int level, t->hwformat = TEXEL_VUY422; break; default: - sis_fatal_error("Bad texture format 0x%x.\n", - image->TexFormat->MesaFormat); + sis_fatal_error("Bad texture format 0x%x.\n", image->TexFormat); } } assert(t->format == image->_BaseFormat); - texel_size = _mesa_get_format_bytes(image->TexFormat->MesaFormat); + texel_size = _mesa_get_format_bytes(image->TexFormat); size = image->Width * image->Height * texel_size + TEXTURE_HW_PLUS; addr = sisAllocFB( smesa, size, &t->image[level].handle ); @@ -230,7 +229,7 @@ static GLboolean sisIsTextureResident( GLcontext * ctx, return (texObj->DriverData != NULL); } -static const struct gl_texture_format * +static gl_format sisChooseTextureFormat( GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type ) { @@ -248,15 +247,15 @@ sisChooseTextureFormat( GLcontext *ctx, GLint internalFormat, switch ( type ) { case GL_UNSIGNED_INT_10_10_10_2: case GL_UNSIGNED_INT_2_10_10_10_REV: - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb1555; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB1555; case GL_UNSIGNED_SHORT_4_4_4_4: case GL_UNSIGNED_SHORT_4_4_4_4_REV: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_UNSIGNED_SHORT_5_5_5_1: case GL_UNSIGNED_SHORT_1_5_5_5_REV: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; default: - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; } case 3: @@ -265,46 +264,46 @@ sisChooseTextureFormat( GLcontext *ctx, GLint internalFormat, switch ( type ) { case GL_UNSIGNED_SHORT_4_4_4_4: case GL_UNSIGNED_SHORT_4_4_4_4_REV: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_UNSIGNED_SHORT_5_5_5_1: case GL_UNSIGNED_SHORT_1_5_5_5_REV: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case GL_UNSIGNED_SHORT_5_6_5: case GL_UNSIGNED_SHORT_5_6_5_REV: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; default: - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_rgb565; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_RGB565; } case GL_RGBA8: case GL_RGBA12: case GL_RGBA16: return !force16bpt ? - &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444; + MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; case GL_RGB10_A2: return !force16bpt ? - &_mesa_texformat_argb8888 : &_mesa_texformat_argb1555; + MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB1555; case GL_RGBA4: case GL_RGBA2: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_RGB5_A1: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case GL_RGB8: case GL_RGB10: case GL_RGB12: case GL_RGB16: - return !force16bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_rgb565; + return !force16bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_RGB565; case GL_RGB5: case GL_RGB4: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; case GL_R3_G3_B2: - return &_mesa_texformat_rgb332; + return MESA_FORMAT_RGB332; case GL_ALPHA: case GL_ALPHA4: /* FIXME: This could use its own texstore */ @@ -312,7 +311,7 @@ sisChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_ALPHA12: case GL_ALPHA16: case GL_COMPRESSED_ALPHA: - return &_mesa_texformat_a8; + return MESA_FORMAT_A8; case 1: case GL_LUMINANCE: @@ -321,7 +320,7 @@ sisChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE12: case GL_LUMINANCE16: case GL_COMPRESSED_LUMINANCE: - return &_mesa_texformat_l8; + return MESA_FORMAT_L8; case 2: case GL_LUMINANCE_ALPHA: @@ -332,7 +331,7 @@ sisChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE12_ALPHA12: case GL_LUMINANCE16_ALPHA16: case GL_COMPRESSED_LUMINANCE_ALPHA: - return &_mesa_texformat_al88; + return MESA_FORMAT_AL88; case GL_INTENSITY: case GL_INTENSITY4: @@ -340,19 +339,19 @@ sisChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_INTENSITY12: case GL_INTENSITY16: case GL_COMPRESSED_INTENSITY: - return &_mesa_texformat_i8; + return MESA_FORMAT_I8; case GL_YCBCR_MESA: if (type == GL_UNSIGNED_SHORT_8_8_APPLE || type == GL_UNSIGNED_BYTE) - return &_mesa_texformat_ycbcr; + return MESA_FORMAT_YCBCR; else - return &_mesa_texformat_ycbcr_rev; + return MESA_FORMAT_YCBCR_REV; default: _mesa_problem(ctx, "unexpected format in sisDDChooseTextureFormat: %d", internalFormat); - return NULL; + return MESA_FORMAT_NONE; } } @@ -425,7 +424,7 @@ static void sisTexSubImage1D( GLcontext *ctx, /* Upload the texture */ WaitEngIdle(smesa); - texelBytes = _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); copySize = width * texelBytes; src = (char *)texImage->Data + xoffset * texelBytes; @@ -513,7 +512,7 @@ static void sisTexSubImage2D( GLcontext *ctx, /* Upload the texture */ WaitEngIdle(smesa); - texelBytes = _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); copySize = width * texelBytes; src = (char *)texImage->Data + (xoffset + yoffset * texImage->Width) * diff --git a/src/mesa/drivers/dri/tdfx/tdfx_tex.c b/src/mesa/drivers/dri/tdfx/tdfx_tex.c index 51d86aea37..427d315a01 100644 --- a/src/mesa/drivers/dri/tdfx/tdfx_tex.c +++ b/src/mesa/drivers/dri/tdfx/tdfx_tex.c @@ -72,13 +72,13 @@ _mesa_halve2x2_teximage2d ( GLcontext *ctx, GLubyte *_d = NULL; GLenum _t = 0; - if (texImage->TexFormat->MesaFormat == MESA_FORMAT_RGB565) { + if (texImage->TexFormat == MESA_FORMAT_RGB565) { _t = GL_UNSIGNED_SHORT_5_6_5_REV; bpt = bytesPerPixel; - } else if (texImage->TexFormat->MesaFormat == MESA_FORMAT_ARGB4444) { + } else if (texImage->TexFormat == MESA_FORMAT_ARGB4444) { _t = GL_UNSIGNED_SHORT_4_4_4_4_REV; bpt = bytesPerPixel; - } else if (texImage->TexFormat->MesaFormat == MESA_FORMAT_ARGB1555) { + } else if (texImage->TexFormat == MESA_FORMAT_ARGB1555) { _t = GL_UNSIGNED_SHORT_1_5_5_5_REV; bpt = bytesPerPixel; } @@ -94,7 +94,7 @@ _mesa_halve2x2_teximage2d ( GLcontext *ctx, _s = src = MALLOC(srcRowStride * srcHeight); _d = dst = MALLOC(dstWidth * bytesPerPixel * dstHeight); _mesa_texstore(ctx, 2, GL_RGBA, - &_mesa_texformat_rgba8888_rev, src, + MESA_FORMAT_RGBA8888_REV, src, 0, 0, 0, /* dstX/Y/Zoffset */ srcRowStride, /* dstRowStride */ &dstImageOffsets, @@ -190,6 +190,7 @@ tdfxGenerateMipmap(GLcontext *ctx, GLenum target, const tdfxMipMapLevel *mml; texImage = _mesa_get_tex_image(ctx, texObj, target, level); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); assert(!texImage->IsCompressed); mml = TDFX_TEXIMAGE_DATA(texImage); @@ -760,7 +761,7 @@ fxTexusError(const char *string, FxBool fatal) #endif -static const struct gl_texture_format * +static gl_format tdfxChooseTextureFormat( GLcontext *ctx, GLint internalFormat, GLenum srcFormat, GLenum srcType ) { @@ -774,7 +775,7 @@ tdfxChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_ALPHA12: case GL_ALPHA16: case GL_COMPRESSED_ALPHA: - return &_mesa_texformat_a8; + return MESA_FORMAT_A8; case 1: case GL_LUMINANCE: case GL_LUMINANCE4: @@ -782,7 +783,7 @@ tdfxChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE12: case GL_LUMINANCE16: case GL_COMPRESSED_LUMINANCE: - return &_mesa_texformat_l8; + return MESA_FORMAT_L8; case 2: case GL_LUMINANCE_ALPHA: case GL_LUMINANCE4_ALPHA4: @@ -792,48 +793,47 @@ tdfxChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE12_ALPHA12: case GL_LUMINANCE16_ALPHA16: case GL_COMPRESSED_LUMINANCE_ALPHA: - return &_mesa_texformat_al88; + return MESA_FORMAT_AL88; case GL_INTENSITY: case GL_INTENSITY4: case GL_INTENSITY8: case GL_INTENSITY12: case GL_INTENSITY16: case GL_COMPRESSED_INTENSITY: - return &_mesa_texformat_i8; + return MESA_FORMAT_I8; case GL_R3_G3_B2: case GL_RGB4: case GL_RGB5: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; case GL_COMPRESSED_RGB: /* intentional fall-through */ case 3: case GL_RGB: if ( srcFormat == GL_RGB && srcType == GL_UNSIGNED_SHORT_5_6_5 ) { - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; } /* intentional fall through */ case GL_RGB8: case GL_RGB10: case GL_RGB12: case GL_RGB16: - return (allow32bpt) ? &_mesa_texformat_argb8888 - : &_mesa_texformat_rgb565; + return (allow32bpt) ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_RGB565; case GL_RGBA2: case GL_RGBA4: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_COMPRESSED_RGBA: /* intentional fall-through */ case 4: case GL_RGBA: if ( srcFormat == GL_BGRA ) { if ( srcType == GL_UNSIGNED_INT_8_8_8_8_REV ) { - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; } else if ( srcType == GL_UNSIGNED_SHORT_4_4_4_4_REV ) { - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; } else if ( srcType == GL_UNSIGNED_SHORT_1_5_5_5_REV ) { - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; } } /* intentional fall through */ @@ -841,10 +841,9 @@ tdfxChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_RGB10_A2: case GL_RGBA12: case GL_RGBA16: - return allow32bpt ? &_mesa_texformat_argb8888 - : &_mesa_texformat_argb4444; + return allow32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; case GL_RGB5_A1: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case GL_COLOR_INDEX: case GL_COLOR_INDEX1_EXT: case GL_COLOR_INDEX2_EXT: @@ -852,29 +851,29 @@ tdfxChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_COLOR_INDEX8_EXT: case GL_COLOR_INDEX12_EXT: case GL_COLOR_INDEX16_EXT: - return &_mesa_texformat_ci8; + return MESA_FORMAT_CI8; /* GL_EXT_texture_compression_s3tc */ /* GL_S3_s3tc */ case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: case GL_RGB_S3TC: case GL_RGB4_S3TC: - return &_mesa_texformat_rgb_dxt1; + return MESA_FORMAT_RGB_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: - return &_mesa_texformat_rgba_dxt1; + return MESA_FORMAT_RGBA_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: case GL_RGBA_S3TC: case GL_RGBA4_S3TC: - return &_mesa_texformat_rgba_dxt3; + return MESA_FORMAT_RGBA_DXT3; case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: - return &_mesa_texformat_rgba_dxt5; + return MESA_FORMAT_RGBA_DXT5; /* GL_3DFX_texture_compression_FXT1 */ case GL_COMPRESSED_RGB_FXT1_3DFX: - return &_mesa_texformat_rgb_fxt1; + return MESA_FORMAT_RGB_FXT1; case GL_COMPRESSED_RGBA_FXT1_3DFX: - return &_mesa_texformat_rgba_fxt1; + return MESA_FORMAT_RGBA_FXT1; default: _mesa_problem(ctx, "unexpected format in tdfxChooseTextureFormat"); - return NULL; + return MESA_FORMAT_NONE; } } @@ -1126,7 +1125,9 @@ fetch_rgb_dxt1(const struct gl_texture_image *texImage, i = i * mml->wScale; j = j * mml->hScale; + /* XXX Get fetch func from _mesa_get_texel_fetch_func() _mesa_texformat_rgb_dxt1.FetchTexel2D(texImage, i, j, k, rgba); + */ } @@ -1139,7 +1140,9 @@ fetch_rgba_dxt1(const struct gl_texture_image *texImage, i = i * mml->wScale; j = j * mml->hScale; + /* XXX Get fetch func from _mesa_get_texel_fetch_func() _mesa_texformat_rgba_dxt1.FetchTexel2D(texImage, i, j, k, rgba); + */ } @@ -1152,7 +1155,9 @@ fetch_rgba_dxt3(const struct gl_texture_image *texImage, i = i * mml->wScale; j = j * mml->hScale; + /* XXX Get fetch func from _mesa_get_texel_fetch_func() _mesa_texformat_rgba_dxt3.FetchTexel2D(texImage, i, j, k, rgba); + */ } @@ -1165,7 +1170,9 @@ fetch_rgba_dxt5(const struct gl_texture_image *texImage, i = i * mml->wScale; j = j * mml->hScale; + /* XXX Get fetch func from _mesa_get_texel_fetch_func() _mesa_texformat_rgba_dxt5.FetchTexel2D(texImage, i, j, k, rgba); + */ } @@ -1268,7 +1275,7 @@ adjust2DRatio (GLcontext *ctx, } /* unpack image, apply transfer ops and store in rawImage */ _mesa_texstore(ctx, 2, GL_RGBA, - &_mesa_texformat_rgba8888_rev, rawImage, + MESA_FORMAT_RGBA8888_REV, rawImage, 0, 0, 0, /* dstX/Y/Zoffset */ width * rawBytes, /* dstRowStride */ &dstImageOffsets, @@ -1396,11 +1403,11 @@ tdfxTexImage2D(GLcontext *ctx, GLenum target, GLint level, texImage->TexFormat = (*ctx->Driver.ChooseTextureFormat)(ctx, internalFormat, format, type); assert(texImage->TexFormat); - mesaFormat = texImage->TexFormat->MesaFormat; + mesaFormat = texImage->TexFormat; mml->glideFormat = fxGlideFormat(mesaFormat); ti->info.format = mml->glideFormat; texImage->FetchTexelc = fxFetchFunction(mesaFormat); - texelBytes = _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); if (texImage->IsCompressed) { texImage->CompressedSize = _mesa_compressed_texture_size(ctx, @@ -1408,7 +1415,7 @@ tdfxTexImage2D(GLcontext *ctx, GLenum target, GLint level, mml->height, 1, mesaFormat); - dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, mml->width); + dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat, mml->width); texImage->Data = _mesa_alloc_texmemory(texImage->CompressedSize); } else { dstRowStride = mml->width * texelBytes; @@ -1484,9 +1491,9 @@ tdfxTexSubImage2D(GLcontext *ctx, GLenum target, GLint level, assert(texImage->Data); /* must have an existing texture image! */ assert(texImage->_BaseFormat); - texelBytes = _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); if (texImage->IsCompressed) { - dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, mml->width); + dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat, mml->width); } else { dstRowStride = mml->width * texelBytes; } @@ -1626,7 +1633,7 @@ tdfxCompressedTexImage2D (GLcontext *ctx, GLenum target, /* Determine the appropriate Glide texel format, * given the user's internal texture format hint. */ - mesaFormat = texImage->TexFormat->MesaFormat; + mesaFormat = texImage->TexFormat; mml->glideFormat = fxGlideFormat(mesaFormat); ti->info.format = mml->glideFormat; texImage->FetchTexelc = fxFetchFunction(mesaFormat); @@ -1661,7 +1668,7 @@ tdfxCompressedTexImage2D (GLcontext *ctx, GLenum target, * we replicate the data over the padded area. * For now, we take 2) + 3) but texelfetchers will be wrong! */ - const GLuint mesaFormat = texImage->TexFormat->MesaFormat; + const GLuint mesaFormat = texImage->TexFormat; GLuint srcRowStride = _mesa_compressed_row_stride(mesaFormat, width); GLuint destRowStride = _mesa_compressed_row_stride(mesaFormat, @@ -1698,7 +1705,7 @@ tdfxCompressedTexSubImage2D( GLcontext *ctx, GLenum target, GLint destRowStride, srcRowStride; GLint i, rows; GLubyte *dest; - const GLuint mesaFormat = texImage->TexFormat->MesaFormat; + const GLuint mesaFormat = texImage->TexFormat; if (TDFX_DEBUG & DEBUG_VERBOSE_DRI) { fprintf(stderr, "tdfxCompressedTexSubImage2D: id=%d\n", texObj->Name); diff --git a/src/mesa/drivers/dri/unichrome/via_tex.c b/src/mesa/drivers/dri/unichrome/via_tex.c index f700994025..b6be06d1ee 100644 --- a/src/mesa/drivers/dri/unichrome/via_tex.c +++ b/src/mesa/drivers/dri/unichrome/via_tex.c @@ -49,7 +49,7 @@ #include "via_ioctl.h" #include "via_3d_reg.h" -static const struct gl_texture_format * +static gl_format viaChooseTexFormat( GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type ) { @@ -66,56 +66,56 @@ viaChooseTexFormat( GLcontext *ctx, GLint internalFormat, if ( format == GL_BGRA ) { if ( type == GL_UNSIGNED_INT_8_8_8_8_REV || type == GL_UNSIGNED_BYTE ) { - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; } else if ( type == GL_UNSIGNED_SHORT_4_4_4_4_REV ) { - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; } else if ( type == GL_UNSIGNED_SHORT_1_5_5_5_REV ) { - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; } } else if ( type == GL_UNSIGNED_BYTE || type == GL_UNSIGNED_INT_8_8_8_8_REV || type == GL_UNSIGNED_INT_8_8_8_8 ) { - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; } - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; case 3: case GL_RGB: case GL_COMPRESSED_RGB: if ( format == GL_RGB && type == GL_UNSIGNED_SHORT_5_6_5 ) { - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; } else if ( type == GL_UNSIGNED_BYTE ) { - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; } - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_rgb565; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_RGB565; case GL_RGBA8: case GL_RGB10_A2: case GL_RGBA12: case GL_RGBA16: - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; case GL_RGBA4: case GL_RGBA2: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_RGB5_A1: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case GL_RGB8: case GL_RGB10: case GL_RGB12: case GL_RGB16: - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; case GL_RGB5: case GL_RGB4: case GL_R3_G3_B2: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; case GL_ALPHA: case GL_ALPHA4: @@ -123,7 +123,7 @@ viaChooseTexFormat( GLcontext *ctx, GLint internalFormat, case GL_ALPHA12: case GL_ALPHA16: case GL_COMPRESSED_ALPHA: - return &_mesa_texformat_a8; + return MESA_FORMAT_A8; case 1: case GL_LUMINANCE: @@ -132,7 +132,7 @@ viaChooseTexFormat( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE12: case GL_LUMINANCE16: case GL_COMPRESSED_LUMINANCE: - return &_mesa_texformat_l8; + return MESA_FORMAT_L8; case 2: case GL_LUMINANCE_ALPHA: @@ -143,7 +143,7 @@ viaChooseTexFormat( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE12_ALPHA12: case GL_LUMINANCE16_ALPHA16: case GL_COMPRESSED_LUMINANCE_ALPHA: - return &_mesa_texformat_al88; + return MESA_FORMAT_AL88; case GL_INTENSITY: case GL_INTENSITY4: @@ -151,35 +151,35 @@ viaChooseTexFormat( GLcontext *ctx, GLint internalFormat, case GL_INTENSITY12: case GL_INTENSITY16: case GL_COMPRESSED_INTENSITY: - return &_mesa_texformat_i8; + return MESA_FORMAT_I8; case GL_YCBCR_MESA: if (type == GL_UNSIGNED_SHORT_8_8_MESA || type == GL_UNSIGNED_BYTE) - return &_mesa_texformat_ycbcr; + return MESA_FORMAT_YCBCR; else - return &_mesa_texformat_ycbcr_rev; + return MESA_FORMAT_YCBCR_REV; case GL_COMPRESSED_RGB_FXT1_3DFX: - return &_mesa_texformat_rgb_fxt1; + return MESA_FORMAT_RGB_FXT1; case GL_COMPRESSED_RGBA_FXT1_3DFX: - return &_mesa_texformat_rgba_fxt1; + return MESA_FORMAT_RGBA_FXT1; case GL_RGB_S3TC: case GL_RGB4_S3TC: case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: - return &_mesa_texformat_rgb_dxt1; + return MESA_FORMAT_RGB_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: - return &_mesa_texformat_rgba_dxt1; + return MESA_FORMAT_RGBA_DXT1; case GL_RGBA_S3TC: case GL_RGBA4_S3TC: case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: - return &_mesa_texformat_rgba_dxt3; + return MESA_FORMAT_RGBA_DXT3; case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: - return &_mesa_texformat_rgba_dxt5; + return MESA_FORMAT_RGBA_DXT5; case GL_COLOR_INDEX: case GL_COLOR_INDEX1_EXT: @@ -188,16 +188,16 @@ viaChooseTexFormat( GLcontext *ctx, GLint internalFormat, case GL_COLOR_INDEX8_EXT: case GL_COLOR_INDEX12_EXT: case GL_COLOR_INDEX16_EXT: - return &_mesa_texformat_ci8; + return MESA_FORMAT_CI8; default: fprintf(stderr, "unexpected texture format %s in %s\n", _mesa_lookup_enum_by_nr(internalFormat), __FUNCTION__); - return NULL; + return MESA_FORMAT_NONE; } - return NULL; /* never get here */ + return MESA_FORMAT_NONE; /* never get here */ } static int logbase2(int n) @@ -458,7 +458,7 @@ static GLboolean viaSetTexImages(GLcontext *ctx, GLuint widthExp = 0; GLuint heightExp = 0; - switch (baseImage->image.TexFormat->MesaFormat) { + switch (baseImage->image.TexFormat) { case MESA_FORMAT_ARGB8888: texFormat = HC_HTXnFM_ARGB8888; break; @@ -692,7 +692,7 @@ static void viaTexImage(GLcontext *ctx, _mesa_set_fetch_functions(texImage, dims); - texelBytes = _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); if (texelBytes == 0) { /* compressed format */ @@ -700,7 +700,7 @@ static void viaTexImage(GLcontext *ctx, texImage->CompressedSize = ctx->Driver.CompressedTextureSize(ctx, texImage->Width, texImage->Height, texImage->Depth, - texImage->TexFormat->MesaFormat); + texImage->TexFormat); } /* Minimum pitch of 32 bytes */ @@ -794,10 +794,10 @@ static void viaTexImage(GLcontext *ctx, GLboolean success; if (texImage->IsCompressed) { - dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width); + dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat, width); } else { - dstRowStride = postConvWidth * _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + dstRowStride = postConvWidth * _mesa_get_format_bytes(texImage->TexFormat); } success = _mesa_texstore(ctx, dims, texImage->_BaseFormat, diff --git a/src/mesa/drivers/glide/fxddtex.c b/src/mesa/drivers/glide/fxddtex.c index 354015af1d..a64b6a5553 100644 --- a/src/mesa/drivers/glide/fxddtex.c +++ b/src/mesa/drivers/glide/fxddtex.c @@ -1016,7 +1016,7 @@ PrintTexture(int w, int h, int c, const GLubyte * data) #endif -const struct gl_texture_format * +gl_format fxDDChooseTextureFormat( GLcontext *ctx, GLint internalFormat, GLenum srcFormat, GLenum srcType ) { @@ -1033,31 +1033,31 @@ fxDDChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case 3: case GL_RGB: if ( srcFormat == GL_RGB && srcType == GL_UNSIGNED_SHORT_5_6_5 ) { - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; } /* intentional fall through */ case GL_RGB8: case GL_RGB10: case GL_RGB12: case GL_RGB16: - return (allow32bpt) ? &_mesa_texformat_argb8888 - : &_mesa_texformat_rgb565; + return (allow32bpt) ? MESA_FORMAT_ARGB8888 + : MESA_FORMAT_RGB565; case GL_RGBA2: case GL_RGBA4: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_COMPRESSED_RGBA: /* intentional fall through */ case 4: case GL_RGBA: if ( srcFormat == GL_BGRA ) { if ( srcType == GL_UNSIGNED_INT_8_8_8_8_REV ) { - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; } else if ( srcType == GL_UNSIGNED_SHORT_4_4_4_4_REV ) { - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; } else if ( srcType == GL_UNSIGNED_SHORT_1_5_5_5_REV ) { - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; } } /* intentional fall through */ @@ -1065,15 +1065,15 @@ fxDDChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_RGB10_A2: case GL_RGBA12: case GL_RGBA16: - return (allow32bpt) ? &_mesa_texformat_argb8888 - : &_mesa_texformat_argb4444; + return (allow32bpt) ? MESA_FORMAT_ARGB8888 + : MESA_FORMAT_ARGB4444; case GL_INTENSITY: case GL_INTENSITY4: case GL_INTENSITY8: case GL_INTENSITY12: case GL_INTENSITY16: case GL_COMPRESSED_INTENSITY: - return &_mesa_texformat_i8; + return MESA_FORMAT_I8; case 1: case GL_LUMINANCE: case GL_LUMINANCE4: @@ -1081,14 +1081,14 @@ fxDDChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE12: case GL_LUMINANCE16: case GL_COMPRESSED_LUMINANCE: - return &_mesa_texformat_l8; + return MESA_FORMAT_L8; case GL_ALPHA: case GL_ALPHA4: case GL_ALPHA8: case GL_ALPHA12: case GL_ALPHA16: case GL_COMPRESSED_ALPHA: - return &_mesa_texformat_a8; + return MESA_FORMAT_A8; case GL_COLOR_INDEX: case GL_COLOR_INDEX1_EXT: case GL_COLOR_INDEX2_EXT: @@ -1096,7 +1096,7 @@ fxDDChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_COLOR_INDEX8_EXT: case GL_COLOR_INDEX12_EXT: case GL_COLOR_INDEX16_EXT: - return &_mesa_texformat_ci8; + return MESA_FORMAT_CI8; case 2: case GL_LUMINANCE_ALPHA: case GL_LUMINANCE4_ALPHA4: @@ -1106,35 +1106,35 @@ fxDDChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE12_ALPHA12: case GL_LUMINANCE16_ALPHA16: case GL_COMPRESSED_LUMINANCE_ALPHA: - return &_mesa_texformat_al88; + return MESA_FORMAT_AL88; case GL_R3_G3_B2: case GL_RGB4: case GL_RGB5: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; case GL_RGB5_A1: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; /* GL_EXT_texture_compression_s3tc */ /* GL_S3_s3tc */ case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: case GL_RGB_S3TC: case GL_RGB4_S3TC: - return &_mesa_texformat_rgb_dxt1; + return MESA_FORMAT_RGB_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: - return &_mesa_texformat_rgba_dxt1; + return MESA_FORMAT_RGBA_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: case GL_RGBA_S3TC: case GL_RGBA4_S3TC: - return &_mesa_texformat_rgba_dxt3; + return MESA_FORMAT_RGBA_DXT3; case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: - return &_mesa_texformat_rgba_dxt5; + return MESA_FORMAT_RGBA_DXT5; /* GL_3DFX_texture_compression_FXT1 */ case GL_COMPRESSED_RGB_FXT1_3DFX: - return &_mesa_texformat_rgb_fxt1; + return MESA_FORMAT_RGB_FXT1; case GL_COMPRESSED_RGBA_FXT1_3DFX: - return &_mesa_texformat_rgba_fxt1; + return MESA_FORMAT_RGBA_FXT1; default: _mesa_problem(NULL, "unexpected format in fxDDChooseTextureFormat"); - return NULL; + return MESA_FORMAT_NONE; } } diff --git a/src/mesa/drivers/x11/xm_dd.c b/src/mesa/drivers/x11/xm_dd.c index e2d4aa9b2d..5b00b5b82c 100644 --- a/src/mesa/drivers/x11/xm_dd.c +++ b/src/mesa/drivers/x11/xm_dd.c @@ -1019,15 +1019,15 @@ test_proxy_teximage(GLcontext *ctx, GLenum target, GLint level, /** * In SW, we don't really compress GL_COMPRESSED_RGB[A] textures! */ -static const struct gl_texture_format * +static gl_format choose_tex_format( GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type ) { switch (internalFormat) { case GL_COMPRESSED_RGB_ARB: - return &_mesa_texformat_rgb; + return MESA_FORMAT_RGB; case GL_COMPRESSED_RGBA_ARB: - return &_mesa_texformat_rgba; + return MESA_FORMAT_RGBA; default: return _mesa_choose_tex_format(ctx, internalFormat, format, type); } diff --git a/src/mesa/main/dd.h b/src/mesa/main/dd.h index ce5e158626..9131f20f52 100644 --- a/src/mesa/main/dd.h +++ b/src/mesa/main/dd.h @@ -184,8 +184,8 @@ struct dd_function_table { * functions. The driver should examine \p internalFormat and return a * pointer to an appropriate gl_texture_format. */ - const struct gl_texture_format *(*ChooseTextureFormat)( GLcontext *ctx, - GLint internalFormat, GLenum srcFormat, GLenum srcType ); + GLuint (*ChooseTextureFormat)( GLcontext *ctx, GLint internalFormat, + GLenum srcFormat, GLenum srcType ); /** * Called by glTexImage1D(). diff --git a/src/mesa/main/debug.c b/src/mesa/main/debug.c index 8492c8561d..391180a7c6 100644 --- a/src/mesa/main/debug.c +++ b/src/mesa/main/debug.c @@ -315,7 +315,7 @@ dump_texture_cb(GLuint id, void *data, void *userData) if (texImg) { _mesa_printf(" Image %u: %d x %d x %d, format %u at %p\n", i, texImg->Width, texImg->Height, texImg->Depth, - texImg->TexFormat->MesaFormat, texImg->Data); + texImg->TexFormat, texImg->Data); if (DumpImages && !written) { GLuint face = 0; write_texture_image(texObj, face, i); diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c index 04419da6e5..6610725de8 100644 --- a/src/mesa/main/fbobject.c +++ b/src/mesa/main/fbobject.c @@ -384,7 +384,7 @@ test_attachment_completeness(const GLcontext *ctx, GLenum format, return; } - baseFormat = _mesa_get_format_base_format(texImage->TexFormat->MesaFormat); + baseFormat = _mesa_get_format_base_format(texImage->TexFormat); if (format == GL_COLOR) { if (baseFormat != GL_RGB && @@ -393,7 +393,7 @@ test_attachment_completeness(const GLcontext *ctx, GLenum format, att->Complete = GL_FALSE; return; } - if (_mesa_is_format_compressed(texImage->TexFormat->MesaFormat)) { + if (_mesa_is_format_compressed(texImage->TexFormat)) { att_incomplete("compressed internalformat"); att->Complete = GL_FALSE; return; diff --git a/src/mesa/main/mipmap.c b/src/mesa/main/mipmap.c index c02c705228..7e99a5d3de 100644 --- a/src/mesa/main/mipmap.c +++ b/src/mesa/main/mipmap.c @@ -1561,7 +1561,7 @@ _mesa_generate_mipmap(GLcontext *ctx, GLenum target, } else { /* uncompressed */ - convertFormat = srcImage->TexFormat->MesaFormat; + convertFormat = srcImage->TexFormat; } _mesa_format_to_type_and_comps(convertFormat, &datatype, &comps); @@ -1620,7 +1620,7 @@ _mesa_generate_mipmap(GLcontext *ctx, GLenum target, = ctx->Driver.CompressedTextureSize(ctx, dstImage->Width, dstImage->Height, dstImage->Depth, - dstImage->TexFormat->MesaFormat); + dstImage->TexFormat); ASSERT(dstImage->CompressedSize > 0); } @@ -1642,7 +1642,7 @@ _mesa_generate_mipmap(GLcontext *ctx, GLenum target, ASSERT(dstData); } else { - bytesPerTexel = _mesa_get_format_bytes(dstImage->TexFormat->MesaFormat); + bytesPerTexel = _mesa_get_format_bytes(dstImage->TexFormat); ASSERT(dstWidth * dstHeight * dstDepth * bytesPerTexel > 0); dstImage->Data = _mesa_alloc_texmemory(dstWidth * dstHeight * dstDepth * bytesPerTexel); @@ -1666,7 +1666,7 @@ _mesa_generate_mipmap(GLcontext *ctx, GLenum target, /* compress image from dstData into dstImage->Data */ const GLenum srcFormat = _mesa_get_format_base_format(convertFormat); GLint dstRowStride - = _mesa_compressed_row_stride(dstImage->TexFormat->MesaFormat, dstWidth); + = _mesa_compressed_row_stride(dstImage->TexFormat, dstWidth); ASSERT(srcFormat == GL_RGB || srcFormat == GL_RGBA); _mesa_texstore(ctx, 2, dstImage->_BaseFormat, diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index d448e3e158..56d5e9fafd 100644 --- a/src/mesa/main/mtypes.h +++ b/src/mesa/main/mtypes.h @@ -1200,7 +1200,7 @@ struct gl_texture_image GLboolean IsClientData; /**< Data owned by client? */ GLboolean _IsPowerOfTwo; /**< Are all dimensions powers of two? */ - const struct gl_texture_format *TexFormat; + GLuint TexFormat; /**< XXX Really gl_format */ struct gl_texture_object *TexObject; /**< Pointer back to parent object */ diff --git a/src/mesa/main/texcompress_fxt1.c b/src/mesa/main/texcompress_fxt1.c index c401f82be0..54e24fd297 100644 --- a/src/mesa/main/texcompress_fxt1.c +++ b/src/mesa/main/texcompress_fxt1.c @@ -74,7 +74,7 @@ _mesa_texstore_rgb_fxt1(TEXSTORE_PARAMS) const GLint texWidth = dstRowStride * 8 / 16; /* a bit of a hack */ const GLchan *tempImage = NULL; - ASSERT(dstFormat == &_mesa_texformat_rgb_fxt1); + ASSERT(dstFormat == MESA_FORMAT_RGB_FXT1); ASSERT(dstXoffset % 8 == 0); ASSERT(dstYoffset % 4 == 0); ASSERT(dstZoffset == 0); @@ -88,7 +88,7 @@ _mesa_texstore_rgb_fxt1(TEXSTORE_PARAMS) /* convert image to RGB/GLchan */ tempImage = _mesa_make_temp_chan_image(ctx, dims, baseInternalFormat, - dstFormat->BaseFormat, + _mesa_get_format_base_format(dstFormat), srcWidth, srcHeight, srcDepth, srcFormat, srcType, srcAddr, srcPacking); @@ -106,7 +106,7 @@ _mesa_texstore_rgb_fxt1(TEXSTORE_PARAMS) } dst = _mesa_compressed_image_address(dstXoffset, dstYoffset, 0, - dstFormat->MesaFormat, + dstFormat, texWidth, (GLubyte *) dstAddr); fxt1_encode(srcWidth, srcHeight, 3, pixels, srcRowStride, @@ -131,7 +131,7 @@ _mesa_texstore_rgba_fxt1(TEXSTORE_PARAMS) GLint texWidth = dstRowStride * 8 / 16; /* a bit of a hack */ const GLchan *tempImage = NULL; - ASSERT(dstFormat == &_mesa_texformat_rgba_fxt1); + ASSERT(dstFormat == MESA_FORMAT_RGBA_FXT1); ASSERT(dstXoffset % 8 == 0); ASSERT(dstYoffset % 4 == 0); ASSERT(dstZoffset == 0); @@ -145,7 +145,7 @@ _mesa_texstore_rgba_fxt1(TEXSTORE_PARAMS) /* convert image to RGBA/GLchan */ tempImage = _mesa_make_temp_chan_image(ctx, dims, baseInternalFormat, - dstFormat->BaseFormat, + _mesa_get_format_base_format(dstFormat), srcWidth, srcHeight, srcDepth, srcFormat, srcType, srcAddr, srcPacking); @@ -163,7 +163,7 @@ _mesa_texstore_rgba_fxt1(TEXSTORE_PARAMS) } dst = _mesa_compressed_image_address(dstXoffset, dstYoffset, 0, - dstFormat->MesaFormat, + dstFormat, texWidth, (GLubyte *) dstAddr); fxt1_encode(srcWidth, srcHeight, 4, pixels, srcRowStride, diff --git a/src/mesa/main/texcompress_s3tc.c b/src/mesa/main/texcompress_s3tc.c index 2294fdca73..69e43af0fd 100644 --- a/src/mesa/main/texcompress_s3tc.c +++ b/src/mesa/main/texcompress_s3tc.c @@ -165,7 +165,7 @@ _mesa_texstore_rgb_dxt1(TEXSTORE_PARAMS) const GLint texWidth = dstRowStride * 4 / 8; /* a bit of a hack */ const GLchan *tempImage = NULL; - ASSERT(dstFormat == &_mesa_texformat_rgb_dxt1); + ASSERT(dstFormat == MESA_FORMAT_RGB_DXT1); ASSERT(dstXoffset % 4 == 0); ASSERT(dstYoffset % 4 == 0); ASSERT(dstZoffset % 4 == 0); @@ -179,7 +179,7 @@ _mesa_texstore_rgb_dxt1(TEXSTORE_PARAMS) /* convert image to RGB/GLchan */ tempImage = _mesa_make_temp_chan_image(ctx, dims, baseInternalFormat, - dstFormat->BaseFormat, + _mesa_get_format_base_format(dstFormat), srcWidth, srcHeight, srcDepth, srcFormat, srcType, srcAddr, srcPacking); @@ -197,7 +197,7 @@ _mesa_texstore_rgb_dxt1(TEXSTORE_PARAMS) } dst = _mesa_compressed_image_address(dstXoffset, dstYoffset, 0, - dstFormat->MesaFormat, + dstFormat, texWidth, (GLubyte *) dstAddr); if (ext_tx_compress_dxtn) { @@ -228,7 +228,7 @@ _mesa_texstore_rgba_dxt1(TEXSTORE_PARAMS) const GLint texWidth = dstRowStride * 4 / 8; /* a bit of a hack */ const GLchan *tempImage = NULL; - ASSERT(dstFormat == &_mesa_texformat_rgba_dxt1); + ASSERT(dstFormat == MESA_FORMAT_RGBA_DXT1); ASSERT(dstXoffset % 4 == 0); ASSERT(dstYoffset % 4 == 0); ASSERT(dstZoffset % 4 == 0); @@ -242,7 +242,7 @@ _mesa_texstore_rgba_dxt1(TEXSTORE_PARAMS) /* convert image to RGBA/GLchan */ tempImage = _mesa_make_temp_chan_image(ctx, dims, baseInternalFormat, - dstFormat->BaseFormat, + _mesa_get_format_base_format(dstFormat), srcWidth, srcHeight, srcDepth, srcFormat, srcType, srcAddr, srcPacking); @@ -260,7 +260,7 @@ _mesa_texstore_rgba_dxt1(TEXSTORE_PARAMS) } dst = _mesa_compressed_image_address(dstXoffset, dstYoffset, 0, - dstFormat->MesaFormat, + dstFormat, texWidth, (GLubyte *) dstAddr); if (ext_tx_compress_dxtn) { (*ext_tx_compress_dxtn)(4, srcWidth, srcHeight, pixels, @@ -290,7 +290,7 @@ _mesa_texstore_rgba_dxt3(TEXSTORE_PARAMS) const GLint texWidth = dstRowStride * 4 / 16; /* a bit of a hack */ const GLchan *tempImage = NULL; - ASSERT(dstFormat == &_mesa_texformat_rgba_dxt3); + ASSERT(dstFormat == MESA_FORMAT_RGBA_DXT3); ASSERT(dstXoffset % 4 == 0); ASSERT(dstYoffset % 4 == 0); ASSERT(dstZoffset % 4 == 0); @@ -304,7 +304,7 @@ _mesa_texstore_rgba_dxt3(TEXSTORE_PARAMS) /* convert image to RGBA/GLchan */ tempImage = _mesa_make_temp_chan_image(ctx, dims, baseInternalFormat, - dstFormat->BaseFormat, + _mesa_get_format_base_format(dstFormat), srcWidth, srcHeight, srcDepth, srcFormat, srcType, srcAddr, srcPacking); @@ -321,7 +321,7 @@ _mesa_texstore_rgba_dxt3(TEXSTORE_PARAMS) } dst = _mesa_compressed_image_address(dstXoffset, dstYoffset, 0, - dstFormat->MesaFormat, + dstFormat, texWidth, (GLubyte *) dstAddr); if (ext_tx_compress_dxtn) { (*ext_tx_compress_dxtn)(4, srcWidth, srcHeight, pixels, @@ -351,7 +351,7 @@ _mesa_texstore_rgba_dxt5(TEXSTORE_PARAMS) const GLint texWidth = dstRowStride * 4 / 16; /* a bit of a hack */ const GLchan *tempImage = NULL; - ASSERT(dstFormat == &_mesa_texformat_rgba_dxt5); + ASSERT(dstFormat == MESA_FORMAT_RGBA_DXT5); ASSERT(dstXoffset % 4 == 0); ASSERT(dstYoffset % 4 == 0); ASSERT(dstZoffset % 4 == 0); @@ -365,7 +365,7 @@ _mesa_texstore_rgba_dxt5(TEXSTORE_PARAMS) /* convert image to RGBA/GLchan */ tempImage = _mesa_make_temp_chan_image(ctx, dims, baseInternalFormat, - dstFormat->BaseFormat, + _mesa_get_format_base_format(dstFormat), srcWidth, srcHeight, srcDepth, srcFormat, srcType, srcAddr, srcPacking); @@ -382,7 +382,7 @@ _mesa_texstore_rgba_dxt5(TEXSTORE_PARAMS) } dst = _mesa_compressed_image_address(dstXoffset, dstYoffset, 0, - dstFormat->MesaFormat, + dstFormat, texWidth, (GLubyte *) dstAddr); if (ext_tx_compress_dxtn) { (*ext_tx_compress_dxtn)(4, srcWidth, srcHeight, pixels, diff --git a/src/mesa/main/texformat.c b/src/mesa/main/texformat.c index 60b2065a6c..019193f134 100644 --- a/src/mesa/main/texformat.c +++ b/src/mesa/main/texformat.c @@ -130,7 +130,7 @@ static void store_null_texel(struct gl_texture_image *texImage, /***************************************************************/ /** \name Default GLchan-based formats */ /*@{*/ - +#if 0 const struct gl_texture_format _mesa_texformat_rgba = { MESA_FORMAT_RGBA, /* MesaFormat */ GL_RGBA, /* BaseFormat */ @@ -1016,6 +1016,7 @@ const struct gl_texture_format _mesa_null_texformat = { 0, /* StencilBits */ 0, /* TexelBytes */ }; +#endif /*@}*/ @@ -1035,7 +1036,7 @@ const struct gl_texture_format _mesa_null_texformat = { * This is called via dd_function_table::ChooseTextureFormat. Hardware drivers * will typically override this function with a specialized version. */ -const struct gl_texture_format * +gl_format _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type ) { @@ -1049,15 +1050,15 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, case GL_RGB10_A2: case GL_RGBA12: case GL_RGBA16: - return &_mesa_texformat_rgba; + return MESA_FORMAT_RGBA; case GL_RGBA8: - return &_mesa_texformat_rgba8888; + return MESA_FORMAT_RGBA8888; case GL_RGB5_A1: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case GL_RGBA2: - return &_mesa_texformat_argb4444_rev; /* just to test another format*/ + return MESA_FORMAT_ARGB4444_REV; /* just to test another format*/ case GL_RGBA4: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; /* RGB formats */ case 3: @@ -1065,24 +1066,24 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, case GL_RGB10: case GL_RGB12: case GL_RGB16: - return &_mesa_texformat_rgb; + return MESA_FORMAT_RGB; case GL_RGB8: - return &_mesa_texformat_rgb888; + return MESA_FORMAT_RGB888; case GL_R3_G3_B2: - return &_mesa_texformat_rgb332; + return MESA_FORMAT_RGB332; case GL_RGB4: - return &_mesa_texformat_rgb565_rev; /* just to test another format */ + return MESA_FORMAT_RGB565_REV; /* just to test another format */ case GL_RGB5: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; /* Alpha formats */ case GL_ALPHA: case GL_ALPHA4: case GL_ALPHA12: case GL_ALPHA16: - return &_mesa_texformat_alpha; + return MESA_FORMAT_ALPHA; case GL_ALPHA8: - return &_mesa_texformat_a8; + return MESA_FORMAT_A8; /* Luminance formats */ case 1: @@ -1090,9 +1091,9 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE4: case GL_LUMINANCE12: case GL_LUMINANCE16: - return &_mesa_texformat_luminance; + return MESA_FORMAT_LUMINANCE; case GL_LUMINANCE8: - return &_mesa_texformat_l8; + return MESA_FORMAT_L8; /* Luminance/Alpha formats */ case 2: @@ -1102,17 +1103,17 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE12_ALPHA4: case GL_LUMINANCE12_ALPHA12: case GL_LUMINANCE16_ALPHA16: - return &_mesa_texformat_luminance_alpha; + return MESA_FORMAT_LUMINANCE_ALPHA; case GL_LUMINANCE8_ALPHA8: - return &_mesa_texformat_al88; + return MESA_FORMAT_AL88; case GL_INTENSITY: case GL_INTENSITY4: case GL_INTENSITY12: case GL_INTENSITY16: - return &_mesa_texformat_intensity; + return MESA_FORMAT_INTENSITY; case GL_INTENSITY8: - return &_mesa_texformat_i8; + return MESA_FORMAT_I8; case GL_COLOR_INDEX: case GL_COLOR_INDEX1_EXT: @@ -1121,7 +1122,7 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, case GL_COLOR_INDEX12_EXT: case GL_COLOR_INDEX16_EXT: case GL_COLOR_INDEX8_EXT: - return &_mesa_texformat_ci8; + return MESA_FORMAT_CI8; default: ; /* fallthrough */ @@ -1132,9 +1133,9 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, case GL_DEPTH_COMPONENT: case GL_DEPTH_COMPONENT24: case GL_DEPTH_COMPONENT32: - return &_mesa_texformat_z32; + return MESA_FORMAT_Z32; case GL_DEPTH_COMPONENT16: - return &_mesa_texformat_z16; + return MESA_FORMAT_Z16; default: ; /* fallthrough */ } @@ -1142,35 +1143,35 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, switch (internalFormat) { case GL_COMPRESSED_ALPHA_ARB: - return &_mesa_texformat_alpha; + return MESA_FORMAT_ALPHA; case GL_COMPRESSED_LUMINANCE_ARB: - return &_mesa_texformat_luminance; + return MESA_FORMAT_LUMINANCE; case GL_COMPRESSED_LUMINANCE_ALPHA_ARB: - return &_mesa_texformat_luminance_alpha; + return MESA_FORMAT_LUMINANCE_ALPHA; case GL_COMPRESSED_INTENSITY_ARB: - return &_mesa_texformat_intensity; + return MESA_FORMAT_INTENSITY; case GL_COMPRESSED_RGB_ARB: #if FEATURE_texture_fxt1 if (ctx->Extensions.TDFX_texture_compression_FXT1) - return &_mesa_texformat_rgb_fxt1; + return MESA_FORMAT_RGB_FXT1; #endif #if FEATURE_texture_s3tc if (ctx->Extensions.EXT_texture_compression_s3tc || ctx->Extensions.S3_s3tc) - return &_mesa_texformat_rgb_dxt1; + return MESA_FORMAT_RGB_DXT1; #endif - return &_mesa_texformat_rgb; + return MESA_FORMAT_RGB; case GL_COMPRESSED_RGBA_ARB: #if FEATURE_texture_fxt1 if (ctx->Extensions.TDFX_texture_compression_FXT1) - return &_mesa_texformat_rgba_fxt1; + return MESA_FORMAT_RGBA_FXT1; #endif #if FEATURE_texture_s3tc if (ctx->Extensions.EXT_texture_compression_s3tc || ctx->Extensions.S3_s3tc) - return &_mesa_texformat_rgba_dxt3; /* Not rgba_dxt1, see spec */ + return MESA_FORMAT_RGBA_DXT3; /* Not rgba_dxt1, see spec */ #endif - return &_mesa_texformat_rgba; + return MESA_FORMAT_RGBA; default: ; /* fallthrough */ } @@ -1178,9 +1179,9 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, if (ctx->Extensions.MESA_ycbcr_texture) { if (internalFormat == GL_YCBCR_MESA) { if (type == GL_UNSIGNED_SHORT_8_8_MESA) - return &_mesa_texformat_ycbcr; + return MESA_FORMAT_YCBCR; else - return &_mesa_texformat_ycbcr_rev; + return MESA_FORMAT_YCBCR_REV; } } @@ -1188,9 +1189,9 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, if (ctx->Extensions.TDFX_texture_compression_FXT1) { switch (internalFormat) { case GL_COMPRESSED_RGB_FXT1_3DFX: - return &_mesa_texformat_rgb_fxt1; + return MESA_FORMAT_RGB_FXT1; case GL_COMPRESSED_RGBA_FXT1_3DFX: - return &_mesa_texformat_rgba_fxt1; + return MESA_FORMAT_RGBA_FXT1; default: ; /* fallthrough */ } @@ -1201,13 +1202,13 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, if (ctx->Extensions.EXT_texture_compression_s3tc) { switch (internalFormat) { case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: - return &_mesa_texformat_rgb_dxt1; + return MESA_FORMAT_RGB_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: - return &_mesa_texformat_rgba_dxt1; + return MESA_FORMAT_RGBA_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: - return &_mesa_texformat_rgba_dxt3; + return MESA_FORMAT_RGBA_DXT3; case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: - return &_mesa_texformat_rgba_dxt5; + return MESA_FORMAT_RGBA_DXT5; default: ; /* fallthrough */ } @@ -1217,10 +1218,10 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, switch (internalFormat) { case GL_RGB_S3TC: case GL_RGB4_S3TC: - return &_mesa_texformat_rgb_dxt1; + return MESA_FORMAT_RGB_DXT1; case GL_RGBA_S3TC: case GL_RGBA4_S3TC: - return &_mesa_texformat_rgba_dxt3; + return MESA_FORMAT_RGBA_DXT3; default: ; /* fallthrough */ } @@ -1230,29 +1231,29 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, if (ctx->Extensions.ARB_texture_float) { switch (internalFormat) { case GL_ALPHA16F_ARB: - return &_mesa_texformat_alpha_float16; + return MESA_FORMAT_ALPHA_FLOAT16; case GL_ALPHA32F_ARB: - return &_mesa_texformat_alpha_float32; + return MESA_FORMAT_ALPHA_FLOAT32; case GL_LUMINANCE16F_ARB: - return &_mesa_texformat_luminance_float16; + return MESA_FORMAT_LUMINANCE_FLOAT16; case GL_LUMINANCE32F_ARB: - return &_mesa_texformat_luminance_float32; + return MESA_FORMAT_LUMINANCE_FLOAT32; case GL_LUMINANCE_ALPHA16F_ARB: - return &_mesa_texformat_luminance_alpha_float16; + return MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16; case GL_LUMINANCE_ALPHA32F_ARB: - return &_mesa_texformat_luminance_alpha_float32; + return MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32; case GL_INTENSITY16F_ARB: - return &_mesa_texformat_intensity_float16; + return MESA_FORMAT_INTENSITY_FLOAT16; case GL_INTENSITY32F_ARB: - return &_mesa_texformat_intensity_float32; + return MESA_FORMAT_INTENSITY_FLOAT32; case GL_RGB16F_ARB: - return &_mesa_texformat_rgb_float16; + return MESA_FORMAT_RGB_FLOAT16; case GL_RGB32F_ARB: - return &_mesa_texformat_rgb_float32; + return MESA_FORMAT_RGB_FLOAT32; case GL_RGBA16F_ARB: - return &_mesa_texformat_rgba_float16; + return MESA_FORMAT_RGBA_FLOAT16; case GL_RGBA32F_ARB: - return &_mesa_texformat_rgba_float32; + return MESA_FORMAT_RGBA_FLOAT32; default: ; /* fallthrough */ } @@ -1262,7 +1263,7 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, switch (internalFormat) { case GL_DEPTH_STENCIL_EXT: case GL_DEPTH24_STENCIL8_EXT: - return &_mesa_texformat_z24_s8; + return MESA_FORMAT_Z24_S8; default: ; /* fallthrough */ } @@ -1272,7 +1273,7 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, switch (internalFormat) { case GL_DUDV_ATI: case GL_DU8DV8_ATI: - return &_mesa_texformat_dudv8; + return MESA_FORMAT_DUDV8; default: ; /* fallthrough */ } @@ -1282,7 +1283,7 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, switch (internalFormat) { case GL_RGBA_SNORM: case GL_RGBA8_SNORM: - return &_mesa_texformat_signed_rgba8888; + return MESA_FORMAT_SIGNED_RGBA8888; default: ; /* fallthrough */ } @@ -1294,48 +1295,48 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, switch (internalFormat) { case GL_SRGB_EXT: case GL_SRGB8_EXT: - return &_mesa_texformat_srgb8; + return MESA_FORMAT_SRGB8; case GL_SRGB_ALPHA_EXT: case GL_SRGB8_ALPHA8_EXT: - return &_mesa_texformat_srgba8; + return MESA_FORMAT_SRGBA8; case GL_SLUMINANCE_EXT: case GL_SLUMINANCE8_EXT: - return &_mesa_texformat_sl8; + return MESA_FORMAT_SL8; case GL_SLUMINANCE_ALPHA_EXT: case GL_SLUMINANCE8_ALPHA8_EXT: - return &_mesa_texformat_sla8; + return MESA_FORMAT_SLA8; case GL_COMPRESSED_SLUMINANCE_EXT: - return &_mesa_texformat_sl8; + return MESA_FORMAT_SL8; case GL_COMPRESSED_SLUMINANCE_ALPHA_EXT: - return &_mesa_texformat_sla8; + return MESA_FORMAT_SLA8; case GL_COMPRESSED_SRGB_EXT: #if FEATURE_texture_s3tc if (ctx->Extensions.EXT_texture_compression_s3tc) - return &_mesa_texformat_srgb_dxt1; + return MESA_FORMAT_SRGB_DXT1; #endif - return &_mesa_texformat_srgb8; + return MESA_FORMAT_SRGB8; case GL_COMPRESSED_SRGB_ALPHA_EXT: #if FEATURE_texture_s3tc if (ctx->Extensions.EXT_texture_compression_s3tc) - return &_mesa_texformat_srgba_dxt3; /* Not srgba_dxt1, see spec */ + return MESA_FORMAT_SRGBA_DXT3; /* Not srgba_dxt1, see spec */ #endif - return &_mesa_texformat_srgba8; + return MESA_FORMAT_SRGBA8; #if FEATURE_texture_s3tc case GL_COMPRESSED_SRGB_S3TC_DXT1_EXT: if (ctx->Extensions.EXT_texture_compression_s3tc) - return &_mesa_texformat_srgb_dxt1; + return MESA_FORMAT_SRGB_DXT1; break; case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT1_EXT: if (ctx->Extensions.EXT_texture_compression_s3tc) - return &_mesa_texformat_srgba_dxt1; + return MESA_FORMAT_SRGBA_DXT1; break; case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT3_EXT: if (ctx->Extensions.EXT_texture_compression_s3tc) - return &_mesa_texformat_srgba_dxt3; + return MESA_FORMAT_SRGBA_DXT3; break; case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT5_EXT: if (ctx->Extensions.EXT_texture_compression_s3tc) - return &_mesa_texformat_srgba_dxt5; + return MESA_FORMAT_SRGBA_DXT5; break; #endif default: @@ -1345,7 +1346,7 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, #endif /* FEATURE_EXT_texture_sRGB */ _mesa_problem(ctx, "unexpected format in _mesa_choose_tex_format()"); - return NULL; + return MESA_FORMAT_NONE; } diff --git a/src/mesa/main/texformat.h b/src/mesa/main/texformat.h index 638eadff97..9095726ac2 100644 --- a/src/mesa/main/texformat.h +++ b/src/mesa/main/texformat.h @@ -39,7 +39,7 @@ #include "mtypes.h" #include "formats.h" - +#if 0 /** GLchan-valued formats */ /*@{*/ extern const struct gl_texture_format _mesa_texformat_rgba; @@ -143,9 +143,9 @@ extern const struct gl_texture_format _mesa_texformat_rgba_dxt5; /*@{*/ extern const struct gl_texture_format _mesa_null_texformat; /*@}*/ +#endif - -extern const struct gl_texture_format * +extern gl_format _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type ); diff --git a/src/mesa/main/texformat_tmp.h b/src/mesa/main/texformat_tmp.h index eb160deff9..cb8386bbc8 100644 --- a/src/mesa/main/texformat_tmp.h +++ b/src/mesa/main/texformat_tmp.h @@ -1424,7 +1424,7 @@ static void FETCH(f_z24_s8)( const struct gl_texture_image *texImage, const GLuint *src = TEXEL_ADDR(GLuint, texImage, i, j, k, 1); const GLfloat scale = 1.0F / (GLfloat) 0xffffff; texel[0] = ((*src) >> 8) * scale; - ASSERT(texImage->TexFormat->MesaFormat == MESA_FORMAT_Z24_S8); + ASSERT(texImage->TexFormat == MESA_FORMAT_Z24_S8); ASSERT(texel[0] >= 0.0F); ASSERT(texel[0] <= 1.0F); } @@ -1451,7 +1451,7 @@ static void FETCH(f_s8_z24)( const struct gl_texture_image *texImage, const GLuint *src = TEXEL_ADDR(GLuint, texImage, i, j, k, 1); const GLfloat scale = 1.0F / (GLfloat) 0xffffff; texel[0] = ((*src) & 0x00ffffff) * scale; - ASSERT(texImage->TexFormat->MesaFormat == MESA_FORMAT_S8_Z24); + ASSERT(texImage->TexFormat == MESA_FORMAT_S8_Z24); ASSERT(texel[0] >= 0.0F); ASSERT(texel[0] <= 1.0F); } diff --git a/src/mesa/main/texgetimage.c b/src/mesa/main/texgetimage.c index 2575d0d868..e9e408d8c5 100644 --- a/src/mesa/main/texgetimage.c +++ b/src/mesa/main/texgetimage.c @@ -49,7 +49,7 @@ static GLboolean is_srgb_teximage(const struct gl_texture_image *texImage) { - switch (texImage->TexFormat->MesaFormat) { + switch (texImage->TexFormat) { case MESA_FORMAT_SRGB8: case MESA_FORMAT_SRGBA8: case MESA_FORMAT_SARGB8: @@ -160,7 +160,7 @@ _mesa_get_teximage(GLcontext *ctx, GLenum target, GLint level, if (format == GL_COLOR_INDEX) { GLuint indexRow[MAX_WIDTH]; GLint col; - GLuint indexBits = _mesa_get_format_bits(texImage->TexFormat->MesaFormat, GL_TEXTURE_INDEX_SIZE_EXT); + GLuint indexBits = _mesa_get_format_bits(texImage->TexFormat, GL_TEXTURE_INDEX_SIZE_EXT); /* Can't use FetchTexel here because that returns RGBA */ if (indexBits == 8) { const GLubyte *src = (const GLubyte *) texImage->Data; @@ -210,9 +210,9 @@ _mesa_get_teximage(GLcontext *ctx, GLenum target, GLint level, (const GLushort *) texImage->Data + row * rowstride, width * sizeof(GLushort)); /* check for byte swapping */ - if ((texImage->TexFormat->MesaFormat == MESA_FORMAT_YCBCR + if ((texImage->TexFormat == MESA_FORMAT_YCBCR && type == GL_UNSIGNED_SHORT_8_8_REV_MESA) || - (texImage->TexFormat->MesaFormat == MESA_FORMAT_YCBCR_REV + (texImage->TexFormat == MESA_FORMAT_YCBCR_REV && type == GL_UNSIGNED_SHORT_8_8_MESA)) { if (!ctx->Pack.SwapBytes) _mesa_swap2((GLushort *) dest, width); @@ -259,7 +259,7 @@ _mesa_get_teximage(GLcontext *ctx, GLenum target, GLint level, GLint col; GLbitfield transferOps = 0x0; GLenum dataType = - _mesa_get_format_datatype(texImage->TexFormat->MesaFormat); + _mesa_get_format_datatype(texImage->TexFormat); /* clamp does not apply to GetTexImage (final conversion)? * Looks like we need clamp though when going from format @@ -350,7 +350,7 @@ _mesa_get_compressed_teximage(GLcontext *ctx, GLenum target, GLint level, /* don't use texImage->CompressedSize since that may be padded out */ size = _mesa_compressed_texture_size(ctx, texImage->Width, texImage->Height, texImage->Depth, - texImage->TexFormat->MesaFormat); + texImage->TexFormat); /* just memcpy, no pixelstore or pixel transfer */ _mesa_memcpy(img, texImage->Data, size); @@ -439,7 +439,7 @@ getteximage_error_check(GLcontext *ctx, GLenum target, GLint level, return GL_TRUE; } - baseFormat = _mesa_get_format_base_format(texImage->TexFormat->MesaFormat); + baseFormat = _mesa_get_format_base_format(texImage->TexFormat); /* Make sure the requested image format is compatible with the * texture's format. Note that a color index texture can be converted diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c index 465da6b046..c4e5ce2682 100644 --- a/src/mesa/main/teximage.c +++ b/src/mesa/main/teximage.c @@ -900,7 +900,7 @@ clear_teximage_fields(struct gl_texture_image *img) img->HeightLog2 = 0; img->DepthLog2 = 0; img->Data = NULL; - img->TexFormat = &_mesa_null_texformat; + img->TexFormat = MESA_FORMAT_NONE; img->FetchTexelc = NULL; img->FetchTexelf = NULL; img->IsCompressed = 0; @@ -2232,8 +2232,8 @@ _mesa_TexImage1D( GLenum target, GLint level, GLint internalFormat, _mesa_init_teximage_fields(ctx, target, texImage, postConvWidth, 1, 1, border, internalFormat); - texImage->TexFormat = (*ctx->Driver.ChooseTextureFormat)(ctx, - internalFormat, format, type); + texImage->TexFormat = + ctx->Driver.ChooseTextureFormat(ctx, internalFormat, format, type); } } else { @@ -2352,8 +2352,8 @@ _mesa_TexImage2D( GLenum target, GLint level, GLint internalFormat, _mesa_init_teximage_fields(ctx, target, texImage, postConvWidth, postConvHeight, 1, border, internalFormat); - texImage->TexFormat = (*ctx->Driver.ChooseTextureFormat)(ctx, - internalFormat, format, type); + texImage->TexFormat = + ctx->Driver.ChooseTextureFormat(ctx, internalFormat, format, type); } } else { @@ -2456,8 +2456,8 @@ _mesa_TexImage3D( GLenum target, GLint level, GLint internalFormat, /* no error, set the tex image parameters */ _mesa_init_teximage_fields(ctx, target, texImage, width, height, depth, border, internalFormat); - texImage->TexFormat = (*ctx->Driver.ChooseTextureFormat)(ctx, - internalFormat, format, type); + texImage->TexFormat = + ctx->Driver.ChooseTextureFormat(ctx, internalFormat, format, type); } } else { diff --git a/src/mesa/main/texparam.c b/src/mesa/main/texparam.c index d38d5a4c23..a9df1dac15 100644 --- a/src/mesa/main/texparam.c +++ b/src/mesa/main/texparam.c @@ -765,7 +765,7 @@ _mesa_GetTexLevelParameteriv( GLenum target, GLint level, goto out; } - texFormat = img->TexFormat->MesaFormat; + texFormat = img->TexFormat; isProxy = _mesa_is_proxy_texture(target); diff --git a/src/mesa/main/texrender.c b/src/mesa/main/texrender.c index 54e5668abc..81bb1d40ff 100644 --- a/src/mesa/main/texrender.c +++ b/src/mesa/main/texrender.c @@ -470,7 +470,7 @@ update_wrapper(GLcontext *ctx, const struct gl_renderbuffer_attachment *att) trb->TexImage = att->Texture->Image[att->CubeMapFace][att->TextureLevel]; ASSERT(trb->TexImage); - trb->Store = _mesa_get_texel_store_func(trb->TexImage->TexFormat->MesaFormat); + trb->Store = _mesa_get_texel_store_func(trb->TexImage->TexFormat); if (!trb->Store) { /* we'll never draw into some textures (compressed formats) */ trb->Store = store_nop; @@ -485,21 +485,21 @@ update_wrapper(GLcontext *ctx, const struct gl_renderbuffer_attachment *att) trb->Zoffset = att->Zoffset; } - texFormat = trb->TexImage->TexFormat->MesaFormat; + texFormat = trb->TexImage->TexFormat; trb->Base.Width = trb->TexImage->Width; trb->Base.Height = trb->TexImage->Height; trb->Base.InternalFormat = trb->TexImage->InternalFormat; /* XXX may need more special cases here */ - if (trb->TexImage->TexFormat->MesaFormat == MESA_FORMAT_Z24_S8) { + if (trb->TexImage->TexFormat == MESA_FORMAT_Z24_S8) { trb->Base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; trb->Base.DataType = GL_UNSIGNED_INT_24_8_EXT; } - else if (trb->TexImage->TexFormat->MesaFormat == MESA_FORMAT_Z16) { + else if (trb->TexImage->TexFormat == MESA_FORMAT_Z16) { trb->Base._ActualFormat = GL_DEPTH_COMPONENT; trb->Base.DataType = GL_UNSIGNED_SHORT; } - else if (trb->TexImage->TexFormat->MesaFormat == MESA_FORMAT_Z32) { + else if (trb->TexImage->TexFormat == MESA_FORMAT_Z32) { trb->Base._ActualFormat = GL_DEPTH_COMPONENT; trb->Base.DataType = GL_UNSIGNED_INT; } diff --git a/src/mesa/main/texstore.c b/src/mesa/main/texstore.c index ca298bb237..02e3df89cf 100644 --- a/src/mesa/main/texstore.c +++ b/src/mesa/main/texstore.c @@ -932,7 +932,7 @@ _mesa_swizzle_ubyte_image(GLcontext *ctx, static void memcpy_texture(GLcontext *ctx, GLuint dimensions, - const struct gl_texture_format *dstFormat, + gl_format dstFormat, GLvoid *dstAddr, GLint dstXoffset, GLint dstYoffset, GLint dstZoffset, GLint dstRowStride, @@ -948,7 +948,7 @@ memcpy_texture(GLcontext *ctx, srcWidth, srcHeight, srcFormat, srcType); const GLubyte *srcImage = (const GLubyte *) _mesa_image_address(dimensions, srcPacking, srcAddr, srcWidth, srcHeight, srcFormat, srcType, 0, 0, 0); - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); const GLint bytesPerRow = srcWidth * texelBytes; #if 0 @@ -1017,15 +1017,15 @@ static GLboolean _mesa_texstore_rgba(TEXSTORE_PARAMS) { const GLint components = _mesa_components_in_format(baseInternalFormat); - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); - - ASSERT(dstFormat == &_mesa_texformat_rgba || - dstFormat == &_mesa_texformat_rgb || - dstFormat == &_mesa_texformat_alpha || - dstFormat == &_mesa_texformat_luminance || - dstFormat == &_mesa_texformat_luminance_alpha || - dstFormat == &_mesa_texformat_intensity); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); + + ASSERT(dstFormat == MESA_FORMAT_RGBA || + dstFormat == MESA_FORMAT_RGB || + dstFormat == MESA_FORMAT_ALPHA || + dstFormat == MESA_FORMAT_LUMINANCE || + dstFormat == MESA_FORMAT_LUMINANCE_ALPHA || + dstFormat == MESA_FORMAT_INTENSITY); ASSERT(baseInternalFormat == GL_RGBA || baseInternalFormat == GL_RGB || baseInternalFormat == GL_ALPHA || @@ -1048,7 +1048,7 @@ _mesa_texstore_rgba(TEXSTORE_PARAMS) } else if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_rgb && + dstFormat == MESA_FORMAT_RGB && srcFormat == GL_RGBA && srcType == CHAN_TYPE) { /* extract RGB from RGBA */ @@ -1089,27 +1089,27 @@ _mesa_texstore_rgba(TEXSTORE_PARAMS) /* dstmap - how to swizzle from RGBA to dst format: */ - if (dstFormat == &_mesa_texformat_rgba) { + if (dstFormat == MESA_FORMAT_RGBA) { dstmap = mappings[IDX_RGBA].from_rgba; components = 4; } - else if (dstFormat == &_mesa_texformat_rgb) { + else if (dstFormat == MESA_FORMAT_RGB) { dstmap = mappings[IDX_RGB].from_rgba; components = 3; } - else if (dstFormat == &_mesa_texformat_alpha) { + else if (dstFormat == MESA_FORMAT_ALPHA) { dstmap = mappings[IDX_ALPHA].from_rgba; components = 1; } - else if (dstFormat == &_mesa_texformat_luminance) { + else if (dstFormat == MESA_FORMAT_LUMINANCE) { dstmap = mappings[IDX_LUMINANCE].from_rgba; components = 1; } - else if (dstFormat == &_mesa_texformat_luminance_alpha) { + else if (dstFormat == MESA_FORMAT_LUMINANCE_ALPHA) { dstmap = mappings[IDX_LUMINANCE_ALPHA].from_rgba; components = 2; } - else if (dstFormat == &_mesa_texformat_intensity) { + else if (dstFormat == MESA_FORMAT_INTENSITY) { dstmap = mappings[IDX_INTENSITY].from_rgba; components = 1; } @@ -1168,9 +1168,9 @@ static GLboolean _mesa_texstore_z32(TEXSTORE_PARAMS) { const GLuint depthScale = 0xffffffff; - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); (void) dims; - ASSERT(dstFormat == &_mesa_texformat_z32); + ASSERT(dstFormat == MESA_FORMAT_Z32); ASSERT(texelBytes == sizeof(GLuint)); if (ctx->Pixel.DepthScale == 1.0f && @@ -1217,9 +1217,9 @@ static GLboolean _mesa_texstore_z16(TEXSTORE_PARAMS) { const GLuint depthScale = 0xffff; - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); (void) dims; - ASSERT(dstFormat == &_mesa_texformat_z16); + ASSERT(dstFormat == MESA_FORMAT_Z16); ASSERT(texelBytes == sizeof(GLushort)); if (ctx->Pixel.DepthScale == 1.0f && @@ -1265,16 +1265,16 @@ _mesa_texstore_z16(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_rgb565(TEXSTORE_PARAMS) { - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_rgb565 || - dstFormat == &_mesa_texformat_rgb565_rev); + ASSERT(dstFormat == MESA_FORMAT_RGB565 || + dstFormat == MESA_FORMAT_RGB565_REV); ASSERT(texelBytes == 2); if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_rgb565 && + dstFormat == MESA_FORMAT_RGB565 && baseInternalFormat == GL_RGB && srcFormat == GL_RGB && srcType == GL_UNSIGNED_SHORT_5_6_5) { @@ -1306,7 +1306,7 @@ _mesa_texstore_rgb565(TEXSTORE_PARAMS) const GLubyte *srcUB = (const GLubyte *) src; GLushort *dstUS = (GLushort *) dst; /* check for byteswapped format */ - if (dstFormat == &_mesa_texformat_rgb565) { + if (dstFormat == MESA_FORMAT_RGB565) { for (col = 0; col < srcWidth; col++) { dstUS[col] = PACK_COLOR_565( srcUB[0], srcUB[1], srcUB[2] ); srcUB += 3; @@ -1343,7 +1343,7 @@ _mesa_texstore_rgb565(TEXSTORE_PARAMS) for (row = 0; row < srcHeight; row++) { GLushort *dstUS = (GLushort *) dstRow; /* check for byteswapped format */ - if (dstFormat == &_mesa_texformat_rgb565) { + if (dstFormat == MESA_FORMAT_RGB565) { for (col = 0; col < srcWidth; col++) { dstUS[col] = PACK_COLOR_565( CHAN_TO_UBYTE(src[RCOMP]), CHAN_TO_UBYTE(src[GCOMP]), @@ -1375,16 +1375,16 @@ static GLboolean _mesa_texstore_rgba8888(TEXSTORE_PARAMS) { const GLboolean littleEndian = _mesa_little_endian(); - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_rgba8888 || - dstFormat == &_mesa_texformat_rgba8888_rev); + ASSERT(dstFormat == MESA_FORMAT_RGBA8888 || + dstFormat == MESA_FORMAT_RGBA8888_REV); ASSERT(texelBytes == 4); if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_rgba8888 && + dstFormat == MESA_FORMAT_RGBA8888 && baseInternalFormat == GL_RGBA && ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8) || (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && !littleEndian) || @@ -1400,7 +1400,7 @@ _mesa_texstore_rgba8888(TEXSTORE_PARAMS) } else if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_rgba8888_rev && + dstFormat == MESA_FORMAT_RGBA8888_REV && baseInternalFormat == GL_RGBA && ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && littleEndian) || @@ -1425,8 +1425,8 @@ _mesa_texstore_rgba8888(TEXSTORE_PARAMS) /* dstmap - how to swizzle from RGBA to dst format: */ - if ((littleEndian && dstFormat == &_mesa_texformat_rgba8888) || - (!littleEndian && dstFormat == &_mesa_texformat_rgba8888_rev)) { + if ((littleEndian && dstFormat == MESA_FORMAT_RGBA8888) || + (!littleEndian && dstFormat == MESA_FORMAT_RGBA8888_REV)) { dstmap[3] = 0; dstmap[2] = 1; dstmap[1] = 2; @@ -1469,7 +1469,7 @@ _mesa_texstore_rgba8888(TEXSTORE_PARAMS) + dstXoffset * texelBytes; for (row = 0; row < srcHeight; row++) { GLuint *dstUI = (GLuint *) dstRow; - if (dstFormat == &_mesa_texformat_rgba8888) { + if (dstFormat == MESA_FORMAT_RGBA8888) { for (col = 0; col < srcWidth; col++) { dstUI[col] = PACK_COLOR_8888( CHAN_TO_UBYTE(src[RCOMP]), CHAN_TO_UBYTE(src[GCOMP]), @@ -1500,16 +1500,16 @@ static GLboolean _mesa_texstore_argb8888(TEXSTORE_PARAMS) { const GLboolean littleEndian = _mesa_little_endian(); - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_argb8888 || - dstFormat == &_mesa_texformat_argb8888_rev); + ASSERT(dstFormat == MESA_FORMAT_ARGB8888 || + dstFormat == MESA_FORMAT_ARGB8888_REV); ASSERT(texelBytes == 4); if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_argb8888 && + dstFormat == MESA_FORMAT_ARGB8888 && baseInternalFormat == GL_RGBA && srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && littleEndian) || @@ -1524,7 +1524,7 @@ _mesa_texstore_argb8888(TEXSTORE_PARAMS) } else if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_argb8888_rev && + dstFormat == MESA_FORMAT_ARGB8888_REV && baseInternalFormat == GL_RGBA && srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && !littleEndian) || @@ -1539,7 +1539,7 @@ _mesa_texstore_argb8888(TEXSTORE_PARAMS) } else if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_argb8888 && + dstFormat == MESA_FORMAT_ARGB8888 && srcFormat == GL_RGB && (baseInternalFormat == GL_RGBA || baseInternalFormat == GL_RGB) && @@ -1569,7 +1569,7 @@ _mesa_texstore_argb8888(TEXSTORE_PARAMS) } else if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_argb8888 && + dstFormat == MESA_FORMAT_ARGB8888 && srcFormat == GL_RGBA && baseInternalFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE) { @@ -1614,16 +1614,16 @@ _mesa_texstore_argb8888(TEXSTORE_PARAMS) /* dstmap - how to swizzle from RGBA to dst format: */ - if ((littleEndian && dstFormat == &_mesa_texformat_argb8888) || - (!littleEndian && dstFormat == &_mesa_texformat_argb8888_rev)) { + if ((littleEndian && dstFormat == MESA_FORMAT_ARGB8888) || + (!littleEndian && dstFormat == MESA_FORMAT_ARGB8888_REV)) { dstmap[3] = 3; /* alpha */ dstmap[2] = 0; /* red */ dstmap[1] = 1; /* green */ dstmap[0] = 2; /* blue */ } else { - assert((littleEndian && dstFormat == &_mesa_texformat_argb8888_rev) || - (!littleEndian && dstFormat == &_mesa_texformat_argb8888)); + assert((littleEndian && dstFormat == MESA_FORMAT_ARGB8888_REV) || + (!littleEndian && dstFormat == MESA_FORMAT_ARGB8888)); dstmap[3] = 2; dstmap[2] = 1; dstmap[1] = 0; @@ -1662,7 +1662,7 @@ _mesa_texstore_argb8888(TEXSTORE_PARAMS) + dstXoffset * texelBytes; for (row = 0; row < srcHeight; row++) { GLuint *dstUI = (GLuint *) dstRow; - if (dstFormat == &_mesa_texformat_argb8888) { + if (dstFormat == MESA_FORMAT_ARGB8888) { for (col = 0; col < srcWidth; col++) { dstUI[col] = PACK_COLOR_8888( CHAN_TO_UBYTE(src[ACOMP]), CHAN_TO_UBYTE(src[RCOMP]), @@ -1693,10 +1693,10 @@ static GLboolean _mesa_texstore_rgb888(TEXSTORE_PARAMS) { const GLboolean littleEndian = _mesa_little_endian(); - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_rgb888); + ASSERT(dstFormat == MESA_FORMAT_RGB888); ASSERT(texelBytes == 3); if (!ctx->_ImageTransferState && @@ -1820,10 +1820,10 @@ static GLboolean _mesa_texstore_bgr888(TEXSTORE_PARAMS) { const GLboolean littleEndian = _mesa_little_endian(); - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_bgr888); + ASSERT(dstFormat == MESA_FORMAT_BGR888); ASSERT(texelBytes == 3); if (!ctx->_ImageTransferState && @@ -1926,15 +1926,15 @@ _mesa_texstore_bgr888(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_rgba4444(TEXSTORE_PARAMS) { - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_rgba4444); + ASSERT(dstFormat == MESA_FORMAT_RGBA4444); ASSERT(texelBytes == 2); if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_rgba4444 && + dstFormat == MESA_FORMAT_RGBA4444 && baseInternalFormat == GL_RGBA && srcFormat == GL_RGBA && srcType == GL_UNSIGNED_SHORT_4_4_4_4){ @@ -1984,16 +1984,16 @@ _mesa_texstore_rgba4444(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_argb4444(TEXSTORE_PARAMS) { - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_argb4444 || - dstFormat == &_mesa_texformat_argb4444_rev); + ASSERT(dstFormat == MESA_FORMAT_ARGB4444 || + dstFormat == MESA_FORMAT_ARGB4444_REV); ASSERT(texelBytes == 2); if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_argb4444 && + dstFormat == MESA_FORMAT_ARGB4444 && baseInternalFormat == GL_RGBA && srcFormat == GL_BGRA && srcType == GL_UNSIGNED_SHORT_4_4_4_4_REV) { @@ -2025,7 +2025,7 @@ _mesa_texstore_argb4444(TEXSTORE_PARAMS) + dstXoffset * texelBytes; for (row = 0; row < srcHeight; row++) { GLushort *dstUS = (GLushort *) dstRow; - if (dstFormat == &_mesa_texformat_argb4444) { + if (dstFormat == MESA_FORMAT_ARGB4444) { for (col = 0; col < srcWidth; col++) { dstUS[col] = PACK_COLOR_4444( CHAN_TO_UBYTE(src[ACOMP]), CHAN_TO_UBYTE(src[RCOMP]), @@ -2054,15 +2054,15 @@ _mesa_texstore_argb4444(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_rgba5551(TEXSTORE_PARAMS) { - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_rgba5551); + ASSERT(dstFormat == MESA_FORMAT_RGBA5551); ASSERT(texelBytes == 2); if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_rgba5551 && + dstFormat == MESA_FORMAT_RGBA5551 && baseInternalFormat == GL_RGBA && srcFormat == GL_RGBA && srcType == GL_UNSIGNED_SHORT_5_5_5_1) { @@ -2112,16 +2112,16 @@ _mesa_texstore_rgba5551(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_argb1555(TEXSTORE_PARAMS) { - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_argb1555 || - dstFormat == &_mesa_texformat_argb1555_rev); + ASSERT(dstFormat == MESA_FORMAT_ARGB1555 || + dstFormat == MESA_FORMAT_ARGB1555_REV); ASSERT(texelBytes == 2); if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_argb1555 && + dstFormat == MESA_FORMAT_ARGB1555 && baseInternalFormat == GL_RGBA && srcFormat == GL_BGRA && srcType == GL_UNSIGNED_SHORT_1_5_5_5_REV) { @@ -2153,7 +2153,7 @@ _mesa_texstore_argb1555(TEXSTORE_PARAMS) + dstXoffset * texelBytes; for (row = 0; row < srcHeight; row++) { GLushort *dstUS = (GLushort *) dstRow; - if (dstFormat == &_mesa_texformat_argb1555) { + if (dstFormat == MESA_FORMAT_ARGB1555) { for (col = 0; col < srcWidth; col++) { dstUS[col] = PACK_COLOR_1555( CHAN_TO_UBYTE(src[ACOMP]), CHAN_TO_UBYTE(src[RCOMP]), @@ -2184,16 +2184,16 @@ static GLboolean _mesa_texstore_al88(TEXSTORE_PARAMS) { const GLboolean littleEndian = _mesa_little_endian(); - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_al88 || - dstFormat == &_mesa_texformat_al88_rev); + ASSERT(dstFormat == MESA_FORMAT_AL88 || + dstFormat == MESA_FORMAT_AL88_REV); ASSERT(texelBytes == 2); if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_al88 && + dstFormat == MESA_FORMAT_AL88 && baseInternalFormat == GL_LUMINANCE_ALPHA && srcFormat == GL_LUMINANCE_ALPHA && srcType == GL_UNSIGNED_BYTE && @@ -2216,8 +2216,8 @@ _mesa_texstore_al88(TEXSTORE_PARAMS) /* dstmap - how to swizzle from RGBA to dst format: */ - if ((littleEndian && dstFormat == &_mesa_texformat_al88) || - (!littleEndian && dstFormat == &_mesa_texformat_al88_rev)) { + if ((littleEndian && dstFormat == MESA_FORMAT_AL88) || + (!littleEndian && dstFormat == MESA_FORMAT_AL88_REV)) { dstmap[0] = 0; dstmap[1] = 3; } @@ -2258,7 +2258,7 @@ _mesa_texstore_al88(TEXSTORE_PARAMS) + dstXoffset * texelBytes; for (row = 0; row < srcHeight; row++) { GLushort *dstUS = (GLushort *) dstRow; - if (dstFormat == &_mesa_texformat_al88) { + if (dstFormat == MESA_FORMAT_AL88) { for (col = 0; col < srcWidth; col++) { /* src[0] is luminance, src[1] is alpha */ dstUS[col] = PACK_COLOR_88( CHAN_TO_UBYTE(src[1]), @@ -2286,10 +2286,10 @@ _mesa_texstore_al88(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_rgb332(TEXSTORE_PARAMS) { - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_rgb332); + ASSERT(dstFormat == MESA_FORMAT_RGB332); ASSERT(texelBytes == 1); if (!ctx->_ImageTransferState && @@ -2344,12 +2344,12 @@ _mesa_texstore_rgb332(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_a8(TEXSTORE_PARAMS) { - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_a8 || - dstFormat == &_mesa_texformat_l8 || - dstFormat == &_mesa_texformat_i8); + ASSERT(dstFormat == MESA_FORMAT_A8 || + dstFormat == MESA_FORMAT_L8 || + dstFormat == MESA_FORMAT_I8); ASSERT(texelBytes == 1); if (!ctx->_ImageTransferState && @@ -2373,7 +2373,7 @@ _mesa_texstore_a8(TEXSTORE_PARAMS) /* dstmap - how to swizzle from RGBA to dst format: */ - if (dstFormat == &_mesa_texformat_a8) { + if (dstFormat == MESA_FORMAT_A8) { dstmap[0] = 3; } else { @@ -2429,10 +2429,10 @@ _mesa_texstore_a8(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_ci8(TEXSTORE_PARAMS) { - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); (void) dims; (void) baseInternalFormat; - ASSERT(dstFormat == &_mesa_texformat_ci8); + ASSERT(dstFormat == MESA_FORMAT_CI8); ASSERT(texelBytes == 1); ASSERT(baseInternalFormat == GL_COLOR_INDEX); @@ -2471,18 +2471,18 @@ _mesa_texstore_ci8(TEXSTORE_PARAMS) /** - * Texstore for _mesa_texformat_ycbcr or _mesa_texformat_ycbcr_rev. + * Texstore for _mesa_texformat_ycbcr or _mesa_texformat_ycbcr_REV. */ static GLboolean _mesa_texstore_ycbcr(TEXSTORE_PARAMS) { const GLboolean littleEndian = _mesa_little_endian(); - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); (void) ctx; (void) dims; (void) baseInternalFormat; - ASSERT((dstFormat == &_mesa_texformat_ycbcr) || - (dstFormat == &_mesa_texformat_ycbcr_rev)); + ASSERT((dstFormat == MESA_FORMAT_YCBCR) || + (dstFormat == MESA_FORMAT_YCBCR_REV)); ASSERT(texelBytes == 2); ASSERT(ctx->Extensions.MESA_ycbcr_texture); ASSERT(srcFormat == GL_YCBCR_MESA); @@ -2502,7 +2502,7 @@ _mesa_texstore_ycbcr(TEXSTORE_PARAMS) /* XXX the logic here _might_ be wrong */ if (srcPacking->SwapBytes ^ (srcType == GL_UNSIGNED_SHORT_8_8_REV_MESA) ^ - (dstFormat == &_mesa_texformat_ycbcr_rev) ^ + (dstFormat == MESA_FORMAT_YCBCR_REV) ^ !littleEndian) { GLint img, row; for (img = 0; img < srcDepth; img++) { @@ -2523,9 +2523,9 @@ static GLboolean _mesa_texstore_dudv8(TEXSTORE_PARAMS) { const GLboolean littleEndian = _mesa_little_endian(); - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_dudv8); + ASSERT(dstFormat == MESA_FORMAT_DUDV8); ASSERT(texelBytes == 2); ASSERT(ctx->Extensions.ATI_envmap_bumpmap); ASSERT((srcFormat == GL_DU8DV8_ATI) || @@ -2617,16 +2617,16 @@ static GLboolean _mesa_texstore_signed_rgba8888(TEXSTORE_PARAMS) { const GLboolean littleEndian = _mesa_little_endian(); - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_signed_rgba8888 || - dstFormat == &_mesa_texformat_signed_rgba8888_rev); + ASSERT(dstFormat == MESA_FORMAT_SIGNED_RGBA8888 || + dstFormat == MESA_FORMAT_SIGNED_RGBA8888_REV); ASSERT(texelBytes == 4); if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_signed_rgba8888 && + dstFormat == MESA_FORMAT_SIGNED_RGBA8888 && baseInternalFormat == GL_RGBA && ((srcFormat == GL_RGBA && srcType == GL_BYTE && !littleEndian) || (srcFormat == GL_ABGR_EXT && srcType == GL_BYTE && littleEndian))) { @@ -2640,7 +2640,7 @@ _mesa_texstore_signed_rgba8888(TEXSTORE_PARAMS) } else if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_signed_rgba8888_rev && + dstFormat == MESA_FORMAT_SIGNED_RGBA8888_REV && baseInternalFormat == GL_RGBA && ((srcFormat == GL_RGBA && srcType == GL_BYTE && littleEndian) || (srcFormat == GL_ABGR_EXT && srcType == GL_BYTE && !littleEndian))) { @@ -2661,8 +2661,8 @@ _mesa_texstore_signed_rgba8888(TEXSTORE_PARAMS) /* dstmap - how to swizzle from RGBA to dst format: */ - if ((littleEndian && dstFormat == &_mesa_texformat_signed_rgba8888) || - (!littleEndian && dstFormat == &_mesa_texformat_signed_rgba8888_rev)) { + if ((littleEndian && dstFormat == MESA_FORMAT_SIGNED_RGBA8888) || + (!littleEndian && dstFormat == MESA_FORMAT_SIGNED_RGBA8888_REV)) { dstmap[3] = 0; dstmap[2] = 1; dstmap[1] = 2; @@ -2705,7 +2705,7 @@ _mesa_texstore_signed_rgba8888(TEXSTORE_PARAMS) + dstXoffset * texelBytes; for (row = 0; row < srcHeight; row++) { GLuint *dstUI = (GLuint *) dstRow; - if (dstFormat == &_mesa_texformat_signed_rgba8888) { + if (dstFormat == MESA_FORMAT_SIGNED_RGBA8888) { for (col = 0; col < srcWidth; col++) { dstUI[col] = PACK_COLOR_8888( FLOAT_TO_BYTE_TEX(srcRow[RCOMP]), FLOAT_TO_BYTE_TEX(srcRow[GCOMP]), @@ -2743,7 +2743,7 @@ _mesa_texstore_z24_s8(TEXSTORE_PARAMS) / sizeof(GLuint); GLint img, row; - ASSERT(dstFormat == &_mesa_texformat_z24_s8); + ASSERT(dstFormat == MESA_FORMAT_Z24_S8); ASSERT(srcFormat == GL_DEPTH_STENCIL_EXT || srcFormat == GL_DEPTH_COMPONENT); ASSERT(srcFormat != GL_DEPTH_STENCIL_EXT || srcType == GL_UNSIGNED_INT_24_8_EXT); @@ -2844,7 +2844,7 @@ _mesa_texstore_s8_z24(TEXSTORE_PARAMS) / sizeof(GLuint); GLint img, row; - ASSERT(dstFormat == &_mesa_texformat_s8_z24); + ASSERT(dstFormat == MESA_FORMAT_S8_Z24); ASSERT(srcFormat == GL_DEPTH_STENCIL_EXT || srcFormat == GL_DEPTH_COMPONENT); ASSERT(srcFormat != GL_DEPTH_STENCIL_EXT || srcType == GL_UNSIGNED_INT_24_8_EXT); @@ -2927,16 +2927,16 @@ _mesa_texstore_s8_z24(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_rgba_float32(TEXSTORE_PARAMS) { - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); const GLint components = _mesa_components_in_format(baseFormat); - ASSERT(dstFormat == &_mesa_texformat_rgba_float32 || - dstFormat == &_mesa_texformat_rgb_float32 || - dstFormat == &_mesa_texformat_alpha_float32 || - dstFormat == &_mesa_texformat_luminance_float32 || - dstFormat == &_mesa_texformat_luminance_alpha_float32 || - dstFormat == &_mesa_texformat_intensity_float32); + ASSERT(dstFormat == MESA_FORMAT_RGBA_FLOAT32 || + dstFormat == MESA_FORMAT_RGB_FLOAT32 || + dstFormat == MESA_FORMAT_ALPHA_FLOAT32 || + dstFormat == MESA_FORMAT_LUMINANCE_FLOAT32 || + dstFormat == MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32 || + dstFormat == MESA_FORMAT_INTENSITY_FLOAT32); ASSERT(baseInternalFormat == GL_RGBA || baseInternalFormat == GL_RGB || baseInternalFormat == GL_ALPHA || @@ -2996,16 +2996,16 @@ _mesa_texstore_rgba_float32(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_rgba_float16(TEXSTORE_PARAMS) { - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); const GLint components = _mesa_components_in_format(baseFormat); - ASSERT(dstFormat == &_mesa_texformat_rgba_float16 || - dstFormat == &_mesa_texformat_rgb_float16 || - dstFormat == &_mesa_texformat_alpha_float16 || - dstFormat == &_mesa_texformat_luminance_float16 || - dstFormat == &_mesa_texformat_luminance_alpha_float16 || - dstFormat == &_mesa_texformat_intensity_float16); + ASSERT(dstFormat == MESA_FORMAT_RGBA_FLOAT16 || + dstFormat == MESA_FORMAT_RGB_FLOAT16 || + dstFormat == MESA_FORMAT_ALPHA_FLOAT16 || + dstFormat == MESA_FORMAT_LUMINANCE_FLOAT16 || + dstFormat == MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16 || + dstFormat == MESA_FORMAT_INTENSITY_FLOAT16); ASSERT(baseInternalFormat == GL_RGBA || baseInternalFormat == GL_RGB || baseInternalFormat == GL_ALPHA || @@ -3065,13 +3065,13 @@ _mesa_texstore_rgba_float16(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_srgb8(TEXSTORE_PARAMS) { - const struct gl_texture_format *newDstFormat; + gl_format newDstFormat; GLboolean k; - ASSERT(dstFormat == &_mesa_texformat_srgb8); + ASSERT(dstFormat == MESA_FORMAT_SRGB8); /* reuse normal rgb texstore code */ - newDstFormat = &_mesa_texformat_rgb888; + newDstFormat = MESA_FORMAT_RGB888; k = _mesa_texstore_rgb888(ctx, dims, baseInternalFormat, newDstFormat, dstAddr, @@ -3087,13 +3087,13 @@ _mesa_texstore_srgb8(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_srgba8(TEXSTORE_PARAMS) { - const struct gl_texture_format *newDstFormat; + gl_format newDstFormat; GLboolean k; - ASSERT(dstFormat == &_mesa_texformat_srgba8); + ASSERT(dstFormat == MESA_FORMAT_SRGBA8); /* reuse normal rgba texstore code */ - newDstFormat = &_mesa_texformat_rgba8888; + newDstFormat = MESA_FORMAT_RGBA8888; k = _mesa_texstore_rgba8888(ctx, dims, baseInternalFormat, newDstFormat, dstAddr, dstXoffset, dstYoffset, dstZoffset, @@ -3108,13 +3108,13 @@ _mesa_texstore_srgba8(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_sargb8(TEXSTORE_PARAMS) { - const struct gl_texture_format *newDstFormat; + gl_format newDstFormat; GLboolean k; - ASSERT(dstFormat == &_mesa_texformat_sargb8); + ASSERT(dstFormat == MESA_FORMAT_SARGB8); /* reuse normal rgba texstore code */ - newDstFormat = &_mesa_texformat_argb8888; + newDstFormat = MESA_FORMAT_ARGB8888; k = _mesa_texstore_argb8888(ctx, dims, baseInternalFormat, newDstFormat, dstAddr, @@ -3130,12 +3130,12 @@ _mesa_texstore_sargb8(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_sl8(TEXSTORE_PARAMS) { - const struct gl_texture_format *newDstFormat; + gl_format newDstFormat; GLboolean k; - ASSERT(dstFormat == &_mesa_texformat_sl8); + ASSERT(dstFormat == MESA_FORMAT_SL8); - newDstFormat = &_mesa_texformat_l8; + newDstFormat = MESA_FORMAT_L8; /* _mesa_textore_a8 handles luminance8 too */ k = _mesa_texstore_a8(ctx, dims, baseInternalFormat, @@ -3152,13 +3152,13 @@ _mesa_texstore_sl8(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_sla8(TEXSTORE_PARAMS) { - const struct gl_texture_format *newDstFormat; + gl_format newDstFormat; GLboolean k; - ASSERT(dstFormat == &_mesa_texformat_sla8); + ASSERT(dstFormat == MESA_FORMAT_SLA8); /* reuse normal luminance/alpha texstore code */ - newDstFormat = &_mesa_texformat_al88; + newDstFormat = MESA_FORMAT_AL88; k = _mesa_texstore_al88(ctx, dims, baseInternalFormat, newDstFormat, dstAddr, @@ -3280,7 +3280,7 @@ _mesa_texstore(TEXSTORE_PARAMS) StoreTexImageFunc storeImage; GLboolean success; - storeImage = _mesa_get_texstore_func(dstFormat->MesaFormat); + storeImage = _mesa_get_texstore_func(dstFormat); assert(storeImage); @@ -3390,7 +3390,7 @@ fetch_texel_float_to_chan(const struct gl_texture_image *texImage, GLint i, GLint j, GLint k, GLchan *texelOut) { GLfloat temp[4]; - GLenum baseFormat = _mesa_get_format_base_format(texImage->TexFormat->MesaFormat); + GLenum baseFormat = _mesa_get_format_base_format(texImage->TexFormat); ASSERT(texImage->FetchTexelf); texImage->FetchTexelf(texImage, i, j, k, temp); @@ -3417,7 +3417,7 @@ fetch_texel_chan_to_float(const struct gl_texture_image *texImage, GLint i, GLint j, GLint k, GLfloat *texelOut) { GLchan temp[4]; - GLenum baseFormat = _mesa_get_format_base_format(texImage->TexFormat->MesaFormat); + GLenum baseFormat = _mesa_get_format_base_format(texImage->TexFormat); ASSERT(texImage->FetchTexelc); texImage->FetchTexelc(texImage, i, j, k, temp); @@ -3446,7 +3446,7 @@ _mesa_set_fetch_functions(struct gl_texture_image *texImage, GLuint dims) ASSERT(texImage->TexFormat); texImage->FetchTexelf = - _mesa_get_texel_fetch_func(texImage->TexFormat->MesaFormat, dims); + _mesa_get_texel_fetch_func(texImage->TexFormat, dims); /* now check if we need to use a float/chan adaptor */ if (!texImage->FetchTexelc) { @@ -3466,13 +3466,13 @@ static void compute_texture_size(GLcontext *ctx, struct gl_texture_image *texImage) { texImage->IsCompressed = - _mesa_is_format_compressed(texImage->TexFormat->MesaFormat); + _mesa_is_format_compressed(texImage->TexFormat); if (texImage->IsCompressed) { texImage->CompressedSize = ctx->Driver.CompressedTextureSize(ctx, texImage->Width, texImage->Height, texImage->Depth, - texImage->TexFormat->MesaFormat); + texImage->TexFormat); } else { /* non-compressed format */ @@ -3513,7 +3513,7 @@ _mesa_store_teximage1d(GLcontext *ctx, GLenum target, GLint level, if (texImage->IsCompressed) sizeInBytes = texImage->CompressedSize; else - sizeInBytes = texImage->Width * _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + sizeInBytes = texImage->Width * _mesa_get_format_bytes(texImage->TexFormat); texImage->Data = _mesa_alloc_texmemory(sizeInBytes); if (!texImage->Data) { _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage1D"); @@ -3578,7 +3578,7 @@ _mesa_store_teximage2d(GLcontext *ctx, GLenum target, GLint level, _mesa_set_fetch_functions(texImage, 2); compute_texture_size(ctx, texImage); - texelBytes = _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); /* allocate memory */ if (texImage->IsCompressed) @@ -3605,7 +3605,7 @@ _mesa_store_teximage2d(GLcontext *ctx, GLenum target, GLint level, if (texImage->IsCompressed) { dstRowStride - = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width); + = _mesa_compressed_row_stride(texImage->TexFormat, width); } else { dstRowStride = texImage->RowStride * texelBytes; @@ -3654,7 +3654,7 @@ _mesa_store_teximage3d(GLcontext *ctx, GLenum target, GLint level, _mesa_set_fetch_functions(texImage, 3); compute_texture_size(ctx, texImage); - texelBytes = _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); /* allocate memory */ if (texImage->IsCompressed) @@ -3681,7 +3681,7 @@ _mesa_store_teximage3d(GLcontext *ctx, GLenum target, GLint level, if (texImage->IsCompressed) { dstRowStride - = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width); + = _mesa_compressed_row_stride(texImage->TexFormat, width); } else { dstRowStride = texImage->RowStride * texelBytes; @@ -3770,12 +3770,12 @@ _mesa_store_texsubimage2d(GLcontext *ctx, GLenum target, GLint level, GLboolean success; if (texImage->IsCompressed) { - dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, + dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat, texImage->Width); } else { dstRowStride = texImage->RowStride * - _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + _mesa_get_format_bytes(texImage->TexFormat); } success = _mesa_texstore(ctx, 2, texImage->_BaseFormat, @@ -3820,12 +3820,12 @@ _mesa_store_texsubimage3d(GLcontext *ctx, GLenum target, GLint level, GLboolean success; if (texImage->IsCompressed) { - dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, + dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat, texImage->Width); } else { dstRowStride = texImage->RowStride * - _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + _mesa_get_format_bytes(texImage->TexFormat); } success = _mesa_texstore(ctx, 3, texImage->_BaseFormat, @@ -3985,7 +3985,7 @@ _mesa_store_compressed_texsubimage2d(GLcontext *ctx, GLenum target, GLint i, rows; GLubyte *dest; const GLubyte *src; - const gl_format texFormat = texImage->TexFormat->MesaFormat; + const gl_format texFormat = texImage->TexFormat; (void) format; diff --git a/src/mesa/main/texstore.h b/src/mesa/main/texstore.h index 4a217df103..2db076dfff 100644 --- a/src/mesa/main/texstore.h +++ b/src/mesa/main/texstore.h @@ -58,7 +58,7 @@ #define TEXSTORE_PARAMS \ GLcontext *ctx, GLuint dims, \ GLenum baseInternalFormat, \ - const struct gl_texture_format *dstFormat, \ + gl_format dstFormat, \ GLvoid *dstAddr, \ GLint dstXoffset, GLint dstYoffset, GLint dstZoffset, \ GLint dstRowStride, const GLuint *dstImageOffsets, \ diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c b/src/mesa/state_tracker/st_cb_drawpixels.c index 6da57e817b..081c09c1fb 100644 --- a/src/mesa/state_tracker/st_cb_drawpixels.c +++ b/src/mesa/state_tracker/st_cb_drawpixels.c @@ -338,7 +338,7 @@ make_texture(struct st_context *st, GLcontext *ctx = st->ctx; struct pipe_context *pipe = st->pipe; struct pipe_screen *screen = pipe->screen; - const struct gl_texture_format *mformat; + gl_format mformat; struct pipe_texture *pt; enum pipe_format pipeFormat; GLuint cpp; @@ -350,7 +350,7 @@ make_texture(struct st_context *st, mformat = st_ChooseTextureFormat(ctx, baseFormat, format, type); assert(mformat); - pipeFormat = st_mesa_format_to_pipe_format(mformat->MesaFormat); + pipeFormat = st_mesa_format_to_pipe_format(mformat); assert(pipeFormat); cpp = st_sizeof_format(pipeFormat); diff --git a/src/mesa/state_tracker/st_cb_texture.c b/src/mesa/state_tracker/st_cb_texture.c index d96484c439..716fbc8b29 100644 --- a/src/mesa/state_tracker/st_cb_texture.c +++ b/src/mesa/state_tracker/st_cb_texture.c @@ -95,9 +95,9 @@ gl_target_to_pipe(GLenum target) * format. */ static GLuint -compressed_num_bytes(GLuint mesaFormat) +compressed_num_bytes(gl_format format) { - switch(mesaFormat) { + switch (format) { #if FEATURE_texture_fxt1 case MESA_FORMAT_RGB_FXT1: case MESA_FORMAT_RGBA_FXT1: @@ -117,9 +117,9 @@ compressed_num_bytes(GLuint mesaFormat) static GLboolean -is_compressed_mesa_format(const struct gl_texture_format *format) +is_compressed_mesa_format(gl_format format) { - switch (format->MesaFormat) { + switch (format) { case MESA_FORMAT_RGB_DXT1: case MESA_FORMAT_RGBA_DXT1: case MESA_FORMAT_RGBA_DXT3: @@ -338,7 +338,7 @@ guess_and_alloc_texture(struct st_context *st, lastLevel = firstLevel + MAX2(MAX2(l2width, l2height), l2depth); } - fmt = st_mesa_format_to_pipe_format(stImage->base.TexFormat->MesaFormat); + fmt = st_mesa_format_to_pipe_format(stImage->base.TexFormat); usage = default_usage(fmt); @@ -411,7 +411,7 @@ compress_with_blit(GLcontext * ctx, const GLuint dstImageOffsets[1] = {0}; struct st_texture_image *stImage = st_texture_image(texImage); struct pipe_screen *screen = ctx->st->pipe->screen; - const struct gl_texture_format *mesa_format; + gl_format mesa_format; struct pipe_texture templ; struct pipe_texture *src_tex; struct pipe_surface *dst_surface; @@ -443,7 +443,7 @@ compress_with_blit(GLcontext * ctx, */ memset(&templ, 0, sizeof(templ)); templ.target = PIPE_TEXTURE_2D; - templ.format = st_mesa_format_to_pipe_format(mesa_format->MesaFormat); + templ.format = st_mesa_format_to_pipe_format(mesa_format); pf_get_block(templ.format, &templ.block); templ.width[0] = width; templ.height[0] = height; @@ -559,17 +559,17 @@ st_TexImage(GLcontext * ctx, _mesa_set_fetch_functions(texImage, dims); - if (_mesa_is_format_compressed(texImage->TexFormat->MesaFormat)) { + if (_mesa_is_format_compressed(texImage->TexFormat)) { /* must be a compressed format */ texelBytes = 0; texImage->IsCompressed = GL_TRUE; texImage->CompressedSize = ctx->Driver.CompressedTextureSize(ctx, texImage->Width, texImage->Height, texImage->Depth, - texImage->TexFormat->MesaFormat); + texImage->TexFormat); } else { - texelBytes = _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); /* Minimum pitch of 32 bytes */ if (postConvWidth * texelBytes < 32) { @@ -699,7 +699,7 @@ st_TexImage(GLcontext * ctx, if (texImage->IsCompressed) { sizeInBytes = texImage->CompressedSize; dstRowStride = - _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width); + _mesa_compressed_row_stride(texImage->TexFormat, width); assert(dims != 3); } else { @@ -1824,10 +1824,10 @@ st_finalize_texture(GLcontext *ctx, /* FIXME: determine format block instead of cpp */ if (firstImage->base.IsCompressed) { - cpp = compressed_num_bytes(firstImage->base.TexFormat->MesaFormat); + cpp = compressed_num_bytes(firstImage->base.TexFormat); } else { - cpp = _mesa_get_format_bytes(firstImage->base.TexFormat->MesaFormat); + cpp = _mesa_get_format_bytes(firstImage->base.TexFormat); } /* If we already have a gallium texture, check that it matches the texture @@ -1835,7 +1835,7 @@ st_finalize_texture(GLcontext *ctx, */ if (stObj->pt) { const enum pipe_format fmt = - st_mesa_format_to_pipe_format(firstImage->base.TexFormat->MesaFormat); + st_mesa_format_to_pipe_format(firstImage->base.TexFormat); if (stObj->pt->target != gl_target_to_pipe(stObj->base.Target) || stObj->pt->format != fmt || stObj->pt->last_level < stObj->lastLevel || @@ -1854,7 +1854,7 @@ st_finalize_texture(GLcontext *ctx, */ if (!stObj->pt) { const enum pipe_format fmt = - st_mesa_format_to_pipe_format(firstImage->base.TexFormat->MesaFormat); + st_mesa_format_to_pipe_format(firstImage->base.TexFormat); GLuint usage = default_usage(fmt); stObj->pt = st_texture_create(ctx->st, diff --git a/src/mesa/state_tracker/st_format.c b/src/mesa/state_tracker/st_format.c index dcb90a3107..6f76e2d8c0 100644 --- a/src/mesa/state_tracker/st_format.c +++ b/src/mesa/state_tracker/st_format.c @@ -629,74 +629,74 @@ st_choose_renderbuffer_format(struct pipe_context *pipe, GLenum internalFormat) } -static const struct gl_texture_format * +static gl_format translate_gallium_format_to_mesa_format(enum pipe_format format) { switch (format) { case PIPE_FORMAT_A8R8G8B8_UNORM: - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; case PIPE_FORMAT_A1R5G5B5_UNORM: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case PIPE_FORMAT_A4R4G4B4_UNORM: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case PIPE_FORMAT_R5G6B5_UNORM: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; case PIPE_FORMAT_A8L8_UNORM: - return &_mesa_texformat_al88; + return MESA_FORMAT_AL88; case PIPE_FORMAT_A8_UNORM: - return &_mesa_texformat_a8; + return MESA_FORMAT_A8; case PIPE_FORMAT_L8_UNORM: - return &_mesa_texformat_l8; + return MESA_FORMAT_L8; case PIPE_FORMAT_I8_UNORM: - return &_mesa_texformat_i8; + return MESA_FORMAT_I8; case PIPE_FORMAT_Z16_UNORM: - return &_mesa_texformat_z16; + return MESA_FORMAT_Z16; case PIPE_FORMAT_Z32_UNORM: - return &_mesa_texformat_z32; + return MESA_FORMAT_Z32; case PIPE_FORMAT_Z24S8_UNORM: - return &_mesa_texformat_z24_s8; + return MESA_FORMAT_Z24_S8; case PIPE_FORMAT_S8Z24_UNORM: - return &_mesa_texformat_s8_z24; + return MESA_FORMAT_S8_Z24; case PIPE_FORMAT_YCBCR: - return &_mesa_texformat_ycbcr; + return MESA_FORMAT_YCBCR; case PIPE_FORMAT_YCBCR_REV: - return &_mesa_texformat_ycbcr_rev; + return MESA_FORMAT_YCBCR_REV; #if FEATURE_texture_s3tc case PIPE_FORMAT_DXT1_RGB: - return &_mesa_texformat_rgb_dxt1; + return MESA_FORMAT_RGB_DXT1; case PIPE_FORMAT_DXT1_RGBA: - return &_mesa_texformat_rgba_dxt1; + return MESA_FORMAT_RGBA_DXT1; case PIPE_FORMAT_DXT3_RGBA: - return &_mesa_texformat_rgba_dxt3; + return MESA_FORMAT_RGBA_DXT3; case PIPE_FORMAT_DXT5_RGBA: - return &_mesa_texformat_rgba_dxt5; + return MESA_FORMAT_RGBA_DXT5; #if FEATURE_EXT_texture_sRGB case PIPE_FORMAT_DXT1_SRGB: - return &_mesa_texformat_srgb_dxt1; + return MESA_FORMAT_SRGB_DXT1; case PIPE_FORMAT_DXT1_SRGBA: - return &_mesa_texformat_srgba_dxt1; + return MESA_FORMAT_SRGBA_DXT1; case PIPE_FORMAT_DXT3_SRGBA: - return &_mesa_texformat_srgba_dxt3; + return MESA_FORMAT_SRGBA_DXT3; case PIPE_FORMAT_DXT5_SRGBA: - return &_mesa_texformat_srgba_dxt5; + return MESA_FORMAT_SRGBA_DXT5; #endif #endif #if FEATURE_EXT_texture_sRGB case PIPE_FORMAT_A8L8_SRGB: - return &_mesa_texformat_sla8; + return MESA_FORMAT_SLA8; case PIPE_FORMAT_L8_SRGB: - return &_mesa_texformat_sl8; + return MESA_FORMAT_SL8; case PIPE_FORMAT_R8G8B8_SRGB: - return &_mesa_texformat_srgb8; + return MESA_FORMAT_SRGB8; case PIPE_FORMAT_R8G8B8A8_SRGB: - return &_mesa_texformat_srgba8; + return MESA_FORMAT_SRGBA8; case PIPE_FORMAT_A8R8G8B8_SRGB: - return &_mesa_texformat_sargb8; + return MESA_FORMAT_SARGB8; #endif /* XXX add additional cases */ default: assert(0); - return NULL; + return MESA_FORMAT_NONE; } } @@ -704,7 +704,7 @@ translate_gallium_format_to_mesa_format(enum pipe_format format) /** * Called via ctx->Driver.chooseTextureFormat(). */ -const struct gl_texture_format * +gl_format st_ChooseTextureFormat(GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type) { @@ -716,7 +716,7 @@ st_ChooseTextureFormat(GLcontext *ctx, GLint internalFormat, pFormat = st_choose_format(ctx->st->pipe, internalFormat, PIPE_TEXTURE_2D, PIPE_TEXTURE_USAGE_SAMPLER); if (pFormat == PIPE_FORMAT_NONE) - return NULL; + return MESA_FORMAT_NONE; return translate_gallium_format_to_mesa_format(pFormat); } diff --git a/src/mesa/state_tracker/st_format.h b/src/mesa/state_tracker/st_format.h index 9d9e02fe9b..1a8c6ea98f 100644 --- a/src/mesa/state_tracker/st_format.h +++ b/src/mesa/state_tracker/st_format.h @@ -29,6 +29,7 @@ #ifndef ST_FORMAT_H #define ST_FORMAT_H +#include "main/formats.h" struct pipe_format_info { @@ -71,7 +72,7 @@ extern enum pipe_format st_choose_renderbuffer_format(struct pipe_context *pipe, GLenum internalFormat); -extern const struct gl_texture_format * +extern gl_format st_ChooseTextureFormat(GLcontext * ctx, GLint internalFormat, GLenum format, GLenum type); diff --git a/src/mesa/state_tracker/st_gen_mipmap.c b/src/mesa/state_tracker/st_gen_mipmap.c index 63a6956a7a..58f6933652 100644 --- a/src/mesa/state_tracker/st_gen_mipmap.c +++ b/src/mesa/state_tracker/st_gen_mipmap.c @@ -115,7 +115,7 @@ fallback_generate_mipmap(GLcontext *ctx, GLenum target, assert(target != GL_TEXTURE_3D); /* not done yet */ - _mesa_format_to_type_and_comps(texObj->Image[face][baseLevel]->TexFormat->MesaFormat, + _mesa_format_to_type_and_comps(texObj->Image[face][baseLevel]->TexFormat, &datatype, &comps); for (dstLevel = baseLevel + 1; dstLevel <= lastLevel; dstLevel++) { diff --git a/src/mesa/state_tracker/st_texture.c b/src/mesa/state_tracker/st_texture.c index bbc2830e69..1790e1b28d 100644 --- a/src/mesa/state_tracker/st_texture.c +++ b/src/mesa/state_tracker/st_texture.c @@ -128,7 +128,7 @@ st_texture_match_image(const struct pipe_texture *pt, /* Check if this image's format matches the established texture's format. */ - if (st_mesa_format_to_pipe_format(image->TexFormat->MesaFormat) != pt->format) + if (st_mesa_format_to_pipe_format(image->TexFormat) != pt->format) return GL_FALSE; /* Test if this image's size matches what's expected in the diff --git a/src/mesa/swrast/s_texfilter.c b/src/mesa/swrast/s_texfilter.c index 004d4e05ae..11c8f9256a 100644 --- a/src/mesa/swrast/s_texfilter.c +++ b/src/mesa/swrast/s_texfilter.c @@ -745,7 +745,7 @@ get_border_color(const struct gl_texture_object *tObj, const struct gl_texture_image *img, GLfloat rgba[4]) { - switch (img->TexFormat->BaseFormat) { + switch (img->_BaseFormat) { case GL_RGB: rgba[0] = tObj->BorderColor[0]; rgba[1] = tObj->BorderColor[1]; @@ -1152,7 +1152,7 @@ sample_2d_linear_repeat(GLcontext *ctx, ASSERT(tObj->WrapS == GL_REPEAT); ASSERT(tObj->WrapT == GL_REPEAT); ASSERT(img->Border == 0); - ASSERT(img->TexFormat->BaseFormat != GL_COLOR_INDEX); + ASSERT(img->_BaseFormat != GL_COLOR_INDEX); ASSERT(img->_IsPowerOfTwo); linear_repeat_texel_location(width, texcoord[0], &i0, &i1, &wi); @@ -1343,7 +1343,7 @@ opt_sample_rgb_2d(GLcontext *ctx, ASSERT(tObj->WrapS==GL_REPEAT); ASSERT(tObj->WrapT==GL_REPEAT); ASSERT(img->Border==0); - ASSERT(img->TexFormat->MesaFormat==MESA_FORMAT_RGB); + ASSERT(img->TexFormat == MESA_FORMAT_RGB); ASSERT(img->_IsPowerOfTwo); for (k=0; kWrapS==GL_REPEAT); ASSERT(tObj->WrapT==GL_REPEAT); ASSERT(img->Border==0); - ASSERT(img->TexFormat->MesaFormat==MESA_FORMAT_RGBA); + ASSERT(img->TexFormat == MESA_FORMAT_RGBA); ASSERT(img->_IsPowerOfTwo); for (i = 0; i < n; i++) { @@ -1414,7 +1414,7 @@ sample_lambda_2d(GLcontext *ctx, const GLboolean repeatNoBorderPOT = (tObj->WrapS == GL_REPEAT) && (tObj->WrapT == GL_REPEAT) && (tImg->Border == 0 && (tImg->Width == tImg->RowStride)) - && (tImg->TexFormat->BaseFormat != GL_COLOR_INDEX) + && (tImg->_BaseFormat != GL_COLOR_INDEX) && tImg->_IsPowerOfTwo; ASSERT(lambda != NULL); @@ -1427,7 +1427,7 @@ sample_lambda_2d(GLcontext *ctx, switch (tObj->MinFilter) { case GL_NEAREST: if (repeatNoBorderPOT) { - switch (tImg->TexFormat->MesaFormat) { + switch (tImg->TexFormat) { case MESA_FORMAT_RGB: opt_sample_rgb_2d(ctx, tObj, m, texcoords + minStart, NULL, rgba + minStart); @@ -1484,7 +1484,7 @@ sample_lambda_2d(GLcontext *ctx, switch (tObj->MagFilter) { case GL_NEAREST: if (repeatNoBorderPOT) { - switch (tImg->TexFormat->MesaFormat) { + switch (tImg->TexFormat) { case MESA_FORMAT_RGB: opt_sample_rgb_2d(ctx, tObj, m, texcoords + magStart, NULL, rgba + magStart); @@ -2152,7 +2152,7 @@ sample_nearest_rect(GLcontext *ctx, ASSERT(tObj->WrapT == GL_CLAMP || tObj->WrapT == GL_CLAMP_TO_EDGE || tObj->WrapT == GL_CLAMP_TO_BORDER); - ASSERT(img->TexFormat->BaseFormat != GL_COLOR_INDEX); + ASSERT(img->_BaseFormat != GL_COLOR_INDEX); for (i = 0; i < n; i++) { GLint row, col; @@ -2186,7 +2186,7 @@ sample_linear_rect(GLcontext *ctx, ASSERT(tObj->WrapT == GL_CLAMP || tObj->WrapT == GL_CLAMP_TO_EDGE || tObj->WrapT == GL_CLAMP_TO_BORDER); - ASSERT(img->TexFormat->BaseFormat != GL_COLOR_INDEX); + ASSERT(img->_BaseFormat != GL_COLOR_INDEX); for (i = 0; i < n; i++) { GLint i0, j0, i1, j1; @@ -2973,8 +2973,8 @@ sample_depth_texture( GLcontext *ctx, (void) lambda; - ASSERT(img->TexFormat->BaseFormat == GL_DEPTH_COMPONENT || - img->TexFormat->BaseFormat == GL_DEPTH_STENCIL_EXT); + ASSERT(img->_BaseFormat == GL_DEPTH_COMPONENT || + img->_BaseFormat == GL_DEPTH_STENCIL_EXT); ASSERT(tObj->Target == GL_TEXTURE_1D || tObj->Target == GL_TEXTURE_2D || @@ -3154,7 +3154,7 @@ _swrast_choose_texture_sample_func( GLcontext *ctx, } else { const GLboolean needLambda = (GLboolean) (t->MinFilter != t->MagFilter); - const GLenum format = t->Image[0][t->BaseLevel]->TexFormat->BaseFormat; + const GLenum format = t->Image[0][t->BaseLevel]->_BaseFormat; switch (t->Target) { case GL_TEXTURE_1D: @@ -3189,14 +3189,14 @@ _swrast_choose_texture_sample_func( GLcontext *ctx, t->WrapT == GL_REPEAT && img->_IsPowerOfTwo && img->Border == 0 && - img->TexFormat->MesaFormat == MESA_FORMAT_RGB) { + img->TexFormat == MESA_FORMAT_RGB) { return &opt_sample_rgb_2d; } else if (t->WrapS == GL_REPEAT && t->WrapT == GL_REPEAT && img->_IsPowerOfTwo && img->Border == 0 && - img->TexFormat->MesaFormat == MESA_FORMAT_RGBA) { + img->TexFormat == MESA_FORMAT_RGBA) { return &opt_sample_rgba_2d; } else { diff --git a/src/mesa/swrast/s_triangle.c b/src/mesa/swrast/s_triangle.c index 1ab0e19f92..7b59763f11 100644 --- a/src/mesa/swrast/s_triangle.c +++ b/src/mesa/swrast/s_triangle.c @@ -1055,11 +1055,11 @@ _swrast_choose_triangle( GLcontext *ctx ) const struct gl_texture_object *texObj2D; const struct gl_texture_image *texImg; GLenum minFilter, magFilter, envMode; - GLint format; + gl_format format; texObj2D = ctx->Texture.Unit[0].CurrentTex[TEXTURE_2D_INDEX]; texImg = texObj2D ? texObj2D->Image[0][texObj2D->BaseLevel] : NULL; - format = texImg ? texImg->TexFormat->MesaFormat : -1; + format = texImg ? texImg->TexFormat : -1; minFilter = texObj2D ? texObj2D->MinFilter : (GLenum) 0; magFilter = texObj2D ? texObj2D->MagFilter : (GLenum) 0; envMode = ctx->Texture.Unit[0].EnvMode; -- cgit v1.2.3 From 3f623cfffee8db83ba8e0302fc5e3d1f40d1b0b5 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 2 Oct 2009 14:25:52 -0400 Subject: r600: remove support for host-based ibs no longer used now that the hw supports this natively. Also, clean up some formatting. --- src/mesa/drivers/dri/r600/r600_context.h | 26 ++-- src/mesa/drivers/dri/r600/r700_render.c | 204 +++++++++++-------------------- 2 files changed, 80 insertions(+), 150 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index a296ea23fa..7f68820fda 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -126,32 +126,30 @@ struct r600_hw_state { struct radeon_state_atom tx_brdr_clr; }; -typedef struct StreamDesc +typedef struct StreamDesc { GLint size; //number of data element GLenum type; //data element type GLsizei stride; - struct radeon_bo *bo; - GLint bo_offset; + struct radeon_bo *bo; + GLint bo_offset; - GLuint dwords; + GLuint dwords; GLuint dst_loc; GLuint _signed; GLboolean normalize; - GLboolean is_named_bo; - GLubyte element; + GLboolean is_named_bo; + GLubyte element; } StreamDesc; -typedef struct r700_index_buffer +typedef struct r700_index_buffer { - struct radeon_bo *bo; - int bo_offset; + struct radeon_bo *bo; + int bo_offset; - GLboolean is_32bit; - GLuint count; - - GLboolean bHostIb; + GLboolean is_32bit; + GLuint count; } r700_index_buffer; /** @@ -172,7 +170,7 @@ struct r600_context { GLvector4f dummy_attrib[_TNL_ATTRIB_MAX]; GLvector4f *temp_attrib[_TNL_ATTRIB_MAX]; - GLint nNumActiveAos; + GLint nNumActiveAos; StreamDesc stream_desc[VERT_ATTRIB_MAX]; struct r700_index_buffer ind_buf; }; diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 4949bf013d..0aef0b7ea1 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -251,19 +251,19 @@ static int r700NumVerts(int num_verts, int prim) static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim) { - context_t *context = R700_CONTEXT(ctx); - BATCH_LOCALS(&context->radeon); - int type, i, total_emit; - int num_indices; - uint32_t vgt_draw_initiator = 0; - uint32_t vgt_index_type = 0; - uint32_t vgt_primitive_type = 0; - uint32_t vgt_num_indices = 0; - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *vb = &tnl->vb; - + context_t *context = R700_CONTEXT(ctx); + BATCH_LOCALS(&context->radeon); + int type, i, total_emit; + int num_indices; + uint32_t vgt_draw_initiator = 0; + uint32_t vgt_index_type = 0; + uint32_t vgt_primitive_type = 0; + uint32_t vgt_num_indices = 0; + TNLcontext *tnl = TNL_CONTEXT(ctx); + struct vertex_buffer *vb = &tnl->vb; GLboolean bUseDrawIndex; - if( (NULL != context->ind_buf.bo) && (GL_TRUE != context->ind_buf.bHostIb) ) + + if(NULL != context->ind_buf.bo) { bUseDrawIndex = GL_TRUE; } @@ -272,35 +272,35 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim bUseDrawIndex = GL_FALSE; } - type = r700PrimitiveType(prim); - num_indices = r700NumVerts(end - start, prim); + type = r700PrimitiveType(prim); + num_indices = r700NumVerts(end - start, prim); - radeon_print(RADEON_RENDER, RADEON_TRACE, - "%s type %x num_indices %d\n", - __func__, type, num_indices); + radeon_print(RADEON_RENDER, RADEON_TRACE, + "%s type %x num_indices %d\n", + __func__, type, num_indices); - if (type < 0 || num_indices <= 0) - return; + if (type < 0 || num_indices <= 0) + return; if(GL_TRUE == bUseDrawIndex) { total_emit = 3 /* VGT_PRIMITIVE_TYPE */ - + 2 /* VGT_INDEX_TYPE */ - + 2 /* NUM_INSTANCES */ - + 5+2; /* DRAW_INDEX */ + + 2 /* VGT_INDEX_TYPE */ + + 2 /* NUM_INSTANCES */ + + 5 + 2; /* DRAW_INDEX */ } else { total_emit = 3 /* VGT_PRIMITIVE_TYPE */ - + 2 /* VGT_INDEX_TYPE */ - + 2 /* NUM_INSTANCES */ - + num_indices + 3; /* DRAW_INDEX_IMMD */ + + 2 /* VGT_INDEX_TYPE */ + + 2 /* NUM_INSTANCES */ + + num_indices + 3; /* DRAW_INDEX_IMMD */ } BEGIN_BATCH_NO_AUTOSTATE(total_emit); - // prim + // prim SETfield(vgt_primitive_type, type, - VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask); + VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask); R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); R600_OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); R600_OUT_BATCH(vgt_primitive_type); @@ -319,11 +319,11 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); R600_OUT_BATCH(vgt_index_type); - // num instances - R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0)); - R600_OUT_BATCH(1); + // num instances + R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0)); + R600_OUT_BATCH(1); - // draw packet + // draw packet vgt_num_indices = num_indices; if(GL_TRUE == bUseDrawIndex) @@ -354,44 +354,17 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (num_indices + 1))); R600_OUT_BATCH(vgt_num_indices); R600_OUT_BATCH(vgt_draw_initiator); - } - if(NULL == context->ind_buf.bo) - { - for (i = start; i < (start + num_indices); i++) { + for (i = start; i < (start + num_indices); i++) + { if(vb->Elts) { R600_OUT_BATCH(vb->Elts[i]); } else + { R600_OUT_BATCH(i); - } - } - else - { - if(GL_TRUE == context->ind_buf.bHostIb) - { - if(GL_TRUE != context->ind_buf.is_32bit) - { - GLushort * pIndex = (GLushort*)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset); - pIndex += start; - for (i = 0; i < num_indices; i++) - { - R600_OUT_BATCH(*pIndex); - pIndex++; - } - } - else - { - GLuint * pIndex = (GLuint*)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset); - pIndex += start; - - for (i = 0; i < num_indices; i++) - { - R600_OUT_BATCH(*pIndex); - pIndex++; - } - } + } } } @@ -826,30 +799,21 @@ static void r700FreeData(GLcontext *ctx) * called during context destroy */ context_t *context = R700_CONTEXT(ctx); - + int i; - for (i = 0; i < context->nNumActiveAos; i++) + for (i = 0; i < context->nNumActiveAos; i++) { - if (!context->stream_desc[i].is_named_bo) + if (!context->stream_desc[i].is_named_bo) { radeon_bo_unref(context->stream_desc[i].bo); } context->radeon.tcl.aos[i].bo = NULL; } - - if (context->ind_buf.bo != NULL) + + if (context->ind_buf.bo != NULL) { - if(context->ind_buf.bHostIb != GL_TRUE) - { radeon_bo_unref(context->ind_buf.bo); - } - else - { - FREE(context->ind_buf.bo->ptr); - FREE(context->ind_buf.bo); - context->ind_buf.bo = NULL; - } } } @@ -861,7 +825,7 @@ static void r700FixupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer int i; GLboolean mapped_named_bo = GL_FALSE; - if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer) + if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer) { ctx->Driver.MapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, GL_READ_ONLY_ARB, mesa_ind_buf->obj); mapped_named_bo = GL_TRUE; @@ -869,66 +833,46 @@ static void r700FixupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer } src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr); - if (mesa_ind_buf->type == GL_UNSIGNED_BYTE) + if (mesa_ind_buf->type == GL_UNSIGNED_BYTE) { GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1); GLubyte *in = (GLubyte *)src_ptr; - if(context->ind_buf.bHostIb != GL_TRUE) - { - radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo, - &context->ind_buf.bo_offset, size, 4); + radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo, + &context->ind_buf.bo_offset, size, 4); - assert(context->ind_buf.bo->ptr != NULL); - out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset); - } - else - { - context->ind_buf.bo = MALLOC_STRUCT(radeon_bo); - context->ind_buf.bo->ptr = ALIGN_MALLOC(size, 4); - context->ind_buf.bo_offset = 0; - out = (GLuint *)context->ind_buf.bo->ptr; - } + assert(context->ind_buf.bo->ptr != NULL); + out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset); - for (i = 0; i + 1 < mesa_ind_buf->count; i += 2) + for (i = 0; i + 1 < mesa_ind_buf->count; i += 2) { *out++ = in[i] | in[i + 1] << 16; } - if (i < mesa_ind_buf->count) + if (i < mesa_ind_buf->count) { *out++ = in[i]; } #if MESA_BIG_ENDIAN - } - else + } + else { /* if (mesa_ind_buf->type == GL_UNSIGNED_SHORT) */ GLushort *in = (GLushort *)src_ptr; GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1); - if(context->ind_buf.bHostIb != GL_TRUE) - { - radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo, - &context->ind_buf.bo_offset, size, 4); + radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo, + &context->ind_buf.bo_offset, size, 4); - assert(context->ind_buf.bo->ptr != NULL); - out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset); - } - else - { - context->ind_buf.bo = MALLOC_STRUCT(radeon_bo); - context->ind_buf.bo->ptr = ALIGN_MALLOC(size, 4); - context->ind_buf.bo_offset = 0; - out = (GLuint *)context->ind_buf.bo->ptr; - } + assert(context->ind_buf.bo->ptr != NULL); + out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset); - for (i = 0; i + 1 < mesa_ind_buf->count; i += 2) + for (i = 0; i + 1 < mesa_ind_buf->count; i += 2) { *out++ = in[i] | in[i + 1] << 16; } - if (i < mesa_ind_buf->count) + if (i < mesa_ind_buf->count) { *out++ = in[i]; } @@ -938,7 +882,7 @@ static void r700FixupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer context->ind_buf.is_32bit = GL_FALSE; context->ind_buf.count = mesa_ind_buf->count; - if (mapped_named_bo) + if (mapped_named_bo) { ctx->Driver.UnmapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, mesa_ind_buf->obj); } @@ -953,20 +897,18 @@ static void r700SetupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer return; } - context->ind_buf.bHostIb = GL_FALSE; - #if MESA_BIG_ENDIAN - if (mesa_ind_buf->type == GL_UNSIGNED_INT) + if (mesa_ind_buf->type == GL_UNSIGNED_INT) { #else - if (mesa_ind_buf->type != GL_UNSIGNED_BYTE) + if (mesa_ind_buf->type != GL_UNSIGNED_BYTE) { #endif const GLvoid *src_ptr; GLvoid *dst_ptr; GLboolean mapped_named_bo = GL_FALSE; - if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer) + if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer) { ctx->Driver.MapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, GL_READ_ONLY_ARB, mesa_ind_buf->obj); assert(mesa_ind_buf->obj->Pointer != NULL); @@ -977,32 +919,22 @@ static void r700SetupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer const GLuint size = mesa_ind_buf->count * getTypeSize(mesa_ind_buf->type); - if(context->ind_buf.bHostIb != GL_TRUE) - { - radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo, - &context->ind_buf.bo_offset, size, 4); - assert(context->ind_buf.bo->ptr != NULL); - dst_ptr = ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset); - } - else - { - context->ind_buf.bo = MALLOC_STRUCT(radeon_bo); - context->ind_buf.bo->ptr = ALIGN_MALLOC(size, 4); - context->ind_buf.bo_offset = 0; - dst_ptr = context->ind_buf.bo->ptr; - } + radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo, + &context->ind_buf.bo_offset, size, 4); + assert(context->ind_buf.bo->ptr != NULL); + dst_ptr = ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset); _mesa_memcpy(dst_ptr, src_ptr, size); context->ind_buf.is_32bit = (mesa_ind_buf->type == GL_UNSIGNED_INT); context->ind_buf.count = mesa_ind_buf->count; - if (mapped_named_bo) + if (mapped_named_bo) { ctx->Driver.UnmapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER, mesa_ind_buf->obj); } - } - else + } + else { r700FixupIndexBuffer(ctx, mesa_ind_buf); } @@ -1145,7 +1077,7 @@ static void r700DrawPrims(GLcontext *ctx, void r700InitDraw(GLcontext *ctx) { struct vbo_context *vbo = vbo_context(ctx); - + /* to be enabled */ vbo->draw_prims = r700DrawPrims; } -- cgit v1.2.3 From 0b032eabc77d0e28fc0746cbd8ffb94859fd130d Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 5 Oct 2009 12:53:40 +0300 Subject: r600: update vertex program selection for draw path --- src/mesa/drivers/dri/r600/r700_vertprog.c | 40 +++++++++++++++++++++++++++---- 1 file changed, 35 insertions(+), 5 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index e7a209be9d..d12c39c9f7 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -319,8 +319,10 @@ struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, _mesa_insert_mvp_code(ctx, vp->mesa_program); } - for(i=0; imesa_program->Base.InputsRead & unBit) /* ctx->Array.ArrayObj->xxxxxxx */ { @@ -328,7 +330,17 @@ struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, vp->aos_desc[i].stride = vb->AttribPtr[i]->size * sizeof(GL_FLOAT);/* when emit array, data is packed. vb->AttribPtr[i]->stride;*/ vp->aos_desc[i].type = GL_FLOAT; } + } } + else + { + for(i=0; inNumActiveAos; i++) + { + vp->aos_desc[i].size = context->stream_desc[i].size; + vp->aos_desc[i].stride = context->stream_desc[i].stride; + vp->aos_desc[i].type = context->stream_desc[i].type; + } + } if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) { @@ -388,17 +400,35 @@ void r700SelectVertexShader(GLcontext *ctx, GLint nVersion) for (vp = vpc->progs; vp; vp = vp->next) { + if (vp->uiVersion != nVersion ) + continue; match = GL_TRUE; - for(i=0; iaos_desc[i].size != vb->AttribPtr[i]->size) - match = GL_FALSE; - break; + if (vp->aos_desc[i].size != vb->AttribPtr[i]->size) + { + match = GL_FALSE; + break; + } } + } } + else + { + for(i=0; inNumActiveAos; i++) + { + if (vp->aos_desc[i].size != context->stream_desc[i].size) + { + match = GL_FALSE; + break; + } + } + } if (match) { context->selected_vp = vp; -- cgit v1.2.3 From 3e34a2a2b97e7c93955deedb7c12b73bccd6662d Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Mon, 5 Oct 2009 18:11:35 -0600 Subject: drivers: don't include texformat.h And remove other unneeded #includes while we're at it. --- src/mesa/drivers/dri/gamma/gamma_tex.c | 13 +++++-------- src/mesa/drivers/dri/i810/i810tex.c | 1 - src/mesa/drivers/dri/i810/i810texmem.c | 1 - src/mesa/drivers/dri/i810/i810texstate.c | 1 - src/mesa/drivers/dri/i915/i830_texblend.c | 1 - src/mesa/drivers/dri/i915/i830_texstate.c | 1 - src/mesa/drivers/dri/i915/i830_vtbl.c | 1 - src/mesa/drivers/dri/i915/i915_texstate.c | 1 - src/mesa/drivers/dri/i915/i915_vtbl.c | 1 - src/mesa/drivers/dri/i965/brw_vs_surface_state.c | 1 - src/mesa/drivers/dri/i965/brw_wm.c | 1 - src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 1 - src/mesa/drivers/dri/intel/intel_blit.c | 1 - src/mesa/drivers/dri/intel/intel_fbo.c | 1 - src/mesa/drivers/dri/intel/intel_span.c | 1 - src/mesa/drivers/dri/intel/intel_tex_format.c | 1 - src/mesa/drivers/dri/intel/intel_tex_image.c | 1 - src/mesa/drivers/dri/mach64/mach64_tex.c | 1 - src/mesa/drivers/dri/mach64/mach64_texmem.c | 11 +++++------ src/mesa/drivers/dri/mach64/mach64_texstate.c | 1 - src/mesa/drivers/dri/mga/mga_texstate.c | 15 ++++++--------- src/mesa/drivers/dri/mga/mgatex.c | 13 ++++++------- src/mesa/drivers/dri/r128/r128_tex.c | 1 - src/mesa/drivers/dri/r128/r128_texmem.c | 1 - src/mesa/drivers/dri/r128/r128_texstate.c | 1 - src/mesa/drivers/dri/r200/r200_tex.c | 1 - src/mesa/drivers/dri/r200/r200_texstate.c | 1 - src/mesa/drivers/dri/r300/r300_state.c | 1 - src/mesa/drivers/dri/r300/r300_tex.c | 1 - src/mesa/drivers/dri/r300/r300_texstate.c | 1 - src/mesa/drivers/dri/r600/r600_tex.c | 1 - src/mesa/drivers/dri/r600/r600_texstate.c | 1 - src/mesa/drivers/dri/r600/r700_state.c | 1 - src/mesa/drivers/dri/radeon/radeon_fbo.c | 1 - src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 1 - src/mesa/drivers/dri/radeon/radeon_tex.c | 1 - src/mesa/drivers/dri/radeon/radeon_texstate.c | 1 - src/mesa/drivers/dri/radeon/radeon_texture.c | 1 - src/mesa/drivers/dri/s3v/s3v_tex.c | 4 ---- src/mesa/drivers/dri/savage/savage_xmesa.c | 2 +- src/mesa/drivers/dri/savage/savagetex.c | 23 +++++++++-------------- src/mesa/drivers/dri/sis/sis_tex.c | 8 +++----- src/mesa/drivers/dri/sis/sis_texstate.c | 1 - src/mesa/drivers/dri/tdfx/tdfx_state.c | 1 - src/mesa/drivers/dri/tdfx/tdfx_tex.c | 1 - src/mesa/drivers/dri/unichrome/via_tex.c | 3 +-- 46 files changed, 36 insertions(+), 93 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/gamma/gamma_tex.c b/src/mesa/drivers/dri/gamma/gamma_tex.c index 97797d4788..0dad250e4d 100644 --- a/src/mesa/drivers/dri/gamma/gamma_tex.c +++ b/src/mesa/drivers/dri/gamma/gamma_tex.c @@ -1,21 +1,18 @@ -#include -#include - #include "main/glheader.h" #include "main/mtypes.h" +#include "main/colormac.h" #include "main/imports.h" #include "main/simple_list.h" #include "main/enums.h" +#include "main/mm.h" #include "main/texstore.h" -#include "teximage.h" -#include "main/texformat.h" -#include "texobj.h" +#include "main/teximage.h" +#include "main/texobj.h" + #include "swrast/swrast.h" -#include "main/mm.h" #include "gammacontext.h" -#include "colormac.h" /* diff --git a/src/mesa/drivers/dri/i810/i810tex.c b/src/mesa/drivers/dri/i810/i810tex.c index 8166393eb1..2f6978f5aa 100644 --- a/src/mesa/drivers/dri/i810/i810tex.c +++ b/src/mesa/drivers/dri/i810/i810tex.c @@ -28,7 +28,6 @@ #include "main/simple_list.h" #include "main/enums.h" #include "main/texstore.h" -#include "main/texformat.h" #include "main/teximage.h" #include "main/texobj.h" #include "main/colormac.h" diff --git a/src/mesa/drivers/dri/i810/i810texmem.c b/src/mesa/drivers/dri/i810/i810texmem.c index c2a5d95fc7..d93afbf9ef 100644 --- a/src/mesa/drivers/dri/i810/i810texmem.c +++ b/src/mesa/drivers/dri/i810/i810texmem.c @@ -30,7 +30,6 @@ #include "main/enums.h" #include "main/colormac.h" #include "main/mm.h" -#include "main/texformat.h" #include "i810screen.h" #include "i810_dri.h" diff --git a/src/mesa/drivers/dri/i810/i810texstate.c b/src/mesa/drivers/dri/i810/i810texstate.c index b873ddbecb..bff28c11c8 100644 --- a/src/mesa/drivers/dri/i810/i810texstate.c +++ b/src/mesa/drivers/dri/i810/i810texstate.c @@ -25,7 +25,6 @@ #include "main/glheader.h" #include "main/macros.h" #include "main/mtypes.h" -#include "main/texformat.h" #include "main/simple_list.h" #include "main/enums.h" #include "main/mm.h" diff --git a/src/mesa/drivers/dri/i915/i830_texblend.c b/src/mesa/drivers/dri/i915/i830_texblend.c index 09f7f37e76..3f64be8c96 100644 --- a/src/mesa/drivers/dri/i915/i830_texblend.c +++ b/src/mesa/drivers/dri/i915/i830_texblend.c @@ -30,7 +30,6 @@ #include "main/mtypes.h" #include "main/simple_list.h" #include "main/enums.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/mm.h" diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c index 837ae57074..98fb853c68 100644 --- a/src/mesa/drivers/dri/i915/i830_texstate.c +++ b/src/mesa/drivers/dri/i915/i830_texstate.c @@ -27,7 +27,6 @@ #include "main/mtypes.h" #include "main/enums.h" -#include "main/texformat.h" #include "intel_mipmap_tree.h" #include "intel_tex.h" diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c index d53900b329..22f8bc7f19 100644 --- a/src/mesa/drivers/dri/i915/i830_vtbl.c +++ b/src/mesa/drivers/dri/i915/i830_vtbl.c @@ -26,7 +26,6 @@ **************************************************************************/ #include "glapi/glapi.h" -#include "main/texformat.h" #include "i830_context.h" #include "i830_reg.h" diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index d6f6cfdb49..03ed8a6311 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -27,7 +27,6 @@ #include "main/mtypes.h" #include "main/enums.h" -#include "main/texformat.h" #include "intel_mipmap_tree.h" #include "intel_tex.h" diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index 1c3da63da9..a4b00b06e7 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -32,7 +32,6 @@ #include "main/imports.h" #include "main/macros.h" #include "main/colormac.h" -#include "main/texformat.h" #include "tnl/t_context.h" #include "tnl/t_vertex.h" diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c index 89f47522a1..4fa3269bed 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c @@ -30,7 +30,6 @@ */ #include "main/mtypes.h" -#include "main/texformat.h" #include "main/texstore.h" #include "shader/prog_parameter.h" diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 46df778bee..5a2ac1a651 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -29,7 +29,6 @@ * Keith Whitwell */ -#include "main/texformat.h" #include "brw_context.h" #include "brw_util.h" #include "brw_wm.h" diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 855fe7593d..ea559d2ac7 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -31,7 +31,6 @@ #include "main/mtypes.h" -#include "main/texformat.h" #include "main/texstore.h" #include "shader/prog_parameter.h" diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index 799b22cc90..0158bd309f 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -29,7 +29,6 @@ #include "main/mtypes.h" #include "main/context.h" #include "main/enums.h" -#include "main/texformat.h" #include "main/colormac.h" #include "intel_blit.h" diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 1be381b9ea..3b4b90f2dc 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -33,7 +33,6 @@ #include "main/framebuffer.h" #include "main/renderbuffer.h" #include "main/context.h" -#include "main/texformat.h" #include "main/texrender.h" #include "drivers/common/meta.h" diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index f754ce0cd1..5bbcce6fe4 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -29,7 +29,6 @@ #include "main/macros.h" #include "main/mtypes.h" #include "main/colormac.h" -#include "main/texformat.h" #include "intel_buffers.h" #include "intel_fbo.h" diff --git a/src/mesa/drivers/dri/intel/intel_tex_format.c b/src/mesa/drivers/dri/intel/intel_tex_format.c index 22c010bbd7..eca0f6d572 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_format.c +++ b/src/mesa/drivers/dri/intel/intel_tex_format.c @@ -1,7 +1,6 @@ #include "intel_context.h" #include "intel_tex.h" #include "intel_chipset.h" -#include "main/texformat.h" #include "main/enums.h" diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c index f32ff0dd05..b159010b8e 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_image.c +++ b/src/mesa/drivers/dri/intel/intel_tex_image.c @@ -7,7 +7,6 @@ #include "main/convolve.h" #include "main/context.h" #include "main/texcompress.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/texgetimage.h" #include "main/texobj.h" diff --git a/src/mesa/drivers/dri/mach64/mach64_tex.c b/src/mesa/drivers/dri/mach64/mach64_tex.c index 02433e5dd8..cce0e4d3ff 100644 --- a/src/mesa/drivers/dri/mach64/mach64_tex.c +++ b/src/mesa/drivers/dri/mach64/mach64_tex.c @@ -41,7 +41,6 @@ #include "main/simple_list.h" #include "main/enums.h" #include "main/texstore.h" -#include "main/texformat.h" #include "main/teximage.h" #include "main/texobj.h" #include "main/imports.h" diff --git a/src/mesa/drivers/dri/mach64/mach64_texmem.c b/src/mesa/drivers/dri/mach64/mach64_texmem.c index e83aeae3e1..b97e9eec25 100644 --- a/src/mesa/drivers/dri/mach64/mach64_texmem.c +++ b/src/mesa/drivers/dri/mach64/mach64_texmem.c @@ -31,6 +31,11 @@ * Jose Fonseca */ +#include "main/context.h" +#include "main/macros.h" +#include "main/simple_list.h" +#include "main/imports.h" + #include "mach64_context.h" #include "mach64_state.h" #include "mach64_ioctl.h" @@ -38,12 +43,6 @@ #include "mach64_tris.h" #include "mach64_tex.h" -#include "main/context.h" -#include "main/macros.h" -#include "main/simple_list.h" -#include "main/texformat.h" -#include "main/imports.h" - /* Destroy hardware state associated with texture `t'. */ diff --git a/src/mesa/drivers/dri/mach64/mach64_texstate.c b/src/mesa/drivers/dri/mach64/mach64_texstate.c index c333355324..df0a09a5c1 100644 --- a/src/mesa/drivers/dri/mach64/mach64_texstate.c +++ b/src/mesa/drivers/dri/mach64/mach64_texstate.c @@ -33,7 +33,6 @@ #include "main/imports.h" #include "main/context.h" #include "main/macros.h" -#include "main/texformat.h" #include "mach64_context.h" #include "mach64_ioctl.h" diff --git a/src/mesa/drivers/dri/mga/mga_texstate.c b/src/mesa/drivers/dri/mga/mga_texstate.c index d52f0fac75..54eda62a96 100644 --- a/src/mesa/drivers/dri/mga/mga_texstate.c +++ b/src/mesa/drivers/dri/mga/mga_texstate.c @@ -27,22 +27,19 @@ * Keith Whitwell */ -#include +#include "main/context.h" +#include "main/enums.h" +#include "main/macros.h" #include "main/mm.h" +#include "main/imports.h" +#include "main/simple_list.h" + #include "mgacontext.h" #include "mgatex.h" #include "mgaregs.h" #include "mgatris.h" #include "mgaioctl.h" -#include "main/context.h" -#include "main/enums.h" -#include "main/macros.h" -#include "main/imports.h" - -#include "main/simple_list.h" -#include "main/texformat.h" - #define MGA_USE_TABLE_FOR_FORMAT #ifdef MGA_USE_TABLE_FOR_FORMAT #define TMC_nr_tformat (MESA_FORMAT_YCBCR_REV + 1) diff --git a/src/mesa/drivers/dri/mga/mgatex.c b/src/mesa/drivers/dri/mga/mgatex.c index 71a8400e3b..9163371b33 100644 --- a/src/mesa/drivers/dri/mga/mgatex.c +++ b/src/mesa/drivers/dri/mga/mgatex.c @@ -27,23 +27,22 @@ #include "main/glheader.h" #include "main/mm.h" -#include "mgacontext.h" -#include "mgatex.h" -#include "mgaregs.h" -#include "mgatris.h" -#include "mgaioctl.h" - #include "main/colormac.h" #include "main/context.h" #include "main/enums.h" #include "main/simple_list.h" #include "main/imports.h" #include "main/macros.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/teximage.h" #include "main/texobj.h" +#include "mgacontext.h" +#include "mgatex.h" +#include "mgaregs.h" +#include "mgatris.h" +#include "mgaioctl.h" + #include "swrast/swrast.h" #include "xmlpool.h" diff --git a/src/mesa/drivers/dri/r128/r128_tex.c b/src/mesa/drivers/dri/r128/r128_tex.c index 6acda445f7..0a1207fb89 100644 --- a/src/mesa/drivers/dri/r128/r128_tex.c +++ b/src/mesa/drivers/dri/r128/r128_tex.c @@ -44,7 +44,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/simple_list.h" #include "main/enums.h" #include "main/texstore.h" -#include "main/texformat.h" #include "main/teximage.h" #include "main/texobj.h" #include "main/imports.h" diff --git a/src/mesa/drivers/dri/r128/r128_texmem.c b/src/mesa/drivers/dri/r128/r128_texmem.c index 84f8563b89..4ddcb86bcd 100644 --- a/src/mesa/drivers/dri/r128/r128_texmem.c +++ b/src/mesa/drivers/dri/r128/r128_texmem.c @@ -41,7 +41,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/context.h" #include "main/macros.h" #include "main/simple_list.h" -#include "main/texformat.h" #include "main/imports.h" #define TEX_0 1 diff --git a/src/mesa/drivers/dri/r128/r128_texstate.c b/src/mesa/drivers/dri/r128/r128_texstate.c index 2e71c25861..cb2b5f9536 100644 --- a/src/mesa/drivers/dri/r128/r128_texstate.c +++ b/src/mesa/drivers/dri/r128/r128_texstate.c @@ -36,7 +36,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/imports.h" #include "main/context.h" #include "main/macros.h" -#include "main/texformat.h" #include "r128_context.h" #include "r128_state.h" diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c index 36d9e37d87..5a21a8b9c5 100644 --- a/src/mesa/drivers/dri/r200/r200_tex.c +++ b/src/mesa/drivers/dri/r200/r200_tex.c @@ -38,7 +38,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/enums.h" #include "main/image.h" #include "main/simple_list.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/teximage.h" #include "main/texobj.h" diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index 1a6fa9f548..20ec6fffaf 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -36,7 +36,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/imports.h" #include "main/context.h" #include "main/macros.h" -#include "main/texformat.h" #include "main/teximage.h" #include "main/texobj.h" #include "main/enums.h" diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 3060f49aaf..ac20c08e20 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -45,7 +45,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/framebuffer.h" #include "main/simple_list.h" #include "main/api_arrayelt.h" -#include "main/texformat.h" #include "swrast/swrast.h" #include "swrast_setup/swrast_setup.h" diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c index 10daeca9e6..27b78a912f 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.c +++ b/src/mesa/drivers/dri/r300/r300_tex.c @@ -40,7 +40,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/image.h" #include "main/mipmap.h" #include "main/simple_list.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/teximage.h" #include "main/texobj.h" diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index cb826248f3..1e9bd3e849 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -39,7 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/imports.h" #include "main/context.h" #include "main/macros.h" -#include "main/texformat.h" #include "main/teximage.h" #include "main/texobj.h" #include "main/enums.h" diff --git a/src/mesa/drivers/dri/r600/r600_tex.c b/src/mesa/drivers/dri/r600/r600_tex.c index 47081c968e..20965bb3c8 100644 --- a/src/mesa/drivers/dri/r600/r600_tex.c +++ b/src/mesa/drivers/dri/r600/r600_tex.c @@ -40,7 +40,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/image.h" #include "main/mipmap.h" #include "main/simple_list.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/teximage.h" #include "main/texobj.h" diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 55b455edc0..35186ef970 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -39,7 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/imports.h" #include "main/context.h" #include "main/macros.h" -#include "main/texformat.h" #include "main/teximage.h" #include "main/texobj.h" #include "main/enums.h" diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index fbff109455..65f83b8315 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -46,7 +46,6 @@ #include "shader/prog_parameter.h" #include "shader/prog_statevars.h" #include "vbo/vbo.h" -#include "main/texformat.h" #include "r600_context.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index 90ea2ec335..3f4f382d6c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -33,7 +33,6 @@ #include "main/framebuffer.h" #include "main/renderbuffer.h" #include "main/context.h" -#include "main/texformat.h" #include "main/texrender.h" #include "drivers/common/meta.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index 5429525587..86f596deb9 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -32,7 +32,6 @@ #include "main/simple_list.h" #include "main/texcompress.h" -#include "main/texformat.h" static GLuint radeon_compressed_texture_size(GLcontext *ctx, GLsizei width, GLsizei height, GLsizei depth, diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c index 99865fff27..60981aada2 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.c +++ b/src/mesa/drivers/dri/radeon/radeon_tex.c @@ -38,7 +38,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/enums.h" #include "main/image.h" #include "main/simple_list.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/teximage.h" #include "main/texobj.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index cb17f48bf3..c7786381ae 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -38,7 +38,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/colormac.h" #include "main/context.h" #include "main/macros.h" -#include "main/texformat.h" #include "main/teximage.h" #include "main/texobj.h" #include "main/enums.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index 17e42e72ee..8e9276c5ae 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -34,7 +34,6 @@ #include "main/convolve.h" #include "main/mipmap.h" #include "main/texcompress.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/teximage.h" #include "main/texobj.h" diff --git a/src/mesa/drivers/dri/s3v/s3v_tex.c b/src/mesa/drivers/dri/s3v/s3v_tex.c index ec1182f34f..517f5e5ca7 100644 --- a/src/mesa/drivers/dri/s3v/s3v_tex.c +++ b/src/mesa/drivers/dri/s3v/s3v_tex.c @@ -2,16 +2,12 @@ * Author: Max Lingua */ -#include -#include - #include "main/glheader.h" #include "main/mtypes.h" #include "main/simple_list.h" #include "main/enums.h" #include "main/mm.h" #include "main/texstore.h" -#include "main/texformat.h" #include "main/teximage.h" #include "swrast/swrast.h" diff --git a/src/mesa/drivers/dri/savage/savage_xmesa.c b/src/mesa/drivers/dri/savage/savage_xmesa.c index 06179edae3..048fbe452c 100644 --- a/src/mesa/drivers/dri/savage/savage_xmesa.c +++ b/src/mesa/drivers/dri/savage/savage_xmesa.c @@ -574,7 +574,7 @@ savageDestroyContext(__DRIcontextPrivate *driContextPriv) _mesa_destroy_context(imesa->glCtx); /* no longer use vertex_dma_buf*/ - Xfree(imesa); + _mesa_free(imesa); } } diff --git a/src/mesa/drivers/dri/savage/savagetex.c b/src/mesa/drivers/dri/savage/savagetex.c index 796da4fc0d..6c97bb6c70 100644 --- a/src/mesa/drivers/dri/savage/savagetex.c +++ b/src/mesa/drivers/dri/savage/savagetex.c @@ -23,29 +23,24 @@ */ -#include -#include - -#include - +#include "main/context.h" #include "main/mm.h" -#include "savagecontext.h" -#include "savagetex.h" -#include "savagetris.h" -#include "savageioctl.h" -#include "main/simple_list.h" -#include "main/enums.h" -#include "savage_bci.h" - #include "main/macros.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/texobj.h" #include "main/convolve.h" #include "main/colormac.h" +#include "main/simple_list.h" +#include "main/enums.h" #include "swrast/swrast.h" +#include "savagecontext.h" +#include "savagetex.h" +#include "savagetris.h" +#include "savageioctl.h" +#include "savage_bci.h" + #include "xmlpool.h" #define TILE_INDEX_DXT1 0 diff --git a/src/mesa/drivers/dri/sis/sis_tex.c b/src/mesa/drivers/dri/sis/sis_tex.c index 5dc05146b1..951c470dad 100644 --- a/src/mesa/drivers/dri/sis/sis_tex.c +++ b/src/mesa/drivers/dri/sis/sis_tex.c @@ -28,17 +28,15 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * Eric Anholt */ -#include "sis_context.h" -#include "sis_alloc.h" -#include "sis_tex.h" - #include "swrast/swrast.h" #include "main/imports.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/teximage.h" #include "main/texobj.h" +#include "sis_context.h" +#include "sis_alloc.h" +#include "sis_tex.h" #include "xmlpool.h" #define ALIGN(value, align) (GLubyte *)((long)(value + align - 1) & ~(align - 1)) diff --git a/src/mesa/drivers/dri/sis/sis_texstate.c b/src/mesa/drivers/dri/sis/sis_texstate.c index 46417ce414..a507173b21 100644 --- a/src/mesa/drivers/dri/sis/sis_texstate.c +++ b/src/mesa/drivers/dri/sis/sis_texstate.c @@ -36,7 +36,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/colormac.h" #include "main/context.h" #include "main/macros.h" -#include "main/texformat.h" #include "sis_context.h" #include "sis_state.h" diff --git a/src/mesa/drivers/dri/tdfx/tdfx_state.c b/src/mesa/drivers/dri/tdfx/tdfx_state.c index 591df8a905..cf2712720f 100644 --- a/src/mesa/drivers/dri/tdfx/tdfx_state.c +++ b/src/mesa/drivers/dri/tdfx/tdfx_state.c @@ -40,7 +40,6 @@ #include "main/mtypes.h" #include "main/colormac.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/teximage.h" diff --git a/src/mesa/drivers/dri/tdfx/tdfx_tex.c b/src/mesa/drivers/dri/tdfx/tdfx_tex.c index 5e9421aa2a..0cd9051613 100644 --- a/src/mesa/drivers/dri/tdfx/tdfx_tex.c +++ b/src/mesa/drivers/dri/tdfx/tdfx_tex.c @@ -42,7 +42,6 @@ #include "main/image.h" #include "main/mipmap.h" #include "main/texcompress.h" -#include "main/texformat.h" #include "main/teximage.h" #include "main/texstore.h" #include "main/texobj.h" diff --git a/src/mesa/drivers/dri/unichrome/via_tex.c b/src/mesa/drivers/dri/unichrome/via_tex.c index fa7542c5cb..a72dcd6be2 100644 --- a/src/mesa/drivers/dri/unichrome/via_tex.c +++ b/src/mesa/drivers/dri/unichrome/via_tex.c @@ -35,13 +35,12 @@ #include "main/convolve.h" #include "main/context.h" #include "main/mipmap.h" +#include "main/mm.h" #include "main/simple_list.h" #include "main/texcompress.h" -#include "main/texformat.h" #include "main/texobj.h" #include "main/texstore.h" -#include "main/mm.h" #include "via_context.h" #include "via_fb.h" #include "via_tex.h" -- cgit v1.2.3 From ec58dac86d3068b47c5a4e0187ef56985dcbf75c Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 5 Oct 2009 09:38:52 +0300 Subject: r600: r700PredictRenderSize can flush, so move index buffer setup after it --- src/mesa/drivers/dri/r600/r700_render.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 0aef0b7ea1..4f39d9f1bd 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -960,7 +960,6 @@ static GLboolean r700TryDrawPrims(GLcontext *ctx, _tnl_UpdateFixedFunctionProgram(ctx); r700SetVertexFormat(ctx, arrays, max_index + 1); - r700SetupIndexBuffer(ctx, ib); /* shaders need to be updated before buffers are validated */ r700UpdateShaders2(ctx); if (!r600ValidateBuffers(ctx)) @@ -981,6 +980,7 @@ static GLboolean r700TryDrawPrims(GLcontext *ctx, GLuint emit_end = r700PredictRenderSize(ctx, nr_prims) + context->radeon.cmdbuf.cs->cdw; + r700SetupIndexBuffer(ctx, ib); r700SetupStreams2(ctx, arrays, max_index + 1); radeonEmitState(radeon); -- cgit v1.2.3 From 44c6c20b69839ea130a255496f5f692186b68793 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Fri, 9 Oct 2009 10:46:12 +0300 Subject: r600: fixup KIL instruction a bit - KILLGT takes 2 arguments - arb KIL has no dst register - add TODO about clause ending but currently piglit fp-kil passes and does not hang the card --- src/mesa/drivers/dri/r600/r700_assembler.c | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 903b6968be..fefae22ba7 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -336,7 +336,8 @@ unsigned int r700GetNumOperands(r700_AssemblerBase* pAsm) switch (pAsm->D.dst.opcode) { - case SQ_OP2_INST_ADD: + case SQ_OP2_INST_ADD: + case SQ_OP2_INST_KILLGT: case SQ_OP2_INST_MUL: case SQ_OP2_INST_MAX: case SQ_OP2_INST_MIN: @@ -356,7 +357,6 @@ unsigned int r700GetNumOperands(r700_AssemblerBase* pAsm) case SQ_OP2_INST_MOV: case SQ_OP2_INST_FRACT: case SQ_OP2_INST_FLOOR: - case SQ_OP2_INST_KILLGT: case SQ_OP2_INST_EXP_IEEE: case SQ_OP2_INST_LOG_CLAMPED: case SQ_OP2_INST_LOG_IEEE: @@ -2744,15 +2744,15 @@ GLboolean assemble_FRC(r700_AssemblerBase *pAsm) GLboolean assemble_KIL(r700_AssemblerBase *pAsm) { + /* TODO: doc says KILL has to be last(end) ALU clause */ + checkop1(pAsm); pAsm->D.dst.opcode = SQ_OP2_INST_KILLGT; - - if ( GL_FALSE == assemble_dst(pAsm) ) - { - return GL_FALSE; - } + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = 0; pAsm->D.dst.writex = 0; pAsm->D.dst.writey = 0; pAsm->D.dst.writez = 0; @@ -2765,20 +2765,11 @@ GLboolean assemble_KIL(r700_AssemblerBase *pAsm) setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_0); noneg_PVSSRC(&(pAsm->S[0].src)); - pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; - - if(PROGRAM_TEMPORARY == pAsm->pILInst[pAsm->uiCurInst].DstReg.File) + if ( GL_FALSE == assemble_src(pAsm, 0, 1) ) { - pAsm->S[1].src.reg = pAsm->pILInst[pAsm->uiCurInst].DstReg.Index + pAsm->starting_temp_register_number; - } - else - { //PROGRAM_OUTPUT - pAsm->S[1].src.reg = pAsm->uiFP_OutputMap[pAsm->pILInst[pAsm->uiCurInst].DstReg.Index]; + return GL_FALSE; } - setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); - noswizzle_PVSSRC(&(pAsm->S[1].src)); - if ( GL_FALSE == next_ins(pAsm) ) { return GL_FALSE; -- cgit v1.2.3 From 194ede4bf97547ce8a61587ede0b0a5054955783 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 9 Oct 2009 15:44:32 -0400 Subject: radeon: fix scissor regression fixes fdo bug 24248 --- src/mesa/drivers/dri/r600/r700_state.c | 10 +++++++--- src/mesa/drivers/dri/radeon/radeon_common.c | 9 ++++----- 2 files changed, 11 insertions(+), 8 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 124469b5a6..98f116d0a6 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -1269,11 +1269,15 @@ void r700SetScissor(context_t *context) //--------------- return; } if (context->radeon.state.scissor.enabled) { - /* r600 has exclusive scissors */ x1 = context->radeon.state.scissor.rect.x1; y1 = context->radeon.state.scissor.rect.y1; - x2 = context->radeon.state.scissor.rect.x2 + 1; - y2 = context->radeon.state.scissor.rect.y2 + 1; + x2 = context->radeon.state.scissor.rect.x2; + y2 = context->radeon.state.scissor.rect.y2; + /* r600 has exclusive BR scissors */ + if (context->radeon.radeonScreen->kernel_mm) { + x2++; + y2++; + } } else { if (context->radeon.radeonScreen->driScreen->dri2.enabled) { x1 = 0; diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 9817ff856b..8032cbcd69 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -229,16 +229,15 @@ void radeonUpdateScissor( GLcontext *ctx ) } if (!rmesa->radeonScreen->kernel_mm) { /* Fix scissors for dri 1 */ - __DRIdrawablePrivate *dPriv = radeon_get_drawable(rmesa); x1 += dPriv->x; - x2 += dPriv->x; + x2 += dPriv->x + 1; min_x += dPriv->x; - max_x += dPriv->x; + max_x += dPriv->x + 1; y1 += dPriv->y; - y2 += dPriv->y; + y2 += dPriv->y + 1; min_y += dPriv->y; - max_y += dPriv->y; + max_y += dPriv->y + 1; } rmesa->state.scissor.rect.x1 = CLAMP(x1, min_x, max_x); -- cgit v1.2.3 From 97dd35bd6f2e2654b96923fd06bf9761e7b2269d Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 12 Oct 2009 12:20:26 +0300 Subject: r600: DPH adds w comp of second operand, so set first one to 1 instead --- src/mesa/drivers/dri/r600/r700_assembler.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index fefae22ba7..a1331fdfd2 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -2635,7 +2635,7 @@ GLboolean assemble_DOT(r700_AssemblerBase *pAsm) } else if(pAsm->pILInst[pAsm->uiCurInst].Opcode == OPCODE_DPH) { - onecomp_PVSSRC(&(pAsm->S[1].src), 3); + onecomp_PVSSRC(&(pAsm->S[0].src), 3); } if ( GL_FALSE == next_ins(pAsm) ) -- cgit v1.2.3 From da66d9e12d339c5c6df08ea0bd11a550c9c57b36 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 12 Oct 2009 12:58:40 +0300 Subject: r600: LIT dst.y gets value from src.x seems I overlooked this when removing hardcoded swizzles for this one previously --- src/mesa/drivers/dri/r600/r700_assembler.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index a1331fdfd2..ed597c027b 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -3026,6 +3026,7 @@ GLboolean assemble_LIT(r700_AssemblerBase *pAsm) pAsm->S[0].src.rtype = srcType; pAsm->S[0].src.reg = srcReg; setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X, SQ_SEL_X, SQ_SEL_X, SQ_SEL_X); pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; pAsm->S[1].src.reg = tmp; setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); -- cgit v1.2.3 From 7a32c0a19e77e2e735f8d5cbc5b3bb9fda9606e5 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 12 Oct 2009 14:57:45 +0300 Subject: r600: implement ProgramStringNotify need this to properly test with piglit/glean vert/fragprog tests copied mostly from r300, many thanks to osiris, nha, airlied, others... --- src/mesa/drivers/dri/r600/r700_oglprog.c | 55 ++++++++++++++++++++++---------- 1 file changed, 38 insertions(+), 17 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_oglprog.c b/src/mesa/drivers/dri/r600/r700_oglprog.c index 5290ef31be..0d476fcd86 100644 --- a/src/mesa/drivers/dri/r600/r700_oglprog.c +++ b/src/mesa/drivers/dri/r600/r700_oglprog.c @@ -40,6 +40,24 @@ #include "r700_vertprog.h" +static void freeVertProgCache(GLcontext *ctx, struct r700_vertex_program_cont *cache) +{ + struct r700_vertex_program *tmp, *vp = cache->progs; + + while (vp) { + tmp = vp->next; + /* Release DMA region */ + r600DeleteShader(ctx, vp->shaderbo); + /* Clean up */ + Clean_Up_Assembler(&(vp->r700AsmCode)); + Clean_Up_Shader(&(vp->r700Shader)); + + _mesa_reference_vertprog(ctx, &vp->mesa_program, NULL); + _mesa_free(vp); + vp = tmp; + } +} + static struct gl_program *r700NewProgram(GLcontext * ctx, GLenum target, GLuint id) @@ -84,8 +102,7 @@ static struct gl_program *r700NewProgram(GLcontext * ctx, static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) { - struct r700_vertex_program_cont * vpc; - struct r700_vertex_program *vp, *tmp; + struct r700_vertex_program_cont *vpc = (struct r700_vertex_program_cont *)prog; struct r700_fragment_program * fp; radeon_print(RADEON_SHADER, RADEON_VERBOSE, @@ -95,20 +112,7 @@ static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) { case GL_VERTEX_STATE_PROGRAM_NV: case GL_VERTEX_PROGRAM_ARB: - vpc = (struct r700_vertex_program_cont*)prog; - vp = vpc->progs; - while (vp) { - tmp = vp->next; - /* Release DMA region */ - - r600DeleteShader(ctx, vp->shaderbo); - - /* Clean up */ - Clean_Up_Assembler(&(vp->r700AsmCode)); - Clean_Up_Shader(&(vp->r700Shader)); - _mesa_free(vp); - vp = tmp; - } + freeVertProgCache(ctx, vpc); break; case GL_FRAGMENT_PROGRAM_NV: case GL_FRAGMENT_PROGRAM_ARB: @@ -131,7 +135,24 @@ static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) static void r700ProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog) { - + struct r700_vertex_program_cont *vpc = (struct r700_vertex_program_cont *)prog; + struct r700_fragment_program * fp = (struct r700_fragment_program*)prog; + + switch (target) { + case GL_VERTEX_PROGRAM_ARB: + freeVertProgCache(ctx, vpc); + vpc->progs = NULL; + break; + case GL_FRAGMENT_PROGRAM_ARB: + r600DeleteShader(ctx, fp->shaderbo); + Clean_Up_Assembler(&(fp->r700AsmCode)); + Clean_Up_Shader(&(fp->r700Shader)); + fp->translated = GL_FALSE; + fp->loaded = GL_FALSE; + fp->shaderbo = NULL; + break; + } + } static GLboolean r700IsProgramNative(GLcontext * ctx, GLenum target, struct gl_program *prog) -- cgit v1.2.3 From f22c427bd685f55e6f7e29dcd72cdb1aa42f04d9 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 14 Oct 2009 14:18:36 -0400 Subject: r600: enable EXT_vertex_array_bgra extensions --- src/mesa/drivers/dri/r600/r600_context.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 969144ba12..ba0d450cbb 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -131,6 +131,7 @@ const struct dri_extension card_extensions[] = { {"GL_EXT_texture_lod_bias", NULL}, {"GL_EXT_texture_mirror_clamp", NULL}, {"GL_EXT_texture_rectangle", NULL}, + {"GL_EXT_vertex_array_bgra", NULL}, {"GL_EXT_texture_sRGB", NULL}, {"GL_ATI_separate_stencil", GL_ATI_separate_stencil_functions}, {"GL_ATI_texture_env_combine3", NULL}, -- cgit v1.2.3 From f7285bdffcd8cca1c7d3066d38907a5987e844ea Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Tue, 29 Sep 2009 09:46:29 +0300 Subject: r600: clear position enable bit when when wpos is not used by FP Makes doom3 alot nicer.. --- src/mesa/drivers/dri/r600/r700_fragprog.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index 78ce3ae436..62a1ea1a22 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -341,6 +341,11 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, POSITION_ENA_bit); SETbit(r700->SPI_INPUT_Z.u32All, PROVIDE_Z_TO_SPI_bit); } + else + { + CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, POSITION_ENA_bit); + CLEARbit(r700->SPI_INPUT_Z.u32All, PROVIDE_Z_TO_SPI_bit); + } ui = (unNumOfReg < ui) ? ui : unNumOfReg; -- cgit v1.2.3 From 5101215a64a69a212241eadba7f097cef33a0b5c Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 28 Sep 2009 10:42:35 +0300 Subject: r600: user correct alpha blend factor Signed-off-by: Dave Airlie --- src/mesa/drivers/dri/r600/r700_state.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 98f116d0a6..0d1f906d84 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -467,10 +467,10 @@ static void r700SetBlendState(GLcontext * ctx) eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask); SETfield(blend_reg, - blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE), + blend_factor(ctx->Color.BlendSrcA, GL_TRUE), ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask); SETfield(blend_reg, - blend_factor(ctx->Color.BlendDstRGB, GL_FALSE), + blend_factor(ctx->Color.BlendDstA, GL_FALSE), ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask); switch (ctx->Color.BlendEquationA) { -- cgit v1.2.3 From bf68e54a4d69bdd9a01656919d3cd752c96157b3 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 28 Sep 2009 11:23:49 +0300 Subject: r600: use CB_TARGET_MASK instead of CB_SHADER_MASK for setting color mask makes blend functions work better Signed-off-by: Dave Airlie --- src/mesa/drivers/dri/r600/r700_state.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 0d1f906d84..244a016e07 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -745,9 +745,9 @@ static void r700ColorMask(GLcontext * ctx, (b ? 4 : 0) | (a ? 8 : 0)); - if (mask != r700->CB_SHADER_MASK.u32All) { + if (mask != r700->CB_TARGET_MASK.u32All) { R600_STATECHANGE(context, cb); - SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask); + SETfield(r700->CB_TARGET_MASK.u32All, mask, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask); } } @@ -1758,7 +1758,7 @@ void r700InitState(GLcontext * ctx) //------------------- r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF; /* screen/window/view */ - SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask); + SETfield(r700->CB_SHADER_MASK.u32All, 0xF, (4 * id), OUTPUT0_ENABLE_mask); context->radeon.hw.all_dirty = GL_TRUE; -- cgit v1.2.3 From 95851d8cb232cbd1312d2b8de471ba2aeb276911 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Fri, 9 Oct 2009 10:46:12 +0300 Subject: r600: fixup KIL instruction a bit - KILLGT takes 2 arguments - arb KIL has no dst register - add TODO about clause ending but currently piglit fp-kil passes and does not hang the card --- src/mesa/drivers/dri/r600/r700_assembler.c | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 00eda544d4..e79c256c6b 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -336,7 +336,8 @@ unsigned int r700GetNumOperands(r700_AssemblerBase* pAsm) switch (pAsm->D.dst.opcode) { - case SQ_OP2_INST_ADD: + case SQ_OP2_INST_ADD: + case SQ_OP2_INST_KILLGT: case SQ_OP2_INST_MUL: case SQ_OP2_INST_MAX: case SQ_OP2_INST_MIN: @@ -356,7 +357,6 @@ unsigned int r700GetNumOperands(r700_AssemblerBase* pAsm) case SQ_OP2_INST_MOV: case SQ_OP2_INST_FRACT: case SQ_OP2_INST_FLOOR: - case SQ_OP2_INST_KILLGT: case SQ_OP2_INST_EXP_IEEE: case SQ_OP2_INST_LOG_CLAMPED: case SQ_OP2_INST_LOG_IEEE: @@ -2617,15 +2617,15 @@ GLboolean assemble_FRC(r700_AssemblerBase *pAsm) GLboolean assemble_KIL(r700_AssemblerBase *pAsm) { + /* TODO: doc says KILL has to be last(end) ALU clause */ + checkop1(pAsm); pAsm->D.dst.opcode = SQ_OP2_INST_KILLGT; - - if ( GL_FALSE == assemble_dst(pAsm) ) - { - return GL_FALSE; - } + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = 0; pAsm->D.dst.writex = 0; pAsm->D.dst.writey = 0; pAsm->D.dst.writez = 0; @@ -2638,20 +2638,11 @@ GLboolean assemble_KIL(r700_AssemblerBase *pAsm) setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_0); noneg_PVSSRC(&(pAsm->S[0].src)); - pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; - - if(PROGRAM_TEMPORARY == pAsm->pILInst[pAsm->uiCurInst].DstReg.File) + if ( GL_FALSE == assemble_src(pAsm, 0, 1) ) { - pAsm->S[1].src.reg = pAsm->pILInst[pAsm->uiCurInst].DstReg.Index + pAsm->starting_temp_register_number; - } - else - { //PROGRAM_OUTPUT - pAsm->S[1].src.reg = pAsm->uiFP_OutputMap[pAsm->pILInst[pAsm->uiCurInst].DstReg.Index]; + return GL_FALSE; } - setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); - noswizzle_PVSSRC(&(pAsm->S[1].src)); - if ( GL_FALSE == next_ins(pAsm) ) { return GL_FALSE; -- cgit v1.2.3 From 74c31e5d05f7ed342fb143cb6f637b54e8961973 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 12 Oct 2009 12:20:26 +0300 Subject: r600: DPH adds w comp of second operand, so set first one to 1 instead --- src/mesa/drivers/dri/r600/r700_assembler.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index e79c256c6b..1837712883 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -2508,7 +2508,7 @@ GLboolean assemble_DOT(r700_AssemblerBase *pAsm) } else if(pAsm->pILInst[pAsm->uiCurInst].Opcode == OPCODE_DPH) { - onecomp_PVSSRC(&(pAsm->S[1].src), 3); + onecomp_PVSSRC(&(pAsm->S[0].src), 3); } if ( GL_FALSE == next_ins(pAsm) ) -- cgit v1.2.3 From 606becc7f3513354548f587d84db731046616401 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 12 Oct 2009 12:58:40 +0300 Subject: r600: LIT dst.y gets value from src.x seems I overlooked this when removing hardcoded swizzles for this one previously --- src/mesa/drivers/dri/r600/r700_assembler.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 1837712883..25b27cd829 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -2899,6 +2899,7 @@ GLboolean assemble_LIT(r700_AssemblerBase *pAsm) pAsm->S[0].src.rtype = srcType; pAsm->S[0].src.reg = srcReg; setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X, SQ_SEL_X, SQ_SEL_X, SQ_SEL_X); pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; pAsm->S[1].src.reg = tmp; setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); -- cgit v1.2.3 From a3fec141017a39916d07000a3aa00eef3c9ac8a7 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 12 Oct 2009 14:57:45 +0300 Subject: r600: implement ProgramStringNotify need this to properly test with piglit/glean vert/fragprog tests copied mostly from r300, many thanks to osiris, nha, airlied, others... --- src/mesa/drivers/dri/r600/r700_oglprog.c | 55 ++++++++++++++++++++++---------- 1 file changed, 38 insertions(+), 17 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_oglprog.c b/src/mesa/drivers/dri/r600/r700_oglprog.c index 5290ef31be..0d476fcd86 100644 --- a/src/mesa/drivers/dri/r600/r700_oglprog.c +++ b/src/mesa/drivers/dri/r600/r700_oglprog.c @@ -40,6 +40,24 @@ #include "r700_vertprog.h" +static void freeVertProgCache(GLcontext *ctx, struct r700_vertex_program_cont *cache) +{ + struct r700_vertex_program *tmp, *vp = cache->progs; + + while (vp) { + tmp = vp->next; + /* Release DMA region */ + r600DeleteShader(ctx, vp->shaderbo); + /* Clean up */ + Clean_Up_Assembler(&(vp->r700AsmCode)); + Clean_Up_Shader(&(vp->r700Shader)); + + _mesa_reference_vertprog(ctx, &vp->mesa_program, NULL); + _mesa_free(vp); + vp = tmp; + } +} + static struct gl_program *r700NewProgram(GLcontext * ctx, GLenum target, GLuint id) @@ -84,8 +102,7 @@ static struct gl_program *r700NewProgram(GLcontext * ctx, static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) { - struct r700_vertex_program_cont * vpc; - struct r700_vertex_program *vp, *tmp; + struct r700_vertex_program_cont *vpc = (struct r700_vertex_program_cont *)prog; struct r700_fragment_program * fp; radeon_print(RADEON_SHADER, RADEON_VERBOSE, @@ -95,20 +112,7 @@ static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) { case GL_VERTEX_STATE_PROGRAM_NV: case GL_VERTEX_PROGRAM_ARB: - vpc = (struct r700_vertex_program_cont*)prog; - vp = vpc->progs; - while (vp) { - tmp = vp->next; - /* Release DMA region */ - - r600DeleteShader(ctx, vp->shaderbo); - - /* Clean up */ - Clean_Up_Assembler(&(vp->r700AsmCode)); - Clean_Up_Shader(&(vp->r700Shader)); - _mesa_free(vp); - vp = tmp; - } + freeVertProgCache(ctx, vpc); break; case GL_FRAGMENT_PROGRAM_NV: case GL_FRAGMENT_PROGRAM_ARB: @@ -131,7 +135,24 @@ static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) static void r700ProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog) { - + struct r700_vertex_program_cont *vpc = (struct r700_vertex_program_cont *)prog; + struct r700_fragment_program * fp = (struct r700_fragment_program*)prog; + + switch (target) { + case GL_VERTEX_PROGRAM_ARB: + freeVertProgCache(ctx, vpc); + vpc->progs = NULL; + break; + case GL_FRAGMENT_PROGRAM_ARB: + r600DeleteShader(ctx, fp->shaderbo); + Clean_Up_Assembler(&(fp->r700AsmCode)); + Clean_Up_Shader(&(fp->r700Shader)); + fp->translated = GL_FALSE; + fp->loaded = GL_FALSE; + fp->shaderbo = NULL; + break; + } + } static GLboolean r700IsProgramNative(GLcontext * ctx, GLenum target, struct gl_program *prog) -- cgit v1.2.3 From 22a0029a68cf6a17e5d799c7d8eb8a699ccdeabb Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Thu, 15 Oct 2009 11:24:49 -0400 Subject: r600: fix tfp1 bo size Setting the wrong bo size resulting in an incomplete read cache flush when reading the texture. This fixes the compiz text corruption. [agd5f: take hw pitch alignment into account] --- src/mesa/drivers/dri/r600/r600_texstate.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index bcb8d7c73d..61ff7e8158 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -721,7 +721,9 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname, struct gl_texture_object *tObj = _mesa_lookup_texture(rmesa->radeon.glCtx, texname); radeonTexObjPtr t = radeon_tex_obj(tObj); - uint32_t pitch_val, size; + int firstlevel = t->mt ? t->mt->firstLevel : 0; + const struct gl_texture_image *firstImage; + uint32_t pitch_val, size, row_align; if (!tObj) return; @@ -731,7 +733,9 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname, if (!offset) return; - size = pitch;//h * w * (depth / 8); + firstImage = t->base.Image[0][firstlevel]; + row_align = rmesa->radeon.texture_row_align - 1; + size = ((firstImage->Width * (depth / 8) + row_align) & ~row_align) * firstImage->Height; if (t->bo) { radeon_bo_unref(t->bo); t->bo = NULL; -- cgit v1.2.3 From a176b1c5d8b14601ec7e6ca9599c55fcc4797a7d Mon Sep 17 00:00:00 2001 From: Robert Noland Date: Wed, 14 Oct 2009 14:02:12 -0500 Subject: r600: cleanup in r600_cs_process_relocs(). Signed-off-by: Robert Noland --- src/mesa/drivers/dri/r600/r600_cmdbuf.c | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c index 3cfe03a45f..d27a3245a3 100644 --- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c +++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c @@ -254,7 +254,7 @@ static int r600_cs_process_relocs(struct radeon_cs *cs, relocs = (struct r600_cs_reloc_legacy *)cs->relocs; restart: for (i = 0; i < cs->crelocs; i++) { - uint32_t soffset, eoffset, asicoffset; + uint32_t soffset, eoffset; r = radeon_bo_legacy_validate(relocs[i].base.bo, &soffset, &eoffset); @@ -262,24 +262,12 @@ restart: goto restart; } if (r) { - fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", + fprintf(stderr, "invalid bo(%p) [0x%08X, 0x%08X]\n", relocs[i].base.bo, soffset, eoffset); return r; } - asicoffset = soffset; for (j = 0; j < relocs[i].cindices; j++) { - if (asicoffset >= eoffset) { - /* radeon_bo_debug(relocs[i].base.bo, 12); */ - fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n", - relocs[i].base.bo, soffset, eoffset); - fprintf(stderr, "above end: %p 0x%08X 0x%08X\n", - relocs[i].base.bo, - cs->packets[relocs[i].indices[j]], - eoffset); - exit(0); - return -EINVAL; - } /* pkt3 nop header in ib chunk */ cs->packets[relocs[i].reloc_indices[j]] = 0xC0001000; /* reloc index in ib chunk */ @@ -287,7 +275,7 @@ restart: } /* asic offset in reloc chunk */ /* see alex drm r600_nomm_relocate */ - reloc_chunk[offset_dw] = asicoffset; + reloc_chunk[offset_dw] = soffset; reloc_chunk[offset_dw + 3] = 0; offset_dw += 4; -- cgit v1.2.3 From 16c6a3b71e6be04b6bb3d08fcb658194c5251fc7 Mon Sep 17 00:00:00 2001 From: Robert Noland Date: Wed, 14 Oct 2009 14:04:24 -0500 Subject: r600: FRAG_ATTRIB_WPOS and FRAG_ATTRIB_FOGC appear to be supported. Report unsupported attributes while I'm here. Signed-off-by: Robert Noland --- src/mesa/drivers/dri/r600/r700_assembler.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 25b27cd829..a683008746 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -1180,8 +1180,10 @@ GLboolean tex_src(r700_AssemblerBase *pAsm) case PROGRAM_INPUT: switch (pILInst->SrcReg[0].Index) { + case FRAG_ATTRIB_WPOS: case FRAG_ATTRIB_COL0: case FRAG_ATTRIB_COL1: + case FRAG_ATTRIB_FOGC: case FRAG_ATTRIB_TEX0: case FRAG_ATTRIB_TEX1: case FRAG_ATTRIB_TEX2: @@ -1194,7 +1196,16 @@ GLboolean tex_src(r700_AssemblerBase *pAsm) pAsm->S[0].src.reg = pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index]; pAsm->S[0].src.rtype = SRC_REG_INPUT; - break; + break; + case FRAG_ATTRIB_FACE: + fprintf(stderr, "FRAG_ATTRIB_FACE unsupported\n"); + break; + case FRAG_ATTRIB_PNTC: + fprintf(stderr, "FRAG_ATTRIB_PNTC unsupported\n"); + break; + case FRAG_ATTRIB_VAR0: + fprintf(stderr, "FRAG_ATTRIB_VAR0 unsupported\n"); + break; } break; } -- cgit v1.2.3 From f094b86bb5ab93aedc03df5cf5bdf51ab9d37045 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Fri, 16 Oct 2009 09:33:11 -0600 Subject: mesa: lift default symlinks target into Makefile.template Driver Makefiles can still add symlink dependencies/rules if needed. --- src/mesa/drivers/dri/Makefile.template | 4 ++++ src/mesa/drivers/dri/fb/Makefile | 2 -- src/mesa/drivers/dri/ffb/Makefile | 1 - src/mesa/drivers/dri/gamma/Makefile | 1 - src/mesa/drivers/dri/i810/Makefile | 1 - src/mesa/drivers/dri/i915/Makefile | 1 - src/mesa/drivers/dri/i965/Makefile | 1 - src/mesa/drivers/dri/mach64/Makefile | 1 - src/mesa/drivers/dri/mga/Makefile | 1 - src/mesa/drivers/dri/r128/Makefile | 1 - src/mesa/drivers/dri/r200/Makefile | 1 - src/mesa/drivers/dri/r300/Makefile | 2 -- src/mesa/drivers/dri/r600/Makefile | 1 - src/mesa/drivers/dri/radeon/Makefile | 1 - src/mesa/drivers/dri/s3v/Makefile | 1 - src/mesa/drivers/dri/savage/Makefile | 1 - src/mesa/drivers/dri/sis/Makefile | 1 - src/mesa/drivers/dri/swrast/Makefile | 1 - src/mesa/drivers/dri/tdfx/Makefile | 2 -- src/mesa/drivers/dri/trident/Makefile | 1 - src/mesa/drivers/dri/unichrome/Makefile | 1 - 21 files changed, 4 insertions(+), 23 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/Makefile.template b/src/mesa/drivers/dri/Makefile.template index d2731aebae..1ce9315530 100644 --- a/src/mesa/drivers/dri/Makefile.template +++ b/src/mesa/drivers/dri/Makefile.template @@ -86,6 +86,10 @@ subdirs: fi +.PHONY: symlinks +symlinks: + + depend: $(C_SOURCES) $(ASM_SOURCES) $(SYMLINKS) @ echo "running $(MKDEP)" @ rm -f depend diff --git a/src/mesa/drivers/dri/fb/Makefile b/src/mesa/drivers/dri/fb/Makefile index 309f50b95f..cf9b3a8556 100644 --- a/src/mesa/drivers/dri/fb/Makefile +++ b/src/mesa/drivers/dri/fb/Makefile @@ -25,5 +25,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: - diff --git a/src/mesa/drivers/dri/ffb/Makefile b/src/mesa/drivers/dri/ffb/Makefile index cb73238c03..e9da8f9066 100644 --- a/src/mesa/drivers/dri/ffb/Makefile +++ b/src/mesa/drivers/dri/ffb/Makefile @@ -33,4 +33,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/gamma/Makefile b/src/mesa/drivers/dri/gamma/Makefile index 250d3ac089..09df1578fc 100644 --- a/src/mesa/drivers/dri/gamma/Makefile +++ b/src/mesa/drivers/dri/gamma/Makefile @@ -32,4 +32,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/i810/Makefile b/src/mesa/drivers/dri/i810/Makefile index a7825b49b4..3874faee51 100644 --- a/src/mesa/drivers/dri/i810/Makefile +++ b/src/mesa/drivers/dri/i810/Makefile @@ -29,4 +29,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/i915/Makefile b/src/mesa/drivers/dri/i915/Makefile index 393312e732..37f15aa767 100644 --- a/src/mesa/drivers/dri/i915/Makefile +++ b/src/mesa/drivers/dri/i915/Makefile @@ -72,4 +72,3 @@ intel_decode.o: ../intel/intel_decode.c intel_tex_layout.o: ../intel/intel_tex_layout.c -symlinks: diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile index 57dcc91586..7a55333e89 100644 --- a/src/mesa/drivers/dri/i965/Makefile +++ b/src/mesa/drivers/dri/i965/Makefile @@ -100,6 +100,5 @@ DRI_LIB_DEPS += -ldrm_intel include ../Makefile.template -symlinks: intel_decode.o: ../intel/intel_decode.c intel_tex_layout.o: ../intel/intel_tex_layout.c diff --git a/src/mesa/drivers/dri/mach64/Makefile b/src/mesa/drivers/dri/mach64/Makefile index 7246d51f5d..a8f463e9fd 100644 --- a/src/mesa/drivers/dri/mach64/Makefile +++ b/src/mesa/drivers/dri/mach64/Makefile @@ -30,4 +30,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/mga/Makefile b/src/mesa/drivers/dri/mga/Makefile index a871064c62..0cc329fb22 100644 --- a/src/mesa/drivers/dri/mga/Makefile +++ b/src/mesa/drivers/dri/mga/Makefile @@ -31,4 +31,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/r128/Makefile b/src/mesa/drivers/dri/r128/Makefile index 796dfbc516..52c5a38a70 100644 --- a/src/mesa/drivers/dri/r128/Makefile +++ b/src/mesa/drivers/dri/r128/Makefile @@ -29,4 +29,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile index fbce70c37b..776f1e3f3f 100644 --- a/src/mesa/drivers/dri/r200/Makefile +++ b/src/mesa/drivers/dri/r200/Makefile @@ -66,4 +66,3 @@ include ../Makefile.template #INCLUDES += -I../radeon/server -symlinks: diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index 0e5b29b685..cb0f715fa0 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -78,5 +78,3 @@ EXTRA_MODULES = compiler/libr300compiler.a include ../Makefile.template -symlinks: - diff --git a/src/mesa/drivers/dri/r600/Makefile b/src/mesa/drivers/dri/r600/Makefile index 7d5a7b1ab6..9b7c42042e 100644 --- a/src/mesa/drivers/dri/r600/Makefile +++ b/src/mesa/drivers/dri/r600/Makefile @@ -76,4 +76,3 @@ DRI_LIB_DEPS += $(RADEON_LDFLAGS) include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/radeon/Makefile b/src/mesa/drivers/dri/radeon/Makefile index b1efc72872..ae2e695bfc 100644 --- a/src/mesa/drivers/dri/radeon/Makefile +++ b/src/mesa/drivers/dri/radeon/Makefile @@ -55,4 +55,3 @@ X86_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/s3v/Makefile b/src/mesa/drivers/dri/s3v/Makefile index 9bd7973154..da7e6cdc20 100644 --- a/src/mesa/drivers/dri/s3v/Makefile +++ b/src/mesa/drivers/dri/s3v/Makefile @@ -33,4 +33,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/savage/Makefile b/src/mesa/drivers/dri/savage/Makefile index 018482f66b..2e5c40802c 100644 --- a/src/mesa/drivers/dri/savage/Makefile +++ b/src/mesa/drivers/dri/savage/Makefile @@ -27,4 +27,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/sis/Makefile b/src/mesa/drivers/dri/sis/Makefile index d2354e6776..ad009fc239 100644 --- a/src/mesa/drivers/dri/sis/Makefile +++ b/src/mesa/drivers/dri/sis/Makefile @@ -34,4 +34,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/swrast/Makefile b/src/mesa/drivers/dri/swrast/Makefile index 5f3a4f2191..771169c1ff 100644 --- a/src/mesa/drivers/dri/swrast/Makefile +++ b/src/mesa/drivers/dri/swrast/Makefile @@ -21,4 +21,3 @@ SWRAST_COMMON_SOURCES = \ include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/tdfx/Makefile b/src/mesa/drivers/dri/tdfx/Makefile index 092c580fea..b9f25db4fe 100644 --- a/src/mesa/drivers/dri/tdfx/Makefile +++ b/src/mesa/drivers/dri/tdfx/Makefile @@ -32,6 +32,4 @@ ASM_SOURCES = include ../Makefile.template -symlinks: - diff --git a/src/mesa/drivers/dri/trident/Makefile b/src/mesa/drivers/dri/trident/Makefile index 9ee24c504c..bd9b7f35a2 100644 --- a/src/mesa/drivers/dri/trident/Makefile +++ b/src/mesa/drivers/dri/trident/Makefile @@ -23,4 +23,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/unichrome/Makefile b/src/mesa/drivers/dri/unichrome/Makefile index 5fe00c1bd1..344d34fce3 100644 --- a/src/mesa/drivers/dri/unichrome/Makefile +++ b/src/mesa/drivers/dri/unichrome/Makefile @@ -29,4 +29,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: -- cgit v1.2.3 From 8123180ea649540fb7319bc79ad77dca0d5d68cd Mon Sep 17 00:00:00 2001 From: Robert Noland Date: Mon, 19 Oct 2009 09:47:39 -0500 Subject: r600: Fix size calculation for 24 bit depth size was being calculated based on 3 bytes per pixel with 24 bit depth instead of 4 bytes. This caused corruption in the bottom 25% of objects. This finishes fixing the menu/text corruption in compiz/kde4. Signed-off-by: Robert Noland --- src/mesa/drivers/dri/r600/r600_texstate.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 61ff7e8158..a30703e41b 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -723,7 +723,7 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname, radeonTexObjPtr t = radeon_tex_obj(tObj); int firstlevel = t->mt ? t->mt->firstLevel : 0; const struct gl_texture_image *firstImage; - uint32_t pitch_val, size, row_align; + uint32_t pitch_val, size, row_align, bpp; if (!tObj) return; @@ -733,9 +733,13 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname, if (!offset) return; + bpp = depth / 8; + if (bpp == 3) + bpp = 4; + firstImage = t->base.Image[0][firstlevel]; row_align = rmesa->radeon.texture_row_align - 1; - size = ((firstImage->Width * (depth / 8) + row_align) & ~row_align) * firstImage->Height; + size = ((firstImage->Width * bpp + row_align) & ~row_align) * firstImage->Height; if (t->bo) { radeon_bo_unref(t->bo); t->bo = NULL; -- cgit v1.2.3 From c18b022d0d1dc07c37c0bd981d4fc6fac27e5a45 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Wed, 21 Oct 2009 21:12:23 -0600 Subject: radeon: replace MESA_FORMAT_Z24_S8 with MESA_FORMAT_S8_Z24 Core Mesa deals with MESA_FORMAT_S8_Z24 everywhere it should so we shouldn't have to use MESA_FORMAT_Z24_S8 anymore. --- src/mesa/drivers/dri/r300/r300_texstate.c | 2 +- src/mesa/drivers/dri/r600/r600_texstate.c | 6 +++--- src/mesa/drivers/dri/radeon/radeon_span.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 1e9bd3e849..63f0154cd3 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -159,7 +159,7 @@ void r300SetDepthTexMode(struct gl_texture_object *tObj) case MESA_FORMAT_Z16: format = formats[0]; break; - case MESA_FORMAT_Z24_S8: + case MESA_FORMAT_S8_Z24: format = formats[1]; break; case MESA_FORMAT_Z32: diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 35186ef970..63d88f83d6 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -77,7 +77,7 @@ void r600UpdateTextureState(GLcontext * ctx) } } -static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, GLuint mesa_format) +static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa_format) { radeonTexObj *t = radeon_tex_obj(tObj); @@ -479,14 +479,14 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, GLuint mesa_fo SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); break; case MESA_FORMAT_Z16: - case MESA_FORMAT_Z24_S8: + case MESA_FORMAT_S8_Z24: case MESA_FORMAT_Z32: switch (mesa_format) { case MESA_FORMAT_Z16: SETfield(t->SQ_TEX_RESOURCE1, FMT_16, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); break; - case MESA_FORMAT_Z24_S8: + case MESA_FORMAT_S8_Z24: SETfield(t->SQ_TEX_RESOURCE1, FMT_24_8, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); break; diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 055f77a24b..4b47e756c7 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -878,11 +878,11 @@ static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb) radeonInitDepthPointers_z16(&rrb->base); } else if (rrb->base.Format == GL_DEPTH_COMPONENT32) { /* XXX */ radeonInitDepthPointers_z24(&rrb->base); - } else if (rrb->base.Format == MESA_FORMAT_Z24_S8) { + } else if (rrb->base.Format == MESA_FORMAT_S8_Z24) { radeonInitDepthPointers_z24_s8(&rrb->base); } else if (rrb->base.Format == MESA_FORMAT_S8) { radeonInitStencilPointers_z24_s8(&rrb->base); } else { - fprintf(stderr, "radeonSetSpanFunctions: bad actual format: 0x%04X\n", rrb->base.Format); + fprintf(stderr, "radeonSetSpanFunctions: bad format: 0x%04X\n", rrb->base.Format); } } -- cgit v1.2.3 From b86302283b48654682e0580c53ece01bf095fa95 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Tue, 20 Oct 2009 11:45:39 +0300 Subject: r600: add beginnings of ARL instruction --- src/mesa/drivers/dri/r600/r700_assembler.c | 35 +++++++++++++++++++++++++++--- src/mesa/drivers/dri/r600/r700_assembler.h | 1 + 2 files changed, 33 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index a683008746..d0eb9949a6 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -355,6 +355,7 @@ unsigned int r700GetNumOperands(r700_AssemblerBase* pAsm) return 2; case SQ_OP2_INST_MOV: + case SQ_OP2_INST_MOVA_FLOOR: case SQ_OP2_INST_FRACT: case SQ_OP2_INST_FLOOR: case SQ_OP2_INST_EXP_IEEE: @@ -2064,7 +2065,7 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) } //other bits - alu_instruction_ptr->m_Word0.f.index_mode = SQ_INDEX_LOOP; + alu_instruction_ptr->m_Word0.f.index_mode = SQ_INDEX_AR_X; if( (is_single_scalar_operation == GL_TRUE) || (GL_TRUE == bSplitInst) ) @@ -2398,6 +2399,35 @@ GLboolean assemble_ADD(r700_AssemblerBase *pAsm) return GL_TRUE; } +GLboolean assemble_ARL(r700_AssemblerBase *pAsm) +{ /* TODO: ar values dont' persist between clauses */ + if( GL_FALSE == checkop1(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP2_INST_MOVA_FLOOR; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = 0; + pAsm->D.dst.writex = 0; + pAsm->D.dst.writey = 0; + pAsm->D.dst.writez = 0; + pAsm->D.dst.writew = 0; + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + GLboolean assemble_BAD(char *opcode_str) { radeon_error("Not yet implemented instruction (%s)\n", opcode_str); @@ -3812,8 +3842,7 @@ GLboolean AssembleInstr(GLuint uiNumberInsts, break; case OPCODE_ARL: - radeon_error("Not yet implemented instruction OPCODE_ARL \n"); - //if ( GL_FALSE == assemble_BAD("ARL") ) + if ( GL_FALSE == assemble_ARL(pR700AsmCode) ) return GL_FALSE; break; case OPCODE_ARR: diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index 73bb8bac55..d639592702 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -461,6 +461,7 @@ GLboolean next_ins(r700_AssemblerBase *pAsm); GLboolean assemble_math_function(r700_AssemblerBase* pAsm, BITS opcode); GLboolean assemble_ABS(r700_AssemblerBase *pAsm); GLboolean assemble_ADD(r700_AssemblerBase *pAsm); +GLboolean assemble_ARL(r700_AssemblerBase *pAsm); GLboolean assemble_BAD(char *opcode_str); GLboolean assemble_CMP(r700_AssemblerBase *pAsm); GLboolean assemble_COS(r700_AssemblerBase *pAsm); -- cgit v1.2.3 From a88c9296cb079ff42ef901113d0fe772228e6feb Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Wed, 21 Oct 2009 12:23:27 +0300 Subject: r600: need to export something from PS Also avoids empty shader for "END" - seems to be somewhat valid fp Maybe this can be done differently in the future (fake FRAG_RESULT_COLOR already in Map_Fragment_Program() or is there a way to program the chip to not hang in case of no exports. --- src/mesa/drivers/dri/r600/r700_assembler.c | 11 ++++++++++- src/mesa/drivers/dri/r600/r700_fragprog.c | 10 +++++++++- 2 files changed, 19 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index d0eb9949a6..6ff08e1cfb 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -4187,6 +4187,7 @@ GLboolean Process_Fragment_Exports(r700_AssemblerBase *pR700AsmCode, GLbitfield OutputsWritten) { unsigned int unBit; + GLuint export_count = 0; if(pR700AsmCode->depth_export_register_number >= 0) { @@ -4208,6 +4209,7 @@ GLboolean Process_Fragment_Exports(r700_AssemblerBase *pR700AsmCode, { return GL_FALSE; } + export_count++; } unBit = 1 << FRAG_RESULT_DEPTH; if(OutputsWritten & unBit) @@ -4221,8 +4223,15 @@ GLboolean Process_Fragment_Exports(r700_AssemblerBase *pR700AsmCode, { return GL_FALSE; } + export_count++; } - + /* Need to export something, otherwise we'll hang + * results are undefined anyway */ + if(export_count == 0) + { + Process_Export(pR700AsmCode, SQ_EXPORT_PIXEL, 0, 1, 0, GL_FALSE); + } + if(pR700AsmCode->cf_last_export_ptr != NULL) { pR700AsmCode->cf_last_export_ptr->m_Word1.f.cf_inst = SQ_CF_INST_EXPORT_DONE; diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index 62a1ea1a22..3736bce11c 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -251,7 +251,15 @@ GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp, number_of_colors_exported--; } - fp->r700Shader.exportMode = number_of_colors_exported << 1 | z_enabled; + /* illegal to set this to 0 */ + if(number_of_colors_exported || z_enabled) + { + fp->r700Shader.exportMode = number_of_colors_exported << 1 | z_enabled; + } + else + { + fp->r700Shader.exportMode = (1 << 1); + } fp->translated = GL_TRUE; -- cgit v1.2.3 From 869e20bcb7db9c6540eb6b538104303df738d302 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Wed, 21 Oct 2009 19:04:21 +0300 Subject: r600: set barrier for tex inst if dst is used earlier, might overwrite it otherwise --- src/mesa/drivers/dri/r600/r700_fragprog.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index 3736bce11c..0f549ead9c 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -135,15 +135,19 @@ GLboolean Find_Instruction_Dependencies_fp(struct r700_fragment_program *fp, { GLuint i, j; GLint * puiTEMPwrites; + GLint * puiTEMPreads; struct prog_instruction * pILInst; InstDeps *pInstDeps; struct prog_instruction * texcoord_DepInst; GLint nDepInstID; puiTEMPwrites = (GLint*) MALLOC(sizeof(GLuint)*mesa_fp->Base.NumTemporaries); + puiTEMPreads = (GLint*) MALLOC(sizeof(GLuint)*mesa_fp->Base.NumTemporaries); + for(i=0; iBase.NumTemporaries; i++) { puiTEMPwrites[i] = -1; + puiTEMPreads[i] = -1; } pInstDeps = (InstDeps*)MALLOC(sizeof(InstDeps)*mesa_fp->Base.NumInstructions); @@ -167,6 +171,11 @@ GLboolean Find_Instruction_Dependencies_fp(struct r700_fragment_program *fp, { //Set dep. pInstDeps[i].nSrcDeps[j] = puiTEMPwrites[pILInst->SrcReg[j].Index]; + //Set first read + if(puiTEMPreads[pILInst->SrcReg[j].Index] < 0 ) + { + puiTEMPreads[pILInst->SrcReg[j].Index] = i; + } } else { @@ -177,8 +186,6 @@ GLboolean Find_Instruction_Dependencies_fp(struct r700_fragment_program *fp, fp->r700AsmCode.pInstDeps = pInstDeps; - FREE(puiTEMPwrites); - //Find dep for tex inst for(i=0; iBase.NumInstructions; i++) { @@ -203,9 +210,25 @@ GLboolean Find_Instruction_Dependencies_fp(struct r700_fragment_program *fp, { //... other deps? } } + // make sure that we dont overwrite src used earlier + nDepInstID = puiTEMPreads[pILInst->DstReg.Index]; + if(nDepInstID < i) + { + pInstDeps[i].nDstDep = puiTEMPreads[pILInst->DstReg.Index]; + texcoord_DepInst = &(mesa_fp->Base.Instructions[nDepInstID]); + if(GL_TRUE == IsAlu(texcoord_DepInst->Opcode) ) + { + pInstDeps[nDepInstID].nDstDep = i; + } + + } + } } + FREE(puiTEMPwrites); + FREE(puiTEMPreads); + return GL_TRUE; } -- cgit v1.2.3 From 95328c7cf91322813de846a72f157aefff9417a6 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 22 Oct 2009 17:18:01 -0400 Subject: r600: clean up context creation Make it more consistent with other radeon drivers. --- src/mesa/drivers/dri/r600/r600_context.c | 202 +++++++++++++++---------------- 1 file changed, 100 insertions(+), 102 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index ba0d450cbb..9776a868ff 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -213,6 +213,96 @@ static void r600_init_vtbl(radeonContextPtr radeon) radeon->vtbl.fallback = r600_fallback; } +static void r600InitConstValues(GLcontext *ctx, radeonScreenPtr screen) +{ + context_t *r600 = R700_CONTEXT(ctx); + + ctx->Const.MaxTextureImageUnits = + driQueryOptioni(&r600->radeon.optionCache, "texture_image_units"); + ctx->Const.MaxTextureCoordUnits = + driQueryOptioni(&r600->radeon.optionCache, "texture_coord_units"); + ctx->Const.MaxTextureUnits = + MIN2(ctx->Const.MaxTextureImageUnits, + ctx->Const.MaxTextureCoordUnits); + ctx->Const.MaxTextureMaxAnisotropy = 16.0; + ctx->Const.MaxTextureLodBias = 16.0; + + ctx->Const.MaxTextureLevels = 13; /* hw support 14 */ + ctx->Const.MaxTextureRectSize = 4096; /* hw support 8192 */ + + ctx->Const.MinPointSize = 0x0001 / 8.0; + ctx->Const.MinPointSizeAA = 0x0001 / 8.0; + ctx->Const.MaxPointSize = 0xffff / 8.0; + ctx->Const.MaxPointSizeAA = 0xffff / 8.0; + + ctx->Const.MinLineWidth = 0x0001 / 8.0; + ctx->Const.MinLineWidthAA = 0x0001 / 8.0; + ctx->Const.MaxLineWidth = 0xffff / 8.0; + ctx->Const.MaxLineWidthAA = 0xffff / 8.0; + + ctx->Const.MaxDrawBuffers = 1; /* hw supports 8 */ + + /* 256 for reg-based consts, inline consts also supported */ + ctx->Const.VertexProgram.MaxInstructions = 8192; /* in theory no limit */ + ctx->Const.VertexProgram.MaxNativeInstructions = 8192; + ctx->Const.VertexProgram.MaxNativeAttribs = 160; + ctx->Const.VertexProgram.MaxTemps = 128; + ctx->Const.VertexProgram.MaxNativeTemps = 128; + ctx->Const.VertexProgram.MaxNativeParameters = 256; + ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; /* ??? */ + + ctx->Const.FragmentProgram.MaxNativeTemps = 128; + ctx->Const.FragmentProgram.MaxNativeAttribs = 32; + ctx->Const.FragmentProgram.MaxNativeParameters = 256; + ctx->Const.FragmentProgram.MaxNativeAluInstructions = 8192; + /* 8 per clause on r6xx, 16 on rv670/r7xx */ + if ((screen->chip_family == CHIP_FAMILY_RV670) || + (screen->chip_family >= CHIP_FAMILY_RV770)) + ctx->Const.FragmentProgram.MaxNativeTexInstructions = 16; + else + ctx->Const.FragmentProgram.MaxNativeTexInstructions = 8; + ctx->Const.FragmentProgram.MaxNativeInstructions = 8192; + ctx->Const.FragmentProgram.MaxNativeTexIndirections = 8; /* ??? */ + ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0; /* and these are?? */ +} + +static void r600ParseOptions(context_t *r600, radeonScreenPtr screen) +{ + /* Parse configuration files. + * Do this here so that initialMaxAnisotropy is set before we create + * the default textures. + */ + driParseConfigFiles(&r600->radeon.optionCache, &screen->optionCache, + screen->driScreen->myNum, "r600"); + + r600->radeon.initialMaxAnisotropy = driQueryOptionf(&r600->radeon.optionCache, + "def_max_anisotropy"); + +} + +static void r600InitGLExtensions(GLcontext *ctx) +{ + context_t *r600 = R700_CONTEXT(ctx); + + driInitExtensions(ctx, card_extensions, GL_TRUE); + if (r600->radeon.radeonScreen->kernel_mm) + driInitExtensions(ctx, mm_extensions, GL_FALSE); + + if (driQueryOptionb + (&r600->radeon.optionCache, "disable_stencil_two_side")) + _mesa_disable_extension(ctx, "GL_EXT_stencil_two_side"); + + if (r600->radeon.glCtx->Mesa_DXTn + && !driQueryOptionb(&r600->radeon.optionCache, "disable_s3tc")) { + _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc"); + _mesa_enable_extension(ctx, "GL_S3_s3tc"); + } else + if (driQueryOptionb(&r600->radeon.optionCache, "force_s3tc_enable")) + { + _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc"); + } +} + /* Create the device specific rendering context. */ GLboolean r600CreateContext(const __GLcontextModes * glVisual, @@ -236,19 +326,10 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, return GL_FALSE; } - if (!(screen->chip_flags & RADEON_CHIPSET_TCL)) - hw_tcl_on = future_hw_tcl_on = 0; + r600ParseOptions(r600, screen); + r600->radeon.radeonScreen = screen; r600_init_vtbl(&r600->radeon); - /* Parse configuration files. - * Do this here so that initialMaxAnisotropy is set before we create - * the default textures. - */ - driParseConfigFiles(&r600->radeon.optionCache, &screen->optionCache, - screen->driScreen->myNum, "r600"); - - r600->radeon.initialMaxAnisotropy = driQueryOptionf(&r600->radeon.optionCache, - "def_max_anisotropy"); /* Init default driver functions then plug in our R600-specific functions * (the texture functions are especially important) @@ -259,7 +340,7 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, r600InitTextureFuncs(&functions); r700InitShaderFuncs(&functions); r700InitIoctlFuncs(&functions); - radeonInitBufferObjectFuncs(&functions); + radeonInitBufferObjectFuncs(&functions); if (!radeonInitContext(&r600->radeon, &functions, glVisual, driContextPriv, @@ -269,44 +350,14 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, return GL_FALSE; } - /* Init r600 context data */ - /* Set the maximum texture size small enough that we can guarentee that - * all texture units can bind a maximal texture and have them both in - * texturable memory at once. - */ - ctx = r600->radeon.glCtx; - ctx->Const.MaxTextureImageUnits = - driQueryOptioni(&r600->radeon.optionCache, "texture_image_units"); - ctx->Const.MaxTextureCoordUnits = - driQueryOptioni(&r600->radeon.optionCache, "texture_coord_units"); - ctx->Const.MaxTextureUnits = - MIN2(ctx->Const.MaxTextureImageUnits, - ctx->Const.MaxTextureCoordUnits); - ctx->Const.MaxTextureMaxAnisotropy = 16.0; - ctx->Const.MaxTextureLodBias = 16.0; - - ctx->Const.MaxTextureLevels = 13; /* hw support 14 */ - ctx->Const.MaxTextureRectSize = 4096; /* hw support 8192 */ - - ctx->Const.MinPointSize = 0x0001 / 8.0; - ctx->Const.MinPointSizeAA = 0x0001 / 8.0; - ctx->Const.MaxPointSize = 0xffff / 8.0; - ctx->Const.MaxPointSizeAA = 0xffff / 8.0; - - ctx->Const.MinLineWidth = 0x0001 / 8.0; - ctx->Const.MinLineWidthAA = 0x0001 / 8.0; - ctx->Const.MaxLineWidth = 0xffff / 8.0; - ctx->Const.MaxLineWidthAA = 0xffff / 8.0; + ctx->VertexProgram._MaintainTnlProgram = GL_TRUE; + ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE; - /* Needs further modifications */ -#if 0 - ctx->Const.MaxArrayLockSize = - ( /*512 */ RADEON_BUFFER_SIZE * 16 * 1024) / (4 * 4); -#endif + r600InitConstValues(ctx, screen); - ctx->Const.MaxDrawBuffers = 1; + _mesa_set_mvp_with_dp4( ctx, GL_TRUE ); /* Initialize the software rasterizer and helper modules. */ @@ -315,16 +366,12 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, _tnl_CreateContext(ctx); _swsetup_CreateContext(ctx); _swsetup_Wakeup(ctx); - _ae_create_context(ctx); /* Install the customized pipeline: */ _tnl_destroy_pipeline(ctx); _tnl_install_pipeline(ctx, r700_pipeline); - - /* Try and keep materials and vertices separate: - */ -/* _tnl_isolate_materials(ctx, GL_TRUE); */ + TNL_CONTEXT(ctx)->Driver.RunPipeline = r600RunPipeline; /* Configure swrast and TNL to match hardware characteristics: */ @@ -333,65 +380,16 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, _tnl_allow_pixel_fog(ctx, GL_FALSE); _tnl_allow_vertex_fog(ctx, GL_TRUE); - /* 256 for reg-based consts, inline consts also supported */ - ctx->Const.VertexProgram.MaxInstructions = 8192; /* in theory no limit */ - ctx->Const.VertexProgram.MaxNativeInstructions = 8192; - ctx->Const.VertexProgram.MaxNativeAttribs = 160; - ctx->Const.VertexProgram.MaxTemps = 128; - ctx->Const.VertexProgram.MaxNativeTemps = 128; - ctx->Const.VertexProgram.MaxNativeParameters = 256; - ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; /* ??? */ - - ctx->Const.FragmentProgram.MaxNativeTemps = 128; - ctx->Const.FragmentProgram.MaxNativeAttribs = 32; - ctx->Const.FragmentProgram.MaxNativeParameters = 256; - ctx->Const.FragmentProgram.MaxNativeAluInstructions = 8192; - /* 8 per clause on r6xx, 16 on rv670/r7xx */ - if ((screen->chip_family == CHIP_FAMILY_RV670) || - (screen->chip_family >= CHIP_FAMILY_RV770)) - ctx->Const.FragmentProgram.MaxNativeTexInstructions = 16; - else - ctx->Const.FragmentProgram.MaxNativeTexInstructions = 8; - ctx->Const.FragmentProgram.MaxNativeInstructions = 8192; - ctx->Const.FragmentProgram.MaxNativeTexIndirections = 8; /* ??? */ - ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0; /* and these are?? */ - ctx->VertexProgram._MaintainTnlProgram = GL_TRUE; - ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE; - radeon_init_debug(); - driInitExtensions(ctx, card_extensions, GL_TRUE); - if (r600->radeon.radeonScreen->kernel_mm) - driInitExtensions(ctx, mm_extensions, GL_FALSE); - - if (driQueryOptionb - (&r600->radeon.optionCache, "disable_stencil_two_side")) - _mesa_disable_extension(ctx, "GL_EXT_stencil_two_side"); - - if (r600->radeon.glCtx->Mesa_DXTn - && !driQueryOptionb(&r600->radeon.optionCache, "disable_s3tc")) { - _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc"); - _mesa_enable_extension(ctx, "GL_S3_s3tc"); - } else - if (driQueryOptionb(&r600->radeon.optionCache, "force_s3tc_enable")) - { - _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc"); - } - - r700InitDraw(ctx); + r700InitDraw(ctx); radeon_fbo_init(&r600->radeon); radeonInitSpanFuncs( ctx ); - r600InitCmdBuf(r600); - r700InitState(r600->radeon.glCtx); - TNL_CONTEXT(ctx)->Driver.RunPipeline = r600RunPipeline; - - if (driQueryOptionb(&r600->radeon.optionCache, "no_rast")) { - radeon_warning("disabling 3D acceleration\n"); - } + r600InitGLExtensions(ctx); return GL_TRUE; } -- cgit v1.2.3 From 614e8f220332d5876c787ea07300c6c8508219d5 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 22 Oct 2009 17:41:31 -0400 Subject: r600: remove old tnl pipeline --- src/mesa/drivers/dri/r600/r600_context.c | 33 +++--- src/mesa/drivers/dri/r600/r700_render.c | 193 +++---------------------------- 2 files changed, 34 insertions(+), 192 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 9776a868ff..e6791b46f0 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -94,8 +94,6 @@ int hw_tcl_on = 1; #include "extension_helper.h" -extern const struct tnl_pipeline_stage *r700_pipeline[]; - const struct dri_extension card_extensions[] = { /* *INDENT-OFF* */ {"GL_ARB_depth_texture", NULL}, @@ -160,17 +158,20 @@ const struct dri_extension gl_20_extension[] = { {"GL_VERSION_2_0", GL_VERSION_2_0_functions }, }; - -static void r600RunPipeline(GLcontext * ctx) -{ - _mesa_lock_context_textures(ctx); - - if (ctx->NewState) - _mesa_update_state_locked(ctx); - - _tnl_run_pipeline(ctx); - _mesa_unlock_context_textures(ctx); -} +static const struct tnl_pipeline_stage *r600_pipeline[] = { + /* Catch any t&l fallbacks + */ + &_tnl_vertex_transform_stage, + &_tnl_normal_transform_stage, + &_tnl_lighting_stage, + &_tnl_fog_coordinate_stage, + &_tnl_texgen_stage, + &_tnl_texture_transform_stage, + &_tnl_point_attenuation_stage, + &_tnl_vertex_program_stage, + &_tnl_render_stage, + 0, +}; static void r600_get_lock(radeonContextPtr rmesa) { @@ -181,7 +182,7 @@ static void r600_get_lock(radeonContextPtr rmesa) if (!rmesa->radeonScreen->kernel_mm) radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom); } -} +} static void r600_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) { @@ -370,8 +371,8 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, /* Install the customized pipeline: */ _tnl_destroy_pipeline(ctx); - _tnl_install_pipeline(ctx, r700_pipeline); - TNL_CONTEXT(ctx)->Driver.RunPipeline = r600RunPipeline; + _tnl_install_pipeline(ctx, r600_pipeline); + TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline; /* Configure swrast and TNL to match hardware characteristics: */ diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 4f39d9f1bd..71f95a19c0 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -409,139 +409,6 @@ static GLuint r700PredictRenderSize(GLcontext* ctx, GLuint nr_prims) return dwords; } -static GLboolean r700RunRender(GLcontext * ctx, - struct tnl_pipeline_stage *stage) -{ - context_t *context = R700_CONTEXT(ctx); - radeonContextPtr radeon = &context->radeon; - unsigned int i, id = 0; - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *vb = &tnl->vb; - struct radeon_renderbuffer *rrb; - - radeon_print(RADEON_RENDER, RADEON_NORMAL, "%s: cs begin at %d\n", - __func__, context->radeon.cmdbuf.cs->cdw); - - /* always emit CB base to prevent - * lock ups on some chips. - */ - R600_STATECHANGE(context, cb_target); - /* mark vtx as dirty since it changes per-draw */ - R600_STATECHANGE(context, vtx); - - r700SetScissor(context); - r700SetupVertexProgram(ctx); - r700SetupFragmentProgram(ctx); - r600UpdateTextureState(ctx); - - GLuint emit_end = r700PredictRenderSize(ctx, 0) - + context->radeon.cmdbuf.cs->cdw; - r700SetupStreams(ctx); - - radeonEmitState(radeon); - - radeon_debug_add_indent(); - /* richard test code */ - for (i = 0; i < vb->PrimitiveCount; i++) { - GLuint prim = _tnl_translate_prim(&vb->Primitive[i]); - GLuint start = vb->Primitive[i].start; - GLuint end = vb->Primitive[i].start + vb->Primitive[i].count; - r700RunRenderPrimitive(ctx, start, end, prim); - } - radeon_debug_remove_indent(); - - /* Flush render op cached for last several quads. */ - r700WaitForIdleClean(context); - - rrb = radeon_get_colorbuffer(&context->radeon); - if (rrb && rrb->bo) - r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM, - CB_ACTION_ENA_bit | (1 << (id + 6))); - - rrb = radeon_get_depthbuffer(&context->radeon); - if (rrb && rrb->bo) - r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM, - DB_ACTION_ENA_bit | DB_DEST_BASE_ENA_bit); - - radeonReleaseArrays(ctx, ~0); - - radeon_print(RADEON_RENDER, RADEON_TRACE, "%s: cs end at %d\n", - __func__, context->radeon.cmdbuf.cs->cdw); - - if ( emit_end < context->radeon.cmdbuf.cs->cdw ) - WARN_ONCE("Rendering was %d commands larger than predicted size." - " We might overflow command buffer.\n", context->radeon.cmdbuf.cs->cdw - emit_end); - - return GL_FALSE; -} - -static GLboolean r700RunNonTCLRender(GLcontext * ctx, - struct tnl_pipeline_stage *stage) /* -------------------- */ -{ - GLboolean bRet = GL_TRUE; - - return bRet; -} - -static GLboolean r700RunTCLRender(GLcontext * ctx, /*----------------------*/ - struct tnl_pipeline_stage *stage) -{ - GLboolean bRet = GL_FALSE; - - /* TODO : sw fallback */ - - /* Need shader bo's setup before bo check */ - r700UpdateShaders(ctx); - /** - - * Ensure all enabled and complete textures are uploaded along with any buffers being used. - */ - if(!r600ValidateBuffers(ctx)) - { - return GL_TRUE; - } - - bRet = r700RunRender(ctx, stage); - - return bRet; - //GL_FALSE will stop to do other pipe stage in _tnl_run_pipeline - //The render here DOES finish the whole pipe, so GL_FALSE should be returned for success. -} - -const struct tnl_pipeline_stage _r700_render_stage = { - "r700 Hardware Rasterization", - NULL, - NULL, - NULL, - NULL, - r700RunNonTCLRender -}; - -const struct tnl_pipeline_stage _r700_tcl_stage = { - "r700 Hardware Transform, Clipping and Lighting", - NULL, - NULL, - NULL, - NULL, - r700RunTCLRender -}; - -const struct tnl_pipeline_stage *r700_pipeline[] = -{ - &_r700_tcl_stage, - &_tnl_vertex_transform_stage, - &_tnl_normal_transform_stage, - &_tnl_lighting_stage, - &_tnl_fog_coordinate_stage, - &_tnl_texgen_stage, - &_tnl_texture_transform_stage, - &_tnl_vertex_program_stage, - - &_r700_render_stage, - &_tnl_render_stage, - 0, -}; - #define CONVERT( TYPE, MACRO ) do { \ GLuint i, j, sz; \ sz = input->Size; \ @@ -941,12 +808,12 @@ static void r700SetupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer } static GLboolean r700TryDrawPrims(GLcontext *ctx, - const struct gl_client_array *arrays[], - const struct _mesa_prim *prim, - GLuint nr_prims, - const struct _mesa_index_buffer *ib, - GLuint min_index, - GLuint max_index ) + const struct gl_client_array *arrays[], + const struct _mesa_prim *prim, + GLuint nr_prims, + const struct _mesa_index_buffer *ib, + GLuint min_index, + GLuint max_index ) { context_t *context = R700_CONTEXT(ctx); radeonContextPtr radeon = &context->radeon; @@ -954,9 +821,7 @@ static GLboolean r700TryDrawPrims(GLcontext *ctx, struct radeon_renderbuffer *rrb; if (ctx->NewState) - { _mesa_update_state( ctx ); - } _tnl_UpdateFixedFunctionProgram(ctx); r700SetVertexFormat(ctx, arrays, max_index + 1); @@ -1019,18 +884,18 @@ static GLboolean r700TryDrawPrims(GLcontext *ctx, return GL_TRUE; } -static void r700DrawPrimsRe(GLcontext *ctx, - const struct gl_client_array *arrays[], - const struct _mesa_prim *prim, - GLuint nr_prims, - const struct _mesa_index_buffer *ib, - GLboolean index_bounds_valid, - GLuint min_index, - GLuint max_index) +static void r700DrawPrims(GLcontext *ctx, + const struct gl_client_array *arrays[], + const struct _mesa_prim *prim, + GLuint nr_prims, + const struct _mesa_index_buffer *ib, + GLboolean index_bounds_valid, + GLuint min_index, + GLuint max_index) { - GLboolean retval = GL_FALSE; + GLboolean retval = GL_FALSE; - /* This check should get folded into just the places that + /* This check should get folded into just the places that * min/max index are really needed. */ if (!index_bounds_valid) { @@ -1038,7 +903,7 @@ static void r700DrawPrimsRe(GLcontext *ctx, } if (min_index) { - vbo_rebase_prims( ctx, arrays, prim, nr_prims, ib, min_index, max_index, r700DrawPrimsRe ); + vbo_rebase_prims( ctx, arrays, prim, nr_prims, ib, min_index, max_index, r700DrawPrims ); return; } @@ -1050,30 +915,6 @@ static void r700DrawPrimsRe(GLcontext *ctx, _tnl_draw_prims(ctx, arrays, prim, nr_prims, ib, min_index, max_index); } -static void r700DrawPrims(GLcontext *ctx, - const struct gl_client_array *arrays[], - const struct _mesa_prim *prim, - GLuint nr_prims, - const struct _mesa_index_buffer *ib, - GLboolean index_bounds_valid, - GLuint min_index, - GLuint max_index) -{ - context_t *context = R700_CONTEXT(ctx); - - /* For non indexed drawing, using tnl pipe. */ - if(!ib) - { - context->ind_buf.bo = NULL; - - _tnl_vbo_draw_prims(ctx, arrays, prim, nr_prims, ib, - index_bounds_valid, min_index, max_index); - return; - } - - r700DrawPrimsRe(ctx, arrays, prim, nr_prims, ib, index_bounds_valid, min_index, max_index); -} - void r700InitDraw(GLcontext *ctx) { struct vbo_context *vbo = vbo_context(ctx); -- cgit v1.2.3 From fc38a3cfe84e4e79af43f29d236748120789a286 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 23 Oct 2009 00:40:41 -0400 Subject: r600: fix render size prediction --- src/mesa/drivers/dri/r600/r700_chip.c | 4 ++-- src/mesa/drivers/dri/r600/r700_render.c | 35 +++++++++++++++---------------- src/mesa/drivers/dri/r600/r700_vertprog.c | 1 + 3 files changed, 20 insertions(+), 20 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 3b7f6fffe0..3ebc53d94f 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -210,8 +210,8 @@ static void r700SetupVTXConstants(GLcontext * ctx, extern int getTypeSize(GLenum type); static void r700SetupVTXConstants2(GLcontext * ctx, - void * pAos, - StreamDesc * pStreamDesc) + void * pAos, + StreamDesc * pStreamDesc) { context_t *context = R700_CONTEXT(ctx); struct radeon_aos * paos = (struct radeon_aos *)pAos; diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 71f95a19c0..c2e7680eae 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -375,38 +375,38 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim /* start 3d, idle, cb/db flush */ #define PRE_EMIT_STATE_BUFSZ 10 + 5 + 14 -static GLuint r700PredictRenderSize(GLcontext* ctx, GLuint nr_prims) +static GLuint r700PredictRenderSize(GLcontext* ctx, + const struct _mesa_prim *prim, + const struct _mesa_index_buffer *ib, + GLuint nr_prims) { context_t *context = R700_CONTEXT(ctx); - struct r700_vertex_program *vp = context->selected_vp; GLboolean flushed; GLuint dwords, i; GLuint state_size; - /* pre calculate aos count so state prediction works */ - context->radeon.tcl.aos_count = _mesa_bitcount(vp->mesa_program->Base.InputsRead); dwords = PRE_EMIT_STATE_BUFSZ; - if (nr_prims) + if (ib) dwords += nr_prims * 14; else { - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *vb = &tnl->vb; - - for (i = 0; i < vb->PrimitiveCount; i++) - dwords += vb->Primitive[i].count + 10; + for (i = 0; i < nr_prims; ++i) + { + dwords += prim[i].count + 10; + } } + state_size = radeonCountStateEmitSize(&context->radeon); flushed = rcommonEnsureCmdBufSpace(&context->radeon, - dwords + state_size, __FUNCTION__); - + dwords + state_size, + __FUNCTION__); if (flushed) - dwords += radeonCountStateEmitSize(&context->radeon); + dwords += radeonCountStateEmitSize(&context->radeon); else - dwords += state_size; + dwords += state_size; - radeon_print(RADEON_RENDER, RADEON_VERBOSE, - "%s: total prediction size is %d.\n", __FUNCTION__, dwords); + radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s: total prediction size is %d.\n", __FUNCTION__, dwords); return dwords; + } #define CONVERT( TYPE, MACRO ) do { \ @@ -653,7 +653,6 @@ static void r700SetupStreams2(GLcontext *ctx, const struct gl_client_array *inpu } } - context->radeon.tcl.aos_count = context->nNumActiveAos; ret = radeon_cs_space_check_with_bo(context->radeon.cmdbuf.cs, first_elem(&context->radeon.dma.reserved)->bo, RADEON_GEM_DOMAIN_GTT, 0); @@ -842,7 +841,7 @@ static GLboolean r700TryDrawPrims(GLcontext *ctx, r700SetupFragmentProgram(ctx); r600UpdateTextureState(ctx); - GLuint emit_end = r700PredictRenderSize(ctx, nr_prims) + GLuint emit_end = r700PredictRenderSize(ctx, prim, ib, nr_prims) + context->radeon.cmdbuf.cs->cdw; r700SetupIndexBuffer(ctx, ib); diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index d12c39c9f7..65c2c3f811 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -580,6 +580,7 @@ void r700SetVertexFormat(GLcontext *ctx, const struct gl_client_array *arrays[], unBit >>= 1; ++unLoc; } + context->radeon.tcl.aos_count = context->nNumActiveAos; } void * r700GetActiveVpShaderBo(GLcontext * ctx) -- cgit v1.2.3 From 45eb9d2f6dced7654291cabb4b8dd02a695db694 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 23 Oct 2009 01:00:23 -0400 Subject: r600: remove remains of old tnl pipeline --- src/mesa/drivers/dri/r600/r600_context.h | 30 -------- src/mesa/drivers/dri/r600/r700_chip.c | 121 ++---------------------------- src/mesa/drivers/dri/r600/r700_render.c | 6 +- src/mesa/drivers/dri/r600/r700_shader.h | 1 + src/mesa/drivers/dri/r600/r700_state.c | 40 +--------- src/mesa/drivers/dri/r600/r700_vertprog.c | 103 ++++++------------------- src/mesa/drivers/dri/r600/r700_vertprog.h | 8 +- 7 files changed, 41 insertions(+), 268 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index 7f68820fda..394fd757d4 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -58,29 +58,6 @@ typedef struct r600_context context_t; #include "main/mm.h" -/************ DMA BUFFERS **************/ - -/* The blit width for texture uploads - */ -#define R600_BLIT_WIDTH_BYTES 1024 -#define R600_MAX_TEXTURE_UNITS 8 - -struct r600_texture_state { - int tc_count; /* number of incoming texture coordinates from VAP */ -}; - -/* Perhaps more if we store programs in vmem? */ -/* drm_r600_cmd_header_t->vpu->count is unsigned char */ -#define VSF_MAX_FRAGMENT_LENGTH (255*4) - -/* Can be tested with colormat currently. */ -#define VSF_MAX_FRAGMENT_TEMPS (14) - -#define STATE_R600_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0) -#define STATE_R600_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1) - -extern int hw_tcl_on; - #define COLOR_IS_RGBA #define TAG(x) r600##x #include "tnl_dd/t_dd_vertex.h" @@ -167,9 +144,6 @@ struct r600_context { /* Vertex buffers */ - GLvector4f dummy_attrib[_TNL_ATTRIB_MAX]; - GLvector4f *temp_attrib[_TNL_ATTRIB_MAX]; - GLint nNumActiveAos; StreamDesc stream_desc[VERT_ATTRIB_MAX]; struct r700_index_buffer ind_buf; @@ -203,7 +177,6 @@ extern GLboolean r700SyncSurf(context_t *context, uint32_t write_domain, uint32_t sync_type); -extern void r700SetupStreams(GLcontext * ctx); extern void r700Start3D(context_t *context); extern void r600InitAtoms(context_t *context); extern void r700InitDraw(GLcontext *ctx); @@ -213,7 +186,4 @@ extern void r700InitDraw(GLcontext *ctx); #define RADEON_D_PLAYBACK_RAW 2 #define RADEON_D_T 3 -#define r600PackFloat32 radeonPackFloat32 -#define r600PackFloat24 radeonPackFloat24 - #endif /* __R600_CONTEXT_H__ */ diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 3ebc53d94f..75b97c56cd 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -141,77 +141,10 @@ static void r700SendTexBorderColorState(GLcontext *ctx, struct radeon_state_atom } } +extern int getTypeSize(GLenum type); static void r700SetupVTXConstants(GLcontext * ctx, - unsigned int nStreamID, void * pAos, - unsigned int size, /* number of elements in vector */ - unsigned int stride, - unsigned int count) /* number of vectors in stream */ -{ - context_t *context = R700_CONTEXT(ctx); - struct radeon_aos * paos = (struct radeon_aos *)pAos; - BATCH_LOCALS(&context->radeon); - radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); - - unsigned int uSQ_VTX_CONSTANT_WORD0_0; - unsigned int uSQ_VTX_CONSTANT_WORD1_0; - unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0; - unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0; - unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0; - - if (!paos->bo) - return; - - if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) || - (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) || - (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) || - (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) || - (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710)) - r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit); - else - r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit); - - uSQ_VTX_CONSTANT_WORD0_0 = paos->offset; - uSQ_VTX_CONSTANT_WORD1_0 = count * (size * 4) - 1; - - SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); /* TODO */ - SETfield(uSQ_VTX_CONSTANT_WORD2_0, stride, SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift, - SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask); - SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(GL_FLOAT, size, NULL), - SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift, - SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); /* TODO : trace back api for initial data type, not only GL_FLOAT */ - SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_SCALED, - SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask); - SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit); - - SETfield(uSQ_VTX_CONSTANT_WORD3_0, 1, MEM_REQUEST_SIZE_shift, MEM_REQUEST_SIZE_mask); - SETfield(uSQ_VTX_CONSTANT_WORD6_0, SQ_TEX_VTX_VALID_BUFFER, - SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask); - - BEGIN_BATCH_NO_AUTOSTATE(9 + 2); - - R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); - R600_OUT_BATCH((nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE); - R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0); - R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0); - R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0); - R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0); - R600_OUT_BATCH(0); - R600_OUT_BATCH(0); - R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0); - R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0, - paos->bo, - uSQ_VTX_CONSTANT_WORD0_0, - RADEON_GEM_DOMAIN_GTT, 0, 0); - END_BATCH(); - COMMIT_BATCH(); - -} - -extern int getTypeSize(GLenum type); -static void r700SetupVTXConstants2(GLcontext * ctx, - void * pAos, - StreamDesc * pStreamDesc) + StreamDesc * pStreamDesc) { context_t *context = R700_CONTEXT(ctx); struct radeon_aos * paos = (struct radeon_aos *)pAos; @@ -295,31 +228,6 @@ static void r700SetupVTXConstants2(GLcontext * ctx, } -void r700SetupStreams(GLcontext *ctx) -{ - context_t *context = R700_CONTEXT(ctx); - struct r700_vertex_program *vp = context->selected_vp; - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *vb = &tnl->vb; - unsigned int i, j = 0; - radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); - - R600_STATECHANGE(context, vtx); - - for(i=0; imesa_program->Base.InputsRead & (1 << i)) { - rcommon_emit_vector(ctx, - &context->radeon.tcl.aos[j], - vb->AttribPtr[i]->data, - vb->AttribPtr[i]->size, - vb->AttribPtr[i]->stride, - vb->Count); - j++; - } - } - context->radeon.tcl.aos_count = j; -} - static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom) { context_t *context = R700_CONTEXT(ctx); @@ -343,25 +251,12 @@ static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); for(i=0; imesa_program->Base.InputsRead & (1 << i)) - { - if(1 == context->selected_vp->uiVersion) - { - /* currently aos are packed */ - r700SetupVTXConstants(ctx, - i, - (void*)(&context->radeon.tcl.aos[j]), - (unsigned int)context->radeon.tcl.aos[j].components, - (unsigned int)context->radeon.tcl.aos[j].stride * 4, - (unsigned int)context->radeon.tcl.aos[j].count); - } - else - { /* context->selected_vp->uiVersion == 2 : aos not always packed */ - r700SetupVTXConstants2(ctx, - (void*)(&context->radeon.tcl.aos[j]), - &(context->stream_desc[j])); - } - j++; + if(vp->mesa_program->Base.InputsRead & (1 << i)) + { + r700SetupVTXConstants(ctx, + (void*)(&context->radeon.tcl.aos[j]), + &(context->stream_desc[j])); + j++; } } } diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index c2e7680eae..3e1ce9fb72 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -550,7 +550,7 @@ static void r700AlignDataToDword(GLcontext *ctx, attr->stride = dst_stride; } -static void r700SetupStreams2(GLcontext *ctx, const struct gl_client_array *input[], int count) +static void r700SetupStreams(GLcontext *ctx, const struct gl_client_array *input[], int count) { context_t *context = R700_CONTEXT(ctx); GLuint stride; @@ -825,7 +825,7 @@ static GLboolean r700TryDrawPrims(GLcontext *ctx, _tnl_UpdateFixedFunctionProgram(ctx); r700SetVertexFormat(ctx, arrays, max_index + 1); /* shaders need to be updated before buffers are validated */ - r700UpdateShaders2(ctx); + r700UpdateShaders(ctx); if (!r600ValidateBuffers(ctx)) return GL_FALSE; @@ -845,7 +845,7 @@ static GLboolean r700TryDrawPrims(GLcontext *ctx, + context->radeon.cmdbuf.cs->cdw; r700SetupIndexBuffer(ctx, ib); - r700SetupStreams2(ctx, arrays, max_index + 1); + r700SetupStreams(ctx, arrays, max_index + 1); radeonEmitState(radeon); diff --git a/src/mesa/drivers/dri/r600/r700_shader.h b/src/mesa/drivers/dri/r600/r700_shader.h index 997cb05aaf..c6a058617e 100644 --- a/src/mesa/drivers/dri/r600/r700_shader.h +++ b/src/mesa/drivers/dri/r600/r700_shader.h @@ -128,6 +128,7 @@ typedef struct R700_Shader //Internal void AddInstToList(TypedShaderList * plstCFInstructions, R700ShaderInstruction * pInst); +void TakeInstOutFromList(TypedShaderList * plstCFInstructions, R700ShaderInstruction * pInst); void ResolveLinks(R700_Shader *pShader); void Assemble(R700_Shader *pShader); diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 3d3c8b958f..9a6a68a68c 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -61,12 +61,9 @@ static void r700UpdatePolygonMode(GLcontext * ctx); static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state); static void r700SetStencilState(GLcontext * ctx, GLboolean state); -void r700UpdateShaders (GLcontext * ctx) //---------------------------------- +void r700UpdateShaders(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); - GLvector4f dummy_attrib[_TNL_ATTRIB_MAX]; - GLvector4f *temp_attrib[_TNL_ATTRIB_MAX]; - int i; /* should only happenen once, just after context is created */ /* TODO: shouldn't we fallback to sw here? */ @@ -77,40 +74,7 @@ void r700UpdateShaders (GLcontext * ctx) //---------------------------------- r700SelectFragmentShader(ctx); - if (context->radeon.NewGLState) { - for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) { - /* mat states from state var not array for sw */ - dummy_attrib[i].stride = 0; - temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i]; - TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]); - } - - _tnl_UpdateFixedFunctionProgram(ctx); - - for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) { - TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i]; - } - } - - r700SelectVertexShader(ctx, 1); - r700UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS); - context->radeon.NewGLState = 0; -} - -void r700UpdateShaders2(GLcontext * ctx) -{ - context_t *context = R700_CONTEXT(ctx); - - /* should only happenen once, just after context is created */ - /* TODO: shouldn't we fallback to sw here? */ - if (!ctx->FragmentProgram._Current) { - _mesa_fprintf(stderr, "No ctx->FragmentProgram._Current!!\n"); - return; - } - - r700SelectFragmentShader(ctx); - - r700SelectVertexShader(ctx, 2); + r700SelectVertexShader(ctx); r700UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS); context->radeon.NewGLState = 0; } diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index 65c2c3f811..c84b0ac059 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -203,22 +203,11 @@ void Map_Vertex_Program(GLcontext *ctx, pAsm->number_used_registers += num_inputs; // Create VFETCH instructions for inputs - if(1 == vp->uiVersion) - { - if (GL_TRUE != Process_Vertex_Program_Vfetch_Instructions(vp, mesa_vp) ) - { - radeon_error("Calling Process_Vertex_Program_Vfetch_Instructions return error. \n"); - return; - } - } - else - { - if (GL_TRUE != Process_Vertex_Program_Vfetch_Instructions2(ctx, vp, mesa_vp) ) - { - radeon_error("Calling Process_Vertex_Program_Vfetch_Instructions2 return error. \n"); - return; - } - } + if (GL_TRUE != Process_Vertex_Program_Vfetch_Instructions2(ctx, vp, mesa_vp) ) + { + radeon_error("Calling Process_Vertex_Program_Vfetch_Instructions2 return error. \n"); + return; + } // Map Outputs pAsm->number_of_exports = Map_Vertex_Output(pAsm, mesa_vp, pAsm->number_used_registers); @@ -228,7 +217,7 @@ void Map_Vertex_Program(GLcontext *ctx, pAsm->number_used_registers += pAsm->number_of_exports; pAsm->pucOutMask = (unsigned char*) MALLOC(pAsm->number_of_exports); - + for(ui=0; uinumber_of_exports; ui++) { pAsm->pucOutMask[ui] = 0x0; @@ -245,7 +234,7 @@ void Map_Vertex_Program(GLcontext *ctx, { /* fix func t_vp uses NumTemporaries */ pAsm->number_used_registers += mesa_vp->Base.NumTemporaries; } - + pAsm->uFirstHelpReg = pAsm->number_used_registers; } @@ -300,18 +289,13 @@ GLboolean Find_Instruction_Dependencies_vp(struct r700_vertex_program *vp, } struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, - struct gl_vertex_program *mesa_vp, - GLint nVer) + struct gl_vertex_program *mesa_vp) { context_t *context = R700_CONTEXT(ctx); struct r700_vertex_program *vp; - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *vb = &tnl->vb; - unsigned int unBit; unsigned int i; vp = _mesa_calloc(sizeof(*vp)); - vp->uiVersion = nVer; vp->mesa_program = (struct gl_vertex_program *)_mesa_clone_program(ctx, &mesa_vp->Base); if (mesa_vp->IsPositionInvariant) @@ -319,29 +303,13 @@ struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, _mesa_insert_mvp_code(ctx, vp->mesa_program); } - if( 1 == nVer ) + for(i=0; inNumActiveAos; i++) { - for(i=0; imesa_program->Base.InputsRead & unBit) /* ctx->Array.ArrayObj->xxxxxxx */ - { - vp->aos_desc[i].size = vb->AttribPtr[i]->size; - vp->aos_desc[i].stride = vb->AttribPtr[i]->size * sizeof(GL_FLOAT);/* when emit array, data is packed. vb->AttribPtr[i]->stride;*/ - vp->aos_desc[i].type = GL_FLOAT; - } - } + vp->aos_desc[i].size = context->stream_desc[i].size; + vp->aos_desc[i].stride = context->stream_desc[i].stride; + vp->aos_desc[i].type = context->stream_desc[i].type; } - else - { - for(i=0; inNumActiveAos; i++) - { - vp->aos_desc[i].size = context->stream_desc[i].size; - vp->aos_desc[i].stride = context->stream_desc[i].stride; - vp->aos_desc[i].type = context->stream_desc[i].type; - } - } - + if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) { vp->r700AsmCode.bR6xx = 1; @@ -354,14 +322,14 @@ struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, if(GL_FALSE == Find_Instruction_Dependencies_vp(vp, vp->mesa_program)) { return NULL; - } + } if(GL_FALSE == AssembleInstr(vp->mesa_program->Base.NumInstructions, - &(vp->mesa_program->Base.Instructions[0]), + &(vp->mesa_program->Base.Instructions[0]), &(vp->r700AsmCode)) ) { return NULL; - } + } if(GL_FALSE == Process_Vertex_Exports(&(vp->r700AsmCode), vp->mesa_program->Base.OutputsWritten) ) { @@ -378,14 +346,11 @@ struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, return vp; } -void r700SelectVertexShader(GLcontext *ctx, GLint nVersion) +void r700SelectVertexShader(GLcontext *ctx) { context_t *context = R700_CONTEXT(ctx); struct r700_vertex_program_cont *vpc; struct r700_vertex_program *vp; - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *vb = &tnl->vb; - unsigned int unBit; unsigned int i; GLboolean match; GLbitfield InputsRead; @@ -396,47 +361,27 @@ void r700SelectVertexShader(GLcontext *ctx, GLint nVersion) if (vpc->mesa_program.IsPositionInvariant) { InputsRead |= VERT_BIT_POS; - } - + } + for (vp = vpc->progs; vp; vp = vp->next) { - if (vp->uiVersion != nVersion ) - continue; - match = GL_TRUE; - if ( 1 == nVersion ) + match = GL_TRUE; + for(i=0; inNumActiveAos; i++) { - for(i=0; iaos_desc[i].size != context->stream_desc[i].size) { - if (vp->aos_desc[i].size != vb->AttribPtr[i]->size) - { match = GL_FALSE; break; - } } - } } - else - { - for(i=0; inNumActiveAos; i++) - { - if (vp->aos_desc[i].size != context->stream_desc[i].size) - { - match = GL_FALSE; - break; - } - } - } - if (match) + if (match) { context->selected_vp = vp; return; } } - vp = r700TranslateVertexShader(ctx, &(vpc->mesa_program), nVersion); + vp = r700TranslateVertexShader(ctx, &(vpc->mesa_program)); if(!vp) { radeon_error("Failed to translate vertex shader. \n"); diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.h b/src/mesa/drivers/dri/r600/r700_vertprog.h index f9a3e395ee..00824c29d3 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.h +++ b/src/mesa/drivers/dri/r600/r700_vertprog.h @@ -52,8 +52,7 @@ struct r700_vertex_program GLboolean translated; GLboolean loaded; - GLint uiVersion; - + void * shaderbo; ArrayDesc aos_desc[VERT_ATTRIB_MAX]; @@ -87,11 +86,10 @@ GLboolean Find_Instruction_Dependencies_vp(struct r700_vertex_program *vp, struct gl_vertex_program *mesa_vp); struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, - struct gl_vertex_program *mesa_vp, - GLint nVer); + struct gl_vertex_program *mesa_vp); /* Interface */ -extern void r700SelectVertexShader(GLcontext *ctx, GLint nVersion); +extern void r700SelectVertexShader(GLcontext *ctx); extern void r700SetVertexFormat(GLcontext *ctx, const struct gl_client_array *arrays[], int count); extern GLboolean r700SetupVertexProgram(GLcontext * ctx); -- cgit v1.2.3 From 738b394769bb95036635f7a00a1ef08890c5be63 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Fri, 23 Oct 2009 14:25:09 +0300 Subject: r600: for position invariant programs reading vert_pos is not always known at this point --- src/mesa/drivers/dri/r600/r700_vertprog.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index c84b0ac059..ffc6068bd8 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -515,6 +515,11 @@ void r700SetVertexFormat(GLcontext *ctx, const struct gl_client_array *arrays[], unsigned int unBit = mesa_vp->Base.InputsRead; context->nNumActiveAos = 0; + if (mesa_vp->IsPositionInvariant) + { + unBit |= VERT_BIT_POS; + } + while(unBit) { if(unBit & 1) -- cgit v1.2.3 From d4d4733e6c312f2a8e9977b06fc554904407c456 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Fri, 23 Oct 2009 16:44:31 +0300 Subject: r600: remove duplicate stride setting Stride is set already in r700SetVertexFormat and there it works correctly for 0 also --- src/mesa/drivers/dri/r600/r700_render.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 3e1ce9fb72..9cf984f966 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -618,19 +618,15 @@ static void r700SetupStreams(GLcontext *ctx, const struct gl_client_array *input { case 1: radeonEmitVec4(dst, input[i]->Ptr, input[i]->StrideB, local_count); - context->stream_desc[index].stride = 4; break; case 2: radeonEmitVec8(dst, input[i]->Ptr, input[i]->StrideB, local_count); - context->stream_desc[index].stride = 8; break; case 3: radeonEmitVec12(dst, input[i]->Ptr, input[i]->StrideB, local_count); - context->stream_desc[index].stride = 12; break; case 4: radeonEmitVec16(dst, input[i]->Ptr, input[i]->StrideB, local_count); - context->stream_desc[index].stride = 16; break; default: assert(0); -- cgit v1.2.3 From 17ef1f6074d6107c167f1956a5c60993904c0b72 Mon Sep 17 00:00:00 2001 From: Chia-I Wu Date: Thu, 8 Oct 2009 10:33:57 +0800 Subject: mesa: Enable remap table in core. This enables the remap table in core. driInitExtensions is adapted to use the remap table. All uses of extension_helper.h are replaced by remap_helper.h. The chicken-egg problem of the DRI drivers is also solved. It is now also possible to pass NULL extensions to driInitExtensions. It will cause driInitExtensions to map all known functions. This functionality is used by software drivers and EGL_i915. Signed-off-by: Chia-I Wu --- src/gallium/state_trackers/dri/dri_extensions.c | 10 ++- src/gallium/state_trackers/dri/dri_screen.c | 5 -- src/gallium/state_trackers/egl/egl_context.c | 67 ------------------ src/gallium/state_trackers/egl/egl_tracker.c | 4 +- src/mesa/drivers/dri/common/utils.c | 94 +++++-------------------- src/mesa/drivers/dri/common/utils.h | 32 +-------- src/mesa/drivers/dri/i810/i810context.c | 2 +- src/mesa/drivers/dri/i810/i810screen.c | 4 -- src/mesa/drivers/dri/intel/intel_extensions.c | 3 +- src/mesa/drivers/dri/intel/intel_screen.c | 24 ------- src/mesa/drivers/dri/mach64/mach64_context.c | 2 +- src/mesa/drivers/dri/mach64/mach64_screen.c | 14 ---- src/mesa/drivers/dri/mga/mga_xmesa.c | 18 +---- src/mesa/drivers/dri/r128/r128_context.c | 4 +- src/mesa/drivers/dri/r128/r128_screen.c | 14 ---- src/mesa/drivers/dri/r200/r200_context.c | 16 ++--- src/mesa/drivers/dri/r300/r300_context.c | 8 +-- src/mesa/drivers/dri/r600/r600_context.c | 8 +-- src/mesa/drivers/dri/radeon/radeon_context.c | 6 +- src/mesa/drivers/dri/radeon/radeon_screen.c | 54 -------------- src/mesa/drivers/dri/savage/savage_xmesa.c | 14 +--- src/mesa/drivers/dri/sis/sis_context.c | 6 +- src/mesa/drivers/dri/sis/sis_screen.c | 12 ---- src/mesa/drivers/dri/swrast/swrast.c | 74 +------------------ src/mesa/drivers/dri/tdfx/tdfx_context.c | 6 +- src/mesa/drivers/dri/tdfx/tdfx_screen.c | 16 ----- src/mesa/drivers/dri/unichrome/via_context.c | 4 +- src/mesa/drivers/dri/unichrome/via_screen.c | 14 ---- src/mesa/drivers/x11/xm_api.c | 73 ------------------- src/mesa/main/context.c | 3 + src/mesa/sources.mak | 1 + 31 files changed, 66 insertions(+), 546 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/gallium/state_trackers/dri/dri_extensions.c b/src/gallium/state_trackers/dri/dri_extensions.c index 800d462e32..78c4cd8375 100644 --- a/src/gallium/state_trackers/dri/dri_extensions.c +++ b/src/gallium/state_trackers/dri/dri_extensions.c @@ -59,12 +59,13 @@ #define need_GL_NV_vertex_program #define need_GL_VERSION_2_0 #define need_GL_VERSION_2_1 -#include "extension_helper.h" +#include "main/remap_helper.h" +#include "utils.h" /** * Extension strings exported by the driver. */ -const struct dri_extension card_extensions[] = { +static const struct dri_extension card_extensions[] = { {"GL_ARB_fragment_shader", NULL}, {"GL_ARB_map_buffer_range", GL_ARB_map_buffer_range_functions}, {"GL_ARB_multisample", GL_ARB_multisample_functions}, @@ -127,10 +128,7 @@ dri_init_extensions(struct dri_context *ctx) * capabilities of the pipe_screen. This is actually something * that can/should be done inside st_create_context(). */ - if (ctx) - driInitExtensions(ctx->st->ctx, card_extensions, GL_TRUE); - else - driInitExtensions(NULL, card_extensions, GL_FALSE); + driInitExtensions(ctx->st->ctx, card_extensions, GL_TRUE); } /* vim: set sw=3 ts=8 sts=3 expandtab: */ diff --git a/src/gallium/state_trackers/dri/dri_screen.c b/src/gallium/state_trackers/dri/dri_screen.c index 884b6d5011..cb864d45d5 100644 --- a/src/gallium/state_trackers/dri/dri_screen.c +++ b/src/gallium/state_trackers/dri/dri_screen.c @@ -226,8 +226,6 @@ dri_init_screen(__DRIscreenPrivate * sPriv) const __DRIconfig **configs; struct dri1_create_screen_arg arg; - dri_init_extensions(NULL); - screen = CALLOC_STRUCT(dri_screen); if (!screen) return NULL; @@ -292,9 +290,6 @@ dri_init_screen2(__DRIscreenPrivate * sPriv) struct dri_screen *screen; struct drm_create_screen_arg arg; - /* Set up dispatch table to cope with all known extensions */ - dri_init_extensions(NULL); - screen = CALLOC_STRUCT(dri_screen); if (!screen) goto fail; diff --git a/src/gallium/state_trackers/egl/egl_context.c b/src/gallium/state_trackers/egl/egl_context.c index e21a4a1095..fee186c601 100644 --- a/src/gallium/state_trackers/egl/egl_context.c +++ b/src/gallium/state_trackers/egl/egl_context.c @@ -16,73 +16,6 @@ #include "GL/internal/glcore.h" -#define need_GL_ARB_multisample -#define need_GL_ARB_point_parameters -#define need_GL_ARB_texture_compression -#define need_GL_ARB_vertex_buffer_object -#define need_GL_ARB_vertex_program -#define need_GL_ARB_window_pos -#define need_GL_EXT_blend_color -#define need_GL_EXT_blend_equation_separate -#define need_GL_EXT_blend_func_separate -#define need_GL_EXT_blend_minmax -#define need_GL_EXT_cull_vertex -#define need_GL_EXT_fog_coord -#define need_GL_EXT_framebuffer_object -#define need_GL_EXT_multi_draw_arrays -#define need_GL_EXT_secondary_color -#define need_GL_NV_vertex_program -#include "extension_helper.h" - -/** - * TODO HACK! FUGLY! - * Copied for intel extentions. - */ -const struct dri_extension card_extensions[] = { - {"GL_ARB_multisample", GL_ARB_multisample_functions}, - {"GL_ARB_multitexture", NULL}, - {"GL_ARB_point_parameters", GL_ARB_point_parameters_functions}, - {"GL_ARB_texture_border_clamp", NULL}, - {"GL_ARB_texture_compression", GL_ARB_texture_compression_functions}, - {"GL_ARB_texture_cube_map", NULL}, - {"GL_ARB_texture_env_add", NULL}, - {"GL_ARB_texture_env_combine", NULL}, - {"GL_ARB_texture_env_dot3", NULL}, - {"GL_ARB_texture_mirrored_repeat", NULL}, - {"GL_ARB_texture_rectangle", NULL}, - {"GL_ARB_vertex_buffer_object", GL_ARB_vertex_buffer_object_functions}, - {"GL_ARB_pixel_buffer_object", NULL}, - {"GL_ARB_vertex_program", GL_ARB_vertex_program_functions}, - {"GL_ARB_window_pos", GL_ARB_window_pos_functions}, - {"GL_EXT_blend_color", GL_EXT_blend_color_functions}, - {"GL_EXT_blend_equation_separate", GL_EXT_blend_equation_separate_functions}, - {"GL_EXT_blend_func_separate", GL_EXT_blend_func_separate_functions}, - {"GL_EXT_blend_minmax", GL_EXT_blend_minmax_functions}, - {"GL_EXT_blend_subtract", NULL}, - {"GL_EXT_cull_vertex", GL_EXT_cull_vertex_functions}, - {"GL_EXT_fog_coord", GL_EXT_fog_coord_functions}, - {"GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions}, - {"GL_EXT_multi_draw_arrays", GL_EXT_multi_draw_arrays_functions}, - {"GL_EXT_packed_depth_stencil", NULL}, - {"GL_EXT_pixel_buffer_object", NULL}, - {"GL_EXT_secondary_color", GL_EXT_secondary_color_functions}, - {"GL_EXT_stencil_wrap", NULL}, - {"GL_EXT_texture_edge_clamp", NULL}, - {"GL_EXT_texture_env_combine", NULL}, - {"GL_EXT_texture_env_dot3", NULL}, - {"GL_EXT_texture_filter_anisotropic", NULL}, - {"GL_EXT_texture_lod_bias", NULL}, - {"GL_3DFX_texture_compression_FXT1", NULL}, - {"GL_APPLE_client_storage", NULL}, - {"GL_MESA_pack_invert", NULL}, - {"GL_MESA_ycbcr_texture", NULL}, - {"GL_NV_blend_square", NULL}, - {"GL_NV_vertex_program", GL_NV_vertex_program_functions}, - {"GL_NV_vertex_program1_1", NULL}, - {"GL_SGIS_generate_mipmap", NULL }, - {NULL, NULL} -}; - _EGLContext * drm_create_context(_EGLDriver *drv, _EGLDisplay *dpy, _EGLConfig *conf, _EGLContext *share_list, const EGLint *attrib_list) { diff --git a/src/gallium/state_trackers/egl/egl_tracker.c b/src/gallium/state_trackers/egl/egl_tracker.c index 5140755001..8d29bf490b 100644 --- a/src/gallium/state_trackers/egl/egl_tracker.c +++ b/src/gallium/state_trackers/egl/egl_tracker.c @@ -16,7 +16,6 @@ /** HACK */ void* driDriverAPI; -extern const struct dri_extension card_extensions[]; /* @@ -168,8 +167,7 @@ drm_initialize(_EGLDriver *drv, _EGLDisplay *disp, EGLint *major, EGLint *minor) goto err_screen; dev->winsys = dev->screen->winsys; - /* TODO HACK */ - driInitExtensions(NULL, card_extensions, GL_FALSE); + driInitExtensions(NULL, NULL, GL_FALSE); drm_update_res(dev); res = dev->res; diff --git a/src/mesa/drivers/dri/common/utils.c b/src/mesa/drivers/dri/common/utils.c index 66f277c10b..b272eb74ea 100644 --- a/src/mesa/drivers/dri/common/utils.c +++ b/src/mesa/drivers/dri/common/utils.c @@ -38,9 +38,6 @@ #include "utils.h" -int driDispatchRemapTable[ driDispatchRemapTable_size ]; - - unsigned driParseDebugString( const char * debug, const struct dri_debug_control * control ) @@ -142,7 +139,7 @@ driGetRendererString( char * buffer, const char * hardware_name, #define need_GL_EXT_blend_func_separate #define need_GL_NV_vertex_program -#include "extension_helper.h" +#include "main/remap_helper.h" static const struct dri_extension all_mesa_extensions[] = { { "GL_ARB_draw_buffers", GL_ARB_draw_buffers_functions }, @@ -165,8 +162,12 @@ static const struct dri_extension all_mesa_extensions[] = { /** - * Enable extensions supported by the driver. + * Enable and map extensions supported by the driver. * + * When ctx is NULL, extensions are not enabled, but their functions + * are still mapped. When extensions_to_enable is NULL, all static + * functions known to mesa core are mapped. + * * \bug * ARB_imaging isn't handled properly. In Mesa, enabling ARB_imaging also * enables all the sub-extensions that are folded into it. This means that @@ -181,18 +182,23 @@ void driInitExtensions( GLcontext * ctx, unsigned i; if ( first_time ) { - for ( i = 0 ; i < driDispatchRemapTable_size ; i++ ) { - driDispatchRemapTable[i] = -1; - } - first_time = 0; - driInitExtensions( ctx, all_mesa_extensions, GL_FALSE ); + driInitExtensions( NULL, all_mesa_extensions, GL_FALSE ); } if ( (ctx != NULL) && enable_imaging ) { _mesa_enable_imaging_extensions( ctx ); } + /* The caller is too lazy to list any extension */ + if ( extensions_to_enable == NULL ) { + /* Map the static functions. Together with those mapped by remap + * table, this should cover everything mesa core knows. + */ + _mesa_map_static_functions(); + return; + } + for ( i = 0 ; extensions_to_enable[i].name != NULL ; i++ ) { driInitSingleExtension( ctx, & extensions_to_enable[i] ); } @@ -202,80 +208,18 @@ void driInitExtensions( GLcontext * ctx, /** - * Enable and add dispatch functions for a single extension + * Enable and map functions for a single extension * * \param ctx Context where extension is to be enabled. * \param ext Extension that is to be enabled. * - * \sa driInitExtensions, _mesa_enable_extension, _glapi_add_entrypoint - * - * \todo - * Determine if it would be better to use \c strlen instead of the hardcoded - * for-loops. + * \sa driInitExtensions, _mesa_enable_extension, _mesa_map_function_array */ void driInitSingleExtension( GLcontext * ctx, const struct dri_extension * ext ) { - unsigned i; - - if ( ext->functions != NULL ) { - for ( i = 0 ; ext->functions[i].strings != NULL ; i++ ) { - const char * functions[16]; - const char * parameter_signature; - const char * str = ext->functions[i].strings; - unsigned j; - unsigned offset; - - - /* Separate the parameter signature from the rest of the string. - * If the parameter signature is empty (i.e., the string starts - * with a NUL character), then the function has a void parameter - * list. - */ - parameter_signature = str; - while ( str[0] != '\0' ) { - str++; - } - str++; - - - /* Divide the string into the substrings that name each - * entry-point for the function. - */ - for ( j = 0 ; j < 16 ; j++ ) { - if ( str[0] == '\0' ) { - functions[j] = NULL; - break; - } - - functions[j] = str; - - while ( str[0] != '\0' ) { - str++; - } - str++; - } - - - /* Add each entry-point to the dispatch table. - */ - offset = _glapi_add_dispatch( functions, parameter_signature ); - if (offset == -1) { -#if 0 /* this causes noise with egl */ - fprintf(stderr, "DISPATCH ERROR! _glapi_add_dispatch failed " - "to add %s!\n", functions[0]); -#endif - } - else if (ext->functions[i].remap_index != -1) { - driDispatchRemapTable[ ext->functions[i].remap_index ] = - offset; - } - else if (ext->functions[i].offset != offset) { - fprintf(stderr, "DISPATCH ERROR! %s -> %u != %u\n", - functions[0], offset, ext->functions[i].offset); - } - } + _mesa_map_function_array(ext->functions); } if ( ctx != NULL ) { diff --git a/src/mesa/drivers/dri/common/utils.h b/src/mesa/drivers/dri/common/utils.h index 9e9e5bc224..2aa6de66c1 100644 --- a/src/mesa/drivers/dri/common/utils.h +++ b/src/mesa/drivers/dri/common/utils.h @@ -31,6 +31,7 @@ #include #include #include "main/context.h" +#include "main/remap.h" typedef struct __DRIutilversionRec2 __DRIutilversion2; @@ -39,35 +40,6 @@ struct dri_debug_control { unsigned flag; }; -/** - * Description of the entry-points and parameters for an OpenGL function. - */ -struct dri_extension_function { - /** - * \brief - * Packed string describing the parameter signature and the entry-point - * names. - * - * The parameter signature and the names of the entry-points for this - * function are packed into a single string. The substrings are - * separated by NUL characters. The whole string is terminated by - * two consecutive NUL characters. - */ - const char * strings; - - - /** - * Location in the remap table where the dispatch offset should be - * stored. - */ - int remap_index; - - /** - * Offset of the function in the dispatch table. - */ - int offset; -}; - /** * Description of the API for an extension to OpenGL. */ @@ -83,7 +55,7 @@ struct dri_extension { * is terminated by a structure with a \c NULL * \c dri_extension_function::strings pointer. */ - const struct dri_extension_function * functions; + const struct gl_function_remap * functions; }; /** diff --git a/src/mesa/drivers/dri/i810/i810context.c b/src/mesa/drivers/dri/i810/i810context.c index 6785655686..7311b2e765 100644 --- a/src/mesa/drivers/dri/i810/i810context.c +++ b/src/mesa/drivers/dri/i810/i810context.c @@ -116,7 +116,7 @@ static void i810BufferSize(GLframebuffer *buffer, GLuint *width, GLuint *height) /* Extension strings exported by the i810 driver. */ -const struct dri_extension card_extensions[] = +static const struct dri_extension card_extensions[] = { { "GL_ARB_multitexture", NULL }, { "GL_ARB_texture_env_add", NULL }, diff --git a/src/mesa/drivers/dri/i810/i810screen.c b/src/mesa/drivers/dri/i810/i810screen.c index 6e49f3466c..a9ee61132e 100644 --- a/src/mesa/drivers/dri/i810/i810screen.c +++ b/src/mesa/drivers/dri/i810/i810screen.c @@ -53,8 +53,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "GL/internal/dri_interface.h" -extern const struct dri_extension card_extensions[]; - static const __DRIconfig ** i810FillInModes( __DRIscreenPrivate *psp, unsigned pixel_bits, unsigned depth_bits, @@ -166,8 +164,6 @@ i810InitScreen(__DRIscreen *sPriv) return NULL; } - driInitExtensions( NULL, card_extensions, GL_TRUE ); - if (sPriv->devPrivSize != sizeof(I810DRIRec)) { fprintf(stderr,"\nERROR! sizeof(I810DRIRec) does not match passed size from device driver\n"); return GL_FALSE; diff --git a/src/mesa/drivers/dri/intel/intel_extensions.c b/src/mesa/drivers/dri/intel/intel_extensions.c index 2eb08a8f05..b6754c9fcb 100644 --- a/src/mesa/drivers/dri/intel/intel_extensions.c +++ b/src/mesa/drivers/dri/intel/intel_extensions.c @@ -28,6 +28,7 @@ #include "intel_chipset.h" #include "intel_context.h" #include "intel_extensions.h" +#include "utils.h" #define need_GL_ARB_copy_buffer @@ -63,7 +64,7 @@ #define need_GL_VERSION_2_0 #define need_GL_VERSION_2_1 -#include "extension_helper.h" +#include "main/remap_helper.h" /** diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index 24f7fbc992..41342ddcae 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -696,18 +696,6 @@ static const __DRIconfig **intelInitScreen(__DRIscreenPrivate *psp) return NULL; } - /* Calling driInitExtensions here, with a NULL context pointer, - * does not actually enable the extensions. It just makes sure - * that all the dispatch offsets for all the extensions that - * *might* be enables are known. This is needed because the - * dispatch offsets need to be known when _mesa_context_create is - * called, but we can't enable the extensions until we have a - * context pointer. - * - * Hello chicken. Hello egg. How are you two today? - */ - intelInitExtensions(NULL, GL_TRUE); - if (!intelInitDriver(psp)) return NULL; @@ -760,18 +748,6 @@ __DRIconfig **intelInitScreen2(__DRIscreenPrivate *psp) int color; __DRIconfig **configs = NULL; - /* Calling driInitExtensions here, with a NULL context pointer, - * does not actually enable the extensions. It just makes sure - * that all the dispatch offsets for all the extensions that - * *might* be enables are known. This is needed because the - * dispatch offsets need to be known when _mesa_context_create is - * called, but we can't enable the extensions until we have a - * context pointer. - * - * Hello chicken. Hello egg. How are you two today? - */ - intelInitExtensions(NULL, GL_TRUE); - /* Allocate the private area */ intelScreen = (intelScreenPrivate *) CALLOC(sizeof(intelScreenPrivate)); if (!intelScreen) { diff --git a/src/mesa/drivers/dri/mach64/mach64_context.c b/src/mesa/drivers/dri/mach64/mach64_context.c index 9c7f513c6f..2bca293b3c 100644 --- a/src/mesa/drivers/dri/mach64/mach64_context.c +++ b/src/mesa/drivers/dri/mach64/mach64_context.c @@ -76,7 +76,7 @@ static const struct dri_debug_control debug_control[] = { NULL, 0 } }; -const struct dri_extension card_extensions[] = +static const struct dri_extension card_extensions[] = { { "GL_ARB_multitexture", NULL }, { "GL_EXT_texture_edge_clamp", NULL }, diff --git a/src/mesa/drivers/dri/mach64/mach64_screen.c b/src/mesa/drivers/dri/mach64/mach64_screen.c index 6440027ca4..43aac899f7 100644 --- a/src/mesa/drivers/dri/mach64/mach64_screen.c +++ b/src/mesa/drivers/dri/mach64/mach64_screen.c @@ -67,8 +67,6 @@ static const GLuint __driNConfigOptions = 3; static const GLuint __driNConfigOptions = 2; #endif -extern const struct dri_extension card_extensions[]; - static const __DRIconfig ** mach64FillInModes( __DRIscreenPrivate *psp, unsigned pixel_bits, unsigned depth_bits, @@ -436,18 +434,6 @@ mach64InitScreen(__DRIscreenPrivate *psp) return NULL; } - /* Calling driInitExtensions here, with a NULL context pointer, - * does not actually enable the extensions. It just makes sure - * that all the dispatch offsets for all the extensions that - * *might* be enables are known. This is needed because the - * dispatch offsets need to be known when _mesa_context_create is - * called, but we can't enable the extensions until we have a - * context pointer. - * - * Hello chicken. Hello egg. How are you two today? - */ - driInitExtensions( NULL, card_extensions, GL_FALSE ); - if (!mach64InitDriver(psp)) return NULL; diff --git a/src/mesa/drivers/dri/mga/mga_xmesa.c b/src/mesa/drivers/dri/mga/mga_xmesa.c index 0dc76fea50..03fd9b6fc1 100644 --- a/src/mesa/drivers/dri/mga/mga_xmesa.c +++ b/src/mesa/drivers/dri/mga/mga_xmesa.c @@ -78,7 +78,7 @@ #endif #define need_GL_APPLE_vertex_array_object #define need_GL_NV_vertex_program -#include "extension_helper.h" +#include "main/remap_helper.h" /* MGA configuration */ @@ -945,22 +945,6 @@ static const __DRIconfig **mgaInitScreen(__DRIscreen *psp) return NULL; - /* Calling driInitExtensions here, with a NULL context pointer, - * does not actually enable the extensions. It just makes sure - * that all the dispatch offsets for all the extensions that - * *might* be enables are known. This is needed because the - * dispatch offsets need to be known when _mesa_context_create is - * called, but we can't enable the extensions until we have a - * context pointer. - * - * Hello chicken. Hello egg. How are you two today? - */ - - driInitExtensions( NULL, card_extensions, GL_FALSE ); - driInitExtensions( NULL, g400_extensions, GL_FALSE ); - driInitExtensions(NULL, ARB_vp_extensions, GL_FALSE); - driInitExtensions( NULL, NV_vp_extensions, GL_FALSE ); - if (!mgaInitDriver(psp)) return NULL; diff --git a/src/mesa/drivers/dri/r128/r128_context.c b/src/mesa/drivers/dri/r128/r128_context.c index f511a67bad..0b250876c5 100644 --- a/src/mesa/drivers/dri/r128/r128_context.c +++ b/src/mesa/drivers/dri/r128/r128_context.c @@ -68,9 +68,9 @@ int R128_DEBUG = 0; #define need_GL_EXT_blend_minmax #define need_GL_EXT_fog_coord #define need_GL_EXT_secondary_color -#include "extension_helper.h" +#include "main/remap_helper.h" -const struct dri_extension card_extensions[] = +static const struct dri_extension card_extensions[] = { { "GL_ARB_multitexture", NULL }, { "GL_ARB_texture_env_add", NULL }, diff --git a/src/mesa/drivers/dri/r128/r128_screen.c b/src/mesa/drivers/dri/r128/r128_screen.c index f5bcc2f290..a68b019776 100644 --- a/src/mesa/drivers/dri/r128/r128_screen.c +++ b/src/mesa/drivers/dri/r128/r128_screen.c @@ -74,8 +74,6 @@ static const GLuint __driNConfigOptions = 4; static const GLuint __driNConfigOptions = 3; #endif -extern const struct dri_extension card_extensions[]; - #if 1 /* Including xf86PciInfo.h introduces a bunch of errors... */ @@ -493,18 +491,6 @@ r128InitScreen(__DRIscreenPrivate *psp) &psp->drm_version, & drm_expected ) ) return NULL; - /* Calling driInitExtensions here, with a NULL context pointer, - * does not actually enable the extensions. It just makes sure - * that all the dispatch offsets for all the extensions that - * *might* be enables are known. This is needed because the - * dispatch offsets need to be known when _mesa_context_create is - * called, but we can't enable the extensions until we have a - * context pointer. - * - * Hello chicken. Hello egg. How are you two today? - */ - driInitExtensions( NULL, card_extensions, GL_FALSE ); - if (!r128InitDriver(psp)) return NULL; diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 3ddb5bf7d6..e3ae839235 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -75,7 +75,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define need_GL_NV_vertex_program #define need_GL_ARB_point_parameters #define need_GL_EXT_framebuffer_object -#include "extension_helper.h" +#include "main/remap_helper.h" #define DRIVER_DATE "20060602" @@ -115,7 +115,7 @@ static const GLubyte *r200GetString( GLcontext *ctx, GLenum name ) /* Extension strings exported by the R200 driver. */ -const struct dri_extension card_extensions[] = +static const struct dri_extension card_extensions[] = { { "GL_ARB_multitexture", NULL }, { "GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions}, @@ -146,31 +146,31 @@ const struct dri_extension card_extensions[] = { NULL, NULL } }; -const struct dri_extension blend_extensions[] = { +static const struct dri_extension blend_extensions[] = { { "GL_EXT_blend_equation_separate", GL_EXT_blend_equation_separate_functions }, { "GL_EXT_blend_func_separate", GL_EXT_blend_func_separate_functions }, { NULL, NULL } }; -const struct dri_extension ARB_vp_extension[] = { +static const struct dri_extension ARB_vp_extension[] = { { "GL_ARB_vertex_program", GL_ARB_vertex_program_functions } }; -const struct dri_extension NV_vp_extension[] = { +static const struct dri_extension NV_vp_extension[] = { { "GL_NV_vertex_program", GL_NV_vertex_program_functions } }; -const struct dri_extension ATI_fs_extension[] = { +static const struct dri_extension ATI_fs_extension[] = { { "GL_ATI_fragment_shader", GL_ATI_fragment_shader_functions } }; -const struct dri_extension point_extensions[] = { +static const struct dri_extension point_extensions[] = { { "GL_ARB_point_sprite", NULL }, { "GL_ARB_point_parameters", GL_ARB_point_parameters_functions }, { NULL, NULL } }; -const struct dri_extension mm_extensions[] = { +static const struct dri_extension mm_extensions[] = { { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, { NULL, NULL } }; diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 2c2b16aa98..6f66e970e4 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -90,10 +90,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define need_GL_ATI_separate_stencil #define need_GL_NV_vertex_program -#include "extension_helper.h" +#include "main/remap_helper.h" -const struct dri_extension card_extensions[] = { +static const struct dri_extension card_extensions[] = { /* *INDENT-OFF* */ {"GL_ARB_depth_texture", NULL}, {"GL_ARB_fragment_program", NULL}, @@ -145,7 +145,7 @@ const struct dri_extension card_extensions[] = { }; -const struct dri_extension mm_extensions[] = { +static const struct dri_extension mm_extensions[] = { { "GL_EXT_framebuffer_blit", GL_EXT_framebuffer_blit_functions }, { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, { NULL, NULL } @@ -155,7 +155,7 @@ const struct dri_extension mm_extensions[] = { * The GL 2.0 functions are needed to make display lists work with * functions added by GL_ATI_separate_stencil. */ -const struct dri_extension gl_20_extension[] = { +static const struct dri_extension gl_20_extension[] = { {"GL_VERSION_2_0", GL_VERSION_2_0_functions }, }; diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index e6791b46f0..c1bf76deb8 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -92,9 +92,9 @@ int hw_tcl_on = 1; #define need_GL_ATI_separate_stencil #define need_GL_NV_vertex_program -#include "extension_helper.h" +#include "main/remap_helper.h" -const struct dri_extension card_extensions[] = { +static const struct dri_extension card_extensions[] = { /* *INDENT-OFF* */ {"GL_ARB_depth_texture", NULL}, {"GL_ARB_fragment_program", NULL}, @@ -145,7 +145,7 @@ const struct dri_extension card_extensions[] = { }; -const struct dri_extension mm_extensions[] = { +static const struct dri_extension mm_extensions[] = { { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, { NULL, NULL } }; @@ -154,7 +154,7 @@ const struct dri_extension mm_extensions[] = { * The GL 2.0 functions are needed to make display lists work with * functions added by GL_ATI_separate_stencil. */ -const struct dri_extension gl_20_extension[] = { +static const struct dri_extension gl_20_extension[] = { {"GL_VERSION_2_0", GL_VERSION_2_0_functions }, }; diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index 8f4485aee7..5e700be4a5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -69,7 +69,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define need_GL_EXT_fog_coord #define need_GL_EXT_secondary_color #define need_GL_EXT_framebuffer_object -#include "extension_helper.h" +#include "main/remap_helper.h" #define DRIVER_DATE "20061018" @@ -79,7 +79,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* Extension strings exported by the R100 driver. */ -const struct dri_extension card_extensions[] = +static const struct dri_extension card_extensions[] = { { "GL_ARB_multitexture", NULL }, { "GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions}, @@ -109,7 +109,7 @@ const struct dri_extension card_extensions[] = { NULL, NULL } }; -const struct dri_extension mm_extensions[] = { +static const struct dri_extension mm_extensions[] = { { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, { NULL, NULL } }; diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 573eb6c9c1..2fb2d37cf1 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -141,12 +141,6 @@ DRI_CONF_BEGIN DRI_CONF_END; static const GLuint __driNConfigOptions = 17; -extern const struct dri_extension blend_extensions[]; -extern const struct dri_extension ARB_vp_extension[]; -extern const struct dri_extension NV_vp_extension[]; -extern const struct dri_extension ATI_fs_extension[]; -extern const struct dri_extension point_extensions[]; - #elif defined(RADEON_R300) || defined(RADEON_R600) #define DRI_CONF_FP_OPTIMIZATION_SPEED 0 @@ -218,13 +212,8 @@ DRI_CONF_BEGIN DRI_CONF_END; static const GLuint __driNConfigOptions = 17; -extern const struct dri_extension gl_20_extension[]; - #endif -extern const struct dri_extension card_extensions[]; -extern const struct dri_extension mm_extensions[]; - static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); static int @@ -1619,27 +1608,6 @@ radeonInitScreen(__DRIscreenPrivate *psp) return NULL; } - /* Calling driInitExtensions here, with a NULL context pointer, - * does not actually enable the extensions. It just makes sure - * that all the dispatch offsets for all the extensions that - * *might* be enables are known. This is needed because the - * dispatch offsets need to be known when _mesa_context_create - * is called, but we can't enable the extensions until we have a - * context pointer. - * - * Hello chicken. Hello egg. How are you two today? - */ - driInitExtensions( NULL, card_extensions, GL_FALSE ); -#if defined(RADEON_R200) - driInitExtensions( NULL, blend_extensions, GL_FALSE ); - driInitSingleExtension( NULL, ARB_vp_extension ); - driInitSingleExtension( NULL, NV_vp_extension ); - driInitSingleExtension( NULL, ATI_fs_extension ); - driInitExtensions( NULL, point_extensions, GL_FALSE ); -#elif (defined(RADEON_R300) || defined(RADEON_R600)) - driInitSingleExtension( NULL, gl_20_extension ); -#endif - if (!radeonInitDriver(psp)) return NULL; @@ -1672,28 +1640,6 @@ __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) int color; __DRIconfig **configs = NULL; - /* Calling driInitExtensions here, with a NULL context pointer, - * does not actually enable the extensions. It just makes sure - * that all the dispatch offsets for all the extensions that - * *might* be enables are known. This is needed because the - * dispatch offsets need to be known when _mesa_context_create - * is called, but we can't enable the extensions until we have a - * context pointer. - * - * Hello chicken. Hello egg. How are you two today? - */ - driInitExtensions( NULL, card_extensions, GL_FALSE ); - driInitExtensions( NULL, mm_extensions, GL_FALSE ); -#if defined(RADEON_R200) - driInitExtensions( NULL, blend_extensions, GL_FALSE ); - driInitSingleExtension( NULL, ARB_vp_extension ); - driInitSingleExtension( NULL, NV_vp_extension ); - driInitSingleExtension( NULL, ATI_fs_extension ); - driInitExtensions( NULL, point_extensions, GL_FALSE ); -#elif (defined(RADEON_R300) || defined(RADEON_R600)) - driInitSingleExtension( NULL, gl_20_extension ); -#endif - if (!radeonInitDriver(psp)) { return NULL; } diff --git a/src/mesa/drivers/dri/savage/savage_xmesa.c b/src/mesa/drivers/dri/savage/savage_xmesa.c index 931ceff0a8..0fccf50a03 100644 --- a/src/mesa/drivers/dri/savage/savage_xmesa.c +++ b/src/mesa/drivers/dri/savage/savage_xmesa.c @@ -59,7 +59,7 @@ #include "texmem.h" #define need_GL_EXT_secondary_color -#include "extension_helper.h" +#include "main/remap_helper.h" #include "xmlpool.h" @@ -980,18 +980,6 @@ savageInitScreen(__DRIscreenPrivate *psp) &psp->drm_version, & drm_expected ) ) return NULL; - /* Calling driInitExtensions here, with a NULL context pointer, - * does not actually enable the extensions. It just makes sure - * that all the dispatch offsets for all the extensions that - * *might* be enables are known. This is needed because the - * dispatch offsets need to be known when _mesa_context_create is - * called, but we can't enable the extensions until we have a - * context pointer. - * - * Hello chicken. Hello egg. How are you two today? - */ - driInitExtensions( NULL, card_extensions, GL_FALSE ); - if (!savageInitDriver(psp)) return NULL; diff --git a/src/mesa/drivers/dri/sis/sis_context.c b/src/mesa/drivers/dri/sis/sis_context.c index a070fe3d79..f501e7ad2e 100644 --- a/src/mesa/drivers/dri/sis/sis_context.c +++ b/src/mesa/drivers/dri/sis/sis_context.c @@ -59,7 +59,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #define need_GL_EXT_fog_coord #define need_GL_EXT_secondary_color -#include "extension_helper.h" +#include "main/remap_helper.h" #ifndef SIS_DEBUG int SIS_DEBUG = 0; @@ -69,7 +69,7 @@ int GlobalCurrentHwcx = -1; int GlobalHwcxCountBase = 1; int GlobalCmdQueueLen = 0; -struct dri_extension card_extensions[] = +static struct dri_extension card_extensions[] = { { "GL_ARB_multitexture", NULL }, { "GL_ARB_texture_border_clamp", NULL }, @@ -83,7 +83,7 @@ struct dri_extension card_extensions[] = { NULL, NULL } }; -struct dri_extension card_extensions_6326[] = +static struct dri_extension card_extensions_6326[] = { /*{ "GL_ARB_texture_border_clamp", NULL },*/ /*{ "GL_ARB_texture_mirrored_repeat", NULL },*/ diff --git a/src/mesa/drivers/dri/sis/sis_screen.c b/src/mesa/drivers/dri/sis/sis_screen.c index b5f04ae28d..fec9158236 100644 --- a/src/mesa/drivers/dri/sis/sis_screen.c +++ b/src/mesa/drivers/dri/sis/sis_screen.c @@ -298,18 +298,6 @@ sisInitScreen(__DRIscreenPrivate *psp) &psp->drm_version, &drm_expected)) return NULL; - /* Calling driInitExtensions here, with a NULL context pointer, - * does not actually enable the extensions. It just makes sure - * that all the dispatch offsets for all the extensions that - * *might* be enables are known. This is needed because the - * dispatch offsets need to be known when _mesa_context_create is - * called, but we can't enable the extensions until we have a - * context pointer. - * - * Hello chicken. Hello egg. How are you two today? - */ - driInitExtensions( NULL, card_extensions, GL_FALSE ); - psp->private = sisCreateScreen(psp); if (!psp->private) { diff --git a/src/mesa/drivers/dri/swrast/swrast.c b/src/mesa/drivers/dri/swrast/swrast.c index f4947daa06..df5221b135 100644 --- a/src/mesa/drivers/dri/swrast/swrast.c +++ b/src/mesa/drivers/dri/swrast/swrast.c @@ -49,78 +49,6 @@ #include "swrast_priv.h" -#define need_GL_VERSION_1_3 -#define need_GL_VERSION_1_4 -#define need_GL_VERSION_1_5 -#define need_GL_VERSION_2_0 -#define need_GL_VERSION_2_1 - -/* sw extensions for imaging */ -#define need_GL_EXT_blend_color -#define need_GL_EXT_blend_minmax -#define need_GL_EXT_convolution -#define need_GL_EXT_histogram -#define need_GL_SGI_color_table - -/* sw extensions not associated with some GL version */ -#define need_GL_ARB_draw_elements_base_vertex -#define need_GL_ARB_shader_objects -#define need_GL_ARB_vertex_array_object -#define need_GL_ARB_vertex_program -#define need_GL_ARB_sync -#define need_GL_APPLE_vertex_array_object -#define need_GL_ATI_fragment_shader -#define need_GL_ATI_separate_stencil -#define need_GL_EXT_depth_bounds_test -#define need_GL_EXT_framebuffer_object -#define need_GL_EXT_framebuffer_blit -#define need_GL_EXT_gpu_program_parameters -#define need_GL_EXT_paletted_texture -#define need_GL_EXT_stencil_two_side -#define need_GL_MESA_resize_buffers -#define need_GL_NV_vertex_program -#define need_GL_NV_fragment_program - -#include "extension_helper.h" - -const struct dri_extension card_extensions[] = -{ - { "GL_VERSION_1_3", GL_VERSION_1_3_functions }, - { "GL_VERSION_1_4", GL_VERSION_1_4_functions }, - { "GL_VERSION_1_5", GL_VERSION_1_5_functions }, - { "GL_VERSION_2_0", GL_VERSION_2_0_functions }, - { "GL_VERSION_2_1", GL_VERSION_2_1_functions }, - - { "GL_EXT_blend_color", GL_EXT_blend_color_functions }, - { "GL_EXT_blend_minmax", GL_EXT_blend_minmax_functions }, - { "GL_EXT_convolution", GL_EXT_convolution_functions }, - { "GL_EXT_histogram", GL_EXT_histogram_functions }, - { "GL_SGI_color_table", GL_SGI_color_table_functions }, - - { "GL_ARB_depth_clamp", NULL }, - { "GL_ARB_draw_elements_base_vertex", GL_ARB_draw_elements_base_vertex_functions }, - { "GL_ARB_shader_objects", GL_ARB_shader_objects_functions }, - { "GL_ARB_vertex_array_object", GL_ARB_vertex_array_object_functions }, - { "GL_ARB_vertex_program", GL_ARB_vertex_program_functions }, - { "GL_ARB_sync", GL_ARB_sync_functions }, - { "GL_APPLE_vertex_array_object", GL_APPLE_vertex_array_object_functions }, - { "GL_ATI_fragment_shader", GL_ATI_fragment_shader_functions }, - { "GL_ATI_separate_stencil", GL_ATI_separate_stencil_functions }, - { "GL_EXT_depth_bounds_test", GL_EXT_depth_bounds_test_functions }, - { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, - { "GL_EXT_framebuffer_blit", GL_EXT_framebuffer_blit_functions }, - { "GL_EXT_gpu_program_parameters", GL_EXT_gpu_program_parameters_functions }, - { "GL_EXT_paletted_texture", GL_EXT_paletted_texture_functions }, - { "GL_EXT_stencil_two_side", GL_EXT_stencil_two_side_functions }, - { "GL_MESA_resize_buffers", GL_MESA_resize_buffers_functions }, - { "GL_NV_depth_clamp", NULL }, - { "GL_NV_vertex_program", GL_NV_vertex_program_functions }, - { "GL_NV_fragment_program", GL_NV_fragment_program_functions }, - { "GL_NV_fragment_program_option", NULL }, - { NULL, NULL } -}; - - /** * Screen and config-related functions */ @@ -244,7 +172,7 @@ driCreateNewScreen(int scrn, const __DRIextension **extensions, *driver_configs = (const __DRIconfig **) driConcatConfigs(configs24, configs32); - driInitExtensions( NULL, card_extensions, GL_FALSE ); + driInitExtensions( NULL, NULL, GL_FALSE ); return psp; } diff --git a/src/mesa/drivers/dri/tdfx/tdfx_context.c b/src/mesa/drivers/dri/tdfx/tdfx_context.c index 68b5027561..e742d414a5 100644 --- a/src/mesa/drivers/dri/tdfx/tdfx_context.c +++ b/src/mesa/drivers/dri/tdfx/tdfx_context.c @@ -68,13 +68,13 @@ #define need_GL_EXT_paletted_texture /* #define need_GL_EXT_secondary_color */ /* #define need_GL_NV_vertex_program */ -#include "extension_helper.h" +#include "main/remap_helper.h" /** * Common extension strings exported by all cards */ -const struct dri_extension card_extensions[] = +static const struct dri_extension card_extensions[] = { { "GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions }, { "GL_ARB_texture_mirrored_repeat", NULL }, @@ -107,7 +107,7 @@ const struct dri_extension card_extensions[] = /** * Extension strings exported only by Naplam (e.g., Voodoo4 & Voodoo5) cards. */ -const struct dri_extension napalm_extensions[] = +static const struct dri_extension napalm_extensions[] = { { "GL_ARB_texture_env_combine", NULL }, { "GL_EXT_blend_equation_separate", GL_EXT_blend_equation_separate_functions }, diff --git a/src/mesa/drivers/dri/tdfx/tdfx_screen.c b/src/mesa/drivers/dri/tdfx/tdfx_screen.c index 58bd48b294..d8a4b401c0 100644 --- a/src/mesa/drivers/dri/tdfx/tdfx_screen.c +++ b/src/mesa/drivers/dri/tdfx/tdfx_screen.c @@ -69,9 +69,6 @@ static const __DRIextension *tdfxExtensions[] = { static const GLuint __driNConfigOptions = 1; -extern const struct dri_extension card_extensions[]; -extern const struct dri_extension napalm_extensions[]; - static GLboolean tdfxCreateScreen( __DRIscreenPrivate *sPriv ) { @@ -418,19 +415,6 @@ tdfxInitScreen(__DRIscreen *psp) &psp->drm_version, & drm_expected ) ) return NULL; - /* Calling driInitExtensions here, with a NULL context pointer, - * does not actually enable the extensions. It just makes sure - * that all the dispatch offsets for all the extensions that - * *might* be enables are known. This is needed because the - * dispatch offsets need to be known when _mesa_context_create is - * called, but we can't enable the extensions until we have a - * context pointer. - * - * Hello chicken. Hello egg. How are you two today? - */ - driInitExtensions( NULL, card_extensions, GL_FALSE ); - driInitExtensions( NULL, napalm_extensions, GL_FALSE ); - if (!tdfxInitDriver(psp)) return NULL; diff --git a/src/mesa/drivers/dri/unichrome/via_context.c b/src/mesa/drivers/dri/unichrome/via_context.c index 6eb19ac079..5be1cf32c2 100644 --- a/src/mesa/drivers/dri/unichrome/via_context.c +++ b/src/mesa/drivers/dri/unichrome/via_context.c @@ -65,7 +65,7 @@ #define need_GL_ARB_point_parameters #define need_GL_EXT_fog_coord #define need_GL_EXT_secondary_color -#include "extension_helper.h" +#include "main/remap_helper.h" #define DRIVER_DATE "20060710" @@ -362,7 +362,7 @@ void viaReAllocateBuffers(GLcontext *ctx, GLframebuffer *drawbuffer, /* Extension strings exported by the Unichrome driver. */ -const struct dri_extension card_extensions[] = +static const struct dri_extension card_extensions[] = { { "GL_ARB_multitexture", NULL }, { "GL_ARB_point_parameters", GL_ARB_point_parameters_functions }, diff --git a/src/mesa/drivers/dri/unichrome/via_screen.c b/src/mesa/drivers/dri/unichrome/via_screen.c index 3dbb570571..7cfc60a015 100644 --- a/src/mesa/drivers/dri/unichrome/via_screen.c +++ b/src/mesa/drivers/dri/unichrome/via_screen.c @@ -62,8 +62,6 @@ DRI_CONF_BEGIN DRI_CONF_END; static const GLuint __driNConfigOptions = 3; -extern const struct dri_extension card_extensions[]; - static drmBufMapPtr via_create_empty_buffers(void) { drmBufMapPtr retval; @@ -393,18 +391,6 @@ viaInitScreen(__DRIscreenPrivate *psp) &psp->drm_version, & drm_expected) ) return NULL; - /* Calling driInitExtensions here, with a NULL context pointer, - * does not actually enable the extensions. It just makes sure - * that all the dispatch offsets for all the extensions that - * *might* be enables are known. This is needed because the - * dispatch offsets need to be known when _mesa_context_create is - * called, but we can't enable the extensions until we have a - * context pointer. - * - * Hello chicken. Hello egg. How are you two today? - */ - driInitExtensions( NULL, card_extensions, GL_FALSE ); - if (!viaInitDriver(psp)) return NULL; diff --git a/src/mesa/drivers/x11/xm_api.c b/src/mesa/drivers/x11/xm_api.c index 79b058634c..bf767bcedd 100644 --- a/src/mesa/drivers/x11/xm_api.c +++ b/src/mesa/drivers/x11/xm_api.c @@ -1303,71 +1303,6 @@ xmesa_convert_from_x_visual_type( int visualType ) /**********************************************************************/ -#ifdef IN_DRI_DRIVER -#define need_GL_VERSION_1_3 -#define need_GL_VERSION_1_4 -#define need_GL_VERSION_1_5 -#define need_GL_VERSION_2_0 - -/* sw extensions for imaging */ -#define need_GL_EXT_blend_color -#define need_GL_EXT_blend_minmax -#define need_GL_EXT_convolution -#define need_GL_EXT_histogram -#define need_GL_SGI_color_table - -/* sw extensions not associated with some GL version */ -#define need_GL_ARB_draw_elements_base_vertex -#define need_GL_ARB_shader_objects -#define need_GL_ARB_sync -#define need_GL_ARB_vertex_program -#define need_GL_APPLE_vertex_array_object -#define need_GL_ATI_fragment_shader -#define need_GL_EXT_depth_bounds_test -#define need_GL_EXT_framebuffer_object -#define need_GL_EXT_framebuffer_blit -#define need_GL_EXT_gpu_program_parameters -#define need_GL_EXT_paletted_texture -#define need_GL_MESA_resize_buffers -#define need_GL_NV_vertex_program -#define need_GL_NV_fragment_program - -#include "extension_helper.h" -#include "utils.h" - -const struct dri_extension card_extensions[] = -{ - { "GL_VERSION_1_3", GL_VERSION_1_3_functions }, - { "GL_VERSION_1_4", GL_VERSION_1_4_functions }, - { "GL_VERSION_1_5", GL_VERSION_1_5_functions }, - { "GL_VERSION_2_0", GL_VERSION_2_0_functions }, - - { "GL_EXT_blend_color", GL_EXT_blend_color_functions }, - { "GL_EXT_blend_minmax", GL_EXT_blend_minmax_functions }, - { "GL_EXT_convolution", GL_EXT_convolution_functions }, - { "GL_EXT_histogram", GL_EXT_histogram_functions }, - { "GL_SGI_color_table", GL_SGI_color_table_functions }, - - { "GL_ARB_depth_clamp", NULL }, - { "GL_ARB_draw_elements_base_vertex", GL_ARB_draw_elements_base_vertex_functions }, - { "GL_ARB_shader_objects", GL_ARB_shader_objects_functions }, - { "GL_ARB_sync", GL_ARB_sync_functions }, - { "GL_ARB_vertex_program", GL_ARB_vertex_program_functions }, - { "GL_APPLE_vertex_array_object", GL_APPLE_vertex_array_object_functions }, - { "GL_ATI_fragment_shader", GL_ATI_fragment_shader_functions }, - { "GL_EXT_depth_bounds_test", GL_EXT_depth_bounds_test_functions }, - { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, - { "GL_EXT_framebuffer_blit", GL_EXT_framebuffer_blit_functions }, - { "GL_EXT_gpu_program_parameters", GL_EXT_gpu_program_parameters_functions }, - { "GL_EXT_paletted_texture", GL_EXT_paletted_texture_functions }, - { "GL_MESA_resize_buffers", GL_MESA_resize_buffers_functions }, - { "GL_NV_depth_clamp", NULL }, - { "GL_NV_vertex_program", GL_NV_vertex_program_functions }, - { "GL_NV_fragment_program", GL_NV_fragment_program_functions }, - { NULL, NULL } -}; -#endif - /* * Create a new X/Mesa visual. * Input: display - X11 display @@ -1413,14 +1348,6 @@ XMesaVisual XMesaCreateVisual( XMesaDisplay *display, XMesaVisual v; GLint red_bits, green_bits, blue_bits, alpha_bits; -#ifdef IN_DRI_DRIVER - /* driInitExtensions() should be called once per screen to setup extension - * indices. There is no need to call it when the context is created since - * XMesa enables mesa sw extensions on its own. - */ - driInitExtensions( NULL, card_extensions, GL_FALSE ); -#endif - #ifndef XFree86Server /* For debugging only */ if (_mesa_getenv("MESA_XSYNC")) { diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c index 490b8f0f33..ea820d77b3 100644 --- a/src/mesa/main/context.c +++ b/src/mesa/main/context.c @@ -117,6 +117,7 @@ #include "syncobj.h" #endif #include "rastpos.h" +#include "remap.h" #include "scissor.h" #include "shared.h" #include "simple_list.h" @@ -407,6 +408,8 @@ one_time_init( GLcontext *ctx ) _mesa_get_cpu_features(); + _mesa_init_remap_table(); + _mesa_init_sqrt_table(); for (i = 0; i < 256; i++) { diff --git a/src/mesa/sources.mak b/src/mesa/sources.mak index 7107538cee..0838014e93 100644 --- a/src/mesa/sources.mak +++ b/src/mesa/sources.mak @@ -55,6 +55,7 @@ MAIN_SOURCES = \ main/rastpos.c \ main/rbadaptors.c \ main/readpix.c \ + main/remap.c \ main/renderbuffer.c \ main/scissor.c \ main/shaders.c \ -- cgit v1.2.3 From 11caea687e3f10ae12d33e44edf84635f73047dd Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Sun, 25 Oct 2009 18:06:18 -0600 Subject: mesa: choose texture format in core mesa, not drivers Call the ctx->Driver.ChooseTextureFormat() function from core Mesa's _mesa_[Copy]TexImage functions instead of in the driver functions. One less thing for drivers to do. --- src/mesa/drivers/dri/intel/intel_tex_image.c | 6 ---- src/mesa/drivers/dri/r200/r200_texstate.c | 4 +-- src/mesa/drivers/dri/r300/r300_texstate.c | 3 -- src/mesa/drivers/dri/r600/r600_texstate.c | 4 +-- src/mesa/drivers/dri/radeon/radeon_fbo.c | 3 ++ src/mesa/drivers/dri/radeon/radeon_texstate.c | 4 +-- src/mesa/drivers/dri/radeon/radeon_texture.c | 3 -- src/mesa/drivers/dri/tdfx/tdfx_tex.c | 11 ------ src/mesa/drivers/glide/fxddtex.c | 12 ------- src/mesa/main/teximage.c | 48 +++++++++++++++++++++++++++ src/mesa/main/texstore.c | 16 --------- src/mesa/state_tracker/st_cb_texture.c | 4 --- 12 files changed, 54 insertions(+), 64 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c index daf6d9da0e..ef5902a5e5 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_image.c +++ b/src/mesa/drivers/dri/intel/intel_tex_image.c @@ -330,10 +330,6 @@ intelTexImage(GLcontext * ctx, &postConvHeight); } - /* choose the texture format */ - texImage->TexFormat = intelChooseTextureFormat(ctx, internalFormat, - format, type); - if (_mesa_is_format_compressed(texImage->TexFormat)) { texelBytes = 0; } @@ -787,8 +783,6 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, intelImage->face = target_to_face(target); intelImage->level = level; - texImage->TexFormat = intelChooseTextureFormat(&intel->ctx, internalFormat, - type, format); texImage->RowStride = rb->region->pitch; intel_miptree_reference(&intelImage->mt, intelObj->mt); diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index 20ec6fffaf..7d0afa1add 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -835,9 +835,7 @@ void r200SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo _mesa_init_teximage_fields(radeon->glCtx, target, texImage, rb->base.Width, rb->base.Height, 1, 0, rb->cpp); texImage->RowStride = rb->pitch / rb->cpp; - texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx, - internalFormat, - type, format, 0); + rImage->bo = rb->bo; radeon_bo_ref(rImage->bo); t->bo = rb->bo; diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index 63f0154cd3..b7bb8bfadc 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -444,9 +444,6 @@ void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo _mesa_init_teximage_fields(radeon->glCtx, target, texImage, rb->base.Width, rb->base.Height, 1, 0, rb->cpp); texImage->RowStride = rb->pitch / rb->cpp; - texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx, - internalFormat, - type, format, 0); rImage->bo = rb->bo; radeon_bo_ref(rImage->bo); t->bo = rb->bo; diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 63d88f83d6..a083f9afc0 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -907,9 +907,7 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo _mesa_init_teximage_fields(radeon->glCtx, target, texImage, rb->base.Width, rb->base.Height, 1, 0, rb->cpp); texImage->RowStride = rb->pitch / rb->cpp; - texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx, - internalFormat, - type, format, 0); + rImage->bo = rb->bo; radeon_bo_ref(rImage->bo); t->bo = rb->bo; diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index 40846828c5..3f0ab83996 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -385,6 +385,9 @@ restart: texImage->TexFormat); return GL_FALSE; } + /* XXX why is the tex format being set here? + * I think this can be removed. + */ texImage->TexFormat = radeonChooseTextureFormat(ctx, texImage->InternalFormat, 0, _mesa_get_format_datatype(texImage->TexFormat), 1); diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index c7786381ae..0fd9a138d6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -709,9 +709,7 @@ void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_ _mesa_init_teximage_fields(radeon->glCtx, target, texImage, rb->base.Width, rb->base.Height, 1, 0, rb->cpp); texImage->RowStride = rb->pitch / rb->cpp; - texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx, - internalFormat, - type, format, 0); + rImage->bo = rb->bo; radeon_bo_ref(rImage->bo); t->bo = rb->bo; diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index d8e81237d0..9b391620c6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -538,9 +538,6 @@ static void radeon_teximage( &postConvHeight); } - /* Choose and fill in the texture format for this image */ - texImage->TexFormat = radeonChooseTextureFormat(ctx, internalFormat, format, type, 0); - if (_mesa_is_format_compressed(texImage->TexFormat)) { texelBytes = 0; } else { diff --git a/src/mesa/drivers/dri/tdfx/tdfx_tex.c b/src/mesa/drivers/dri/tdfx/tdfx_tex.c index af434315c1..0aa09e733b 100644 --- a/src/mesa/drivers/dri/tdfx/tdfx_tex.c +++ b/src/mesa/drivers/dri/tdfx/tdfx_tex.c @@ -1396,11 +1396,6 @@ tdfxTexImage2D(GLcontext *ctx, GLenum target, GLint level, } #endif - /* choose the texture format */ - assert(ctx->Driver.ChooseTextureFormat); - texImage->TexFormat = (*ctx->Driver.ChooseTextureFormat)(ctx, - internalFormat, format, type); - assert(texImage->TexFormat); mesaFormat = texImage->TexFormat; mml->glideFormat = fxGlideFormat(mesaFormat); ti->info.format = mml->glideFormat; @@ -1618,12 +1613,6 @@ tdfxCompressedTexImage2D (GLcontext *ctx, GLenum target, mml->height = height * mml->hScale; - /* choose the texture format */ - assert(ctx->Driver.ChooseTextureFormat); - texImage->TexFormat = (*ctx->Driver.ChooseTextureFormat)(ctx, - internalFormat, -1/*format*/, -1/*type*/); - assert(texImage->TexFormat); - /* Determine the appropriate Glide texel format, * given the user's internal texture format hint. */ diff --git a/src/mesa/drivers/glide/fxddtex.c b/src/mesa/drivers/glide/fxddtex.c index 9fcbf96114..a863b028ad 100644 --- a/src/mesa/drivers/glide/fxddtex.c +++ b/src/mesa/drivers/glide/fxddtex.c @@ -1384,11 +1384,6 @@ fxDDTexImage2D(GLcontext * ctx, GLenum target, GLint level, } #endif - /* choose the texture format */ - assert(ctx->Driver.ChooseTextureFormat); - texImage->TexFormat = (*ctx->Driver.ChooseTextureFormat)(ctx, - internalFormat, format, type); - assert(texImage->TexFormat); texelBytes = _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); /*if (!fxMesa->HaveTexFmt) assert(texelBytes == 1 || texelBytes == 2);*/ @@ -1648,13 +1643,6 @@ fxDDCompressedTexImage2D (GLcontext *ctx, GLenum target, mml->width = width * mml->wScale; mml->height = height * mml->hScale; - - /* choose the texture format */ - assert(ctx->Driver.ChooseTextureFormat); - texImage->TexFormat = (*ctx->Driver.ChooseTextureFormat)(ctx, - internalFormat, -1/*format*/, -1/*type*/); - assert(texImage->TexFormat); - /* Determine the appropriate Glide texel format, * given the user's internal texture format hint. */ diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c index bd5ad56258..2555934eca 100644 --- a/src/mesa/main/teximage.c +++ b/src/mesa/main/teximage.c @@ -2195,6 +2195,12 @@ _mesa_TexImage1D( GLenum target, GLint level, GLint internalFormat, postConvWidth, 1, 1, border, internalFormat); + /* Choose actual texture format */ + texImage->TexFormat = + ctx->Driver.ChooseTextureFormat(ctx, internalFormat, + format, type); + ASSERT(texImage->TexFormat != MESA_FORMAT_NONE); + /* Give the texture to the driver. may be null. */ ASSERT(ctx->Driver.TexImage1D); ctx->Driver.TexImage1D(ctx, target, level, internalFormat, @@ -2311,6 +2317,12 @@ _mesa_TexImage2D( GLenum target, GLint level, GLint internalFormat, postConvWidth, postConvHeight, 1, border, internalFormat); + /* Choose actual texture format */ + texImage->TexFormat = + ctx->Driver.ChooseTextureFormat(ctx, internalFormat, + format, type); + ASSERT(texImage->TexFormat != MESA_FORMAT_NONE); + /* Give the texture to the driver. may be null. */ ASSERT(ctx->Driver.TexImage2D); ctx->Driver.TexImage2D(ctx, target, level, internalFormat, @@ -2423,6 +2435,12 @@ _mesa_TexImage3D( GLenum target, GLint level, GLint internalFormat, width, height, depth, border, internalFormat); + /* Choose actual texture format */ + texImage->TexFormat = + ctx->Driver.ChooseTextureFormat(ctx, internalFormat, + format, type); + ASSERT(texImage->TexFormat != MESA_FORMAT_NONE); + /* Give the texture to the driver. may be null. */ ASSERT(ctx->Driver.TexImage3D); ctx->Driver.TexImage3D(ctx, target, level, internalFormat, @@ -2735,6 +2753,12 @@ _mesa_CopyTexImage1D( GLenum target, GLint level, _mesa_init_teximage_fields(ctx, target, texImage, postConvWidth, 1, 1, border, internalFormat); + /* Choose actual texture format */ + texImage->TexFormat = + ctx->Driver.ChooseTextureFormat(ctx, internalFormat, + GL_NONE, GL_NONE); + ASSERT(texImage->TexFormat != MESA_FORMAT_NONE); + ASSERT(ctx->Driver.CopyTexImage1D); ctx->Driver.CopyTexImage1D(ctx, target, level, internalFormat, x, y, width, border); @@ -2812,6 +2836,12 @@ _mesa_CopyTexImage2D( GLenum target, GLint level, GLenum internalFormat, postConvWidth, postConvHeight, 1, border, internalFormat); + /* Choose actual texture format */ + texImage->TexFormat = + ctx->Driver.ChooseTextureFormat(ctx, internalFormat, + GL_NONE, GL_NONE); + ASSERT(texImage->TexFormat != MESA_FORMAT_NONE); + ASSERT(ctx->Driver.CopyTexImage2D); ctx->Driver.CopyTexImage2D(ctx, target, level, internalFormat, x, y, width, height, border); @@ -3290,6 +3320,12 @@ _mesa_CompressedTexImage1DARB(GLenum target, GLint level, _mesa_init_teximage_fields(ctx, target, texImage, width, 1, 1, border, internalFormat); + /* Choose actual texture format */ + texImage->TexFormat = + ctx->Driver.ChooseTextureFormat(ctx, internalFormat, + GL_NONE, GL_NONE); + ASSERT(texImage->TexFormat != MESA_FORMAT_NONE); + ASSERT(ctx->Driver.CompressedTexImage1D); ctx->Driver.CompressedTexImage1D(ctx, target, level, internalFormat, width, border, @@ -3396,6 +3432,12 @@ _mesa_CompressedTexImage2DARB(GLenum target, GLint level, _mesa_init_teximage_fields(ctx, target, texImage, width, height, 1, border, internalFormat); + /* Choose actual texture format */ + texImage->TexFormat = + ctx->Driver.ChooseTextureFormat(ctx, internalFormat, + GL_NONE, GL_NONE); + ASSERT(texImage->TexFormat != MESA_FORMAT_NONE); + ASSERT(ctx->Driver.CompressedTexImage2D); ctx->Driver.CompressedTexImage2D(ctx, target, level, internalFormat, width, height, @@ -3501,6 +3543,12 @@ _mesa_CompressedTexImage3DARB(GLenum target, GLint level, width, height, depth, border, internalFormat); + /* Choose actual texture format */ + texImage->TexFormat = + ctx->Driver.ChooseTextureFormat(ctx, internalFormat, + GL_NONE, GL_NONE); + ASSERT(texImage->TexFormat != MESA_FORMAT_NONE); + ASSERT(ctx->Driver.CompressedTexImage3D); ctx->Driver.CompressedTexImage3D(ctx, target, level, internalFormat, diff --git a/src/mesa/main/texstore.c b/src/mesa/main/texstore.c index dd146254b4..692923ba0a 100644 --- a/src/mesa/main/texstore.c +++ b/src/mesa/main/texstore.c @@ -3250,10 +3250,6 @@ _mesa_store_teximage1d(GLcontext *ctx, GLenum target, GLint level, GLuint sizeInBytes; (void) border; - texImage->TexFormat - = ctx->Driver.ChooseTextureFormat(ctx, internalFormat, format, type); - ASSERT(texImage->TexFormat); - /* allocate memory */ sizeInBytes = texture_size(texImage); texImage->Data = _mesa_alloc_texmemory(sizeInBytes); @@ -3311,10 +3307,6 @@ _mesa_store_teximage2d(GLcontext *ctx, GLenum target, GLint level, GLuint sizeInBytes; (void) border; - texImage->TexFormat - = ctx->Driver.ChooseTextureFormat(ctx, internalFormat, format, type); - ASSERT(texImage->TexFormat); - /* allocate memory */ sizeInBytes = texture_size(texImage); texImage->Data = _mesa_alloc_texmemory(sizeInBytes); @@ -3368,10 +3360,6 @@ _mesa_store_teximage3d(GLcontext *ctx, GLenum target, GLint level, GLuint sizeInBytes; (void) border; - texImage->TexFormat - = ctx->Driver.ChooseTextureFormat(ctx, internalFormat, format, type); - ASSERT(texImage->TexFormat); - /* allocate memory */ sizeInBytes = texture_size(texImage); texImage->Data = _mesa_alloc_texmemory(sizeInBytes); @@ -3570,10 +3558,6 @@ _mesa_store_compressed_teximage2d(GLcontext *ctx, GLenum target, GLint level, ASSERT(texImage->Depth == 1); ASSERT(texImage->Data == NULL); /* was freed in glCompressedTexImage2DARB */ - texImage->TexFormat - = ctx->Driver.ChooseTextureFormat(ctx, internalFormat, 0, 0); - ASSERT(texImage->TexFormat); - /* allocate storage */ texImage->Data = _mesa_alloc_texmemory(imageSize); if (!texImage->Data) { diff --git a/src/mesa/state_tracker/st_cb_texture.c b/src/mesa/state_tracker/st_cb_texture.c index 4397adbc12..e8bb720acc 100644 --- a/src/mesa/state_tracker/st_cb_texture.c +++ b/src/mesa/state_tracker/st_cb_texture.c @@ -555,10 +555,6 @@ st_TexImage(GLcontext * ctx, } #endif - /* choose the texture format */ - texImage->TexFormat = st_ChooseTextureFormat(ctx, internalFormat, - format, type); - _mesa_set_fetch_functions(texImage, dims); if (_mesa_is_format_compressed(texImage->TexFormat)) { -- cgit v1.2.3 From 660acd60d00366c97fbe7caf3995a75ce935a19b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 28 Oct 2009 15:36:53 -0400 Subject: r600: add occlusion query support Based on initial patch from Stephan Schmid . Basic idea is to dump the zpass count at the start and end of the query and subtract to get the total number of visible fragments. HW writes alternating qwords for up to 4 DBs. On the first pass, we start at buffer address + 0; on the second pass, we start at buffer address + 8 (bytes). The resulting buffer at the end of the query looks like: qw[0]: db0 start qw[1]: db0 end ... qw[6]: db3 start qw[7]: db3 end The MSB of each qword is the valid bit and the lower 63 bits are the zpass count for that DB. OQ on RV740 is disabled at the moment as it only seems to report results for half of its DBs. This needs further investigation. Signed-off-by: Alex Deucher --- src/mesa/drivers/dri/r600/r600_context.c | 31 +++++++++++++-- src/mesa/drivers/dri/r600/r700_chip.c | 54 +++++++++++++++++++++++++++ src/mesa/drivers/dri/r600/r700_state.c | 1 + src/mesa/drivers/dri/radeon/radeon_queryobj.c | 33 +++++++++++++--- 4 files changed, 109 insertions(+), 10 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index c1bf76deb8..6de151d51b 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -64,6 +64,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r600_cmdbuf.h" #include "r600_emit.h" #include "radeon_bocs_wrapper.h" +#include "radeon_queryobj.h" #include "r700_state.h" #include "r700_ioctl.h" @@ -73,11 +74,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "utils.h" #include "xmlpool.h" /* for symbolic values of enum-type options */ -/* hw_tcl_on derives from future_hw_tcl_on when its safe to change it. */ -int future_hw_tcl_on = 1; -int hw_tcl_on = 1; - #define need_GL_VERSION_2_0 +#define need_GL_ARB_occlusion_query #define need_GL_ARB_point_parameters #define need_GL_ARB_vertex_program #define need_GL_EXT_blend_equation_separate @@ -98,6 +96,7 @@ static const struct dri_extension card_extensions[] = { /* *INDENT-OFF* */ {"GL_ARB_depth_texture", NULL}, {"GL_ARB_fragment_program", NULL}, + {"GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions}, {"GL_ARB_multitexture", NULL}, {"GL_ARB_point_parameters", GL_ARB_point_parameters_functions}, {"GL_ARB_shadow", NULL}, @@ -204,6 +203,24 @@ static void r600_fallback(GLcontext *ctx, GLuint bit, GLboolean mode) context->radeon.Fallback &= ~bit; } +static void r600_emit_query_finish(radeonContextPtr radeon) +{ + context_t *context = (context_t*) radeon; + BATCH_LOCALS(&context->radeon); + + struct radeon_query_object *query = radeon->query.current; + + BEGIN_BATCH_NO_AUTOSTATE(4 + 2); + R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2)); + R600_OUT_BATCH(ZPASS_DONE); + R600_OUT_BATCH(query->curr_offset + 8); /* hw writes qwords */ + R600_OUT_BATCH(0x00000000); + R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0); + END_BATCH(); + assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE); + query->emitted_begin = GL_FALSE; +} + static void r600_init_vtbl(radeonContextPtr radeon) { radeon->vtbl.get_lock = r600_get_lock; @@ -212,6 +229,7 @@ static void r600_init_vtbl(radeonContextPtr radeon) radeon->vtbl.swtcl_flush = NULL; radeon->vtbl.pre_emit_atoms = r600_vtbl_pre_emit_atoms; radeon->vtbl.fallback = r600_fallback; + radeon->vtbl.emit_query_finish = r600_emit_query_finish; } static void r600InitConstValues(GLcontext *ctx, radeonScreenPtr screen) @@ -302,6 +320,10 @@ static void r600InitGLExtensions(GLcontext *ctx) { _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc"); } + + /* XXX: RV740 only seems to report results from half of its DBs */ + if (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV740) + _mesa_disable_extension(ctx, "GL_ARB_occlusion_query"); } /* Create the device specific rendering context. @@ -340,6 +362,7 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, r700InitStateFuncs(&functions); r600InitTextureFuncs(&functions); r700InitShaderFuncs(&functions); + radeonInitQueryObjFunctions(&functions); r700InitIoctlFuncs(&functions); radeonInitBufferObjectFuncs(&functions); diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 75b97c56cd..ace3d24f06 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -1100,6 +1100,32 @@ static void r700SendVSConsts(GLcontext *ctx, struct radeon_state_atom *atom) COMMIT_BATCH(); } +static void r700SendQueryBegin(GLcontext *ctx, struct radeon_state_atom *atom) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + struct radeon_query_object *query = radeon->query.current; + BATCH_LOCALS(radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); + + /* clear the buffer */ + radeon_bo_map(query->bo, GL_FALSE); + memset(query->bo->ptr, 0, 4 * 2 * sizeof(uint64_t)); /* 4 DBs, 2 qwords each */ + radeon_bo_unmap(query->bo); + + radeon_cs_space_check_with_bo(radeon->cmdbuf.cs, + query->bo, + 0, RADEON_GEM_DOMAIN_GTT); + + BEGIN_BATCH_NO_AUTOSTATE(4 + 2); + R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2)); + R600_OUT_BATCH(ZPASS_DONE); + R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */ + R600_OUT_BATCH(0x00000000); + R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0); + END_BATCH(); + query->emitted_begin = GL_TRUE; +} + static int check_always(GLcontext *ctx, struct radeon_state_atom *atom) { return atom->cmd_size; @@ -1208,6 +1234,20 @@ static int check_vs_consts(GLcontext *ctx, struct radeon_state_atom *atom) return count; } +static int check_queryobj(GLcontext *ctx, struct radeon_state_atom *atom) +{ + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + struct radeon_query_object *query = radeon->query.current; + int count; + + if (!query || query->emitted_begin) + count = 0; + else + count = atom->cmd_size; + radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count); + return count; +} + #define ALLOC_STATE( ATOM, CHK, SZ, EMIT ) \ do { \ context->atoms.ATOM.cmd_size = (SZ); \ @@ -1221,6 +1261,19 @@ do { \ insert_at_tail(&context->radeon.hw.atomlist, &context->atoms.ATOM); \ } while (0) +static void r600_init_query_stateobj(radeonContextPtr radeon, int SZ) +{ + radeon->query.queryobj.cmd_size = (SZ); + radeon->query.queryobj.cmd = NULL; + radeon->query.queryobj.name = "queryobj"; + radeon->query.queryobj.idx = 0; + radeon->query.queryobj.check = check_queryobj; + radeon->query.queryobj.dirty = GL_FALSE; + radeon->query.queryobj.emit = r700SendQueryBegin; + radeon->hw.max_state_size += (SZ); + insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj); +} + void r600InitAtoms(context_t *context) { radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context); @@ -1260,6 +1313,7 @@ void r600InitAtoms(context_t *context) ALLOC_STATE(tx, tx, (R700_TEXTURE_NUMBERUNITS * 20), r700SendTexState); ALLOC_STATE(tx_smplr, tx, (R700_TEXTURE_NUMBERUNITS * 5), r700SendTexSamplerState); ALLOC_STATE(tx_brdr_clr, tx, (R700_TEXTURE_NUMBERUNITS * 6), r700SendTexBorderColorState); + r600_init_query_stateobj(&context->radeon, 6 * 2); context->radeon.hw.is_dirty = GL_TRUE; context->radeon.hw.all_dirty = GL_TRUE; diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 9a6a68a68c..0b676362f8 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -1675,6 +1675,7 @@ void r700InitState(GLcontext * ctx) //------------------- SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask); SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask); SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask); + SETbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit); r700->DB_ALPHA_TO_MASK.u32All = 0; SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask); diff --git a/src/mesa/drivers/dri/radeon/radeon_queryobj.c b/src/mesa/drivers/dri/radeon/radeon_queryobj.c index b79d864ba2..6539c36268 100644 --- a/src/mesa/drivers/dri/radeon/radeon_queryobj.c +++ b/src/mesa/drivers/dri/radeon/radeon_queryobj.c @@ -47,8 +47,8 @@ static int radeonQueryIsFlushed(GLcontext *ctx, struct gl_query_object *q) static void radeonQueryGetResult(GLcontext *ctx, struct gl_query_object *q) { + radeonContextPtr radeon = RADEON_CONTEXT(ctx); struct radeon_query_object *query = (struct radeon_query_object *)q; - uint32_t *result; int i; radeon_print(RADEON_STATE, RADEON_VERBOSE, @@ -57,12 +57,33 @@ static void radeonQueryGetResult(GLcontext *ctx, struct gl_query_object *q) radeon_bo_map(query->bo, GL_FALSE); - result = query->bo->ptr; - query->Base.Result = 0; - for (i = 0; i < query->curr_offset/sizeof(uint32_t); ++i) { - query->Base.Result += result[i]; - radeon_print(RADEON_STATE, RADEON_TRACE, "result[%d] = %d\n", i, result[i]); + if (IS_R600_CLASS(radeon->radeonScreen)) { + /* ZPASS EVENT writes alternating qwords + * At query start we set the start offset to 0 and + * hw writes zpass start counts to qwords 0, 2, 4, 6. + * At query end we set the start offset to 8 and + * hw writes zpass end counts to qwords 1, 3, 5, 7. + * then we substract. MSB is the valid bit. + */ + uint64_t *result = query->bo->ptr; + for (i = 0; i < 8; i += 2) { + uint64_t start = result[i]; + uint64_t end = result[i + 1]; + if ((start & 0x8000000000000000) && (end & 0x8000000000000000)) { + uint64_t query_count = end - start; + query->Base.Result += query_count; + + } + radeon_print(RADEON_STATE, RADEON_TRACE, + "%d start: %lx, end: %lx %ld\n", i, start, end, end - start); + } + } else { + uint32_t *result = query->bo->ptr; + for (i = 0; i < query->curr_offset/sizeof(uint32_t); ++i) { + query->Base.Result += result[i]; + radeon_print(RADEON_STATE, RADEON_TRACE, "result[%d] = %d\n", i, result[i]); + } } radeon_bo_unmap(query->bo); -- cgit v1.2.3 From b924579bd4afaf5daa9df8d4f120f42fa20cafc6 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 29 Oct 2009 19:42:12 -0400 Subject: r600: Add support for ARB_depth_clamp --- src/mesa/drivers/dri/r600/r600_context.c | 1 + src/mesa/drivers/dri/r600/r700_state.c | 15 +++++++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 6de151d51b..dbd233729c 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -94,6 +94,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. static const struct dri_extension card_extensions[] = { /* *INDENT-OFF* */ + {"GL_ARB_depth_clamp", NULL}, {"GL_ARB_depth_texture", NULL}, {"GL_ARB_fragment_program", NULL}, {"GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions}, diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 2b42bfa3f9..b278887266 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -1030,6 +1030,7 @@ static void r700UpdateWindow(GLcontext * ctx, int id) //-------------------- GLfloat tz = v[MAT_TZ] * depthScale; R600_STATECHANGE(context, vpt); + R600_STATECHANGE(context, cl); r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx; r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx; @@ -1040,6 +1041,18 @@ static void r700UpdateWindow(GLcontext * ctx, int id) //-------------------- r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz; r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz; + if (ctx->Transform.DepthClamp) { + r700->viewport[id].PA_SC_VPORT_ZMIN_0.f32All = MIN2(ctx->Viewport.Near, ctx->Viewport.Far); + r700->viewport[id].PA_SC_VPORT_ZMAX_0.f32All = MAX2(ctx->Viewport.Near, ctx->Viewport.Far); + SETbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_NEAR_DISABLE_bit); + SETbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_FAR_DISABLE_bit); + } else { + r700->viewport[id].PA_SC_VPORT_ZMIN_0.f32All = 0.0; + r700->viewport[id].PA_SC_VPORT_ZMAX_0.f32All = 1.0; + CLEARbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_NEAR_DISABLE_bit); + CLEARbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_FAR_DISABLE_bit); + } + r700->viewport[id].enabled = GL_TRUE; r700SetScissor(context); @@ -1345,8 +1358,6 @@ void r700SetScissor(context_t *context) //--------------- SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask); - r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All = 0; - r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000; r700->viewport[id].enabled = GL_TRUE; } -- cgit v1.2.3 From c243e8dd23e8827afe926ec6314ffdfa15b3f7ab Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 29 Oct 2009 19:44:35 -0400 Subject: r600: remove the no rrb messages --- src/mesa/drivers/dri/r600/r700_chip.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index ace3d24f06..47b38d2e36 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -358,7 +358,6 @@ static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *a rrb = radeon_get_depthbuffer(&context->radeon); if (!rrb || !rrb->bo) { - fprintf(stderr, "no rrb\n"); return; } @@ -400,7 +399,6 @@ static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom * rrb = radeon_get_colorbuffer(&context->radeon); if (!rrb || !rrb->bo) { - fprintf(stderr, "no rrb\n"); return; } -- cgit v1.2.3 From 5f7d5d3ea3932ef6028b21bb22d8d28dbdd9fa9f Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Wed, 28 Oct 2009 18:02:22 +0200 Subject: r600: use AUTO_INDEX for draw - saves cmd buffer space also seems we can use INDX_OFFSET if start != 0 --- src/mesa/drivers/dri/r600/r700_render.c | 28 ++++++++++------------------ 1 file changed, 10 insertions(+), 18 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 9cf984f966..dc117183cb 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -259,8 +259,6 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim uint32_t vgt_index_type = 0; uint32_t vgt_primitive_type = 0; uint32_t vgt_num_indices = 0; - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *vb = &tnl->vb; GLboolean bUseDrawIndex; if(NULL != context->ind_buf.bo) @@ -287,6 +285,7 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim total_emit = 3 /* VGT_PRIMITIVE_TYPE */ + 2 /* VGT_INDEX_TYPE */ + 2 /* NUM_INSTANCES */ + + 3 /* VGT_INDEX_OFFSET */ + 5 + 2; /* DRAW_INDEX */ } else @@ -294,7 +293,8 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim total_emit = 3 /* VGT_PRIMITIVE_TYPE */ + 2 /* VGT_INDEX_TYPE */ + 2 /* NUM_INSTANCES */ - + num_indices + 3; /* DRAW_INDEX_IMMD */ + + 3 /* VGT_INDEX_OFFSET */ + + 3; /* DRAW_INDEX_IMMD */ } BEGIN_BATCH_NO_AUTOSTATE(total_emit); @@ -332,13 +332,15 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim } else { - SETfield(vgt_draw_initiator, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask); + SETfield(vgt_draw_initiator, DI_SRC_SEL_AUTO_INDEX, SOURCE_SELECT_shift, SOURCE_SELECT_mask); } SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask); if(GL_TRUE == bUseDrawIndex) { + R600_OUT_BATCH_REGSEQ(VGT_INDX_OFFSET, 1); + R600_OUT_BATCH(0); R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX, 3)); R600_OUT_BATCH(context->ind_buf.bo_offset); R600_OUT_BATCH(0); @@ -351,21 +353,11 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim } else { - R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (num_indices + 1))); + R600_OUT_BATCH_REGSEQ(VGT_INDX_OFFSET, 1); + R600_OUT_BATCH(start); + R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO,1)); R600_OUT_BATCH(vgt_num_indices); R600_OUT_BATCH(vgt_draw_initiator); - - for (i = start; i < (start + num_indices); i++) - { - if(vb->Elts) - { - R600_OUT_BATCH(vb->Elts[i]); - } - else - { - R600_OUT_BATCH(i); - } - } } END_BATCH(); @@ -391,7 +383,7 @@ static GLuint r700PredictRenderSize(GLcontext* ctx, else { for (i = 0; i < nr_prims; ++i) { - dwords += prim[i].count + 10; + dwords += 13; } } -- cgit v1.2.3 From 57864f6e0450c589059e07534e2af152bbefa75f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 30 Oct 2009 11:51:24 -0400 Subject: r600: fix a warning, update comments --- src/mesa/drivers/dri/r600/r700_render.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index dc117183cb..268bfd8bf0 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -253,7 +253,7 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim { context_t *context = R700_CONTEXT(ctx); BATCH_LOCALS(&context->radeon); - int type, i, total_emit; + int type, total_emit; int num_indices; uint32_t vgt_draw_initiator = 0; uint32_t vgt_index_type = 0; @@ -294,7 +294,7 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim + 2 /* VGT_INDEX_TYPE */ + 2 /* NUM_INSTANCES */ + 3 /* VGT_INDEX_OFFSET */ - + 3; /* DRAW_INDEX_IMMD */ + + 3; /* DRAW_INDEX_AUTO */ } BEGIN_BATCH_NO_AUTOSTATE(total_emit); @@ -335,7 +335,7 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim SETfield(vgt_draw_initiator, DI_SRC_SEL_AUTO_INDEX, SOURCE_SELECT_shift, SOURCE_SELECT_mask); } - SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask); + SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask); if(GL_TRUE == bUseDrawIndex) { -- cgit v1.2.3 From 703a836d4075b0e95633020765000430192986bb Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 30 Oct 2009 15:02:34 -0400 Subject: r600: fill in some missing tex formats This improves shadowtex since the component ordering is at least correct now, but I'm not sure how to deal with texturing from a depth surface yet due to differences in depth and color tile layouts. Signed-off-by: Alex Deucher --- src/mesa/drivers/dri/r600/r600_texstate.c | 46 +++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index c2f2be1d4c..6357d52523 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -85,10 +85,21 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + + SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED, + FORMAT_COMP_X_shift, FORMAT_COMP_X_mask); + SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED, + FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask); + SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED, + FORMAT_COMP_X_shift, FORMAT_COMP_Z_mask); + SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED, + FORMAT_COMP_W_shift, FORMAT_COMP_W_mask); switch (mesa_format) /* This is mesa format. */ { case MESA_FORMAT_RGBA8888: + case MESA_FORMAT_SIGNED_RGBA8888: SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); @@ -100,8 +111,19 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888) { + SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED, + FORMAT_COMP_X_shift, FORMAT_COMP_X_mask); + SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED, + FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask); + SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED, + FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask); + SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED, + FORMAT_COMP_W_shift, FORMAT_COMP_W_mask); + } break; case MESA_FORMAT_RGBA8888_REV: + case MESA_FORMAT_SIGNED_RGBA8888_REV: SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); @@ -113,6 +135,16 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); + if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888_REV) { + SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED, + FORMAT_COMP_X_shift, FORMAT_COMP_X_mask); + SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED, + FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask); + SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED, + FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask); + SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED, + FORMAT_COMP_W_shift, FORMAT_COMP_W_mask); + } break; case MESA_FORMAT_ARGB8888: SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8, @@ -479,14 +511,22 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); break; case MESA_FORMAT_Z16: + case MESA_FORMAT_X8_Z24: case MESA_FORMAT_S8_Z24: + case MESA_FORMAT_Z24_S8: case MESA_FORMAT_Z32: + case MESA_FORMAT_S8: switch (mesa_format) { case MESA_FORMAT_Z16: SETfield(t->SQ_TEX_RESOURCE1, FMT_16, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); break; + case MESA_FORMAT_X8_Z24: case MESA_FORMAT_S8_Z24: + SETfield(t->SQ_TEX_RESOURCE1, FMT_8_24, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + break; + case MESA_FORMAT_Z24_S8: SETfield(t->SQ_TEX_RESOURCE1, FMT_24_8, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); break; @@ -494,6 +534,12 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa SETfield(t->SQ_TEX_RESOURCE1, FMT_32, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); break; + case MESA_FORMAT_S8: + SETfield(t->SQ_TEX_RESOURCE1, FMT_8, + SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask); + break; + default: + break; }; switch (tObj->DepthMode) { case GL_LUMINANCE: /* X, X, X, ONE */ -- cgit v1.2.3 From b568a2c808cc2258c354bf14f640bb1f6eaba4ba Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 30 Oct 2009 15:08:09 -0400 Subject: r600: remove duplicate line --- src/mesa/drivers/dri/r600/r600_texstate.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 6357d52523..27c8354923 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -85,7 +85,6 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask); CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask); CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); - CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask); SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED, FORMAT_COMP_X_shift, FORMAT_COMP_X_mask); -- cgit v1.2.3 From d00cbba403640c82683a876fa795cd638f1bbc24 Mon Sep 17 00:00:00 2001 From: Pierre Ossman Date: Sun, 1 Nov 2009 21:38:48 +0100 Subject: r600: implement EXP op in compiler --- src/mesa/drivers/dri/r600/r700_assembler.c | 132 ++++++++++++++++++++++++++++- src/mesa/drivers/dri/r600/r700_assembler.h | 1 + 2 files changed, 130 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 917318c02a..fbf1f29fa3 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -2729,6 +2729,133 @@ GLboolean assemble_EX2(r700_AssemblerBase *pAsm) { return assemble_math_function(pAsm, SQ_OP2_INST_EXP_IEEE); } + +GLboolean assemble_EXP(r700_AssemblerBase *pAsm) +{ + BITS tmp; + + checkop1(pAsm); + + tmp = gethelpr(pAsm); + + // FLOOR tmp.x, a.x + // EX2 dst.x tmp.x + + if (pAsm->pILInst->DstReg.WriteMask & 0x1) { + pAsm->D.dst.opcode = SQ_OP2_INST_FLOOR; + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + pAsm->D.dst.writex = 1; + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP2_INST_EXP_IEEE; + pAsm->D.dst.math = 1; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.writey = pAsm->D.dst.writez = pAsm->D.dst.writew = 0; + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = DST_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp; + + setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X); + noneg_PVSSRC(&(pAsm->S[0].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + } + + // FRACT dst.y a.x + + if ((pAsm->pILInst->DstReg.WriteMask >> 1) & 0x1) { + pAsm->D.dst.opcode = SQ_OP2_INST_FRACT; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + pAsm->D.dst.writex = pAsm->D.dst.writez = pAsm->D.dst.writew = 0; + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + } + + // EX2 dst.z, a.x + + if ((pAsm->pILInst->DstReg.WriteMask >> 2) & 0x1) { + pAsm->D.dst.opcode = SQ_OP2_INST_EXP_IEEE; + pAsm->D.dst.math = 1; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + pAsm->D.dst.writex = pAsm->D.dst.writey = pAsm->D.dst.writew = 0; + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + } + + // MOV dst.w 1.0 + + if ((pAsm->pILInst->DstReg.WriteMask >> 3) & 0x1) { + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.writex = pAsm->D.dst.writey = pAsm->D.dst.writez = 0; + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp; + + setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_1); + noneg_PVSSRC(&(pAsm->S[0].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + } + + return GL_TRUE; +} GLboolean assemble_FLR(r700_AssemblerBase *pAsm) { @@ -4004,10 +4131,9 @@ GLboolean AssembleInstr(GLuint uiNumberInsts, return GL_FALSE; break; case OPCODE_EXP: - radeon_error("Not yet implemented instruction OPCODE_EXP \n"); - //if ( GL_FALSE == assemble_BAD("EXP") ) + if ( GL_FALSE == assemble_EXP(pR700AsmCode) ) return GL_FALSE; - break; // approx of EX2 + break; case OPCODE_FLR: if ( GL_FALSE == assemble_FLR(pR700AsmCode) ) diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index 8cbca066e9..317feb1b7d 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -477,6 +477,7 @@ GLboolean assemble_COS(r700_AssemblerBase *pAsm); GLboolean assemble_DOT(r700_AssemblerBase *pAsm); GLboolean assemble_DST(r700_AssemblerBase *pAsm); GLboolean assemble_EX2(r700_AssemblerBase *pAsm); +GLboolean assemble_EXP(r700_AssemblerBase *pAsm); GLboolean assemble_FLR(r700_AssemblerBase *pAsm); GLboolean assemble_FLR_INT(r700_AssemblerBase *pAsm); GLboolean assemble_FRC(r700_AssemblerBase *pAsm); -- cgit v1.2.3 From 213ec8251cb3e859b41306eae4092d89592c33db Mon Sep 17 00:00:00 2001 From: Pierre Ossman Date: Sun, 1 Nov 2009 22:28:02 +0100 Subject: r600: implement LOG op in compiler --- src/mesa/drivers/dri/r600/r700_assembler.c | 216 ++++++++++++++++++++++++++++- src/mesa/drivers/dri/r600/r700_assembler.h | 1 + 2 files changed, 214 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index fbf1f29fa3..e0d7d4fa6b 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -3037,6 +3037,217 @@ GLboolean assemble_LRP(r700_AssemblerBase *pAsm) return GL_TRUE; } +GLboolean assemble_LOG(r700_AssemblerBase *pAsm) +{ + BITS tmp1, tmp2, tmp3; + + checkop1(pAsm); + + tmp1 = gethelpr(pAsm); + tmp2 = gethelpr(pAsm); + tmp3 = gethelpr(pAsm); + + // FIXME: The hardware can do fabs() directly on input + // elements, but the compiler doesn't have the + // capability to use that. + + // MAX tmp1.x, a.x, -a.x (fabs(a.x)) + + pAsm->D.dst.opcode = SQ_OP2_INST_MAX; + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp1; + pAsm->D.dst.writex = 1; + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + pAsm->S[1].bits = pAsm->S[0].bits; + flipneg_PVSSRC(&(pAsm->S[1].src)); + + if ( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + // Entire algo: + // + // LG2 tmp2.x, tmp1.x + // FLOOR tmp3.x, tmp2.x + // MOV dst.x, tmp3.x + // ADD tmp3.x, tmp2.x, -tmp3.x + // EX2 dst.y, tmp3.x + // MOV dst.z, tmp2.x + // MOV dst.w, 1.0 + + // LG2 tmp2.x, tmp1.x + // FLOOR tmp3.x, tmp2.x + + pAsm->D.dst.opcode = SQ_OP2_INST_LOG_IEEE; + pAsm->D.dst.math = 1; + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp2; + pAsm->D.dst.writex = 1; + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = DST_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp1; + + setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X); + noneg_PVSSRC(&(pAsm->S[0].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP2_INST_FLOOR; + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp3; + pAsm->D.dst.writex = 1; + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = DST_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp2; + + setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X); + noneg_PVSSRC(&(pAsm->S[0].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + // MOV dst.x, tmp3.x + + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.writey = pAsm->D.dst.writez = pAsm->D.dst.writew = 0; + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = DST_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp3; + + setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X); + noneg_PVSSRC(&(pAsm->S[0].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + // ADD tmp3.x, tmp2.x, -tmp3.x + // EX2 dst.y, tmp3.x + + pAsm->D.dst.opcode = SQ_OP2_INST_ADD; + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp3; + pAsm->D.dst.writex = 1; + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = DST_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp2; + + setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X); + noneg_PVSSRC(&(pAsm->S[0].src)); + + setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); + pAsm->S[1].src.rtype = DST_REG_TEMPORARY; + pAsm->S[1].src.reg = tmp3; + + setswizzle_PVSSRC(&(pAsm->S[1].src), SQ_SEL_X); + neg_PVSSRC(&(pAsm->S[1].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP2_INST_EXP_IEEE; + pAsm->D.dst.math = 1; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.writex = pAsm->D.dst.writez = pAsm->D.dst.writew = 0; + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = DST_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp3; + + setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X); + noneg_PVSSRC(&(pAsm->S[0].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + // MOV dst.z, tmp2.x + + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.writex = pAsm->D.dst.writey = pAsm->D.dst.writew = 0; + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = DST_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp2; + + setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X); + noneg_PVSSRC(&(pAsm->S[0].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + // MOV dst.w 1.0 + + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.writex = pAsm->D.dst.writey = pAsm->D.dst.writez = 0; + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp1; + + setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_1); + noneg_PVSSRC(&(pAsm->S[0].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + GLboolean assemble_MAD(struct r700_AssemblerBase *pAsm) { int tmp, ii; @@ -4166,10 +4377,9 @@ GLboolean AssembleInstr(GLuint uiNumberInsts, return GL_FALSE; break; case OPCODE_LOG: - radeon_error("Not yet implemented instruction OPCODE_LOG \n"); - //if ( GL_FALSE == assemble_BAD("LOG") ) + if ( GL_FALSE == assemble_LOG(pR700AsmCode) ) return GL_FALSE; - break; // approx of LG2 + break; case OPCODE_MAD: if ( GL_FALSE == assemble_MAD(pR700AsmCode) ) diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index 317feb1b7d..c66db502a1 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -484,6 +484,7 @@ GLboolean assemble_FRC(r700_AssemblerBase *pAsm); GLboolean assemble_KIL(r700_AssemblerBase *pAsm); GLboolean assemble_LG2(r700_AssemblerBase *pAsm); GLboolean assemble_LRP(r700_AssemblerBase *pAsm); +GLboolean assemble_LOG(r700_AssemblerBase *pAsm); GLboolean assemble_MAD(r700_AssemblerBase *pAsm); GLboolean assemble_LIT(r700_AssemblerBase *pAsm); GLboolean assemble_MAX(r700_AssemblerBase *pAsm); -- cgit v1.2.3 From 70dade8afeadf83c6c993b39d3322e7c9353eea7 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 4 Nov 2009 14:43:24 -0500 Subject: r600: fix count prediction for IB case Signed-off-by: Alex Deucher --- src/mesa/drivers/dri/r600/r700_render.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 268bfd8bf0..b20b129d17 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -379,7 +379,7 @@ static GLuint r700PredictRenderSize(GLcontext* ctx, dwords = PRE_EMIT_STATE_BUFSZ; if (ib) - dwords += nr_prims * 14; + dwords += nr_prims * 17; else { for (i = 0; i < nr_prims; ++i) { -- cgit v1.2.3 From 9fce12b894c3af33d7a0732332446893682a48d5 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 4 Nov 2009 16:59:13 -0500 Subject: r600: rework draw functions Seems INDX_OFFSET doesn't work properly on some cards, so change back to immediate mode indices. Seems to only affect DRI1. Needs more investigation. Rework and clean up the draw functions. Signed-off-by: Alex Deucher --- src/mesa/drivers/dri/r600/r700_render.c | 198 +++++++++++++++++++++----------- 1 file changed, 134 insertions(+), 64 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index b20b129d17..c345b9d8ac 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -259,16 +259,6 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim uint32_t vgt_index_type = 0; uint32_t vgt_primitive_type = 0; uint32_t vgt_num_indices = 0; - GLboolean bUseDrawIndex; - - if(NULL != context->ind_buf.bo) - { - bUseDrawIndex = GL_TRUE; - } - else - { - bUseDrawIndex = GL_FALSE; - } type = r700PrimitiveType(prim); num_indices = r700NumVerts(end - start, prim); @@ -280,85 +270,154 @@ static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim if (type < 0 || num_indices <= 0) return; - if(GL_TRUE == bUseDrawIndex) - { - total_emit = 3 /* VGT_PRIMITIVE_TYPE */ - + 2 /* VGT_INDEX_TYPE */ - + 2 /* NUM_INSTANCES */ - + 3 /* VGT_INDEX_OFFSET */ - + 5 + 2; /* DRAW_INDEX */ - } - else - { - total_emit = 3 /* VGT_PRIMITIVE_TYPE */ - + 2 /* VGT_INDEX_TYPE */ - + 2 /* NUM_INSTANCES */ - + 3 /* VGT_INDEX_OFFSET */ - + 3; /* DRAW_INDEX_AUTO */ - } - - BEGIN_BATCH_NO_AUTOSTATE(total_emit); - // prim SETfield(vgt_primitive_type, type, VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask); - R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); - R600_OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX); - R600_OUT_BATCH(vgt_primitive_type); - // index type SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask); - if(GL_TRUE == bUseDrawIndex) + if(GL_TRUE != context->ind_buf.is_32bit) { - if(GL_TRUE != context->ind_buf.is_32bit) - { SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask); - } } + vgt_num_indices = num_indices; + SETfield(vgt_draw_initiator, DI_SRC_SEL_DMA, SOURCE_SELECT_shift, SOURCE_SELECT_mask); + SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask); + + total_emit = 3 /* VGT_PRIMITIVE_TYPE */ + + 2 /* VGT_INDEX_TYPE */ + + 2 /* NUM_INSTANCES */ + + 5 + 2; /* DRAW_INDEX */ + + BEGIN_BATCH_NO_AUTOSTATE(total_emit); + // prim + R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1); + R600_OUT_BATCH(vgt_primitive_type); + // index type R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); R600_OUT_BATCH(vgt_index_type); - // num instances R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0)); R600_OUT_BATCH(1); - // draw packet - vgt_num_indices = num_indices; + R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX, 3)); + R600_OUT_BATCH(context->ind_buf.bo_offset); + R600_OUT_BATCH(0); + R600_OUT_BATCH(vgt_num_indices); + R600_OUT_BATCH(vgt_draw_initiator); + R600_OUT_BATCH_RELOC(context->ind_buf.bo_offset, + context->ind_buf.bo, + context->ind_buf.bo_offset, + RADEON_GEM_DOMAIN_GTT, 0, 0); + END_BATCH(); + COMMIT_BATCH(); +} + +static void r700RunRenderPrimitiveImmediate(GLcontext * ctx, int start, int end, int prim) +{ + context_t *context = R700_CONTEXT(ctx); + BATCH_LOCALS(&context->radeon); + int type, i; + uint32_t num_indices, total_emit = 0; + uint32_t vgt_draw_initiator = 0; + uint32_t vgt_index_type = 0; + uint32_t vgt_primitive_type = 0; + uint32_t vgt_num_indices = 0; + + type = r700PrimitiveType(prim); + num_indices = r700NumVerts(end - start, prim); - if(GL_TRUE == bUseDrawIndex) + radeon_print(RADEON_RENDER, RADEON_TRACE, + "%s type %x num_indices %d\n", + __func__, type, num_indices); + + if (type < 0 || num_indices <= 0) + return; + + SETfield(vgt_primitive_type, type, + VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask); + + if (num_indices > 0xffff) { - SETfield(vgt_draw_initiator, DI_SRC_SEL_DMA, SOURCE_SELECT_shift, SOURCE_SELECT_mask); + SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask); } else { - SETfield(vgt_draw_initiator, DI_SRC_SEL_AUTO_INDEX, SOURCE_SELECT_shift, SOURCE_SELECT_mask); + SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask); } + vgt_num_indices = num_indices; SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask); - if(GL_TRUE == bUseDrawIndex) + if (start == 0) { - R600_OUT_BATCH_REGSEQ(VGT_INDX_OFFSET, 1); - R600_OUT_BATCH(0); - R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX, 3)); - R600_OUT_BATCH(context->ind_buf.bo_offset); - R600_OUT_BATCH(0); - R600_OUT_BATCH(vgt_num_indices); - R600_OUT_BATCH(vgt_draw_initiator); - R600_OUT_BATCH_RELOC(context->ind_buf.bo_offset, - context->ind_buf.bo, - context->ind_buf.bo_offset, - RADEON_GEM_DOMAIN_GTT, 0, 0); + SETfield(vgt_draw_initiator, DI_SRC_SEL_AUTO_INDEX, SOURCE_SELECT_shift, SOURCE_SELECT_mask); } else { - R600_OUT_BATCH_REGSEQ(VGT_INDX_OFFSET, 1); - R600_OUT_BATCH(start); - R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO,1)); + if (num_indices > 0xffff) + { + total_emit += num_indices; + } + else + { + total_emit += (num_indices + 1) / 2; + } + SETfield(vgt_draw_initiator, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask); + } + + total_emit += 3 /* VGT_PRIMITIVE_TYPE */ + + 2 /* VGT_INDEX_TYPE */ + + 2 /* NUM_INSTANCES */ + + 3; /* DRAW */ + + BEGIN_BATCH_NO_AUTOSTATE(total_emit); + // prim + R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1); + R600_OUT_BATCH(vgt_primitive_type); + // index type + R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); + R600_OUT_BATCH(vgt_index_type); + // num instances + R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0)); + R600_OUT_BATCH(1); + // draw packet + if(start == 0) + { + R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1)); R600_OUT_BATCH(vgt_num_indices); R600_OUT_BATCH(vgt_draw_initiator); } + else + { + if (num_indices > 0xffff) + { + R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (num_indices + 1))); + R600_OUT_BATCH(vgt_num_indices); + R600_OUT_BATCH(vgt_draw_initiator); + for (i = start; i < (start + num_indices); i++) + { + R600_OUT_BATCH(i); + } + } + else + { + R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (((num_indices + 1) / 2) + 1))); + R600_OUT_BATCH(vgt_num_indices); + R600_OUT_BATCH(vgt_draw_initiator); + for (i = start; i < (start + num_indices); i += 2) + { + if ((i + 1) == (start + num_indices)) + { + R600_OUT_BATCH(i); + } + else + { + R600_OUT_BATCH(((i + 1) << 16) | (i)); + } + } + } + } END_BATCH(); COMMIT_BATCH(); @@ -379,11 +438,16 @@ static GLuint r700PredictRenderSize(GLcontext* ctx, dwords = PRE_EMIT_STATE_BUFSZ; if (ib) - dwords += nr_prims * 17; + dwords += nr_prims * 14; else { for (i = 0; i < nr_prims; ++i) { - dwords += 13; + if (prim[i].start == 0) + dwords += 10; + else if (prim[i].count > 0xffff) + dwords += prim[i].count + 10; + else + dwords += ((prim[i].count + 1) / 2) + 10; } } @@ -840,10 +904,16 @@ static GLboolean r700TryDrawPrims(GLcontext *ctx, radeon_debug_add_indent(); for (i = 0; i < nr_prims; ++i) { - r700RunRenderPrimitive(ctx, - prim[i].start, - prim[i].start + prim[i].count, - prim[i].mode); + if (context->ind_buf.bo) + r700RunRenderPrimitive(ctx, + prim[i].start, + prim[i].start + prim[i].count, + prim[i].mode); + else + r700RunRenderPrimitiveImmediate(ctx, + prim[i].start, + prim[i].start + prim[i].count, + prim[i].mode); } radeon_debug_remove_indent(); -- cgit v1.2.3 From a9035f3dc313d047ce3af191d6d7ac8ada8167df Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 9 Nov 2009 11:34:13 -0500 Subject: r600: add missing ZPASS setup bits for r7xx+ --- src/mesa/drivers/dri/r600/r600_reg_r7xx.h | 2 ++ src/mesa/drivers/dri/r600/r700_state.c | 4 ++++ 2 files changed, 6 insertions(+) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_reg_r7xx.h b/src/mesa/drivers/dri/r600/r600_reg_r7xx.h index e5c01c861a..eb169bd885 100644 --- a/src/mesa/drivers/dri/r600/r600_reg_r7xx.h +++ b/src/mesa/drivers/dri/r600/r600_reg_r7xx.h @@ -143,6 +143,8 @@ enum { // SQ_TEX_SAMPLER_MISC_0 = 0x0003d03c, R7xx_TRUNCATE_COORD_bit = 1 << 9, R7xx_DISABLE_CUBE_WRAP_bit = 1 << 10, +// DB_RENDER_CONTROL = 0x00028d0c, + PERFECT_ZPASS_COUNTS_bit = 1 << 15, } ; diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index b278887266..b95fc87d30 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -1686,6 +1686,10 @@ void r700InitState(GLcontext * ctx) //------------------- SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask); SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask); SETbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit); + if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770) + { + CLEARbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit); + } r700->DB_ALPHA_TO_MASK.u32All = 0; SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask); -- cgit v1.2.3 From 37676b396a8416ad35253412d3a2e06482859a4d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 9 Nov 2009 11:36:10 -0500 Subject: r600: don't emit htile regs These are needed for HiZ which is not currently used and the _BASE reg requires a reloc which is not currently supported in the drm. --- src/mesa/drivers/dri/r600/r700_chip.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 47b38d2e36..ec76fbcb6d 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -784,8 +784,7 @@ static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&context->radeon); radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); - BEGIN_BATCH_NO_AUTOSTATE(23); - R600_OUT_BATCH_REGVAL(DB_HTILE_DATA_BASE, r700->DB_HTILE_DATA_BASE.u32All); + BEGIN_BATCH_NO_AUTOSTATE(17); R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2); R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All); @@ -798,7 +797,6 @@ static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom) R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All); R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All); - R600_OUT_BATCH_REGVAL(DB_HTILE_SURFACE, r700->DB_HTILE_SURFACE.u32All); R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All); END_BATCH(); @@ -1282,7 +1280,7 @@ void r600InitAtoms(context_t *context) context->radeon.hw.atomlist.name = "atom-list"; ALLOC_STATE(sq, always, 34, r700SendSQConfig); - ALLOC_STATE(db, always, 23, r700SendDBState); + ALLOC_STATE(db, always, 17, r700SendDBState); ALLOC_STATE(stencil, always, 4, r700SendStencilState); ALLOC_STATE(db_target, always, 12, r700SendDepthTargetState); ALLOC_STATE(sc, always, 15, r700SendSCState); -- cgit v1.2.3 From 66d6f9e860143c3d705f1d78c324159cadd258cc Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 9 Nov 2009 12:20:47 -0500 Subject: r600: rework DB render setup - consolidate DB render setup - only enable perfect ZPASS counts and cull disable when OQ is active - enable early Z --- src/mesa/drivers/dri/r600/r700_fragprog.c | 27 ++-------- src/mesa/drivers/dri/r600/r700_render.c | 4 +- src/mesa/drivers/dri/r600/r700_state.c | 82 +++++++++++++++++++++++++------ src/mesa/drivers/dri/r600/r700_state.h | 2 +- 4 files changed, 73 insertions(+), 42 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index 0f549ead9c..ccafd433bf 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -393,26 +393,6 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) SETfield(r700->ps.SQ_PGM_EXPORTS_PS.u32All, fp->r700Shader.exportMode, EXPORT_MODE_shift, EXPORT_MODE_mask); - R600_STATECHANGE(context, db); - - if(fp->r700Shader.killIsUsed) - { - SETbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit); - } - else - { - CLEARbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit); - } - - if(fp->r700Shader.depthIsExported) - { - SETbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit); - } - else - { - CLEARbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit); - } - // emit ps input map unBit = 1 << FRAG_ATTRIB_WPOS; if(mesa_fp->Base.InputsRead & unBit) @@ -479,9 +459,12 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) } } - R600_STATECHANGE(context, cb); exportCount = (r700->ps.SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift); - r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1; + if (r700->CB_SHADER_CONTROL.u32All != ((1 << exportCount) - 1)) + { + R600_STATECHANGE(context, cb); + r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1; + } /* sent out shader constants. */ paramList = fp->mesa_program.Base.Parameters; diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index c345b9d8ac..47f89c91f8 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -59,9 +59,7 @@ void r700WaitForIdle(context_t *context); void r700WaitForIdleClean(context_t *context); -GLboolean r700SendTextureState(context_t *context); static unsigned int r700PrimitiveType(int prim); -void r600UpdateTextureState(GLcontext * ctx); GLboolean r700SyncSurf(context_t *context, struct radeon_bo *pbo, uint32_t read_domain, @@ -891,7 +889,7 @@ static GLboolean r700TryDrawPrims(GLcontext *ctx, r700SetScissor(context); r700SetupVertexProgram(ctx); r700SetupFragmentProgram(ctx); - r600UpdateTextureState(ctx); + r700UpdateShaderStates(ctx); GLuint emit_end = r700PredictRenderSize(ctx, prim, ib, nr_prims) + context->radeon.cmdbuf.cs->cdw; diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index b95fc87d30..41000dc8ce 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -54,7 +54,7 @@ #include "r700_fragprog.h" #include "r700_vertprog.h" - +void r600UpdateTextureState(GLcontext * ctx); static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state); static void r700UpdatePolygonMode(GLcontext * ctx); static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state); @@ -191,6 +191,70 @@ static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //----------- context->radeon.NewGLState |= new_state; } +static void r700SetDBRenderState(GLcontext * ctx) +{ + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); + struct r700_fragment_program *fp = (struct r700_fragment_program *) + (ctx->FragmentProgram._Current); + + R600_STATECHANGE(context, db); + + SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit); + SETfield(r700->DB_SHADER_CONTROL.u32All, EARLY_Z_THEN_LATE_Z, Z_ORDER_shift, Z_ORDER_mask); + /* XXX not sure if this is required */ + if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) + SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit); + /* XXX need to enable htile for hiz/s */ + SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask); + SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask); + SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask); + + if (context->radeon.query.current) + { + SETbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit); + if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770) + { + SETbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit); + } + } + else + { + CLEARbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit); + if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770) + { + CLEARbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit); + } + } + + if (fp) + { + if (fp->r700Shader.killIsUsed) + { + SETbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit); + } + else + { + CLEARbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit); + } + + if (fp->r700Shader.depthIsExported) + { + SETbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit); + } + else + { + CLEARbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit); + } + } +} + +void r700UpdateShaderStates(GLcontext * ctx) +{ + r700SetDBRenderState(ctx); + r600UpdateTextureState(ctx); +} + static void r700SetDepthState(GLcontext * ctx) { context_t *context = R700_CONTEXT(ctx); @@ -1672,24 +1736,10 @@ void r700InitState(GLcontext * ctx) //------------------- r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test); r700DepthMask(ctx, ctx->Depth.Mask); r700DepthFunc(ctx, ctx->Depth.Func); - SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit); - r700->DB_DEPTH_CLEAR.u32All = 0x3F800000; - - r700->DB_RENDER_CONTROL.u32All = 0; SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit); SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit); - r700->DB_RENDER_OVERRIDE.u32All = 0; - if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) - SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit); - SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask); - SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask); - SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask); - SETbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit); - if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770) - { - CLEARbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit); - } + r700SetDBRenderState(ctx); r700->DB_ALPHA_TO_MASK.u32All = 0; SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask); diff --git a/src/mesa/drivers/dri/r600/r700_state.h b/src/mesa/drivers/dri/r600/r700_state.h index 209189d8d7..60c6a7f23c 100644 --- a/src/mesa/drivers/dri/r600/r700_state.h +++ b/src/mesa/drivers/dri/r600/r700_state.h @@ -35,7 +35,7 @@ extern void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state); extern void r700UpdateShaders (GLcontext * ctx); -extern void r700UpdateShaders2(GLcontext * ctx); +extern void r700UpdateShaderStates(GLcontext * ctx); extern void r700UpdateViewportOffset(GLcontext * ctx); -- cgit v1.2.3 From 74ef3207d8bd97a529e7b0ab8d99e44c805f3af0 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 9 Nov 2009 11:36:10 -0500 Subject: r600: don't emit htile regs These are needed for HiZ which is not currently used and the _BASE reg requires a reloc which is not currently supported in the drm. --- src/mesa/drivers/dri/r600/r700_chip.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 06d7e9c9ab..8707a764ac 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -794,8 +794,7 @@ static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom) BATCH_LOCALS(&context->radeon); radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); - BEGIN_BATCH_NO_AUTOSTATE(23); - R600_OUT_BATCH_REGVAL(DB_HTILE_DATA_BASE, r700->DB_HTILE_DATA_BASE.u32All); + BEGIN_BATCH_NO_AUTOSTATE(17); R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2); R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All); @@ -808,7 +807,6 @@ static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom) R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All); R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All); - R600_OUT_BATCH_REGVAL(DB_HTILE_SURFACE, r700->DB_HTILE_SURFACE.u32All); R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All); END_BATCH(); @@ -1239,7 +1237,7 @@ void r600InitAtoms(context_t *context) context->radeon.hw.atomlist.name = "atom-list"; ALLOC_STATE(sq, always, 34, r700SendSQConfig); - ALLOC_STATE(db, always, 23, r700SendDBState); + ALLOC_STATE(db, always, 17, r700SendDBState); ALLOC_STATE(stencil, always, 4, r700SendStencilState); ALLOC_STATE(db_target, always, 12, r700SendDepthTargetState); ALLOC_STATE(sc, always, 15, r700SendSCState); -- cgit v1.2.3 From 216319fc0fe5dc3f298dd602812afa0f28a4ee60 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Mon, 9 Nov 2009 22:37:41 +0100 Subject: r600/r700: typo, fix mask of DB_ALPHA_TO_MASK --- src/mesa/drivers/dri/r600/r600_reg_r6xx.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_reg_r6xx.h b/src/mesa/drivers/dri/r600/r600_reg_r6xx.h index f7702c46de..74af7b4fed 100644 --- a/src/mesa/drivers/dri/r600/r600_reg_r6xx.h +++ b/src/mesa/drivers/dri/r600/r600_reg_r6xx.h @@ -415,11 +415,11 @@ enum { ALPHA_TO_MASK_ENABLE = 1 << 0, ALPHA_TO_MASK_OFFSET0_mask = 0x03 << 8, ALPHA_TO_MASK_OFFSET0_shift = 8, - ALPHA_TO_MASK_OFFSET1_mask = 0x03 << 8, + ALPHA_TO_MASK_OFFSET1_mask = 0x03 << 10, ALPHA_TO_MASK_OFFSET1_shift = 10, - ALPHA_TO_MASK_OFFSET2_mask = 0x03 << 8, + ALPHA_TO_MASK_OFFSET2_mask = 0x03 << 12, ALPHA_TO_MASK_OFFSET2_shift = 12, - ALPHA_TO_MASK_OFFSET3_mask = 0x03 << 8, + ALPHA_TO_MASK_OFFSET3_mask = 0x03 << 14, ALPHA_TO_MASK_OFFSET3_shift = 14, // SQ_VTX_CONSTANT_WORD2_0 = 0x00038008, -- cgit v1.2.3 From d683acb101a65d0688bfd0818a0ddb4be16e376d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 16 Nov 2009 15:03:48 -0500 Subject: r600: don't force Z order Let the hw decide (early vs late Z) fixes fdo bug 25092 Signed-off-by: Alex Deucher --- src/mesa/drivers/dri/r600/r700_state.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 41000dc8ce..d7420678ff 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -202,9 +202,6 @@ static void r700SetDBRenderState(GLcontext * ctx) SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit); SETfield(r700->DB_SHADER_CONTROL.u32All, EARLY_Z_THEN_LATE_Z, Z_ORDER_shift, Z_ORDER_mask); - /* XXX not sure if this is required */ - if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) - SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit); /* XXX need to enable htile for hiz/s */ SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask); SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask); -- cgit v1.2.3 From 7118db870091d4c9c2465e79f361ff0ed36d1f90 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Wed, 18 Nov 2009 22:02:48 +0100 Subject: r600: align for mipmap tree changes --- src/mesa/drivers/dri/r600/r600_tex.c | 17 +++----------- src/mesa/drivers/dri/r600/r600_texstate.c | 37 ++++++++++++------------------- src/mesa/drivers/dri/r600/r700_chip.c | 10 ++++++--- 3 files changed, 24 insertions(+), 40 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_tex.c b/src/mesa/drivers/dri/r600/r600_tex.c index 20965bb3c8..9d83a64e22 100644 --- a/src/mesa/drivers/dri/r600/r600_tex.c +++ b/src/mesa/drivers/dri/r600/r600_tex.c @@ -312,16 +312,7 @@ static void r600TexParameter(GLcontext * ctx, GLenum target, case GL_TEXTURE_MAX_LEVEL: case GL_TEXTURE_MIN_LOD: case GL_TEXTURE_MAX_LOD: - /* This isn't the most efficient solution but there doesn't appear to - * be a nice alternative. Since there's no LOD clamping, - * we just have to rely on loading the right subset of mipmap levels - * to simulate a clamped LOD. - */ - if (t->mt) { - radeon_miptree_unreference(t->mt); - t->mt = 0; - t->validated = GL_FALSE; - } + t->validated = GL_FALSE; break; case GL_DEPTH_TEXTURE_MODE: @@ -369,10 +360,8 @@ static void r600DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) t->bo = NULL; } - if (t->mt) { - radeon_miptree_unreference(t->mt); - t->mt = 0; - } + radeon_miptree_unreference(&t->mt); + _mesa_delete_texture_object(ctx, texObj); } diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 27c8354923..4ec315b78c 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -649,7 +649,6 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex { radeonTexObj *t = radeon_tex_obj(texObj); const struct gl_texture_image *firstImage; - int firstlevel = t->mt ? t->mt->firstLevel : 0; GLuint uTexelPitch, row_align; if (rmesa->radeon.radeonScreen->driScreen->dri2.enabled && @@ -657,7 +656,7 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex t->bo) return; - firstImage = t->base.Image[0][firstlevel]; + firstImage = t->base.Image[0][t->minLod]; if (!t->image_override) { if (!r600GetTexFormat(texObj, firstImage->TexFormat)) { @@ -692,7 +691,8 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex } row_align = rmesa->radeon.texture_row_align - 1; - uTexelPitch = ((firstImage->Width * t->mt->bpp + row_align) & ~row_align) / t->mt->bpp; + uTexelPitch = (_mesa_format_row_stride(firstImage->TexFormat, firstImage->Width) + row_align) & ~row_align; + uTexelPitch = uTexelPitch / _mesa_get_format_bytes(firstImage->TexFormat); uTexelPitch = (uTexelPitch + R700_TEXEL_PITCH_ALIGNMENT_MASK) & ~R700_TEXEL_PITCH_ALIGNMENT_MASK; @@ -706,10 +706,10 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex SETfield(t->SQ_TEX_RESOURCE1, firstImage->Height - 1, TEX_HEIGHT_shift, TEX_HEIGHT_mask); - if ((t->mt->lastLevel - t->mt->firstLevel) > 0) { - t->SQ_TEX_RESOURCE3 = t->mt->levels[0].size / 256; - SETfield(t->SQ_TEX_RESOURCE4, t->mt->firstLevel, BASE_LEVEL_shift, BASE_LEVEL_mask); - SETfield(t->SQ_TEX_RESOURCE5, t->mt->lastLevel, LAST_LEVEL_shift, LAST_LEVEL_mask); + if ((t->maxLod - t->minLod) > 0) { + t->SQ_TEX_RESOURCE3 = t->mt->levels[t->minLod].size / 256; + SETfield(t->SQ_TEX_RESOURCE4, 0, BASE_LEVEL_shift, BASE_LEVEL_mask); + SETfield(t->SQ_TEX_RESOURCE5, t->maxLod - t->minLod, LAST_LEVEL_shift, LAST_LEVEL_mask); } } @@ -808,9 +808,8 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname, struct gl_texture_object *tObj = _mesa_lookup_texture(rmesa->radeon.glCtx, texname); radeonTexObjPtr t = radeon_tex_obj(tObj); - int firstlevel = t->mt ? t->mt->firstLevel : 0; const struct gl_texture_image *firstImage; - uint32_t pitch_val, size, row_align, bpp; + uint32_t pitch_val, size, row_align; if (!tObj) return; @@ -820,13 +819,9 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname, if (!offset) return; - bpp = depth / 8; - if (bpp == 3) - bpp = 4; - - firstImage = t->base.Image[0][firstlevel]; + firstImage = t->base.Image[0][t->minLod]; row_align = rmesa->radeon.texture_row_align - 1; - size = ((firstImage->Width * bpp + row_align) & ~row_align) * firstImage->Height; + size = ((_mesa_format_row_stride(firstImage->TexFormat, firstImage->Width) + row_align) & ~row_align) * firstImage->Height; if (t->bo) { radeon_bo_unref(t->bo); t->bo = NULL; @@ -949,14 +944,10 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo radeon_bo_unref(rImage->bo); rImage->bo = NULL; } - if (t->mt) { - radeon_miptree_unreference(t->mt); - t->mt = NULL; - } - if (rImage->mt) { - radeon_miptree_unreference(rImage->mt); - rImage->mt = NULL; - } + + radeon_miptree_unreference(&t->mt); + radeon_miptree_unreference(&rImage->mt); + _mesa_init_teximage_fields(radeon->glCtx, target, texImage, rb->base.Width, rb->base.Height, 1, 0, rb->cpp); texImage->RowStride = rb->pitch / rb->cpp; diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index ec76fbcb6d..2b2b4d748f 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -54,11 +54,15 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom) for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) { if (ctx->Texture.Unit[i]._ReallyEnabled) { radeonTexObj *t = r700->textures[i]; + uint32_t offset; if (t) { - if (!t->image_override) + if (!t->image_override) { bo = t->mt->bo; - else + offset = get_base_teximage_offset(t); + } else { bo = t->bo; + offset = 0; + } if (bo) { r700SyncSurf(context, bo, @@ -77,7 +81,7 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom) R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6); R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2, bo, - 0, + offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3, bo, -- cgit v1.2.3 From fe5c46546e740a16a13fe9e8aaa4b071bc13d70b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 18 Nov 2009 11:51:20 -0500 Subject: r600: disable compressed texture support It's not implemented yet. fixes fdo bug 24047 --- src/mesa/drivers/dri/r600/r600_context.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index e0b77d4385..8dab57b433 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -362,6 +362,7 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, (&r600->radeon.optionCache, "disable_stencil_two_side")) _mesa_disable_extension(ctx, "GL_EXT_stencil_two_side"); +#if 0 if (r600->radeon.glCtx->Mesa_DXTn && !driQueryOptionb(&r600->radeon.optionCache, "disable_s3tc")) { _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc"); @@ -371,6 +372,9 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, { _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc"); } +#else + _mesa_disable_extension(ctx, "GL_ARB_texture_compression"); +#endif radeon_fbo_init(&r600->radeon); radeonInitSpanFuncs( ctx ); -- cgit v1.2.3 From 3132853e1242607d5ff62785cd7dad5ef3a783d0 Mon Sep 17 00:00:00 2001 From: Richard Li Date: Tue, 17 Nov 2009 16:25:02 -0500 Subject: r600 : Initial version of glsl fc. --- src/mesa/drivers/dri/r600/r700_assembler.c | 2572 ++++++++++++++++++++++++---- src/mesa/drivers/dri/r600/r700_assembler.h | 111 +- src/mesa/drivers/dri/r600/r700_chip.c | 99 +- src/mesa/drivers/dri/r600/r700_fragprog.c | 94 +- src/mesa/drivers/dri/r600/r700_shader.c | 9 +- src/mesa/drivers/dri/r600/r700_shader.h | 3 +- src/mesa/drivers/dri/r600/r700_vertprog.c | 21 +- 7 files changed, 2507 insertions(+), 402 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index e0d7d4fa6b..4b5d40bd3a 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -38,6 +38,8 @@ #include "r700_assembler.h" +#define USE_CF_FOR_CONTINUE_BREAK 1 + BITS addrmode_PVSDST(PVSDST * pPVSDST) { return pPVSDST->addrmode0 | ((BITS)pPVSDST->addrmode1 << 1); @@ -343,6 +345,8 @@ unsigned int r700GetNumOperands(r700_AssemblerBase* pAsm) case SQ_OP2_INST_MIN: //case SQ_OP2_INST_MAX_DX10: //case SQ_OP2_INST_MIN_DX10: + case SQ_OP2_INST_SETE: + case SQ_OP2_INST_SETNE: case SQ_OP2_INST_SETGT: case SQ_OP2_INST_SETGE: case SQ_OP2_INST_PRED_SETE: @@ -398,6 +402,9 @@ int Init_r700_AssemblerBase(SHADER_PIPE_TYPE spt, r700_AssemblerBase* pAsm, R700 pAsm->number_of_exports = 0; pAsm->number_of_export_opcodes = 0; + pAsm->alu_x_opcode = 0; + + pAsm->D2.bits = 0; pAsm->D.bits = 0; pAsm->S[0].bits = 0; @@ -474,6 +481,22 @@ int Init_r700_AssemblerBase(SHADER_PIPE_TYPE spt, r700_AssemblerBase* pAsm, R700 pAsm->is_tex = GL_FALSE; pAsm->need_tex_barrier = GL_FALSE; + pAsm->subs = NULL; + pAsm->unSubArraySize = 0; + pAsm->unSubArrayPointer = 0; + pAsm->callers = NULL; + pAsm->unCallerArraySize = 0; + pAsm->unCallerArrayPointer = 0; + + pAsm->CALLSP = 0; + pAsm->CALLSTACK[0].FCSP_BeforeEntry; + pAsm->CALLSTACK[0].plstCFInstructions_local + = &(pAsm->pR700Shader->lstCFInstructions); + + SetActiveCFlist(pAsm->pR700Shader, pAsm->CALLSTACK[0].plstCFInstructions_local); + + pAsm->unCFflags = 0; + return 0; } @@ -592,6 +615,31 @@ int check_current_clause(r700_AssemblerBase* pAsm, return GL_TRUE; } +GLboolean add_cf_instruction(r700_AssemblerBase* pAsm) +{ + if(GL_FALSE == check_current_clause(pAsm, CF_OTHER_CLAUSE)) + { + return GL_FALSE; + } + + pAsm->cf_current_cf_clause_ptr = + (R700ControlFlowGenericClause*) CALLOC_STRUCT(R700ControlFlowGenericClause); + + if (pAsm->cf_current_cf_clause_ptr != NULL) + { + Init_R700ControlFlowGenericClause(pAsm->cf_current_cf_clause_ptr); + AddCFInstruction( pAsm->pR700Shader, + (R700ControlFlowInstruction *)pAsm->cf_current_cf_clause_ptr ); + } + else + { + radeon_error("Could not allocate a new VFetch CF instruction.\n"); + return GL_FALSE; + } + + return GL_TRUE; +} + GLboolean add_vfetch_instruction(r700_AssemblerBase* pAsm, R700VertexInstruction* vertex_instruction_ptr) { @@ -1153,6 +1201,7 @@ GLboolean assemble_src(r700_AssemblerBase *pAsm, case PROGRAM_LOCAL_PARAM: case PROGRAM_ENV_PARAM: case PROGRAM_STATE_VAR: + case PROGRAM_UNIFORM: if (1 == pILInst->SrcReg[src].RelAddr) { setaddrmode_PVSSRC(&(pAsm->S[fld].src), ADDR_RELATIVE_A0); @@ -1179,7 +1228,7 @@ GLboolean assemble_src(r700_AssemblerBase *pAsm, } break; default: - radeon_error("Invalid source argument type\n"); + radeon_error("Invalid source argument type : %d \n", pILInst->SrcReg[src].File); return GL_FALSE; } } @@ -1315,7 +1364,7 @@ GLboolean tex_src(r700_AssemblerBase *pAsm) case FRAG_ATTRIB_TEX0: case FRAG_ATTRIB_TEX1: case FRAG_ATTRIB_TEX2: - case FRAG_ATTRIB_TEX3: + case FRAG_ATTRIB_TEX3: case FRAG_ATTRIB_TEX4: case FRAG_ATTRIB_TEX5: case FRAG_ATTRIB_TEX6: @@ -1335,6 +1384,16 @@ GLboolean tex_src(r700_AssemblerBase *pAsm) fprintf(stderr, "FRAG_ATTRIB_VAR0 unsupported\n"); break; } + + if( (pILInst->SrcReg[0].Index >= FRAG_ATTRIB_VAR0) || + (pILInst->SrcReg[0].Index < FRAG_ATTRIB_MAX) ) + { + bValidTexCoord = GL_TRUE; + pAsm->S[0].src.reg = + pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index]; + pAsm->S[0].src.rtype = SRC_REG_INPUT; + } + break; } } @@ -1517,6 +1576,10 @@ GLboolean assemble_alu_src(R700ALUInstruction* alu_instruction_ptr, { src_sel = pSource->reg + CFILE_REGISTER_OFFSET; } + else if (pSource->rtype == SRC_REC_LITERAL) + { + src_sel = SQ_ALU_SRC_LITERAL; + } else { radeon_error("Source (%d) register type (%d) not one of TEMP, INPUT, or CONSTANT.\n", @@ -1606,7 +1669,8 @@ GLboolean add_alu_instruction(r700_AssemblerBase* pAsm, return GL_FALSE; } - if ( pAsm->cf_current_alu_clause_ptr == NULL || + if ( pAsm->alu_x_opcode != 0 || + pAsm->cf_current_alu_clause_ptr == NULL || ( (pAsm->cf_current_alu_clause_ptr != NULL) && (pAsm->cf_current_alu_clause_ptr->m_Word1.f.count >= (GetCFMaxInstructions(pAsm->cf_current_alu_clause_ptr->m_ShaderInstType)-contiguous_slots_needed-1) ) ) ) @@ -1636,9 +1700,17 @@ GLboolean add_alu_instruction(r700_AssemblerBase* pAsm, pAsm->cf_current_alu_clause_ptr->m_Word1.f.kcache_addr0 = 0x0; pAsm->cf_current_alu_clause_ptr->m_Word1.f.kcache_addr1 = 0x0; - //cf_current_alu_clause_ptr->m_Word1.f.count = number_of_scalar_operations - 1; pAsm->cf_current_alu_clause_ptr->m_Word1.f.count = 0x0; - pAsm->cf_current_alu_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_ALU; + + if(pAsm->alu_x_opcode != 0) + { + pAsm->cf_current_alu_clause_ptr->m_Word1.f.cf_inst = pAsm->alu_x_opcode; + pAsm->alu_x_opcode = 0; + } + else + { + pAsm->cf_current_alu_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_ALU; + } pAsm->cf_current_alu_clause_ptr->m_Word1.f.whole_quad_mode = 0x0; @@ -2358,146 +2430,711 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) return GL_TRUE; } -GLboolean next_ins(r700_AssemblerBase *pAsm) +GLboolean assemble_alu_instruction2(r700_AssemblerBase *pAsm) { - struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); + GLuint number_of_scalar_operations; + GLboolean is_single_scalar_operation; + GLuint scalar_channel_index; - if( GL_TRUE == pAsm->is_tex ) + PVSSRC * pcurrent_source; + int current_source_index; + GLuint contiguous_slots_needed; + + GLuint uNumSrc = r700GetNumOperands(pAsm); + + GLboolean bSplitInst = GL_FALSE; + + if (1 == pAsm->D.dst.math) { - if (pILInst->TexSrcTarget == TEXTURE_RECT_INDEX) { - if( GL_FALSE == assemble_tex_instruction(pAsm, GL_FALSE) ) - { - radeon_error("Error assembling TEX instruction\n"); - return GL_FALSE; - } - } else { - if( GL_FALSE == assemble_tex_instruction(pAsm, GL_TRUE) ) - { - radeon_error("Error assembling TEX instruction\n"); - return GL_FALSE; - } - } + is_single_scalar_operation = GL_TRUE; + number_of_scalar_operations = 1; } else - { //ALU - if( GL_FALSE == assemble_alu_instruction(pAsm) ) - { - radeon_error("Error assembling ALU instruction\n"); - return GL_FALSE; - } - } - - if(pAsm->D.dst.rtype == DST_REG_OUT) { - if(pAsm->D.dst.op3) - { - // There is no mask for OP3 instructions, so all channels are written - pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number] = 0xF; - } - else - { - pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number] - |= (unsigned char)pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask; - } + is_single_scalar_operation = GL_FALSE; + number_of_scalar_operations = 4; } - - //reset for next inst. - pAsm->D.bits = 0; - pAsm->S[0].bits = 0; - pAsm->S[1].bits = 0; - pAsm->S[2].bits = 0; - pAsm->is_tex = GL_FALSE; - pAsm->need_tex_barrier = GL_FALSE; - return GL_TRUE; -} - -GLboolean assemble_math_function(r700_AssemblerBase* pAsm, BITS opcode) -{ - BITS tmp; - - checkop1(pAsm); - - tmp = gethelpr(pAsm); - - // opcode tmp.x, a.x - // MOV dst, tmp.x - pAsm->D.dst.opcode = opcode; - pAsm->D.dst.math = 1; - - setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); - pAsm->D.dst.rtype = DST_REG_TEMPORARY; - pAsm->D.dst.reg = tmp; - pAsm->D.dst.writex = 1; + contiguous_slots_needed = 0; - if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + if(GL_TRUE == is_reduction_opcode(&(pAsm->D)) ) { - return GL_FALSE; + contiguous_slots_needed = 4; } - if ( GL_FALSE == next_ins(pAsm) ) + initialize(pAsm); + + for (scalar_channel_index=0; + scalar_channel_index < number_of_scalar_operations; + scalar_channel_index++) { - return GL_FALSE; - } + R700ALUInstruction* alu_instruction_ptr = (R700ALUInstruction*) CALLOC_STRUCT(R700ALUInstruction); + if (alu_instruction_ptr == NULL) + { + return GL_FALSE; + } + Init_R700ALUInstruction(alu_instruction_ptr); + + //src 0 + current_source_index = 0; + pcurrent_source = &(pAsm->S[0].src); - // Now replicate result to all necessary channels in destination - pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + if (GL_FALSE == assemble_alu_src(alu_instruction_ptr, + current_source_index, + pcurrent_source, + scalar_channel_index) ) + { + return GL_FALSE; + } + + if (uNumSrc > 1) + { + // Process source 1 + current_source_index = 1; + pcurrent_source = &(pAsm->S[current_source_index].src); - if( GL_FALSE == assemble_dst(pAsm) ) - { - return GL_FALSE; - } + if (GL_FALSE == assemble_alu_src(alu_instruction_ptr, + current_source_index, + pcurrent_source, + scalar_channel_index) ) + { + return GL_FALSE; + } + } - setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); - pAsm->S[0].src.rtype = DST_REG_TEMPORARY; - pAsm->S[0].src.reg = tmp; + //other bits + alu_instruction_ptr->m_Word0.f.index_mode = SQ_INDEX_LOOP; - setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X); - noneg_PVSSRC(&(pAsm->S[0].src)); + if( (is_single_scalar_operation == GL_TRUE) + || (GL_TRUE == bSplitInst) ) + { + alu_instruction_ptr->m_Word0.f.last = 1; + } + else + { + alu_instruction_ptr->m_Word0.f.last = (scalar_channel_index == 3) ? 1 : 0; + } - if( GL_FALSE == next_ins(pAsm) ) - { - return GL_FALSE; - } + alu_instruction_ptr->m_Word0.f.pred_sel = (pAsm->D.dst.pred_inv > 0) ? 1 : 0; + if(1 == pAsm->D.dst.predicated) + { + alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0x1; + alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0x1; + } + else + { + alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0x0; + alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0x0; + } + + // dst + if( (pAsm->D.dst.rtype == DST_REG_TEMPORARY) || + (pAsm->D.dst.rtype == DST_REG_OUT) ) + { + alu_instruction_ptr->m_Word1.f.dst_gpr = pAsm->D.dst.reg; + } + else + { + radeon_error("Only temp destination registers supported for ALU dest regs.\n"); + return GL_FALSE; + } - return GL_TRUE; -} + alu_instruction_ptr->m_Word1.f.dst_rel = SQ_ABSOLUTE; //D.rtype -GLboolean assemble_ABS(r700_AssemblerBase *pAsm) -{ - checkop1(pAsm); + if ( is_single_scalar_operation == GL_TRUE ) + { + // Override scalar_channel_index since only one scalar value will be written + if(pAsm->D.dst.writex) + { + scalar_channel_index = 0; + } + else if(pAsm->D.dst.writey) + { + scalar_channel_index = 1; + } + else if(pAsm->D.dst.writez) + { + scalar_channel_index = 2; + } + else if(pAsm->D.dst.writew) + { + scalar_channel_index = 3; + } + } - pAsm->D.dst.opcode = SQ_OP2_INST_MAX; + alu_instruction_ptr->m_Word1.f.dst_chan = scalar_channel_index; - if( GL_FALSE == assemble_dst(pAsm) ) - { - return GL_FALSE; - } - if( GL_FALSE == assemble_src(pAsm, 0, -1) ) - { - return GL_FALSE; - } - - pAsm->S[1].bits = pAsm->S[0].bits; - flipneg_PVSSRC(&(pAsm->S[1].src)); + alu_instruction_ptr->m_Word1.f.clamp = pAsm->D2.dst2.SaturateMode; - if ( GL_FALSE == next_ins(pAsm) ) - { - return GL_FALSE; - } + if (pAsm->D.dst.op3) + { + //op3 - return GL_TRUE; -} + alu_instruction_ptr->m_Word1_OP3.f.alu_inst = pAsm->D.dst.opcode; -GLboolean assemble_ADD(r700_AssemblerBase *pAsm) -{ - if( GL_FALSE == checkop2(pAsm) ) - { - return GL_FALSE; - } + //There's 3rd src for op3 + current_source_index = 2; + pcurrent_source = &(pAsm->S[current_source_index].src); - pAsm->D.dst.opcode = SQ_OP2_INST_ADD; - + if ( GL_FALSE == assemble_alu_src(alu_instruction_ptr, + current_source_index, + pcurrent_source, + scalar_channel_index) ) + { + return GL_FALSE; + } + } + else + { + //op2 + if (pAsm->bR6xx) + { + alu_instruction_ptr->m_Word1_OP2.f6.alu_inst = pAsm->D.dst.opcode; + + alu_instruction_ptr->m_Word1_OP2.f6.src0_abs = 0x0; + alu_instruction_ptr->m_Word1_OP2.f6.src1_abs = 0x0; + + //alu_instruction_ptr->m_Word1_OP2.f6.update_execute_mask = 0x0; + //alu_instruction_ptr->m_Word1_OP2.f6.update_pred = 0x0; + switch (scalar_channel_index) + { + case 0: + alu_instruction_ptr->m_Word1_OP2.f6.write_mask = pAsm->D.dst.writex; + break; + case 1: + alu_instruction_ptr->m_Word1_OP2.f6.write_mask = pAsm->D.dst.writey; + break; + case 2: + alu_instruction_ptr->m_Word1_OP2.f6.write_mask = pAsm->D.dst.writez; + break; + case 3: + alu_instruction_ptr->m_Word1_OP2.f6.write_mask = pAsm->D.dst.writew; + break; + default: + alu_instruction_ptr->m_Word1_OP2.f6.write_mask = 1; //SQ_SEL_MASK; + break; + } + alu_instruction_ptr->m_Word1_OP2.f6.omod = SQ_ALU_OMOD_OFF; + } + else + { + alu_instruction_ptr->m_Word1_OP2.f.alu_inst = pAsm->D.dst.opcode; + + alu_instruction_ptr->m_Word1_OP2.f.src0_abs = 0x0; + alu_instruction_ptr->m_Word1_OP2.f.src1_abs = 0x0; + + //alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0x0; + //alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0x0; + switch (scalar_channel_index) + { + case 0: + alu_instruction_ptr->m_Word1_OP2.f.write_mask = pAsm->D.dst.writex; + break; + case 1: + alu_instruction_ptr->m_Word1_OP2.f.write_mask = pAsm->D.dst.writey; + break; + case 2: + alu_instruction_ptr->m_Word1_OP2.f.write_mask = pAsm->D.dst.writez; + break; + case 3: + alu_instruction_ptr->m_Word1_OP2.f.write_mask = pAsm->D.dst.writew; + break; + default: + alu_instruction_ptr->m_Word1_OP2.f.write_mask = 1; //SQ_SEL_MASK; + break; + } + alu_instruction_ptr->m_Word1_OP2.f.omod = SQ_ALU_OMOD_OFF; + } + } + + if(GL_FALSE == add_alu_instruction(pAsm, alu_instruction_ptr, contiguous_slots_needed) ) + { + return GL_FALSE; + } + + /* + * Judge the type of current instruction, is it vector or scalar + * instruction. + */ + if (is_single_scalar_operation) + { + if(GL_FALSE == check_scalar(pAsm, alu_instruction_ptr) ) + { + return GL_FALSE; + } + } + else + { + if(GL_FALSE == check_vector(pAsm, alu_instruction_ptr) ) + { + return 1; + } + } + + contiguous_slots_needed = 0; + } + + return GL_TRUE; +} + +GLboolean assemble_alu_instruction_literal(r700_AssemblerBase *pAsm, GLfloat * pLiteral) +{ + R700ALUInstruction * alu_instruction_ptr; + R700ALUInstructionHalfLiteral * alu_instruction_ptr_hl; + R700ALUInstructionFullLiteral * alu_instruction_ptr_fl; + + GLuint number_of_scalar_operations; + GLboolean is_single_scalar_operation; + GLuint scalar_channel_index; + + GLuint contiguous_slots_needed; + GLuint lastInstruction; + GLuint not_masked[4]; + + GLuint uNumSrc = r700GetNumOperands(pAsm); + + GLboolean bSplitInst = GL_FALSE; + + number_of_scalar_operations = 0; + contiguous_slots_needed = 0; + + if(1 == pAsm->D.dst.writew) + { + lastInstruction = 3; + number_of_scalar_operations++; + not_masked[3] = 1; + } + else + { + not_masked[3] = 0; + } + if(1 == pAsm->D.dst.writez) + { + lastInstruction = 2; + number_of_scalar_operations++; + not_masked[2] = 1; + } + else + { + not_masked[2] = 0; + } + if(1 == pAsm->D.dst.writey) + { + lastInstruction = 1; + number_of_scalar_operations++; + not_masked[1] = 1; + } + else + { + not_masked[1] = 0; + } + if(1 == pAsm->D.dst.writex) + { + lastInstruction = 0; + number_of_scalar_operations++; + not_masked[0] = 1; + } + else + { + not_masked[0] = 0; + } + + if(GL_TRUE == is_reduction_opcode(&(pAsm->D)) ) + { + contiguous_slots_needed = 4; + } + else + { + contiguous_slots_needed = number_of_scalar_operations; + } + + if(1 == pAsm->D2.dst2.literal) + { + contiguous_slots_needed += 1; + } + else if(2 == pAsm->D2.dst2.literal) + { + contiguous_slots_needed += 2; + } + + initialize(pAsm); + + for (scalar_channel_index=0; scalar_channel_index < 4; scalar_channel_index++) + { + if(0 == not_masked[scalar_channel_index]) + { + continue; + } + + if(scalar_channel_index == lastInstruction) + { + switch (pAsm->D2.dst2.literal) + { + case 0: + alu_instruction_ptr = (R700ALUInstruction*) CALLOC_STRUCT(R700ALUInstruction); + if (alu_instruction_ptr == NULL) + { + return GL_FALSE; + } + Init_R700ALUInstruction(alu_instruction_ptr); + break; + case 1: + alu_instruction_ptr_hl = (R700ALUInstructionHalfLiteral*) CALLOC_STRUCT(R700ALUInstructionHalfLiteral); + if (alu_instruction_ptr_hl == NULL) + { + return GL_FALSE; + } + Init_R700ALUInstructionHalfLiteral(alu_instruction_ptr_hl, pLiteral[0], pLiteral[1]); + alu_instruction_ptr = (R700ALUInstruction*)alu_instruction_ptr_hl; + break; + case 2: + alu_instruction_ptr_fl = (R700ALUInstructionFullLiteral*) CALLOC_STRUCT(R700ALUInstructionFullLiteral); + if (alu_instruction_ptr_fl == NULL) + { + return GL_FALSE; + } + Init_R700ALUInstructionFullLiteral(alu_instruction_ptr_fl, pLiteral[0], pLiteral[1], pLiteral[2], pLiteral[3]); + alu_instruction_ptr = (R700ALUInstruction*)alu_instruction_ptr_fl; + break; + default: + break; + }; + } + else + { + alu_instruction_ptr = (R700ALUInstruction*) CALLOC_STRUCT(R700ALUInstruction); + if (alu_instruction_ptr == NULL) + { + return GL_FALSE; + } + Init_R700ALUInstruction(alu_instruction_ptr); + } + + //src 0 + if (GL_FALSE == assemble_alu_src(alu_instruction_ptr, + 0, + &(pAsm->S[0].src), + scalar_channel_index) ) + { + return GL_FALSE; + } + + if (uNumSrc > 1) + { + // Process source 1 + if (GL_FALSE == assemble_alu_src(alu_instruction_ptr, + 1, + &(pAsm->S[1].src), + scalar_channel_index) ) + { + return GL_FALSE; + } + } + + //other bits + alu_instruction_ptr->m_Word0.f.index_mode = SQ_INDEX_LOOP; + + if(scalar_channel_index == lastInstruction) + { + alu_instruction_ptr->m_Word0.f.last = 1; + } + + alu_instruction_ptr->m_Word0.f.pred_sel = 0x0; + if(1 == pAsm->D.dst.predicated) + { + alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0x1; + alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0x1; + } + else + { + alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0; + alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0; + } + + // dst + if( (pAsm->D.dst.rtype == DST_REG_TEMPORARY) || + (pAsm->D.dst.rtype == DST_REG_OUT) ) + { + alu_instruction_ptr->m_Word1.f.dst_gpr = pAsm->D.dst.reg; + } + else + { + radeon_error("Only temp destination registers supported for ALU dest regs.\n"); + return GL_FALSE; + } + + alu_instruction_ptr->m_Word1.f.dst_rel = SQ_ABSOLUTE; //D.rtype + + alu_instruction_ptr->m_Word1.f.dst_chan = scalar_channel_index; + + alu_instruction_ptr->m_Word1.f.clamp = pAsm->D2.dst2.SaturateMode; + + if (pAsm->D.dst.op3) + { + //op3 + alu_instruction_ptr->m_Word1_OP3.f.alu_inst = pAsm->D.dst.opcode; + + //There's 3rd src for op3 + if ( GL_FALSE == assemble_alu_src(alu_instruction_ptr, + 2, + &(pAsm->S[2].src), + scalar_channel_index) ) + { + return GL_FALSE; + } + } + else + { + //op2 + if (pAsm->bR6xx) + { + alu_instruction_ptr->m_Word1_OP2.f6.alu_inst = pAsm->D.dst.opcode; + alu_instruction_ptr->m_Word1_OP2.f6.src0_abs = 0x0; + alu_instruction_ptr->m_Word1_OP2.f6.src1_abs = 0x0; + alu_instruction_ptr->m_Word1_OP2.f6.write_mask = 1; + alu_instruction_ptr->m_Word1_OP2.f6.omod = SQ_ALU_OMOD_OFF; + } + else + { + alu_instruction_ptr->m_Word1_OP2.f.alu_inst = pAsm->D.dst.opcode; + alu_instruction_ptr->m_Word1_OP2.f.src0_abs = 0x0; + alu_instruction_ptr->m_Word1_OP2.f.src1_abs = 0x0; + alu_instruction_ptr->m_Word1_OP2.f.write_mask = 1; + alu_instruction_ptr->m_Word1_OP2.f.omod = SQ_ALU_OMOD_OFF; + } + } + + if(GL_FALSE == add_alu_instruction(pAsm, alu_instruction_ptr, contiguous_slots_needed) ) + { + return GL_FALSE; + } + + if (1 == number_of_scalar_operations) + { + if(GL_FALSE == check_scalar(pAsm, alu_instruction_ptr) ) + { + return GL_FALSE; + } + } + else + { + if(GL_FALSE == check_vector(pAsm, alu_instruction_ptr) ) + { + return GL_FALSE; + } + } + + contiguous_slots_needed -= 2; + } + + return GL_TRUE; +} + +GLboolean next_ins(r700_AssemblerBase *pAsm) +{ + struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); + + if( GL_TRUE == pAsm->is_tex ) + { + if (pILInst->TexSrcTarget == TEXTURE_RECT_INDEX) { + if( GL_FALSE == assemble_tex_instruction(pAsm, GL_FALSE) ) + { + radeon_error("Error assembling TEX instruction\n"); + return GL_FALSE; + } + } else { + if( GL_FALSE == assemble_tex_instruction(pAsm, GL_TRUE) ) + { + radeon_error("Error assembling TEX instruction\n"); + return GL_FALSE; + } + } + } + else + { //ALU + if( GL_FALSE == assemble_alu_instruction(pAsm) ) + { + radeon_error("Error assembling ALU instruction\n"); + return GL_FALSE; + } + } + + if(pAsm->D.dst.rtype == DST_REG_OUT) + { + if(pAsm->D.dst.op3) + { + // There is no mask for OP3 instructions, so all channels are written + pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number] = 0xF; + } + else + { + pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number] + |= (unsigned char)pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask; + } + } + + //reset for next inst. + pAsm->D.bits = 0; + pAsm->D2.bits = 0; + pAsm->S[0].bits = 0; + pAsm->S[1].bits = 0; + pAsm->S[2].bits = 0; + pAsm->is_tex = GL_FALSE; + pAsm->need_tex_barrier = GL_FALSE; + + return GL_TRUE; +} + +GLboolean next_ins2(r700_AssemblerBase *pAsm) +{ + struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); + + //ALU + if( GL_FALSE == assemble_alu_instruction2(pAsm) ) + { + radeon_error("Error assembling ALU instruction\n"); + return GL_FALSE; + } + + if(pAsm->D.dst.rtype == DST_REG_OUT) + { + if(pAsm->D.dst.op3) + { + // There is no mask for OP3 instructions, so all channels are written + pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number] = 0xF; + } + else + { + pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number] + |= (unsigned char)pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask; + } + } + + //reset for next inst. + pAsm->D.bits = 0; + pAsm->D2.bits = 0; + pAsm->S[0].bits = 0; + pAsm->S[1].bits = 0; + pAsm->S[2].bits = 0; + pAsm->is_tex = GL_FALSE; + pAsm->need_tex_barrier = GL_FALSE; + + //richard nov.16 glsl + pAsm->D2.bits = 0; + + return GL_TRUE; +} + +/* not work yet */ +GLboolean next_ins_literal(r700_AssemblerBase *pAsm, GLfloat * pLiteral) +{ + struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); + + //ALU + if( GL_FALSE == assemble_alu_instruction_literal(pAsm, pLiteral) ) + { + radeon_error("Error assembling ALU instruction\n"); + return GL_FALSE; + } + + //reset for next inst. + pAsm->D.bits = 0; + pAsm->D2.bits = 0; + pAsm->S[0].bits = 0; + pAsm->S[1].bits = 0; + pAsm->S[2].bits = 0; + pAsm->is_tex = GL_FALSE; + pAsm->need_tex_barrier = GL_FALSE; + return GL_TRUE; +} + +GLboolean assemble_math_function(r700_AssemblerBase* pAsm, BITS opcode) +{ + BITS tmp; + + checkop1(pAsm); + + tmp = gethelpr(pAsm); + + // opcode tmp.x, a.x + // MOV dst, tmp.x + + pAsm->D.dst.opcode = opcode; + pAsm->D.dst.math = 1; + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + pAsm->D.dst.writex = 1; + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if ( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + // Now replicate result to all necessary channels in destination + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = DST_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp; + + setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X); + noneg_PVSSRC(&(pAsm->S[0].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_ABS(r700_AssemblerBase *pAsm) +{ + checkop1(pAsm); + + pAsm->D.dst.opcode = SQ_OP2_INST_MAX; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + pAsm->S[1].bits = pAsm->S[0].bits; + flipneg_PVSSRC(&(pAsm->S[1].src)); + + if ( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_ADD(r700_AssemblerBase *pAsm) +{ + if( GL_FALSE == checkop2(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP2_INST_ADD; + if( GL_FALSE == assemble_dst(pAsm) ) { return GL_FALSE; @@ -3809,10 +4446,78 @@ GLboolean assemble_SCS(r700_AssemblerBase *pAsm) pAsm->S[0].src.swizzlez = SQ_SEL_0; pAsm->S[0].src.swizzlew = SQ_SEL_0; - if ( GL_FALSE == next_ins(pAsm) ) - { - return GL_FALSE; - } + if ( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_LOGIC(r700_AssemblerBase *pAsm, BITS opcode) +{ + if( GL_FALSE == checkop2(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = opcode; + pAsm->D.dst.math = 1; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 1, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_LOGIC_PRED(r700_AssemblerBase *pAsm, BITS opcode) +{ + if( GL_FALSE == checkop2(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = opcode; + pAsm->D.dst.math = 1; + pAsm->D.dst.predicated = 1; + pAsm->D2.dst2.SaturateMode = pAsm->pILInst[pAsm->uiCurInst].SaturateMode; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 1, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == next_ins2(pAsm) ) + { + return GL_FALSE; + } return GL_TRUE; } @@ -4077,223 +4782,930 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) pAsm->D.dst.writez = 0; pAsm->D.dst.writew = 0; - setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); - pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; - pAsm->S[0].src.reg = tmp2; - noswizzle_PVSSRC(&(pAsm->S[0].src)); - setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); - pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; - pAsm->S[1].src.reg = 252; // SQ_ALU_SRC_0_5 - noswizzle_PVSSRC(&(pAsm->S[1].src)); + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp2; + noswizzle_PVSSRC(&(pAsm->S[0].src)); + setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); + pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[1].src.reg = 252; // SQ_ALU_SRC_0_5 + noswizzle_PVSSRC(&(pAsm->S[1].src)); + + next_ins(pAsm); + + /* tmp1.xy = temp2.xy */ + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp1; + pAsm->D.dst.writex = 1; + pAsm->D.dst.writey = 1; + pAsm->D.dst.writez = 0; + pAsm->D.dst.writew = 0; + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp2; + noswizzle_PVSSRC(&(pAsm->S[0].src)); + + next_ins(pAsm); + pAsm->aArgSubst[1] = tmp1; + need_barrier = GL_TRUE; + + } + + pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE; + pAsm->is_tex = GL_TRUE; + if ( GL_TRUE == need_barrier ) + { + pAsm->need_tex_barrier = GL_TRUE; + } + // Set src1 to tex unit id + pAsm->S[1].src.reg = pAsm->pILInst[pAsm->uiCurInst].TexSrcUnit; + pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; + + //No sw info from mesa compiler, so hard code here. + pAsm->S[1].src.swizzlex = SQ_SEL_X; + pAsm->S[1].src.swizzley = SQ_SEL_Y; + pAsm->S[1].src.swizzlez = SQ_SEL_Z; + pAsm->S[1].src.swizzlew = SQ_SEL_W; + + if( GL_FALSE == tex_dst(pAsm) ) + { + return GL_FALSE; + } + + if( GL_FALSE == tex_src(pAsm) ) + { + return GL_FALSE; + } + + if(pAsm->pILInst[pAsm->uiCurInst].Opcode == OPCODE_TXP) + { + /* hopefully did swizzles before */ + noswizzle_PVSSRC(&(pAsm->S[0].src)); + } + + if(pAsm->pILInst[pAsm->uiCurInst].TexSrcTarget == TEXTURE_CUBE_INDEX) + { + /* SAMPLE dst, tmp.yxwy, CUBE */ + pAsm->S[0].src.swizzlex = SQ_SEL_Y; + pAsm->S[0].src.swizzley = SQ_SEL_X; + pAsm->S[0].src.swizzlez = SQ_SEL_W; + pAsm->S[0].src.swizzlew = SQ_SEL_Y; + } + + if ( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + return GL_TRUE; +} + +GLboolean assemble_XPD(r700_AssemblerBase *pAsm) +{ + BITS tmp; + + if( GL_FALSE == checkop2(pAsm) ) + { + return GL_FALSE; + } + + tmp = gethelpr(pAsm); + + pAsm->D.dst.opcode = SQ_OP2_INST_MUL; + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + nomask_PVSDST(&(pAsm->D.dst)); + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 1, -1) ) + { + return GL_FALSE; + } + + swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_Z, SQ_SEL_X, SQ_SEL_Y, SQ_SEL_0); + swizzleagain_PVSSRC(&(pAsm->S[1].src), SQ_SEL_Y, SQ_SEL_Z, SQ_SEL_X, SQ_SEL_0); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP3_INST_MULADD; + pAsm->D.dst.op3 = 1; + + if(0xF != pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask) + { + tmp = gethelpr(pAsm); + + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + + nomask_PVSDST(&(pAsm->D.dst)); + } + else + { + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + } + + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } + + if( GL_FALSE == assemble_src(pAsm, 1, -1) ) + { + return GL_FALSE; + } + + swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_Y, SQ_SEL_Z, SQ_SEL_X, SQ_SEL_0); + swizzleagain_PVSSRC(&(pAsm->S[1].src), SQ_SEL_Z, SQ_SEL_X, SQ_SEL_Y, SQ_SEL_0); + + // result1 + (neg) result0 + setaddrmode_PVSSRC(&(pAsm->S[2].src),ADDR_ABSOLUTE); + pAsm->S[2].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[2].src.reg = tmp; + + neg_PVSSRC(&(pAsm->S[2].src)); + noswizzle_PVSSRC(&(pAsm->S[2].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + + + if(0xF != pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask) + { + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + + // Use tmp as source + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp; + + noneg_PVSSRC(&(pAsm->S[0].src)); + noswizzle_PVSSRC(&(pAsm->S[0].src)); + + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } + } + + return GL_TRUE; +} + +GLboolean assemble_EXPORT(r700_AssemblerBase *pAsm) +{ + return GL_TRUE; +} + +GLboolean jumpToOffest(r700_AssemblerBase *pAsm, GLuint pops, GLint offset) +{ + if(GL_FALSE == add_cf_instruction(pAsm) ) + { + return GL_FALSE; + } + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = pops; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_JUMP; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1; + + pAsm->cf_current_cf_clause_ptr->m_Word0.f.addr = pAsm->cf_current_cf_clause_ptr->m_uIndex + offset; + + return GL_TRUE; +} + +GLboolean pops(r700_AssemblerBase *pAsm, GLuint pops) +{ + if(GL_FALSE == add_cf_instruction(pAsm) ) + { + return GL_FALSE; + } + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = pops; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_POP; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1; + pAsm->cf_current_cf_clause_ptr->m_Word0.f.addr = pAsm->cf_current_cf_clause_ptr->m_uIndex + 1; + + return GL_TRUE; +} + +GLboolean assemble_IF(r700_AssemblerBase *pAsm) +{ + if(GL_FALSE == add_cf_instruction(pAsm) ) + { + return GL_FALSE; + } + + if(GL_TRUE != bHasElse) + { + pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 1; + } + else + { + pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 0; + } + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_JUMP; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1; + + pAsm->FCSP++; + pAsm->fc_stack[pAsm->FCSP].type = FC_IF; + pAsm->fc_stack[pAsm->FCSP].bpush = 0; + pAsm->fc_stack[pAsm->FCSP].mid = NULL; + pAsm->fc_stack[pAsm->FCSP].midLen= 0; + pAsm->fc_stack[pAsm->FCSP].first = pAsm->cf_current_cf_clause_ptr; + + if(GL_TRUE != bHasElse) + { + pAsm->alu_x_opcode = SQ_CF_INST_ALU_POP_AFTER; + } + + pAsm->branch_depth++; + + if(pAsm->branch_depth > pAsm->max_branch_depth) + { + pAsm->max_branch_depth = pAsm->branch_depth; + } + return GL_TRUE; +} + +GLboolean assemble_ELSE(r700_AssemblerBase *pAsm) +{ + if(GL_FALSE == add_cf_instruction(pAsm) ) + { + return GL_FALSE; + } + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 1; /// + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE; - next_ins(pAsm); + pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_ELSE; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0; - /* tmp1.xy = temp2.xy */ - pAsm->D.dst.opcode = SQ_OP2_INST_MOV; - setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); - pAsm->D.dst.rtype = DST_REG_TEMPORARY; - pAsm->D.dst.reg = tmp1; - pAsm->D.dst.writex = 1; - pAsm->D.dst.writey = 1; - pAsm->D.dst.writez = 0; - pAsm->D.dst.writew = 0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1; - setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); - pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; - pAsm->S[0].src.reg = tmp2; - noswizzle_PVSSRC(&(pAsm->S[0].src)); + pAsm->fc_stack[pAsm->FCSP].mid = (R700ControlFlowGenericClause **)_mesa_realloc( (void *)pAsm->fc_stack[pAsm->FCSP].mid, + 0, + sizeof(R700ControlFlowGenericClause *) ); + pAsm->fc_stack[pAsm->FCSP].mid[0] = pAsm->cf_current_cf_clause_ptr; + //pAsm->fc_stack[pAsm->FCSP].unNumMid = 1; - next_ins(pAsm); - pAsm->aArgSubst[1] = tmp1; - need_barrier = GL_TRUE; + pAsm->alu_x_opcode = SQ_CF_INST_ALU_POP_AFTER; + + pAsm->fc_stack[pAsm->FCSP].first->m_Word0.f.addr = pAsm->pR700Shader->plstCFInstructions_active->uNumOfNode - 1; + + return GL_TRUE; +} + +GLboolean assemble_ENDIF(r700_AssemblerBase *pAsm) +{ + pAsm->alu_x_opcode = SQ_CF_INST_ALU; + if(NULL == pAsm->fc_stack[pAsm->FCSP].mid) + { + /* no else in between */ + pAsm->fc_stack[pAsm->FCSP].first->m_Word0.f.addr = pAsm->pR700Shader->plstCFInstructions_active->uNumOfNode; + } + else + { + pAsm->fc_stack[pAsm->FCSP].mid[0]->m_Word0.f.addr = pAsm->pR700Shader->plstCFInstructions_active->uNumOfNode; } - pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE; - pAsm->is_tex = GL_TRUE; - if ( GL_TRUE == need_barrier ) + if(NULL != pAsm->fc_stack[pAsm->FCSP].mid) { - pAsm->need_tex_barrier = GL_TRUE; + FREE(pAsm->fc_stack[pAsm->FCSP].mid); } - // Set src1 to tex unit id - pAsm->S[1].src.reg = pAsm->pILInst[pAsm->uiCurInst].TexSrcUnit; - pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; - //No sw info from mesa compiler, so hard code here. - pAsm->S[1].src.swizzlex = SQ_SEL_X; - pAsm->S[1].src.swizzley = SQ_SEL_Y; - pAsm->S[1].src.swizzlez = SQ_SEL_Z; - pAsm->S[1].src.swizzlew = SQ_SEL_W; + if(pAsm->fc_stack[pAsm->FCSP].type != FC_IF) + { + radeon_error("if/endif in shader code are not paired. \n"); + return GL_FALSE; + } + pAsm->branch_depth--; + pAsm->FCSP--; - if( GL_FALSE == tex_dst(pAsm) ) + return GL_TRUE; +} + +GLboolean assemble_BGNLOOP(r700_AssemblerBase *pAsm) +{ + if(GL_FALSE == add_cf_instruction(pAsm) ) { return GL_FALSE; } - if( GL_FALSE == tex_src(pAsm) ) + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_LOOP_START_NO_AL; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1; + + pAsm->FCSP++; + pAsm->fc_stack[pAsm->FCSP].type = FC_LOOP; + pAsm->fc_stack[pAsm->FCSP].bpush = 1; + pAsm->fc_stack[pAsm->FCSP].mid = NULL; + pAsm->fc_stack[pAsm->FCSP].unNumMid = 0; + pAsm->fc_stack[pAsm->FCSP].midLen = 0; + pAsm->fc_stack[pAsm->FCSP].first = pAsm->cf_current_cf_clause_ptr; + + pAsm->branch_depth++; + + if(pAsm->branch_depth > pAsm->max_branch_depth) + { + pAsm->max_branch_depth = pAsm->branch_depth; + } + return GL_TRUE; +} + +GLboolean assemble_BRK(r700_AssemblerBase *pAsm) +{ +#ifdef USE_CF_FOR_CONTINUE_BREAK + unsigned int unFCSP; + for(unFCSP=pAsm->FCSP; unFCSP>0; unFCSP--) + { + if(FC_LOOP == pAsm->fc_stack[unFCSP].type) + { + break; + } + } + if(0 == FC_LOOP) { + radeon_error("Break is not inside loop/endloop pair.\n"); return GL_FALSE; } - if(pAsm->pILInst[pAsm->uiCurInst].Opcode == OPCODE_TXP) + if(GL_FALSE == add_cf_instruction(pAsm) ) { - /* hopefully did swizzles before */ - noswizzle_PVSSRC(&(pAsm->S[0].src)); + return GL_FALSE; } - - if(pAsm->pILInst[pAsm->uiCurInst].TexSrcTarget == TEXTURE_CUBE_INDEX) + + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 1; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_LOOP_BREAK; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1; + + pAsm->fc_stack[unFCSP].mid = (R700ControlFlowGenericClause **)_mesa_realloc( + (void *)pAsm->fc_stack[unFCSP].mid, + sizeof(R700ControlFlowGenericClause *) * pAsm->fc_stack[unFCSP].unNumMid, + sizeof(R700ControlFlowGenericClause *) * (pAsm->fc_stack[unFCSP].unNumMid + 1) ); + pAsm->fc_stack[unFCSP].mid[pAsm->fc_stack[unFCSP].unNumMid] = pAsm->cf_current_cf_clause_ptr; + pAsm->fc_stack[unFCSP].unNumMid++; + + if(GL_FALSE == add_cf_instruction(pAsm) ) { - /* SAMPLE dst, tmp.yxwy, CUBE */ - pAsm->S[0].src.swizzlex = SQ_SEL_Y; - pAsm->S[0].src.swizzley = SQ_SEL_X; - pAsm->S[0].src.swizzlez = SQ_SEL_W; - pAsm->S[0].src.swizzlew = SQ_SEL_Y; + return GL_FALSE; } + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 1; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_POP; - if ( GL_FALSE == next_ins(pAsm) ) - { - return GL_FALSE; - } + pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1; + pAsm->cf_current_cf_clause_ptr->m_Word0.f.addr = pAsm->cf_current_cf_clause_ptr->m_uIndex + 1; +#endif //USE_CF_FOR_CONTINUE_BREAK return GL_TRUE; } -GLboolean assemble_XPD(r700_AssemblerBase *pAsm) +GLboolean assemble_CONT(r700_AssemblerBase *pAsm) { - BITS tmp; +#ifdef USE_CF_FOR_CONTINUE_BREAK + unsigned int unFCSP; + for(unFCSP=pAsm->FCSP; unFCSP>0; unFCSP--) + { + if(FC_LOOP == pAsm->fc_stack[unFCSP].type) + { + break; + } + } + if(0 == FC_LOOP) + { + radeon_error("Continue is not inside loop/endloop pair.\n"); + return GL_FALSE; + } - if( GL_FALSE == checkop2(pAsm) ) + if(GL_FALSE == add_cf_instruction(pAsm) ) { - return GL_FALSE; + return GL_FALSE; } - tmp = gethelpr(pAsm); + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 1; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE; - pAsm->D.dst.opcode = SQ_OP2_INST_MUL; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_LOOP_CONTINUE; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0; - setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); - pAsm->D.dst.rtype = DST_REG_TEMPORARY; - pAsm->D.dst.reg = tmp; - nomask_PVSDST(&(pAsm->D.dst)); - - if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1; + + pAsm->fc_stack[unFCSP].mid = (R700ControlFlowGenericClause **)_mesa_realloc( + (void *)pAsm->fc_stack[unFCSP].mid, + sizeof(R700ControlFlowGenericClause *) * pAsm->fc_stack[unFCSP].unNumMid, + sizeof(R700ControlFlowGenericClause *) * (pAsm->fc_stack[unFCSP].unNumMid + 1) ); + pAsm->fc_stack[unFCSP].mid[pAsm->fc_stack[unFCSP].unNumMid] = pAsm->cf_current_cf_clause_ptr; + pAsm->fc_stack[unFCSP].unNumMid++; + + if(GL_FALSE == add_cf_instruction(pAsm) ) { return GL_FALSE; } - if( GL_FALSE == assemble_src(pAsm, 1, -1) ) + pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 1; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_POP; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1; + pAsm->cf_current_cf_clause_ptr->m_Word0.f.addr = pAsm->cf_current_cf_clause_ptr->m_uIndex + 1; + +#endif /* USE_CF_FOR_CONTINUE_BREAK */ + + return GL_TRUE; +} + +GLboolean assemble_ENDLOOP(r700_AssemblerBase *pAsm) +{ + GLuint i; + + if(GL_FALSE == add_cf_instruction(pAsm) ) { return GL_FALSE; } - - swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_Z, SQ_SEL_X, SQ_SEL_Y, SQ_SEL_0); - swizzleagain_PVSSRC(&(pAsm->S[1].src), SQ_SEL_Y, SQ_SEL_Z, SQ_SEL_X, SQ_SEL_0); - if( GL_FALSE == next_ins(pAsm) ) + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_LOOP_END; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1; + + pAsm->cf_current_cf_clause_ptr->m_Word0.f.addr = pAsm->fc_stack[pAsm->FCSP].first->m_uIndex + 1; + pAsm->fc_stack[pAsm->FCSP].first->m_Word0.f.addr = pAsm->cf_current_cf_clause_ptr->m_uIndex + 1; + +#ifdef USE_CF_FOR_CONTINUE_BREAK + for(i=0; ifc_stack[pAsm->FCSP].unNumMid; i++) + { + pAsm->fc_stack[pAsm->FCSP].mid[i]->m_Word0.f.addr = pAsm->cf_current_cf_clause_ptr->m_uIndex; + } + if(NULL != pAsm->fc_stack[pAsm->FCSP].mid) + { + FREE(pAsm->fc_stack[pAsm->FCSP].mid); + } +#endif + + if(pAsm->fc_stack[pAsm->FCSP].type != FC_LOOP) { + radeon_error("loop/endloop in shader code are not paired. \n"); return GL_FALSE; } - pAsm->D.dst.opcode = SQ_OP3_INST_MULADD; - pAsm->D.dst.op3 = 1; + unsigned int unFCSP = 0; + if((pAsm->unCFflags & HAS_CURRENT_LOOPRET) > 0) + { + for(unFCSP=(pAsm->FCSP-1); unFCSP>pAsm->CALLSTACK[pAsm->CALLSP].FCSP_BeforeEntry; unFCSP--) + { + if(FC_LOOP == pAsm->fc_stack[unFCSP].type) + { + break; + } + } + if(unFCSP <= pAsm->CALLSTACK[pAsm->CALLSP].FCSP_BeforeEntry) + { + unFCSP = 0; - if(0xF != pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask) - { - tmp = gethelpr(pAsm); + returnOnFlag(pAsm); + pAsm->unCFflags &= ~HAS_CURRENT_LOOPRET; + } + } - setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); - pAsm->D.dst.rtype = DST_REG_TEMPORARY; - pAsm->D.dst.reg = tmp; + pAsm->branch_depth--; + pAsm->FCSP--; - nomask_PVSDST(&(pAsm->D.dst)); + if(unFCSP > 0) + { + breakLoopOnFlag(pAsm, unFCSP); } - else + + return GL_TRUE; +} + +void add_return_inst(r700_AssemblerBase *pAsm) +{ + if(GL_FALSE == add_cf_instruction(pAsm) ) { - if( GL_FALSE == assemble_dst(pAsm) ) + return GL_FALSE; + } + //pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 1; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_RETURN; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1; +} + +GLboolean assemble_BGNSUB(r700_AssemblerBase *pAsm, GLint nILindex) +{ + /* Put in sub */ + if( (pAsm->unSubArrayPointer + 1) > pAsm->unSubArraySize ) + { + pAsm->subs = (SUB_OFFSET*)_mesa_realloc( (void *)pAsm->subs, + sizeof(SUB_OFFSET) * pAsm->unSubArraySize, + sizeof(SUB_OFFSET) * (pAsm->unSubArraySize + 10) ); + if(NULL == pAsm->subs) { return GL_FALSE; } + pAsm->unSubArraySize += 10; } - if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + pAsm->subs[pAsm->unSubArrayPointer].subIL_Offset = nILindex; + pAsm->subs[pAsm->unSubArrayPointer].lstCFInstructions_local.pHead=NULL; + pAsm->subs[pAsm->unSubArrayPointer].lstCFInstructions_local.pTail=NULL; + pAsm->subs[pAsm->unSubArrayPointer].lstCFInstructions_local.uNumOfNode=0; + + pAsm->CALLSP++; + pAsm->CALLSTACK[pAsm->CALLSP].FCSP_BeforeEntry = pAsm->FCSP; + pAsm->CALLSTACK[pAsm->CALLSP].plstCFInstructions_local + = &(pAsm->subs[pAsm->unSubArrayPointer].lstCFInstructions_local); + SetActiveCFlist(pAsm->pR700Shader, + pAsm->CALLSTACK[pAsm->CALLSP].plstCFInstructions_local); + + pAsm->unSubArrayPointer++; + + /* start sub */ + pAsm->alu_x_opcode = SQ_CF_INST_ALU; + + return GL_TRUE; +} + +GLboolean assemble_ENDSUB(r700_AssemblerBase *pAsm) +{ + pAsm->CALLSP--; + SetActiveCFlist(pAsm->pR700Shader, + pAsm->CALLSTACK[pAsm->CALLSP].plstCFInstructions_local); + + pAsm->alu_x_opcode = SQ_CF_INST_ALU; + + return GL_TRUE; +} + +GLboolean assemble_RET(r700_AssemblerBase *pAsm) +{ + if(pAsm->CALLSP > 0) + { /* in sub */ + unsigned int unFCSP; + for(unFCSP=pAsm->FCSP; unFCSP>pAsm->CALLSTACK[pAsm->CALLSP].FCSP_BeforeEntry; unFCSP--) + { + if(FC_LOOP == pAsm->fc_stack[unFCSP].type) + { + setRetInLoopFlag(pAsm, SQ_SEL_1); + breakLoopOnFlag(pAsm, unFCSP); + pAsm->unCFflags |= LOOPRET_FLAGS; + + return GL_TRUE; + } + } + } + + add_return_inst(pAsm); + + return GL_TRUE; +} + +GLboolean assemble_CAL(r700_AssemblerBase *pAsm, + GLint nILindex, + GLuint uiNumberInsts, + struct prog_instruction *pILInst) +{ + pAsm->alu_x_opcode = SQ_CF_INST_ALU; + + if(GL_FALSE == add_cf_instruction(pAsm) ) { return GL_FALSE; } - if( GL_FALSE == assemble_src(pAsm, 1, -1) ) + pAsm->cf_current_cf_clause_ptr->m_Word1.f.call_count = 1; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_CALL; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1; + + /* Put in caller */ + if( (pAsm->unCallerArrayPointer + 1) > pAsm->unCallerArraySize ) { - return GL_FALSE; + pAsm->callers = (CALLER_POINTER*)_mesa_realloc( (void *)pAsm->callers, + sizeof(CALLER_POINTER) * pAsm->unCallerArraySize, + sizeof(CALLER_POINTER) * (pAsm->unCallerArraySize + 10) ); + if(NULL == pAsm->callers) + { + return GL_FALSE; + } + pAsm->unCallerArraySize += 10; } - - swizzleagain_PVSSRC(&(pAsm->S[0].src), SQ_SEL_Y, SQ_SEL_Z, SQ_SEL_X, SQ_SEL_0); - swizzleagain_PVSSRC(&(pAsm->S[1].src), SQ_SEL_Z, SQ_SEL_X, SQ_SEL_Y, SQ_SEL_0); + + pAsm->callers[pAsm->unCallerArrayPointer].subIL_Offset = nILindex; + pAsm->callers[pAsm->unCallerArrayPointer].cf_ptr = pAsm->cf_current_cf_clause_ptr; - // result1 + (neg) result0 - setaddrmode_PVSSRC(&(pAsm->S[2].src),ADDR_ABSOLUTE); - pAsm->S[2].src.rtype = SRC_REG_TEMPORARY; - pAsm->S[2].src.reg = tmp; + pAsm->unCallerArrayPointer++; - neg_PVSSRC(&(pAsm->S[2].src)); - noswizzle_PVSSRC(&(pAsm->S[2].src)); + int j; + for(j=0; junSubArrayPointer; j++) + { + if(nILindex == pAsm->subs[j].subIL_Offset) + { /* compiled before */ + pAsm->callers[pAsm->unCallerArrayPointer - 1].subDescIndex = j; + return GL_TRUE; + } + } + + pAsm->callers[pAsm->unCallerArrayPointer - 1].subDescIndex = pAsm->unSubArrayPointer; + + return AssembleInstr(nILindex, uiNumberInsts, pILInst, pAsm); +} + +GLboolean setRetInLoopFlag(r700_AssemblerBase *pAsm, GLuint flagValue) +{ + GLfloat fLiteral[2] = {0.1, 0.0}; + + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + pAsm->D.dst.op3 = 0; + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = pAsm->flag_reg_index; + pAsm->D.dst.writex = 1; + pAsm->D.dst.writey = 0; + pAsm->D.dst.writez = 0; + pAsm->D.dst.writew = 0; + pAsm->D2.dst2.literal = 1; + pAsm->D2.dst2.SaturateMode = SATURATE_OFF; + pAsm->D.dst.predicated = 0; +#if 0 + pAsm->S[0].src.rtype = SRC_REC_LITERAL; + //pAsm->S[0].src.reg = 0; + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + noneg_PVSSRC(&(pAsm->S[0].src)); + pAsm->S[0].src.swizzlex = SQ_SEL_X; + pAsm->S[0].src.swizzley = SQ_SEL_Y; + pAsm->S[0].src.swizzlez = SQ_SEL_Z; + pAsm->S[0].src.swizzlew = SQ_SEL_W; + + if( GL_FALSE == next_ins_literal(pAsm, &(fLiteral[0])) ) + { + return GL_FALSE; + } +#else + pAsm->S[0].src.rtype = DST_REG_TEMPORARY; + pAsm->S[0].src.reg = 0; + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + noneg_PVSSRC(&(pAsm->S[0].src)); + pAsm->S[0].src.swizzlex = flagValue; + pAsm->S[0].src.swizzley = flagValue; + pAsm->S[0].src.swizzlez = flagValue; + pAsm->S[0].src.swizzlew = flagValue; - if( GL_FALSE == next_ins(pAsm) ) + if( GL_FALSE == next_ins2(pAsm) ) { return GL_FALSE; } +#endif + return GL_TRUE; +} - if(0xF != pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask) - { - if( GL_FALSE == assemble_dst(pAsm) ) - { - return GL_FALSE; - } +GLboolean testFlag(r700_AssemblerBase *pAsm) +{ + GLfloat fLiteral[2] = {0.1, 0.0}; - pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + //Test flag + GLuint tmp = gethelpr(pAsm); + pAsm->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; - // Use tmp as source - setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); - pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; - pAsm->S[0].src.reg = tmp; + pAsm->D.dst.opcode = SQ_OP2_INST_PRED_SETE; + pAsm->D.dst.math = 1; + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + pAsm->D.dst.writex = 1; + pAsm->D.dst.writey = 0; + pAsm->D.dst.writez = 0; + pAsm->D.dst.writew = 0; + pAsm->D2.dst2.literal = 1; + pAsm->D2.dst2.SaturateMode = SATURATE_OFF; + pAsm->D.dst.predicated = 1; - noneg_PVSSRC(&(pAsm->S[0].src)); - noswizzle_PVSSRC(&(pAsm->S[0].src)); + pAsm->S[0].src.rtype = DST_REG_TEMPORARY; + pAsm->S[0].src.reg = pAsm->flag_reg_index; + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + noneg_PVSSRC(&(pAsm->S[0].src)); + pAsm->S[0].src.swizzlex = SQ_SEL_X; + pAsm->S[0].src.swizzley = SQ_SEL_Y; + pAsm->S[0].src.swizzlez = SQ_SEL_Z; + pAsm->S[0].src.swizzlew = SQ_SEL_W; +#if 0 + pAsm->S[1].src.rtype = SRC_REC_LITERAL; + //pAsm->S[1].src.reg = 0; + setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); + noneg_PVSSRC(&(pAsm->S[1].src)); + pAsm->S[1].src.swizzlex = SQ_SEL_X; + pAsm->S[1].src.swizzley = SQ_SEL_Y; + pAsm->S[1].src.swizzlez = SQ_SEL_Z; + pAsm->S[1].src.swizzlew = SQ_SEL_W; - if( GL_FALSE == next_ins(pAsm) ) - { - return GL_FALSE; - } + if( GL_FALSE == next_ins_literal(pAsm, &(fLiteral[0])) ) + { + return GL_FALSE; + } +#else + pAsm->S[1].src.rtype = DST_REG_TEMPORARY; + pAsm->S[1].src.reg = 0; + setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); + noneg_PVSSRC(&(pAsm->S[1].src)); + pAsm->S[1].src.swizzlex = SQ_SEL_1; + pAsm->S[1].src.swizzley = SQ_SEL_1; + pAsm->S[1].src.swizzlez = SQ_SEL_1; + pAsm->S[1].src.swizzlew = SQ_SEL_1; + + if( GL_FALSE == next_ins2(pAsm) ) + { + return GL_FALSE; } +#endif return GL_TRUE; } -GLboolean assemble_EXPORT(r700_AssemblerBase *pAsm) +GLboolean returnOnFlag(r700_AssemblerBase *pAsm) { - return GL_TRUE; -} + testFlag(pAsm); + jumpToOffest(pAsm, 1, 4); + setRetInLoopFlag(pAsm, SQ_SEL_0); + pops(pAsm, 1); + add_return_inst(pAsm); -GLboolean assemble_IF(r700_AssemblerBase *pAsm) -{ return GL_TRUE; } -GLboolean assemble_ENDIF(r700_AssemblerBase *pAsm) +GLboolean breakLoopOnFlag(r700_AssemblerBase *pAsm, GLuint unFCSP) { + testFlag(pAsm); + + //break + if(GL_FALSE == add_cf_instruction(pAsm) ) + { + return GL_FALSE; + } + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 1; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_const = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cond = SQ_CF_COND_ACTIVE; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.end_of_program = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.valid_pixel_mode = 0x0; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.cf_inst = SQ_CF_INST_LOOP_BREAK; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.whole_quad_mode = 0x0; + + pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1; + + pAsm->fc_stack[unFCSP].mid = (R700ControlFlowGenericClause **)_mesa_realloc( + (void *)pAsm->fc_stack[unFCSP].mid, + sizeof(R700ControlFlowGenericClause *) * pAsm->fc_stack[unFCSP].unNumMid, + sizeof(R700ControlFlowGenericClause *) * (pAsm->fc_stack[unFCSP].unNumMid + 1) ); + pAsm->fc_stack[unFCSP].mid[pAsm->fc_stack[unFCSP].unNumMid] = pAsm->cf_current_cf_clause_ptr; + pAsm->fc_stack[unFCSP].unNumMid++; + + pops(pAsm, 1); + return GL_TRUE; } -GLboolean AssembleInstr(GLuint uiNumberInsts, +GLboolean AssembleInstr(GLuint uiFirstInst, + GLuint uiNumberInsts, struct prog_instruction *pILInst, r700_AssemblerBase *pR700AsmCode) { GLuint i; pR700AsmCode->pILInst = pILInst; - for(i=0; iuiCurInst = i; +#ifndef USE_CF_FOR_CONTINUE_BREAK + if(OPCODE_BRK == pILInst[i+1].Opcode) + { + switch(pILInst[i].Opcode) + { + case OPCODE_SLE: + pILInst[i].Opcode = OPCODE_SGT; + break; + case OPCODE_SLT: + pILInst[i].Opcode = OPCODE_SGE; + break; + case OPCODE_SGE: + pILInst[i].Opcode = OPCODE_SLT; + break; + case OPCODE_SGT: + pILInst[i].Opcode = OPCODE_SLE; + break; + case OPCODE_SEQ: + pILInst[i].Opcode = OPCODE_SNE; + break; + case OPCODE_SNE: + pILInst[i].Opcode = OPCODE_SEQ; + break; + default: + break; + } + } +#endif + switch (pILInst[i].Opcode) { case OPCODE_ABS: @@ -4337,101 +5749,383 @@ GLboolean AssembleInstr(GLuint uiNumberInsts, return GL_FALSE; break; - case OPCODE_EX2: - if ( GL_FALSE == assemble_EX2(pR700AsmCode) ) - return GL_FALSE; - break; - case OPCODE_EXP: - if ( GL_FALSE == assemble_EXP(pR700AsmCode) ) - return GL_FALSE; + case OPCODE_EX2: + if ( GL_FALSE == assemble_EX2(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_EXP: + if ( GL_FALSE == assemble_EXP(pR700AsmCode) ) + return GL_FALSE; + break; + + case OPCODE_FLR: + if ( GL_FALSE == assemble_FLR(pR700AsmCode) ) + return GL_FALSE; + break; + //case OP_FLR_INT: + // if ( GL_FALSE == assemble_FLR_INT() ) + // return GL_FALSE; + // break; + + case OPCODE_FRC: + if ( GL_FALSE == assemble_FRC(pR700AsmCode) ) + return GL_FALSE; + break; + + case OPCODE_KIL: + if ( GL_FALSE == assemble_KIL(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_LG2: + if ( GL_FALSE == assemble_LG2(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_LIT: + if ( GL_FALSE == assemble_LIT(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_LRP: + if ( GL_FALSE == assemble_LRP(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_LOG: + if ( GL_FALSE == assemble_LOG(pR700AsmCode) ) + return GL_FALSE; + break; + + case OPCODE_MAD: + if ( GL_FALSE == assemble_MAD(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_MAX: + if ( GL_FALSE == assemble_MAX(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_MIN: + if ( GL_FALSE == assemble_MIN(pR700AsmCode) ) + return GL_FALSE; + break; + + case OPCODE_MOV: + if ( GL_FALSE == assemble_MOV(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_MUL: + if ( GL_FALSE == assemble_MUL(pR700AsmCode) ) + return GL_FALSE; + break; + + case OPCODE_POW: + if ( GL_FALSE == assemble_POW(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_RCP: + if ( GL_FALSE == assemble_RCP(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_RSQ: + if ( GL_FALSE == assemble_RSQ(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_SIN: + if ( GL_FALSE == assemble_SIN(pR700AsmCode) ) + return GL_FALSE; + break; + case OPCODE_SCS: + if ( GL_FALSE == assemble_SCS(pR700AsmCode) ) + return GL_FALSE; + break; + + case OPCODE_SEQ: + if(OPCODE_IF == pILInst[i+1].Opcode) + { + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; + if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETE) ) + { + return GL_FALSE; + } + } + else if(OPCODE_BRK == pILInst[i+1].Opcode) + { +#ifdef USE_CF_FOR_CONTINUE_BREAK + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; +#else + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_BREAK; +#endif + if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETE) ) + { + return GL_FALSE; + } + } + else if(OPCODE_CONT == pILInst[i+1].Opcode) + { +#ifdef USE_CF_FOR_CONTINUE_BREAK + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; +#else + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_CONTINUE; +#endif + if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETE) ) + { + return GL_FALSE; + } + } + else + { + if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETE) ) + { + return GL_FALSE; + } + } + break; + + case OPCODE_SGT: + if(OPCODE_IF == pILInst[i+1].Opcode) + { + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; + if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGT) ) + { + return GL_FALSE; + } + } + else if(OPCODE_BRK == pILInst[i+1].Opcode) + { +#ifdef USE_CF_FOR_CONTINUE_BREAK + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; +#else + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_BREAK; +#endif + if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGT) ) + { + return GL_FALSE; + } + } + else if(OPCODE_CONT == pILInst[i+1].Opcode) + { +#ifdef USE_CF_FOR_CONTINUE_BREAK + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; +#else + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_CONTINUE; +#endif + + if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGT) ) + { + return GL_FALSE; + } + } + else + { + if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETGT) ) + { + return GL_FALSE; + } + } + break; + + case OPCODE_SGE: + if(OPCODE_IF == pILInst[i+1].Opcode) + { + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; + if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGE) ) + { + return GL_FALSE; + } + } + else if(OPCODE_BRK == pILInst[i+1].Opcode) + { +#ifdef USE_CF_FOR_CONTINUE_BREAK + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; +#else + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_BREAK; +#endif + if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGE) ) + { + return GL_FALSE; + } + } + else if(OPCODE_CONT == pILInst[i+1].Opcode) + { +#ifdef USE_CF_FOR_CONTINUE_BREAK + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; +#else + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_CONTINUE; +#endif + + if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGE) ) + { + return GL_FALSE; + } + } + else + { + if ( GL_FALSE == assemble_SGE(pR700AsmCode) ) + { + return GL_FALSE; + } + } + break; + + /* NO LT, LE, TODO : use GE => LE, GT => LT : reverse 2 src order would be simpliest. Or use SQ_CF_COND_FALSE for SQ_CF_COND_ACTIVE.*/ + case OPCODE_SLT: + { + struct prog_src_register SrcRegSave[2]; + SrcRegSave[0] = pILInst[i].SrcReg[0]; + SrcRegSave[1] = pILInst[i].SrcReg[1]; + pILInst[i].SrcReg[0] = SrcRegSave[1]; + pILInst[i].SrcReg[1] = SrcRegSave[0]; + if(OPCODE_IF == pILInst[i+1].Opcode) + { + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; + if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGT) ) + { + pILInst[i].SrcReg[0] = SrcRegSave[0]; + pILInst[i].SrcReg[1] = SrcRegSave[1]; + return GL_FALSE; + } + } + else if(OPCODE_BRK == pILInst[i+1].Opcode) + { +#ifdef USE_CF_FOR_CONTINUE_BREAK + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; +#else + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_BREAK; +#endif + if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGT) ) + { + pILInst[i].SrcReg[0] = SrcRegSave[0]; + pILInst[i].SrcReg[1] = SrcRegSave[1]; + return GL_FALSE; + } + } + else if(OPCODE_CONT == pILInst[i+1].Opcode) + { +#ifdef USE_CF_FOR_CONTINUE_BREAK + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; +#else + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_CONTINUE; +#endif + + if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGT) ) + { + pILInst[i].SrcReg[0] = SrcRegSave[0]; + pILInst[i].SrcReg[1] = SrcRegSave[1]; + return GL_FALSE; + } + } + else + { + if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETGT) ) + { + pILInst[i].SrcReg[0] = SrcRegSave[0]; + pILInst[i].SrcReg[1] = SrcRegSave[1]; + return GL_FALSE; + } + } + pILInst[i].SrcReg[0] = SrcRegSave[0]; + pILInst[i].SrcReg[1] = SrcRegSave[1]; + } break; - case OPCODE_FLR: - if ( GL_FALSE == assemble_FLR(pR700AsmCode) ) - return GL_FALSE; - break; - //case OP_FLR_INT: - // if ( GL_FALSE == assemble_FLR_INT() ) - // return GL_FALSE; - // break; - - case OPCODE_FRC: - if ( GL_FALSE == assemble_FRC(pR700AsmCode) ) - return GL_FALSE; - break; + case OPCODE_SLE: + { + struct prog_src_register SrcRegSave[2]; + SrcRegSave[0] = pILInst[i].SrcReg[0]; + SrcRegSave[1] = pILInst[i].SrcReg[1]; + pILInst[i].SrcReg[0] = SrcRegSave[1]; + pILInst[i].SrcReg[1] = SrcRegSave[0]; + if(OPCODE_IF == pILInst[i+1].Opcode) + { + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; + if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGE) ) + { + pILInst[i].SrcReg[0] = SrcRegSave[0]; + pILInst[i].SrcReg[1] = SrcRegSave[1]; + return GL_FALSE; + } + } + else if(OPCODE_BRK == pILInst[i+1].Opcode) + { +#ifdef USE_CF_FOR_CONTINUE_BREAK + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; +#else + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_BREAK; +#endif + if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGE) ) + { + pILInst[i].SrcReg[0] = SrcRegSave[0]; + pILInst[i].SrcReg[1] = SrcRegSave[1]; + return GL_FALSE; + } + } + else if(OPCODE_CONT == pILInst[i+1].Opcode) + { +#ifdef USE_CF_FOR_CONTINUE_BREAK + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; +#else + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_CONTINUE; +#endif - case OPCODE_KIL: - if ( GL_FALSE == assemble_KIL(pR700AsmCode) ) - return GL_FALSE; - break; - case OPCODE_LG2: - if ( GL_FALSE == assemble_LG2(pR700AsmCode) ) - return GL_FALSE; - break; - case OPCODE_LIT: - if ( GL_FALSE == assemble_LIT(pR700AsmCode) ) - return GL_FALSE; - break; - case OPCODE_LRP: - if ( GL_FALSE == assemble_LRP(pR700AsmCode) ) - return GL_FALSE; - break; - case OPCODE_LOG: - if ( GL_FALSE == assemble_LOG(pR700AsmCode) ) - return GL_FALSE; + if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGE) ) + { + pILInst[i].SrcReg[0] = SrcRegSave[0]; + pILInst[i].SrcReg[1] = SrcRegSave[1]; + return GL_FALSE; + } + } + else + { + if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETGE) ) + { + pILInst[i].SrcReg[0] = SrcRegSave[0]; + pILInst[i].SrcReg[1] = SrcRegSave[1]; + return GL_FALSE; + } + } + pILInst[i].SrcReg[0] = SrcRegSave[0]; + pILInst[i].SrcReg[1] = SrcRegSave[1]; + } break; - case OPCODE_MAD: - if ( GL_FALSE == assemble_MAD(pR700AsmCode) ) - return GL_FALSE; - break; - case OPCODE_MAX: - if ( GL_FALSE == assemble_MAX(pR700AsmCode) ) - return GL_FALSE; - break; - case OPCODE_MIN: - if ( GL_FALSE == assemble_MIN(pR700AsmCode) ) - return GL_FALSE; - break; - - case OPCODE_MOV: - if ( GL_FALSE == assemble_MOV(pR700AsmCode) ) - return GL_FALSE; - break; - case OPCODE_MUL: - if ( GL_FALSE == assemble_MUL(pR700AsmCode) ) - return GL_FALSE; - break; - - case OPCODE_POW: - if ( GL_FALSE == assemble_POW(pR700AsmCode) ) - return GL_FALSE; - break; - case OPCODE_RCP: - if ( GL_FALSE == assemble_RCP(pR700AsmCode) ) - return GL_FALSE; - break; - case OPCODE_RSQ: - if ( GL_FALSE == assemble_RSQ(pR700AsmCode) ) - return GL_FALSE; - break; - case OPCODE_SIN: - if ( GL_FALSE == assemble_SIN(pR700AsmCode) ) - return GL_FALSE; - break; - case OPCODE_SCS: - if ( GL_FALSE == assemble_SCS(pR700AsmCode) ) - return GL_FALSE; - break; - - case OPCODE_SGE: - if ( GL_FALSE == assemble_SGE(pR700AsmCode) ) - return GL_FALSE; - break; - case OPCODE_SLT: - if ( GL_FALSE == assemble_SLT(pR700AsmCode) ) - return GL_FALSE; - break; + case OPCODE_SNE: + if(OPCODE_IF == pILInst[i+1].Opcode) + { + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; + if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETNE) ) + { + return GL_FALSE; + } + } + else if(OPCODE_BRK == pILInst[i+1].Opcode) + { +#ifdef USE_CF_FOR_CONTINUE_BREAK + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; +#else + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_BREAK; +#endif + if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETNE) ) + { + return GL_FALSE; + } + } + else if(OPCODE_CONT == pILInst[i+1].Opcode) + { +#ifdef USE_CF_FOR_CONTINUE_BREAK + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; +#else + pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_CONTINUE; +#endif + if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETNE) ) + { + return GL_FALSE; + } + } + else + { + if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETNE) ) + { + return GL_FALSE; + } + } + break; //case OP_STP: // if ( GL_FALSE == assemble_STP(pR700AsmCode) ) @@ -4471,24 +6165,91 @@ GLboolean AssembleInstr(GLuint uiNumberInsts, break; case OPCODE_IF : - if ( GL_FALSE == assemble_IF(pR700AsmCode) ) - return GL_FALSE; + { + GLboolean bHasElse = GL_FALSE; + + if(pILInst[pILInst[i].BranchTarget - 1].Opcode == OPCODE_ELSE) + { + bHasElse = GL_TRUE; + } + + if ( GL_FALSE == assemble_IF(pR700AsmCode, bHasElse) ) + { + return GL_FALSE; + } + } break; + case OPCODE_ELSE : - radeon_error("Not yet implemented instruction OPCODE_ELSE \n"); - //if ( GL_FALSE == assemble_BAD("ELSE") ) + if ( GL_FALSE == assemble_ELSE(pR700AsmCode) ) return GL_FALSE; break; + case OPCODE_ENDIF: if ( GL_FALSE == assemble_ENDIF(pR700AsmCode) ) return GL_FALSE; break; + case OPCODE_BGNLOOP: + if( GL_FALSE == assemble_BGNLOOP(pR700AsmCode) ) + { + return GL_FALSE; + } + break; + + case OPCODE_BRK: + if( GL_FALSE == assemble_BRK(pR700AsmCode) ) + { + return GL_FALSE; + } + break; + + case OPCODE_CONT: + if( GL_FALSE == assemble_CONT(pR700AsmCode) ) + { + return GL_FALSE; + } + break; + + case OPCODE_ENDLOOP: + if( GL_FALSE == assemble_ENDLOOP(pR700AsmCode) ) + { + return GL_FALSE; + } + break; + + case OPCODE_BGNSUB: + if( GL_FALSE == assemble_BGNSUB(pR700AsmCode, i) ) + { + return GL_FALSE; + } + break; + + case OPCODE_RET: + if( GL_FALSE == assemble_RET(pR700AsmCode) ) + { + return GL_FALSE; + } + break; + + case OPCODE_CAL: + if( GL_FALSE == assemble_CAL(pR700AsmCode, + pILInst[i].BranchTarget, + uiNumberInsts, + pILInst) ) + { + return GL_FALSE; + } + break; + //case OPCODE_EXPORT: // if ( GL_FALSE == assemble_EXPORT() ) // return GL_FALSE; // break; + case OPCODE_ENDSUB: + return assemble_ENDSUB(pR700AsmCode); + case OPCODE_END: //pR700AsmCode->uiCurInst = i; //This is to remaind that if in later exoort there is depth/stencil @@ -4505,6 +6266,116 @@ GLboolean AssembleInstr(GLuint uiNumberInsts, return GL_TRUE; } +GLboolean InitShaderProgram(r700_AssemblerBase * pAsm) +{ + setRetInLoopFlag(pAsm, SQ_SEL_0); + return GL_TRUE; +} + +GLboolean RelocProgram(r700_AssemblerBase * pAsm) +{ + GLuint i; + GLuint unCFoffset; + TypedShaderList * plstCFmain; + TypedShaderList * plstCFsub; + + R700ShaderInstruction * pInst; + R700ControlFlowGenericClause * pCFInst; + + if(0 == pAsm->unSubArrayPointer) + { + return GL_TRUE; + } + + plstCFmain = pAsm->CALLSTACK[0].plstCFInstructions_local; + unCFoffset = plstCFmain->uNumOfNode; + + /* Reloc subs */ + for(i=0; iunSubArrayPointer; i++) + { + pAsm->subs[i].unCFoffset = unCFoffset; + plstCFsub = &(pAsm->subs[i].lstCFInstructions_local); + + pInst = plstCFsub->pHead; + + /* reloc instructions */ + while(pInst) + { + if(SIT_CF_GENERIC == pInst->m_ShaderInstType) + { + pCFInst = (R700ControlFlowGenericClause *)pInst; + + switch (pCFInst->m_Word1.f.cf_inst) + { + case SQ_CF_INST_POP: + case SQ_CF_INST_JUMP: + case SQ_CF_INST_ELSE: + case SQ_CF_INST_LOOP_END: + case SQ_CF_INST_LOOP_START: + case SQ_CF_INST_LOOP_START_NO_AL: + case SQ_CF_INST_LOOP_CONTINUE: + case SQ_CF_INST_LOOP_BREAK: + pCFInst->m_Word0.f.addr += unCFoffset; + break; + default: + break; + } + } + + pInst->m_uIndex += unCFoffset; + + pInst = pInst->pNextInst; + }; + + /* Put sub into main */ + plstCFmain->pTail->pNextInst = plstCFsub->pHead; + plstCFmain->pTail = plstCFsub->pTail; + plstCFmain->uNumOfNode += plstCFsub->uNumOfNode; + + unCFoffset += plstCFsub->uNumOfNode; + } + + /* reloc callers */ + for(i=0; iunCallerArrayPointer; i++) + { + pAsm->callers[i].cf_ptr->m_Word0.f.addr + = pAsm->subs[pAsm->callers[i].subDescIndex].unCFoffset; + } + + /* remove flags init if they are not used */ + if((pAsm->unCFflags & HAS_LOOPRET) == 0) + { + R700ControlFlowALUClause * pCF_ALU; + pInst = plstCFmain->pHead; + while(pInst) + { + if(SIT_CF_ALU == pInst->m_ShaderInstType) + { + pCF_ALU = (R700ControlFlowALUClause *)pInst; + if(1 == pCF_ALU->m_Word1.f.count) + { + pCF_ALU->m_Word1.f.cf_inst = SQ_CF_INST_NOP; + } + else + { + R700ALUInstruction * pALU = pCF_ALU->m_pLinkedALUInstruction; + + pALU->m_pLinkedALUClause = NULL; + pALU = (R700ALUInstruction *)(pALU->pNextInst); + pALU->m_pLinkedALUClause = pCF_ALU; + pCF_ALU->m_pLinkedALUInstruction = pALU; + + pCF_ALU->m_Word1.f.count--; + } + break; + } + pInst = pInst->pNextInst; + }; + } + + return GL_TRUE; +} + GLboolean Process_Export(r700_AssemblerBase* pAsm, GLuint type, GLuint export_starting_index, @@ -4800,6 +6671,25 @@ GLboolean Process_Vertex_Exports(r700_AssemblerBase *pR700AsmCode, } } + for(i=VERT_RESULT_VAR0; iucVP_OutputMap[i], + GL_FALSE) ) + { + return GL_FALSE; + } + + export_starting_index++; + } + } + // At least one param should be exported if (export_count) { @@ -4833,6 +6723,16 @@ GLboolean Clean_Up_Assembler(r700_AssemblerBase *pR700AsmCode) { FREE(pR700AsmCode->pucOutMask); FREE(pR700AsmCode->pInstDeps); + + if(NULL != pR700AsmCode->subs) + { + FREE(pR700AsmCode->subs); + } + if(NULL != pR700AsmCode->callers) + { + FREE(pR700AsmCode->callers); + } + return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index c66db502a1..85d32212c0 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -72,7 +72,8 @@ typedef enum SrcRegisterType SRC_REG_INPUT = 1, SRC_REG_CONSTANT = 2, SRC_REG_ALT_TEMPORARY = 3, - NUMBER_OF_SRC_REG_TYPE = 4 + SRC_REC_LITERAL = 4, + NUMBER_OF_SRC_REG_TYPE = 5 } SrcRegisterType; typedef enum DstRegisterType @@ -111,6 +112,12 @@ typedef struct PVSDSTtag BITS addrmode1:1; //32 } PVSDST; +typedef struct PVSINSTtag +{ + BITS literal :2; + BITS SaturateMode :2; +} PVSINST; + typedef struct PVSSRCtag { BITS rtype:4; @@ -148,6 +155,7 @@ typedef union PVSDWORDtag { BITS bits; PVSDST dst; + PVSINST dst2; PVSSRC src; PVSMATH math; float f; @@ -263,14 +271,15 @@ enum typedef struct FC_LEVEL { - unsigned int first; ///< first fc instruction on level (if, rep, loop) - unsigned int* mid; ///< middle instructions - else or all breaks on this level - unsigned int midLen; - unsigned int type; - unsigned int cond; - unsigned int inv; - unsigned int bpush; ///< 1 if first instruction does branch stack push - int id; ///< id of bool or int variable + R700ControlFlowGenericClause * first; + R700ControlFlowGenericClause ** mid; + unsigned int unNumMid; + unsigned int midLen; + unsigned int type; + unsigned int cond; + unsigned int inv; + unsigned int bpush; ///< 1 if first instruction does branch stack push + int id; ///< id of bool or int variable } FC_LEVEL; typedef struct VTX_FETCH_METHOD @@ -279,6 +288,28 @@ typedef struct VTX_FETCH_METHOD GLuint mega_fetch_remainder; } VTX_FETCH_METHOD; +typedef struct SUB_OFFSET +{ + GLint subIL_Offset; + GLuint unCFoffset; + TypedShaderList lstCFInstructions_local; +} SUB_OFFSET; + +typedef struct CALLER_POINTER +{ + GLint subIL_Offset; + GLint subDescIndex; + R700ControlFlowGenericClause* cf_ptr; +} CALLER_POINTER; + +#define SQ_MAX_CALL_DEPTH 0x00000020 + +typedef struct CALL_LEVEL +{ + unsigned int FCSP_BeforeEntry; + TypedShaderList * plstCFInstructions_local; +} CALL_LEVEL; + typedef struct r700_AssemblerBase { R700ControlFlowSXClause* cf_last_export_ptr; @@ -294,11 +325,14 @@ typedef struct r700_AssemblerBase // No clause has been created yet CF_CLAUSE_TYPE cf_current_clause_type; + BITS alu_x_opcode; + GLuint number_of_exports; GLuint number_of_colorandz_exports; GLuint number_of_export_opcodes; PVSDWORD D; + PVSDWORD D2; PVSDWORD S[3]; unsigned int uLastPosUpdate; @@ -310,6 +344,8 @@ typedef struct r700_AssemblerBase unsigned int number_used_registers; unsigned int uUsedConsts; + unsigned int flag_reg_index; + // Fragment programs unsigned int uiFP_AttributeMap[FRAG_ATTRIB_MAX]; unsigned int uiFP_OutputMap[FRAG_RESULT_MAX]; @@ -378,6 +414,18 @@ typedef struct r700_AssemblerBase GLboolean is_tex; /* we inserted helper intructions and need barrier on next TEX ins */ GLboolean need_tex_barrier; + + SUB_OFFSET * subs; + GLuint unSubArraySize; + GLuint unSubArrayPointer; + CALLER_POINTER * callers; + GLuint unCallerArraySize; + GLuint unCallerArrayPointer; + unsigned int CALLSP; + CALL_LEVEL CALLSTACK[SQ_MAX_CALL_DEPTH]; + + GLuint unCFflags; + } r700_AssemblerBase; //Internal use @@ -446,6 +494,10 @@ GLboolean assemble_alu_src(R700ALUInstruction* alu_instruction_ptr, GLboolean add_alu_instruction(r700_AssemblerBase* pAsm, R700ALUInstruction* alu_instruction_ptr, GLuint contiguous_slots_needed); + +GLboolean add_cf_instruction(r700_AssemblerBase* pAsm); +void add_return_inst(r700_AssemblerBase *pAsm); + void get_src_properties(R700ALUInstruction* alu_instruction_ptr, int source_index, BITS* psrc_sel, @@ -467,6 +519,21 @@ GLboolean check_vector(r700_AssemblerBase* pAsm, R700ALUInstruction* alu_instruction_ptr); GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm); GLboolean next_ins(r700_AssemblerBase *pAsm); + +GLboolean next_ins2(r700_AssemblerBase *pAsm); +GLboolean assemble_alu_instruction2(r700_AssemblerBase *pAsm); + +/* TODO : merge next_ins/2/literal, assemble_alu_instruction/2/literal */ +GLboolean next_ins_literal(r700_AssemblerBase *pAsm, GLfloat * pLiteral); +GLboolean assemble_alu_instruction_literal(r700_AssemblerBase *pAsm, GLfloat * pLiteral); + +GLboolean pops(r700_AssemblerBase *pAsm, GLuint pops); +GLboolean jumpToOffest(r700_AssemblerBase *pAsm, GLuint pops, GLint offset); +GLboolean setRetInLoopFlag(r700_AssemblerBase *pAsm, GLuint flagValue); +GLboolean testFlag(r700_AssemblerBase *pAsm); +GLboolean breakLoopOnFlag(r700_AssemblerBase *pAsm, GLuint unFCSP); +GLboolean returnOnFlag(r700_AssemblerBase *pAsm); + GLboolean assemble_math_function(r700_AssemblerBase* pAsm, BITS opcode); GLboolean assemble_ABS(r700_AssemblerBase *pAsm); GLboolean assemble_ADD(r700_AssemblerBase *pAsm); @@ -497,14 +564,32 @@ GLboolean assemble_RSQ(r700_AssemblerBase *pAsm); GLboolean assemble_SIN(r700_AssemblerBase *pAsm); GLboolean assemble_SCS(r700_AssemblerBase *pAsm); GLboolean assemble_SGE(r700_AssemblerBase *pAsm); + +GLboolean assemble_LOGIC(r700_AssemblerBase *pAsm, BITS opcode); +GLboolean assemble_LOGIC_PRED(r700_AssemblerBase *pAsm, BITS opcode); + GLboolean assemble_SLT(r700_AssemblerBase *pAsm); GLboolean assemble_STP(r700_AssemblerBase *pAsm); GLboolean assemble_TEX(r700_AssemblerBase *pAsm); GLboolean assemble_XPD(r700_AssemblerBase *pAsm); GLboolean assemble_EXPORT(r700_AssemblerBase *pAsm); -GLboolean assemble_IF(r700_AssemblerBase *pAsm); +GLboolean assemble_IF(r700_AssemblerBase *pAsm, GLboolean bHasElse); +GLboolean assemble_ELSE(r700_AssemblerBase *pAsm); GLboolean assemble_ENDIF(r700_AssemblerBase *pAsm); +GLboolean assemble_BGNLOOP(r700_AssemblerBase *pAsm); +GLboolean assemble_BRK(r700_AssemblerBase *pAsm); +GLboolean assemble_COND(r700_AssemblerBase *pAsm); +GLboolean assemble_ENDLOOP(r700_AssemblerBase *pAsm); + +GLboolean assemble_BGNSUB(r700_AssemblerBase *pAsm, GLint nILindex); +GLboolean assemble_ENDSUB(r700_AssemblerBase *pAsm); +GLboolean assemble_RET(r700_AssemblerBase *pAsm); +GLboolean assemble_CAL(r700_AssemblerBase *pAsm, + GLint nILindex, + GLuint uiNumberInsts, + struct prog_instruction *pILInst); + GLboolean Process_Export(r700_AssemblerBase* pAsm, GLuint type, GLuint export_starting_index, @@ -516,12 +601,16 @@ GLboolean Move_Depth_Exports_To_Correct_Channels(r700_AssemblerBase *pAsm, //Interface -GLboolean AssembleInstr(GLuint uiNumberInsts, +GLboolean AssembleInstr(GLuint uiFirstInst, + GLuint uiNumberInsts, struct prog_instruction *pILInst, r700_AssemblerBase *pR700AsmCode); GLboolean Process_Fragment_Exports(r700_AssemblerBase *pR700AsmCode, GLbitfield OutputsWritten); GLboolean Process_Vertex_Exports(r700_AssemblerBase *pR700AsmCode, GLbitfield OutputsWritten); +GLboolean RelocProgram(r700_AssemblerBase * pAsm); +GLboolean InitShaderProgram(r700_AssemblerBase * pAsm); + int Init_r700_AssemblerBase(SHADER_PIPE_TYPE spt, r700_AssemblerBase* pAsm, R700_Shader* pShader); GLboolean Clean_Up_Assembler(r700_AssemblerBase *pR700AsmCode); diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index ec76fbcb6d..197916ac0d 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -442,68 +442,77 @@ static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom * static void r700SendPSState(GLcontext *ctx, struct radeon_state_atom *atom) { - context_t *context = R700_CONTEXT(ctx); - R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); - struct radeon_bo * pbo; - BATCH_LOCALS(&context->radeon); - radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + struct radeon_bo * pbo; + BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); - pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context)); + pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context)); - if (!pbo) - return; + if (!pbo) + return; - r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); + r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); - BEGIN_BATCH_NO_AUTOSTATE(3 + 2); - R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1); - R600_OUT_BATCH(r700->ps.SQ_PGM_START_PS.u32All); - R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All, - pbo, - r700->ps.SQ_PGM_START_PS.u32All, - RADEON_GEM_DOMAIN_GTT, 0, 0); - END_BATCH(); + BEGIN_BATCH_NO_AUTOSTATE(3 + 2); + R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1); + R600_OUT_BATCH(r700->ps.SQ_PGM_START_PS.u32All); + R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All, + pbo, + r700->ps.SQ_PGM_START_PS.u32All, + RADEON_GEM_DOMAIN_GTT, 0, 0); + END_BATCH(); - BEGIN_BATCH_NO_AUTOSTATE(9); - R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, r700->ps.SQ_PGM_RESOURCES_PS.u32All); - R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, r700->ps.SQ_PGM_EXPORTS_PS.u32All); - R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, r700->ps.SQ_PGM_CF_OFFSET_PS.u32All); - END_BATCH(); + BEGIN_BATCH_NO_AUTOSTATE(9); + R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, r700->ps.SQ_PGM_RESOURCES_PS.u32All); + R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, r700->ps.SQ_PGM_EXPORTS_PS.u32All); + R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, r700->ps.SQ_PGM_CF_OFFSET_PS.u32All); + END_BATCH(); - COMMIT_BATCH(); + BEGIN_BATCH_NO_AUTOSTATE(3); + R600_OUT_BATCH_REGVAL(SQ_LOOP_CONST_0, 0x01000FFF); + END_BATCH(); + + COMMIT_BATCH(); } static void r700SendVSState(GLcontext *ctx, struct radeon_state_atom *atom) { - context_t *context = R700_CONTEXT(ctx); - R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); - struct radeon_bo * pbo; - BATCH_LOCALS(&context->radeon); - radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); + context_t *context = R700_CONTEXT(ctx); + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + struct radeon_bo * pbo; + BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); - pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); + pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); - if (!pbo) - return; + if (!pbo) + return; - r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); + r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); - BEGIN_BATCH_NO_AUTOSTATE(3 + 2); - R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1); - R600_OUT_BATCH(r700->vs.SQ_PGM_START_VS.u32All); - R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All, - pbo, - r700->vs.SQ_PGM_START_VS.u32All, - RADEON_GEM_DOMAIN_GTT, 0, 0); - END_BATCH(); + BEGIN_BATCH_NO_AUTOSTATE(3 + 2); + R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1); + R600_OUT_BATCH(r700->vs.SQ_PGM_START_VS.u32All); + R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All, + pbo, + r700->vs.SQ_PGM_START_VS.u32All, + RADEON_GEM_DOMAIN_GTT, 0, 0); + END_BATCH(); - BEGIN_BATCH_NO_AUTOSTATE(6); - R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, r700->vs.SQ_PGM_RESOURCES_VS.u32All); - R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, r700->vs.SQ_PGM_CF_OFFSET_VS.u32All); - END_BATCH(); + BEGIN_BATCH_NO_AUTOSTATE(6); + R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, r700->vs.SQ_PGM_RESOURCES_VS.u32All); + R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, r700->vs.SQ_PGM_CF_OFFSET_VS.u32All); + END_BATCH(); - COMMIT_BATCH(); + BEGIN_BATCH_NO_AUTOSTATE(3); + R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + 32*4), 0x0100000F); + //R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + (SQ_LOOP_CONST_vs<2)), 0x0100000F); + END_BATCH(); + + COMMIT_BATCH(); } static void r700SendFSState(GLcontext *ctx, struct radeon_state_atom *atom) diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index ccafd433bf..21ac46e7b8 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -73,11 +73,11 @@ void Map_Fragment_Program(r700_AssemblerBase *pAsm, pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1] = pAsm->number_used_registers++; } - unBit = 1 << FRAG_ATTRIB_FOGC; - if(mesa_fp->Base.InputsRead & unBit) - { - pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC] = pAsm->number_used_registers++; - } + unBit = 1 << FRAG_ATTRIB_FOGC; + if(mesa_fp->Base.InputsRead & unBit) + { + pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC] = pAsm->number_used_registers++; + } for(i=0; i<8; i++) { @@ -88,6 +88,62 @@ void Map_Fragment_Program(r700_AssemblerBase *pAsm, } } +/* order has been taken care of */ +#if 1 + for(i=FRAG_ATTRIB_VAR0; iBase.InputsRead & unBit) + { + pAsm->uiFP_AttributeMap[i] = pAsm->number_used_registers++; + } + } +#else + if( (mesa_fp->Base.InputsRead >> FRAG_ATTRIB_VAR0) > 0 ) + { + struct r700_vertex_program_cont *vpc = + (struct r700_vertex_program_cont *)ctx->VertexProgram._Current; + struct gl_program_parameter_list * VsVarying = vpc->mesa_program.Base.Varying; + struct gl_program_parameter_list * PsVarying = mesa_fp->Base.Varying; + struct gl_program_parameter * pVsParam; + struct gl_program_parameter * pPsParam; + GLuint j, k; + GLuint unMaxVarying = 0; + + for(i=0; iNumParameters; i++) + { + pAsm->uiFP_AttributeMap[i + FRAG_ATTRIB_VAR0] = 0; + } + + for(i=FRAG_ATTRIB_VAR0; iBase.InputsRead & unBit) + { + j = i - FRAG_ATTRIB_VAR0; + pPsParam = PsVarying->Parameters + j; + + for(k=0; kNumParameters; k++) + { + pVsParam = VsVarying->Parameters + k; + + if( strcmp(pPsParam->Name, pVsParam->Name) == 0) + { + pAsm->uiFP_AttributeMap[i] = pAsm->number_used_registers + k; + if(k > unMaxVarying) + { + unMaxVarying = k; + } + break; + } + } + } + } + + pAsm->number_used_registers += unMaxVarying + 1; + } +#endif + /* Map temporary registers (GPRs) */ pAsm->starting_temp_register_number = pAsm->number_used_registers; @@ -127,6 +183,8 @@ void Map_Fragment_Program(r700_AssemblerBase *pAsm, pAsm->pucOutMask[ui] = 0x0; } + pAsm->flag_reg_index = pAsm->number_used_registers++; + pAsm->uFirstHelpReg = pAsm->number_used_registers; } @@ -247,8 +305,11 @@ GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp, { return GL_FALSE; } + + InitShaderProgram(&(fp->r700AsmCode)); - if( GL_FALSE == AssembleInstr(mesa_fp->Base.NumInstructions, + if( GL_FALSE == AssembleInstr(0, + mesa_fp->Base.NumInstructions, &(mesa_fp->Base.Instructions[0]), &(fp->r700AsmCode)) ) { @@ -260,6 +321,11 @@ GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp, return GL_FALSE; } + if( GL_FALSE == RelocProgram(&(fp->r700AsmCode)) ) + { + return GL_FALSE; + } + fp->r700Shader.nRegs = (fp->r700AsmCode.number_used_registers == 0) ? 0 : (fp->r700AsmCode.number_used_registers - 1); @@ -459,6 +525,22 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) } } + for(i=FRAG_ATTRIB_VAR0; iBase.InputsRead & unBit) + { + ui = pAsm->uiFP_AttributeMap[i]; + SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit); + SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui, + SEMANTIC_shift, SEMANTIC_mask); + if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit) + SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit); + else + CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit); + } + } + exportCount = (r700->ps.SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift); if (r700->CB_SHADER_CONTROL.u32All != ((1 << exportCount) - 1)) { diff --git a/src/mesa/drivers/dri/r600/r700_shader.c b/src/mesa/drivers/dri/r600/r700_shader.c index 955ea4e4e1..2eed1acc2f 100644 --- a/src/mesa/drivers/dri/r600/r700_shader.c +++ b/src/mesa/drivers/dri/r600/r700_shader.c @@ -159,13 +159,18 @@ void Init_R700_Shader(R700_Shader * pShader) pShader->lstVTXInstructions.uNumOfNode=0; } +void SetActiveCFlist(R700_Shader *pShader, TypedShaderList * plstCF) +{ + pShader->plstCFInstructions_active = plstCF; +} + void AddCFInstruction(R700_Shader *pShader, R700ControlFlowInstruction *pCFInst) { R700ControlFlowSXClause* pSXClause; R700ControlFlowSMXClause* pSMXClause; - pCFInst->m_uIndex = pShader->lstCFInstructions.uNumOfNode; - AddInstToList(&(pShader->lstCFInstructions), + pCFInst->m_uIndex = pShader->plstCFInstructions_active->uNumOfNode; + AddInstToList(pShader->plstCFInstructions_active, (R700ShaderInstruction*)pCFInst); pShader->uShaderBinaryDWORDSize += GetInstructionSize(pCFInst->m_ShaderInstType); diff --git a/src/mesa/drivers/dri/r600/r700_shader.h b/src/mesa/drivers/dri/r600/r700_shader.h index c6a058617e..0599ffd901 100644 --- a/src/mesa/drivers/dri/r600/r700_shader.h +++ b/src/mesa/drivers/dri/r600/r700_shader.h @@ -109,6 +109,7 @@ typedef struct R700_Shader GLuint uStackSize; GLuint uMaxCallDepth; + TypedShaderList * plstCFInstructions_active; TypedShaderList lstCFInstructions; TypedShaderList lstALUInstructions; TypedShaderList lstTEXInstructions; @@ -132,13 +133,13 @@ void TakeInstOutFromList(TypedShaderList * plstCFInstructions, R700ShaderInstruc void ResolveLinks(R700_Shader *pShader); void Assemble(R700_Shader *pShader); - //Interface void Init_R700_Shader(R700_Shader * pShader); void AddCFInstruction(R700_Shader *pShader, R700ControlFlowInstruction *pCFInst); void AddVTXInstruction(R700_Shader *pShader, R700VertexInstruction *pVTXInst); void AddTEXInstruction(R700_Shader *pShader, R700TextureInstruction *pTEXInst); void AddALUInstruction(R700_Shader *pShader, R700ALUInstruction *pALUInst); +void SetActiveCFlist(R700_Shader *pShader, TypedShaderList * plstCF); void LoadProgram(R700_Shader *pShader); void UpdateShaderRegisters(R700_Shader *pShader); diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index ffc6068bd8..c8f72d588b 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -111,6 +111,15 @@ unsigned int Map_Vertex_Output(r700_AssemblerBase *pAsm, } } + for(i=VERT_RESULT_VAR0; iBase.OutputsWritten & unBit) + { + pAsm->ucVP_OutputMap[i] = unTotal++; + } + } + return (unTotal - unStart); } @@ -235,6 +244,8 @@ void Map_Vertex_Program(GLcontext *ctx, pAsm->number_used_registers += mesa_vp->Base.NumTemporaries; } + pAsm->flag_reg_index = pAsm->number_used_registers++; + pAsm->uFirstHelpReg = pAsm->number_used_registers; } @@ -324,7 +335,10 @@ struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, return NULL; } - if(GL_FALSE == AssembleInstr(vp->mesa_program->Base.NumInstructions, + InitShaderProgram(&(vp->r700AsmCode)); + + if(GL_FALSE == AssembleInstr(0, + vp->mesa_program->Base.NumInstructions, &(vp->mesa_program->Base.Instructions[0]), &(vp->r700AsmCode)) ) { @@ -336,6 +350,11 @@ struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, return NULL; } + if( GL_FALSE == RelocProgram(&(vp->r700AsmCode)) ) + { + return GL_FALSE; + } + vp->r700Shader.nRegs = (vp->r700AsmCode.number_used_registers == 0) ? 0 : (vp->r700AsmCode.number_used_registers - 1); -- cgit v1.2.3 From de460871605c5575c5513dd1283cb61710b60cfe Mon Sep 17 00:00:00 2001 From: Richard Li Date: Wed, 18 Nov 2009 14:43:59 -0500 Subject: r600 : add some defs --- src/mesa/drivers/dri/r600/r700_assembler.c | 35 ++++++++++++++++++++++++++++-- src/mesa/drivers/dri/r600/r700_assembler.h | 21 ++++++++++++++++++ src/mesa/drivers/dri/r600/r700_shader.c | 2 +- 3 files changed, 55 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 4b5d40bd3a..6e8d1cd927 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -39,6 +39,7 @@ #include "r700_assembler.h" #define USE_CF_FOR_CONTINUE_BREAK 1 +#define USE_CF_FOR_POP_AFTER 1 BITS addrmode_PVSDST(PVSDST * pPVSDST) { @@ -489,10 +490,12 @@ int Init_r700_AssemblerBase(SHADER_PIPE_TYPE spt, r700_AssemblerBase* pAsm, R700 pAsm->unCallerArrayPointer = 0; pAsm->CALLSP = 0; - pAsm->CALLSTACK[0].FCSP_BeforeEntry; + pAsm->CALLSTACK[0].FCSP_BeforeEntry = 0; pAsm->CALLSTACK[0].plstCFInstructions_local = &(pAsm->pR700Shader->lstCFInstructions); + pAsm->CALLSTACK[0].stackUsage.bits = 0; + SetActiveCFlist(pAsm->pR700Shader, pAsm->CALLSTACK[0].plstCFInstructions_local); pAsm->unCFflags = 0; @@ -4978,6 +4981,21 @@ GLboolean assemble_EXPORT(r700_AssemblerBase *pAsm) return GL_TRUE; } +inline void checkStackDepth(r700_AssemblerBase *pAsm, GLuint uReason) +{ + switch (uReason) + { + case FC_PUSH_VPM: + break; + case FC_PUSH_WQM: + break; + case FC_LOOP: + break; + case FC_REP: + break; + }; +} + GLboolean jumpToOffest(r700_AssemblerBase *pAsm, GLuint pops, GLint offset) { if(GL_FALSE == add_cf_instruction(pAsm) ) @@ -5024,7 +5042,7 @@ GLboolean pops(r700_AssemblerBase *pAsm, GLuint pops) return GL_TRUE; } -GLboolean assemble_IF(r700_AssemblerBase *pAsm) +GLboolean assemble_IF(r700_AssemblerBase *pAsm, GLboolean bHasElse) { if(GL_FALSE == add_cf_instruction(pAsm) ) { @@ -5056,10 +5074,12 @@ GLboolean assemble_IF(r700_AssemblerBase *pAsm) pAsm->fc_stack[pAsm->FCSP].midLen= 0; pAsm->fc_stack[pAsm->FCSP].first = pAsm->cf_current_cf_clause_ptr; +#ifndef USE_CF_FOR_POP_AFTER if(GL_TRUE != bHasElse) { pAsm->alu_x_opcode = SQ_CF_INST_ALU_POP_AFTER; } +#endif /* USE_CF_FOR_POP_AFTER */ pAsm->branch_depth++; @@ -5072,6 +5092,10 @@ GLboolean assemble_IF(r700_AssemblerBase *pAsm) GLboolean assemble_ELSE(r700_AssemblerBase *pAsm) { +#ifdef USE_CF_FOR_POP_AFTER + pops(pAsm, 1); +#endif /* USE_CF_FOR_POP_AFTER */ + if(GL_FALSE == add_cf_instruction(pAsm) ) { return GL_FALSE; @@ -5094,7 +5118,9 @@ GLboolean assemble_ELSE(r700_AssemblerBase *pAsm) pAsm->fc_stack[pAsm->FCSP].mid[0] = pAsm->cf_current_cf_clause_ptr; //pAsm->fc_stack[pAsm->FCSP].unNumMid = 1; +#ifndef USE_CF_FOR_POP_AFTER pAsm->alu_x_opcode = SQ_CF_INST_ALU_POP_AFTER; +#endif /* USE_CF_FOR_POP_AFTER */ pAsm->fc_stack[pAsm->FCSP].first->m_Word0.f.addr = pAsm->pR700Shader->plstCFInstructions_active->uNumOfNode - 1; @@ -5103,6 +5129,10 @@ GLboolean assemble_ELSE(r700_AssemblerBase *pAsm) GLboolean assemble_ENDIF(r700_AssemblerBase *pAsm) { +#ifdef USE_CF_FOR_POP_AFTER + pops(pAsm, 1); +#endif /* USE_CF_FOR_POP_AFTER */ + pAsm->alu_x_opcode = SQ_CF_INST_ALU; if(NULL == pAsm->fc_stack[pAsm->FCSP].mid) @@ -5410,6 +5440,7 @@ GLboolean assemble_BGNSUB(r700_AssemblerBase *pAsm, GLint nILindex) pAsm->CALLSTACK[pAsm->CALLSP].FCSP_BeforeEntry = pAsm->FCSP; pAsm->CALLSTACK[pAsm->CALLSP].plstCFInstructions_local = &(pAsm->subs[pAsm->unSubArrayPointer].lstCFInstructions_local); + pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.bits = 0; SetActiveCFlist(pAsm->pR700Shader, pAsm->CALLSTACK[pAsm->CALLSP].plstCFInstructions_local); diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index 85d32212c0..516923f67c 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -259,6 +259,8 @@ enum FC_IF = 1, FC_LOOP = 2, FC_REP = 3, + FC_PUSH_VPM = 4, + FC_PUSH_WQM = 5, COND_NONE = 0, COND_BOOL = 1, @@ -304,12 +306,30 @@ typedef struct CALLER_POINTER #define SQ_MAX_CALL_DEPTH 0x00000020 +typedef struct STACK_USAGE +{ + BITS pushs :8; + BITS current :8; + BITS max :8; +} STACK_USAGE; + +typedef union STACKDWORDtag +{ + BITS bits; + STACK_USAGE su; +} STACKDWORD; + typedef struct CALL_LEVEL { unsigned int FCSP_BeforeEntry; + STACKDWORD stackUsage; TypedShaderList * plstCFInstructions_local; } CALL_LEVEL; +#define HAS_CURRENT_LOOPRET 0x1L +#define HAS_LOOPRET 0x2L +#define LOOPRET_FLAGS HAS_LOOPRET | HAS_CURRENT_LOOPRET + typedef struct r700_AssemblerBase { R700ControlFlowSXClause* cf_last_export_ptr; @@ -429,6 +449,7 @@ typedef struct r700_AssemblerBase } r700_AssemblerBase; //Internal use +inline void checkStackDepth(r700_AssemblerBase *pAsm, GLuint uReason); BITS addrmode_PVSDST(PVSDST * pPVSDST); void setaddrmode_PVSDST(PVSDST * pPVSDST, BITS addrmode); void nomask_PVSDST(PVSDST * pPVSDST); diff --git a/src/mesa/drivers/dri/r600/r700_shader.c b/src/mesa/drivers/dri/r600/r700_shader.c index 2eed1acc2f..db951e48c4 100644 --- a/src/mesa/drivers/dri/r600/r700_shader.c +++ b/src/mesa/drivers/dri/r600/r700_shader.c @@ -140,7 +140,7 @@ void Init_R700_Shader(R700_Shader * pShader) pShader->killIsUsed = GL_FALSE; pShader->uCFOffset = 0; - pShader->uStackSize = 0; + pShader->uStackSize = 10; //richard test pShader->uMaxCallDepth = 0; pShader->bSurfAllocated = GL_FALSE; -- cgit v1.2.3 From eec428280075c12dfef61bf3f18012dece384923 Mon Sep 17 00:00:00 2001 From: Richard Li Date: Wed, 18 Nov 2009 14:56:01 -0500 Subject: r600 : update PS and VS emit count for loop constants. --- src/mesa/drivers/dri/r600/r700_chip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 197916ac0d..705b5738ed 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -1310,8 +1310,8 @@ void r600InitAtoms(context_t *context) ALLOC_STATE(spi, always, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState); ALLOC_STATE(vpt, always, 16, r700SendViewportState); ALLOC_STATE(fs, always, 18, r700SendFSState); - ALLOC_STATE(vs, always, 18, r700SendVSState); - ALLOC_STATE(ps, always, 21, r700SendPSState); + ALLOC_STATE(vs, always, 21, r700SendVSState); + ALLOC_STATE(ps, always, 24, r700SendPSState); ALLOC_STATE(vs_consts, vs_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendVSConsts); ALLOC_STATE(ps_consts, ps_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendPSConsts); ALLOC_STATE(vtx, vtx, (6 + (VERT_ATTRIB_MAX * 18)), r700SendVTXState); -- cgit v1.2.3 From 6345a7ba447d3e04b939ead6fee44fe9201ec2e3 Mon Sep 17 00:00:00 2001 From: Richard Li Date: Thu, 19 Nov 2009 16:05:43 -0500 Subject: r600 : check in shader code test enable flag: if flag R600_ENABLE_GLSL_TEST defined, IL shader code will goto r600 assembler. The test base is /mesa/progs/glsl/brick, and changes shader code in CH06-brick.frag/vert to test different logic op combination. (if,else,while,function,...). The stack depth code is not in yet, so it is hard coded now. So complex code would not run (such as things like 8 loops embeded loop in loop). --- src/mesa/drivers/dri/r600/r600_context.c | 54 +++++++++++++++++++++++++++--- src/mesa/drivers/dri/r600/r700_assembler.c | 44 +++++++++++++++--------- 2 files changed, 77 insertions(+), 21 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index dbd233729c..ca0a670f3c 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -72,7 +72,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "vblank.h" #include "utils.h" -#include "xmlpool.h" /* for symbolic values of enum-type options */ +#include "xmlpool.h" /* for symbolic values of enum-type options */ + +//#define R600_ENABLE_GLSL_TEST 1 #define need_GL_VERSION_2_0 #define need_GL_ARB_occlusion_query @@ -154,8 +156,12 @@ static const struct dri_extension mm_extensions[] = { * The GL 2.0 functions are needed to make display lists work with * functions added by GL_ATI_separate_stencil. */ -static const struct dri_extension gl_20_extension[] = { - {"GL_VERSION_2_0", GL_VERSION_2_0_functions }, +static const struct dri_extension gl_20_extension[] = { +#ifdef R600_ENABLE_GLSL_TEST + {"GL_ARB_shading_language_100", GL_VERSION_2_0_functions }, +#else + {"GL_VERSION_2_0", GL_VERSION_2_0_functions }, +#endif /* R600_ENABLE_GLSL_TEST */ }; static const struct tnl_pipeline_stage *r600_pipeline[] = { @@ -306,7 +312,28 @@ static void r600InitGLExtensions(GLcontext *ctx) driInitExtensions(ctx, card_extensions, GL_TRUE); if (r600->radeon.radeonScreen->kernel_mm) - driInitExtensions(ctx, mm_extensions, GL_FALSE); + driInitExtensions(ctx, mm_extensions, GL_FALSE); + +#ifdef R600_ENABLE_GLSL_TEST + driInitExtensions(ctx, gl_20_extension, GL_TRUE); + //_mesa_enable_2_0_extensions(ctx); + //1.5 + ctx->Extensions.ARB_occlusion_query = GL_TRUE; + ctx->Extensions.ARB_vertex_buffer_object = GL_TRUE; + ctx->Extensions.EXT_shadow_funcs = GL_TRUE; + //2.0 + ctx->Extensions.ARB_draw_buffers = GL_TRUE; + ctx->Extensions.ARB_point_sprite = GL_TRUE; + ctx->Extensions.ARB_shader_objects = GL_TRUE; + ctx->Extensions.ARB_vertex_shader = GL_TRUE; + ctx->Extensions.ARB_fragment_shader = GL_TRUE; + ctx->Extensions.ARB_texture_non_power_of_two = GL_TRUE; + ctx->Extensions.EXT_blend_equation_separate = GL_TRUE; + ctx->Extensions.ATI_separate_stencil = GL_TRUE; + + /* glsl compiler has problem if this is not GL_TRUE */ + ctx->Shader.EmitCondCodes = GL_TRUE; +#endif /* R600_ENABLE_GLSL_TEST */ if (driQueryOptionb (&r600->radeon.optionCache, "disable_stencil_two_side")) @@ -341,7 +368,24 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, assert(glVisual); assert(driContextPriv); - assert(screen); + assert(screen); + + //richard test + FILE *pFile = NULL; + unsigned long ulByteToWrite = 0; + char szStr[1024]; + + pFile = fopen("//home//richard//rtp-log//func_call.log", "a+"); + if(NULL != pFile) + { + sprintf(szStr, "r600CreateContext \r\n"); + ulByteToWrite = strlen(szStr); + fwrite(szStr, 1, ulByteToWrite, pFile); + + fclose(pFile); + pFile = NULL; + } + //------------- /* Allocate the R600 context */ r600 = (context_t*) CALLOC(sizeof(*r600)); diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 6e8d1cd927..16ac920f29 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -4983,17 +4983,31 @@ GLboolean assemble_EXPORT(r700_AssemblerBase *pAsm) inline void checkStackDepth(r700_AssemblerBase *pAsm, GLuint uReason) { - switch (uReason) - { - case FC_PUSH_VPM: - break; - case FC_PUSH_WQM: - break; - case FC_LOOP: - break; - case FC_REP: - break; - }; + switch (uReason) + { + case FC_PUSH_VPM: + pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs++; + pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.current++; + break; + case FC_PUSH_WQM: + pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs++; + pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.current += 4; + break; + case FC_LOOP: + pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs += 4; + break; + case FC_REP: + /* TODO : for 16 vp asic, should += 2; */ + pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs += 1; + break; + }; + + if(pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs + > pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.max) + { + pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.max = + pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs; + } } GLboolean jumpToOffest(r700_AssemblerBase *pAsm, GLuint pops, GLint offset) @@ -5092,10 +5106,6 @@ GLboolean assemble_IF(r700_AssemblerBase *pAsm, GLboolean bHasElse) GLboolean assemble_ELSE(r700_AssemblerBase *pAsm) { -#ifdef USE_CF_FOR_POP_AFTER - pops(pAsm, 1); -#endif /* USE_CF_FOR_POP_AFTER */ - if(GL_FALSE == add_cf_instruction(pAsm) ) { return GL_FALSE; @@ -5647,7 +5657,9 @@ GLboolean testFlag(r700_AssemblerBase *pAsm) { return GL_FALSE; } -#endif +#endif + + checkStackDepth(pAsm, FC_PUSH_VPM); return GL_TRUE; } -- cgit v1.2.3 From 48dfd3938e428295c45692cfde0a2afff04a7970 Mon Sep 17 00:00:00 2001 From: Richard Li Date: Thu, 19 Nov 2009 16:55:16 -0500 Subject: r600 : change shader pop method for now. --- src/mesa/drivers/dri/r600/r700_assembler.c | 54 +++++++++++++++--------------- 1 file changed, 27 insertions(+), 27 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 16ac920f29..e3bc46802f 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -39,7 +39,7 @@ #include "r700_assembler.h" #define USE_CF_FOR_CONTINUE_BREAK 1 -#define USE_CF_FOR_POP_AFTER 1 +//#define USE_CF_FOR_POP_AFTER 1 BITS addrmode_PVSDST(PVSDST * pPVSDST) { @@ -4983,30 +4983,30 @@ GLboolean assemble_EXPORT(r700_AssemblerBase *pAsm) inline void checkStackDepth(r700_AssemblerBase *pAsm, GLuint uReason) { - switch (uReason) - { - case FC_PUSH_VPM: - pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs++; - pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.current++; - break; - case FC_PUSH_WQM: - pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs++; - pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.current += 4; - break; - case FC_LOOP: - pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs += 4; - break; - case FC_REP: - /* TODO : for 16 vp asic, should += 2; */ - pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs += 1; - break; - }; - - if(pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs - > pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.max) - { - pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.max = - pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs; + switch (uReason) + { + case FC_PUSH_VPM: + pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs++; + pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.current++; + break; + case FC_PUSH_WQM: + pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs++; + pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.current += 4; + break; + case FC_LOOP: + pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs += 4; + break; + case FC_REP: + /* TODO : for 16 vp asic, should += 2; */ + pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs += 1; + break; + }; + + if(pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs + > pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.max) + { + pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.max = + pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs; } } @@ -5657,8 +5657,8 @@ GLboolean testFlag(r700_AssemblerBase *pAsm) { return GL_FALSE; } -#endif - +#endif + checkStackDepth(pAsm, FC_PUSH_VPM); return GL_TRUE; -- cgit v1.2.3 From b09e74901a4f92299fe3f52f57d27fd5ca5bdd2d Mon Sep 17 00:00:00 2001 From: Richard Li Date: Thu, 19 Nov 2009 17:41:10 -0500 Subject: r600 : Clean up a bit test code mess. --- src/mesa/drivers/dri/r600/r600_context.c | 17 ----------------- 1 file changed, 17 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index ca0a670f3c..97b25ea3ff 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -369,23 +369,6 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, assert(glVisual); assert(driContextPriv); assert(screen); - - //richard test - FILE *pFile = NULL; - unsigned long ulByteToWrite = 0; - char szStr[1024]; - - pFile = fopen("//home//richard//rtp-log//func_call.log", "a+"); - if(NULL != pFile) - { - sprintf(szStr, "r600CreateContext \r\n"); - ulByteToWrite = strlen(szStr); - fwrite(szStr, 1, ulByteToWrite, pFile); - - fclose(pFile); - pFile = NULL; - } - //------------- /* Allocate the R600 context */ r600 = (context_t*) CALLOC(sizeof(*r600)); -- cgit v1.2.3 From 08e5d1ecad79d1c08541ba08a436f5145c5c9376 Mon Sep 17 00:00:00 2001 From: Richard Li Date: Fri, 20 Nov 2009 10:58:05 -0500 Subject: r600 : eliminate Wondows line ending for test code. --- src/mesa/drivers/dri/r600/r600_context.c | 56 ++++++++++++++++---------------- 1 file changed, 28 insertions(+), 28 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 97b25ea3ff..7de29e5bb8 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -72,8 +72,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "vblank.h" #include "utils.h" -#include "xmlpool.h" /* for symbolic values of enum-type options */ - +#include "xmlpool.h" /* for symbolic values of enum-type options */ + //#define R600_ENABLE_GLSL_TEST 1 #define need_GL_VERSION_2_0 @@ -156,11 +156,11 @@ static const struct dri_extension mm_extensions[] = { * The GL 2.0 functions are needed to make display lists work with * functions added by GL_ATI_separate_stencil. */ -static const struct dri_extension gl_20_extension[] = { -#ifdef R600_ENABLE_GLSL_TEST - {"GL_ARB_shading_language_100", GL_VERSION_2_0_functions }, +static const struct dri_extension gl_20_extension[] = { +#ifdef R600_ENABLE_GLSL_TEST + {"GL_ARB_shading_language_100", GL_VERSION_2_0_functions }, #else - {"GL_VERSION_2_0", GL_VERSION_2_0_functions }, + {"GL_VERSION_2_0", GL_VERSION_2_0_functions }, #endif /* R600_ENABLE_GLSL_TEST */ }; @@ -312,27 +312,27 @@ static void r600InitGLExtensions(GLcontext *ctx) driInitExtensions(ctx, card_extensions, GL_TRUE); if (r600->radeon.radeonScreen->kernel_mm) - driInitExtensions(ctx, mm_extensions, GL_FALSE); - -#ifdef R600_ENABLE_GLSL_TEST - driInitExtensions(ctx, gl_20_extension, GL_TRUE); - //_mesa_enable_2_0_extensions(ctx); - //1.5 - ctx->Extensions.ARB_occlusion_query = GL_TRUE; - ctx->Extensions.ARB_vertex_buffer_object = GL_TRUE; - ctx->Extensions.EXT_shadow_funcs = GL_TRUE; - //2.0 - ctx->Extensions.ARB_draw_buffers = GL_TRUE; - ctx->Extensions.ARB_point_sprite = GL_TRUE; - ctx->Extensions.ARB_shader_objects = GL_TRUE; - ctx->Extensions.ARB_vertex_shader = GL_TRUE; - ctx->Extensions.ARB_fragment_shader = GL_TRUE; - ctx->Extensions.ARB_texture_non_power_of_two = GL_TRUE; - ctx->Extensions.EXT_blend_equation_separate = GL_TRUE; - ctx->Extensions.ATI_separate_stencil = GL_TRUE; - - /* glsl compiler has problem if this is not GL_TRUE */ - ctx->Shader.EmitCondCodes = GL_TRUE; + driInitExtensions(ctx, mm_extensions, GL_FALSE); + +#ifdef R600_ENABLE_GLSL_TEST + driInitExtensions(ctx, gl_20_extension, GL_TRUE); + //_mesa_enable_2_0_extensions(ctx); + //1.5 + ctx->Extensions.ARB_occlusion_query = GL_TRUE; + ctx->Extensions.ARB_vertex_buffer_object = GL_TRUE; + ctx->Extensions.EXT_shadow_funcs = GL_TRUE; + //2.0 + ctx->Extensions.ARB_draw_buffers = GL_TRUE; + ctx->Extensions.ARB_point_sprite = GL_TRUE; + ctx->Extensions.ARB_shader_objects = GL_TRUE; + ctx->Extensions.ARB_vertex_shader = GL_TRUE; + ctx->Extensions.ARB_fragment_shader = GL_TRUE; + ctx->Extensions.ARB_texture_non_power_of_two = GL_TRUE; + ctx->Extensions.EXT_blend_equation_separate = GL_TRUE; + ctx->Extensions.ATI_separate_stencil = GL_TRUE; + + /* glsl compiler has problem if this is not GL_TRUE */ + ctx->Shader.EmitCondCodes = GL_TRUE; #endif /* R600_ENABLE_GLSL_TEST */ if (driQueryOptionb @@ -368,7 +368,7 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, assert(glVisual); assert(driContextPriv); - assert(screen); + assert(screen); /* Allocate the R600 context */ r600 = (context_t*) CALLOC(sizeof(*r600)); -- cgit v1.2.3 From a02938a8421270389178d4969a5411a1691d929a Mon Sep 17 00:00:00 2001 From: Richard Li Date: Fri, 20 Nov 2009 16:36:55 -0500 Subject: r600 : use cf for all pop now, left optimization for future. --- src/mesa/drivers/dri/r600/r700_assembler.c | 56 ++++++++++++++++++++++-------- src/mesa/drivers/dri/r600/r700_assembler.h | 2 +- 2 files changed, 42 insertions(+), 16 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index e3bc46802f..27083a895c 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -39,7 +39,7 @@ #include "r700_assembler.h" #define USE_CF_FOR_CONTINUE_BREAK 1 -//#define USE_CF_FOR_POP_AFTER 1 +#define USE_CF_FOR_POP_AFTER 1 BITS addrmode_PVSDST(PVSDST * pPVSDST) { @@ -3022,7 +3022,6 @@ GLboolean next_ins2(r700_AssemblerBase *pAsm) pAsm->is_tex = GL_FALSE; pAsm->need_tex_barrier = GL_FALSE; - //richard nov.16 glsl pAsm->D2.bits = 0; return GL_TRUE; @@ -5377,32 +5376,35 @@ GLboolean assemble_ENDLOOP(r700_AssemblerBase *pAsm) return GL_FALSE; } - unsigned int unFCSP = 0; + GLuint unFCSP; + GLuint unIF = 0; if((pAsm->unCFflags & HAS_CURRENT_LOOPRET) > 0) { for(unFCSP=(pAsm->FCSP-1); unFCSP>pAsm->CALLSTACK[pAsm->CALLSP].FCSP_BeforeEntry; unFCSP--) { if(FC_LOOP == pAsm->fc_stack[unFCSP].type) { + breakLoopOnFlag(pAsm, unFCSP); break; } + else if(FC_IF == pAsm->fc_stack[unFCSP].type) + { + unIF++; + } } if(unFCSP <= pAsm->CALLSTACK[pAsm->CALLSP].FCSP_BeforeEntry) { - unFCSP = 0; - - returnOnFlag(pAsm); +#ifdef USE_CF_FOR_POP_AFTER + returnOnFlag(pAsm, unIF); +#else + returnOnFlag(pAsm, 0); +#endif /* USE_CF_FOR_POP_AFTER */ pAsm->unCFflags &= ~HAS_CURRENT_LOOPRET; } } pAsm->branch_depth--; pAsm->FCSP--; - - if(unFCSP > 0) - { - breakLoopOnFlag(pAsm, unFCSP); - } return GL_TRUE; } @@ -5459,25 +5461,38 @@ GLboolean assemble_BGNSUB(r700_AssemblerBase *pAsm, GLint nILindex) /* start sub */ pAsm->alu_x_opcode = SQ_CF_INST_ALU; + pAsm->FCSP++; + pAsm->fc_stack[pAsm->FCSP].type = FC_REP; + return GL_TRUE; } GLboolean assemble_ENDSUB(r700_AssemblerBase *pAsm) { + if(pAsm->fc_stack[pAsm->FCSP].type != FC_REP) + { + radeon_error("BGNSUB/ENDSUB in shader code are not paired. \n"); + return GL_FALSE; + } + pAsm->CALLSP--; SetActiveCFlist(pAsm->pR700Shader, pAsm->CALLSTACK[pAsm->CALLSP].plstCFInstructions_local); pAsm->alu_x_opcode = SQ_CF_INST_ALU; + pAsm->FCSP--; + return GL_TRUE; } GLboolean assemble_RET(r700_AssemblerBase *pAsm) { + GLuint unIF = 0; + if(pAsm->CALLSP > 0) { /* in sub */ - unsigned int unFCSP; + GLuint unFCSP; for(unFCSP=pAsm->FCSP; unFCSP>pAsm->CALLSTACK[pAsm->CALLSP].FCSP_BeforeEntry; unFCSP--) { if(FC_LOOP == pAsm->fc_stack[unFCSP].type) @@ -5488,9 +5503,20 @@ GLboolean assemble_RET(r700_AssemblerBase *pAsm) return GL_TRUE; } + else if(FC_IF == pAsm->fc_stack[unFCSP].type) + { + unIF++; + } } } - + +#ifdef USE_CF_FOR_POP_AFTER + if(unIF > 0) + { + pops(pAsm, unIF); + } +#endif /* USE_CF_FOR_POP_AFTER */ + add_return_inst(pAsm); return GL_TRUE; @@ -5664,12 +5690,12 @@ GLboolean testFlag(r700_AssemblerBase *pAsm) return GL_TRUE; } -GLboolean returnOnFlag(r700_AssemblerBase *pAsm) +GLboolean returnOnFlag(r700_AssemblerBase *pAsm, GLuint unIF) { testFlag(pAsm); jumpToOffest(pAsm, 1, 4); setRetInLoopFlag(pAsm, SQ_SEL_0); - pops(pAsm, 1); + pops(pAsm, unIF + 1); add_return_inst(pAsm); return GL_TRUE; diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index 516923f67c..ca562d29f1 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -553,7 +553,7 @@ GLboolean jumpToOffest(r700_AssemblerBase *pAsm, GLuint pops, GLint offset); GLboolean setRetInLoopFlag(r700_AssemblerBase *pAsm, GLuint flagValue); GLboolean testFlag(r700_AssemblerBase *pAsm); GLboolean breakLoopOnFlag(r700_AssemblerBase *pAsm, GLuint unFCSP); -GLboolean returnOnFlag(r700_AssemblerBase *pAsm); +GLboolean returnOnFlag(r700_AssemblerBase *pAsm, GLuint unIF); GLboolean assemble_math_function(r700_AssemblerBase* pAsm, BITS opcode); GLboolean assemble_ABS(r700_AssemblerBase *pAsm); -- cgit v1.2.3 From 1f8c23d9db84178f5b129dcd5f6dbae4a31f796a Mon Sep 17 00:00:00 2001 From: Richard Li Date: Sun, 22 Nov 2009 12:58:28 -0500 Subject: r600 : add stack depth calculation, enable CF pop. --- src/mesa/drivers/dri/r600/r700_assembler.c | 341 ++++++++++++++++++----------- src/mesa/drivers/dri/r600/r700_assembler.h | 41 ++-- src/mesa/drivers/dri/r600/r700_shader.c | 2 +- 3 files changed, 223 insertions(+), 161 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 27083a895c..16cdb741ae 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -388,99 +388,94 @@ int Init_r700_AssemblerBase(SHADER_PIPE_TYPE spt, r700_AssemblerBase* pAsm, R700 pAsm->pR700Shader = pShader; pAsm->currentShaderType = spt; - pAsm->cf_last_export_ptr = NULL; + pAsm->cf_last_export_ptr = NULL; - pAsm->cf_current_export_clause_ptr = NULL; - pAsm->cf_current_alu_clause_ptr = NULL; - pAsm->cf_current_tex_clause_ptr = NULL; - pAsm->cf_current_vtx_clause_ptr = NULL; - pAsm->cf_current_cf_clause_ptr = NULL; + pAsm->cf_current_export_clause_ptr = NULL; + pAsm->cf_current_alu_clause_ptr = NULL; + pAsm->cf_current_tex_clause_ptr = NULL; + pAsm->cf_current_vtx_clause_ptr = NULL; + pAsm->cf_current_cf_clause_ptr = NULL; - // No clause has been created yet - pAsm->cf_current_clause_type = CF_EMPTY_CLAUSE; + // No clause has been created yet + pAsm->cf_current_clause_type = CF_EMPTY_CLAUSE; - pAsm->number_of_colorandz_exports = 0; - pAsm->number_of_exports = 0; - pAsm->number_of_export_opcodes = 0; + pAsm->number_of_colorandz_exports = 0; + pAsm->number_of_exports = 0; + pAsm->number_of_export_opcodes = 0; pAsm->alu_x_opcode = 0; pAsm->D2.bits = 0; - pAsm->D.bits = 0; - pAsm->S[0].bits = 0; - pAsm->S[1].bits = 0; - pAsm->S[2].bits = 0; + pAsm->D.bits = 0; + pAsm->S[0].bits = 0; + pAsm->S[1].bits = 0; + pAsm->S[2].bits = 0; - pAsm->uLastPosUpdate = 0; + pAsm->uLastPosUpdate = 0; - *(BITS *) &pAsm->fp_stOutFmt0 = 0; - - pAsm->uIIns = 0; - pAsm->uOIns = 0; - pAsm->number_used_registers = 0; - pAsm->uUsedConsts = 256; - + *(BITS *) &pAsm->fp_stOutFmt0 = 0; - // Fragment programs - pAsm->uBoolConsts = 0; - pAsm->uIntConsts = 0; - pAsm->uInsts = 0; - pAsm->uConsts = 0; + pAsm->uIIns = 0; + pAsm->uOIns = 0; + pAsm->number_used_registers = 0; + pAsm->uUsedConsts = 256; - pAsm->FCSP = 0; - pAsm->fc_stack[0].type = FC_NONE; - pAsm->branch_depth = 0; - pAsm->max_branch_depth = 0; + // Fragment programs + pAsm->uBoolConsts = 0; + pAsm->uIntConsts = 0; + pAsm->uInsts = 0; + pAsm->uConsts = 0; - pAsm->aArgSubst[0] = - pAsm->aArgSubst[1] = - pAsm->aArgSubst[2] = - pAsm->aArgSubst[3] = (-1); + pAsm->FCSP = 0; + pAsm->fc_stack[0].type = FC_NONE; - pAsm->uOutputs = 0; - - for (i=0; icolor_export_register_number[i] = (-1); - } + pAsm->aArgSubst[0] = + pAsm->aArgSubst[1] = + pAsm->aArgSubst[2] = + pAsm->aArgSubst[3] = (-1); + pAsm->uOutputs = 0; - pAsm->depth_export_register_number = (-1); - pAsm->stencil_export_register_number = (-1); - pAsm->coverage_to_mask_export_register_number = (-1); - pAsm->mask_export_register_number = (-1); + for (i=0; icolor_export_register_number[i] = (-1); + } - pAsm->starting_export_register_number = 0; - pAsm->starting_vfetch_register_number = 0; - pAsm->starting_temp_register_number = 0; - pAsm->uFirstHelpReg = 0; + pAsm->depth_export_register_number = (-1); + pAsm->stencil_export_register_number = (-1); + pAsm->coverage_to_mask_export_register_number = (-1); + pAsm->mask_export_register_number = (-1); - pAsm->input_position_is_used = GL_FALSE; - pAsm->input_normal_is_used = GL_FALSE; + pAsm->starting_export_register_number = 0; + pAsm->starting_vfetch_register_number = 0; + pAsm->starting_temp_register_number = 0; + pAsm->uFirstHelpReg = 0; + pAsm->input_position_is_used = GL_FALSE; + pAsm->input_normal_is_used = GL_FALSE; - for (i=0; iinput_color_is_used[ i ] = GL_FALSE; - } + for (i=0; iinput_color_is_used[ i ] = GL_FALSE; + } - for (i=0; iinput_texture_unit_is_used[ i ] = GL_FALSE; - } + for (i=0; iinput_texture_unit_is_used[ i ] = GL_FALSE; + } - for (i=0; ivfetch_instruction_ptr_array[ i ] = NULL; - } + for (i=0; ivfetch_instruction_ptr_array[ i ] = NULL; + } - pAsm->number_of_inputs = 0; + pAsm->number_of_inputs = 0; - pAsm->is_tex = GL_FALSE; - pAsm->need_tex_barrier = GL_FALSE; + pAsm->is_tex = GL_FALSE; + pAsm->need_tex_barrier = GL_FALSE; pAsm->subs = NULL; pAsm->unSubArraySize = 0; @@ -494,13 +489,14 @@ int Init_r700_AssemblerBase(SHADER_PIPE_TYPE spt, r700_AssemblerBase* pAsm, R700 pAsm->CALLSTACK[0].plstCFInstructions_local = &(pAsm->pR700Shader->lstCFInstructions); - pAsm->CALLSTACK[0].stackUsage.bits = 0; + pAsm->CALLSTACK[0].max = 0; + pAsm->CALLSTACK[0].current = 0; SetActiveCFlist(pAsm->pR700Shader, pAsm->CALLSTACK[0].plstCFInstructions_local); pAsm->unCFflags = 0; - return 0; + return 0; } GLboolean IsTex(gl_inst_opcode Opcode) @@ -4980,32 +4976,74 @@ GLboolean assemble_EXPORT(r700_AssemblerBase *pAsm) return GL_TRUE; } -inline void checkStackDepth(r700_AssemblerBase *pAsm, GLuint uReason) +inline void decreaseCurrent(r700_AssemblerBase *pAsm, GLuint uReason) +{ + switch (uReason) + { + case FC_PUSH_VPM: + pAsm->CALLSTACK[pAsm->CALLSP].current--; + break; + case FC_PUSH_WQM: + pAsm->CALLSTACK[pAsm->CALLSP].current -= 4; + break; + case FC_LOOP: + pAsm->CALLSTACK[pAsm->CALLSP].current -= 4; + break; + case FC_REP: + /* TODO : for 16 vp asic, should -= 2; */ + pAsm->CALLSTACK[pAsm->CALLSP].current -= 1; + break; + }; +} + +inline void checkStackDepth(r700_AssemblerBase *pAsm, GLuint uReason, GLboolean bCheckMaxOnly) { + if(GL_TRUE == bCheckMaxOnly) + { + switch (uReason) + { + case FC_PUSH_VPM: + if((pAsm->CALLSTACK[pAsm->CALLSP].current + 1) + > pAsm->CALLSTACK[pAsm->CALLSP].max) + { + pAsm->CALLSTACK[pAsm->CALLSP].max = + pAsm->CALLSTACK[pAsm->CALLSP].current + 1; + } + break; + case FC_PUSH_WQM: + if((pAsm->CALLSTACK[pAsm->CALLSP].current + 4) + > pAsm->CALLSTACK[pAsm->CALLSP].max) + { + pAsm->CALLSTACK[pAsm->CALLSP].max = + pAsm->CALLSTACK[pAsm->CALLSP].current + 4; + } + break; + } + return; + } + switch (uReason) { case FC_PUSH_VPM: - pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs++; - pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.current++; + pAsm->CALLSTACK[pAsm->CALLSP].current++; break; case FC_PUSH_WQM: - pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs++; - pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.current += 4; + pAsm->CALLSTACK[pAsm->CALLSP].current += 4; break; case FC_LOOP: - pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs += 4; + pAsm->CALLSTACK[pAsm->CALLSP].current += 4; break; case FC_REP: /* TODO : for 16 vp asic, should += 2; */ - pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs += 1; + pAsm->CALLSTACK[pAsm->CALLSP].current += 1; break; }; - if(pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs - > pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.max) + if(pAsm->CALLSTACK[pAsm->CALLSP].current + > pAsm->CALLSTACK[pAsm->CALLSP].max) { - pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.max = - pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.su.pushs; + pAsm->CALLSTACK[pAsm->CALLSP].max = + pAsm->CALLSTACK[pAsm->CALLSP].current; } } @@ -5082,7 +5120,6 @@ GLboolean assemble_IF(r700_AssemblerBase *pAsm, GLboolean bHasElse) pAsm->FCSP++; pAsm->fc_stack[pAsm->FCSP].type = FC_IF; - pAsm->fc_stack[pAsm->FCSP].bpush = 0; pAsm->fc_stack[pAsm->FCSP].mid = NULL; pAsm->fc_stack[pAsm->FCSP].midLen= 0; pAsm->fc_stack[pAsm->FCSP].first = pAsm->cf_current_cf_clause_ptr; @@ -5094,12 +5131,8 @@ GLboolean assemble_IF(r700_AssemblerBase *pAsm, GLboolean bHasElse) } #endif /* USE_CF_FOR_POP_AFTER */ - pAsm->branch_depth++; + checkStackDepth(pAsm, FC_PUSH_VPM, GL_FALSE); - if(pAsm->branch_depth > pAsm->max_branch_depth) - { - pAsm->max_branch_depth = pAsm->branch_depth; - } return GL_TRUE; } @@ -5164,9 +5197,11 @@ GLboolean assemble_ENDIF(r700_AssemblerBase *pAsm) radeon_error("if/endif in shader code are not paired. \n"); return GL_FALSE; } - pAsm->branch_depth--; + pAsm->FCSP--; + decreaseCurrent(pAsm, FC_PUSH_VPM); + return GL_TRUE; } @@ -5191,18 +5226,13 @@ GLboolean assemble_BGNLOOP(r700_AssemblerBase *pAsm) pAsm->FCSP++; pAsm->fc_stack[pAsm->FCSP].type = FC_LOOP; - pAsm->fc_stack[pAsm->FCSP].bpush = 1; pAsm->fc_stack[pAsm->FCSP].mid = NULL; pAsm->fc_stack[pAsm->FCSP].unNumMid = 0; pAsm->fc_stack[pAsm->FCSP].midLen = 0; pAsm->fc_stack[pAsm->FCSP].first = pAsm->cf_current_cf_clause_ptr; - pAsm->branch_depth++; + checkStackDepth(pAsm, FC_LOOP, GL_FALSE); - if(pAsm->branch_depth > pAsm->max_branch_depth) - { - pAsm->max_branch_depth = pAsm->branch_depth; - } return GL_TRUE; } @@ -5266,6 +5296,8 @@ GLboolean assemble_BRK(r700_AssemblerBase *pAsm) pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1; pAsm->cf_current_cf_clause_ptr->m_Word0.f.addr = pAsm->cf_current_cf_clause_ptr->m_uIndex + 1; + checkStackDepth(pAsm, FC_PUSH_VPM, GL_TRUE); + #endif //USE_CF_FOR_CONTINUE_BREAK return GL_TRUE; } @@ -5330,6 +5362,8 @@ GLboolean assemble_CONT(r700_AssemblerBase *pAsm) pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1; pAsm->cf_current_cf_clause_ptr->m_Word0.f.addr = pAsm->cf_current_cf_clause_ptr->m_uIndex + 1; + checkStackDepth(pAsm, FC_PUSH_VPM, GL_TRUE); + #endif /* USE_CF_FOR_CONTINUE_BREAK */ return GL_TRUE; @@ -5403,8 +5437,9 @@ GLboolean assemble_ENDLOOP(r700_AssemblerBase *pAsm) } } - pAsm->branch_depth--; pAsm->FCSP--; + + decreaseCurrent(pAsm, FC_LOOP); return GL_TRUE; } @@ -5445,14 +5480,16 @@ GLboolean assemble_BGNSUB(r700_AssemblerBase *pAsm, GLint nILindex) pAsm->subs[pAsm->unSubArrayPointer].subIL_Offset = nILindex; pAsm->subs[pAsm->unSubArrayPointer].lstCFInstructions_local.pHead=NULL; - pAsm->subs[pAsm->unSubArrayPointer].lstCFInstructions_local.pTail=NULL; - pAsm->subs[pAsm->unSubArrayPointer].lstCFInstructions_local.uNumOfNode=0; + pAsm->subs[pAsm->unSubArrayPointer].lstCFInstructions_local.pTail=NULL; + pAsm->subs[pAsm->unSubArrayPointer].lstCFInstructions_local.uNumOfNode=0; pAsm->CALLSP++; + pAsm->CALLSTACK[pAsm->CALLSP].subDescIndex = pAsm->unSubArrayPointer; pAsm->CALLSTACK[pAsm->CALLSP].FCSP_BeforeEntry = pAsm->FCSP; pAsm->CALLSTACK[pAsm->CALLSP].plstCFInstructions_local = &(pAsm->subs[pAsm->unSubArrayPointer].lstCFInstructions_local); - pAsm->CALLSTACK[pAsm->CALLSP].stackUsage.bits = 0; + pAsm->CALLSTACK[pAsm->CALLSP].max = 0; + pAsm->CALLSTACK[pAsm->CALLSP].current = 0; SetActiveCFlist(pAsm->pR700Shader, pAsm->CALLSTACK[pAsm->CALLSP].plstCFInstructions_local); @@ -5462,7 +5499,9 @@ GLboolean assemble_BGNSUB(r700_AssemblerBase *pAsm, GLint nILindex) pAsm->alu_x_opcode = SQ_CF_INST_ALU; pAsm->FCSP++; - pAsm->fc_stack[pAsm->FCSP].type = FC_REP; + pAsm->fc_stack[pAsm->FCSP].type = FC_REP; + + checkStackDepth(pAsm, FC_REP, GL_FALSE); return GL_TRUE; } @@ -5475,6 +5514,12 @@ GLboolean assemble_ENDSUB(r700_AssemblerBase *pAsm) return GL_FALSE; } + /* copy max to sub structure */ + pAsm->subs[pAsm->CALLSTACK[pAsm->CALLSP].subDescIndex].unStackDepthMax + = pAsm->CALLSTACK[pAsm->CALLSP].max; + + decreaseCurrent(pAsm, FC_REP); + pAsm->CALLSP--; SetActiveCFlist(pAsm->pR700Shader, pAsm->CALLSTACK[pAsm->CALLSP].plstCFInstructions_local); @@ -5565,18 +5610,42 @@ GLboolean assemble_CAL(r700_AssemblerBase *pAsm, pAsm->unCallerArrayPointer++; int j; + GLuint max; + GLuint unSubID; + GLboolean bRet; for(j=0; junSubArrayPointer; j++) { if(nILindex == pAsm->subs[j].subIL_Offset) { /* compiled before */ + + max = pAsm->subs[j].unStackDepthMax + + pAsm->CALLSTACK[pAsm->CALLSP].current; + if(max > pAsm->CALLSTACK[pAsm->CALLSP].max) + { + pAsm->CALLSTACK[pAsm->CALLSP].max = max; + } + pAsm->callers[pAsm->unCallerArrayPointer - 1].subDescIndex = j; return GL_TRUE; } } pAsm->callers[pAsm->unCallerArrayPointer - 1].subDescIndex = pAsm->unSubArrayPointer; + unSubID = pAsm->unSubArrayPointer; + + bRet = AssembleInstr(nILindex, uiNumberInsts, pILInst, pAsm); + + if(GL_TRUE == bRet) + { + max = pAsm->subs[unSubID].unStackDepthMax + + pAsm->CALLSTACK[pAsm->CALLSP].current; + if(max > pAsm->CALLSTACK[pAsm->CALLSP].max) + { + pAsm->CALLSTACK[pAsm->CALLSP].max = max; + } + } - return AssembleInstr(nILindex, uiNumberInsts, pILInst, pAsm); + return bRet; } GLboolean setRetInLoopFlag(r700_AssemblerBase *pAsm, GLuint flagValue) @@ -5685,7 +5754,7 @@ GLboolean testFlag(r700_AssemblerBase *pAsm) } #endif - checkStackDepth(pAsm, FC_PUSH_VPM); + checkStackDepth(pAsm, FC_PUSH_VPM, GL_TRUE); return GL_TRUE; } @@ -5704,7 +5773,7 @@ GLboolean returnOnFlag(r700_AssemblerBase *pAsm, GLuint unIF) GLboolean breakLoopOnFlag(r700_AssemblerBase *pAsm, GLuint unFCSP) { testFlag(pAsm); - + //break if(GL_FALSE == add_cf_instruction(pAsm) ) { @@ -5831,7 +5900,8 @@ GLboolean AssembleInstr(GLuint uiFirstInst, if ( GL_FALSE == assemble_FLR(pR700AsmCode) ) return GL_FALSE; break; - //case OP_FLR_INT: + //case OP_FLR_INT: ; + // if ( GL_FALSE == assemble_FLR_INT() ) // return GL_FALSE; // break; @@ -6351,11 +6421,47 @@ GLboolean RelocProgram(r700_AssemblerBase * pAsm) R700ShaderInstruction * pInst; R700ControlFlowGenericClause * pCFInst; + /* remove flags init if they are not used */ + if((pAsm->unCFflags & HAS_LOOPRET) == 0) + { + R700ControlFlowALUClause * pCF_ALU; + pInst = plstCFmain->pHead; + while(pInst) + { + if(SIT_CF_ALU == pInst->m_ShaderInstType) + { + pCF_ALU = (R700ControlFlowALUClause *)pInst; + if(1 == pCF_ALU->m_Word1.f.count) + { + pCF_ALU->m_Word1.f.cf_inst = SQ_CF_INST_NOP; + } + else + { + R700ALUInstruction * pALU = pCF_ALU->m_pLinkedALUInstruction; + + pALU->m_pLinkedALUClause = NULL; + pALU = (R700ALUInstruction *)(pALU->pNextInst); + pALU->m_pLinkedALUClause = pCF_ALU; + pCF_ALU->m_pLinkedALUInstruction = pALU; + + pCF_ALU->m_Word1.f.count--; + } + break; + } + pInst = pInst->pNextInst; + }; + } + if(0 == pAsm->unSubArrayPointer) { return GL_TRUE; } + if(pAsm->CALLSTACK[0].max > 0) + { + pAsm->pR700Shader->uStackSize = ((pAsm->CALLSTACK[0].max + 3)>>2) + 2; + } + plstCFmain = pAsm->CALLSTACK[0].plstCFInstructions_local; unCFoffset = plstCFmain->uNumOfNode; @@ -6411,37 +6517,6 @@ GLboolean RelocProgram(r700_AssemblerBase * pAsm) = pAsm->subs[pAsm->callers[i].subDescIndex].unCFoffset; } - /* remove flags init if they are not used */ - if((pAsm->unCFflags & HAS_LOOPRET) == 0) - { - R700ControlFlowALUClause * pCF_ALU; - pInst = plstCFmain->pHead; - while(pInst) - { - if(SIT_CF_ALU == pInst->m_ShaderInstType) - { - pCF_ALU = (R700ControlFlowALUClause *)pInst; - if(1 == pCF_ALU->m_Word1.f.count) - { - pCF_ALU->m_Word1.f.cf_inst = SQ_CF_INST_NOP; - } - else - { - R700ALUInstruction * pALU = pCF_ALU->m_pLinkedALUInstruction; - - pALU->m_pLinkedALUClause = NULL; - pALU = (R700ALUInstruction *)(pALU->pNextInst); - pALU->m_pLinkedALUClause = pCF_ALU; - pCF_ALU->m_pLinkedALUInstruction = pALU; - - pCF_ALU->m_Word1.f.count--; - } - break; - } - pInst = pInst->pNextInst; - }; - } - return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index ca562d29f1..7efb346fa7 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -273,27 +273,27 @@ enum typedef struct FC_LEVEL { - R700ControlFlowGenericClause * first; + R700ControlFlowGenericClause * first; R700ControlFlowGenericClause ** mid; unsigned int unNumMid; - unsigned int midLen; - unsigned int type; - unsigned int cond; - unsigned int inv; - unsigned int bpush; ///< 1 if first instruction does branch stack push - int id; ///< id of bool or int variable + unsigned int midLen; + unsigned int type; + unsigned int cond; + unsigned int inv; + int id; ///< id of bool or int variable } FC_LEVEL; typedef struct VTX_FETCH_METHOD { - GLboolean bEnableMini; - GLuint mega_fetch_remainder; + GLboolean bEnableMini; + GLuint mega_fetch_remainder; } VTX_FETCH_METHOD; typedef struct SUB_OFFSET { GLint subIL_Offset; GLuint unCFoffset; + GLuint unStackDepthMax; TypedShaderList lstCFInstructions_local; } SUB_OFFSET; @@ -306,23 +306,12 @@ typedef struct CALLER_POINTER #define SQ_MAX_CALL_DEPTH 0x00000020 -typedef struct STACK_USAGE -{ - BITS pushs :8; - BITS current :8; - BITS max :8; -} STACK_USAGE; - -typedef union STACKDWORDtag -{ - BITS bits; - STACK_USAGE su; -} STACKDWORD; - typedef struct CALL_LEVEL { unsigned int FCSP_BeforeEntry; - STACKDWORD stackUsage; + GLint subDescIndex; + GLushort current; + GLushort max; TypedShaderList * plstCFInstructions_local; } CALL_LEVEL; @@ -386,9 +375,6 @@ typedef struct r700_AssemblerBase unsigned int FCSP; FC_LEVEL fc_stack[32]; - unsigned int branch_depth; - unsigned int max_branch_depth; - //----------------------------------------------------------------------------------- // ArgSubst used in Assemble_Source() function //----------------------------------------------------------------------------------- @@ -449,7 +435,8 @@ typedef struct r700_AssemblerBase } r700_AssemblerBase; //Internal use -inline void checkStackDepth(r700_AssemblerBase *pAsm, GLuint uReason); +inline void checkStackDepth(r700_AssemblerBase *pAsm, GLuint uReason, GLboolean bCheckMaxOnly); +inline void decreaseCurrent(r700_AssemblerBase *pAsm, GLuint uReason); BITS addrmode_PVSDST(PVSDST * pPVSDST); void setaddrmode_PVSDST(PVSDST * pPVSDST, BITS addrmode); void nomask_PVSDST(PVSDST * pPVSDST); diff --git a/src/mesa/drivers/dri/r600/r700_shader.c b/src/mesa/drivers/dri/r600/r700_shader.c index db951e48c4..2eed1acc2f 100644 --- a/src/mesa/drivers/dri/r600/r700_shader.c +++ b/src/mesa/drivers/dri/r600/r700_shader.c @@ -140,7 +140,7 @@ void Init_R700_Shader(R700_Shader * pShader) pShader->killIsUsed = GL_FALSE; pShader->uCFOffset = 0; - pShader->uStackSize = 10; //richard test + pShader->uStackSize = 0; pShader->uMaxCallDepth = 0; pShader->bSurfAllocated = GL_FALSE; -- cgit v1.2.3 From f9b0f1dfa1695db79553f67fd0c156d445062ffa Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 23 Nov 2009 06:31:29 +1000 Subject: r600: fix inline issues --- src/mesa/drivers/dri/r600/r700_assembler.c | 4 ++-- src/mesa/drivers/dri/r600/r700_assembler.h | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 16cdb741ae..c46dd757d0 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -4976,7 +4976,7 @@ GLboolean assemble_EXPORT(r700_AssemblerBase *pAsm) return GL_TRUE; } -inline void decreaseCurrent(r700_AssemblerBase *pAsm, GLuint uReason) +static inline void decreaseCurrent(r700_AssemblerBase *pAsm, GLuint uReason) { switch (uReason) { @@ -4996,7 +4996,7 @@ inline void decreaseCurrent(r700_AssemblerBase *pAsm, GLuint uReason) }; } -inline void checkStackDepth(r700_AssemblerBase *pAsm, GLuint uReason, GLboolean bCheckMaxOnly) +static inline void checkStackDepth(r700_AssemblerBase *pAsm, GLuint uReason, GLboolean bCheckMaxOnly) { if(GL_TRUE == bCheckMaxOnly) { diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index 7efb346fa7..3e4106335a 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -435,8 +435,6 @@ typedef struct r700_AssemblerBase } r700_AssemblerBase; //Internal use -inline void checkStackDepth(r700_AssemblerBase *pAsm, GLuint uReason, GLboolean bCheckMaxOnly); -inline void decreaseCurrent(r700_AssemblerBase *pAsm, GLuint uReason); BITS addrmode_PVSDST(PVSDST * pPVSDST); void setaddrmode_PVSDST(PVSDST * pPVSDST, BITS addrmode); void nomask_PVSDST(PVSDST * pPVSDST); -- cgit v1.2.3 From c3c8c40cab193e0aa0f1a42bff7b0d726df8cf9f Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 23 Nov 2009 06:44:29 +1000 Subject: r600: hopefully fix segfault. --- src/mesa/drivers/dri/r600/r700_assembler.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index c46dd757d0..702add9772 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -6421,6 +6421,8 @@ GLboolean RelocProgram(r700_AssemblerBase * pAsm) R700ShaderInstruction * pInst; R700ControlFlowGenericClause * pCFInst; + plstCFmain = pAsm->CALLSTACK[0].plstCFInstructions_local; + /* remove flags init if they are not used */ if((pAsm->unCFflags & HAS_LOOPRET) == 0) { @@ -6462,7 +6464,6 @@ GLboolean RelocProgram(r700_AssemblerBase * pAsm) pAsm->pR700Shader->uStackSize = ((pAsm->CALLSTACK[0].max + 3)>>2) + 2; } - plstCFmain = pAsm->CALLSTACK[0].plstCFInstructions_local; unCFoffset = plstCFmain->uNumOfNode; /* Reloc subs */ -- cgit v1.2.3 From a12b468d002edb6c8a7c95882edd3e5e7f615a4e Mon Sep 17 00:00:00 2001 From: Richard Li Date: Sun, 22 Nov 2009 21:31:46 -0500 Subject: r600 : add support for shader instruction trunc and discard. --- src/mesa/drivers/dri/r600/r700_assembler.c | 105 +++++++++++++++++++++-------- src/mesa/drivers/dri/r600/r700_assembler.h | 2 +- 2 files changed, 78 insertions(+), 29 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 702add9772..8e57396a0d 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -340,7 +340,10 @@ unsigned int r700GetNumOperands(r700_AssemblerBase* pAsm) switch (pAsm->D.dst.opcode) { case SQ_OP2_INST_ADD: + case SQ_OP2_INST_KILLE: case SQ_OP2_INST_KILLGT: + case SQ_OP2_INST_KILLGE: + case SQ_OP2_INST_KILLNE: case SQ_OP2_INST_MUL: case SQ_OP2_INST_MAX: case SQ_OP2_INST_MIN: @@ -363,6 +366,7 @@ unsigned int r700GetNumOperands(r700_AssemblerBase* pAsm) case SQ_OP2_INST_MOVA_FLOOR: case SQ_OP2_INST_FRACT: case SQ_OP2_INST_FLOOR: + case SQ_OP2_INST_TRUNC: case SQ_OP2_INST_EXP_IEEE: case SQ_OP2_INST_LOG_CLAMPED: case SQ_OP2_INST_LOG_IEEE: @@ -1379,19 +1383,16 @@ GLboolean tex_src(r700_AssemblerBase *pAsm) case FRAG_ATTRIB_PNTC: fprintf(stderr, "FRAG_ATTRIB_PNTC unsupported\n"); break; - case FRAG_ATTRIB_VAR0: - fprintf(stderr, "FRAG_ATTRIB_VAR0 unsupported\n"); - break; } if( (pILInst->SrcReg[0].Index >= FRAG_ATTRIB_VAR0) || - (pILInst->SrcReg[0].Index < FRAG_ATTRIB_MAX) ) - { + (pILInst->SrcReg[0].Index < FRAG_ATTRIB_MAX) ) + { bValidTexCoord = GL_TRUE; pAsm->S[0].src.reg = pAsm->uiFP_AttributeMap[pILInst->SrcReg[0].Index]; pAsm->S[0].src.rtype = SRC_REG_INPUT; - } + } break; } @@ -2469,9 +2470,9 @@ GLboolean assemble_alu_instruction2(r700_AssemblerBase *pAsm) { R700ALUInstruction* alu_instruction_ptr = (R700ALUInstruction*) CALLOC_STRUCT(R700ALUInstruction); if (alu_instruction_ptr == NULL) - { - return GL_FALSE; - } + { + return GL_FALSE; + } Init_R700ALUInstruction(alu_instruction_ptr); //src 0 @@ -3545,13 +3546,12 @@ GLboolean assemble_FRC(r700_AssemblerBase *pAsm) return GL_TRUE; } -GLboolean assemble_KIL(r700_AssemblerBase *pAsm) -{ - /* TODO: doc says KILL has to be last(end) ALU clause */ - - checkop1(pAsm); +GLboolean assemble_KIL(r700_AssemblerBase *pAsm, GLuint opcode) +{ + checkop2(pAsm); - pAsm->D.dst.opcode = SQ_OP2_INST_KILLGT; + pAsm->D.dst.opcode = opcode; + pAsm->D.dst.math = 1; setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); pAsm->D.dst.rtype = DST_REG_TEMPORARY; @@ -3561,24 +3561,24 @@ GLboolean assemble_KIL(r700_AssemblerBase *pAsm) pAsm->D.dst.writez = 0; pAsm->D.dst.writew = 0; - setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); - pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; - pAsm->S[0].src.reg = 0; - - setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_0); - noneg_PVSSRC(&(pAsm->S[0].src)); + if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + { + return GL_FALSE; + } - if ( GL_FALSE == assemble_src(pAsm, 0, 1) ) + if( GL_FALSE == assemble_src(pAsm, 1, -1) ) { return GL_FALSE; } - if ( GL_FALSE == next_ins(pAsm) ) + if ( GL_FALSE == next_ins2(pAsm) ) { return GL_FALSE; } + /* Doc says KILL has to be last(end) ALU clause */ pAsm->pR700Shader->killIsUsed = GL_TRUE; + pAsm->alu_x_opcode = SQ_CF_INST_ALU; return GL_TRUE; } @@ -5018,7 +5018,7 @@ static inline void checkStackDepth(r700_AssemblerBase *pAsm, GLuint uReason, GLb pAsm->CALLSTACK[pAsm->CALLSP].current + 4; } break; - } + } return; } @@ -5102,7 +5102,7 @@ GLboolean assemble_IF(r700_AssemblerBase *pAsm, GLboolean bHasElse) if(GL_TRUE != bHasElse) { - pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 1; + pAsm->cf_current_cf_clause_ptr->m_Word1.f.pop_count = 1; } else { @@ -5172,7 +5172,7 @@ GLboolean assemble_ELSE(r700_AssemblerBase *pAsm) GLboolean assemble_ENDIF(r700_AssemblerBase *pAsm) { #ifdef USE_CF_FOR_POP_AFTER - pops(pAsm, 1); + pops(pAsm, 1); #endif /* USE_CF_FOR_POP_AFTER */ pAsm->alu_x_opcode = SQ_CF_INST_ALU; @@ -5912,8 +5912,10 @@ GLboolean AssembleInstr(GLuint uiFirstInst, break; case OPCODE_KIL: - if ( GL_FALSE == assemble_KIL(pR700AsmCode) ) - return GL_FALSE; + case OPCODE_KIL_NV: + /* done at OPCODE_SE/SGT...etc. */ + /* if ( GL_FALSE == assemble_KIL(pR700AsmCode) ) + return GL_FALSE; */ break; case OPCODE_LG2: if ( GL_FALSE == assemble_LG2(pR700AsmCode) ) @@ -6008,6 +6010,13 @@ GLboolean AssembleInstr(GLuint uiFirstInst, return GL_FALSE; } } + else if((OPCODE_KIL == pILInst[i+1].Opcode)||(OPCODE_KIL_NV == pILInst[i+1].Opcode)) + { + if ( GL_FALSE == assemble_KIL(pR700AsmCode, SQ_OP2_INST_KILLE) ) + { + return GL_FALSE; + } + } else { if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETE) ) @@ -6051,6 +6060,13 @@ GLboolean AssembleInstr(GLuint uiFirstInst, return GL_FALSE; } } + else if((OPCODE_KIL == pILInst[i+1].Opcode)||(OPCODE_KIL_NV == pILInst[i+1].Opcode)) + { + if ( GL_FALSE == assemble_KIL(pR700AsmCode, SQ_OP2_INST_KILLGT) ) + { + return GL_FALSE; + } + } else { if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETGT) ) @@ -6094,6 +6110,13 @@ GLboolean AssembleInstr(GLuint uiFirstInst, return GL_FALSE; } } + else if((OPCODE_KIL == pILInst[i+1].Opcode)||(OPCODE_KIL_NV == pILInst[i+1].Opcode)) + { + if ( GL_FALSE == assemble_KIL(pR700AsmCode, SQ_OP2_INST_KILLGE) ) + { + return GL_FALSE; + } + } else { if ( GL_FALSE == assemble_SGE(pR700AsmCode) ) @@ -6150,6 +6173,13 @@ GLboolean AssembleInstr(GLuint uiFirstInst, return GL_FALSE; } } + else if((OPCODE_KIL == pILInst[i+1].Opcode)||(OPCODE_KIL_NV == pILInst[i+1].Opcode)) + { + if ( GL_FALSE == assemble_KIL(pR700AsmCode, SQ_OP2_INST_KILLGT) ) + { + return GL_FALSE; + } + } else { if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETGT) ) @@ -6210,6 +6240,13 @@ GLboolean AssembleInstr(GLuint uiFirstInst, return GL_FALSE; } } + else if((OPCODE_KIL == pILInst[i+1].Opcode)||(OPCODE_KIL_NV == pILInst[i+1].Opcode)) + { + if ( GL_FALSE == assemble_KIL(pR700AsmCode, SQ_OP2_INST_KILLGE) ) + { + return GL_FALSE; + } + } else { if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETGE) ) @@ -6257,6 +6294,13 @@ GLboolean AssembleInstr(GLuint uiFirstInst, return GL_FALSE; } } + else if((OPCODE_KIL == pILInst[i+1].Opcode)||(OPCODE_KIL_NV == pILInst[i+1].Opcode)) + { + if ( GL_FALSE == assemble_KIL(pR700AsmCode, SQ_OP2_INST_KILLNE) ) + { + return GL_FALSE; + } + } else { if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETNE) ) @@ -6298,6 +6342,11 @@ GLboolean AssembleInstr(GLuint uiFirstInst, return GL_FALSE; break; + case OPCODE_TRUNC: + if ( GL_FALSE == assemble_math_function(pR700AsmCode, SQ_OP2_INST_TRUNC) ) + return GL_FALSE; + break; + case OPCODE_XPD: if ( GL_FALSE == assemble_XPD(pR700AsmCode) ) return GL_FALSE; diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index 3e4106335a..130fc89dae 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -554,7 +554,7 @@ GLboolean assemble_EXP(r700_AssemblerBase *pAsm); GLboolean assemble_FLR(r700_AssemblerBase *pAsm); GLboolean assemble_FLR_INT(r700_AssemblerBase *pAsm); GLboolean assemble_FRC(r700_AssemblerBase *pAsm); -GLboolean assemble_KIL(r700_AssemblerBase *pAsm); +GLboolean assemble_KIL(r700_AssemblerBase *pAsm, GLuint opcode); GLboolean assemble_LG2(r700_AssemblerBase *pAsm); GLboolean assemble_LRP(r700_AssemblerBase *pAsm); GLboolean assemble_LOG(r700_AssemblerBase *pAsm); -- cgit v1.2.3 From bd13e6e5e2403ada2098e3a07c0af4b4ba989ab7 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 24 Nov 2009 10:49:34 +1000 Subject: radeon/r200/r300/r600: make bo mapping be explicit This moves the bo mapping outside the DMA layer and makes it explicit, this should in theory make it simpler to split the clean up the dma/cmdbuf linkage that I created before that is broken. Tested on: r600, rv380 (tcl/no-tcl), rv200 (tcl/no-tcl) Signed-off-by: Dave Airlie --- src/mesa/drivers/dri/r200/r200_maos_arrays.c | 2 ++ src/mesa/drivers/dri/r200/r200_swtcl.c | 2 +- src/mesa/drivers/dri/r300/r300_draw.c | 15 ++++++++++++-- src/mesa/drivers/dri/r300/r300_swtcl.c | 8 ++++---- src/mesa/drivers/dri/r600/r700_render.c | 21 ++++++++++++++++++- .../drivers/dri/radeon/radeon_common_context.h | 1 + src/mesa/drivers/dri/radeon/radeon_dma.c | 24 +++++++++++----------- src/mesa/drivers/dri/radeon/radeon_maos_arrays.c | 4 ++++ src/mesa/drivers/dri/radeon/radeon_maos_verts.c | 4 ++-- src/mesa/drivers/dri/radeon/radeon_swtcl.c | 2 +- 10 files changed, 60 insertions(+), 23 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c index 383a0c4b0d..249c0bbc11 100644 --- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c +++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c @@ -90,12 +90,14 @@ static void r200_emit_vecfog(GLcontext *ctx, struct radeon_aos *aos, aos->components = size; aos->count = count; + radeon_bo_map(aos->bo, 1); out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); for (i = 0; i < count; i++) { out[0] = r200ComputeFogBlendFactor( ctx, *(GLfloat *)data ); out++; data += stride; } + radeon_bo_unmap(aos->bo); } /* Emit any changed arrays to new GART memory, re-emit a packet to diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c index fadc766b49..4596912ddc 100644 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ b/src/mesa/drivers/dri/r200/r200_swtcl.c @@ -297,7 +297,7 @@ void r200_swtcl_flush(GLcontext *ctx, uint32_t current_offset) radeonEmitState(&rmesa->radeon); r200EmitVertexAOS( rmesa, rmesa->radeon.swtcl.vertex_size, - first_elem(&rmesa->radeon.dma.reserved)->bo, + rmesa->radeon.swtcl.bo, current_offset); diff --git a/src/mesa/drivers/dri/r300/r300_draw.c b/src/mesa/drivers/dri/r300/r300_draw.c index e9968f9ffe..3dcd986e22 100644 --- a/src/mesa/drivers/dri/r300/r300_draw.c +++ b/src/mesa/drivers/dri/r300/r300_draw.c @@ -100,7 +100,7 @@ static void r300FixupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer GLubyte *in = (GLubyte *)src_ptr; radeonAllocDmaRegion(&r300->radeon, &r300->ind_buf.bo, &r300->ind_buf.bo_offset, size, 4); - + radeon_bo_map(r300->ind_buf.bo, 1); assert(r300->ind_buf.bo->ptr != NULL); out = (GLuint *)ADD_POINTERS(r300->ind_buf.bo->ptr, r300->ind_buf.bo_offset); @@ -111,7 +111,7 @@ static void r300FixupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer if (i < mesa_ind_buf->count) { *out++ = in[i]; } - + radeon_bo_unmap(r300->ind_buf.bo); #if MESA_BIG_ENDIAN } else { /* if (mesa_ind_buf->type == GL_UNSIGNED_SHORT) */ GLushort *in = (GLushort *)src_ptr; @@ -120,6 +120,7 @@ static void r300FixupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer radeonAllocDmaRegion(&r300->radeon, &r300->ind_buf.bo, &r300->ind_buf.bo_offset, size, 4); + radeon_bo_map(r300->ind_buf.bo, 1); assert(r300->ind_buf.bo->ptr != NULL); out = (GLuint *)ADD_POINTERS(r300->ind_buf.bo->ptr, r300->ind_buf.bo_offset); @@ -130,6 +131,7 @@ static void r300FixupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer if (i < mesa_ind_buf->count) { *out++ = in[i]; } + radeon_bo_unmap(r300->ind_buf.bo); #endif } @@ -173,10 +175,12 @@ static void r300SetupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer radeonAllocDmaRegion(&r300->radeon, &r300->ind_buf.bo, &r300->ind_buf.bo_offset, size, 4); + radeon_bo_map(r300->ind_buf.bo, 1); assert(r300->ind_buf.bo->ptr != NULL); dst_ptr = ADD_POINTERS(r300->ind_buf.bo->ptr, r300->ind_buf.bo_offset); _mesa_memcpy(dst_ptr, src_ptr, size); + radeon_bo_unmap(r300->ind_buf.bo); r300->ind_buf.is_32bit = (mesa_ind_buf->type == GL_UNSIGNED_INT); r300->ind_buf.count = mesa_ind_buf->count; @@ -242,6 +246,7 @@ static void r300ConvertAttrib(GLcontext *ctx, int count, const struct gl_client_ } radeonAllocDmaRegion(&r300->radeon, &attr->bo, &attr->bo_offset, sizeof(GLfloat) * input->Size * count, 32); + radeon_bo_map(attr->bo, 1); dst_ptr = (GLfloat *)ADD_POINTERS(attr->bo->ptr, attr->bo_offset); radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT, @@ -280,6 +285,7 @@ static void r300ConvertAttrib(GLcontext *ctx, int count, const struct gl_client_ break; } + radeon_bo_unmap(attr->bo); if (mapped_named_bo) { ctx->Driver.UnmapBuffer(ctx, GL_ARRAY_BUFFER, input->BufferObj); } @@ -294,6 +300,8 @@ static void r300AlignDataToDword(GLcontext *ctx, const struct gl_client_array *i radeonAllocDmaRegion(&r300->radeon, &attr->bo, &attr->bo_offset, size, 32); + radeon_bo_map(attr->bo, 1); + if (!input->BufferObj->Pointer) { ctx->Driver.MapBuffer(ctx, GL_ARRAY_BUFFER, GL_READ_ONLY_ARB, input->BufferObj); mapped_named_bo = GL_TRUE; @@ -317,6 +325,7 @@ static void r300AlignDataToDword(GLcontext *ctx, const struct gl_client_array *i ctx->Driver.UnmapBuffer(ctx, GL_ARRAY_BUFFER, input->BufferObj); } + radeon_bo_unmap(attr->bo); attr->stride = dst_stride; } @@ -527,6 +536,7 @@ static void r300AllocDmaRegions(GLcontext *ctx, const struct gl_client_array *in } radeonAllocDmaRegion(&r300->radeon, &vbuf->attribs[index].bo, &vbuf->attribs[index].bo_offset, size, 32); + radeon_bo_map(vbuf->attribs[index].bo, 1); assert(vbuf->attribs[index].bo->ptr != NULL); dst = (uint32_t *)ADD_POINTERS(vbuf->attribs[index].bo->ptr, vbuf->attribs[index].bo_offset); switch (vbuf->attribs[index].dwords) { @@ -536,6 +546,7 @@ static void r300AllocDmaRegions(GLcontext *ctx, const struct gl_client_array *in case 4: radeonEmitVec16(dst, input[i]->Ptr, input[i]->StrideB, local_count); break; default: assert(0); break; } + radeon_bo_unmap(vbuf->attribs[index].bo); } } diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 99bd22edac..383c8a274b 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -665,11 +665,11 @@ void r300_swtcl_flush(GLcontext *ctx, uint32_t current_offset) r300EmitCacheFlush(rmesa); radeonEmitState(&rmesa->radeon); - r300_emit_scissor(ctx); + r300_emit_scissor(ctx); r300EmitVertexAOS(rmesa, - rmesa->radeon.swtcl.vertex_size, - first_elem(&rmesa->radeon.dma.reserved)->bo, - current_offset); + rmesa->radeon.swtcl.vertex_size, + rmesa->radeon.swtcl.bo, + current_offset); r300EmitVbufPrim(rmesa, rmesa->radeon.swtcl.hw_primitive, diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 47f89c91f8..eab27cbd84 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -526,6 +526,9 @@ static void r700ConvertAttrib(GLcontext *ctx, int count, radeonAllocDmaRegion(&context->radeon, &attr->bo, &attr->bo_offset, sizeof(GLfloat) * input->Size * count, 32); + + radeon_bo_map(attr->bo, 1); + dst_ptr = (GLfloat *)ADD_POINTERS(attr->bo->ptr, attr->bo_offset); assert(src_ptr != NULL); @@ -559,6 +562,8 @@ static void r700ConvertAttrib(GLcontext *ctx, int count, break; } + radeon_bo_unmap(attr->bo); + if (mapped_named_bo) { ctx->Driver.UnmapBuffer(ctx, GL_ARRAY_BUFFER, input->BufferObj); @@ -577,6 +582,8 @@ static void r700AlignDataToDword(GLcontext *ctx, radeonAllocDmaRegion(&context->radeon, &attr->bo, &attr->bo_offset, size, 32); + radeon_bo_map(attr->bo, 1); + if (!input->BufferObj->Pointer) { ctx->Driver.MapBuffer(ctx, GL_ARRAY_BUFFER, GL_READ_ONLY_ARB, input->BufferObj); @@ -596,6 +603,7 @@ static void r700AlignDataToDword(GLcontext *ctx, } } + radeon_bo_unmap(attr->bo); if (mapped_named_bo) { ctx->Driver.UnmapBuffer(ctx, GL_ARRAY_BUFFER, input->BufferObj); @@ -664,14 +672,18 @@ static void r700SetupStreams(GLcontext *ctx, const struct gl_client_array *input radeonAllocDmaRegion(&context->radeon, &context->stream_desc[index].bo, &context->stream_desc[index].bo_offset, size, 32); + + radeon_bo_map(context->stream_desc[index].bo, 1); assert(context->stream_desc[index].bo->ptr != NULL); + + dst = (uint32_t *)ADD_POINTERS(context->stream_desc[index].bo->ptr, context->stream_desc[index].bo_offset); switch (context->stream_desc[index].dwords) { case 1: - radeonEmitVec4(dst, input[i]->Ptr, input[i]->StrideB, local_count); + radeonEmitVec4(dst, input[i]->Ptr, input[i]->StrideB, local_count); break; case 2: radeonEmitVec8(dst, input[i]->Ptr, input[i]->StrideB, local_count); @@ -686,6 +698,7 @@ static void r700SetupStreams(GLcontext *ctx, const struct gl_client_array *input assert(0); break; } + radeon_bo_unmap(context->stream_desc[index].bo); } } @@ -757,6 +770,7 @@ static void r700FixupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo, &context->ind_buf.bo_offset, size, 4); + radeon_bo_map(context->ind_buf.bo, 1); assert(context->ind_buf.bo->ptr != NULL); out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset); @@ -770,6 +784,7 @@ static void r700FixupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer *out++ = in[i]; } + radeon_bo_unmap(context->ind_buf.bo); #if MESA_BIG_ENDIAN } else @@ -780,6 +795,7 @@ static void r700FixupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo, &context->ind_buf.bo_offset, size, 4); + radeon_bo_map(context->ind_buf.bo, 1); assert(context->ind_buf.bo->ptr != NULL); out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset); @@ -792,6 +808,7 @@ static void r700FixupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer { *out++ = in[i]; } + radeon_bo_unmap(context->ind_buf.bo); #endif } @@ -837,11 +854,13 @@ static void r700SetupIndexBuffer(GLcontext *ctx, const struct _mesa_index_buffer radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo, &context->ind_buf.bo_offset, size, 4); + radeon_bo_map(context->ind_buf.bo, 1); assert(context->ind_buf.bo->ptr != NULL); dst_ptr = ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset); _mesa_memcpy(dst_ptr, src_ptr, size); + radeon_bo_unmap(context->ind_buf.bo); context->ind_buf.is_32bit = (mesa_ind_buf->type == GL_UNSIGNED_INT); context->ind_buf.count = mesa_ind_buf->count; diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index ded81fff29..ad953ddbb5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -328,6 +328,7 @@ struct radeon_swtcl_info { GLuint vertex_attr_count; GLuint emit_prediction; + struct radeon_bo *bo; }; #define RADEON_MAX_AOS_ARRAYS 16 diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c index c6edbae9a1..2a1bd7357a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_dma.c +++ b/src/mesa/drivers/dri/radeon/radeon_dma.c @@ -151,6 +151,7 @@ void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, aos->components = size; aos->count = count; + radeon_bo_map(aos->bo, 1); out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); switch (size) { case 1: radeonEmitVec4(out, data, stride, count); break; @@ -161,6 +162,7 @@ void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, assert(0); break; } + radeon_bo_unmap(aos->bo); } void radeon_init_dma(radeonContextPtr rmesa) @@ -183,10 +185,6 @@ void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size) __FUNCTION__, size, rmesa->dma.minimum_size); - /* unmap old reserved bo */ - if (!is_empty_list(&rmesa->dma.reserved)) - radeon_bo_unmap(first_elem(&rmesa->dma.reserved)->bo); - if (is_empty_list(&rmesa->dma.free) || last_elem(&rmesa->dma.free)->bo->size < size) { dma_bo = CALLOC_STRUCT(radeon_dma_bo); @@ -223,8 +221,6 @@ again_alloc: /* Cmd buff have been flushed in radeon_revalidate_bos */ goto again_alloc; } - - radeon_bo_map(first_elem(&rmesa->dma.reserved)->bo, 1); } /* Allocates a region from rmesa->dma.current. If there isn't enough @@ -281,7 +277,6 @@ void radeonFreeDmaRegions(radeonContextPtr rmesa) foreach_s(dma_bo, temp, &rmesa->dma.reserved) { remove_from_list(dma_bo); - radeon_bo_unmap(dma_bo->bo); radeon_bo_unref(dma_bo->bo); FREE(dma_bo); } @@ -367,9 +362,6 @@ void radeonReleaseDmaRegions(radeonContextPtr rmesa) insert_at_tail(&rmesa->dma.free, dma_bo); } - /* unmap the last dma region */ - if (!is_empty_list(&rmesa->dma.reserved)) - radeon_bo_unmap(first_elem(&rmesa->dma.reserved)->bo); /* move reserved to wait list */ foreach_s(dma_bo, temp, &rmesa->dma.reserved) { /* free objects that are too small to be used because of large request */ @@ -403,11 +395,12 @@ void rcommon_flush_last_swtcl_prim( GLcontext *ctx ) radeonContextPtr rmesa = RADEON_CONTEXT(ctx); struct radeon_dma *dma = &rmesa->dma; - if (RADEON_DEBUG & RADEON_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); dma->flush = NULL; + radeon_bo_unmap(rmesa->swtcl.bo); + if (!is_empty_list(&dma->reserved)) { GLuint current_offset = dma->current_used; @@ -422,6 +415,8 @@ void rcommon_flush_last_swtcl_prim( GLcontext *ctx ) } rmesa->swtcl.numverts = 0; } + radeon_bo_unref(rmesa->swtcl.bo); + rmesa->swtcl.bo = NULL; } /* Alloc space in the current dma region. */ @@ -432,6 +427,7 @@ rcommonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize ) void *head; if (RADEON_DEBUG & RADEON_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); + if(is_empty_list(&rmesa->dma.reserved) ||rmesa->dma.current_vertexptr + bytes > first_elem(&rmesa->dma.reserved)->bo->size) { if (rmesa->dma.flush) { @@ -455,7 +451,11 @@ rcommonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize ) rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == rmesa->dma.current_vertexptr ); - head = (first_elem(&rmesa->dma.reserved)->bo->ptr + rmesa->dma.current_vertexptr); + rmesa->swtcl.bo = first_elem(&rmesa->dma.reserved)->bo; + radeon_bo_ref(rmesa->swtcl.bo); + radeon_bo_map(rmesa->swtcl.bo, 1); + + head = (rmesa->swtcl.bo->ptr + rmesa->dma.current_vertexptr); rmesa->dma.current_vertexptr += bytes; rmesa->swtcl.numverts += nverts; return head; diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c index de18d2ddd6..d810e6080e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c +++ b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c @@ -76,12 +76,14 @@ static void emit_vecfog(GLcontext *ctx, struct radeon_aos *aos, /* Emit the data */ + radeon_bo_map(aos->bo, 1); out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); for (i = 0; i < count; i++) { out[0] = radeonComputeFogBlendFactor( ctx, *(GLfloat *)data ); out++; data += stride; } + radeon_bo_unmap(aos->bo); } static void emit_s0_vec(uint32_t *out, GLvoid *data, int stride, int count) @@ -151,6 +153,7 @@ static void emit_tex_vector(GLcontext *ctx, struct radeon_aos *aos, /* Emit the data */ + radeon_bo_map(aos->bo, 1); out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); switch (size) { case 1: @@ -170,6 +173,7 @@ static void emit_tex_vector(GLcontext *ctx, struct radeon_aos *aos, exit(1); break; } + radeon_bo_unmap(aos->bo); } diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c index 5ed11d0a9d..98f96ff2a7 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c +++ b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c @@ -420,10 +420,10 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) } - + radeon_bo_map(rmesa->radeon.tcl.aos[0].bo, 1); setup_tab[i].emit( ctx, 0, VB->Count, rmesa->radeon.tcl.aos[0].bo->ptr + rmesa->radeon.tcl.aos[0].offset); - + radeon_bo_unmap(rmesa->radeon.tcl.aos[0].bo); // rmesa->radeon.tcl.aos[0].size = setup_tab[i].vertex_size; rmesa->radeon.tcl.aos[0].stride = setup_tab[i].vertex_size; rmesa->tcl.vertex_format = setup_tab[i].vertex_format; diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c b/src/mesa/drivers/dri/radeon/radeon_swtcl.c index 6bbe8e252e..8bf1bfbc57 100644 --- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c @@ -309,7 +309,7 @@ void r100_swtcl_flush(GLcontext *ctx, uint32_t current_offset) radeonEmitState(&rmesa->radeon); radeonEmitVertexAOS( rmesa, rmesa->radeon.swtcl.vertex_size, - first_elem(&rmesa->radeon.dma.reserved)->bo, + rmesa->radeon.swtcl.bo, current_offset); -- cgit v1.2.3 From d4c2f53ca56beb8fe9289fb17c3f5fcc2cc7dc10 Mon Sep 17 00:00:00 2001 From: Richard Li Date: Tue, 24 Nov 2009 12:16:39 -0500 Subject: r600 : fix stack depth setting bug. --- src/mesa/drivers/dri/r600/r700_assembler.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 8e57396a0d..0c16594adc 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -6503,14 +6503,14 @@ GLboolean RelocProgram(r700_AssemblerBase * pAsm) }; } - if(0 == pAsm->unSubArrayPointer) + if(pAsm->CALLSTACK[0].max > 0) { - return GL_TRUE; + pAsm->pR700Shader->uStackSize = ((pAsm->CALLSTACK[0].max + 3)>>2) + 2; } - if(pAsm->CALLSTACK[0].max > 0) + if(0 == pAsm->unSubArrayPointer) { - pAsm->pR700Shader->uStackSize = ((pAsm->CALLSTACK[0].max + 3)>>2) + 2; + return GL_TRUE; } unCFoffset = plstCFmain->uNumOfNode; -- cgit v1.2.3 From 11dce740305ea3f45966a9e9f72ba94b4eae6d40 Mon Sep 17 00:00:00 2001 From: Richard Li Date: Tue, 24 Nov 2009 16:00:25 -0500 Subject: r600 : reset stack flag with one channel only. --- src/mesa/drivers/dri/r600/r700_assembler.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 0c16594adc..ba97d3e073 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -5663,6 +5663,8 @@ GLboolean setRetInLoopFlag(r700_AssemblerBase *pAsm, GLuint flagValue) pAsm->D2.dst2.literal = 1; pAsm->D2.dst2.SaturateMode = SATURATE_OFF; pAsm->D.dst.predicated = 0; + /* in reloc where dislink flag init inst, only one slot alu inst is handled. */ + pAsm->D.dst.math = 1; /* TODO : not math really, but one channel op, more generic alu assembler needed */ #if 0 pAsm->S[0].src.rtype = SRC_REC_LITERAL; //pAsm->S[0].src.reg = 0; @@ -6457,6 +6459,7 @@ GLboolean AssembleInstr(GLuint uiFirstInst, GLboolean InitShaderProgram(r700_AssemblerBase * pAsm) { setRetInLoopFlag(pAsm, SQ_SEL_0); + pAsm->alu_x_opcode = SQ_CF_INST_ALU; return GL_TRUE; } @@ -6482,7 +6485,7 @@ GLboolean RelocProgram(r700_AssemblerBase * pAsm) if(SIT_CF_ALU == pInst->m_ShaderInstType) { pCF_ALU = (R700ControlFlowALUClause *)pInst; - if(1 == pCF_ALU->m_Word1.f.count) + if(0 == pCF_ALU->m_Word1.f.count) { pCF_ALU->m_Word1.f.cf_inst = SQ_CF_INST_NOP; } -- cgit v1.2.3 From ce56a867f71d0a74172a00869a3c5cb1862f4b04 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 25 Nov 2009 15:45:31 +1000 Subject: r600: add ARB_texture_non_power_of_two support. This makes the miptree rounds up to the near POT for each level for all radeons, however since mipmaps aren't support with NPOT on previous radeons this calculation shouldn't cause any problems. If it does we can just make it r600 only. I tested a few mipmap demos on r500 and they all seem to work. Signed-off-by: Dave Airlie --- src/mesa/drivers/dri/r600/r600_context.c | 2 +- src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 26 +++++++++++++++++++----- 2 files changed, 22 insertions(+), 6 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 7de29e5bb8..25314eff56 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -111,6 +111,7 @@ static const struct dri_extension card_extensions[] = { {"GL_ARB_texture_env_crossbar", NULL}, {"GL_ARB_texture_env_dot3", NULL}, {"GL_ARB_texture_mirrored_repeat", NULL}, + {"GL_ARB_texture_non_power_of_two", NULL}, {"GL_ARB_vertex_program", GL_ARB_vertex_program_functions}, {"GL_EXT_blend_equation_separate", GL_EXT_blend_equation_separate_functions}, {"GL_EXT_blend_func_separate", GL_EXT_blend_func_separate_functions}, @@ -327,7 +328,6 @@ static void r600InitGLExtensions(GLcontext *ctx) ctx->Extensions.ARB_shader_objects = GL_TRUE; ctx->Extensions.ARB_vertex_shader = GL_TRUE; ctx->Extensions.ARB_fragment_shader = GL_TRUE; - ctx->Extensions.ARB_texture_non_power_of_two = GL_TRUE; ctx->Extensions.EXT_blend_equation_separate = GL_TRUE; ctx->Extensions.ATI_separate_stencil = GL_TRUE; diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index 46603de2e7..f2f7b2a9fd 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -68,6 +68,19 @@ static unsigned get_compressed_image_size( return rowStride * ((height + blockHeight - 1) / blockHeight); } +static int find_next_power_of_two(GLuint value) +{ + int i, tmp; + + i = 0; + tmp = value - 1; + while (tmp) { + tmp >>= 1; + i++; + } + return (1 << i); +} + /** * Compute sizes and fill in offset and blit information for the given * image (determined by \p face and \p level). @@ -80,25 +93,28 @@ static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree { radeon_mipmap_level *lvl = &mt->levels[level]; uint32_t row_align; + GLuint height; + + height = find_next_power_of_two(lvl->height); /* Find image size in bytes */ if (_mesa_is_format_compressed(mt->mesaFormat)) { lvl->rowstride = get_aligned_compressed_row_stride(mt->mesaFormat, lvl->width, rmesa->texture_compressed_row_align); - lvl->size = get_compressed_image_size(mt->mesaFormat, lvl->rowstride, lvl->height); + lvl->size = get_compressed_image_size(mt->mesaFormat, lvl->rowstride, height); } else if (mt->target == GL_TEXTURE_RECTANGLE_NV) { row_align = rmesa->texture_rect_row_align - 1; lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) + row_align) & ~row_align; - lvl->size = lvl->rowstride * lvl->height; + lvl->size = lvl->rowstride * height; } else if (mt->tilebits & RADEON_TXO_MICRO_TILE) { /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned, * though the actual offset may be different (if texture is less than * 32 bytes width) to the untiled case */ lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) * 2 + 31) & ~31; - lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth; + lvl->size = lvl->rowstride * ((height + 1) / 2) * lvl->depth; } else { row_align = rmesa->texture_row_align - 1; lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) + row_align) & ~row_align; - lvl->size = lvl->rowstride * lvl->height * lvl->depth; + lvl->size = lvl->rowstride * height * lvl->depth; } assert(lvl->size > 0); @@ -110,7 +126,7 @@ static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree if (RADEON_DEBUG & RADEON_TEXTURE) fprintf(stderr, "level %d, face %d: rs:%d %dx%d at %d\n", - level, face, lvl->rowstride, lvl->width, lvl->height, lvl->faces[face].offset); + level, face, lvl->rowstride, lvl->width, height, lvl->faces[face].offset); } static GLuint minify(GLuint size, GLuint levels) -- cgit v1.2.3 From 2db72f329f35ee6e12df3ed472de2ee72cf23399 Mon Sep 17 00:00:00 2001 From: Richard Li Date: Sun, 29 Nov 2009 12:12:19 -0500 Subject: r600 : add read port allocation for uniform; mapping ps input based on vs output; fix bugs including constants updating for vs. --- src/mesa/drivers/dri/r600/r700_assembler.c | 46 +++++++++------- src/mesa/drivers/dri/r600/r700_fragprog.c | 85 +++++++++++++++++------------- src/mesa/drivers/dri/r600/r700_fragprog.h | 6 ++- src/mesa/drivers/dri/r600/r700_vertprog.c | 26 +++++++-- 4 files changed, 101 insertions(+), 62 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index ba97d3e073..309c90fdd0 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -1038,7 +1038,8 @@ GLboolean checkop2(r700_AssemblerBase* pAsm) checkop_init(pAsm); - if( (pILInst->SrcReg[0].File == PROGRAM_CONSTANT) || + if( (pILInst->SrcReg[0].File == PROGRAM_UNIFORM) || + (pILInst->SrcReg[0].File == PROGRAM_CONSTANT) || (pILInst->SrcReg[0].File == PROGRAM_LOCAL_PARAM) || (pILInst->SrcReg[0].File == PROGRAM_ENV_PARAM) || (pILInst->SrcReg[0].File == PROGRAM_STATE_VAR) ) @@ -1049,7 +1050,8 @@ GLboolean checkop2(r700_AssemblerBase* pAsm) { bSrcConst[0] = GL_FALSE; } - if( (pILInst->SrcReg[1].File == PROGRAM_CONSTANT) || + if( (pILInst->SrcReg[1].File == PROGRAM_UNIFORM) || + (pILInst->SrcReg[1].File == PROGRAM_CONSTANT) || (pILInst->SrcReg[1].File == PROGRAM_LOCAL_PARAM) || (pILInst->SrcReg[1].File == PROGRAM_ENV_PARAM) || (pILInst->SrcReg[1].File == PROGRAM_STATE_VAR) ) @@ -1082,7 +1084,8 @@ GLboolean checkop3(r700_AssemblerBase* pAsm) checkop_init(pAsm); - if( (pILInst->SrcReg[0].File == PROGRAM_CONSTANT) || + if( (pILInst->SrcReg[0].File == PROGRAM_UNIFORM) || + (pILInst->SrcReg[0].File == PROGRAM_CONSTANT) || (pILInst->SrcReg[0].File == PROGRAM_LOCAL_PARAM) || (pILInst->SrcReg[0].File == PROGRAM_ENV_PARAM) || (pILInst->SrcReg[0].File == PROGRAM_STATE_VAR) ) @@ -1093,7 +1096,8 @@ GLboolean checkop3(r700_AssemblerBase* pAsm) { bSrcConst[0] = GL_FALSE; } - if( (pILInst->SrcReg[1].File == PROGRAM_CONSTANT) || + if( (pILInst->SrcReg[1].File == PROGRAM_UNIFORM) || + (pILInst->SrcReg[1].File == PROGRAM_CONSTANT) || (pILInst->SrcReg[1].File == PROGRAM_LOCAL_PARAM) || (pILInst->SrcReg[1].File == PROGRAM_ENV_PARAM) || (pILInst->SrcReg[1].File == PROGRAM_STATE_VAR) ) @@ -1104,7 +1108,8 @@ GLboolean checkop3(r700_AssemblerBase* pAsm) { bSrcConst[1] = GL_FALSE; } - if( (pILInst->SrcReg[2].File == PROGRAM_CONSTANT) || + if( (pILInst->SrcReg[2].File == PROGRAM_UNIFORM) || + (pILInst->SrcReg[2].File == PROGRAM_CONSTANT) || (pILInst->SrcReg[2].File == PROGRAM_LOCAL_PARAM) || (pILInst->SrcReg[2].File == PROGRAM_ENV_PARAM) || (pILInst->SrcReg[2].File == PROGRAM_STATE_VAR) ) @@ -1218,7 +1223,7 @@ GLboolean assemble_src(r700_AssemblerBase *pAsm, pAsm->S[fld].src.reg = pILInst->SrcReg[src].Index; break; case PROGRAM_INPUT: - setaddrmode_PVSSRC(&(pAsm->S[fld].src), ADDR_ABSOLUTE); + setaddrmode_PVSSRC(&(pAsm->S[fld].src), ADDR_ABSOLUTE); pAsm->S[fld].src.rtype = SRC_REG_INPUT; switch (pAsm->currentShaderType) { @@ -1346,6 +1351,7 @@ GLboolean tex_src(r700_AssemblerBase *pAsm) else { switch (pILInst->SrcReg[0].File) { + case PROGRAM_UNIFORM: case PROGRAM_CONSTANT: case PROGRAM_LOCAL_PARAM: case PROGRAM_ENV_PARAM: @@ -2117,7 +2123,7 @@ GLboolean check_vector(r700_AssemblerBase* pAsm, if( is_gpr(sel) ) { if( GL_FALSE == cycle_for_vector_bank_swizzle(bank_swizzle, src, &cycle) ) - { + { return GL_FALSE; } @@ -2129,7 +2135,7 @@ GLboolean check_vector(r700_AssemblerBase* pAsm, else { if( GL_FALSE == reserve_gpr(pAsm, sel, chan, cycle) ) - { + { return GL_FALSE; } } @@ -2141,7 +2147,7 @@ GLboolean check_vector(r700_AssemblerBase* pAsm, if( is_cfile(sel) ) { if( GL_FALSE == reserve_cfile(pAsm, sel, chan) ) - { + { return GL_FALSE; } } @@ -2244,7 +2250,7 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) current_source_index, pcurrent_source, scalar_channel_index) ) - { + { return GL_FALSE; } @@ -2258,7 +2264,7 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) current_source_index, pcurrent_source, scalar_channel_index) ) - { + { return GL_FALSE; } } @@ -2287,7 +2293,7 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) alu_instruction_ptr->m_Word1.f.dst_gpr = pAsm->D.dst.reg; } else - { + { radeon_error("Only temp destination registers supported for ALU dest regs.\n"); return GL_FALSE; } @@ -2401,7 +2407,7 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) } if(GL_FALSE == add_alu_instruction(pAsm, alu_instruction_ptr, contiguous_slots_needed) ) - { + { return GL_FALSE; } @@ -2412,15 +2418,15 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) if (is_single_scalar_operation) { if(GL_FALSE == check_scalar(pAsm, alu_instruction_ptr) ) - { + { return GL_FALSE; } } else { if(GL_FALSE == check_vector(pAsm, alu_instruction_ptr) ) - { - return 1; + { + return GL_FALSE; } } @@ -2667,7 +2673,7 @@ GLboolean assemble_alu_instruction2(r700_AssemblerBase *pAsm) { if(GL_FALSE == check_vector(pAsm, alu_instruction_ptr) ) { - return 1; + return GL_FALSE; } } @@ -3642,6 +3648,7 @@ GLboolean assemble_LRP(r700_AssemblerBase *pAsm) { return GL_FALSE; } + if( GL_FALSE == assemble_src(pAsm, 2, -1) ) { return GL_FALSE; @@ -4598,6 +4605,7 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) switch (pAsm->pILInst[pAsm->uiCurInst].SrcReg[0].File) { + case PROGRAM_UNIFORM: case PROGRAM_CONSTANT: case PROGRAM_LOCAL_PARAM: case PROGRAM_ENV_PARAM: @@ -6867,7 +6875,7 @@ GLboolean Process_Vertex_Exports(r700_AssemblerBase *pR700AsmCode, export_starting_index++; } } - + for(i=VERT_RESULT_VAR0; iucVP_OutputMap[i], GL_FALSE) ) - { + { return GL_FALSE; } diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index 21ac46e7b8..e9ef6c8695 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -44,12 +44,18 @@ //TODO : Validate FP input with VP output. void Map_Fragment_Program(r700_AssemblerBase *pAsm, - struct gl_fragment_program *mesa_fp) + struct gl_fragment_program *mesa_fp, + GLcontext *ctx) { unsigned int unBit; unsigned int i; GLuint ui; + /* match fp inputs with vp exports. */ + struct r700_vertex_program_cont *vpc = + (struct r700_vertex_program_cont *)ctx->VertexProgram._Current; + GLbitfield OutputsWritten = vpc->mesa_program.Base.OutputsWritten; + pAsm->number_used_registers = 0; //Input mapping : mesa_fp->Base.InputsRead set the flag, set in @@ -61,41 +67,41 @@ void Map_Fragment_Program(r700_AssemblerBase *pAsm, pAsm->uiFP_AttributeMap[FRAG_ATTRIB_WPOS] = pAsm->number_used_registers++; } - unBit = 1 << FRAG_ATTRIB_COL0; - if(mesa_fp->Base.InputsRead & unBit) + unBit = 1 << VERT_RESULT_COL0; + if(OutputsWritten & unBit) { pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL0] = pAsm->number_used_registers++; } - unBit = 1 << FRAG_ATTRIB_COL1; - if(mesa_fp->Base.InputsRead & unBit) + unBit = 1 << VERT_RESULT_COL1; + if(OutputsWritten & unBit) { pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1] = pAsm->number_used_registers++; } - unBit = 1 << FRAG_ATTRIB_FOGC; - if(mesa_fp->Base.InputsRead & unBit) + unBit = 1 << VERT_RESULT_FOGC; + if(OutputsWritten & unBit) { - pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC] = pAsm->number_used_registers++; + pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC] = pAsm->number_used_registers++; } for(i=0; i<8; i++) { - unBit = 1 << (FRAG_ATTRIB_TEX0 + i); - if(mesa_fp->Base.InputsRead & unBit) + unBit = 1 << (VERT_RESULT_TEX0 + i); + if(OutputsWritten & unBit) { pAsm->uiFP_AttributeMap[FRAG_ATTRIB_TEX0 + i] = pAsm->number_used_registers++; } } -/* order has been taken care of */ +/* order has been taken care of */ #if 1 - for(i=FRAG_ATTRIB_VAR0; iBase.InputsRead & unBit) + if(OutputsWritten & unBit) { - pAsm->uiFP_AttributeMap[i] = pAsm->number_used_registers++; + pAsm->uiFP_AttributeMap[i-VERT_RESULT_VAR0+FRAG_ATTRIB_VAR0] = pAsm->number_used_registers++; } } #else @@ -291,7 +297,8 @@ GLboolean Find_Instruction_Dependencies_fp(struct r700_fragment_program *fp, } GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp, - struct gl_fragment_program *mesa_fp) + struct gl_fragment_program *mesa_fp, + GLcontext *ctx) { GLuint number_of_colors_exported; GLboolean z_enabled = GL_FALSE; @@ -299,7 +306,7 @@ GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp, //Init_Program Init_r700_AssemblerBase( SPT_FP, &(fp->r700AsmCode), &(fp->r700Shader) ); - Map_Fragment_Program(&(fp->r700AsmCode), mesa_fp); + Map_Fragment_Program(&(fp->r700AsmCode), mesa_fp, ctx); if( GL_FALSE == Find_Instruction_Dependencies_fp(fp, mesa_fp) ) { @@ -366,7 +373,7 @@ void r700SelectFragmentShader(GLcontext *ctx) } if (GL_FALSE == fp->translated) - r700TranslateFragmentShader(fp, &(fp->mesa_program)); + r700TranslateFragmentShader(fp, &(fp->mesa_program), ctx); } void * r700GetActiveFpShaderBo(GLcontext * ctx) @@ -460,6 +467,9 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) EXPORT_MODE_shift, EXPORT_MODE_mask); // emit ps input map + struct r700_vertex_program_cont *vpc = + (struct r700_vertex_program_cont *)ctx->VertexProgram._Current; + GLbitfield OutputsWritten = vpc->mesa_program.Base.OutputsWritten; unBit = 1 << FRAG_ATTRIB_WPOS; if(mesa_fp->Base.InputsRead & unBit) { @@ -473,8 +483,8 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit); } - unBit = 1 << FRAG_ATTRIB_COL0; - if(mesa_fp->Base.InputsRead & unBit) + unBit = 1 << VERT_RESULT_COL0; + if(OutputsWritten & unBit) { ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL0]; SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit); @@ -486,8 +496,8 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit); } - unBit = 1 << FRAG_ATTRIB_COL1; - if(mesa_fp->Base.InputsRead & unBit) + unBit = 1 << VERT_RESULT_COL1; + if(OutputsWritten & unBit) { ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1]; SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit); @@ -499,8 +509,8 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit); } - unBit = 1 << FRAG_ATTRIB_FOGC; - if(mesa_fp->Base.InputsRead & unBit) + unBit = 1 << VERT_RESULT_FOGC; + if(OutputsWritten & unBit) { ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC]; SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit); @@ -514,8 +524,8 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) for(i=0; i<8; i++) { - unBit = 1 << (FRAG_ATTRIB_TEX0 + i); - if(mesa_fp->Base.InputsRead & unBit) + unBit = 1 << (VERT_RESULT_TEX0 + i); + if(OutputsWritten & unBit) { ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_TEX0 + i]; SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit); @@ -525,12 +535,12 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) } } - for(i=FRAG_ATTRIB_VAR0; iBase.InputsRead & unBit) + unBit = 1 << i; + if(OutputsWritten & unBit) { - ui = pAsm->uiFP_AttributeMap[i]; + ui = pAsm->uiFP_AttributeMap[i-VERT_RESULT_VAR0+FRAG_ATTRIB_VAR0]; SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit); SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui, SEMANTIC_shift, SEMANTIC_mask); @@ -538,8 +548,8 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit); else CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit); - } - } + } + } exportCount = (r700->ps.SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift); if (r700->CB_SHADER_CONTROL.u32All != ((1 << exportCount) - 1)) @@ -551,7 +561,8 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) /* sent out shader constants. */ paramList = fp->mesa_program.Base.Parameters; - if(NULL != paramList) { + if(NULL != paramList) + { _mesa_load_state_parameters(ctx, paramList); if (paramList->NumParameters > R700_MAX_DX9_CONSTS) @@ -564,10 +575,10 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) unNumParamData = paramList->NumParameters; for(ui=0; uips.consts[ui][0].f32All = paramList->ParameterValues[ui][0]; - r700->ps.consts[ui][1].f32All = paramList->ParameterValues[ui][1]; - r700->ps.consts[ui][2].f32All = paramList->ParameterValues[ui][2]; - r700->ps.consts[ui][3].f32All = paramList->ParameterValues[ui][3]; + r700->ps.consts[ui][0].f32All = paramList->ParameterValues[ui][0]; + r700->ps.consts[ui][1].f32All = paramList->ParameterValues[ui][1]; + r700->ps.consts[ui][2].f32All = paramList->ParameterValues[ui][2]; + r700->ps.consts[ui][3].f32All = paramList->ParameterValues[ui][3]; } } else r700->ps.num_consts = 0; diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.h b/src/mesa/drivers/dri/r600/r700_fragprog.h index cbb108d212..843de2c029 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.h +++ b/src/mesa/drivers/dri/r600/r700_fragprog.h @@ -49,12 +49,14 @@ struct r700_fragment_program /* Internal */ void Map_Fragment_Program(r700_AssemblerBase *pAsm, - struct gl_fragment_program *mesa_fp); + struct gl_fragment_program *mesa_fp, + GLcontext *ctx); //richard glsl nov.27 GLboolean Find_Instruction_Dependencies_fp(struct r700_fragment_program *fp, struct gl_fragment_program *mesa_fp); GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp, - struct gl_fragment_program *mesa_vp); + struct gl_fragment_program *mesa_vp, + GLcontext *ctx); //richard glsl nov.27 /* Interface */ extern void r700SelectFragmentShader(GLcontext *ctx); diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index c8f72d588b..7715214da1 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -631,6 +631,14 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) paramList = vp->mesa_program->Base.Parameters; if(NULL != paramList) { + //vp->mesa_program was cloned, not updated by glsl shader api. + //_mesa_reference_program has already checked glsl shProg is ok and set ctx->VertexProgem._Current + // so, use ctx->VertexProgem._Current + struct gl_program_parameter_list *paramListOrginal = + paramListOrginal = ctx->VertexProgram._Current->Base.Parameters; + + //--------------------------- + _mesa_load_state_parameters(ctx, paramList); if (paramList->NumParameters > R700_MAX_DX9_CONSTS) @@ -643,10 +651,20 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) unNumParamData = paramList->NumParameters; for(ui=0; uivs.consts[ui][0].f32All = paramList->ParameterValues[ui][0]; - r700->vs.consts[ui][1].f32All = paramList->ParameterValues[ui][1]; - r700->vs.consts[ui][2].f32All = paramList->ParameterValues[ui][2]; - r700->vs.consts[ui][3].f32All = paramList->ParameterValues[ui][3]; + if(paramList->Parameters[ui].Type == PROGRAM_UNIFORM) + { + r700->vs.consts[ui][0].f32All = paramListOrginal->ParameterValues[ui][0]; + r700->vs.consts[ui][1].f32All = paramListOrginal->ParameterValues[ui][1]; + r700->vs.consts[ui][2].f32All = paramListOrginal->ParameterValues[ui][2]; + r700->vs.consts[ui][3].f32All = paramListOrginal->ParameterValues[ui][3]; + } + else + { + r700->vs.consts[ui][0].f32All = paramList->ParameterValues[ui][0]; + r700->vs.consts[ui][1].f32All = paramList->ParameterValues[ui][1]; + r700->vs.consts[ui][2].f32All = paramList->ParameterValues[ui][2]; + r700->vs.consts[ui][3].f32All = paramList->ParameterValues[ui][3]; + } } } else r700->vs.num_consts = 0; -- cgit v1.2.3 From a1b9c4e22a83d2125f66c3a3af3143bc0daee9a4 Mon Sep 17 00:00:00 2001 From: Richard Li Date: Sun, 29 Nov 2009 12:28:32 -0500 Subject: r600 : clena up a bit for last commit. --- src/mesa/drivers/dri/r600/r700_fragprog.h | 4 ++-- src/mesa/drivers/dri/r600/r700_vertprog.c | 10 ++++------ 2 files changed, 6 insertions(+), 8 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.h b/src/mesa/drivers/dri/r600/r700_fragprog.h index 843de2c029..e562bfa478 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.h +++ b/src/mesa/drivers/dri/r600/r700_fragprog.h @@ -50,13 +50,13 @@ struct r700_fragment_program /* Internal */ void Map_Fragment_Program(r700_AssemblerBase *pAsm, struct gl_fragment_program *mesa_fp, - GLcontext *ctx); //richard glsl nov.27 + GLcontext *ctx); GLboolean Find_Instruction_Dependencies_fp(struct r700_fragment_program *fp, struct gl_fragment_program *mesa_fp); GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp, struct gl_fragment_program *mesa_vp, - GLcontext *ctx); //richard glsl nov.27 + GLcontext *ctx); /* Interface */ extern void r700SelectFragmentShader(GLcontext *ctx); diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index 7715214da1..d3d1da7959 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -631,14 +631,12 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) paramList = vp->mesa_program->Base.Parameters; if(NULL != paramList) { - //vp->mesa_program was cloned, not updated by glsl shader api. - //_mesa_reference_program has already checked glsl shProg is ok and set ctx->VertexProgem._Current - // so, use ctx->VertexProgem._Current + /* vp->mesa_program was cloned, not updated by glsl shader api. */ + /* _mesa_reference_program has already checked glsl shProg is ok and set ctx->VertexProgem._Current */ + /* so, use ctx->VertexProgem._Current */ struct gl_program_parameter_list *paramListOrginal = paramListOrginal = ctx->VertexProgram._Current->Base.Parameters; - - //--------------------------- - + _mesa_load_state_parameters(ctx, paramList); if (paramList->NumParameters > R700_MAX_DX9_CONSTS) -- cgit v1.2.3 From df02bc42b330fe20679dd3e5e83317df72ddd5ca Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Sat, 5 Dec 2009 18:24:41 -0500 Subject: radeon/r200/r600: fix drivers for changes in 433f0a82f5a4696e6b0c4061f645485ec8079bb4 --- src/mesa/drivers/dri/r200/r200_texstate.c | 15 ++------------- src/mesa/drivers/dri/r600/r600_texstate.c | 13 +------------ src/mesa/drivers/dri/radeon/radeon_texstate.c | 15 ++------------- 3 files changed, 5 insertions(+), 38 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index 7782404a79..e2f9cf0ea8 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -797,24 +797,13 @@ void r200SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo return; } - radeon_update_renderbuffers(pDRICtx, dPriv); - /* back & depth buffer are useless free them right away */ - rb = (void*)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = (void*)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } + radeon_update_renderbuffers(pDRICtx, dPriv, GL_TRUE); rb = rfb->color_rb[0]; if (rb->bo == NULL) { /* Failed to BO for the buffer */ return; } - + _mesa_lock_texture(radeon->glCtx, texObj); if (t->bo) { radeon_bo_unref(t->bo); diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 4ec315b78c..2a4a6e6ee1 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -917,18 +917,7 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo return; } - radeon_update_renderbuffers(pDRICtx, dPriv); - /* back & depth buffer are useless free them right away */ - rb = (void*)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = (void*)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } + radeon_update_renderbuffers(pDRICtx, dPriv, GL_TRUE); rb = rfb->color_rb[0]; if (rb->bo == NULL) { /* Failed to BO for the buffer */ diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index 3cbe3b4725..84ddcfd4fd 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -672,24 +672,13 @@ void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_ return; } - radeon_update_renderbuffers(pDRICtx, dPriv); - /* back & depth buffer are useless free them right away */ - rb = (void*)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } - rb = (void*)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer; - if (rb && rb->bo) { - radeon_bo_unref(rb->bo); - rb->bo = NULL; - } + radeon_update_renderbuffers(pDRICtx, dPriv, GL_TRUE); rb = rfb->color_rb[0]; if (rb->bo == NULL) { /* Failed to BO for the buffer */ return; } - + _mesa_lock_texture(radeon->glCtx, texObj); if (t->bo) { radeon_bo_unref(t->bo); -- cgit v1.2.3 From dc0777d3e3b760d7faa5fb99a189919bde07ca0b Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Wed, 4 Nov 2009 10:00:47 +0200 Subject: r600: reorder state for render_target and blend First time around render targets are not enabled yet (done in r700SendRenderTargetState) so blend state is not emitted for any targets. Affects first glClear in some mesa tests. As a quick fix reorder state emit so that target is set first --- src/mesa/drivers/dri/r600/r700_chip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 8707a764ac..d8661b4439 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -1250,9 +1250,9 @@ void r600InitAtoms(context_t *context) ALLOC_STATE(poly, always, 10, r700SendPolyState); ALLOC_STATE(cb, cb, 18, r700SendCBState); ALLOC_STATE(clrcmp, always, 6, r700SendCBCLRCMPState); + ALLOC_STATE(cb_target, always, 25, r700SendRenderTargetState); ALLOC_STATE(blnd, blnd, (6 + (R700_MAX_RENDER_TARGETS * 3)), r700SendCBBlendState); ALLOC_STATE(blnd_clr, always, 6, r700SendCBBlendColorState); - ALLOC_STATE(cb_target, always, 25, r700SendRenderTargetState); ALLOC_STATE(sx, always, 9, r700SendSXState); ALLOC_STATE(vgt, always, 41, r700SendVGTState); ALLOC_STATE(spi, always, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState); -- cgit v1.2.3 From 369669ff9a7ff7636cadef8e2b13f2f28face98f Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Thu, 3 Dec 2009 12:26:44 +0200 Subject: r600: add support for TXB instruction makes testing other things easier - does not hang the card TODO: enable TEX dependency tracking in vertex programs --- src/mesa/drivers/dri/r600/r700_assembler.c | 26 +++++++++----------------- 1 file changed, 9 insertions(+), 17 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 6ff08e1cfb..be875ae6b8 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -3450,22 +3450,6 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) need_barrier = GL_TRUE; } - switch (pAsm->pILInst[pAsm->uiCurInst].Opcode) - { - case OPCODE_TEX: - break; - case OPCODE_TXB: - radeon_error("do not support TXB yet\n"); - return GL_FALSE; - break; - case OPCODE_TXP: - break; - default: - radeon_error("Internal error: bad texture op (not TEX)\n"); - return GL_FALSE; - break; - } - if (pAsm->pILInst[pAsm->uiCurInst].Opcode == OPCODE_TXP) { GLuint tmp = gethelpr(pAsm); @@ -3644,7 +3628,15 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) } - pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE; + if(pAsm->pILInst[pAsm->uiCurInst].Opcode == OPCODE_TXB) + { + pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE_L; + } + else + { + pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE; + } + pAsm->is_tex = GL_TRUE; if ( GL_TRUE == need_barrier ) { -- cgit v1.2.3 From 94c6ec5809b08676f12628b49dd88ec694d07a48 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Thu, 3 Dec 2009 18:12:45 +0200 Subject: r600: execute SET funtions on all channels seems assemble_LOGIC was meant for non-condition-code instructions so execute in for all components as previously --- src/mesa/drivers/dri/r600/r700_assembler.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index cf64d170ed..fe006ef19c 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -4467,7 +4467,7 @@ GLboolean assemble_LOGIC(r700_AssemblerBase *pAsm, BITS opcode) } pAsm->D.dst.opcode = opcode; - pAsm->D.dst.math = 1; + //pAsm->D.dst.math = 1; if( GL_FALSE == assemble_dst(pAsm) ) { -- cgit v1.2.3 From c1d79a4235fa2edb05e92f9b93a105ff356a4a18 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Fri, 4 Dec 2009 11:37:15 +0200 Subject: r600: wip glsl - refactor conditional instructions a bit remember the dst register which is used for cond updates when it's time to use the cond codes issue a separate PRED instruction --- src/mesa/drivers/dri/r600/r700_assembler.c | 379 ++++++----------------------- src/mesa/drivers/dri/r600/r700_assembler.h | 1 + 2 files changed, 70 insertions(+), 310 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index fe006ef19c..87c1638de4 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -3557,7 +3557,7 @@ GLboolean assemble_KIL(r700_AssemblerBase *pAsm, GLuint opcode) checkop2(pAsm); pAsm->D.dst.opcode = opcode; - pAsm->D.dst.math = 1; + //pAsm->D.dst.math = 1; setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); pAsm->D.dst.rtype = DST_REG_TEMPORARY; @@ -3567,17 +3567,23 @@ GLboolean assemble_KIL(r700_AssemblerBase *pAsm, GLuint opcode) pAsm->D.dst.writez = 0; pAsm->D.dst.writew = 0; - if( GL_FALSE == assemble_src(pAsm, 0, -1) ) + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = 0; + setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_0); + noneg_PVSSRC(&(pAsm->S[0].src)); + + if( GL_FALSE == assemble_src(pAsm, 0, 1) ) { return GL_FALSE; } - if( GL_FALSE == assemble_src(pAsm, 1, -1) ) + /*if( GL_FALSE == assemble_src(pAsm, 1, -1) ) { return GL_FALSE; } - - if ( GL_FALSE == next_ins2(pAsm) ) + */ + if ( GL_FALSE == next_ins(pAsm) ) { return GL_FALSE; } @@ -4494,30 +4500,32 @@ GLboolean assemble_LOGIC(r700_AssemblerBase *pAsm, BITS opcode) GLboolean assemble_LOGIC_PRED(r700_AssemblerBase *pAsm, BITS opcode) { - if( GL_FALSE == checkop2(pAsm) ) - { - return GL_FALSE; - } + struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); pAsm->D.dst.opcode = opcode; pAsm->D.dst.math = 1; pAsm->D.dst.predicated = 1; - pAsm->D2.dst2.SaturateMode = pAsm->pILInst[pAsm->uiCurInst].SaturateMode; - if( GL_FALSE == assemble_dst(pAsm) ) - { - return GL_FALSE; - } + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = pAsm->uHelpReg; + pAsm->D.dst.writex = 1; + pAsm->D.dst.writey = pAsm->D.dst.writez = pAsm->D.dst.writew = 0; - if( GL_FALSE == assemble_src(pAsm, 0, -1) ) - { - return GL_FALSE; - } + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = pAsm->last_cond_register + pAsm->starting_temp_register_number; + pAsm->S[0].src.swizzlex = pILInst->DstReg.CondSwizzle & 0x7; + noneg_PVSSRC(&(pAsm->S[0].src)); - if( GL_FALSE == assemble_src(pAsm, 1, -1) ) - { - return GL_FALSE; - } + pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[1].src.reg = pAsm->uHelpReg; + setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); + noneg_PVSSRC(&(pAsm->S[1].src)); + pAsm->S[1].src.swizzlex = SQ_SEL_0; + pAsm->S[1].src.swizzley = SQ_SEL_0; + pAsm->S[1].src.swizzlez = SQ_SEL_0; + pAsm->S[1].src.swizzlew = SQ_SEL_0; if( GL_FALSE == next_ins2(pAsm) ) { @@ -5098,6 +5106,11 @@ GLboolean pops(r700_AssemblerBase *pAsm, GLuint pops) GLboolean assemble_IF(r700_AssemblerBase *pAsm, GLboolean bHasElse) { + pAsm->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; + + assemble_LOGIC_PRED(pAsm, SQ_OP2_INST_PRED_SETNE); + + if(GL_FALSE == add_cf_instruction(pAsm) ) { return GL_FALSE; @@ -5242,6 +5255,11 @@ GLboolean assemble_BGNLOOP(r700_AssemblerBase *pAsm) GLboolean assemble_BRK(r700_AssemblerBase *pAsm) { #ifdef USE_CF_FOR_CONTINUE_BREAK + + pAsm->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; + + assemble_LOGIC_PRED(pAsm, SQ_OP2_INST_PRED_SETNE); + unsigned int unFCSP; for(unFCSP=pAsm->FCSP; unFCSP>0; unFCSP--) { @@ -5308,6 +5326,10 @@ GLboolean assemble_BRK(r700_AssemblerBase *pAsm) GLboolean assemble_CONT(r700_AssemblerBase *pAsm) { #ifdef USE_CF_FOR_CONTINUE_BREAK + pAsm->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; + + assemble_LOGIC_PRED(pAsm, SQ_OP2_INST_PRED_SETNE); + unsigned int unFCSP; for(unFCSP=pAsm->FCSP; unFCSP>0; unFCSP--) { @@ -5848,6 +5870,12 @@ GLboolean AssembleInstr(GLuint uiFirstInst, } } #endif + if(pILInst[i].CondUpdate == 1) + { + /* remember dest register used for cond evaluation */ + /* XXX also handle PROGRAM_OUTPUT registers here? */ + pR700AsmCode->last_cond_register = pILInst[i].DstReg.Index; + } switch (pILInst[i].Opcode) { @@ -5918,9 +5946,8 @@ GLboolean AssembleInstr(GLuint uiFirstInst, case OPCODE_KIL: case OPCODE_KIL_NV: - /* done at OPCODE_SE/SGT...etc. */ - /* if ( GL_FALSE == assemble_KIL(pR700AsmCode) ) - return GL_FALSE; */ + if ( GL_FALSE == assemble_KIL(pR700AsmCode, SQ_OP2_INST_KILLGT) ) + return GL_FALSE; break; case OPCODE_LG2: if ( GL_FALSE == assemble_LG2(pR700AsmCode) ) @@ -5983,151 +6010,23 @@ GLboolean AssembleInstr(GLuint uiFirstInst, break; case OPCODE_SEQ: - if(OPCODE_IF == pILInst[i+1].Opcode) - { - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; - if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETE) ) - { - return GL_FALSE; - } - } - else if(OPCODE_BRK == pILInst[i+1].Opcode) + if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETE) ) { -#ifdef USE_CF_FOR_CONTINUE_BREAK - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; -#else - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_BREAK; -#endif - if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETE) ) - { - return GL_FALSE; - } - } - else if(OPCODE_CONT == pILInst[i+1].Opcode) - { -#ifdef USE_CF_FOR_CONTINUE_BREAK - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; -#else - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_CONTINUE; -#endif - if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETE) ) - { - return GL_FALSE; - } - } - else if((OPCODE_KIL == pILInst[i+1].Opcode)||(OPCODE_KIL_NV == pILInst[i+1].Opcode)) - { - if ( GL_FALSE == assemble_KIL(pR700AsmCode, SQ_OP2_INST_KILLE) ) - { - return GL_FALSE; - } - } - else - { - if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETE) ) - { - return GL_FALSE; - } + return GL_FALSE; } break; case OPCODE_SGT: - if(OPCODE_IF == pILInst[i+1].Opcode) - { - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; - if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGT) ) - { - return GL_FALSE; - } - } - else if(OPCODE_BRK == pILInst[i+1].Opcode) + if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETGT) ) { -#ifdef USE_CF_FOR_CONTINUE_BREAK - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; -#else - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_BREAK; -#endif - if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGT) ) - { - return GL_FALSE; - } - } - else if(OPCODE_CONT == pILInst[i+1].Opcode) - { -#ifdef USE_CF_FOR_CONTINUE_BREAK - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; -#else - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_CONTINUE; -#endif - - if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGT) ) - { - return GL_FALSE; - } - } - else if((OPCODE_KIL == pILInst[i+1].Opcode)||(OPCODE_KIL_NV == pILInst[i+1].Opcode)) - { - if ( GL_FALSE == assemble_KIL(pR700AsmCode, SQ_OP2_INST_KILLGT) ) - { - return GL_FALSE; - } - } - else - { - if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETGT) ) - { - return GL_FALSE; - } + return GL_FALSE; } break; case OPCODE_SGE: - if(OPCODE_IF == pILInst[i+1].Opcode) - { - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; - if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGE) ) - { - return GL_FALSE; - } - } - else if(OPCODE_BRK == pILInst[i+1].Opcode) - { -#ifdef USE_CF_FOR_CONTINUE_BREAK - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; -#else - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_BREAK; -#endif - if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGE) ) - { - return GL_FALSE; - } - } - else if(OPCODE_CONT == pILInst[i+1].Opcode) - { -#ifdef USE_CF_FOR_CONTINUE_BREAK - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; -#else - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_CONTINUE; -#endif - - if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGE) ) - { - return GL_FALSE; - } - } - else if((OPCODE_KIL == pILInst[i+1].Opcode)||(OPCODE_KIL_NV == pILInst[i+1].Opcode)) - { - if ( GL_FALSE == assemble_KIL(pR700AsmCode, SQ_OP2_INST_KILLGE) ) - { - return GL_FALSE; - } - } - else - { - if ( GL_FALSE == assemble_SGE(pR700AsmCode) ) - { - return GL_FALSE; - } + if ( GL_FALSE == assemble_SGE(pR700AsmCode) ) + { + return GL_FALSE; } break; @@ -6139,61 +6038,12 @@ GLboolean AssembleInstr(GLuint uiFirstInst, SrcRegSave[1] = pILInst[i].SrcReg[1]; pILInst[i].SrcReg[0] = SrcRegSave[1]; pILInst[i].SrcReg[1] = SrcRegSave[0]; - if(OPCODE_IF == pILInst[i+1].Opcode) - { - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; - if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGT) ) - { - pILInst[i].SrcReg[0] = SrcRegSave[0]; - pILInst[i].SrcReg[1] = SrcRegSave[1]; - return GL_FALSE; - } - } - else if(OPCODE_BRK == pILInst[i+1].Opcode) - { -#ifdef USE_CF_FOR_CONTINUE_BREAK - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; -#else - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_BREAK; -#endif - if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGT) ) - { - pILInst[i].SrcReg[0] = SrcRegSave[0]; - pILInst[i].SrcReg[1] = SrcRegSave[1]; - return GL_FALSE; - } - } - else if(OPCODE_CONT == pILInst[i+1].Opcode) - { -#ifdef USE_CF_FOR_CONTINUE_BREAK - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; -#else - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_CONTINUE; -#endif - - if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGT) ) - { - pILInst[i].SrcReg[0] = SrcRegSave[0]; - pILInst[i].SrcReg[1] = SrcRegSave[1]; - return GL_FALSE; - } - } - else if((OPCODE_KIL == pILInst[i+1].Opcode)||(OPCODE_KIL_NV == pILInst[i+1].Opcode)) + if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETGT) ) { - if ( GL_FALSE == assemble_KIL(pR700AsmCode, SQ_OP2_INST_KILLGT) ) - { - return GL_FALSE; - } + pILInst[i].SrcReg[0] = SrcRegSave[0]; + pILInst[i].SrcReg[1] = SrcRegSave[1]; + return GL_FALSE; } - else - { - if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETGT) ) - { - pILInst[i].SrcReg[0] = SrcRegSave[0]; - pILInst[i].SrcReg[1] = SrcRegSave[1]; - return GL_FALSE; - } - } pILInst[i].SrcReg[0] = SrcRegSave[0]; pILInst[i].SrcReg[1] = SrcRegSave[1]; } @@ -6206,60 +6056,11 @@ GLboolean AssembleInstr(GLuint uiFirstInst, SrcRegSave[1] = pILInst[i].SrcReg[1]; pILInst[i].SrcReg[0] = SrcRegSave[1]; pILInst[i].SrcReg[1] = SrcRegSave[0]; - if(OPCODE_IF == pILInst[i+1].Opcode) + if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETGE) ) { - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; - if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGE) ) - { - pILInst[i].SrcReg[0] = SrcRegSave[0]; - pILInst[i].SrcReg[1] = SrcRegSave[1]; - return GL_FALSE; - } - } - else if(OPCODE_BRK == pILInst[i+1].Opcode) - { -#ifdef USE_CF_FOR_CONTINUE_BREAK - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; -#else - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_BREAK; -#endif - if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGE) ) - { - pILInst[i].SrcReg[0] = SrcRegSave[0]; - pILInst[i].SrcReg[1] = SrcRegSave[1]; - return GL_FALSE; - } - } - else if(OPCODE_CONT == pILInst[i+1].Opcode) - { -#ifdef USE_CF_FOR_CONTINUE_BREAK - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; -#else - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_CONTINUE; -#endif - - if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETGE) ) - { - pILInst[i].SrcReg[0] = SrcRegSave[0]; - pILInst[i].SrcReg[1] = SrcRegSave[1]; - return GL_FALSE; - } - } - else if((OPCODE_KIL == pILInst[i+1].Opcode)||(OPCODE_KIL_NV == pILInst[i+1].Opcode)) - { - if ( GL_FALSE == assemble_KIL(pR700AsmCode, SQ_OP2_INST_KILLGE) ) - { - return GL_FALSE; - } - } - else - { - if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETGE) ) - { - pILInst[i].SrcReg[0] = SrcRegSave[0]; - pILInst[i].SrcReg[1] = SrcRegSave[1]; - return GL_FALSE; - } + pILInst[i].SrcReg[0] = SrcRegSave[0]; + pILInst[i].SrcReg[1] = SrcRegSave[1]; + return GL_FALSE; } pILInst[i].SrcReg[0] = SrcRegSave[0]; pILInst[i].SrcReg[1] = SrcRegSave[1]; @@ -6267,51 +6068,9 @@ GLboolean AssembleInstr(GLuint uiFirstInst, break; case OPCODE_SNE: - if(OPCODE_IF == pILInst[i+1].Opcode) - { - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; - if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETNE) ) - { - return GL_FALSE; - } - } - else if(OPCODE_BRK == pILInst[i+1].Opcode) + if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETNE) ) { -#ifdef USE_CF_FOR_CONTINUE_BREAK - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; -#else - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_BREAK; -#endif - if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETNE) ) - { - return GL_FALSE; - } - } - else if(OPCODE_CONT == pILInst[i+1].Opcode) - { -#ifdef USE_CF_FOR_CONTINUE_BREAK - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_PUSH_BEFORE; -#else - pR700AsmCode->alu_x_opcode = SQ_CF_INST_ALU_CONTINUE; -#endif - if ( GL_FALSE == assemble_LOGIC_PRED(pR700AsmCode, SQ_OP2_INST_PRED_SETNE) ) - { - return GL_FALSE; - } - } - else if((OPCODE_KIL == pILInst[i+1].Opcode)||(OPCODE_KIL_NV == pILInst[i+1].Opcode)) - { - if ( GL_FALSE == assemble_KIL(pR700AsmCode, SQ_OP2_INST_KILLNE) ) - { - return GL_FALSE; - } - } - else - { - if ( GL_FALSE == assemble_LOGIC(pR700AsmCode, SQ_OP2_INST_SETNE) ) - { - return GL_FALSE; - } + return GL_FALSE; } break; diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index 130fc89dae..ef1f924add 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -345,6 +345,7 @@ typedef struct r700_AssemblerBase PVSDWORD S[3]; unsigned int uLastPosUpdate; + unsigned int last_cond_register; OUT_FRAGMENT_FMT_0 fp_stOutFmt0; -- cgit v1.2.3 From 323d1fb3910d7e53cb5200ee90849b2231fd96fb Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Fri, 4 Dec 2009 12:58:36 +0200 Subject: r600: quick hack to get KIL_NV working - does condition TR only for now --- src/mesa/drivers/dri/r600/r700_assembler.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 87c1638de4..3738edbc2f 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -3554,7 +3554,10 @@ GLboolean assemble_FRC(r700_AssemblerBase *pAsm) GLboolean assemble_KIL(r700_AssemblerBase *pAsm, GLuint opcode) { - checkop2(pAsm); + struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); + + if(pILInst->Opcode == OPCODE_KIL) + checkop1(pAsm); pAsm->D.dst.opcode = opcode; //pAsm->D.dst.math = 1; @@ -3573,16 +3576,23 @@ GLboolean assemble_KIL(r700_AssemblerBase *pAsm, GLuint opcode) setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_0); noneg_PVSSRC(&(pAsm->S[0].src)); - if( GL_FALSE == assemble_src(pAsm, 0, 1) ) + if(pILInst->Opcode == OPCODE_KIL_NV) { - return GL_FALSE; + setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); + pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[1].src.reg = 0; + setswizzle_PVSSRC(&(pAsm->S[1].src), SQ_SEL_1); + neg_PVSSRC(&(pAsm->S[1].src)); } - - /*if( GL_FALSE == assemble_src(pAsm, 1, -1) ) + else { - return GL_FALSE; + if( GL_FALSE == assemble_src(pAsm, 0, 1) ) + { + return GL_FALSE; + } + } - */ + if ( GL_FALSE == next_ins(pAsm) ) { return GL_FALSE; -- cgit v1.2.3 From 94723b60cf3dd838dfaf505450db8ef2e089399c Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Fri, 4 Dec 2009 13:53:44 +0200 Subject: r600: implement FRAG_ATTRIB_FACE, glsl/twoside works --- src/mesa/drivers/dri/r600/r700_fragprog.c | 34 ++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index e9ef6c8695..0cb9707ee6 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -93,7 +93,7 @@ void Map_Fragment_Program(r700_AssemblerBase *pAsm, pAsm->uiFP_AttributeMap[FRAG_ATTRIB_TEX0 + i] = pAsm->number_used_registers++; } } - + /* order has been taken care of */ #if 1 for(i=VERT_RESULT_VAR0; inumber_used_registers += unMaxVarying + 1; } #endif + unBit = 1 << FRAG_ATTRIB_FACE; + if(mesa_fp->Base.InputsRead & unBit) + { + pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FACE] = pAsm->number_used_registers++; + } /* Map temporary registers (GPRs) */ pAsm->starting_temp_register_number = pAsm->number_used_registers; @@ -451,6 +456,20 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) CLEARbit(r700->SPI_INPUT_Z.u32All, PROVIDE_Z_TO_SPI_bit); } + if (mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_FACE)) + { + ui += 1; + SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, ui, NUM_INTERP_shift, NUM_INTERP_mask); + SETbit(r700->SPI_PS_IN_CONTROL_1.u32All, FRONT_FACE_ENA_bit); + SETbit(r700->SPI_PS_IN_CONTROL_1.u32All, FRONT_FACE_ALL_BITS_bit); + SETfield(r700->SPI_PS_IN_CONTROL_1.u32All, pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FACE], FRONT_FACE_ADDR_shift, FRONT_FACE_ADDR_mask); + } + else + { + CLEARbit(r700->SPI_PS_IN_CONTROL_1.u32All, FRONT_FACE_ENA_bit); + } + + ui = (unNumOfReg < ui) ? ui : unNumOfReg; SETfield(r700->ps.SQ_PGM_RESOURCES_PS.u32All, ui, NUM_GPRS_shift, NUM_GPRS_mask); @@ -535,6 +554,19 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) } } + unBit = 1 << FRAG_ATTRIB_FACE; + if(mesa_fp->Base.InputsRead & unBit) + { + ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FACE]; + SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit); + SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui, + SEMANTIC_shift, SEMANTIC_mask); + if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit) + SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit); + else + CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit); + } + for(i=VERT_RESULT_VAR0; i Date: Fri, 4 Dec 2009 16:36:41 +0200 Subject: r600: glsl - allow specifying texture sampler via uniforms looks kinda hackish, should rethink later --- src/mesa/drivers/dri/r600/r700_assembler.c | 2 +- src/mesa/drivers/dri/r600/r700_assembler.h | 1 + src/mesa/drivers/dri/r600/r700_fragprog.c | 5 +++++ src/mesa/drivers/dri/r600/r700_vertprog.c | 4 ++++ 4 files changed, 11 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 3738edbc2f..158c5fa549 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -4840,7 +4840,7 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) pAsm->need_tex_barrier = GL_TRUE; } // Set src1 to tex unit id - pAsm->S[1].src.reg = pAsm->pILInst[pAsm->uiCurInst].TexSrcUnit; + pAsm->S[1].src.reg = pAsm->SamplerUnits[pAsm->pILInst[pAsm->uiCurInst].TexSrcUnit]; pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; //No sw info from mesa compiler, so hard code here. diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index ef1f924add..48ffef501f 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -416,6 +416,7 @@ typedef struct r700_AssemblerBase SHADER_PIPE_TYPE currentShaderType; struct prog_instruction * pILInst; GLuint uiCurInst; + GLubyte SamplerUnits[MAX_SAMPLERS]; GLboolean bR6xx; /* helper to decide which type of instruction to assemble */ GLboolean is_tex; diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index 0cb9707ee6..8eb439a951 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -308,6 +308,7 @@ GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp, GLuint number_of_colors_exported; GLboolean z_enabled = GL_FALSE; GLuint unBit; + int i; //Init_Program Init_r700_AssemblerBase( SPT_FP, &(fp->r700AsmCode), &(fp->r700Shader) ); @@ -320,6 +321,10 @@ GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp, InitShaderProgram(&(fp->r700AsmCode)); + for(i=0; i < MAX_SAMPLERS; i++) + { + fp->r700AsmCode.SamplerUnits[i] = fp->mesa_program.Base.SamplerUnits[i]; + } if( GL_FALSE == AssembleInstr(0, mesa_fp->Base.NumInstructions, &(mesa_fp->Base.Instructions[0]), diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index d3d1da7959..759b74dc7e 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -337,6 +337,10 @@ struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, InitShaderProgram(&(vp->r700AsmCode)); + for(i=0; i < MAX_SAMPLERS; i++) + { + vp->r700AsmCode.SamplerUnits[i] = vp->mesa_program->Base.SamplerUnits[i]; + } if(GL_FALSE == AssembleInstr(0, vp->mesa_program->Base.NumInstructions, &(vp->mesa_program->Base.Instructions[0]), -- cgit v1.2.3 From 17e212e2631cd652c28378399806c3b3bd293e9a Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 7 Dec 2009 11:51:36 +0200 Subject: r600: add ABS support for source regs to assembler use it in tex cube instruction sequence --- src/mesa/drivers/dri/r600/r700_assembler.c | 27 +++++---------------------- src/mesa/drivers/dri/r600/r700_assembler.h | 7 ++++--- 2 files changed, 9 insertions(+), 25 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 158c5fa549..2f8038adb3 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -2350,8 +2350,8 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) { alu_instruction_ptr->m_Word1_OP2.f6.alu_inst = pAsm->D.dst.opcode; - alu_instruction_ptr->m_Word1_OP2.f6.src0_abs = 0x0; - alu_instruction_ptr->m_Word1_OP2.f6.src1_abs = 0x0; + alu_instruction_ptr->m_Word1_OP2.f6.src0_abs = pAsm->S[0].src.abs; + alu_instruction_ptr->m_Word1_OP2.f6.src1_abs = pAsm->S[1].src.abs; //alu_instruction_ptr->m_Word1_OP2.f6.update_execute_mask = 0x0; //alu_instruction_ptr->m_Word1_OP2.f6.update_pred = 0x0; @@ -2379,8 +2379,8 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) { alu_instruction_ptr->m_Word1_OP2.f.alu_inst = pAsm->D.dst.opcode; - alu_instruction_ptr->m_Word1_OP2.f.src0_abs = 0x0; - alu_instruction_ptr->m_Word1_OP2.f.src1_abs = 0x0; + alu_instruction_ptr->m_Word1_OP2.f.src0_abs = pAsm->S[0].src.abs; + alu_instruction_ptr->m_Word1_OP2.f.src1_abs = pAsm->S[1].src.abs; //alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0x0; //alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0x0; @@ -4721,24 +4721,6 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) return GL_FALSE; } - /* tmp1.z = ABS(tmp1.z) dont have abs support in assembler currently - * have to do explicit instruction - */ - pAsm->D.dst.opcode = SQ_OP2_INST_MAX; - setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); - pAsm->D.dst.rtype = DST_REG_TEMPORARY; - pAsm->D.dst.reg = tmp1; - pAsm->D.dst.writez = 1; - - setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); - pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; - pAsm->S[0].src.reg = tmp1; - noswizzle_PVSSRC(&(pAsm->S[0].src)); - pAsm->S[1].bits = pAsm->S[0].bits; - flipneg_PVSSRC(&(pAsm->S[1].src)); - - next_ins(pAsm); - /* tmp1.z = RCP_e(|tmp1.z|) */ pAsm->D.dst.opcode = SQ_OP2_INST_RECIP_IEEE; pAsm->D.dst.math = 1; @@ -4751,6 +4733,7 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; pAsm->S[0].src.reg = tmp1; pAsm->S[0].src.swizzlex = SQ_SEL_Z; + pAsm->S[0].src.abs = 1; next_ins(pAsm); diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index 48ffef501f..cfa2610a55 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -120,14 +120,15 @@ typedef struct PVSINSTtag typedef struct PVSSRCtag { - BITS rtype:4; + BITS rtype:3; BITS addrmode0:1; - BITS reg:10; //15 (8) + BITS reg:10; //14 (8) BITS swizzlex:3; BITS swizzley:3; BITS swizzlez:3; - BITS swizzlew:3; //27 + BITS swizzlew:3; //26 + BITS abs:1; BITS negx:1; BITS negy:1; BITS negz:1; -- cgit v1.2.3 From 602ba357edd640e0db17911b39d3ecfbf5675230 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 7 Dec 2009 13:04:32 +0200 Subject: r600: merge alu_instruction/alu_instruction2 --- src/mesa/drivers/dri/r600/r700_assembler.c | 320 +++-------------------------- src/mesa/drivers/dri/r600/r700_assembler.h | 6 +- 2 files changed, 29 insertions(+), 297 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 2f8038adb3..8155d53eeb 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -1292,6 +1292,15 @@ GLboolean assemble_dst(r700_AssemblerBase *pAsm) pAsm->D.dst.writez = (pILInst->DstReg.WriteMask >> 2) & 0x1; pAsm->D.dst.writew = (pILInst->DstReg.WriteMask >> 3) & 0x1; + if(pILInst->SaturateMode == SATURATE_ZERO_ONE) + { + pAsm->D2.dst2.SaturateMode = 1; + } + else + { + pAsm->D2.dst2.SaturateMode = 0; + } + return GL_TRUE; } @@ -2270,7 +2279,7 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) } //other bits - alu_instruction_ptr->m_Word0.f.index_mode = SQ_INDEX_AR_X; + alu_instruction_ptr->m_Word0.f.index_mode = pAsm->D2.dst2.index_mode; if( (is_single_scalar_operation == GL_TRUE) || (GL_TRUE == bSplitInst) ) @@ -2282,9 +2291,17 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) alu_instruction_ptr->m_Word0.f.last = (scalar_channel_index == 3) ? 1 : 0; } - alu_instruction_ptr->m_Word0.f.pred_sel = 0x0; - alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0x0; - alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0x0; + alu_instruction_ptr->m_Word0.f.pred_sel = (pAsm->D.dst.pred_inv > 0) ? 1 : 0; + if(1 == pAsm->D.dst.predicated) + { + alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0x1; + alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0x1; + } + else + { + alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0x0; + alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0x0; + } // dst if( (pAsm->D.dst.rtype == DST_REG_TEMPORARY) || @@ -2323,7 +2340,7 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) alu_instruction_ptr->m_Word1.f.dst_chan = scalar_channel_index; - alu_instruction_ptr->m_Word1.f.clamp = pAsm->pILInst[pAsm->uiCurInst].SaturateMode; + alu_instruction_ptr->m_Word1.f.clamp = pAsm->D2.dst2.SaturateMode; if (pAsm->D.dst.op3) { @@ -2436,253 +2453,6 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) return GL_TRUE; } -GLboolean assemble_alu_instruction2(r700_AssemblerBase *pAsm) -{ - GLuint number_of_scalar_operations; - GLboolean is_single_scalar_operation; - GLuint scalar_channel_index; - - PVSSRC * pcurrent_source; - int current_source_index; - GLuint contiguous_slots_needed; - - GLuint uNumSrc = r700GetNumOperands(pAsm); - - GLboolean bSplitInst = GL_FALSE; - - if (1 == pAsm->D.dst.math) - { - is_single_scalar_operation = GL_TRUE; - number_of_scalar_operations = 1; - } - else - { - is_single_scalar_operation = GL_FALSE; - number_of_scalar_operations = 4; - } - - contiguous_slots_needed = 0; - - if(GL_TRUE == is_reduction_opcode(&(pAsm->D)) ) - { - contiguous_slots_needed = 4; - } - - initialize(pAsm); - - for (scalar_channel_index=0; - scalar_channel_index < number_of_scalar_operations; - scalar_channel_index++) - { - R700ALUInstruction* alu_instruction_ptr = (R700ALUInstruction*) CALLOC_STRUCT(R700ALUInstruction); - if (alu_instruction_ptr == NULL) - { - return GL_FALSE; - } - Init_R700ALUInstruction(alu_instruction_ptr); - - //src 0 - current_source_index = 0; - pcurrent_source = &(pAsm->S[0].src); - - if (GL_FALSE == assemble_alu_src(alu_instruction_ptr, - current_source_index, - pcurrent_source, - scalar_channel_index) ) - { - return GL_FALSE; - } - - if (uNumSrc > 1) - { - // Process source 1 - current_source_index = 1; - pcurrent_source = &(pAsm->S[current_source_index].src); - - if (GL_FALSE == assemble_alu_src(alu_instruction_ptr, - current_source_index, - pcurrent_source, - scalar_channel_index) ) - { - return GL_FALSE; - } - } - - //other bits - alu_instruction_ptr->m_Word0.f.index_mode = SQ_INDEX_LOOP; - - if( (is_single_scalar_operation == GL_TRUE) - || (GL_TRUE == bSplitInst) ) - { - alu_instruction_ptr->m_Word0.f.last = 1; - } - else - { - alu_instruction_ptr->m_Word0.f.last = (scalar_channel_index == 3) ? 1 : 0; - } - - alu_instruction_ptr->m_Word0.f.pred_sel = (pAsm->D.dst.pred_inv > 0) ? 1 : 0; - if(1 == pAsm->D.dst.predicated) - { - alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0x1; - alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0x1; - } - else - { - alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0x0; - alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0x0; - } - - // dst - if( (pAsm->D.dst.rtype == DST_REG_TEMPORARY) || - (pAsm->D.dst.rtype == DST_REG_OUT) ) - { - alu_instruction_ptr->m_Word1.f.dst_gpr = pAsm->D.dst.reg; - } - else - { - radeon_error("Only temp destination registers supported for ALU dest regs.\n"); - return GL_FALSE; - } - - alu_instruction_ptr->m_Word1.f.dst_rel = SQ_ABSOLUTE; //D.rtype - - if ( is_single_scalar_operation == GL_TRUE ) - { - // Override scalar_channel_index since only one scalar value will be written - if(pAsm->D.dst.writex) - { - scalar_channel_index = 0; - } - else if(pAsm->D.dst.writey) - { - scalar_channel_index = 1; - } - else if(pAsm->D.dst.writez) - { - scalar_channel_index = 2; - } - else if(pAsm->D.dst.writew) - { - scalar_channel_index = 3; - } - } - - alu_instruction_ptr->m_Word1.f.dst_chan = scalar_channel_index; - - alu_instruction_ptr->m_Word1.f.clamp = pAsm->D2.dst2.SaturateMode; - - if (pAsm->D.dst.op3) - { - //op3 - - alu_instruction_ptr->m_Word1_OP3.f.alu_inst = pAsm->D.dst.opcode; - - //There's 3rd src for op3 - current_source_index = 2; - pcurrent_source = &(pAsm->S[current_source_index].src); - - if ( GL_FALSE == assemble_alu_src(alu_instruction_ptr, - current_source_index, - pcurrent_source, - scalar_channel_index) ) - { - return GL_FALSE; - } - } - else - { - //op2 - if (pAsm->bR6xx) - { - alu_instruction_ptr->m_Word1_OP2.f6.alu_inst = pAsm->D.dst.opcode; - - alu_instruction_ptr->m_Word1_OP2.f6.src0_abs = 0x0; - alu_instruction_ptr->m_Word1_OP2.f6.src1_abs = 0x0; - - //alu_instruction_ptr->m_Word1_OP2.f6.update_execute_mask = 0x0; - //alu_instruction_ptr->m_Word1_OP2.f6.update_pred = 0x0; - switch (scalar_channel_index) - { - case 0: - alu_instruction_ptr->m_Word1_OP2.f6.write_mask = pAsm->D.dst.writex; - break; - case 1: - alu_instruction_ptr->m_Word1_OP2.f6.write_mask = pAsm->D.dst.writey; - break; - case 2: - alu_instruction_ptr->m_Word1_OP2.f6.write_mask = pAsm->D.dst.writez; - break; - case 3: - alu_instruction_ptr->m_Word1_OP2.f6.write_mask = pAsm->D.dst.writew; - break; - default: - alu_instruction_ptr->m_Word1_OP2.f6.write_mask = 1; //SQ_SEL_MASK; - break; - } - alu_instruction_ptr->m_Word1_OP2.f6.omod = SQ_ALU_OMOD_OFF; - } - else - { - alu_instruction_ptr->m_Word1_OP2.f.alu_inst = pAsm->D.dst.opcode; - - alu_instruction_ptr->m_Word1_OP2.f.src0_abs = 0x0; - alu_instruction_ptr->m_Word1_OP2.f.src1_abs = 0x0; - - //alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0x0; - //alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0x0; - switch (scalar_channel_index) - { - case 0: - alu_instruction_ptr->m_Word1_OP2.f.write_mask = pAsm->D.dst.writex; - break; - case 1: - alu_instruction_ptr->m_Word1_OP2.f.write_mask = pAsm->D.dst.writey; - break; - case 2: - alu_instruction_ptr->m_Word1_OP2.f.write_mask = pAsm->D.dst.writez; - break; - case 3: - alu_instruction_ptr->m_Word1_OP2.f.write_mask = pAsm->D.dst.writew; - break; - default: - alu_instruction_ptr->m_Word1_OP2.f.write_mask = 1; //SQ_SEL_MASK; - break; - } - alu_instruction_ptr->m_Word1_OP2.f.omod = SQ_ALU_OMOD_OFF; - } - } - - if(GL_FALSE == add_alu_instruction(pAsm, alu_instruction_ptr, contiguous_slots_needed) ) - { - return GL_FALSE; - } - - /* - * Judge the type of current instruction, is it vector or scalar - * instruction. - */ - if (is_single_scalar_operation) - { - if(GL_FALSE == check_scalar(pAsm, alu_instruction_ptr) ) - { - return GL_FALSE; - } - } - else - { - if(GL_FALSE == check_vector(pAsm, alu_instruction_ptr) ) - { - return GL_FALSE; - } - } - - contiguous_slots_needed = 0; - } - - return GL_TRUE; -} - GLboolean assemble_alu_instruction_literal(r700_AssemblerBase *pAsm, GLfloat * pLiteral) { R700ALUInstruction * alu_instruction_ptr; @@ -2987,44 +2757,6 @@ GLboolean next_ins(r700_AssemblerBase *pAsm) pAsm->S[2].bits = 0; pAsm->is_tex = GL_FALSE; pAsm->need_tex_barrier = GL_FALSE; - - return GL_TRUE; -} - -GLboolean next_ins2(r700_AssemblerBase *pAsm) -{ - struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); - - //ALU - if( GL_FALSE == assemble_alu_instruction2(pAsm) ) - { - radeon_error("Error assembling ALU instruction\n"); - return GL_FALSE; - } - - if(pAsm->D.dst.rtype == DST_REG_OUT) - { - if(pAsm->D.dst.op3) - { - // There is no mask for OP3 instructions, so all channels are written - pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number] = 0xF; - } - else - { - pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number] - |= (unsigned char)pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask; - } - } - - //reset for next inst. - pAsm->D.bits = 0; - pAsm->D2.bits = 0; - pAsm->S[0].bits = 0; - pAsm->S[1].bits = 0; - pAsm->S[2].bits = 0; - pAsm->is_tex = GL_FALSE; - pAsm->need_tex_barrier = GL_FALSE; - pAsm->D2.bits = 0; return GL_TRUE; @@ -4537,7 +4269,7 @@ GLboolean assemble_LOGIC_PRED(r700_AssemblerBase *pAsm, BITS opcode) pAsm->S[1].src.swizzlez = SQ_SEL_0; pAsm->S[1].src.swizzlew = SQ_SEL_0; - if( GL_FALSE == next_ins2(pAsm) ) + if( GL_FALSE == next_ins(pAsm) ) { return GL_FALSE; } @@ -5683,6 +5415,7 @@ GLboolean setRetInLoopFlag(r700_AssemblerBase *pAsm, GLuint flagValue) pAsm->D.dst.predicated = 0; /* in reloc where dislink flag init inst, only one slot alu inst is handled. */ pAsm->D.dst.math = 1; /* TODO : not math really, but one channel op, more generic alu assembler needed */ + pAsm->D2.dst2.index_mode = SQ_INDEX_LOOP; /* Check this ! */ #if 0 pAsm->S[0].src.rtype = SRC_REC_LITERAL; //pAsm->S[0].src.reg = 0; @@ -5707,7 +5440,7 @@ GLboolean setRetInLoopFlag(r700_AssemblerBase *pAsm, GLuint flagValue) pAsm->S[0].src.swizzlez = flagValue; pAsm->S[0].src.swizzlew = flagValue; - if( GL_FALSE == next_ins2(pAsm) ) + if( GL_FALSE == next_ins(pAsm) ) { return GL_FALSE; } @@ -5735,6 +5468,7 @@ GLboolean testFlag(r700_AssemblerBase *pAsm) pAsm->D2.dst2.literal = 1; pAsm->D2.dst2.SaturateMode = SATURATE_OFF; pAsm->D.dst.predicated = 1; + pAsm->D2.dst2.index_mode = SQ_INDEX_LOOP; /* Check this ! */ pAsm->S[0].src.rtype = DST_REG_TEMPORARY; pAsm->S[0].src.reg = pAsm->flag_reg_index; @@ -5768,7 +5502,7 @@ GLboolean testFlag(r700_AssemblerBase *pAsm) pAsm->S[1].src.swizzlez = SQ_SEL_1; pAsm->S[1].src.swizzlew = SQ_SEL_1; - if( GL_FALSE == next_ins2(pAsm) ) + if( GL_FALSE == next_ins(pAsm) ) { return GL_FALSE; } diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index cfa2610a55..cb7685464d 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -116,6 +116,7 @@ typedef struct PVSINSTtag { BITS literal :2; BITS SaturateMode :2; + BITS index_mode :3; } PVSINST; typedef struct PVSSRCtag @@ -529,10 +530,7 @@ GLboolean check_vector(r700_AssemblerBase* pAsm, GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm); GLboolean next_ins(r700_AssemblerBase *pAsm); -GLboolean next_ins2(r700_AssemblerBase *pAsm); -GLboolean assemble_alu_instruction2(r700_AssemblerBase *pAsm); - -/* TODO : merge next_ins/2/literal, assemble_alu_instruction/2/literal */ +/* TODO : merge next_ins/literal, assemble_alu_instruction/literal */ GLboolean next_ins_literal(r700_AssemblerBase *pAsm, GLfloat * pLiteral); GLboolean assemble_alu_instruction_literal(r700_AssemblerBase *pAsm, GLfloat * pLiteral); -- cgit v1.2.3 From 4e86cedf5b7ab98dbe59115fc325f9b3172d58be Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 7 Dec 2009 15:23:40 +0200 Subject: r600: add assembler support for literal(inline) constants and use it in cubemap instruction sequence for testing --- src/mesa/drivers/dri/r600/r700_assembler.c | 67 +++++++++++++++++++++--------- src/mesa/drivers/dri/r600/r700_assembler.h | 3 +- 2 files changed, 49 insertions(+), 21 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 8155d53eeb..c1e3377af6 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -1733,7 +1733,7 @@ GLboolean add_alu_instruction(r700_AssemblerBase* pAsm, } else { - pAsm->cf_current_alu_clause_ptr->m_Word1.f.count++; + pAsm->cf_current_alu_clause_ptr->m_Word1.f.count += (GetInstructionSize(alu_instruction_ptr->m_ShaderInstType) / 2); } // If this clause constains any instruction that is forward dependent on a TEX instruction, @@ -2168,6 +2168,10 @@ GLboolean check_vector(r700_AssemblerBase* pAsm, GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) { + R700ALUInstruction * alu_instruction_ptr; + R700ALUInstructionHalfLiteral * alu_instruction_ptr_hl; + R700ALUInstructionFullLiteral * alu_instruction_ptr_fl; + GLuint number_of_scalar_operations; GLboolean is_single_scalar_operation; GLuint scalar_channel_index; @@ -2238,18 +2242,39 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) contiguous_slots_needed = 4; } + contiguous_slots_needed += pAsm->D2.dst2.literal_slots; + initialize(pAsm); for (scalar_channel_index=0; scalar_channel_index < number_of_scalar_operations; scalar_channel_index++) { - R700ALUInstruction* alu_instruction_ptr = (R700ALUInstruction*) CALLOC_STRUCT(R700ALUInstruction); - if (alu_instruction_ptr == NULL) - { - return GL_FALSE; - } - Init_R700ALUInstruction(alu_instruction_ptr); + if(scalar_channel_index == (number_of_scalar_operations-1)) + { + switch(pAsm->D2.dst2.literal_slots) + { + case 0: + alu_instruction_ptr = (R700ALUInstruction*) CALLOC_STRUCT(R700ALUInstruction); + Init_R700ALUInstruction(alu_instruction_ptr); + break; + case 1: + alu_instruction_ptr_hl = (R700ALUInstructionHalfLiteral*) CALLOC_STRUCT(R700ALUInstructionHalfLiteral); + Init_R700ALUInstructionHalfLiteral(alu_instruction_ptr_hl, pAsm->C[0].f, pAsm->C[1].f); + alu_instruction_ptr = (R700ALUInstruction*)alu_instruction_ptr_hl; + break; + case 2: + alu_instruction_ptr_fl = (R700ALUInstructionFullLiteral*) CALLOC_STRUCT(R700ALUInstructionFullLiteral); + Init_R700ALUInstructionFullLiteral(alu_instruction_ptr_fl,pAsm->C[0].f, pAsm->C[1].f, pAsm->C[2].f, pAsm->C[3].f); + alu_instruction_ptr = (R700ALUInstruction*)alu_instruction_ptr_fl; + break; + }; + } + else + { + alu_instruction_ptr = (R700ALUInstruction*) CALLOC_STRUCT(R700ALUInstruction); + Init_R700ALUInstruction(alu_instruction_ptr); + } //src 0 current_source_index = 0; @@ -2447,12 +2472,12 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) } } - contiguous_slots_needed = 0; + contiguous_slots_needed -= 1; } return GL_TRUE; } - +#if 0 GLboolean assemble_alu_instruction_literal(r700_AssemblerBase *pAsm, GLfloat * pLiteral) { R700ALUInstruction * alu_instruction_ptr; @@ -2705,7 +2730,7 @@ GLboolean assemble_alu_instruction_literal(r700_AssemblerBase *pAsm, GLfloat * p return GL_TRUE; } - +#endif GLboolean next_ins(r700_AssemblerBase *pAsm) { struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); @@ -2758,11 +2783,11 @@ GLboolean next_ins(r700_AssemblerBase *pAsm) pAsm->is_tex = GL_FALSE; pAsm->need_tex_barrier = GL_FALSE; pAsm->D2.bits = 0; - + pAsm->C[0].bits = pAsm->C[1].bits = pAsm->C[2].bits = pAsm->C[3].bits = 0; return GL_TRUE; } -/* not work yet */ +#if 0/* not work yet */ GLboolean next_ins_literal(r700_AssemblerBase *pAsm, GLfloat * pLiteral) { struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); @@ -2784,7 +2809,7 @@ GLboolean next_ins_literal(r700_AssemblerBase *pAsm, GLfloat * pLiteral) pAsm->need_tex_barrier = GL_FALSE; return GL_TRUE; } - +#endif GLboolean assemble_math_function(r700_AssemblerBase* pAsm, BITS opcode) { BITS tmp; @@ -4472,13 +4497,14 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x * muladd has no writemask, have to use another temp - * also no support for imm constants, so add 1 here */ pAsm->D.dst.opcode = SQ_OP3_INST_MULADD; pAsm->D.dst.op3 = 1; setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); pAsm->D.dst.rtype = DST_REG_TEMPORARY; pAsm->D.dst.reg = tmp2; + pAsm->D2.dst2.literal_slots = 1; + pAsm->C[0].f = 1.5F; setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; @@ -4489,12 +4515,13 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) pAsm->S[1].src.reg = tmp1; setswizzle_PVSSRC(&(pAsm->S[1].src), SQ_SEL_Z); setaddrmode_PVSSRC(&(pAsm->S[2].src), ADDR_ABSOLUTE); - pAsm->S[2].src.rtype = SRC_REG_TEMPORARY; + /* immediate c 1.5 */ + pAsm->S[2].src.rtype = SRC_REC_LITERAL; pAsm->S[2].src.reg = tmp1; - setswizzle_PVSSRC(&(pAsm->S[2].src), SQ_SEL_1); + setswizzle_PVSSRC(&(pAsm->S[2].src), SQ_SEL_X); next_ins(pAsm); - +#if 0 /* ADD the remaining .5 */ pAsm->D.dst.opcode = SQ_OP2_INST_ADD; setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); @@ -4515,7 +4542,7 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) noswizzle_PVSSRC(&(pAsm->S[1].src)); next_ins(pAsm); - +#endif /* tmp1.xy = temp2.xy */ pAsm->D.dst.opcode = SQ_OP2_INST_MOV; setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); @@ -5410,7 +5437,7 @@ GLboolean setRetInLoopFlag(r700_AssemblerBase *pAsm, GLuint flagValue) pAsm->D.dst.writey = 0; pAsm->D.dst.writez = 0; pAsm->D.dst.writew = 0; - pAsm->D2.dst2.literal = 1; + pAsm->D2.dst2.literal_slots = 1; pAsm->D2.dst2.SaturateMode = SATURATE_OFF; pAsm->D.dst.predicated = 0; /* in reloc where dislink flag init inst, only one slot alu inst is handled. */ @@ -5465,7 +5492,7 @@ GLboolean testFlag(r700_AssemblerBase *pAsm) pAsm->D.dst.writey = 0; pAsm->D.dst.writez = 0; pAsm->D.dst.writew = 0; - pAsm->D2.dst2.literal = 1; + pAsm->D2.dst2.literal_slots = 1; pAsm->D2.dst2.SaturateMode = SATURATE_OFF; pAsm->D.dst.predicated = 1; pAsm->D2.dst2.index_mode = SQ_INDEX_LOOP; /* Check this ! */ diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index cb7685464d..3fe65654ca 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -114,7 +114,7 @@ typedef struct PVSDSTtag typedef struct PVSINSTtag { - BITS literal :2; + BITS literal_slots :2; BITS SaturateMode :2; BITS index_mode :3; } PVSINST; @@ -345,6 +345,7 @@ typedef struct r700_AssemblerBase PVSDWORD D; PVSDWORD D2; PVSDWORD S[3]; + PVSDWORD C[4]; unsigned int uLastPosUpdate; unsigned int last_cond_register; -- cgit v1.2.3 From 2b8b16f6a6ce6091d4939cfb567a65a52757dff0 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 7 Dec 2009 16:09:10 +0200 Subject: r600: use the new inline constants feature to fix COS --- src/mesa/drivers/dri/r600/r700_assembler.c | 37 +++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index c1e3377af6..660410f1ad 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -3041,7 +3041,42 @@ GLboolean assemble_CMP(r700_AssemblerBase *pAsm) GLboolean assemble_COS(r700_AssemblerBase *pAsm) { - return assemble_math_function(pAsm, SQ_OP2_INST_COS); + int tmp; + //return assemble_math_function(pAsm, SQ_OP2_INST_COS); + checkop1(pAsm); + + tmp = gethelpr(pAsm); + + pAsm->D.dst.opcode = SQ_OP2_INST_MUL; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + pAsm->D.dst.writex = 1; + + assemble_src(pAsm, 0, -1); + + pAsm->S[1].src.rtype = SRC_REC_LITERAL; + setswizzle_PVSSRC(&(pAsm->S[1].src), SQ_SEL_X); + pAsm->D2.dst2.literal_slots = 1; + pAsm->C[0].f = 1/(3.1415926535 * 2); + pAsm->C[1].f = 0.0F; + next_ins(pAsm); + + pAsm->D.dst.opcode = SQ_OP2_INST_COS; + pAsm->D.dst.math = 1; + + assemble_dst(pAsm); + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp; + setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X); + noneg_PVSSRC(&(pAsm->S[0].src)); + + next_ins(pAsm); + + return GL_TRUE; + } GLboolean assemble_DOT(r700_AssemblerBase *pAsm) -- cgit v1.2.3 From fbe06a9c2999a802333f8310156d58045d723799 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 7 Dec 2009 16:23:07 +0200 Subject: r600: fix SIN also --- src/mesa/drivers/dri/r600/r700_assembler.c | 15 +++++---------- src/mesa/drivers/dri/r600/r700_assembler.h | 3 +-- 2 files changed, 6 insertions(+), 12 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 660410f1ad..caccedabdf 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -3039,10 +3039,9 @@ GLboolean assemble_CMP(r700_AssemblerBase *pAsm) return GL_TRUE; } -GLboolean assemble_COS(r700_AssemblerBase *pAsm) +GLboolean assemble_TRIG(r700_AssemblerBase *pAsm, BITS opcode) { int tmp; - //return assemble_math_function(pAsm, SQ_OP2_INST_COS); checkop1(pAsm); tmp = gethelpr(pAsm); @@ -3062,7 +3061,7 @@ GLboolean assemble_COS(r700_AssemblerBase *pAsm) pAsm->C[1].f = 0.0F; next_ins(pAsm); - pAsm->D.dst.opcode = SQ_OP2_INST_COS; + pAsm->D.dst.opcode = opcode; pAsm->D.dst.math = 1; assemble_dst(pAsm); @@ -3075,6 +3074,7 @@ GLboolean assemble_COS(r700_AssemblerBase *pAsm) next_ins(pAsm); + //TODO - replicate if more channels set in WriteMask return GL_TRUE; } @@ -4192,11 +4192,6 @@ GLboolean assemble_RSQ(r700_AssemblerBase *pAsm) return assemble_math_function(pAsm, SQ_OP2_INST_RECIPSQRT_IEEE); } -GLboolean assemble_SIN(r700_AssemblerBase *pAsm) -{ - return assemble_math_function(pAsm, SQ_OP2_INST_SIN); -} - GLboolean assemble_SCS(r700_AssemblerBase *pAsm) { BITS tmp; @@ -5693,7 +5688,7 @@ GLboolean AssembleInstr(GLuint uiFirstInst, return GL_FALSE; break; case OPCODE_COS: - if ( GL_FALSE == assemble_COS(pR700AsmCode) ) + if ( GL_FALSE == assemble_TRIG(pR700AsmCode, SQ_OP2_INST_COS) ) return GL_FALSE; break; @@ -5790,7 +5785,7 @@ GLboolean AssembleInstr(GLuint uiFirstInst, return GL_FALSE; break; case OPCODE_SIN: - if ( GL_FALSE == assemble_SIN(pR700AsmCode) ) + if ( GL_FALSE == assemble_TRIG(pR700AsmCode, SQ_OP2_INST_SIN) ) return GL_FALSE; break; case OPCODE_SCS: diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index 3fe65654ca..f83206b726 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -548,7 +548,6 @@ GLboolean assemble_ADD(r700_AssemblerBase *pAsm); GLboolean assemble_ARL(r700_AssemblerBase *pAsm); GLboolean assemble_BAD(char *opcode_str); GLboolean assemble_CMP(r700_AssemblerBase *pAsm); -GLboolean assemble_COS(r700_AssemblerBase *pAsm); GLboolean assemble_DOT(r700_AssemblerBase *pAsm); GLboolean assemble_DST(r700_AssemblerBase *pAsm); GLboolean assemble_EX2(r700_AssemblerBase *pAsm); @@ -569,12 +568,12 @@ GLboolean assemble_MUL(r700_AssemblerBase *pAsm); GLboolean assemble_POW(r700_AssemblerBase *pAsm); GLboolean assemble_RCP(r700_AssemblerBase *pAsm); GLboolean assemble_RSQ(r700_AssemblerBase *pAsm); -GLboolean assemble_SIN(r700_AssemblerBase *pAsm); GLboolean assemble_SCS(r700_AssemblerBase *pAsm); GLboolean assemble_SGE(r700_AssemblerBase *pAsm); GLboolean assemble_LOGIC(r700_AssemblerBase *pAsm, BITS opcode); GLboolean assemble_LOGIC_PRED(r700_AssemblerBase *pAsm, BITS opcode); +GLboolean assemble_TRIG(r700_AssemblerBase *pAsm, BITS opcode); GLboolean assemble_SLT(r700_AssemblerBase *pAsm); GLboolean assemble_STP(r700_AssemblerBase *pAsm); -- cgit v1.2.3 From 0f854105f5a430ab36281c9bed530eccb8b8f44c Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 7 Dec 2009 16:27:05 +0200 Subject: r600: remove (now) dead code --- src/mesa/drivers/dri/r600/r700_assembler.c | 301 +---------------------------- src/mesa/drivers/dri/r600/r700_assembler.h | 4 - 2 files changed, 2 insertions(+), 303 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index caccedabdf..dd1199756d 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -2477,260 +2477,7 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) return GL_TRUE; } -#if 0 -GLboolean assemble_alu_instruction_literal(r700_AssemblerBase *pAsm, GLfloat * pLiteral) -{ - R700ALUInstruction * alu_instruction_ptr; - R700ALUInstructionHalfLiteral * alu_instruction_ptr_hl; - R700ALUInstructionFullLiteral * alu_instruction_ptr_fl; - - GLuint number_of_scalar_operations; - GLboolean is_single_scalar_operation; - GLuint scalar_channel_index; - - GLuint contiguous_slots_needed; - GLuint lastInstruction; - GLuint not_masked[4]; - - GLuint uNumSrc = r700GetNumOperands(pAsm); - - GLboolean bSplitInst = GL_FALSE; - - number_of_scalar_operations = 0; - contiguous_slots_needed = 0; - - if(1 == pAsm->D.dst.writew) - { - lastInstruction = 3; - number_of_scalar_operations++; - not_masked[3] = 1; - } - else - { - not_masked[3] = 0; - } - if(1 == pAsm->D.dst.writez) - { - lastInstruction = 2; - number_of_scalar_operations++; - not_masked[2] = 1; - } - else - { - not_masked[2] = 0; - } - if(1 == pAsm->D.dst.writey) - { - lastInstruction = 1; - number_of_scalar_operations++; - not_masked[1] = 1; - } - else - { - not_masked[1] = 0; - } - if(1 == pAsm->D.dst.writex) - { - lastInstruction = 0; - number_of_scalar_operations++; - not_masked[0] = 1; - } - else - { - not_masked[0] = 0; - } - - if(GL_TRUE == is_reduction_opcode(&(pAsm->D)) ) - { - contiguous_slots_needed = 4; - } - else - { - contiguous_slots_needed = number_of_scalar_operations; - } - - if(1 == pAsm->D2.dst2.literal) - { - contiguous_slots_needed += 1; - } - else if(2 == pAsm->D2.dst2.literal) - { - contiguous_slots_needed += 2; - } - - initialize(pAsm); - - for (scalar_channel_index=0; scalar_channel_index < 4; scalar_channel_index++) - { - if(0 == not_masked[scalar_channel_index]) - { - continue; - } - - if(scalar_channel_index == lastInstruction) - { - switch (pAsm->D2.dst2.literal) - { - case 0: - alu_instruction_ptr = (R700ALUInstruction*) CALLOC_STRUCT(R700ALUInstruction); - if (alu_instruction_ptr == NULL) - { - return GL_FALSE; - } - Init_R700ALUInstruction(alu_instruction_ptr); - break; - case 1: - alu_instruction_ptr_hl = (R700ALUInstructionHalfLiteral*) CALLOC_STRUCT(R700ALUInstructionHalfLiteral); - if (alu_instruction_ptr_hl == NULL) - { - return GL_FALSE; - } - Init_R700ALUInstructionHalfLiteral(alu_instruction_ptr_hl, pLiteral[0], pLiteral[1]); - alu_instruction_ptr = (R700ALUInstruction*)alu_instruction_ptr_hl; - break; - case 2: - alu_instruction_ptr_fl = (R700ALUInstructionFullLiteral*) CALLOC_STRUCT(R700ALUInstructionFullLiteral); - if (alu_instruction_ptr_fl == NULL) - { - return GL_FALSE; - } - Init_R700ALUInstructionFullLiteral(alu_instruction_ptr_fl, pLiteral[0], pLiteral[1], pLiteral[2], pLiteral[3]); - alu_instruction_ptr = (R700ALUInstruction*)alu_instruction_ptr_fl; - break; - default: - break; - }; - } - else - { - alu_instruction_ptr = (R700ALUInstruction*) CALLOC_STRUCT(R700ALUInstruction); - if (alu_instruction_ptr == NULL) - { - return GL_FALSE; - } - Init_R700ALUInstruction(alu_instruction_ptr); - } - - //src 0 - if (GL_FALSE == assemble_alu_src(alu_instruction_ptr, - 0, - &(pAsm->S[0].src), - scalar_channel_index) ) - { - return GL_FALSE; - } - - if (uNumSrc > 1) - { - // Process source 1 - if (GL_FALSE == assemble_alu_src(alu_instruction_ptr, - 1, - &(pAsm->S[1].src), - scalar_channel_index) ) - { - return GL_FALSE; - } - } - - //other bits - alu_instruction_ptr->m_Word0.f.index_mode = SQ_INDEX_LOOP; - - if(scalar_channel_index == lastInstruction) - { - alu_instruction_ptr->m_Word0.f.last = 1; - } - - alu_instruction_ptr->m_Word0.f.pred_sel = 0x0; - if(1 == pAsm->D.dst.predicated) - { - alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0x1; - alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0x1; - } - else - { - alu_instruction_ptr->m_Word1_OP2.f.update_pred = 0; - alu_instruction_ptr->m_Word1_OP2.f.update_execute_mask = 0; - } - - // dst - if( (pAsm->D.dst.rtype == DST_REG_TEMPORARY) || - (pAsm->D.dst.rtype == DST_REG_OUT) ) - { - alu_instruction_ptr->m_Word1.f.dst_gpr = pAsm->D.dst.reg; - } - else - { - radeon_error("Only temp destination registers supported for ALU dest regs.\n"); - return GL_FALSE; - } - - alu_instruction_ptr->m_Word1.f.dst_rel = SQ_ABSOLUTE; //D.rtype - - alu_instruction_ptr->m_Word1.f.dst_chan = scalar_channel_index; - - alu_instruction_ptr->m_Word1.f.clamp = pAsm->D2.dst2.SaturateMode; - - if (pAsm->D.dst.op3) - { - //op3 - alu_instruction_ptr->m_Word1_OP3.f.alu_inst = pAsm->D.dst.opcode; - - //There's 3rd src for op3 - if ( GL_FALSE == assemble_alu_src(alu_instruction_ptr, - 2, - &(pAsm->S[2].src), - scalar_channel_index) ) - { - return GL_FALSE; - } - } - else - { - //op2 - if (pAsm->bR6xx) - { - alu_instruction_ptr->m_Word1_OP2.f6.alu_inst = pAsm->D.dst.opcode; - alu_instruction_ptr->m_Word1_OP2.f6.src0_abs = 0x0; - alu_instruction_ptr->m_Word1_OP2.f6.src1_abs = 0x0; - alu_instruction_ptr->m_Word1_OP2.f6.write_mask = 1; - alu_instruction_ptr->m_Word1_OP2.f6.omod = SQ_ALU_OMOD_OFF; - } - else - { - alu_instruction_ptr->m_Word1_OP2.f.alu_inst = pAsm->D.dst.opcode; - alu_instruction_ptr->m_Word1_OP2.f.src0_abs = 0x0; - alu_instruction_ptr->m_Word1_OP2.f.src1_abs = 0x0; - alu_instruction_ptr->m_Word1_OP2.f.write_mask = 1; - alu_instruction_ptr->m_Word1_OP2.f.omod = SQ_ALU_OMOD_OFF; - } - } - - if(GL_FALSE == add_alu_instruction(pAsm, alu_instruction_ptr, contiguous_slots_needed) ) - { - return GL_FALSE; - } - - if (1 == number_of_scalar_operations) - { - if(GL_FALSE == check_scalar(pAsm, alu_instruction_ptr) ) - { - return GL_FALSE; - } - } - else - { - if(GL_FALSE == check_vector(pAsm, alu_instruction_ptr) ) - { - return GL_FALSE; - } - } - contiguous_slots_needed -= 2; - } - - return GL_TRUE; -} -#endif GLboolean next_ins(r700_AssemblerBase *pAsm) { struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); @@ -2787,29 +2534,6 @@ GLboolean next_ins(r700_AssemblerBase *pAsm) return GL_TRUE; } -#if 0/* not work yet */ -GLboolean next_ins_literal(r700_AssemblerBase *pAsm, GLfloat * pLiteral) -{ - struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); - - //ALU - if( GL_FALSE == assemble_alu_instruction_literal(pAsm, pLiteral) ) - { - radeon_error("Error assembling ALU instruction\n"); - return GL_FALSE; - } - - //reset for next inst. - pAsm->D.bits = 0; - pAsm->D2.bits = 0; - pAsm->S[0].bits = 0; - pAsm->S[1].bits = 0; - pAsm->S[2].bits = 0; - pAsm->is_tex = GL_FALSE; - pAsm->need_tex_barrier = GL_FALSE; - return GL_TRUE; -} -#endif GLboolean assemble_math_function(r700_AssemblerBase* pAsm, BITS opcode) { BITS tmp; @@ -4533,8 +4257,6 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); pAsm->D.dst.rtype = DST_REG_TEMPORARY; pAsm->D.dst.reg = tmp2; - pAsm->D2.dst2.literal_slots = 1; - pAsm->C[0].f = 1.5F; setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; @@ -4546,33 +4268,14 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) setswizzle_PVSSRC(&(pAsm->S[1].src), SQ_SEL_Z); setaddrmode_PVSSRC(&(pAsm->S[2].src), ADDR_ABSOLUTE); /* immediate c 1.5 */ + pAsm->D2.dst2.literal_slots = 1; + pAsm->C[0].f = 1.5F; pAsm->S[2].src.rtype = SRC_REC_LITERAL; pAsm->S[2].src.reg = tmp1; setswizzle_PVSSRC(&(pAsm->S[2].src), SQ_SEL_X); next_ins(pAsm); -#if 0 - /* ADD the remaining .5 */ - pAsm->D.dst.opcode = SQ_OP2_INST_ADD; - setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); - pAsm->D.dst.rtype = DST_REG_TEMPORARY; - pAsm->D.dst.reg = tmp2; - pAsm->D.dst.writex = 1; - pAsm->D.dst.writey = 1; - pAsm->D.dst.writez = 0; - pAsm->D.dst.writew = 0; - setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); - pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; - pAsm->S[0].src.reg = tmp2; - noswizzle_PVSSRC(&(pAsm->S[0].src)); - setaddrmode_PVSSRC(&(pAsm->S[1].src), ADDR_ABSOLUTE); - pAsm->S[1].src.rtype = SRC_REG_TEMPORARY; - pAsm->S[1].src.reg = 252; // SQ_ALU_SRC_0_5 - noswizzle_PVSSRC(&(pAsm->S[1].src)); - - next_ins(pAsm); -#endif /* tmp1.xy = temp2.xy */ pAsm->D.dst.opcode = SQ_OP2_INST_MOV; setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index f83206b726..6dc44017eb 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -531,10 +531,6 @@ GLboolean check_vector(r700_AssemblerBase* pAsm, GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm); GLboolean next_ins(r700_AssemblerBase *pAsm); -/* TODO : merge next_ins/literal, assemble_alu_instruction/literal */ -GLboolean next_ins_literal(r700_AssemblerBase *pAsm, GLfloat * pLiteral); -GLboolean assemble_alu_instruction_literal(r700_AssemblerBase *pAsm, GLfloat * pLiteral); - GLboolean pops(r700_AssemblerBase *pAsm, GLuint pops); GLboolean jumpToOffest(r700_AssemblerBase *pAsm, GLuint pops, GLint offset); GLboolean setRetInLoopFlag(r700_AssemblerBase *pAsm, GLuint flagValue); -- cgit v1.2.3 From 629a648b059d8a2653b6a9cdf7f460533de0e1da Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 7 Dec 2009 17:22:03 +0200 Subject: r600: and finally fix SCS --- src/mesa/drivers/dri/r600/r700_assembler.c | 97 ++++++++++++++---------------- 1 file changed, 46 insertions(+), 51 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index dd1199756d..aed84fc3bd 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -2237,7 +2237,7 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) contiguous_slots_needed = 0; - if(GL_TRUE == is_reduction_opcode(&(pAsm->D)) ) + if(!is_single_scalar_operation) { contiguous_slots_needed = 4; } @@ -3920,68 +3920,63 @@ GLboolean assemble_SCS(r700_AssemblerBase *pAsm) { BITS tmp; - checkop1(pAsm); - - tmp = gethelpr(pAsm); - - // COS tmp.x, a.x - pAsm->D.dst.opcode = SQ_OP2_INST_COS; - pAsm->D.dst.math = 1; + checkop1(pAsm); - setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); - pAsm->D.dst.rtype = DST_REG_TEMPORARY; - pAsm->D.dst.reg = tmp; - pAsm->D.dst.writex = 1; + tmp = gethelpr(pAsm); + /* tmp.x = src /2*PI */ + pAsm->D.dst.opcode = SQ_OP2_INST_MUL; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = tmp; + pAsm->D.dst.writex = 1; - if( GL_FALSE == assemble_src(pAsm, 0, -1) ) - { - return GL_FALSE; - } + assemble_src(pAsm, 0, -1); - if ( GL_FALSE == next_ins(pAsm) ) - { - return GL_FALSE; - } + pAsm->S[1].src.rtype = SRC_REC_LITERAL; + setswizzle_PVSSRC(&(pAsm->S[1].src), SQ_SEL_X); + pAsm->D2.dst2.literal_slots = 1; + pAsm->C[0].f = 1/(3.1415926535 * 2); + pAsm->C[1].f = 0.0F; - // SIN tmp.y, a.x - pAsm->D.dst.opcode = SQ_OP2_INST_SIN; - pAsm->D.dst.math = 1; + next_ins(pAsm); - setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); - pAsm->D.dst.rtype = DST_REG_TEMPORARY; - pAsm->D.dst.reg = tmp; - pAsm->D.dst.writey = 1; + // COS dst.x, a.x + pAsm->D.dst.opcode = SQ_OP2_INST_COS; + pAsm->D.dst.math = 1; - if( GL_FALSE == assemble_src(pAsm, 0, -1) ) - { - return GL_FALSE; - } + assemble_dst(pAsm); + /* mask y */ + pAsm->D.dst.writey = 0; - if( GL_FALSE == next_ins(pAsm) ) - { - return GL_FALSE; - } + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp; + setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X); + noneg_PVSSRC(&(pAsm->S[0].src)); - // MOV dst.mask, tmp - pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + if ( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } - if( GL_FALSE == assemble_dst(pAsm) ) - { - return GL_FALSE; - } + // SIN dst.y, a.x + pAsm->D.dst.opcode = SQ_OP2_INST_SIN; + pAsm->D.dst.math = 1; - setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); - pAsm->S[0].src.rtype = DST_REG_TEMPORARY; - pAsm->S[0].src.reg = tmp; + assemble_dst(pAsm); + /* mask x */ + pAsm->D.dst.writex = 0; - noswizzle_PVSSRC(&(pAsm->S[0].src)); - pAsm->S[0].src.swizzlez = SQ_SEL_0; - pAsm->S[0].src.swizzlew = SQ_SEL_0; + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = tmp; + setswizzle_PVSSRC(&(pAsm->S[0].src), SQ_SEL_X); + noneg_PVSSRC(&(pAsm->S[0].src)); - if ( GL_FALSE == next_ins(pAsm) ) - { - return GL_FALSE; - } + if( GL_FALSE == next_ins(pAsm) ) + { + return GL_FALSE; + } return GL_TRUE; } -- cgit v1.2.3 From 33a120e4761a661736ea64a3efc2e3831ac5600a Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Wed, 9 Dec 2009 10:51:52 +0200 Subject: r600: fix state size prediction after dc0777d3 --- src/mesa/drivers/dri/r600/r700_chip.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index d8661b4439..dacc2ccc4c 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -1134,7 +1134,11 @@ static int check_blnd(GLcontext *ctx, struct radeon_state_atom *atom) count += 3; if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) { - for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) { + /* targets are enabled in r700SetRenderTarget but state + size is calculated before that. Until MRT's are done + hardcode target0 as enabled. */ + count += 3; + for (ui = 1; ui < R700_MAX_RENDER_TARGETS; ui++) { if (r700->render_target[ui].enabled) count += 3; } -- cgit v1.2.3 From 8927b72118f9433aafd0e811cfc1981215eb3c5f Mon Sep 17 00:00:00 2001 From: Richard Li Date: Wed, 9 Dec 2009 15:39:16 -0500 Subject: r600 : add pre-compile mesa shader calling interface, in order to handle complex built-in shader instructions. --- src/mesa/drivers/dri/r600/r700_assembler.c | 407 +++++++++++++++++++++++++++-- src/mesa/drivers/dri/r600/r700_assembler.h | 65 ++++- src/mesa/drivers/dri/r600/r700_fragprog.c | 25 +- src/mesa/drivers/dri/r600/r700_vertprog.c | 25 +- 4 files changed, 498 insertions(+), 24 deletions(-) (limited to 'src/mesa/drivers/dri/r600') diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index aed84fc3bd..e84f524525 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -32,6 +32,7 @@ #include "main/mtypes.h" #include "main/imports.h" +#include "shader/prog_parameter.h" #include "radeon_debug.h" #include "r600_context.h" @@ -41,6 +42,39 @@ #define USE_CF_FOR_CONTINUE_BREAK 1 #define USE_CF_FOR_POP_AFTER 1 +struct prog_instruction noise1_insts[12] = { + {OPCODE_BGNSUB , {{13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {13, 0, 15, 0, 8, 1672, 0}, 0, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0}, + {OPCODE_MOV , {{0, 0, 0, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {0, 0, 2, 0, 8, 1672, 0}, 0, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0}, + {OPCODE_MOV , {{8, 0, 0, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {0, 0, 4, 0, 8, 1672, 0}, 0, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0}, + {OPCODE_MOV , {{8, 0, 585, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {0, 0, 8, 0, 8, 1672, 0}, 0, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0}, + {OPCODE_SGT , {{0, 0, 585, 0, 0, 0}, {8, 0, 1170, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {0, 1, 1, 0, 8, 1672, 0}, 1, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0}, + {OPCODE_IF , {{13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {13, 0, 15, 0, 7, 0, 0}, 0, 0, 0, 1, 0, 0, 0, 15, 0, 0, 0}, + {OPCODE_MOV , {{0, 0, 1755, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {0, 0, 1, 0, 8, 1672, 0}, 0, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0}, + {OPCODE_RET , {{13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {13, 0, 15, 0, 8, 1672, 0}, 0, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0}, + {OPCODE_ENDIF , {{13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {13, 0, 15, 0, 8, 1672, 0}, 0, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0}, + {OPCODE_MOV , {{0, 0, 1170, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {0, 0, 1, 0, 8, 1672, 0}, 0, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0}, + {OPCODE_RET , {{13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {13, 0, 15, 0, 8, 1672, 0}, 0, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0}, + {OPCODE_ENDSUB , {{13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}, {13, 0, 1672, 0, 0, 0}}, {13, 0, 15, 0, 8, 1672, 0}, 0, 0, 0, 1, 0, 0, 0, -1, 0, 0, 0} +}; +float noise1_const[2][4] = { + {0.300000f, 0.900000f, 0.500000f, 0.300000f} +}; + +COMPILED_SUB noise1_presub = { + &(noise1_insts[0]), + 12, + 2, + 1, + 0, + &(noise1_const[0]), + SWIZZLE_X, + SWIZZLE_X, + SWIZZLE_X, + SWIZZLE_X, + {0,0,0}, + 0 +}; + BITS addrmode_PVSDST(PVSDST * pPVSDST) { return pPVSDST->addrmode0 | ((BITS)pPVSDST->addrmode1 << 1); @@ -330,14 +364,14 @@ GLuint GetSurfaceFormat(GLenum eType, GLuint nChannels, GLuint * pClient_size) return(format); } -unsigned int r700GetNumOperands(r700_AssemblerBase* pAsm) +unsigned int r700GetNumOperands(GLuint opcode, GLuint nIsOp3) { - if(pAsm->D.dst.op3) + if(nIsOp3 > 0) { return 3; } - switch (pAsm->D.dst.opcode) + switch (opcode) { case SQ_OP2_INST_ADD: case SQ_OP2_INST_KILLE: @@ -378,7 +412,7 @@ unsigned int r700GetNumOperands(r700_AssemblerBase* pAsm) return 1; default: radeon_error( - "Need instruction operand number for %x.\n", pAsm->D.dst.opcode); + "Need instruction operand number for %x.\n", opcode); }; return 3; @@ -500,6 +534,11 @@ int Init_r700_AssemblerBase(SHADER_PIPE_TYPE spt, r700_AssemblerBase* pAsm, R700 pAsm->unCFflags = 0; + pAsm->presubs = NULL; + pAsm->unPresubArraySize = 0; + pAsm->unNumPresub = 0; + pAsm->unCurNumILInsts = 0; + return 0; } @@ -2010,7 +2049,7 @@ GLboolean check_scalar(r700_AssemblerBase* pAsm, GLuint swizzle_key; - GLuint number_of_operands = r700GetNumOperands(pAsm); + GLuint number_of_operands = r700GetNumOperands(pAsm->D.dst.opcode, pAsm->D.dst.op3); for (src=0; srcD.dst.opcode, pAsm->D.dst.op3); for (src=0; srcD.dst.opcode, pAsm->D.dst.op3); //GLuint channel_swizzle, j; //GLuint chan_counter[4] = {0, 0, 0, 0}; //PVSSRC * pSource[3]; @@ -4968,7 +5007,7 @@ void add_return_inst(r700_AssemblerBase *pAsm) pAsm->cf_current_cf_clause_ptr->m_Word1.f.barrier = 0x1; } -GLboolean assemble_BGNSUB(r700_AssemblerBase *pAsm, GLint nILindex) +GLboolean assemble_BGNSUB(r700_AssemblerBase *pAsm, GLint nILindex, GLuint uiIL_Shift) { /* Put in sub */ if( (pAsm->unSubArrayPointer + 1) > pAsm->unSubArraySize ) @@ -4983,7 +5022,7 @@ GLboolean assemble_BGNSUB(r700_AssemblerBase *pAsm, GLint nILindex) pAsm->unSubArraySize += 10; } - pAsm->subs[pAsm->unSubArrayPointer].subIL_Offset = nILindex; + pAsm->subs[pAsm->unSubArrayPointer].subIL_Offset = nILindex + uiIL_Shift; pAsm->subs[pAsm->unSubArrayPointer].lstCFInstructions_local.pHead=NULL; pAsm->subs[pAsm->unSubArrayPointer].lstCFInstructions_local.pTail=NULL; pAsm->subs[pAsm->unSubArrayPointer].lstCFInstructions_local.uNumOfNode=0; @@ -5074,9 +5113,13 @@ GLboolean assemble_RET(r700_AssemblerBase *pAsm) GLboolean assemble_CAL(r700_AssemblerBase *pAsm, GLint nILindex, + GLuint uiIL_Shift, GLuint uiNumberInsts, - struct prog_instruction *pILInst) + struct prog_instruction *pILInst, + PRESUB_DESC * pPresubDesc) { + GLint uiIL_Offset; + pAsm->alu_x_opcode = SQ_CF_INST_ALU; if(GL_FALSE == add_cf_instruction(pAsm) ) @@ -5109,8 +5152,12 @@ GLboolean assemble_CAL(r700_AssemblerBase *pAsm, pAsm->unCallerArraySize += 10; } - pAsm->callers[pAsm->unCallerArrayPointer].subIL_Offset = nILindex; - pAsm->callers[pAsm->unCallerArrayPointer].cf_ptr = pAsm->cf_current_cf_clause_ptr; + uiIL_Offset = nILindex + uiIL_Shift; + pAsm->callers[pAsm->unCallerArrayPointer].subIL_Offset = uiIL_Offset; + pAsm->callers[pAsm->unCallerArrayPointer].cf_ptr = pAsm->cf_current_cf_clause_ptr; + + pAsm->callers[pAsm->unCallerArrayPointer].finale_cf_ptr = NULL; + pAsm->callers[pAsm->unCallerArrayPointer].prelude_cf_ptr = NULL; pAsm->unCallerArrayPointer++; @@ -5120,7 +5167,7 @@ GLboolean assemble_CAL(r700_AssemblerBase *pAsm, GLboolean bRet; for(j=0; junSubArrayPointer; j++) { - if(nILindex == pAsm->subs[j].subIL_Offset) + if(uiIL_Offset == pAsm->subs[j].subIL_Offset) { /* compiled before */ max = pAsm->subs[j].unStackDepthMax @@ -5138,7 +5185,7 @@ GLboolean assemble_CAL(r700_AssemblerBase *pAsm, pAsm->callers[pAsm->unCallerArrayPointer - 1].subDescIndex = pAsm->unSubArrayPointer; unSubID = pAsm->unSubArrayPointer; - bRet = AssembleInstr(nILindex, uiNumberInsts, pILInst, pAsm); + bRet = AssembleInstr(nILindex, uiIL_Shift, uiNumberInsts, pILInst, pAsm); if(GL_TRUE == bRet) { @@ -5148,6 +5195,8 @@ GLboolean assemble_CAL(r700_AssemblerBase *pAsm, { pAsm->CALLSTACK[pAsm->CALLSP].max = max; } + + pAsm->subs[unSubID].pPresubDesc = pPresubDesc; } return bRet; @@ -5313,6 +5362,7 @@ GLboolean breakLoopOnFlag(r700_AssemblerBase *pAsm, GLuint unFCSP) } GLboolean AssembleInstr(GLuint uiFirstInst, + GLuint uiIL_Shift, GLuint uiNumberInsts, struct prog_instruction *pILInst, r700_AssemblerBase *pR700AsmCode) @@ -5468,6 +5518,26 @@ GLboolean AssembleInstr(GLuint uiFirstInst, case OPCODE_MUL: if ( GL_FALSE == assemble_MUL(pR700AsmCode) ) return GL_FALSE; + break; + + case OPCODE_NOISE1: + { + callPreSub(pR700AsmCode, + GLSL_NOISE1, + &noise1_presub, + pILInst->DstReg.Index + pR700AsmCode->starting_temp_register_number, + 1); + radeon_error("noise1: not yet supported shader instruction\n"); + }; + break; + case OPCODE_NOISE2: + radeon_error("noise2: not yet supported shader instruction\n"); + break; + case OPCODE_NOISE3: + radeon_error("noise3: not yet supported shader instruction\n"); + break; + case OPCODE_NOISE4: + radeon_error("noise4: not yet supported shader instruction\n"); break; case OPCODE_POW: @@ -5653,7 +5723,7 @@ GLboolean AssembleInstr(GLuint uiFirstInst, break; case OPCODE_BGNSUB: - if( GL_FALSE == assemble_BGNSUB(pR700AsmCode, i) ) + if( GL_FALSE == assemble_BGNSUB(pR700AsmCode, i, uiIL_Shift) ) { return GL_FALSE; } @@ -5668,9 +5738,11 @@ GLboolean AssembleInstr(GLuint uiFirstInst, case OPCODE_CAL: if( GL_FALSE == assemble_CAL(pR700AsmCode, - pILInst[i].BranchTarget, + pILInst[i].BranchTarget, + uiIL_Shift, uiNumberInsts, - pILInst) ) + pILInst, + NULL) ) { return GL_FALSE; } @@ -5707,7 +5779,7 @@ GLboolean InitShaderProgram(r700_AssemblerBase * pAsm) return GL_TRUE; } -GLboolean RelocProgram(r700_AssemblerBase * pAsm) +GLboolean RelocProgram(r700_AssemblerBase * pAsm, struct gl_program * pILProg) { GLuint i; GLuint unCFoffset; @@ -5717,6 +5789,12 @@ GLboolean RelocProgram(r700_AssemblerBase * pAsm) R700ShaderInstruction * pInst; R700ControlFlowGenericClause * pCFInst; + R700ControlFlowALUClause * pCF_ALU; + R700ALUInstruction * pALU; + GLuint unConstOffset = 0; + GLuint unRegOffset; + GLuint unMinRegIndex; + plstCFmain = pAsm->CALLSTACK[0].plstCFInstructions_local; /* remove flags init if they are not used */ @@ -5762,6 +5840,11 @@ GLboolean RelocProgram(r700_AssemblerBase * pAsm) unCFoffset = plstCFmain->uNumOfNode; + if(NULL != pILProg->Parameters) + { + unConstOffset = pILProg->Parameters->NumParameters; + } + /* Reloc subs */ for(i=0; iunSubArrayPointer; i++) { @@ -5799,6 +5882,84 @@ GLboolean RelocProgram(r700_AssemblerBase * pAsm) pInst = pInst->pNextInst; }; + if(NULL != pAsm->subs[i].pPresubDesc) + { + GLuint uNumSrc; + + unMinRegIndex = pAsm->subs[i].pPresubDesc->pCompiledSub->MinRegIndex; + unRegOffset = pAsm->subs[i].pPresubDesc->maxStartReg; + unConstOffset += pAsm->subs[i].pPresubDesc->unConstantsStart; + + pInst = plstCFsub->pHead; + while(pInst) + { + if(SIT_CF_ALU == pInst->m_ShaderInstType) + { + pCF_ALU = (R700ControlFlowALUClause *)pInst; + + pALU = pCF_ALU->m_pLinkedALUInstruction; + for(int j=0; j<=pCF_ALU->m_Word1.f.count; j++) + { + pALU->m_Word1.f.dst_gpr = pALU->m_Word1.f.dst_gpr + unRegOffset - unMinRegIndex; + + if(pALU->m_Word0.f.src0_sel < SQ_ALU_SRC_GPR_SIZE) + { + pALU->m_Word0.f.src0_sel = pALU->m_Word0.f.src0_sel + unRegOffset - unMinRegIndex; + } + else if(pALU->m_Word0.f.src0_sel >= SQ_ALU_SRC_CFILE_BASE) + { + pALU->m_Word0.f.src0_sel += unConstOffset; + } + + if( ((pALU->m_Word1.val >> SQ_ALU_WORD1_OP3_ALU_INST_SHIFT) & 0x0000001F) + >= SQ_OP3_INST_MUL_LIT ) + { /* op3 : 3 srcs */ + if(pALU->m_Word1_OP3.f.src2_sel < SQ_ALU_SRC_GPR_SIZE) + { + pALU->m_Word1_OP3.f.src2_sel = pALU->m_Word1_OP3.f.src2_sel + unRegOffset - unMinRegIndex; + } + else if(pALU->m_Word1_OP3.f.src2_sel >= SQ_ALU_SRC_CFILE_BASE) + { + pALU->m_Word1_OP3.f.src2_sel += unConstOffset; + } + if(pALU->m_Word0.f.src1_sel < SQ_ALU_SRC_GPR_SIZE) + { + pALU->m_Word0.f.src1_sel = pALU->m_Word0.f.src1_sel + unRegOffset - unMinRegIndex; + } + else if(pALU->m_Word0.f.src1_sel >= SQ_ALU_SRC_CFILE_BASE) + { + pALU->m_Word0.f.src1_sel += unConstOffset; + } + } + else + { + if(pAsm->bR6xx) + { + uNumSrc = r700GetNumOperands(pALU->m_Word1_OP2.f6.alu_inst, 0); + } + else + { + uNumSrc = r700GetNumOperands(pALU->m_Word1_OP2.f.alu_inst, 0); + } + if(2 == uNumSrc) + { /* 2 srcs */ + if(pALU->m_Word0.f.src1_sel < SQ_ALU_SRC_GPR_SIZE) + { + pALU->m_Word0.f.src1_sel = pALU->m_Word0.f.src1_sel + unRegOffset - unMinRegIndex; + } + else if(pALU->m_Word0.f.src1_sel >= SQ_ALU_SRC_CFILE_BASE) + { + pALU->m_Word0.f.src1_sel += unConstOffset; + } + } + } + pALU = (R700ALUInstruction*)(pALU->pNextInst); + } + } + pInst = pInst->pNextInst; + }; + } + /* Put sub into main */ plstCFmain->pTail->pNextInst = plstCFsub->pHead; plstCFmain->pTail = plstCFsub->pTail; @@ -5812,11 +5973,216 @@ GLboolean RelocProgram(r700_AssemblerBase * pAsm) { pAsm->callers[i].cf_ptr->m_Word0.f.addr = pAsm->subs[pAsm->callers[i].subDescIndex].unCFoffset; + + if(NULL != pAsm->subs[pAsm->callers[i].subDescIndex].pPresubDesc) + { + unMinRegIndex = pAsm->subs[pAsm->callers[i].subDescIndex].pPresubDesc->pCompiledSub->MinRegIndex; + unRegOffset = pAsm->subs[pAsm->callers[i].subDescIndex].pPresubDesc->maxStartReg; + + if(NULL != pAsm->callers[i].prelude_cf_ptr) + { + pCF_ALU = (R700ControlFlowALUClause * )(pAsm->callers[i].prelude_cf_ptr); + pALU = pCF_ALU->m_pLinkedALUInstruction; + for(int j=0; j<=pCF_ALU->m_Word1.f.count; j++) + { + pALU->m_Word1.f.dst_gpr = pALU->m_Word1.f.dst_gpr + unRegOffset - unMinRegIndex; + pALU = (R700ALUInstruction*)(pALU->pNextInst); + } + } + if(NULL != pAsm->callers[i].finale_cf_ptr) + { + pCF_ALU = (R700ControlFlowALUClause * )(pAsm->callers[i].finale_cf_ptr); + pALU = pCF_ALU->m_pLinkedALUInstruction; + for(int j=0; j<=pCF_ALU->m_Word1.f.count; j++) + { + pALU->m_Word0.f.src0_sel = pALU->m_Word0.f.src0_sel + unRegOffset - unMinRegIndex; + pALU = (R700ALUInstruction*)(pALU->pNextInst); + } + } + } } return GL_TRUE; } +GLboolean callPreSub(r700_AssemblerBase* pAsm, + LOADABLE_SCRIPT_SIGNITURE scriptSigniture, + COMPILED_SUB * pCompiledSub, + GLshort uOutReg, + GLshort uNumValidSrc) +{ + /* save assemble context */ + GLuint starting_temp_register_number_save; + GLuint number_used_registers_save; + GLuint uFirstHelpReg_save; + GLuint uHelpReg_save; + GLuint uiCurInst_save; + struct prog_instruction *pILInst_save; + PRESUB_DESC * pPresubDesc; + GLboolean bRet; + int i; + + R700ControlFlowGenericClause* prelude_cf_ptr = NULL; + + /* copy srcs to presub inputs */ + pAsm->alu_x_opcode = SQ_CF_INST_ALU; + for(i=0; iD.dst.opcode = SQ_OP2_INST_MOV; + setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE); + pAsm->D.dst.rtype = DST_REG_TEMPORARY; + pAsm->D.dst.reg = pCompiledSub->srcRegIndex[i]; + pAsm->D.dst.writex = 1; + pAsm->D.dst.writey = 1; + pAsm->D.dst.writez = 1; + pAsm->D.dst.writew = 1; + + if( GL_FALSE == assemble_src(pAsm, i, 0) ) + { + return GL_FALSE; + } + + next_ins(pAsm); + } + if(uNumValidSrc > 0) + { + prelude_cf_ptr = pAsm->cf_current_alu_clause_ptr; + pAsm->alu_x_opcode = SQ_CF_INST_ALU; + } + + /* browse thro existing presubs. */ + for(i=0; iunNumPresub; i++) + { + if(pAsm->presubs[i].sptSigniture == scriptSigniture) + { + break; + } + } + + if(i == pAsm->unNumPresub) + { /* not loaded yet */ + /* save assemble context */ + number_used_registers_save = pAsm->number_used_registers; + uFirstHelpReg_save = pAsm->uFirstHelpReg; + uHelpReg_save = pAsm->uHelpReg; + starting_temp_register_number_save = pAsm->starting_temp_register_number; + pILInst_save = pAsm->pILInst; + uiCurInst_save = pAsm->uiCurInst; + + /* alloc in presub */ + if( (pAsm->unNumPresub + 1) > pAsm->unPresubArraySize ) + { + pAsm->presubs = (PRESUB_DESC*)_mesa_realloc( (void *)pAsm->presubs, + sizeof(PRESUB_DESC) * pAsm->unPresubArraySize, + sizeof(PRESUB_DESC) * (pAsm->unPresubArraySize + 4) ); + if(NULL == pAsm->presubs) + { + radeon_error("No memeory to allocate built in shader function description structures. \n"); + return GL_FALSE; + } + pAsm->unPresubArraySize += 4; + } + + pPresubDesc = &(pAsm->presubs[i]); + pPresubDesc->sptSigniture = scriptSigniture; + + /* constants offsets need to be final resolved at reloc. */ + if(0 == pAsm->unNumPresub) + { + pPresubDesc->unConstantsStart = 0; + } + else + { + pPresubDesc->unConstantsStart = pAsm->presubs[i-1].unConstantsStart + + pAsm->presubs[i-1].pCompiledSub->NumParameters; + } + + pPresubDesc->pCompiledSub = pCompiledSub; + + pPresubDesc->subIL_Shift = pAsm->unCurNumILInsts; + pPresubDesc->maxStartReg = uFirstHelpReg_save; + pAsm->unCurNumILInsts += pCompiledSub->NumInstructions; + + pAsm->unNumPresub++; + + /* setup new assemble context */ + pAsm->starting_temp_register_number = 0; + pAsm->number_used_registers = pCompiledSub->NumTemporaries; + pAsm->uFirstHelpReg = pAsm->number_used_registers; + pAsm->uHelpReg = pAsm->uFirstHelpReg; + + bRet = assemble_CAL(pAsm, + 0, + pPresubDesc->subIL_Shift, + pCompiledSub->NumInstructions, + pCompiledSub->Instructions, + pPresubDesc); + + + pPresubDesc->number_used_registers = pAsm->number_used_registers; + + /* restore assemble context */ + pAsm->number_used_registers = number_used_registers_save; + pAsm->uFirstHelpReg = uFirstHelpReg_save; + pAsm->uHelpReg = uHelpReg_save; + pAsm->starting_temp_register_number = starting_temp_register_number_save; + pAsm->pILInst = pILInst_save; + pAsm->uiCurInst = uiCurInst_save; + } + else + { /* was loaded */ + pPresubDesc = &(pAsm->presubs[i]); + + bRet = assemble_CAL(pAsm, + 0, + pPresubDesc->subIL_Shift, + pCompiledSub->NumInstructions, + pCompiledSub->Instructions, + pPresubDesc); + } + + if(GL_FALSE == bRet) + { + radeon_error("Shader presub assemble failed. \n"); + } + else + { + /* copy presub output to real dst */ + pAsm->alu_x_opcode = SQ_CF_INST_ALU; + pAsm->D.dst.opcode = SQ_OP2_INST_MOV; + + if( GL_FALSE == assemble_dst(pAsm) ) + { + return GL_FALSE; + } + + setaddrmode_PVSSRC(&(pAsm->S[0].src), ADDR_ABSOLUTE); + pAsm->S[0].src.rtype = SRC_REG_TEMPORARY; + pAsm->S[0].src.reg = pCompiledSub->dstRegIndex; + pAsm->S[0].src.swizzlex = pCompiledSub->outputSwizzleX; + pAsm->S[0].src.swizzley = pCompiledSub->outputSwizzleY; + pAsm->S[0].src.swizzlez = pCompiledSub->outputSwizzleZ; + pAsm->S[0].src.swizzlew = pCompiledSub->outputSwizzleW; + + next_ins(pAsm); + + pAsm->callers[pAsm->unCallerArrayPointer - 1].finale_cf_ptr = pAsm->cf_current_alu_clause_ptr; + pAsm->callers[pAsm->unCallerArrayPointer - 1].prelude_cf_ptr = prelude_cf_ptr; + pAsm->alu_x_opcode = SQ_CF_INST_ALU; + } + + if( (pPresubDesc->number_used_registers + pAsm->uFirstHelpReg) > pAsm->number_used_registers ) + { + pAsm->number_used_registers = pPresubDesc->number_used_registers + pAsm->uFirstHelpReg; + } + if(pAsm->uFirstHelpReg > pPresubDesc->maxStartReg) + { + pPresubDesc->maxStartReg = pAsm->uFirstHelpReg; + } + + return bRet; +} + GLboolean Process_Export(r700_AssemblerBase* pAsm, GLuint type, GLuint export_starting_index, @@ -6174,6 +6540,11 @@ GLboolean Clean_Up_Assembler(r700_AssemblerBase *pR700AsmCode) FREE(pR700AsmCode->callers); } + if(NULL != pR700AsmCode->presubs) + { + FREE(pR700AsmCode->presubs); + } + return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h index 6dc44017eb..6ef945dfda 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.h +++ b/src/mesa/drivers/dri/r600/r700_assembler.h @@ -34,6 +34,45 @@ #include "r700_shaderinst.h" #include "r700_shader.h" +typedef enum LOADABLE_SCRIPT_SIGNITURE +{ + GLSL_NOISE1 = 0x10000001, + GLSL_NOISE2 = 0x10000002, + GLSL_NOISE3 = 0x10000003, + GLSL_NOISE4 = 0x10000004 +}LOADABLE_SCRIPT_SIGNITURE; + +typedef struct COMPILED_SUB +{ + struct prog_instruction *Instructions; + GLuint NumInstructions; + GLuint NumTemporaries; + GLuint NumParameters; + GLuint MinRegIndex; + GLfloat (*ParameterValues)[4]; + GLbyte outputSwizzleX; + GLbyte outputSwizzleY; + GLbyte outputSwizzleZ; + GLbyte outputSwizzleW; + GLshort srcRegIndex[3]; + GLushort dstRegIndex; +}COMPILED_SUB; + +typedef struct PRESUB_DESCtag +{ + LOADABLE_SCRIPT_SIGNITURE sptSigniture; + GLint subIL_Shift; + struct prog_src_register InReg[3]; + struct prog_dst_register OutReg; + + GLushort maxStartReg; + GLushort number_used_registers; + + GLuint unConstantsStart; + + COMPILED_SUB * pCompiledSub; +} PRESUB_DESC; + typedef enum SHADER_PIPE_TYPE { SPT_VP = 0, @@ -296,6 +335,7 @@ typedef struct SUB_OFFSET GLint subIL_Offset; GLuint unCFoffset; GLuint unStackDepthMax; + PRESUB_DESC * pPresubDesc; TypedShaderList lstCFInstructions_local; } SUB_OFFSET; @@ -304,6 +344,9 @@ typedef struct CALLER_POINTER GLint subIL_Offset; GLint subDescIndex; R700ControlFlowGenericClause* cf_ptr; + + R700ControlFlowGenericClause* prelude_cf_ptr; + R700ControlFlowGenericClause* finale_cf_ptr; } CALLER_POINTER; #define SQ_MAX_CALL_DEPTH 0x00000020 @@ -437,6 +480,11 @@ typedef struct r700_AssemblerBase GLuint unCFflags; + PRESUB_DESC * presubs; + GLuint unPresubArraySize; + GLuint unNumPresub; + GLuint unCurNumILInsts; + } r700_AssemblerBase; //Internal use @@ -458,7 +506,7 @@ BITS is_depth_component_exported(OUT_FRAGMENT_FMT_0* pFPOutFmt) ; GLboolean is_reduction_opcode(PVSDWORD * dest); GLuint GetSurfaceFormat(GLenum eType, GLuint nChannels, GLuint * pClient_size); -unsigned int r700GetNumOperands(r700_AssemblerBase* pAsm); +unsigned int r700GetNumOperands(GLuint opcode, GLuint nIsOp3); GLboolean IsTex(gl_inst_opcode Opcode); GLboolean IsAlu(gl_inst_opcode Opcode); @@ -585,13 +633,15 @@ GLboolean assemble_BRK(r700_AssemblerBase *pAsm); GLboolean assemble_COND(r700_AssemblerBase *pAsm); GLboolean assemble_ENDLOOP(r700_AssemblerBase *pAsm); -GLboolean assemble_BGNSUB(r700_AssemblerBase *pAsm, GLint nILindex); +GLboolean assemble_BGNSUB(r700_AssemblerBase *pAsm, GLint nILindex, GLuint uiIL_Shift); GLboolean assemble_ENDSUB(r700_AssemblerBase *pAsm); GLboolean assemble_RET(r700_AssemblerBase *pAsm); GLboolean assemble_CAL(r700_AssemblerBase *pAsm, GLint nILindex, + GLuint uiIL_Offest, GLuint uiNumberInsts, - struct prog_instruction *pILInst); + struct prog_instruction *pILInst, + PRESUB_DESC * pPresubDesc); GLboolean Process_Export(r700_AssemblerBase* pAsm, GLuint type, @@ -602,16 +652,23 @@ GLboolean Process_Export(r700_AssemblerBase* pAsm, GLboolean Move_Depth_Exports_To_Correct_Channels(r700_AssemblerBase *pAsm, BITS depth_channel_select); +GLboolean callPreSub(r700_AssemblerBase* pAsm, + LOADABLE_SCRIPT_SIGNITURE scriptSigniture, + /* struct prog_instruction ** pILInstParent, */ + COMPILED_SUB * pCompiledSub, + GLshort uOutReg, + GLshort uNumValidSrc); //Interface GLboolean AssembleInstr(GLuint uiFirstInst, + GLuint uiIL_Shift, GLuint uiNumberInsts, struct prog_instruction *pILInst, r700_AssemblerBase *pR700AsmCode); GLboolean Process_Fragment_Exports(r700_AssemblerBase *pR700AsmCode, GLbitfield OutputsWritten); GLboolean Process_Vertex_Exports(r700_AssemblerBase *pR700AsmCode, GLbitfield OutputsWritten); -GLboolean RelocProgram(r700_AssemblerBase * pAsm); +GLboolean RelocProgram(r700_AssemblerBase * pAsm, struct gl_program * pILProg); GLboolean InitShaderProgram(r700_AssemblerBase * pAsm); int Init_r700_AssemblerBase(SHADER_PIPE_TYPE spt, r700_AssemblerBase* pAsm, R700_Shader* pShader); diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index 8eb439a951..d15f013710 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -325,7 +325,11 @@ GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp, { fp->r700AsmCode.SamplerUnits[i] = fp->mesa_program.Base.SamplerUnits[i]; } + + fp->r700AsmCode.unCurNumILInsts = mesa_fp->Base.NumInstructions; + if( GL_FALSE == AssembleInstr(0, + 0, mesa_fp->Base.NumInstructions, &(mesa_fp->Base.Instructions[0]), &(fp->r700AsmCode)) ) @@ -338,7 +342,7 @@ GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp, return GL_FALSE; } - if( GL_FALSE == RelocProgram(&(fp->r700AsmCode)) ) + if( GL_FALSE == RelocProgram(&(fp->r700AsmCode), &(mesa_fp->Base)) ) { return GL_FALSE; } @@ -620,6 +624,25 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) } else r700->ps.num_consts = 0; + COMPILED_SUB * pCompiledSub; + GLuint uj; + GLuint unConstOffset = r700->ps.num_consts; + for(ui=0; uiunNumPresub; ui++) + { + pCompiledSub = pAsm->presubs[ui].pCompiledSub; + + r700->ps.num_consts += pCompiledSub->NumParameters; + + for(uj=0; ujNumParameters; uj++) + { + r700->ps.consts[uj + unConstOffset][0].f32All = pCompiledSub->ParameterValues[uj][0]; + r700->ps.consts[uj + unConstOffset][1].f32All = pCompiledSub->ParameterValues[uj][1]; + r700->ps.consts[uj + unConstOffset][2].f32All = pCompiledSub->ParameterValues[uj][2]; + r700->ps.consts[uj + unConstOffset][3].f32All = pCompiledSub->ParameterValues[uj][3]; + } + unConstOffset += pCompiledSub->NumParameters; + } + return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index 759b74dc7e..90fac078ff 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -341,7 +341,11 @@ struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, { vp->r700AsmCode.SamplerUnits[i] = vp->mesa_program->Base.SamplerUnits[i]; } + + vp->r700AsmCode.unCurNumILInsts = vp->mesa_program->Base.NumInstructions; + if(GL_FALSE == AssembleInstr(0, + 0, vp->mesa_program->Base.NumInstructions, &(vp->mesa_program->Base.Instructions[0]), &(vp->r700AsmCode)) ) @@ -354,7 +358,7 @@ struct r700_vertex_program* r700TranslateVertexShader(GLcontext *ctx, return NULL; } - if( GL_FALSE == RelocProgram(&(vp->r700AsmCode)) ) + if( GL_FALSE == RelocProgram(&(vp->r700AsmCode), &(vp->mesa_program->Base)) ) { return GL_FALSE; } @@ -671,5 +675,24 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) } else r700->vs.num_consts = 0; + COMPILED_SUB * pCompiledSub; + GLuint uj; + GLuint unConstOffset = r700->vs.num_consts; + for(ui=0; uir700AsmCode.unNumPresub; ui++) + { + pCompiledSub = vp->r700AsmCode.presubs[ui].pCompiledSub; + + r700->vs.num_consts += pCompiledSub->NumParameters; + + for(uj=0; ujNumParameters; uj++) + { + r700->vs.consts[uj + unConstOffset][0].f32All = pCompiledSub->ParameterValues[uj][0]; + r700->vs.consts[uj + unConstOffset][1].f32All = pCompiledSub->ParameterValues[uj][1]; + r700->vs.consts[uj + unConstOffset][2].f32All = pCompiledSub->ParameterValues[uj][2]; + r700->vs.consts[uj + unConstOffset][3].f32All = pCompiledSub->ParameterValues[uj][3]; + } + unConstOffset += pCompiledSub->NumParameters; + } + return GL_TRUE; } -- cgit v1.2.3