From 23d3559bd4ece1fcab5513ebdaa38600d6654374 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 12 Feb 2009 22:38:10 +1000
Subject: radeon: renaming and headers cleanup

---
 .../drivers/dri/radeon/radeon_common_context.h     | 513 +++++++++++++++++++++
 1 file changed, 513 insertions(+)
 create mode 100644 src/mesa/drivers/dri/radeon/radeon_common_context.h

(limited to 'src/mesa/drivers/dri/radeon/radeon_common_context.h')

diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
new file mode 100644
index 0000000000..b88aeab051
--- /dev/null
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -0,0 +1,513 @@
+
+#ifndef COMMON_CONTEXT_H
+#define COMMON_CONTEXT_H
+
+#include "main/mm.h"
+#include "math/m_vector.h"
+#include "texmem.h"
+#include "tnl/t_context.h"
+#include "main/colormac.h"
+
+#include "radeon_screen.h"
+#include "radeon_drm.h"
+#include "dri_util.h"
+#include "tnl/t_vertex.h"
+
+/* This union is used to avoid warnings/miscompilation
+   with float to uint32_t casts due to strict-aliasing */
+typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
+
+struct radeon_context;
+typedef struct radeon_context radeonContextRec;
+typedef struct radeon_context *radeonContextPtr;
+
+
+#define TEX_0   0x1
+#define TEX_1   0x2
+#define TEX_2   0x4
+#define TEX_3	0x8
+#define TEX_4	0x10
+#define TEX_5	0x20
+
+/* Rasterizing fallbacks */
+/* See correponding strings in r200_swtcl.c */
+#define RADEON_FALLBACK_TEXTURE		0x0001
+#define RADEON_FALLBACK_DRAW_BUFFER	0x0002
+#define RADEON_FALLBACK_STENCIL		0x0004
+#define RADEON_FALLBACK_RENDER_MODE	0x0008
+#define RADEON_FALLBACK_BLEND_EQ	0x0010
+#define RADEON_FALLBACK_BLEND_FUNC	0x0020
+#define RADEON_FALLBACK_DISABLE 	0x0040
+#define RADEON_FALLBACK_BORDER_MODE	0x0080
+
+#define R200_FALLBACK_TEXTURE           0x01
+#define R200_FALLBACK_DRAW_BUFFER       0x02
+#define R200_FALLBACK_STENCIL           0x04
+#define R200_FALLBACK_RENDER_MODE       0x08
+#define R200_FALLBACK_DISABLE           0x10
+#define R200_FALLBACK_BORDER_MODE       0x20
+
+#define RADEON_TCL_FALLBACK_RASTER            0x1 /* rasterization */
+#define RADEON_TCL_FALLBACK_UNFILLED          0x2 /* unfilled tris */
+#define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE     0x4 /* twoside tris */
+#define RADEON_TCL_FALLBACK_MATERIAL          0x8 /* material in vb */
+#define RADEON_TCL_FALLBACK_TEXGEN_0          0x10 /* texgen, unit 0 */
+#define RADEON_TCL_FALLBACK_TEXGEN_1          0x20 /* texgen, unit 1 */
+#define RADEON_TCL_FALLBACK_TEXGEN_2          0x40 /* texgen, unit 2 */
+#define RADEON_TCL_FALLBACK_TCL_DISABLE       0x80 /* user disable */
+#define RADEON_TCL_FALLBACK_FOGCOORDSPEC      0x100 /* fogcoord, sep. spec light */
+
+/* The blit width for texture uploads
+ */
+#define BLIT_WIDTH_BYTES 1024
+
+/* Use the templated vertex format:
+ */
+#define COLOR_IS_RGBA
+#define TAG(x) radeon##x
+#include "tnl_dd/t_dd_vertex.h"
+#undef TAG
+
+struct radeon_colorbuffer_state {
+	GLuint clear;
+	int roundEnable;
+	struct radeon_renderbuffer *rrb;
+};
+
+struct radeon_depthbuffer_state {
+	GLuint clear;
+	GLfloat scale;
+	struct radeon_renderbuffer *rrb;
+};
+
+struct radeon_scissor_state {
+	drm_clip_rect_t rect;
+	GLboolean enabled;
+
+	GLuint numClipRects;	/* Cliprects active */
+	GLuint numAllocedClipRects;	/* Cliprects available */
+	drm_clip_rect_t *pClipRects;
+};
+
+struct radeon_stencilbuffer_state {
+	GLboolean hwBuffer;
+	GLuint clear;		/* rb3d_stencilrefmask value */
+};
+
+struct radeon_stipple_state {
+	GLuint mask[32];
+};
+
+struct radeon_state_atom {
+	struct radeon_state_atom *next, *prev;
+	const char *name;	/* for debug */
+	int cmd_size;		/* size in bytes */
+        GLuint idx;
+	GLuint is_tcl;
+        GLuint *cmd;		/* one or more cmd's */
+	GLuint *lastcmd;		/* one or more cmd's */
+	GLboolean dirty;	/* dirty-mark in emit_state_list */
+        int (*check) (GLcontext *, struct radeon_state_atom *atom); /* is this state active? */
+        void (*emit) (GLcontext *, struct radeon_state_atom *atom);
+};
+
+struct radeon_hw_state {
+  	/* Head of the linked list of state atoms. */
+	struct radeon_state_atom atomlist;
+	int max_state_size;	/* Number of bytes necessary for a full state emit. */
+	GLboolean is_dirty, all_dirty;
+};
+
+
+/* Texture related */
+typedef struct _radeon_texture_image radeon_texture_image;
+
+struct _radeon_texture_image {
+	struct gl_texture_image base;
+
+	/**
+	 * If mt != 0, the image is stored in hardware format in the
+	 * given mipmap tree. In this case, base.Data may point into the
+	 * mapping of the buffer object that contains the mipmap tree.
+	 *
+	 * If mt == 0, the image is stored in normal memory pointed to
+	 * by base.Data.
+	 */
+	struct _radeon_mipmap_tree *mt;
+	struct radeon_bo *bo;
+
+	int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */
+	int mtface; /** if mt != 0, this is the image's face in the mipmap tree */
+};
+
+
+static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image)
+{
+	return (radeon_texture_image*)image;
+}
+
+
+typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
+
+#define RADEON_TXO_MICRO_TILE               (1 << 3)
+
+/* Texture object in locally shared texture space.
+ */
+struct radeon_tex_obj {
+  //	driTextureObject base;
+	struct gl_texture_object base;
+	struct _radeon_mipmap_tree *mt;
+
+	/**
+	 * This is true if we've verified that the mipmap tree above is complete
+	 * and so on.
+	 */
+	GLboolean validated;
+
+	GLuint override_offset;
+	GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
+	GLuint tile_bits;	/* hw texture tile bits used on this texture */
+        struct radeon_bo *bo;
+
+	GLuint bufAddr;		/* Offset to start of locally
+				   shared texture block */
+
+	GLuint dirty_state;	/* Flags (1 per texunit) for
+				   whether or not this texobj
+				   has dirty hardware state
+				   (pp_*) that needs to be
+				   brought into the
+				   texunit. */
+
+	drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
+	/* Six, for the cube faces */
+
+
+
+	GLuint pp_txfilter;	/* hardware register values */
+	GLuint pp_txformat;
+        GLuint pp_txformat_x;
+	GLuint pp_txoffset;	/* Image location in texmem.
+				   All cube faces follow. */
+	GLuint pp_txsize;	/* npot only */
+	GLuint pp_txpitch;	/* npot only */
+	GLuint pp_border_color;
+	GLuint pp_cubic_faces;	/* cube face 1,2,3,4 log2 sizes */
+
+        GLuint pp_txfilter_1;	/*  r300 */
+
+	GLboolean border_fallback;
+
+
+};
+
+static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj)
+{
+	return (radeonTexObj*)texObj;
+}
+
+/* Need refcounting on dma buffers:
+ */
+struct radeon_dma_buffer {
+	int refcount;		/* the number of retained regions in buf */
+	drmBufPtr buf;
+};
+
+struct radeon_aos {
+	struct radeon_bo *bo; /** Buffer object where vertex data is stored */
+	int offset; /** Offset into buffer object, in bytes */
+	int components; /** Number of components per vertex */
+	int stride; /** Stride in dwords (may be 0 for repeating) */
+	int count; /** Number of vertices */
+};
+
+struct radeon_dma {
+        /* Active dma region.  Allocations for vertices and retained
+         * regions come from here.  Also used for emitting random vertices,
+         * these may be flushed by calling flush_current();
+         */
+        struct radeon_bo *current; /** Buffer that DMA memory is allocated from */
+        int current_used; /** Number of bytes allocated and forgotten about */
+        int current_vertexptr; /** End of active vertex region */
+
+        /**
+         * If current_vertexptr != current_used then flush must be non-zero.
+         * flush must be called before non-active vertex allocations can be
+         * performed.
+         */
+        void (*flush) (GLcontext *);
+
+        /* Number of "in-flight" DMA buffers, i.e. the number of buffers
+         * for which a DISCARD command is currently queued in the command buffer
+.
+         */
+        GLuint nr_released_bufs;
+};
+
+/* radeon_swtcl.c
+ */
+struct radeon_swtcl_info {
+
+	GLuint RenderIndex;
+	GLuint vertex_size;
+	GLubyte *verts;
+
+	/* Fallback rasterization functions
+	 */
+	GLuint hw_primitive;
+	GLenum render_primitive;
+	GLuint numverts;
+
+	struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
+	GLuint vertex_attr_count;
+
+};
+
+struct radeon_ioctl {
+	GLuint vertex_offset;
+        struct radeon_bo *bo;
+	GLuint vertex_size;
+};
+
+#define RADEON_MAX_PRIMS 64
+
+struct radeon_prim {
+	GLuint start;
+	GLuint end;
+	GLuint prim;
+};
+
+static INLINE GLuint radeonPackColor(GLuint cpp,
+                                     GLubyte r, GLubyte g,
+                                     GLubyte b, GLubyte a)
+{
+	switch (cpp) {
+	case 2:
+		return PACK_COLOR_565(r, g, b);
+	case 4:
+		return PACK_COLOR_8888(a, r, g, b);
+	default:
+		return 0;
+	}
+}
+
+#define MAX_CMD_BUF_SZ (16*1024)
+
+#define MAX_DMA_BUF_SZ (64*1024)
+
+struct radeon_store {
+	GLuint statenr;
+	GLuint primnr;
+	char cmd_buf[MAX_CMD_BUF_SZ];
+	int cmd_used;
+	int elts_start;
+};
+
+struct radeon_dri_mirror {
+	__DRIcontextPrivate *context;	/* DRI context */
+	__DRIscreenPrivate *screen;	/* DRI screen */
+
+   /**
+    * DRI drawable bound to this context for drawing.
+    */
+	__DRIdrawablePrivate *drawable;
+
+   /**
+    * DRI drawable bound to this context for reading.
+    */
+	__DRIdrawablePrivate *readable;
+
+	drm_context_t hwContext;
+	drm_hw_lock_t *hwLock;
+	int fd;
+	int drmMinor;
+};
+
+#define DEBUG_TEXTURE	0x001
+#define DEBUG_STATE	0x002
+#define DEBUG_IOCTL	0x004
+#define DEBUG_PRIMS	0x008
+#define DEBUG_VERTS	0x010
+#define DEBUG_FALLBACKS	0x020
+#define DEBUG_VFMT	0x040
+#define DEBUG_CODEGEN	0x080
+#define DEBUG_VERBOSE	0x100
+#define DEBUG_DRI       0x200
+#define DEBUG_DMA       0x400
+#define DEBUG_SANITY    0x800
+#define DEBUG_SYNC      0x1000
+#define DEBUG_PIXEL     0x2000
+#define DEBUG_MEMORY    0x4000
+
+
+
+typedef void (*radeon_tri_func) (radeonContextPtr,
+				 radeonVertex *,
+				 radeonVertex *, radeonVertex *);
+
+typedef void (*radeon_line_func) (radeonContextPtr,
+				  radeonVertex *, radeonVertex *);
+
+typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
+
+struct radeon_state {
+	struct radeon_colorbuffer_state color;
+	struct radeon_depthbuffer_state depth;
+	struct radeon_scissor_state scissor;
+	struct radeon_stencilbuffer_state stencil;
+};
+
+/**
+ * This structure holds the command buffer while it is being constructed.
+ *
+ * The first batch of commands in the buffer is always the state that needs
+ * to be re-emitted when the context is lost. This batch can be skipped
+ * otherwise.
+ */
+struct radeon_cmdbuf {
+	struct radeon_cs_manager    *csm;
+	struct radeon_cs            *cs;
+	int size; /** # of dwords total */
+	unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */
+};
+
+struct radeon_context {
+   GLcontext *glCtx;
+   radeonScreenPtr radeonScreen;	/* Screen private DRI data */
+  
+   /* Texture object bookkeeping
+    */
+   unsigned              nr_heaps;
+   driTexHeap          * texture_heaps[ RADEON_NR_TEX_HEAPS ];
+   driTextureObject      swapped;
+   int                   texture_depth;
+   float                 initialMaxAnisotropy;
+
+  struct radeon_dma dma;
+  struct radeon_hw_state hw;
+   /* Rasterization and vertex state:
+    */
+   GLuint TclFallback;
+   GLuint Fallback;
+   GLuint NewGLState;
+   DECLARE_RENDERINPUTS(tnl_index_bitset);	/* index of bits for last tnl_install_attrs */
+
+   /* Page flipping */
+   GLuint doPageFlip;
+
+   /* Drawable, cliprect and scissor information */
+   GLuint numClipRects;	/* Cliprects for the draw buffer */
+   drm_clip_rect_t *pClipRects;
+   unsigned int lastStamp;
+   GLboolean lost_context;
+   drm_radeon_sarea_t *sarea;	/* Private SAREA data */
+
+   /* Mirrors of some DRI state */
+   struct radeon_dri_mirror dri;
+
+   /* Busy waiting */
+   GLuint do_usleeps;
+   GLuint do_irqs;
+   GLuint irqsEmitted;
+   drm_radeon_irq_wait_t iw;
+
+   /* buffer swap */
+   int64_t swap_ust;
+   int64_t swap_missed_ust;
+
+   GLuint swap_count;
+   GLuint swap_missed_count;
+
+   /* Derived state - for r300 only */
+   struct radeon_state state;
+
+   struct radeon_swtcl_info swtcl;
+   /* Configuration cache
+    */
+   driOptionCache optionCache;
+
+   struct radeon_cmdbuf cmdbuf;
+
+   struct {
+	   void (*get_lock)(radeonContextPtr radeon);
+	   void (*update_viewport_offset)(GLcontext *ctx);
+	   void (*update_draw_buffer)(GLcontext *ctx);
+	   void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa);
+	   void (*swtcl_flush)(GLcontext *ctx, uint32_t offset);
+	   void (*pre_emit_atoms)(radeonContextPtr rmesa);
+	   void (*pre_emit_state)(radeonContextPtr rmesa);
+   } vtbl;
+};
+
+#define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
+
+/**
+ * This function takes a float and packs it into a uint32_t
+ */
+static INLINE uint32_t radeonPackFloat32(float fl)
+{
+	union {
+		float fl;
+		uint32_t u;
+	} u;
+
+	u.fl = fl;
+	return u.u;
+}
+
+/* This is probably wrong for some values, I need to test this
+ * some more.  Range checking would be a good idea also..
+ *
+ * But it works for most things.  I'll fix it later if someone
+ * else with a better clue doesn't
+ */
+static INLINE uint32_t radeonPackFloat24(float f)
+{
+	float mantissa;
+	int exponent;
+	uint32_t float24 = 0;
+
+	if (f == 0.0)
+		return 0;
+
+	mantissa = frexpf(f, &exponent);
+
+	/* Handle -ve */
+	if (mantissa < 0) {
+		float24 |= (1 << 23);
+		mantissa = mantissa * -1.0;
+	}
+	/* Handle exponent, bias of 63 */
+	exponent += 62;
+	float24 |= (exponent << 16);
+	/* Kill 7 LSB of mantissa */
+	float24 |= (radeonPackFloat32(mantissa) & 0x7FFFFF) >> 7;
+
+	return float24;
+}
+
+GLboolean radeonInitContext(radeonContextPtr radeon,
+			    struct dd_function_table* functions,
+			    const __GLcontextModes * glVisual,
+			    __DRIcontextPrivate * driContextPriv,
+			    void *sharedContextPrivate);
+
+void radeonCleanupContext(radeonContextPtr radeon);
+GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv);
+void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable);
+GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
+			    __DRIdrawablePrivate * driDrawPriv,
+			    __DRIdrawablePrivate * driReadPriv);
+
+/* ================================================================
+ * Debugging:
+ */
+#define DO_DEBUG		1
+
+#if DO_DEBUG
+extern int RADEON_DEBUG;
+#else
+#define RADEON_DEBUG		0
+#endif
+
+#endif
-- 
cgit v1.2.3


From dc8a707c672918b88dd4135930bef60ed148d8ce Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 12 Feb 2009 23:52:51 +1000
Subject: radeon/r200/r300: make build with out libdrm_radeon installed for now

---
 src/mesa/drivers/dri/r200/Makefile                 |   2 +-
 src/mesa/drivers/dri/r200/r200_ioctl.h             |   2 +-
 src/mesa/drivers/dri/r200/r200_state.c             |   3 +-
 src/mesa/drivers/dri/r200/r200_swtcl.c             |   1 -
 src/mesa/drivers/dri/r300/Makefile                 |   2 +-
 src/mesa/drivers/dri/r300/r300_cmdbuf.c            |   4 +-
 src/mesa/drivers/dri/r300/r300_cmdbuf.h            |   1 -
 src/mesa/drivers/dri/r300/r300_context.c           |   2 +-
 src/mesa/drivers/dri/r300/r300_context.h           |   1 -
 src/mesa/drivers/dri/r300/r300_state.c             |   1 -
 src/mesa/drivers/dri/r300/r300_texstate.c          |   2 -
 src/mesa/drivers/dri/radeon/radeon_bo_drm.h        | 179 +++++++++++++++++++
 src/mesa/drivers/dri/radeon/radeon_bo_legacy.c     |   4 +-
 src/mesa/drivers/dri/radeon/radeon_bo_legacy.h     |   1 -
 src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h  |  35 ++++
 src/mesa/drivers/dri/radeon/radeon_buffer.h        |  49 -----
 src/mesa/drivers/dri/radeon/radeon_cmdbuf.h        |   2 +-
 src/mesa/drivers/dri/radeon/radeon_common.c        |   8 +-
 src/mesa/drivers/dri/radeon/radeon_common.h        |   1 -
 .../drivers/dri/radeon/radeon_common_context.h     |  16 ++
 src/mesa/drivers/dri/radeon/radeon_cs_drm.h        | 198 +++++++++++++++++++++
 src/mesa/drivers/dri/radeon/radeon_cs_legacy.c     |   5 +-
 src/mesa/drivers/dri/radeon/radeon_cs_legacy.h     |   1 -
 src/mesa/drivers/dri/radeon/radeon_ioctl.c         |   1 -
 src/mesa/drivers/dri/radeon/radeon_ioctl.h         |   2 +-
 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c   |   2 -
 src/mesa/drivers/dri/radeon/radeon_screen.c        |   5 +-
 src/mesa/drivers/dri/radeon/radeon_screen.h        |   1 -
 src/mesa/drivers/dri/radeon/radeon_span.c          |   2 -
 src/mesa/drivers/dri/radeon/radeon_span.h          |   2 -
 src/mesa/drivers/dri/radeon/radeon_state_init.c    |   1 -
 31 files changed, 442 insertions(+), 94 deletions(-)
 create mode 100644 src/mesa/drivers/dri/radeon/radeon_bo_drm.h
 create mode 100644 src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h
 delete mode 100644 src/mesa/drivers/dri/radeon/radeon_buffer.h
 create mode 100644 src/mesa/drivers/dri/radeon/radeon_cs_drm.h

(limited to 'src/mesa/drivers/dri/radeon/radeon_common_context.h')

diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile
index 4f626c0584..7b5fe95577 100644
--- a/src/mesa/drivers/dri/r200/Makefile
+++ b/src/mesa/drivers/dri/r200/Makefile
@@ -62,9 +62,9 @@ COMMON_SYMLINKS = \
 	radeon_cs_legacy.c \
 	radeon_bo_legacy.h \
 	radeon_cs_legacy.h \
+	radeon_bocs_wrapper.h \
 	radeon_span.h \
 	radeon_span.c \
-	radeon_buffer.h \
 	radeon_lock.c \
 	radeon_lock.h \
 	radeon_common.c \
diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h
index 777fdc38a5..950478e762 100644
--- a/src/mesa/drivers/dri/r200/r200_ioctl.h
+++ b/src/mesa/drivers/dri/r200/r200_ioctl.h
@@ -38,7 +38,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "main/simple_list.h"
 #include "radeon_dri.h"
 
-#include "radeon_cs_legacy.h"
+#include "radeon_bocs_wrapper.h"
 
 #include "xf86drm.h"
 #include "drm.h"
diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c
index 84b0d90c69..559985bc3f 100644
--- a/src/mesa/drivers/dri/r200/r200_state.c
+++ b/src/mesa/drivers/dri/r200/r200_state.c
@@ -47,8 +47,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "tnl/t_pipeline.h"
 #include "swrast_setup/swrast_setup.h"
 
-#include "radeon_buffer.h"
-#include "radeon_cs.h"
+#include "radeon_common.h"
 #include "radeon_mipmap_tree.h"
 #include "r200_context.h"
 #include "r200_ioctl.h"
diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c
index df786561e1..b006409987 100644
--- a/src/mesa/drivers/dri/r200/r200_swtcl.c
+++ b/src/mesa/drivers/dri/r200/r200_swtcl.c
@@ -48,7 +48,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "tnl/t_context.h"
 #include "tnl/t_pipeline.h"
 
-#include "radeon_bo.h"
 #include "r200_context.h"
 #include "r200_ioctl.h"
 #include "r200_state.h"
diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile
index e9264ce77a..20ee195fe7 100644
--- a/src/mesa/drivers/dri/r300/Makefile
+++ b/src/mesa/drivers/dri/r300/Makefile
@@ -75,11 +75,11 @@ COMMON_SYMLINKS = \
 	radeon_screen.h \
 	radeon_span.h \
 	radeon_span.c \
-	radeon_buffer.h \
 	radeon_bo_legacy.c \
 	radeon_cs_legacy.c \
 	radeon_bo_legacy.h \
 	radeon_cs_legacy.h \
+	radeon_bocs_wrapper.h \
 	radeon_lock.c \
 	radeon_lock.h \
 	radeon_common.c \
diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index d6acb39d9f..29b2c2eb25 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -44,17 +44,15 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "drm.h"
 #include "radeon_drm.h"
 
-#include "radeon_buffer.h"
 #include "r300_context.h"
 #include "r300_ioctl.h"
 #include "radeon_reg.h"
 #include "r300_reg.h"
 #include "r300_cmdbuf.h"
 #include "r300_emit.h"
+#include "radeon_bocs_wrapper.h"
 #include "radeon_mipmap_tree.h"
 #include "r300_state.h"
-#include "radeon_cs_legacy.h"
-#include "radeon_cs_gem.h"
 #include "radeon_reg.h"
 
 #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h
index ab5d50f58e..b7798eb97b 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h
@@ -37,7 +37,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define __R300_CMDBUF_H__
 
 #include "r300_context.h"
-#include "radeon_cs.h"
 
 extern void r300InitCmdBuf(r300ContextPtr r300);
 extern void r300DestroyCmdBuf(r300ContextPtr r300);
diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c
index e4dc37debc..449252a930 100644
--- a/src/mesa/drivers/dri/r300/r300_context.c
+++ b/src/mesa/drivers/dri/r300/r300_context.c
@@ -63,7 +63,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "r300_tex.h"
 #include "r300_emit.h"
 #include "r300_swtcl.h"
-#include "radeon_bo_legacy.h"
+#include "radeon_bocs_wrapper.h"
 
 
 #include "vblank.h"
diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h
index 0be3657249..6d3472722d 100644
--- a/src/mesa/drivers/dri/r300/r300_context.h
+++ b/src/mesa/drivers/dri/r300/r300_context.h
@@ -43,7 +43,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "dri_util.h"
 #include "texmem.h"
 #include "radeon_common.h"
-#include "radeon_bo.h"
 
 #include "main/macros.h"
 #include "main/mtypes.h"
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index 4258a61000..fe58ac00a8 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -53,7 +53,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "vbo/vbo.h"
 #include "tnl/tnl.h"
 
-#include "radeon_buffer.h"
 #include "r300_context.h"
 #include "r300_ioctl.h"
 #include "r300_state.h"
diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c
index 50ecc570bd..e5afff0d61 100644
--- a/src/mesa/drivers/dri/r300/r300_texstate.c
+++ b/src/mesa/drivers/dri/r300/r300_texstate.c
@@ -48,10 +48,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "r300_state.h"
 #include "r300_ioctl.h"
 #include "radeon_mipmap_tree.h"
-#include "radeon_cs.h"
 #include "r300_tex.h"
 #include "r300_reg.h"
-#include "radeon_buffer.h"
 
 #define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5			\
 			   || ((f) >= MESA_FORMAT_RGBA_FLOAT32 &&	\
diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_drm.h b/src/mesa/drivers/dri/radeon/radeon_bo_drm.h
new file mode 100644
index 0000000000..3cabdfc4e8
--- /dev/null
+++ b/src/mesa/drivers/dri/radeon/radeon_bo_drm.h
@@ -0,0 +1,179 @@
+/* 
+ * Copyright © 2008 Jérôme Glisse
+ * All Rights Reserved.
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
+ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ */
+/*
+ * Authors:
+ *      Jérôme Glisse <glisse@freedesktop.org>
+ */
+#ifndef RADEON_BO_H
+#define RADEON_BO_H
+
+#include <stdio.h>
+#include <stdint.h>
+#include "radeon_track.h"
+
+/* bo object */
+#define RADEON_BO_FLAGS_MACRO_TILE  1
+#define RADEON_BO_FLAGS_MICRO_TILE  2
+
+struct radeon_bo_manager;
+
+struct radeon_bo {
+    uint32_t                    alignment;
+    uint32_t                    handle;
+    uint32_t                    size;
+    uint32_t                    domains;
+    uint32_t                    flags;
+    unsigned                    cref;
+#ifdef RADEON_BO_TRACK
+    struct radeon_track         *track;
+#endif
+    void                        *ptr;
+    struct radeon_bo_manager    *bom;
+    uint32_t                    space_accounted;
+};
+
+/* bo functions */
+struct radeon_bo_funcs {
+    struct radeon_bo *(*bo_open)(struct radeon_bo_manager *bom,
+                                 uint32_t handle,
+                                 uint32_t size,
+                                 uint32_t alignment,
+                                 uint32_t domains,
+                                 uint32_t flags);
+    void (*bo_ref)(struct radeon_bo *bo);
+    struct radeon_bo *(*bo_unref)(struct radeon_bo *bo);
+    int (*bo_map)(struct radeon_bo *bo, int write);
+    int (*bo_unmap)(struct radeon_bo *bo);
+    int (*bo_wait)(struct radeon_bo *bo);
+};
+
+struct radeon_bo_manager {
+    struct radeon_bo_funcs  *funcs;
+    int                     fd;
+    struct radeon_tracker   tracker;
+};
+    
+static inline void _radeon_bo_debug(struct radeon_bo *bo,
+                                    const char *op,
+                                    const char *file,
+                                    const char *func,
+                                    int line)
+{
+    fprintf(stderr, "%s %p 0x%08X 0x%08X 0x%08X [%s %s %d]\n",
+            op, bo, bo->handle, bo->size, bo->cref, file, func, line);
+}
+
+static inline struct radeon_bo *_radeon_bo_open(struct radeon_bo_manager *bom,
+                                                uint32_t handle,
+                                                uint32_t size,
+                                                uint32_t alignment,
+                                                uint32_t domains,
+                                                uint32_t flags,
+                                                const char *file,
+                                                const char *func,
+                                                int line)
+{
+    struct radeon_bo *bo;
+
+    bo = bom->funcs->bo_open(bom, handle, size, alignment, domains, flags);
+#ifdef RADEON_BO_TRACK
+    if (bo) {
+        bo->track = radeon_tracker_add_track(&bom->tracker, bo->handle);
+        radeon_track_add_event(bo->track, file, func, "open", line);
+    }
+#endif
+    return bo;
+}
+
+static inline void _radeon_bo_ref(struct radeon_bo *bo,
+                                  const char *file,
+                                  const char *func,
+                                  int line)
+{
+    bo->cref++;
+#ifdef RADEON_BO_TRACK
+    radeon_track_add_event(bo->track, file, func, "ref", line); 
+#endif
+    bo->bom->funcs->bo_ref(bo);
+}
+
+static inline struct radeon_bo *_radeon_bo_unref(struct radeon_bo *bo,
+                                                 const char *file,
+                                                 const char *func,
+                                                 int line)
+{
+    bo->cref--;
+#ifdef RADEON_BO_TRACK
+    radeon_track_add_event(bo->track, file, func, "unref", line);
+    if (bo->cref <= 0) {
+        radeon_tracker_remove_track(&bo->bom->tracker, bo->track);
+        bo->track = NULL;
+    }
+#endif
+    return bo->bom->funcs->bo_unref(bo);
+}
+
+static inline int _radeon_bo_map(struct radeon_bo *bo,
+                                 int write,
+                                 const char *file,
+                                 const char *func,
+                                 int line)
+{
+    return bo->bom->funcs->bo_map(bo, write);
+}
+
+static inline int _radeon_bo_unmap(struct radeon_bo *bo,
+                                   const char *file,
+                                   const char *func,
+                                   int line)
+{
+    return bo->bom->funcs->bo_unmap(bo);
+}
+
+static inline int _radeon_bo_wait(struct radeon_bo *bo,
+                                  const char *file,
+                                  const char *func,
+                                  int line)
+{
+    return bo->bom->funcs->bo_wait(bo);
+}
+
+#define radeon_bo_open(bom, h, s, a, d, f)\
+    _radeon_bo_open(bom, h, s, a, d, f, __FILE__, __FUNCTION__, __LINE__)
+#define radeon_bo_ref(bo)\
+    _radeon_bo_ref(bo, __FILE__, __FUNCTION__, __LINE__)
+#define radeon_bo_unref(bo)\
+    _radeon_bo_unref(bo, __FILE__, __FUNCTION__, __LINE__)
+#define radeon_bo_map(bo, w)\
+    _radeon_bo_map(bo, w, __FILE__, __FUNCTION__, __LINE__)
+#define radeon_bo_unmap(bo)\
+    _radeon_bo_unmap(bo, __FILE__, __FUNCTION__, __LINE__)
+#define radeon_bo_debug(bo, opcode)\
+    _radeon_bo_debug(bo, opcode, __FILE__, __FUNCTION__, __LINE__)
+#define radeon_bo_wait(bo) \
+    _radeon_bo_wait(bo, __FILE__, __func__, __LINE__)
+
+#endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
index b7658353af..1d25887e69 100644
--- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
+++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
@@ -45,9 +45,9 @@
 
 #include "drm.h"
 #include "radeon_drm.h"
-#include "radeon_bo.h"
-#include "radeon_bo_legacy.h"
 #include "radeon_common.h"
+#include "radeon_bocs_wrapper.h"
+
 
 struct bo_legacy {
     struct radeon_bo    base;
diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h
index 575979cbec..9187cd7201 100644
--- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h
+++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h
@@ -32,7 +32,6 @@
 #ifndef RADEON_BO_LEGACY_H
 #define RADEON_BO_LEGACY_H
 
-#include "radeon_bo.h"
 #include "radeon_screen.h"
 
 void radeon_bo_legacy_pending(struct radeon_bo *bo, uint32_t pending);
diff --git a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h
new file mode 100644
index 0000000000..36dea3be7b
--- /dev/null
+++ b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h
@@ -0,0 +1,35 @@
+#ifndef RADEON_CS_WRAPPER_H
+#define RADEON_CS_WRAPPER_H
+
+#ifdef HAVE_LIBDRM_RADEON
+
+#include "radeon_bo.h"
+#include "radeon_bo_gem.h"
+#include "radeon_cs.h"
+#include "radeon_cs_gem.h"
+
+#else
+/* to be used to build locally in mesa with no libdrm bits */
+#include "../radeon/radeon_bo_drm.h"
+#include "../radeon/radeon_cs_drm.h"
+
+#define RADEON_GEM_DOMAIN_CPU 0x1   // Cached CPU domain
+#define RADEON_GEM_DOMAIN_GTT 0x2   // GTT or cache flushed
+#define RADEON_GEM_DOMAIN_VRAM 0x4  // VRAM domain
+
+static inline void *radeon_bo_manager_gem_ctor(int fd)
+{
+  return NULL;
+}
+
+static inline void radeon_bo_manager_gem_dtor(void *dummy)
+{
+}
+
+
+#endif
+
+#include "radeon_bo_legacy.h"
+#include "radeon_cs_legacy.h"
+
+#endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_buffer.h b/src/mesa/drivers/dri/radeon/radeon_buffer.h
deleted file mode 100644
index 62cdfad4a0..0000000000
--- a/src/mesa/drivers/dri/radeon/radeon_buffer.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright 2008 Red Hat, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software")
- * to deal in the software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * them Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTIBILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES, OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT, OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *	Adam Jackson <ajax@redhat.com>
- */
-
-#ifndef RADEON_BUFFER_H
-#define RADEON_BUFFER_H
-
-#include "radeon_bo.h"
-#include "dri_util.h"
-
-struct radeon_renderbuffer
-{
-    struct gl_renderbuffer base;
-    struct radeon_bo *bo;
-    unsigned int cpp;
-    /* unsigned int offset; */
-    unsigned int pitch;
-    unsigned int width;
-    unsigned int height;
-
-    /* boo Xorg 6.8.2 compat */
-    int has_surface;
-
-
-    __DRIdrawablePrivate *dPriv;
-};
-
-#endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h
index 5526934209..4b5116c474 100644
--- a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h
+++ b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h
@@ -1,7 +1,7 @@
 #ifndef COMMON_CMDBUF_H
 #define COMMON_CMDBUF_H
 
-#include "radeon_cs.h"
+#include "radeon_bocs_wrapper.h"
 
 void rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *caller);
 int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller);
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c
index 87b6dac40b..80e8e0d86d 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -63,13 +63,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "vblank.h"
 
 #include "radeon_common.h"
-#include "radeon_common.h"
-#include "radeon_bo.h"
-#include "radeon_cs.h"
-#include "radeon_bo_legacy.h"
-#include "radeon_cs_legacy.h"
-#include "radeon_bo_gem.h"
-#include "radeon_cs_gem.h"
+#include "radeon_bocs_wrapper.h"
 #include "radeon_drm.h"
 #include "radeon_mipmap_tree.h"
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h
index cc9d579ea1..ead0f5551b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common.h
@@ -2,7 +2,6 @@
 #define COMMON_MISC_H
 
 #include "radeon_common_context.h"
-#include "radeon_buffer.h"
 #include "radeon_dma.h"
 #include "radeon_texture.h"
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index b88aeab051..c9be104578 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -68,6 +68,22 @@ typedef struct radeon_context *radeonContextPtr;
 #include "tnl_dd/t_dd_vertex.h"
 #undef TAG
 
+struct radeon_renderbuffer
+{
+	struct gl_renderbuffer base;
+	struct radeon_bo *bo;
+	unsigned int cpp;
+	/* unsigned int offset; */
+	unsigned int pitch;
+	unsigned int width;
+	unsigned int height;
+
+	/* boo Xorg 6.8.2 compat */
+	int has_surface;
+
+	__DRIdrawablePrivate *dPriv;
+};
+
 struct radeon_colorbuffer_state {
 	GLuint clear;
 	int roundEnable;
diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_drm.h b/src/mesa/drivers/dri/radeon/radeon_cs_drm.h
new file mode 100644
index 0000000000..7cc75d4700
--- /dev/null
+++ b/src/mesa/drivers/dri/radeon/radeon_cs_drm.h
@@ -0,0 +1,198 @@
+/* 
+ * Copyright © 2008 Nicolai Haehnle
+ * Copyright © 2008 Jérôme Glisse
+ * All Rights Reserved.
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ */
+/*
+ * Authors:
+ *      Aapo Tahkola <aet@rasterburn.org>
+ *      Nicolai Haehnle <prefect_@gmx.net>
+ *      Jérôme Glisse <glisse@freedesktop.org>
+ */
+#ifndef RADEON_CS_H
+#define RADEON_CS_H
+
+#include <stdint.h>
+#include "drm.h"
+#include "radeon_drm.h"
+#include "radeon_bo.h"
+
+struct radeon_cs_reloc {
+    struct radeon_bo    *bo;
+    uint32_t            read_domain;
+    uint32_t            write_domain;
+    uint32_t            flags;
+};
+
+
+#define RADEON_CS_SPACE_OK 0
+#define RADEON_CS_SPACE_OP_TO_BIG 1
+#define RADEON_CS_SPACE_FLUSH 2
+
+struct radeon_cs_space_check {
+    struct radeon_bo *bo;
+    uint32_t read_domains;
+    uint32_t write_domain;
+    uint32_t new_accounted;
+};
+
+struct radeon_cs_manager;
+
+struct radeon_cs {
+    struct radeon_cs_manager    *csm;
+    void                        *relocs;
+    uint32_t                    *packets;
+    unsigned                    crelocs;
+    unsigned                    relocs_total_size;
+    unsigned                    cdw;
+    unsigned                    ndw;
+    int                         section;
+    unsigned                    section_ndw;
+    unsigned                    section_cdw;
+    const char                  *section_file;
+    const char                  *section_func;
+    int                         section_line;
+
+};
+
+/* cs functions */
+struct radeon_cs_funcs {
+    struct radeon_cs *(*cs_create)(struct radeon_cs_manager *csm,
+                                   uint32_t ndw);
+    int (*cs_write_reloc)(struct radeon_cs *cs,
+                          struct radeon_bo *bo,
+                          uint32_t read_domain,
+                          uint32_t write_domain,
+                          uint32_t flags);
+    int (*cs_begin)(struct radeon_cs *cs,
+                    uint32_t ndw,
+                    const char *file,
+                    const char *func,
+                    int line);
+    int (*cs_end)(struct radeon_cs *cs,
+                  const char *file,
+                  const char *func,
+                  int line);
+    int (*cs_emit)(struct radeon_cs *cs);
+    int (*cs_destroy)(struct radeon_cs *cs);
+    int (*cs_erase)(struct radeon_cs *cs);
+    int (*cs_need_flush)(struct radeon_cs *cs);
+    void (*cs_print)(struct radeon_cs *cs, FILE *file);
+    int (*cs_space_check)(struct radeon_cs *cs, struct radeon_cs_space_check *bos,
+			  int num_bo);
+};
+
+struct radeon_cs_manager {
+    struct radeon_cs_funcs  *funcs;
+    int                     fd;
+    uint32_t vram_limit, gart_limit;
+    uint32_t vram_write_used, gart_write_used;
+    uint32_t read_used;
+};
+
+static inline struct radeon_cs *radeon_cs_create(struct radeon_cs_manager *csm,
+                                                 uint32_t ndw)
+{
+    return csm->funcs->cs_create(csm, ndw);
+}
+
+static inline int radeon_cs_write_reloc(struct radeon_cs *cs,
+                                        struct radeon_bo *bo,
+                                        uint32_t read_domain,
+                                        uint32_t write_domain,
+                                        uint32_t flags)
+{
+    return cs->csm->funcs->cs_write_reloc(cs,
+                                          bo,
+                                          read_domain,
+                                          write_domain,
+                                          flags);
+}
+
+static inline int radeon_cs_begin(struct radeon_cs *cs,
+                                  uint32_t ndw,
+                                  const char *file,
+                                  const char *func,
+                                  int line)
+{
+    return cs->csm->funcs->cs_begin(cs, ndw, file, func, line);
+}
+
+static inline int radeon_cs_end(struct radeon_cs *cs,
+                                const char *file,
+                                const char *func,
+                                int line)
+{
+    return cs->csm->funcs->cs_end(cs, file, func, line);
+}
+
+static inline int radeon_cs_emit(struct radeon_cs *cs)
+{
+    return cs->csm->funcs->cs_emit(cs);
+}
+
+static inline int radeon_cs_destroy(struct radeon_cs *cs)
+{
+    return cs->csm->funcs->cs_destroy(cs);
+}
+
+static inline int radeon_cs_erase(struct radeon_cs *cs)
+{
+    return cs->csm->funcs->cs_erase(cs);
+}
+
+static inline int radeon_cs_need_flush(struct radeon_cs *cs)
+{
+    return cs->csm->funcs->cs_need_flush(cs);
+}
+
+static inline void radeon_cs_print(struct radeon_cs *cs, FILE *file)
+{
+    cs->csm->funcs->cs_print(cs, file);
+}
+
+static inline int radeon_cs_space_check(struct radeon_cs *cs,
+					    struct radeon_cs_space_check *bos,
+					    int num_bo)
+{
+    return cs->csm->funcs->cs_space_check(cs, bos, num_bo);
+}
+
+static inline void radeon_cs_set_limit(struct radeon_cs *cs, uint32_t domain, uint32_t limit)
+{
+    
+    if (domain == RADEON_GEM_DOMAIN_VRAM)
+	cs->csm->vram_limit = limit;
+    else
+	cs->csm->gart_limit = limit;
+}
+
+static inline void radeon_cs_write_dword(struct radeon_cs *cs, uint32_t dword)
+{
+    cs->packets[cs->cdw++] = dword;
+    if (cs->section) {
+        cs->section_cdw++;
+    }
+}
+
+#endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c
index 2db3f7a68d..0f73dec1e5 100644
--- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c
+++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c
@@ -31,10 +31,7 @@
  */
 #include <errno.h>
 
-#include "radeon_cs.h"
-#include "radeon_cs_legacy.h"
-#include "radeon_bo_legacy.h"
-
+#include "radeon_bocs_wrapper.h"
 
 struct cs_manager_legacy {
     struct radeon_cs_manager    base;
diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h
index 19d904174f..e177b4bafe 100644
--- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h
+++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h
@@ -32,7 +32,6 @@
 #ifndef RADEON_CS_LEGACY_H
 #define RADEON_CS_LEGACY_H
 
-#include "radeon_cs.h"
 #include "radeon_common.h"
 
 struct radeon_cs_manager *radeon_cs_manager_legacy_ctor(struct radeon_context *ctx);
diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
index 99b1ef332f..fb3a236d7c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
@@ -44,7 +44,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #include "radeon_context.h"
 #include "radeon_common.h"
-#include "radeon_cs.h"
 #include "radeon_state.h"
 #include "radeon_ioctl.h"
 #include "radeon_tcl.h"
diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.h b/src/mesa/drivers/dri/radeon/radeon_ioctl.h
index 6d616bf804..18805d4c57 100644
--- a/src/mesa/drivers/dri/radeon/radeon_ioctl.h
+++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.h
@@ -38,7 +38,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #include "main/simple_list.h"
 #include "radeon_lock.h"
-#include "radeon_cs_legacy.h"
+#include "radeon_bocs_wrapper.h"
 
 extern void radeonEmitVertexAOS( r100ContextPtr rmesa,
 				 GLuint vertex_size,
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index 323726c574..c21d297b22 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -34,8 +34,6 @@
 #include "main/texcompress.h"
 #include "main/texformat.h"
 
-#include "radeon_buffer.h"
-
 static GLuint radeon_compressed_texture_size(GLcontext *ctx,
 		GLsizei width, GLsizei height, GLsizei depth,
 		GLuint mesaFormat)
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 7f0d526ed2..e8cc3b25a8 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -46,7 +46,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "radeon_chipset.h"
 #include "radeon_macros.h"
 #include "radeon_screen.h"
-#include "radeon_buffer.h"
 #include "radeon_common.h"
 #include "radeon_span.h"
 #if !RADEON_COMMON
@@ -66,13 +65,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "vblank.h"
 #include "drirenderbuffer.h"
 
+#include "radeon_bocs_wrapper.h"
+
 #include "GL/internal/dri_interface.h"
 
 /* Radeon configuration
  */
 #include "xmlpool.h"
-#include "radeon_bo_legacy.h"
-#include "radeon_bo_gem.h"
 
 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h
index 3287e125f4..1c0f5bb9bc 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -46,7 +46,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "radeon_reg.h"
 #include "drm_sarea.h"
 #include "xmlconfig.h"
-#include "radeon_bo.h"
 
 
 typedef struct {
diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c
index ebd18a1634..49ec2c378e 100644
--- a/src/mesa/drivers/dri/radeon/radeon_span.c
+++ b/src/mesa/drivers/dri/radeon/radeon_span.c
@@ -47,8 +47,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "radeon_lock.h"
 #include "radeon_span.h"
 
-#include "radeon_buffer.h"
-
 #define DBG 0
 
 static GLubyte *radeon_ptr32(const struct radeon_renderbuffer * rrb,
diff --git a/src/mesa/drivers/dri/radeon/radeon_span.h b/src/mesa/drivers/dri/radeon/radeon_span.h
index dda542c8d1..dd44ab517a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_span.h
+++ b/src/mesa/drivers/dri/radeon/radeon_span.h
@@ -42,8 +42,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #ifndef __RADEON_SPAN_H__
 #define __RADEON_SPAN_H__
 
-#include "radeon_buffer.h"
-
 extern void radeonInitSpanFuncs(GLcontext * ctx);
 
 extern void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb);
diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c
index a397c0824f..fc42318017 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state_init.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c
@@ -38,7 +38,6 @@
 #include "swrast_setup/swrast_setup.h"
 
 #include "radeon_context.h"
-#include "radeon_cs.h"
 #include "radeon_mipmap_tree.h"
 #include "radeon_ioctl.h"
 #include "radeon_state.h"
-- 
cgit v1.2.3


From 62d504d818f1ab1836a134658b1661ceabb65f1f Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 17 Feb 2009 10:34:01 +1000
Subject: radeon/r200: drop dirty state from texture object + pp_txoffset

this is just more code cleanup for old dead code
---
 src/mesa/drivers/dri/r200/r200_state_init.c        |  2 +-
 src/mesa/drivers/dri/r200/r200_tex.c               |  4 ----
 src/mesa/drivers/dri/r200/r200_texstate.c          | 23 +++-------------------
 .../drivers/dri/radeon/radeon_common_context.h     | 20 +------------------
 src/mesa/drivers/dri/radeon/radeon_state_init.c    |  2 +-
 src/mesa/drivers/dri/radeon/radeon_tex.c           |  4 ----
 src/mesa/drivers/dri/radeon/radeon_texstate.c      | 13 ++++--------
 7 files changed, 10 insertions(+), 58 deletions(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_common_context.h')

diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c
index 0366fc0fbe..013064d2b3 100644
--- a/src/mesa/drivers/dri/r200/r200_state_init.c
+++ b/src/mesa/drivers/dri/r200/r200_state_init.c
@@ -553,7 +553,7 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
      /* workaround for old CS mechanism */
      OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
    } else if (t->image_override)
-     OUT_BATCH(atom->cmd[10]);
+     OUT_BATCH(t->override_offset);
 
    END_BATCH();
 }
diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c
index 5daacb8c95..19a6cad80b 100644
--- a/src/mesa/drivers/dri/r200/r200_tex.c
+++ b/src/mesa/drivers/dri/r200/r200_tex.c
@@ -400,10 +400,6 @@ static void r200TexParameter( GLcontext *ctx, GLenum target,
    default:
       return;
    }
-
-   /* Mark this texobj as dirty (one bit per tex unit)
-    */
-   t->dirty_state = R200_TEX_ALL;
 }
 
 
diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c
index eee4475137..6432068760 100644
--- a/src/mesa/drivers/dri/r200/r200_texstate.c
+++ b/src/mesa/drivers/dri/r200/r200_texstate.c
@@ -743,7 +743,8 @@ void r200SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
 	if (!offset)
 		return;
 
-	t->pp_txoffset = offset;
+	t->bo = NULL;
+	t->override_offset = offset;
 	t->pp_txpitch = pitch - 32;
 
 	switch (depth) {
@@ -1003,18 +1004,9 @@ static void import_tex_obj_state( r200ContextPtr rmesa,
    cmd[TEX_PP_TXSIZE] = texobj->pp_txsize; /* NPOT only! */
    cmd[TEX_PP_TXPITCH] = texobj->pp_txpitch; /* NPOT only! */
    cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color;
-   if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
-      cmd[TEX_PP_TXOFFSET_NEWDRM] = texobj->pp_txoffset;
-   }
-   else {
-      cmd[TEX_PP_TXOFFSET_OLDDRM] = texobj->pp_txoffset;
-   }
 
    if (texobj->base.Target == GL_TEXTURE_CUBE_MAP) {
       GLuint *cube_cmd = &rmesa->hw.cube[unit].cmd[CUBE_CMD_0];
-      //      GLuint bytesPerFace = texobj->base.totalSize / 6;
-      //      ASSERT(texobj->base.totalSize % 6 == 0);
-      GLuint bytesPerFace = 1; // TODO
 
       R200_STATECHANGE( rmesa, cube[unit] );
       cube_cmd[CUBE_PP_CUBIC_FACES] = texobj->pp_cubic_faces;
@@ -1023,14 +1015,8 @@ static void import_tex_obj_state( r200ContextPtr rmesa,
 	    to not include that command when new drm is used */
 	 cmd[TEX_PP_CUBIC_FACES] = texobj->pp_cubic_faces;
       }
-      cube_cmd[CUBE_PP_CUBIC_OFFSET_F1] = texobj->pp_txoffset + 1 * bytesPerFace;
-      cube_cmd[CUBE_PP_CUBIC_OFFSET_F2] = texobj->pp_txoffset + 2 * bytesPerFace;
-      cube_cmd[CUBE_PP_CUBIC_OFFSET_F3] = texobj->pp_txoffset + 3 * bytesPerFace;
-      cube_cmd[CUBE_PP_CUBIC_OFFSET_F4] = texobj->pp_txoffset + 4 * bytesPerFace;
-      cube_cmd[CUBE_PP_CUBIC_OFFSET_F5] = texobj->pp_txoffset + 5 * bytesPerFace;
    }
 
-   texobj->dirty_state &= ~(1<<unit);
 }
 
 static void set_texgen_matrix( r200ContextPtr rmesa, 
@@ -1399,7 +1385,6 @@ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t)
       t->pp_txformat |= R200_TXFORMAT_NON_POWER2;
    }
 
-   t->dirty_state = R200_TEX_ALL;
 }
 
 static GLboolean r200_validate_texture(GLcontext *ctx, struct gl_texture_object *texObj, int unit)
@@ -1429,9 +1414,7 @@ static GLboolean r200_validate_texture(GLcontext *ctx, struct gl_texture_object
    rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] |= 4 << (unit * 3);
 
    rmesa->recheck_texgen[unit] = GL_TRUE;
-   if (t->dirty_state & (1<<unit)) {
-      import_tex_obj_state( rmesa, unit, t );
-   }
+   import_tex_obj_state( rmesa, unit, t );
 
    if (rmesa->recheck_texgen[unit]) {
       GLboolean fallback = !r200_validate_texgen( ctx, unit );
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index c9be104578..7618b3482f 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -170,7 +170,6 @@ typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
 /* Texture object in locally shared texture space.
  */
 struct radeon_tex_obj {
-  //	driTextureObject base;
 	struct gl_texture_object base;
 	struct _radeon_mipmap_tree *mt;
 
@@ -185,26 +184,9 @@ struct radeon_tex_obj {
 	GLuint tile_bits;	/* hw texture tile bits used on this texture */
         struct radeon_bo *bo;
 
-	GLuint bufAddr;		/* Offset to start of locally
-				   shared texture block */
-
-	GLuint dirty_state;	/* Flags (1 per texunit) for
-				   whether or not this texobj
-				   has dirty hardware state
-				   (pp_*) that needs to be
-				   brought into the
-				   texunit. */
-
-	drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
-	/* Six, for the cube faces */
-
-
-
 	GLuint pp_txfilter;	/* hardware register values */
 	GLuint pp_txformat;
-        GLuint pp_txformat_x;
-	GLuint pp_txoffset;	/* Image location in texmem.
-				   All cube faces follow. */
+	GLuint pp_txformat_x;
 	GLuint pp_txsize;	/* npot only */
 	GLuint pp_txpitch;	/* npot only */
 	GLuint pp_border_color;
diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c
index 998ae79624..617e731a41 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state_init.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c
@@ -486,7 +486,7 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
      OUT_BATCH(r100->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
      //     OUT_BATCH(r100->radeon.radeonScreen);
    } else if (t->image_override)
-     OUT_BATCH(atom->cmd[4]);
+     OUT_BATCH(t->override_offset);
 
    OUT_BATCH_TABLE((atom->cmd+4), 5);
    END_BATCH();
diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c
index 4d98b72612..2dfb5042ec 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tex.c
+++ b/src/mesa/drivers/dri/radeon/radeon_tex.c
@@ -362,10 +362,6 @@ static void radeonTexParameter( GLcontext *ctx, GLenum target,
    default:
       return;
    }
-
-   /* Mark this texobj as dirty (one bit per tex unit)
-    */
-   t->dirty_state = R100_TEX_ALL;
 }
 
 static void radeonDeleteTexture( GLcontext *ctx,
diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c
index 2aa1a83342..6a34f1e332 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texstate.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c
@@ -614,8 +614,9 @@ void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname,
 
 	if (!offset)
 		return;
-
-	t->pp_txoffset = offset;
+	
+	t->bo = NULL;
+	t->override_offset = offset;
 	t->pp_txpitch = pitch - 32;
 
 	switch (depth) {
@@ -715,7 +716,6 @@ static void import_tex_obj_state( r100ContextPtr rmesa,
    cmd[TEX_PP_TXFILTER] |= texobj->pp_txfilter & TEXOBJ_TXFILTER_MASK;
    cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK;
    cmd[TEX_PP_TXFORMAT] |= texobj->pp_txformat & TEXOBJ_TXFORMAT_MASK;
-   cmd[TEX_PP_TXOFFSET] = texobj->pp_txoffset;
    cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color;
 
    if (texobj->base.Target == GL_TEXTURE_RECTANGLE_NV) {
@@ -742,8 +742,6 @@ static void import_tex_obj_state( r100ContextPtr rmesa,
       rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
    }
 
-   texobj->dirty_state &= ~(1<<unit);
-
    rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
 }
 
@@ -974,7 +972,6 @@ static GLboolean setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t, int
       t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2;
    }
 
-   t->dirty_state = R100_TEX_ALL;
    return GL_TRUE;
 }
 
@@ -1004,9 +1001,7 @@ static GLboolean radeon_validate_texture(GLcontext *ctx, struct gl_texture_objec
 
    rmesa->recheck_texgen[unit] = GL_TRUE;
 
-   if (t->dirty_state & (1<<unit)) {
-      import_tex_obj_state( rmesa, unit, t );
-   }
+   import_tex_obj_state( rmesa, unit, t );
 
    if (rmesa->recheck_texgen[unit]) {
       GLboolean fallback = !radeon_validate_texgen( ctx, unit );
-- 
cgit v1.2.3


From 2ba4fc3d603ebc9e3210ef96f9fbc2cd488e0a33 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 17 Feb 2009 14:00:24 +1000
Subject: radeon/r200: drop legacy texture heap code

---
 src/mesa/drivers/dri/r200/r200_context.c           | 53 ----------------------
 .../drivers/dri/radeon/radeon_common_context.h     |  3 --
 src/mesa/drivers/dri/radeon/radeon_context.c       | 51 ---------------------
 3 files changed, 107 deletions(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_common_context.h')

diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c
index a9cb2e2fe9..a744469b31 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -331,25 +331,6 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
      return GL_FALSE;
    }
 
-
-   (void) memset( rmesa->radeon.texture_heaps, 0, sizeof( rmesa->radeon.texture_heaps ) );
-   make_empty_list( & rmesa->radeon.swapped );
-
-   rmesa->radeon.nr_heaps = 1 /* screen->numTexHeaps */ ;
-   assert(rmesa->radeon.nr_heaps < RADEON_NR_TEX_HEAPS);
-#if 0
-   for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) {
-      rmesa->radeon.texture_heaps[i] = driCreateTextureHeap( i, rmesa,
-	    screen->texSize[i],
-	    12,
-	    RADEON_NR_TEX_REGIONS,
-	    (drmTextureRegionPtr)rmesa->radeon.sarea->tex_list[i],
-	    & rmesa->radeon.sarea->tex_age[i],
-	    & rmesa->radeon.swapped,
-	    sizeof( radeonTexObj ),
-	    (destroy_texture_object_t *) r200DestroyTexObj );
-   }
-#endif
    rmesa->radeon.texture_depth = driQueryOptioni (&rmesa->radeon.optionCache,
 					   "texture_depth");
    if (rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
@@ -373,22 +354,6 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
 
    i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
 
-   driCalculateMaxTextureLevels( rmesa->radeon.texture_heaps,
-				 rmesa->radeon.nr_heaps,
-				 & ctx->Const,
-				 4,
-				 11, /* max 2D texture size is 2048x2048 */
-#if ENABLE_HW_3D_TEXTURE
-				 8,  /* max 3D texture size is 256^3 */
-#else
-				 0,  /* 3D textures unsupported */
-#endif
-				 11, /* max cube texture size is 2048x2048 */
-				 11, /* max texture rectangle size is 2048x2048 */
-				 12,
-				 GL_FALSE,
-				 i );
-
    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 
    /* No wide AA points.
@@ -541,10 +506,7 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv )
    /* Free r200 context resources */
    assert(rmesa); /* should never be null */
    if ( rmesa ) {
-      GLboolean   release_texture_heaps;
 
-
-      release_texture_heaps = (rmesa->radeon.glCtx->Shared->RefCount == 1);
       _swsetup_DestroyContext( rmesa->radeon.glCtx );
       _tnl_DestroyContext( rmesa->radeon.glCtx );
       _vbo_DestroyContext( rmesa->radeon.glCtx );
@@ -563,21 +525,6 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv )
 	 rmesa->radeon.state.scissor.pClipRects = NULL;
       }
 
-
-      if ( release_texture_heaps ) {
-         /* This share group is about to go away, free our private
-          * texture object data.
-          */
-         int i;
-
-         for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) {
-	    driDestroyTextureHeap( rmesa->radeon.texture_heaps[ i ] );
-	    rmesa->radeon.texture_heaps[ i ] = NULL;
-         }
-
-	 assert( is_empty_list( & rmesa->radeon.swapped ) );
-      }
-
       radeonCleanupContext(&rmesa->radeon);
 
       FREE( rmesa );
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index 7618b3482f..a200e90221 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -375,9 +375,6 @@ struct radeon_context {
   
    /* Texture object bookkeeping
     */
-   unsigned              nr_heaps;
-   driTexHeap          * texture_heaps[ RADEON_NR_TEX_HEAPS ];
-   driTextureObject      swapped;
    int                   texture_depth;
    float                 initialMaxAnisotropy;
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c
index f562876db4..e4202c71fc 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -161,7 +161,6 @@ static void r100_get_lock(radeonContextPtr radeon)
    }
    
    if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) {
-      int i;
       sarea->ctx_owner = rmesa->radeon.dri.hwContext;
       
       if (!radeon->radeonScreen->kernel_mm)
@@ -255,26 +254,6 @@ radeonCreateContext( const __GLcontextModes *glVisual,
      return GL_FALSE;
    }
 
-   (void) memset( rmesa->radeon.texture_heaps, 0, sizeof( rmesa->radeon.texture_heaps ) );
-   make_empty_list( & rmesa->radeon.swapped );
-
-#if 0
-   rmesa->radeon.nr_heaps = screen->numTexHeaps;
-   for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) {
-      rmesa->radeon.texture_heaps[i] = driCreateTextureHeap( i, rmesa,
-	    screen->texSize[i],
-	    12,
-	    RADEON_NR_TEX_REGIONS,
-	    (drmTextureRegionPtr)rmesa->radeon.sarea->tex_list[i],
-	    & rmesa->radeon.sarea->tex_age[i],
-	    & rmesa->radeon.swapped,
-	    sizeof( radeonTexObj ),
-	    (destroy_texture_object_t *) radeonDestroyTexObj );
-
-      driSetTextureSwapCounterLocation( rmesa->radeon.texture_heaps[i],
-					& rmesa->c_textureSwaps );
-   }
-#endif
    rmesa->radeon.texture_depth = driQueryOptioni (&rmesa->radeon.optionCache,
 					   "texture_depth");
    if (rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
@@ -298,19 +277,6 @@ radeonCreateContext( const __GLcontextModes *glVisual,
 
    i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
 
-   driCalculateMaxTextureLevels( rmesa->radeon.texture_heaps,
-				 rmesa->radeon.nr_heaps,
-				 & ctx->Const,
-				 4,
-				 11, /* max 2D texture size is 2048x2048 */
-				 8,  /* 256^3 */
-				 9,  /* \todo: max cube texture size seems to be 512x512(x6) */
-				 11, /* max rect texture size is 2048x2048. */
-				 12,
-				 GL_FALSE,
-				 i );
-
-
    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 
    /* No wide points.
@@ -450,10 +416,7 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv )
    /* Free radeon context resources */
    assert(rmesa); /* should never be null */
    if ( rmesa ) {
-      GLboolean   release_texture_heaps;
-
 
-      release_texture_heaps = (rmesa->radeon.glCtx->Shared->RefCount == 1);
       _swsetup_DestroyContext( rmesa->radeon.glCtx );
       _tnl_DestroyContext( rmesa->radeon.glCtx );
       _vbo_DestroyContext( rmesa->radeon.glCtx );
@@ -473,20 +436,6 @@ void radeonDestroyContext( __DRIcontextPrivate *driContextPriv )
 	 rmesa->radeon.state.scissor.pClipRects = NULL;
       }
 
-      if ( release_texture_heaps ) {
-         /* This share group is about to go away, free our private
-          * texture object data.
-          */
-         int i;
-
-         for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) {
-	    driDestroyTextureHeap( rmesa->radeon.texture_heaps[ i ] );
-	    rmesa->radeon.texture_heaps[ i ] = NULL;
-         }
-
-	 assert( is_empty_list( & rmesa->radeon.swapped ) );
-      }
-
       radeonCleanupContext(&rmesa->radeon);
 
       FREE( rmesa );
-- 
cgit v1.2.3


From 2b85fccae5ba33748846f74f90fe0f72c673a4b1 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 3 Mar 2009 03:27:59 +1000
Subject: radeon: refactor framebuffer code like intel

this is a step towards fbos and should fix pageflipping, but
I think the first flip seems broken.
---
 src/mesa/drivers/dri/r200/r200_context.c           |   2 +-
 src/mesa/drivers/dri/r200/r200_ioctl.c             |   2 +-
 src/mesa/drivers/dri/r200/r200_state.c             |  94 +----
 src/mesa/drivers/dri/r300/r300_context.c           |  39 +-
 src/mesa/drivers/dri/r300/r300_ioctl.c             |   8 +-
 src/mesa/drivers/dri/r300/r300_render.c            |   3 +-
 src/mesa/drivers/dri/r300/r300_state.c             |  71 +---
 src/mesa/drivers/dri/r300/r300_texstate.c          |  10 +-
 src/mesa/drivers/dri/radeon/radeon_common.c        | 470 ++++++++++++++++-----
 src/mesa/drivers/dri/radeon/radeon_common.h        |  11 +-
 .../drivers/dri/radeon/radeon_common_context.c     | 124 +++---
 .../drivers/dri/radeon/radeon_common_context.h     |  43 +-
 src/mesa/drivers/dri/radeon/radeon_context.c       |   4 +-
 src/mesa/drivers/dri/radeon/radeon_lock.c          |  78 ++--
 src/mesa/drivers/dri/radeon/radeon_lock.h          |  69 +--
 src/mesa/drivers/dri/radeon/radeon_screen.c        |  69 +--
 src/mesa/drivers/dri/radeon/radeon_state.c         |  80 +---
 17 files changed, 612 insertions(+), 565 deletions(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_common_context.h')

diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c
index a744469b31..10a6362afd 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -261,9 +261,9 @@ static void r200_init_vtbl(radeonContextPtr radeon)
 {
    radeon->vtbl.get_lock = r200_get_lock;
    radeon->vtbl.update_viewport_offset = r200UpdateViewportOffset;
-   radeon->vtbl.update_draw_buffer = r200UpdateDrawBuffer;
    radeon->vtbl.emit_cs_header = r200_vtbl_emit_cs_header;
    radeon->vtbl.swtcl_flush = r200_swtcl_flush;
+   radeon->vtbl.fallback = r200Fallback;
 }
 
 
diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c
index c08968f7f8..6076b6d7ea 100644
--- a/src/mesa/drivers/dri/r200/r200_ioctl.c
+++ b/src/mesa/drivers/dri/r200/r200_ioctl.c
@@ -203,7 +203,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask )
    GLint ret;
 
    if ( R200_DEBUG & DEBUG_IOCTL ) {
-      fprintf( stderr, "r200Clear\n");
+       fprintf( stderr, "r200Clear %x %d\n", mask, rmesa->radeon.sarea->pfCurrentPage);
    }
 
    {
diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c
index 126f78b39c..46baad33f5 100644
--- a/src/mesa/drivers/dri/r200/r200_state.c
+++ b/src/mesa/drivers/dri/r200/r200_state.c
@@ -1639,6 +1639,8 @@ static void r200Viewport( GLcontext *ctx, GLint x, GLint y,
     * values, or keep the originals hanging around.
     */
    r200UpdateWindow( ctx );
+
+   radeon_viewport(ctx, x, y, width, height);
 }
 
 static void r200DepthRange( GLcontext *ctx, GLclampd nearval,
@@ -1754,47 +1756,6 @@ static void r200LogicOpCode( GLcontext *ctx, GLenum opcode )
    rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = r200_rop_tab[rop];
 }
 
-
-static void r200DrawBuffer( GLcontext *ctx, GLenum mode )
-{
-   r200ContextPtr rmesa = R200_CONTEXT(ctx);
-
-   if (R200_DEBUG & DEBUG_DRI)
-      fprintf(stderr, "%s %s\n", __FUNCTION__,
-	      _mesa_lookup_enum_by_nr( mode ));
-
-   radeon_firevertices(&rmesa->radeon);	/* don't pipeline cliprect changes */
-
-   if (ctx->DrawBuffer->_NumColorDrawBuffers != 1) {
-      /* 0 (GL_NONE) buffers or multiple color drawing buffers */
-      FALLBACK( rmesa, R200_FALLBACK_DRAW_BUFFER, GL_TRUE );
-      return;
-   }
-
-   switch ( ctx->DrawBuffer->_ColorDrawBufferIndexes[0] ) {
-   case BUFFER_FRONT_LEFT:
-   case BUFFER_BACK_LEFT:
-      FALLBACK( rmesa, R200_FALLBACK_DRAW_BUFFER, GL_FALSE );
-      break;
-   default:
-      FALLBACK( rmesa, R200_FALLBACK_DRAW_BUFFER, GL_TRUE );
-      return;
-   }
-
-   radeonSetCliprects( &rmesa->radeon );
-   radeonUpdatePageFlipping(&rmesa->radeon);
-
-   /* We'll set the drawing engine's offset/pitch parameters later
-    * when we update other state.
-    */
-}
-
-
-static void r200ReadBuffer( GLcontext *ctx, GLenum mode )
-{
-   /* nothing, until we implement h/w glRead/CopyPixels or CopyTexImage */
-}
-
 /* =============================================================
  * State enable/disable
  */
@@ -2289,47 +2250,6 @@ static void update_texturematrix( GLcontext *ctx )
    }
 }
 
-
-
-/**
- * Tell the card where to render (offset, pitch).
- * Effected by glDrawBuffer, etc
- */
-void
-r200UpdateDrawBuffer(GLcontext *ctx)
-{
-   r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   struct gl_framebuffer *fb = ctx->DrawBuffer;
-   struct radeon_renderbuffer *rrb;
-
-   if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) {
-     /* draw to front */
-     rrb = (void *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
-   } else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) {
-     /* draw to back */
-     rrb = (void *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
-   } else {
-     /* drawing to multiple buffers, or none */
-     return;
-   }
-
-   assert(rrb);
-   assert(rrb->pitch);
-
-   R200_STATECHANGE( rmesa, ctx );
-
-#if 0
-   /* Note: we used the (possibly) page-flipped values */
-   rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET]
-     = ((rrb->flippedOffset + rmesa->radeon.radeonScreen->fbLocation)
-	& R200_COLOROFFSET_MASK);
-   rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = drb->flippedPitch;
-   if (rmesa->radeon.sarea->tiling_enabled) {
-      rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE;
-   }
-#endif
-}
-
 static GLboolean r200ValidateBuffers(GLcontext *ctx)
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
@@ -2395,7 +2315,11 @@ GLboolean r200ValidateState( GLcontext *ctx )
    GLuint new_state = rmesa->radeon.NewGLState;
 
    if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) {
-     r200UpdateDrawBuffer(ctx);
+      _mesa_update_framebuffer(ctx);
+      /* this updates the DrawBuffer's Width/Height if it's a FBO */
+      _mesa_update_draw_buffer_bounds(ctx);
+      
+      R200_STATECHANGE(rmesa, ctx);
    }
 
    if (new_state & (_NEW_TEXTURE | _NEW_PROGRAM)) {
@@ -2523,8 +2447,8 @@ void r200InitStateFuncs( struct dd_function_table *functions )
    functions->UpdateState		= r200InvalidateState;
    functions->LightingSpaceChange	= r200LightingSpaceChange;
 
-   functions->DrawBuffer		= r200DrawBuffer;
-   functions->ReadBuffer		= r200ReadBuffer;
+   functions->DrawBuffer		= radeonDrawBuffer;
+   functions->ReadBuffer		= radeonReadBuffer;
 
    functions->AlphaFunc			= r200AlphaFunc;
    functions->BlendColor		= r200BlendColor;
diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c
index 5d497efc9c..488fd44740 100644
--- a/src/mesa/drivers/dri/r300/r300_context.c
+++ b/src/mesa/drivers/dri/r300/r300_context.c
@@ -235,26 +235,35 @@ static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmes
 
 static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
 {
-   r300ContextPtr r300 = (r300ContextPtr)radeon;
-   BATCH_LOCALS(radeon);
-
-   r300->vap_flush_needed = GL_TRUE;
+	r300ContextPtr r300 = (r300ContextPtr)radeon;
+	BATCH_LOCALS(radeon);
+	
+	r300->vap_flush_needed = GL_TRUE;
+	
+	cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
+	BEGIN_BATCH_NO_AUTOSTATE(2);
+	OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);
+	END_BATCH();
+	end_3d(radeon);
+}
 
-   cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
-   BEGIN_BATCH_NO_AUTOSTATE(2);
-   OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);
-   END_BATCH();
-   end_3d(radeon);
+static void r300_fallback(GLcontext *ctx, GLuint bit, GLboolean mode)
+{
+	r300ContextPtr r300 = R300_CONTEXT(ctx);
+	if (mode)
+		r300->radeon.Fallback |= bit;
+	else
+		r300->radeon.Fallback &= ~bit;
 }
 
 static void r300_init_vtbl(radeonContextPtr radeon)
 {
-   radeon->vtbl.get_lock = r300_get_lock;
-   radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset;
-   radeon->vtbl.update_draw_buffer = r300UpdateDrawBuffer;
-   radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header;
-   radeon->vtbl.swtcl_flush = r300_swtcl_flush;
-   radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms;
+	radeon->vtbl.get_lock = r300_get_lock;
+	radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset;
+	radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header;
+	radeon->vtbl.swtcl_flush = r300_swtcl_flush;
+	radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms;
+	radeon->vtbl.fallback = r300_fallback;
 }
 
 
diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c
index 619d268f38..d1cf57959f 100644
--- a/src/mesa/drivers/dri/r300/r300_ioctl.c
+++ b/src/mesa/drivers/dri/r300/r300_ioctl.c
@@ -541,7 +541,7 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask)
 {
 	r300ContextPtr r300 = R300_CONTEXT(ctx);
 	__DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable;
-	GLframebuffer *fb = dPriv->driverPrivate;
+	struct radeon_framebuffer *rfb = dPriv->driverPrivate;
 	struct radeon_renderbuffer *rrb;
 	struct radeon_renderbuffer *rrbd;
 	int flags = 0;
@@ -594,16 +594,16 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask)
 	rcommonEnsureCmdBufSpace(&r300->radeon, 421 * 3, __FUNCTION__);
 	if (flags || bits)
 		r300EmitClearState(ctx);
-	rrbd = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer;
+	rrbd = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer;
 
 	if (flags & BUFFER_BIT_FRONT_LEFT) {
-		rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+		rrb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
 		r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
 		bits = 0;
 	}
 
 	if (flags & BUFFER_BIT_BACK_LEFT) {
-		rrb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+		rrb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer;
 		r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
 		bits = 0;
 	}
diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c
index f46477f0f6..402d2d7638 100644
--- a/src/mesa/drivers/dri/r300/r300_render.c
+++ b/src/mesa/drivers/dri/r300/r300_render.c
@@ -427,7 +427,8 @@ static int r300Fallback(GLcontext * ctx)
 {
 	r300ContextPtr r300 = R300_CONTEXT(ctx);
 	const unsigned back = ctx->Stencil._BackFace;
-
+	
+	FALLBACK_IF(r300->radeon.Fallback);
 	/* Do we need to use new-style shaders?
 	 * Also is there a better way to do this? */
 	if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index 59728a07e5..6bb0063bc1 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -1083,20 +1083,13 @@ static void r300UpdateWindow(GLcontext * ctx)
 static void r300Viewport(GLcontext * ctx, GLint x, GLint y,
 			 GLsizei width, GLsizei height)
 {
-	r300ContextPtr rmesa = R300_CONTEXT(ctx);
-    __DRIcontext *driContext = rmesa->radeon.dri.context;
 	/* Don't pipeline viewport changes, conflict with window offset
 	 * setting below.  Could apply deltas to rescue pipelined viewport
 	 * values, or keep the originals hanging around.
 	 */
-    if (rmesa->radeon.radeonScreen->driScreen->dri2.enabled) {
-        radeon_update_renderbuffers(driContext, driContext->driDrawablePriv);
-        if (driContext->driDrawablePriv != driContext->driReadablePriv) {
-            radeon_update_renderbuffers(driContext,
-                                        driContext->driReadablePriv);
-        }
-    }
 	r300UpdateWindow(ctx);
+
+	radeon_viewport(ctx, x, y, width, height);
 }
 
 static void r300DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval)
@@ -1129,34 +1122,6 @@ void r300UpdateViewportOffset(GLcontext * ctx)
 	radeonUpdateScissor(ctx);
 }
 
-/**
- * Tell the card where to render (offset, pitch).
- * Effected by glDrawBuffer, etc
- */
-void r300UpdateDrawBuffer(GLcontext * ctx)
-{
-	r300ContextPtr rmesa = R300_CONTEXT(ctx);
-	struct gl_framebuffer *fb = ctx->DrawBuffer;
-	struct radeon_renderbuffer *rrb;
-
-	if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) {
-		/* draw to front */
-		rrb =
-		    (void *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
-	} else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) {
-		/* draw to back */
-		rrb = (void *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
-	} else {
-		/* drawing to multiple buffers, or none */
-		return;
-	}
-
-	assert(rrb);
-	assert(rrb->pitch);
-
-	R300_STATECHANGE(rmesa, cb);
-}
-
 static void
 r300FetchStateParameter(GLcontext * ctx,
 			const gl_state_index state[STATE_LENGTH],
@@ -2653,7 +2618,11 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state)
 	_ae_invalidate_state(ctx, new_state);
 
 	if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) {
-		r300UpdateDrawBuffer(ctx);
+		_mesa_update_framebuffer(ctx);
+		/* this updates the DrawBuffer's Width/Height if it's a FBO */
+		_mesa_update_draw_buffer_bounds(ctx);
+
+		R300_STATECHANGE(r300, cb);
 	}
 
 	r300UpdateStateParameters(ctx, new_state);
@@ -2705,28 +2674,6 @@ void r300UpdateClipPlanes( GLcontext *ctx )
 	}
 }
 
-static void r300DrawBuffer( GLcontext *ctx, GLenum mode )
-{
-	r300ContextPtr rmesa = R300_CONTEXT(ctx);
-	if (RADEON_DEBUG & DEBUG_DRI)
-		fprintf(stderr, "%s %s\n", __FUNCTION__,
-			_mesa_lookup_enum_by_nr( mode ));
-
-	radeon_firevertices(&rmesa->radeon);	/* don't pipeline cliprect changes */
-
-	radeonSetCliprects( &rmesa->radeon );
-        if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) 
-		radeonUpdatePageFlipping(&rmesa->radeon);
-}
-
-static void r300ReadBuffer( GLcontext *ctx, GLenum mode )
-{
-	if (RADEON_DEBUG & DEBUG_DRI)
-		fprintf(stderr, "%s %s\n", __FUNCTION__,
-			_mesa_lookup_enum_by_nr( mode ));
-
-};
-
 /**
  * Initialize driver's state callback functions
  */
@@ -2770,6 +2717,6 @@ void r300InitStateFuncs(struct dd_function_table *functions)
 	functions->ClipPlane = r300ClipPlane;
 	functions->Scissor = radeonScissor;
 
-	functions->DrawBuffer		= r300DrawBuffer;
-	functions->ReadBuffer		= r300ReadBuffer;
+	functions->DrawBuffer		= radeonDrawBuffer;
+	functions->ReadBuffer		= radeonReadBuffer;
 }
diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c
index 8a90069a6d..2d7f392e7c 100644
--- a/src/mesa/drivers/dri/r300/r300_texstate.c
+++ b/src/mesa/drivers/dri/r300/r300_texstate.c
@@ -393,7 +393,7 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv)
 	radeon_texture_image *rImage;
 	radeonContextPtr radeon;
 	r300ContextPtr rmesa;
-	GLframebuffer *fb;
+	struct radeon_framebuffer *rfb;
 	radeonTexObjPtr t;
 	uint32_t pitch_val;
 
@@ -402,7 +402,7 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv)
 	radeon = pDRICtx->driverPrivate;
 	rmesa = pDRICtx->driverPrivate;
 
-	fb = dPriv->driverPrivate;
+	rfb = dPriv->driverPrivate;
         texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit];
 	texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target);
         texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0);
@@ -415,17 +415,17 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv)
 
 	radeon_update_renderbuffers(pDRICtx, dPriv);
 	/* back & depth buffer are useless free them right away */
-	rb = (void*)fb->Attachment[BUFFER_DEPTH].Renderbuffer;
+	rb = (void*)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer;
 	if (rb && rb->bo) {
 		radeon_bo_unref(rb->bo);
         rb->bo = NULL;
 	}
-	rb = (void*)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+	rb = (void*)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer;
 	if (rb && rb->bo) {
 		radeon_bo_unref(rb->bo);
 		rb->bo = NULL;
 	}
-	rb = (void*)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+	rb = (void*)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
 	if (rb->bo == NULL) {
 		/* Failed to BO for the buffer */
 		return;
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c
index f7c0d7d64f..1021f9beec 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -51,7 +51,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "main/light.h"
 #include "main/framebuffer.h"
 #include "main/simple_list.h"
-
+#include "main/renderbuffer.h"
 #include "swrast/swrast.h"
 #include "vbo/vbo.h"
 #include "tnl/tnl.h"
@@ -132,6 +132,38 @@ void radeonRecalcScissorRects(radeonContextPtr radeon)
 	}
 }
 
+static void radeon_get_cliprects(radeonContextPtr radeon,
+				 struct drm_clip_rect **cliprects,
+				 unsigned int *num_cliprects,
+				 int *x_off, int *y_off)
+{
+	__DRIdrawablePrivate *dPriv = radeon->dri.drawable;
+	struct radeon_framebuffer *rfb = dPriv->driverPrivate;
+
+	if (radeon->constant_cliprect) {
+		radeon->fboRect.x1 = 0;
+		radeon->fboRect.y1 = 0;
+		radeon->fboRect.x2 = radeon->glCtx->DrawBuffer->Width;
+		radeon->fboRect.y2 = radeon->glCtx->DrawBuffer->Height;
+
+		*cliprects = &radeon->fboRect;
+		*num_cliprects = 1;
+		*x_off = 0;
+		*y_off = 0;
+	} else if (radeon->front_cliprects ||
+		   rfb->pf_active || dPriv->numBackClipRects == 0) {
+		*cliprects = dPriv->pClipRects;
+		*num_cliprects = dPriv->numClipRects;
+		*x_off = dPriv->x;
+		*y_off = dPriv->y;
+	} else {
+		*num_cliprects = dPriv->numBackClipRects;
+		*cliprects = dPriv->pBackClipRects;
+		*x_off = dPriv->backX;
+		*y_off = dPriv->backY;
+	}
+}
+
 /**
  * Update cliprects and scissors.
  */
@@ -139,49 +171,37 @@ void radeonSetCliprects(radeonContextPtr radeon)
 {
 	__DRIdrawablePrivate *const drawable = radeon->dri.drawable;
 	__DRIdrawablePrivate *const readable = radeon->dri.readable;
-	GLframebuffer *const draw_fb = (GLframebuffer*)drawable->driverPrivate;
-	GLframebuffer *const read_fb = (GLframebuffer*)readable->driverPrivate;
+	struct radeon_framebuffer *const draw_rfb = drawable->driverPrivate;
+	struct radeon_framebuffer *const read_rfb = readable->driverPrivate;
+	int x_off, y_off;
 
-	if (!radeon->radeonScreen->driScreen->dri2.enabled) {
-		if (draw_fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) {
-			/* Can't ignore 2d windows if we are page flipping. */
-			if (drawable->numBackClipRects == 0 || radeon->doPageFlip ||
-			    radeon->sarea->pfCurrentPage == 1) {
-				radeon->numClipRects = drawable->numClipRects;
-				radeon->pClipRects = drawable->pClipRects;
-			} else {
-				radeon->numClipRects = drawable->numBackClipRects;
-				radeon->pClipRects = drawable->pBackClipRects;
-			}
-		} else {
-			/* front buffer (or none, or multiple buffers */
-			radeon->numClipRects = drawable->numClipRects;
-			radeon->pClipRects = drawable->pClipRects;
-		}
-	}
+	fprintf(stderr,"cliprects %d %d\n", radeon->front_cliprects, radeon->constant_cliprect);
+	radeon_get_cliprects(radeon, &radeon->pClipRects,
+			     &radeon->numClipRects, &x_off, &y_off);
 	
-	if ((draw_fb->Width != drawable->w) ||
-	    (draw_fb->Height != drawable->h)) {
-		_mesa_resize_framebuffer(radeon->glCtx, draw_fb,
+	if ((draw_rfb->base.Width != drawable->w) ||
+	    (draw_rfb->base.Height != drawable->h)) {
+		_mesa_resize_framebuffer(radeon->glCtx, &draw_rfb->base,
 					 drawable->w, drawable->h);
-		draw_fb->Initialized = GL_TRUE;
+		draw_rfb->base.Initialized = GL_TRUE;
 	}
 
 	if (drawable != readable) {
-		if ((read_fb->Width != readable->w) ||
-		    (read_fb->Height != readable->h)) {
-			_mesa_resize_framebuffer(radeon->glCtx, read_fb,
+		if ((read_rfb->base.Width != readable->w) ||
+		    (read_rfb->base.Height != readable->h)) {
+			_mesa_resize_framebuffer(radeon->glCtx, &read_rfb->base,
 						 readable->w, readable->h);
-			read_fb->Initialized = GL_TRUE;
+			read_rfb->base.Initialized = GL_TRUE;
 		}
 	}
 
 	if (radeon->state.scissor.enabled)
 		radeonRecalcScissorRects(radeon);
 
-	radeon->lastStamp = drawable->lastStamp;
 }
 
+
+
 void radeonUpdateScissor( GLcontext *ctx )
 {
 	radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
@@ -348,6 +368,37 @@ static void radeonWaitForIdle(radeonContextPtr radeon)
 	UNLOCK_HARDWARE(radeon);
 }
 
+static void radeon_flip_renderbuffers(struct radeon_framebuffer *rfb)
+{
+	int current_page = rfb->pf_current_page;
+	int next_page = (current_page + 1) % rfb->pf_num_pages;
+	struct gl_renderbuffer *tmp_rb;
+
+	/* Exchange renderbuffers if necessary but make sure their
+	 * reference counts are preserved.
+	 */
+	if (rfb->color_rb[current_page] &&
+	    rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer !=
+	    &rfb->color_rb[current_page]->base) {
+		tmp_rb = NULL;
+		_mesa_reference_renderbuffer(&tmp_rb,
+					     rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer);
+		tmp_rb = &rfb->color_rb[current_page]->base;
+		_mesa_reference_renderbuffer(&rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer, tmp_rb);
+		_mesa_reference_renderbuffer(&tmp_rb, NULL);
+	}
+
+	if (rfb->color_rb[next_page] &&
+	    rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer !=
+	    &rfb->color_rb[next_page]->base) {
+		tmp_rb = NULL;
+		_mesa_reference_renderbuffer(&tmp_rb,
+					     rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer);
+		tmp_rb = &rfb->color_rb[next_page]->base;
+		_mesa_reference_renderbuffer(&rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer, tmp_rb);
+		_mesa_reference_renderbuffer(&tmp_rb, NULL);
+	}
+}
 
 /* Copy the back color buffer to the front color buffer.
  */
@@ -355,10 +406,8 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv,
 		       const drm_clip_rect_t	  *rect)
 {
 	radeonContextPtr rmesa;
+	struct radeon_framebuffer *rfb;
 	GLint nbox, i, ret;
-	GLboolean   missed_target;
-	int64_t ust;
-	__DRIscreenPrivate *psp;
    
 	assert(dPriv);
 	assert(dPriv->driContextPriv);
@@ -366,24 +415,12 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv,
    
 	rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
 
+	rfb = dPriv->driverPrivate;
+
 	if ( RADEON_DEBUG & DEBUG_IOCTL ) {
 		fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx );
 	}
 
-	radeon_firevertices(rmesa);
-	LOCK_HARDWARE( rmesa );
-
-	/* Throttle the frame rate -- only allow one pending swap buffers
-	 * request at a time.
-	 */
-	radeonWaitForFrameCompletion( rmesa );
-	if (!rect)
-	{
-		UNLOCK_HARDWARE( rmesa );
-		driWaitForVBlank( dPriv, & missed_target );
-		LOCK_HARDWARE( rmesa );
-	}
-
 	nbox = dPriv->numClipRects; /* must be in locked region */
 
 	for ( i = 0 ; i < nbox ; ) {
@@ -429,94 +466,76 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv,
 	}
 
 	UNLOCK_HARDWARE( rmesa );
-	if (!rect)
-	{
-		psp = dPriv->driScreenPriv;
-		rmesa->swap_count++;
-		(*psp->systemTime->getUST)( & ust );
-		if ( missed_target ) {
-			rmesa->swap_missed_count++;
-			rmesa->swap_missed_ust = ust - rmesa->swap_ust;
-		}
+}
 
-		rmesa->swap_ust = ust;
-		rmesa->hw.all_dirty = GL_TRUE;
+static int radeonScheduleSwap(__DRIdrawablePrivate *dPriv, GLboolean *missed_target)
+{
+	radeonContextPtr rmesa;
+
+	rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
+	radeon_firevertices(rmesa);
 
+	LOCK_HARDWARE( rmesa );
+
+	if (!dPriv->numClipRects) {
+		UNLOCK_HARDWARE(rmesa);
+		usleep(10000);	/* throttle invisible client 10ms */
+		return 0;
 	}
+
+	radeonWaitForFrameCompletion(rmesa);
+
+	UNLOCK_HARDWARE(rmesa);
+	driWaitForVBlank(dPriv, missed_target);
+	LOCK_HARDWARE(rmesa);
+
+	return 0;
 }
 
-void radeonPageFlip( __DRIdrawablePrivate *dPriv )
+static GLboolean radeonPageFlip( __DRIdrawablePrivate *dPriv )
 {
-	radeonContextPtr rmesa;
+	radeonContextPtr radeon;
 	GLint ret;
-	GLboolean   missed_target;
 	__DRIscreenPrivate *psp;
 	struct radeon_renderbuffer *rrb;
-	GLframebuffer *fb = dPriv->driverPrivate;
-	
+	struct radeon_framebuffer *rfb;
+
 	assert(dPriv);
 	assert(dPriv->driContextPriv);
 	assert(dPriv->driContextPriv->driverPrivate);
 
-	rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
-	rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+	radeon = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
+	rfb = dPriv->driverPrivate;
+	rrb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
 
 	psp = dPriv->driScreenPriv;
 
 	if ( RADEON_DEBUG & DEBUG_IOCTL ) {
-		fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__,
-			rmesa->sarea->pfCurrentPage);
+		fprintf(stderr, "%s: pfCurrentPage: %d %d\n", __FUNCTION__,
+			radeon->sarea->pfCurrentPage, radeon->sarea->pfState);
 	}
-
-	radeon_firevertices(rmesa);
-
-	LOCK_HARDWARE( rmesa );
-
-	if (!dPriv->numClipRects) {
-		UNLOCK_HARDWARE(rmesa);
-		usleep(10000);	/* throttle invisible client 10ms */
-		return;
-	}
-
 	drm_clip_rect_t *box = dPriv->pClipRects;
-	drm_clip_rect_t *b = rmesa->sarea->boxes;
+	drm_clip_rect_t *b = radeon->sarea->boxes;
 	b[0] = box[0];
-	rmesa->sarea->nbox = 1;
-
-	/* Throttle the frame rate -- only allow a few pending swap buffers
-	 * request at a time.
-	 */
-	radeonWaitForFrameCompletion( rmesa );
-	UNLOCK_HARDWARE( rmesa );
-	driWaitForVBlank( dPriv, & missed_target );
-	if ( missed_target ) {
-		rmesa->swap_missed_count++;
-		(void) (*psp->systemTime->getUST)( & rmesa->swap_missed_ust );
-	}
-	LOCK_HARDWARE( rmesa );
+	radeon->sarea->nbox = 1;
 
-	ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_FLIP );
+	ret = drmCommandNone( radeon->dri.fd, DRM_RADEON_FLIP );
 	
-	UNLOCK_HARDWARE( rmesa );
+	UNLOCK_HARDWARE( radeon );
 
 	if ( ret ) {
 		fprintf( stderr, "DRM_RADEON_FLIP: return = %d\n", ret );
-		exit( 1 );
+		return GL_FALSE;
 	}
 
-	rmesa->swap_count++;
-	(void) (*psp->systemTime->getUST)( & rmesa->swap_ust );
-	
-	/* Get ready for drawing next frame.  Update the renderbuffers'
-	 * flippedOffset/Pitch fields so we draw into the right place.
-	 */
-	//	driFlipRenderbuffers(rmesa->glCtx->WinSysDrawBuffer,
-	//			     rmesa->sarea->pfCurrentPage);
-	
-	rmesa->state.color.rrb = rrb;
+	if (!rfb->pf_active)
+		return GL_FALSE;
+
+	rfb->pf_current_page = radeon->sarea->pfCurrentPage;
+	radeon_flip_renderbuffers(rfb);
+	radeon_draw_buffer(radeon->glCtx, &rfb->base);
 
-	if (rmesa->vtbl.update_draw_buffer)
-		rmesa->vtbl.update_draw_buffer(rmesa->glCtx);
+	return GL_TRUE;
 }
 
 
@@ -525,6 +544,9 @@ void radeonPageFlip( __DRIdrawablePrivate *dPriv )
  */
 void radeonSwapBuffers(__DRIdrawablePrivate * dPriv)
 {
+	int64_t ust;
+	__DRIscreenPrivate *psp;
+
 	if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) {
 		radeonContextPtr radeon;
 		GLcontext *ctx;
@@ -533,12 +555,29 @@ void radeonSwapBuffers(__DRIdrawablePrivate * dPriv)
 		ctx = radeon->glCtx;
 
 		if (ctx->Visual.doubleBufferMode) {
+			GLboolean missed_target;
+			struct radeon_framebuffer *rfb = dPriv->driverPrivate;
 			_mesa_notifySwapBuffers(ctx);/* flush pending rendering comands */
-			if (radeon->doPageFlip) {
+
+			radeonScheduleSwap(dPriv, &missed_target);
+
+			if (rfb->pf_active) {
 				radeonPageFlip(dPriv);
 			} else {
 				radeonCopyBuffer(dPriv, NULL);
 			}
+
+			psp = dPriv->driScreenPriv;
+
+			rfb->swap_count++;
+			(*psp->systemTime->getUST)( & ust );
+			if ( missed_target ) {
+				rfb->swap_missed_count++;
+				rfb->swap_missed_ust = ust - rfb->swap_ust;
+			}
+
+			rfb->swap_ust = ust;
+			radeon->hw.all_dirty = GL_TRUE;
 		}
 	} else {
 		/* XXX this shouldn't be an error but we can't handle it for now */
@@ -573,7 +612,224 @@ void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv,
 	}
 }
 
+void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
+{
+	radeonContextPtr radeon = RADEON_CONTEXT(ctx);
+	struct radeon_renderbuffer *rrbDepth = NULL, *rrbStencil = NULL,
+		*rrbColor = NULL;
+       
+
+	if (!fb) {
+		/* this can happen during the initial context initialization */
+		return;
+	}
+
+	/* radeons only handle 1 color draw so far */
+	if (fb->_NumColorDrawBuffers != 1) {
+		radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE);
+		return;
+	}
+		
+	/* Do this here, note core Mesa, since this function is called from
+	 * many places within the driver.
+	 */
+	if (ctx->NewState & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) {
+		/* this updates the DrawBuffer->_NumColorDrawBuffers fields, etc */
+		_mesa_update_framebuffer(ctx);
+		/* this updates the DrawBuffer's Width/Height if it's a FBO */
+		_mesa_update_draw_buffer_bounds(ctx);
+	}
+
+	if (fb->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) {
+		/* this may occur when we're called by glBindFrameBuffer() during
+		 * the process of someone setting up renderbuffers, etc.
+		 */
+		/*_mesa_debug(ctx, "DrawBuffer: incomplete user FBO\n");*/
+		return;
+	}
+
+	if (fb->Name)
+		;/* do something depthy/stencily TODO */
+
+
+		/* none */
+	if (fb->Name == 0) {
+		if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) {
+			rrbColor = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+			radeon->front_cliprects = GL_TRUE;
+		} else {
+			rrbColor = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+			radeon->front_cliprects = GL_FALSE;
+		}
+	} else {
+		/* user FBO in theory */
+		struct radeon_renderbuffer *rrb;
+		rrb = (void *)fb->_ColorDrawBuffers[0];
+		rrbColor = rrb;
+		radeon->constant_cliprect = GL_TRUE;
+	}
+
+	if (rrbColor == NULL)
+		radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE);
+	else
+		radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_FALSE);
+
+
+
+	if (fb->_DepthBuffer && fb->_DepthBuffer->Wrapped) {
+		rrbDepth = (struct radeon_renderbuffer *)fb->_DepthBuffer->Wrapped;
+		if (rrbDepth && rrbDepth->bo) {
+			radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_FALSE);
+		} else {
+			radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_TRUE);
+		}
+	} else {
+		radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_FALSE);
+		rrbDepth = NULL;
+	}
+
+	/* TODO stencil things */
+	if (fb->_StencilBuffer && fb->_StencilBuffer->Wrapped) {
+		rrbStencil = (struct radeon_renderbuffer *)fb->_DepthBuffer->Wrapped;
+		if (rrbStencil && rrbStencil->bo) {
+			radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_FALSE);
+			/* need to re-compute stencil hw state */
+			if (ctx->Driver.Enable != NULL)
+				ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled);
+			else
+				ctx->NewState |= _NEW_STENCIL;
+			if (!rrbDepth)
+				rrbDepth = rrbStencil;
+		} else {
+			radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_TRUE);
+		}
+	} else {
+		radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_FALSE);
+		if (ctx->Driver.Enable != NULL)
+			ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled);
+		else
+			ctx->NewState |= _NEW_STENCIL;
+	}
+
+	/* Update culling direction which changes depending on the
+	 * orientation of the buffer:
+	 */
+	if (ctx->Driver.FrontFace)
+		ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace);
+	else
+		ctx->NewState |= _NEW_POLYGON;
+	
+	/*
+	 * Update depth test state
+	 */
+	if (ctx->Driver.Enable) {
+		if (ctx->Depth.Test && fb->Visual.depthBits > 0) {
+			ctx->Driver.Enable(ctx, GL_DEPTH_TEST, GL_TRUE);
+		} else {
+			ctx->Driver.Enable(ctx, GL_DEPTH_TEST, GL_FALSE);
+		}
+	} else {
+		ctx->NewState |= _NEW_DEPTH;
+	}
+	
+	radeon->state.depth.rrb = rrbDepth;
+
+	radeon->state.color.rrb = rrbColor;
+
+	/* update viewport since it depends on window size */
+	if (ctx->Driver.Viewport) {
+		ctx->Driver.Viewport(ctx, ctx->Viewport.X, ctx->Viewport.Y,
+				     ctx->Viewport.Width, ctx->Viewport.Height);
+	} else {
+		ctx->NewState |= _NEW_VIEWPORT;
+	}
+
+	/* Set state we know depends on drawable parameters:
+	 */
+	if (ctx->Driver.Scissor)
+		ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y,
+				    ctx->Scissor.Width, ctx->Scissor.Height);
+	radeon->NewGLState |= _NEW_SCISSOR;
+}
+
+/**
+ * Called via glDrawBuffer.
+ */
+void radeonDrawBuffer( GLcontext *ctx, GLenum mode )
+{
+	radeonContextPtr radeon = RADEON_CONTEXT(ctx);
+	
+	if (RADEON_DEBUG & DEBUG_DRI)
+		fprintf(stderr, "%s %s\n", __FUNCTION__,
+			_mesa_lookup_enum_by_nr( mode ));
+	
+	radeon_firevertices(radeon);	/* don't pipeline cliprect changes */
+	
+	radeon_draw_buffer(ctx, ctx->DrawBuffer);
+}
+
+void radeonReadBuffer( GLcontext *ctx, GLenum mode )
+{
+	/* nothing, until we implement h/w glRead/CopyPixels or CopyTexImage */
+	if (ctx->ReadBuffer == ctx->DrawBuffer) {
+		/* This will update FBO completeness status.
+		 * A framebuffer will be incomplete if the GL_READ_BUFFER setting
+		 * refers to a missing renderbuffer.  Calling glReadBuffer can set
+		 * that straight and can make the drawing buffer complete.
+		 */
+		radeon_draw_buffer(ctx, ctx->DrawBuffer);
+	}
+}
 
+
+/* Turn on/off page flipping according to the flags in the sarea:
+ */
+void radeonUpdatePageFlipping(radeonContextPtr radeon)
+{
+	struct radeon_framebuffer *rfb = radeon->dri.drawable->driverPrivate;
+
+	rfb->pf_active = radeon->sarea->pfState;
+	rfb->pf_current_page = radeon->sarea->pfCurrentPage;
+	rfb->pf_num_pages = 2;
+	radeon_flip_renderbuffers(rfb);
+	radeon_draw_buffer(radeon->glCtx, radeon->glCtx->DrawBuffer);
+}
+
+void radeon_window_moved(radeonContextPtr radeon)
+{
+	GLcontext *ctx = radeon->glCtx;
+	__DRIdrawablePrivate *dPriv = radeon->dri.drawable;
+	struct radeon_framebuffer *rfb = dPriv->driverPrivate;
+
+	if (!radeon->radeonScreen->driScreen->dri2.enabled) {
+		radeonUpdatePageFlipping(radeon);
+	}
+	radeonSetCliprects(radeon);
+}
+
+void radeon_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei width, GLsizei height)
+{
+	radeonContextPtr radeon = RADEON_CONTEXT(ctx);
+	__DRIcontext *driContext = radeon->dri.context;
+	void (*old_viewport)(GLcontext *ctx, GLint x, GLint y,
+			     GLsizei w, GLsizei h);
+
+	if (!driContext->driScreenPriv->dri2.enabled)
+		return;
+
+	radeon_update_renderbuffers(driContext, driContext->driDrawablePriv);
+	if (driContext->driDrawablePriv != driContext->driReadablePriv)
+		radeon_update_renderbuffers(driContext, driContext->driReadablePriv);
+
+	old_viewport = ctx->Driver.Viewport;
+	ctx->Driver.Viewport = NULL;
+	radeon->dri.drawable = driContext->driDrawablePriv;
+	radeon_window_moved(radeon);
+	radeon_draw_buffer(ctx, radeon->glCtx->DrawBuffer);
+	ctx->Driver.Viewport = old_viewport;
+
+
+}
 static void radeon_print_state_atom(radeonContextPtr radeon, struct radeon_state_atom *state )
 {
 	int i;
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h
index ead0f5551b..95b718184b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common.h
@@ -14,7 +14,6 @@ void radeonWaitForIdleLocked(radeonContextPtr radeon);
 extern uint32_t radeonGetAge(radeonContextPtr radeon);
 void radeonCopyBuffer( __DRIdrawablePrivate *dPriv,
 		       const drm_clip_rect_t	  *rect);
-void radeonPageFlip( __DRIdrawablePrivate *dPriv );
 void radeonSwapBuffers(__DRIdrawablePrivate * dPriv);
 void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv,
 			 int x, int y, int w, int h );
@@ -25,6 +24,12 @@ void radeonFlush(GLcontext *ctx);
 void radeonFinish(GLcontext * ctx);
 void radeonEmitState(radeonContextPtr radeon);
 
+void radeon_window_moved(radeonContextPtr radeon);
+void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb);
+void radeonDrawBuffer( GLcontext *ctx, GLenum mode );
+void radeonReadBuffer( GLcontext *ctx, GLenum mode );
+void radeon_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei width, GLsizei height);
+
 static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPtr rmesa)
 {
 	struct radeon_renderbuffer *rrb;
@@ -38,11 +43,11 @@ static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPt
 static inline struct radeon_renderbuffer *radeon_get_colorbuffer(radeonContextPtr rmesa)
 {
 	struct radeon_renderbuffer *rrb;
-	GLframebuffer *fb = rmesa->dri.drawable->driverPrivate;
+	struct radeon_framebuffer *rfb = rmesa->dri.drawable->driverPrivate;
 
 	rrb = rmesa->state.color.rrb;
 	if (rmesa->radeonScreen->driScreen->dri2.enabled) {
-		rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+		rrb = (struct radeon_renderbuffer *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer;
 	}
 	if (!rrb)
 		return NULL;
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index 1b8a05d045..4da2055c13 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -35,7 +35,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "radeon_common.h"
 #include "xmlpool.h"		/* for symbolic values of enum-type options */
 #include "utils.h"
-#include "drirenderbuffer.h"
 #include "vblank.h"
 #include "main/state.h"
 
@@ -165,8 +164,6 @@ GLboolean radeonInitContext(radeonContextPtr radeon,
 			radeon->do_usleeps ? "usleeps" : "busy waits",
 			fthrottle_mode, radeon->radeonScreen->irq);
 
-	(*sPriv->systemTime->getUST) (&radeon->swap_ust);
-
 	return GL_TRUE;
 }
 
@@ -180,39 +177,39 @@ void radeonCleanupContext(radeonContextPtr radeon)
 	FILE *track;
 #endif
 	struct radeon_renderbuffer *rb;
-	GLframebuffer *fb;
+	struct radeon_framebuffer *rfb;
 
 	/* free the Mesa context */
 	_mesa_destroy_context(radeon->glCtx);
 	
-	fb = (void*)radeon->dri.drawable->driverPrivate;
-	rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+	rfb = (void*)radeon->dri.drawable->driverPrivate;
+	rb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
 	if (rb && rb->bo) {
 		radeon_bo_unref(rb->bo);
 		rb->bo = NULL;
 	}
-	rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+	rb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer;
 	if (rb && rb->bo) {
 		radeon_bo_unref(rb->bo);
 		rb->bo = NULL;
 	}
-	rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer;
+	rb = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer;
 	if (rb && rb->bo) {
 		radeon_bo_unref(rb->bo);
 		rb->bo = NULL;
 	}
-	fb = (void*)radeon->dri.readable->driverPrivate;
-	rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+	rfb = (void*)radeon->dri.readable->driverPrivate;
+	rb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
 	if (rb && rb->bo) {
 		radeon_bo_unref(rb->bo);
 		rb->bo = NULL;
 	}
-	rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+	rb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer;
 	if (rb && rb->bo) {
 		radeon_bo_unref(rb->bo);
 		rb->bo = NULL;
 	}
-	rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer;
+	rb = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer;
 	if (rb && rb->bo) {
 		radeon_bo_unref(rb->bo);
 		rb->bo = NULL;
@@ -260,12 +257,12 @@ GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv)
 
 static void
 radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon,
-					GLframebuffer *draw)
+					struct radeon_framebuffer *draw)
 {
 	/* if radeon->fake */
 	struct radeon_renderbuffer *rb;
 
-	if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
+	if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
 		if (!rb->bo) {
 			rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 						radeon->radeonScreen->frontOffset,
@@ -277,7 +274,7 @@ radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon,
 		rb->cpp = radeon->radeonScreen->cpp;
 		rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp;
 	}
-	if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
+	if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
 		if (!rb->bo) {
 			rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 						radeon->radeonScreen->backOffset,
@@ -289,7 +286,7 @@ radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon,
 		rb->cpp = radeon->radeonScreen->cpp;
 		rb->pitch = radeon->radeonScreen->backPitch * rb->cpp;
 	}
-	if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) {
+	if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) {
 		if (!rb->bo) {
 			rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 						radeon->radeonScreen->depthOffset,
@@ -301,7 +298,7 @@ radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon,
 		rb->cpp = radeon->radeonScreen->cpp;
 		rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
 	}
-	if ((rb = (void *)draw->Attachment[BUFFER_STENCIL].Renderbuffer)) {
+	if ((rb = (void *)draw->base.Attachment[BUFFER_STENCIL].Renderbuffer)) {
 		if (!rb->bo) {
 			rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 						radeon->radeonScreen->depthOffset,
@@ -317,7 +314,7 @@ radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon,
 
 static void
 radeon_make_renderbuffer_current(radeonContextPtr radeon,
-					GLframebuffer *draw)
+				 struct radeon_framebuffer *draw)
 {
 	int size = 4096*4096*4;
 	/* if radeon->fake */
@@ -329,7 +326,7 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon,
 	}
 			
 
-	if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
+	if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
 		if (!rb->bo) {
 			rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 						radeon->radeonScreen->frontOffset +
@@ -342,7 +339,7 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon,
 		rb->cpp = radeon->radeonScreen->cpp;
 		rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp;
 	}
-	if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
+	if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
 		if (!rb->bo) {
 			rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 						radeon->radeonScreen->backOffset +
@@ -355,7 +352,7 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon,
 		rb->cpp = radeon->radeonScreen->cpp;
 		rb->pitch = radeon->radeonScreen->backPitch * rb->cpp;
 	}
-	if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) {
+	if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) {
 		if (!rb->bo) {
 			rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 						radeon->radeonScreen->depthOffset +
@@ -368,7 +365,7 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon,
 		rb->cpp = radeon->radeonScreen->cpp;
 		rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
 	}
-	if ((rb = (void *)draw->Attachment[BUFFER_STENCIL].Renderbuffer)) {
+	if ((rb = (void *)draw->base.Attachment[BUFFER_STENCIL].Renderbuffer)) {
 		if (!rb->bo) {
 			rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 						radeon->radeonScreen->depthOffset +
@@ -392,7 +389,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 	__DRIscreen *screen;
 	struct radeon_renderbuffer *rb;
 	int i, count;
-	GLframebuffer *draw;
+	struct radeon_framebuffer *draw;
 	radeonContextPtr radeon;
 
 	if (RADEON_DEBUG & DEBUG_DRI)
@@ -402,13 +399,13 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 	screen = context->driScreenPriv;
 	radeon = (radeonContextPtr) context->driverPrivate;
 	i = 0;
-	if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
+	if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
 		attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
 	}
-	if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
+	if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
 		attachments[i++] = __DRI_BUFFER_BACK_LEFT;
 	}
-	if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) {
+	if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) {
 		attachments[i++] = __DRI_BUFFER_DEPTH;
 	}
 	
@@ -439,7 +436,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 	for (i = 0; i < count; i++) {
 		switch (buffers[i].attachment) {
 		case __DRI_BUFFER_FRONT_LEFT:
-			rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+			rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
 			if (rb->bo) {
 				radeon_bo_unref(rb->bo);
 				rb->bo = NULL;
@@ -461,7 +458,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 			}
 			break;
 		case __DRI_BUFFER_BACK_LEFT:
-			rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+			rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer;
 			if (rb->bo) {
 				radeon_bo_unref(rb->bo);
 				rb->bo = NULL;
@@ -479,7 +476,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 						buffers[i].flags);
 			break;
 		case __DRI_BUFFER_DEPTH:
-			rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer;
+			rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer;
 			if (rb->bo) {
 				radeon_bo_unref(rb->bo);
 				rb->bo = NULL;
@@ -518,7 +515,8 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
 			    __DRIdrawablePrivate * driReadPriv)
 {
 	radeonContextPtr radeon;
-	GLframebuffer *dfb, *rfb;
+	struct radeon_framebuffer *drfb;
+	struct gl_framebuffer *readfb;
 
 	if (!driContextPriv) {
 		if (RADEON_DEBUG & DEBUG_DRI)
@@ -526,61 +524,65 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
 		_mesa_make_current(NULL, NULL, NULL);
 		return GL_TRUE;
 	}
+
 	radeon = (radeonContextPtr) driContextPriv->driverPrivate;
-	dfb = driDrawPriv->driverPrivate;
-	rfb = driReadPriv->driverPrivate;
+	drfb = driDrawPriv->driverPrivate;
+	readfb = driReadPriv->driverPrivate;
 
 	if (driContextPriv->driScreenPriv->dri2.enabled) {    
 		radeon_update_renderbuffers(driContextPriv, driDrawPriv);
 		if (driDrawPriv != driReadPriv)
 			radeon_update_renderbuffers(driContextPriv, driReadPriv);
 		radeon->state.color.rrb =
-			(void *)dfb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+			(void *)drfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer;
 		radeon->state.depth.rrb =
-			(void *)dfb->Attachment[BUFFER_DEPTH].Renderbuffer;
+			(void *)drfb->base.Attachment[BUFFER_DEPTH].Renderbuffer;
 	} else {
-		radeon_make_renderbuffer_current(radeon, dfb);
+		radeon_make_renderbuffer_current(radeon, drfb);
 	}
 
 
 	if (RADEON_DEBUG & DEBUG_DRI)
-	     fprintf(stderr, "%s ctx %p dfb %p rfb %p\n", __FUNCTION__, radeon->glCtx, dfb, rfb);
+	     fprintf(stderr, "%s ctx %p dfb %p rfb %p\n", __FUNCTION__, radeon->glCtx, drfb, readfb);
 
 	driUpdateFramebufferSize(radeon->glCtx, driDrawPriv);
 	if (driReadPriv != driDrawPriv)
 		driUpdateFramebufferSize(radeon->glCtx, driReadPriv);
 
+	_mesa_make_current(radeon->glCtx, &drfb->base, readfb);
 
-	
-	_mesa_make_current(radeon->glCtx, dfb, rfb);
-
-	if (radeon->dri.drawable != driDrawPriv) {
-		if (driDrawPriv->swap_interval == (unsigned)-1) {
-			driDrawPriv->vblFlags =
-				(radeon->radeonScreen->irq != 0)
-				? driGetDefaultVBlankFlags(&radeon->
-							   optionCache)
-					: VBLANK_FLAG_NO_IRQ;
-
-			driDrawableInitVBlank(driDrawPriv);
-		}
-	}
+	_mesa_update_state(radeon->glCtx);
 
-	radeon->dri.readable = driReadPriv;
+	if (radeon->glCtx->DrawBuffer == &drfb->base) {
 
-	if (radeon->dri.drawable != driDrawPriv ||
-	    radeon->lastStamp != driDrawPriv->lastStamp) {
-		radeon->dri.drawable = driDrawPriv;
+		if (radeon->dri.readable != driReadPriv)
+			radeon->dri.readable = driReadPriv;
 
-		radeonSetCliprects(radeon);
-		radeon->vtbl.update_viewport_offset(radeon->glCtx);
+		if (radeon->dri.drawable != driDrawPriv) {
+			if (driDrawPriv->swap_interval == (unsigned)-1) {
+				int i;
+				driDrawPriv->vblFlags =
+					(radeon->radeonScreen->irq != 0)
+					? driGetDefaultVBlankFlags(&radeon->
+								   optionCache)
+					: VBLANK_FLAG_NO_IRQ;
+				    
+				driDrawableInitVBlank(driDrawPriv);
+				drfb->vbl_waited = driDrawPriv->vblSeq;
+
+				for (i = 0; i < 2; i++) {
+					if (drfb->color_rb[i])
+						drfb->color_rb[i]->vbl_pending = driDrawPriv->vblSeq;
+				}
+				    
+			}
+			radeon->dri.drawable = driDrawPriv;
+			
+//			radeonWindowMoved(radeon);
+		}
+		radeon_draw_buffer(radeon->glCtx, &drfb->base);
 	}
 
-	_mesa_update_state(radeon->glCtx);
-
-	if (!driContextPriv->driScreenPriv->dri2.enabled) {    
-		radeonUpdatePageFlipping(radeon);
-	}
 
 	if (RADEON_DEBUG & DEBUG_DRI)
 		fprintf(stderr, "End %s\n", __FUNCTION__);
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index a200e90221..4aeb50fe68 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -39,6 +39,8 @@ typedef struct radeon_context *radeonContextPtr;
 #define RADEON_FALLBACK_BLEND_FUNC	0x0020
 #define RADEON_FALLBACK_DISABLE 	0x0040
 #define RADEON_FALLBACK_BORDER_MODE	0x0080
+#define RADEON_FALLBACK_DEPTH_BUFFER	0x0100
+#define RADEON_FALLBACK_STENCIL_BUFFER  0x0200
 
 #define R200_FALLBACK_TEXTURE           0x01
 #define R200_FALLBACK_DRAW_BUFFER       0x02
@@ -81,9 +83,34 @@ struct radeon_renderbuffer
 	/* boo Xorg 6.8.2 compat */
 	int has_surface;
 
+	GLuint pf_pending;  /**< sequence number of pending flip */
+	GLuint vbl_pending;   /**< vblank sequence number of pending flip */
 	__DRIdrawablePrivate *dPriv;
 };
 
+struct radeon_framebuffer
+{
+	struct gl_framebuffer base;
+
+	struct radeon_renderbuffer *color_rb[2];
+
+	GLuint vbl_waited;
+
+	/* buffer swap */
+	int64_t swap_ust;
+	int64_t swap_missed_ust;
+
+	GLuint swap_count;
+	GLuint swap_missed_count;
+
+	/* Drawable page flipping state */
+	GLboolean pf_active;
+	GLint pf_current_page;
+	GLint pf_num_pages;
+
+};
+
+ 
 struct radeon_colorbuffer_state {
 	GLuint clear;
 	int roundEnable;
@@ -387,9 +414,6 @@ struct radeon_context {
    GLuint NewGLState;
    DECLARE_RENDERINPUTS(tnl_index_bitset);	/* index of bits for last tnl_install_attrs */
 
-   /* Page flipping */
-   GLuint doPageFlip;
-
    /* Drawable, cliprect and scissor information */
    GLuint numClipRects;	/* Cliprects for the draw buffer */
    drm_clip_rect_t *pClipRects;
@@ -406,13 +430,6 @@ struct radeon_context {
    GLuint irqsEmitted;
    drm_radeon_irq_wait_t iw;
 
-   /* buffer swap */
-   int64_t swap_ust;
-   int64_t swap_missed_ust;
-
-   GLuint swap_count;
-   GLuint swap_missed_count;
-
    /* Derived state - for r300 only */
    struct radeon_state state;
 
@@ -422,15 +439,19 @@ struct radeon_context {
    driOptionCache optionCache;
 
    struct radeon_cmdbuf cmdbuf;
+	
+	drm_clip_rect_t fboRect;
+	GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */
+	GLboolean front_cliprects;
 
    struct {
 	   void (*get_lock)(radeonContextPtr radeon);
 	   void (*update_viewport_offset)(GLcontext *ctx);
-	   void (*update_draw_buffer)(GLcontext *ctx);
 	   void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa);
 	   void (*swtcl_flush)(GLcontext *ctx, uint32_t offset);
 	   void (*pre_emit_atoms)(radeonContextPtr rmesa);
 	   void (*pre_emit_state)(radeonContextPtr rmesa);
+	   void (*fallback)(GLcontext *ctx, GLuint bit, GLboolean mode);
    } vtbl;
 };
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c
index e4202c71fc..47ebe41c6d 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -186,10 +186,10 @@ static void r100_init_vtbl(radeonContextPtr radeon)
 {
    radeon->vtbl.get_lock = r100_get_lock;
    radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset;
-   radeon->vtbl.update_draw_buffer = radeonUpdateDrawBuffer;
    radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header;
    radeon->vtbl.swtcl_flush = r100_swtcl_flush;
    radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state;
+   radeon->vtbl.fallback = radeonFallback;
 }
 
 /* Create the device specific context.
@@ -369,8 +369,6 @@ radeonCreateContext( const __GLcontextModes *glVisual,
 
    rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
 
-   (*sPriv->systemTime->getUST)( & rmesa->radeon.swap_ust );
-
 
 #if DO_DEBUG
    RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c
index 9a7e76b245..fb9e5e025e 100644
--- a/src/mesa/drivers/dri/radeon/radeon_lock.c
+++ b/src/mesa/drivers/dri/radeon/radeon_lock.c
@@ -48,37 +48,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "radeon_lock.h"
 #include "drirenderbuffer.h"
 
-#if DEBUG_LOCKING
-char *prevLockFile = NULL;
-int prevLockLine = 0;
-#endif
-
-/* Turn on/off page flipping according to the flags in the sarea:
- */
-void radeonUpdatePageFlipping(radeonContextPtr rmesa)
-{
-	int use_back;
-	__DRIdrawablePrivate *const drawable = rmesa->dri.drawable;
-	GLframebuffer *fb = drawable->driverPrivate;
-
-	rmesa->doPageFlip = rmesa->sarea->pfState;
-	if (rmesa->glCtx->WinSysDrawBuffer) {
-		rmesa->vtbl.update_draw_buffer(rmesa->glCtx);
-	}
-
-	use_back = rmesa->glCtx->DrawBuffer ?
-	    (rmesa->glCtx->DrawBuffer->_ColorDrawBufferIndexes[0] ==
-	     BUFFER_BACK_LEFT) : 1;
-	use_back ^= (rmesa->sarea->pfCurrentPage == 1);
-
-	if (use_back)
-		rmesa->state.color.rrb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
-	else
-		rmesa->state.color.rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
-
-	rmesa->state.depth.rrb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer;
-}
-
 /* Update the hardware state.  This is called if another context has
  * grabbed the hardware lock, which includes the X server.  This
  * function also updates the driver's window state after the X server
@@ -112,13 +81,52 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags)
 	}
 
 	if (rmesa->lastStamp != drawable->lastStamp) {
-		radeonUpdatePageFlipping(rmesa);
-		radeonSetCliprects(rmesa);
-		rmesa->vtbl.update_viewport_offset(rmesa->glCtx);
-		driUpdateFramebufferSize(rmesa->glCtx, drawable);
+		radeon_window_moved(rmesa);
+		rmesa->lastStamp = drawable->lastStamp;
 	}
 
 	rmesa->vtbl.get_lock(rmesa);
 
 	rmesa->lost_context = GL_TRUE;
 }
+
+static INLINE struct radeon_renderbuffer *
+radeon_get_renderbuffer(struct gl_framebuffer *fb, int attIndex)
+{
+	if (attIndex >= 0)
+		return (struct radeon_renderbuffer *)fb->Attachment[attIndex].Renderbuffer;
+	else
+		return NULL;
+}
+
+void radeon_lock_hardware(radeonContextPtr radeon)
+{
+	__DRIdrawable *dPriv = radeon->dri.drawable;
+	char ret = 0;
+	struct radeon_framebuffer *rfb = NULL;
+	struct radeon_renderbuffer *rrb = NULL;
+
+	if (radeon->dri.drawable) {
+		rfb = radeon->dri.drawable->driverPrivate;
+
+		if (rfb)
+			rrb = radeon_get_renderbuffer(&rfb->base,
+						      rfb->base._ColorDrawBufferIndexes[0]);
+	}
+
+	if (!radeon->radeonScreen->driScreen->dri2.enabled) {
+		DRM_CAS(radeon->dri.hwLock, radeon->dri.hwContext,
+			 (DRM_LOCK_HELD | radeon->dri.hwContext), ret );
+		if (ret)
+			radeonGetLock(radeon, 0);
+	}
+}
+
+void radeon_unlock_hardware(radeonContextPtr radeon)
+{
+	if (!radeon->radeonScreen->driScreen->dri2.enabled) {
+		DRM_UNLOCK( radeon->dri.fd,
+			    radeon->dri.hwLock,
+			    radeon->dri.hwContext );
+	}
+}
diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.h b/src/mesa/drivers/dri/radeon/radeon_lock.h
index f5ebb8dd54..2817709eed 100644
--- a/src/mesa/drivers/dri/radeon/radeon_lock.h
+++ b/src/mesa/drivers/dri/radeon/radeon_lock.h
@@ -48,73 +48,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 extern void radeonGetLock(radeonContextPtr rmesa, GLuint flags);
 
-/* Turn DEBUG_LOCKING on to find locking conflicts.
- */
-#define DEBUG_LOCKING	0
-
-#if DEBUG_LOCKING
-extern char *prevLockFile;
-extern int prevLockLine;
-
-#define DEBUG_LOCK()							\
-   do {									\
-      prevLockFile = (__FILE__);					\
-      prevLockLine = (__LINE__);					\
-   } while (0)
-
-#define DEBUG_RESET()							\
-   do {									\
-      prevLockFile = 0;							\
-      prevLockLine = 0;							\
-   } while (0)
-
-#define DEBUG_CHECK_LOCK()						\
-   do {									\
-      if ( prevLockFile ) {						\
-	 fprintf( stderr,						\
-		  "LOCK SET!\n\tPrevious %s:%d\n\tCurrent: %s:%d\n",	\
-		  prevLockFile, prevLockLine, __FILE__, __LINE__ );	\
-	 exit( 1 );							\
-      }									\
-   } while (0)
-
-#else
-
-#define DEBUG_LOCK()
-#define DEBUG_RESET()
-#define DEBUG_CHECK_LOCK()
-
-#endif
-
-/*
- * !!! We may want to separate locks from locks with validation.  This
- * could be used to improve performance for those things commands that
- * do not do any drawing !!!
- */
+void radeon_lock_hardware(radeonContextPtr rmesa);
+void radeon_unlock_hardware(radeonContextPtr rmesa);
 
 /* Lock the hardware and validate our state.
  */
-#define LOCK_HARDWARE( rmesa )					\
-   do {								\
-      char __ret = 0;						\
-      DEBUG_CHECK_LOCK();					\
-      if (!(rmesa)->radeonScreen->driScreen->dri2.enabled) {		\
-	DRM_CAS( (rmesa)->dri.hwLock, (rmesa)->dri.hwContext,		\
-		 (DRM_LOCK_HELD | (rmesa)->dri.hwContext), __ret );	\
-	if ( __ret )							\
-	  radeonGetLock( (rmesa), 0 );					\
-      }									\
-      DEBUG_LOCK();							\
-   } while (0)
-
-#define UNLOCK_HARDWARE( rmesa )					\
-   do {									\
-     if (!(rmesa)->radeonScreen->driScreen->dri2.enabled) {		\
-       DRM_UNLOCK( (rmesa)->dri.fd,					\
-		   (rmesa)->dri.hwLock,					\
-		   (rmesa)->dri.hwContext );				\
-       DEBUG_RESET();							\
-     }									\
-   } while (0)
+#define LOCK_HARDWARE( rmesa )	radeon_lock_hardware(rmesa)
+#define UNLOCK_HARDWARE( rmesa )  radeon_unlock_hardware(rmesa)
 
 #endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 78f0bc2514..bf5f5c98bd 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -1262,7 +1262,7 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
                     const __GLcontextModes *mesaVis,
                     GLboolean isPixmap )
 {
-   radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
+    radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
 
     const GLboolean swDepth = GL_FALSE;
     const GLboolean swAlpha = GL_FALSE;
@@ -1271,7 +1271,16 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
 	mesaVis->depthBits != 24;
     GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8);
     GLenum depthFormat = GL_NONE;
-    struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
+    struct radeon_framebuffer *rfb;
+
+    if (isPixmap)
+      return GL_FALSE; /* not implemented */
+
+    rfb = CALLOC_STRUCT(radeon_framebuffer);
+    if (!rfb)
+      return GL_FALSE;
+
+    _mesa_initialize_framebuffer(&rfb->base, mesaVis);
 
     if (mesaVis->depthBits == 16)
 	depthFormat = GL_DEPTH_COMPONENT16;
@@ -1279,26 +1288,22 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
 	depthFormat = GL_DEPTH_COMPONENT24;
 
     /* front color renderbuffer */
-    {
-	struct radeon_renderbuffer *front =
-	    radeon_create_renderbuffer(rgbFormat, driDrawPriv);
-	_mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &front->base);
-	front->has_surface = 1;
-    }
+    rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
+    _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base);
+    rfb->color_rb[0]->has_surface = 1;
 
     /* back color renderbuffer */
     if (mesaVis->doubleBufferMode) {
-	struct radeon_renderbuffer *back =
-	    radeon_create_renderbuffer(rgbFormat, driDrawPriv);
-	_mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &back->base);
-	back->has_surface = 1;
+	rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
+	_mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base);
+	rfb->color_rb[1]->has_surface = 1;
     }
 
     /* depth renderbuffer */
     if (depthFormat != GL_NONE) {
 	struct radeon_renderbuffer *depth =
 	    radeon_create_renderbuffer(depthFormat, driDrawPriv);
-	_mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depth->base);
+	_mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
 	depth->has_surface = screen->depthHasSurface;
     }
 
@@ -1306,18 +1311,18 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
     if (mesaVis->stencilBits > 0 && !swStencil) {
 	struct radeon_renderbuffer *stencil =
 	    radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv);
-	_mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencil->base);
+	_mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &stencil->base);
 	stencil->has_surface = screen->depthHasSurface;
     }
 
-    _mesa_add_soft_renderbuffers(fb,
+    _mesa_add_soft_renderbuffers(&rfb->base,
 	    GL_FALSE, /* color */
 	    swDepth,
 	    swStencil,
 	    swAccum,
 	    swAlpha,
 	    GL_FALSE /* aux */);
-    driDrawPriv->driverPrivate = (void *) fb;
+    driDrawPriv->driverPrivate = (void *) rfb;
 
     return (driDrawPriv->driverPrivate != NULL);
 }
@@ -1325,21 +1330,21 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
 static void
 radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
 {
-	struct radeon_renderbuffer *rb;
-	GLframebuffer *fb;
+    struct radeon_renderbuffer *rb;
+    struct radeon_framebuffer *rfb;
     
-    fb = (void*)driDrawPriv->driverPrivate;
-    rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+    rfb = (void*)driDrawPriv->driverPrivate;
+    rb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
     if (rb && rb->bo) {
         radeon_bo_unref(rb->bo);
         rb->bo = NULL;
     }
-    rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+    rb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer;
     if (rb && rb->bo) {
         radeon_bo_unref(rb->bo);
         rb->bo = NULL;
     }
-    rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer;
+    rb = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer;
     if (rb && rb->bo) {
         radeon_bo_unref(rb->bo);
         rb->bo = NULL;
@@ -1541,21 +1546,21 @@ __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp)
 static int
 getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
 {
-   radeonContextPtr  rmesa;
+    struct radeon_framebuffer *rfb;
 
-   if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
-	|| (dPriv->driContextPriv->driverPrivate == NULL)
-	|| (sInfo == NULL) ) {
-      return -1;
+    if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
+	 || (dPriv->driContextPriv->driverPrivate == NULL)
+	 || (sInfo == NULL) ) {
+	return -1;
    }
 
-   rmesa = dPriv->driContextPriv->driverPrivate;
-   sInfo->swap_count = rmesa->swap_count;
-   sInfo->swap_ust = rmesa->swap_ust;
-   sInfo->swap_missed_count = rmesa->swap_missed_count;
+    rfb = dPriv->driverPrivate;
+    sInfo->swap_count = rfb->swap_count;
+    sInfo->swap_ust = rfb->swap_ust;
+    sInfo->swap_missed_count = rfb->swap_missed_count;
 
    sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
-       ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
+       ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust )
        : 0.0;
 
    return 0;
diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c
index 5fffa286fe..0c92a6ff08 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state.c
@@ -1418,6 +1418,8 @@ static void radeonViewport( GLcontext *ctx, GLint x, GLint y,
     * values, or keep the originals hanging around.
     */
    radeonUpdateWindow( ctx );
+
+   radeon_viewport(ctx, x, y, width, height);
 }
 
 static void radeonDepthRange( GLcontext *ctx, GLclampd nearval,
@@ -1532,50 +1534,6 @@ static void radeonLogicOpCode( GLcontext *ctx, GLenum opcode )
    rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = radeon_rop_tab[rop];
 }
 
-
-/**
- * Called via glDrawBuffer.
- */
-static void radeonDrawBuffer( GLcontext *ctx, GLenum mode )
-{
-   r100ContextPtr rmesa = R100_CONTEXT(ctx);
-
-   if (RADEON_DEBUG & DEBUG_DRI)
-      fprintf(stderr, "%s %s\n", __FUNCTION__,
-	      _mesa_lookup_enum_by_nr( mode ));
-
-   radeon_firevertices(&rmesa->radeon);	/* don't pipeline cliprect changes */
-
-   if (ctx->DrawBuffer->_NumColorDrawBuffers != 1) {
-      /* 0 (GL_NONE) buffers or multiple color drawing buffers */
-      FALLBACK( rmesa, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE );
-      return;
-   }
-
-   switch ( ctx->DrawBuffer->_ColorDrawBufferIndexes[0] ) {
-   case BUFFER_FRONT_LEFT:
-   case BUFFER_BACK_LEFT:
-      FALLBACK( rmesa, RADEON_FALLBACK_DRAW_BUFFER, GL_FALSE );
-      break;
-   default:
-      FALLBACK( rmesa, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE );
-      return;
-   }
-
-   radeonSetCliprects( &rmesa->radeon );
-   if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled)
-      radeonUpdatePageFlipping(&rmesa->radeon);
-   /* We'll set the drawing engine's offset/pitch parameters later
-    * when we update other state.
-    */
-}
-
-static void radeonReadBuffer( GLcontext *ctx, GLenum mode )
-{
-   /* nothing, until we implement h/w glRead/CopyPixels or CopyTexImage */
-}
-
-
 /* =============================================================
  * State enable/disable
  */
@@ -2066,42 +2024,16 @@ static void update_texturematrix( GLcontext *ctx )
 }
 
 
-/**
- * Tell the card where to render (offset, pitch).
- * Effected by glDrawBuffer, etc
- */
-void
-radeonUpdateDrawBuffer(GLcontext *ctx)
-{
-   r100ContextPtr rmesa = R100_CONTEXT(ctx);
-   struct gl_framebuffer *fb = ctx->DrawBuffer;
-   struct radeon_renderbuffer *rrb;
-
-   if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) {
-     /* draw to front */
-     rrb = (void *) fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
-   } else if (fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) {
-     /* draw to back */
-     rrb = (void *) fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
-   } else {
-     /* drawing to multiple buffers, or none */
-     return;
-   }
-
-   assert(rrb);
-   assert(rrb->pitch);
-
-   RADEON_STATECHANGE( rmesa, ctx );
-}
-
-
 void radeonValidateState( GLcontext *ctx )
 {
    r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLuint new_state = rmesa->radeon.NewGLState;
 
    if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) {
-     radeonUpdateDrawBuffer(ctx);
+     _mesa_update_framebuffer(ctx);
+     /* this updates the DrawBuffer's Width/Height if it's a FBO */
+     _mesa_update_draw_buffer_bounds(ctx);
+     RADEON_STATECHANGE(rmesa, ctx);
    }
 
    if (new_state & _NEW_TEXTURE) {
-- 
cgit v1.2.3


From bdaa0341caffc353fd26bbd91865c2d86eed11c1 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 19 Mar 2009 15:31:03 +1000
Subject: radeon/r200/r300: cleanup some of the renderbuffer code

---
 src/mesa/drivers/dri/r200/r200_texstate.c          |   2 +-
 src/mesa/drivers/dri/r300/r300_texstate.c          |   2 +-
 src/mesa/drivers/dri/radeon/radeon_common.h        |  19 +++-
 .../drivers/dri/radeon/radeon_common_context.c     | 114 +++++++++------------
 .../drivers/dri/radeon/radeon_common_context.h     |   2 +
 src/mesa/drivers/dri/radeon/radeon_lock.c          |   9 --
 src/mesa/drivers/dri/radeon/radeon_screen.c        |   1 +
 src/mesa/drivers/dri/radeon/radeon_texstate.c      |   2 +-
 8 files changed, 71 insertions(+), 80 deletions(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_common_context.h')

diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c
index 4937b0665d..058e0ee5be 100644
--- a/src/mesa/drivers/dri/r200/r200_texstate.c
+++ b/src/mesa/drivers/dri/r200/r200_texstate.c
@@ -806,7 +806,7 @@ void r200SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv)
 		radeon_bo_unref(rb->bo);
 		rb->bo = NULL;
 	}
-	rb = (void*)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+	rb = rfb->color_rb[0];
 	if (rb->bo == NULL) {
 		/* Failed to BO for the buffer */
 		return;
diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c
index 2d7f392e7c..14d470a11c 100644
--- a/src/mesa/drivers/dri/r300/r300_texstate.c
+++ b/src/mesa/drivers/dri/r300/r300_texstate.c
@@ -425,7 +425,7 @@ void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv)
 		radeon_bo_unref(rb->bo);
 		rb->bo = NULL;
 	}
-	rb = (void*)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+	rb = rfb->color_rb[0];
 	if (rb->bo == NULL) {
 		/* Failed to BO for the buffer */
 		return;
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h
index 95b718184b..814da1b4f5 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common.h
@@ -30,6 +30,23 @@ void radeonDrawBuffer( GLcontext *ctx, GLenum mode );
 void radeonReadBuffer( GLcontext *ctx, GLenum mode );
 void radeon_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei width, GLsizei height);
 
+static inline struct radeon_renderbuffer *radeon_renderbuffer(struct gl_renderbuffer *rb)
+{
+	struct radeon_renderbuffer *rrb = (struct radeon_renderbuffer *)rb;
+	if (rrb && rrb->base.ClassID == RADEON_RB_CLASS)
+		return rrb;
+	else
+		return NULL;
+}
+
+static inline struct radeon_renderbuffer *radeon_get_renderbuffer(struct gl_framebuffer *fb, int att_index)
+{
+	if (att_index >= 0)
+		return radeon_renderbuffer(fb->Attachment[att_index].Renderbuffer);
+	else
+		return NULL;
+}
+
 static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPtr rmesa)
 {
 	struct radeon_renderbuffer *rrb;
@@ -47,7 +64,7 @@ static inline struct radeon_renderbuffer *radeon_get_colorbuffer(radeonContextPt
 
 	rrb = rmesa->state.color.rrb;
 	if (rmesa->radeonScreen->driScreen->dri2.enabled) {
-		rrb = (struct radeon_renderbuffer *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+		rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT);
 	}
 	if (!rrb)
 		return NULL;
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index b63aba2f89..a818440faf 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -183,33 +183,33 @@ void radeonCleanupContext(radeonContextPtr radeon)
 	_mesa_destroy_context(radeon->glCtx);
 	
 	rfb = (void*)radeon->dri.drawable->driverPrivate;
-	rb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+	rb = rfb->color_rb[0];
 	if (rb && rb->bo) {
 		radeon_bo_unref(rb->bo);
 		rb->bo = NULL;
 	}
-	rb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+	rb = rfb->color_rb[1];
 	if (rb && rb->bo) {
 		radeon_bo_unref(rb->bo);
 		rb->bo = NULL;
 	}
-	rb = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer;
+	rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
 	if (rb && rb->bo) {
 		radeon_bo_unref(rb->bo);
 		rb->bo = NULL;
 	}
 	rfb = (void*)radeon->dri.readable->driverPrivate;
-	rb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+	rb = rfb->color_rb[0];
 	if (rb && rb->bo) {
 		radeon_bo_unref(rb->bo);
 		rb->bo = NULL;
 	}
-	rb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+	rb = rfb->color_rb[1];
 	if (rb && rb->bo) {
 		radeon_bo_unref(rb->bo);
 		rb->bo = NULL;
 	}
-	rb = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer;
+	rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
 	if (rb && rb->bo) {
 		radeon_bo_unref(rb->bo);
 		rb->bo = NULL;
@@ -391,6 +391,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 	int i, count;
 	struct radeon_framebuffer *draw;
 	radeonContextPtr radeon;
+	char *regname;
 
 	if (RADEON_DEBUG & DEBUG_DRI)
 	    fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable);
@@ -399,15 +400,14 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 	screen = context->driScreenPriv;
 	radeon = (radeonContextPtr) context->driverPrivate;
 	i = 0;
-	if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
+	if (draw->color_rb[0])
 		attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
-	}
-	if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
+	if (draw->color_rb[1])
 		attachments[i++] = __DRI_BUFFER_BACK_LEFT;
-	}
-	if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) {
+	if (radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH))
 		attachments[i++] = __DRI_BUFFER_DEPTH;
-	}
+	if (radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL))
+		attachments[i++] = __DRI_BUFFER_STENCIL;
 	
 	buffers = (*screen->dri2.loader->getBuffers)(drawable,
 						     &drawable->w,
@@ -436,64 +436,20 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 	for (i = 0; i < count; i++) {
 		switch (buffers[i].attachment) {
 		case __DRI_BUFFER_FRONT_LEFT:
-			rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
-			if (rb->bo) {
-				radeon_bo_unref(rb->bo);
-				rb->bo = NULL;
-			}
-			rb->cpp = buffers[i].cpp;
-			rb->pitch = buffers[i].pitch;
-			rb->width = drawable->w;
-			rb->height = drawable->h;
-			rb->has_surface = 0;
-			rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
-						buffers[i].name,
-						0,
-						0,
-						RADEON_GEM_DOMAIN_VRAM,
-						buffers[i].flags);
-			if (rb->bo == NULL) {
-				fprintf(stderr, "failled to attach front %d\n",
-					buffers[i].name);
-			}
+			rb = draw->color_rb[0];
+			regname = "dri2 front buffer";
 			break;
 		case __DRI_BUFFER_BACK_LEFT:
-			rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer;
-			if (rb->bo) {
-				radeon_bo_unref(rb->bo);
-				rb->bo = NULL;
-			}
-			rb->cpp = buffers[i].cpp;
-			rb->pitch = buffers[i].pitch;
-			rb->width = drawable->w;
-			rb->height = drawable->h;
-			rb->has_surface = 0;
-			rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
-						buffers[i].name,
-						0,
-						0,
-						RADEON_GEM_DOMAIN_VRAM,
-						buffers[i].flags);
+			rb = draw->color_rb[1];
+			regname = "dri2 back buffer";
 			break;
 		case __DRI_BUFFER_DEPTH:
-			rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer;
-			if (rb->bo) {
-				radeon_bo_unref(rb->bo);
-				rb->bo = NULL;
-			}
-			rb->cpp = buffers[i].cpp;
-			rb->pitch = buffers[i].pitch;
-			rb->width = drawable->w;
-			rb->height = drawable->h;
-			rb->has_surface = 0;
-			rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
-						buffers[i].name,
-						0,
-						0,
-						RADEON_GEM_DOMAIN_VRAM,
-						buffers[i].flags);
+			rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH);
+			regname = "dri2 depth buffer";
 			break;
 		case __DRI_BUFFER_STENCIL:
+			rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH);
+			regname = "dri2 stencil buffer";
 			break;
 		case __DRI_BUFFER_ACCUM:
 		default:
@@ -502,8 +458,32 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 				buffers[i].attachment);
 			return;
 		}
+
+		if (rb == NULL)
+			continue;
+
+		if (rb->bo) {
+			radeon_bo_unref(rb->bo);
+			rb->bo = NULL;
+		}
+		rb->cpp = buffers[i].cpp;
+		rb->pitch = buffers[i].pitch;
+		rb->width = drawable->w;
+		rb->height = drawable->h;
+		rb->has_surface = 0;
+		rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+					buffers[i].name,
+					0,
+					0,
+					RADEON_GEM_DOMAIN_VRAM,
+					buffers[i].flags);
+		if (rb->bo == NULL) {
+			fprintf(stderr, "failed to attach %s %d\n",
+				regname, buffers[i].name);
+
+		}
 	}
-	radeon = (radeonContextPtr) context->driverPrivate;
+
 	driUpdateFramebufferSize(radeon->glCtx, drawable);
 }
 
@@ -534,9 +514,9 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
 		if (driDrawPriv != driReadPriv)
 			radeon_update_renderbuffers(driContextPriv, driReadPriv);
 		radeon->state.color.rrb =
-			(void *)drfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+			radeon_get_renderbuffer(&drfb->base, BUFFER_BACK_LEFT);
 		radeon->state.depth.rrb =
-			(void *)drfb->base.Attachment[BUFFER_DEPTH].Renderbuffer;
+			radeon_get_renderbuffer(&drfb->base, BUFFER_DEPTH);
 	} else {
 		radeon_make_renderbuffer_current(radeon, drfb);
 	}
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index 4aeb50fe68..e5ada622b0 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -70,6 +70,8 @@ typedef struct radeon_context *radeonContextPtr;
 #include "tnl_dd/t_dd_vertex.h"
 #undef TAG
 
+#define RADEON_RB_CLASS 0xdeadbeef
+
 struct radeon_renderbuffer
 {
 	struct gl_renderbuffer base;
diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c
index fb9e5e025e..e1bb2cd6e2 100644
--- a/src/mesa/drivers/dri/radeon/radeon_lock.c
+++ b/src/mesa/drivers/dri/radeon/radeon_lock.c
@@ -90,15 +90,6 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags)
 	rmesa->lost_context = GL_TRUE;
 }
 
-static INLINE struct radeon_renderbuffer *
-radeon_get_renderbuffer(struct gl_framebuffer *fb, int attIndex)
-{
-	if (attIndex >= 0)
-		return (struct radeon_renderbuffer *)fb->Attachment[attIndex].Renderbuffer;
-	else
-		return NULL;
-}
-
 void radeon_lock_hardware(radeonContextPtr radeon)
 {
 	__DRIdrawable *dPriv = radeon->dri.drawable;
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index e90dffd766..02101978ac 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -1197,6 +1197,7 @@ radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv)
 	return NULL;
 
     _mesa_init_renderbuffer(&ret->base, 0);
+    ret->base.ClassID = RADEON_RB_CLASS;
 
     /* XXX format junk */
     switch (format) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c
index 06771a359b..b9adab18d4 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texstate.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c
@@ -678,7 +678,7 @@ void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPri
 		radeon_bo_unref(rb->bo);
 		rb->bo = NULL;
 	}
-	rb = (void*)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+	rb = rfb->color_rb[0];
 	if (rb->bo == NULL) {
 		/* Failed to BO for the buffer */
 		return;
-- 
cgit v1.2.3


From c607a664dd005c001afda1fff1a68d41925fa86e Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Sun, 22 Mar 2009 19:11:46 +1000
Subject: radeon fbo: add draw offset calcs

---
 src/mesa/drivers/dri/r300/r300_cmdbuf.c             | 3 ++-
 src/mesa/drivers/dri/radeon/radeon_common.c         | 3 +++
 src/mesa/drivers/dri/radeon/radeon_common_context.h | 2 ++
 src/mesa/drivers/dri/radeon/radeon_fbo.c            | 9 +++++++--
 4 files changed, 14 insertions(+), 3 deletions(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_common_context.h')

diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index 2c6618fc60..d85f106c11 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -213,6 +213,7 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 	BATCH_LOCALS(&r300->radeon);
 	struct radeon_renderbuffer *rrb;
 	uint32_t cbpitch;
+	uint32_t offset = r300->radeon.state.color.draw_offset;
 
 	rrb = radeon_get_colorbuffer(&r300->radeon);
 	if (!rrb || !rrb->bo) {
@@ -231,7 +232,7 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 
 	BEGIN_BATCH_NO_AUTOSTATE(6);
 	OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
-	OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
+	OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 	OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
 	OUT_BATCH(cbpitch);
 	END_BATCH();
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c
index 4d7f91e356..4fd54c06c3 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -619,6 +619,7 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
 	radeonContextPtr radeon = RADEON_CONTEXT(ctx);
 	struct radeon_renderbuffer *rrbDepth = NULL, *rrbStencil = NULL,
 		*rrbColor = NULL;
+	uint32_t offset = 0;
        
 
 	if (!fb) {
@@ -667,6 +668,7 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
 		/* user FBO in theory */
 		struct radeon_renderbuffer *rrb;
 		rrb = (void *)fb->_ColorDrawBuffers[0];
+		offset = rrb->draw_offset;
 		rrbColor = rrb;
 		radeon->constant_cliprect = GL_TRUE;
 	}
@@ -737,6 +739,7 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
 	radeon->state.depth.rrb = rrbDepth;
 
 	radeon->state.color.rrb = rrbColor;
+	radeon->state.color.draw_offset = offset;
 
 	/* update viewport since it depends on window size */
 	if (ctx->Driver.Viewport) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index e5ada622b0..612cc97f25 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -82,6 +82,7 @@ struct radeon_renderbuffer
 	unsigned int width;
 	unsigned int height;
 
+	uint32_t draw_offset; /* FBO */
 	/* boo Xorg 6.8.2 compat */
 	int has_surface;
 
@@ -117,6 +118,7 @@ struct radeon_colorbuffer_state {
 	GLuint clear;
 	int roundEnable;
 	struct radeon_renderbuffer *rrb;
+	uint32_t draw_offset; /* offset into color renderbuffer - FBOs */
 };
 
 struct radeon_depthbuffer_state {
diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c
index a55a563340..7342f2295e 100644
--- a/src/mesa/drivers/dri/radeon/radeon_fbo.c
+++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c
@@ -377,24 +377,28 @@ radeon_update_wrapper(GLcontext *ctx, struct radeon_renderbuffer *rrb,
 		     struct gl_texture_image *texImage)
 {
    if (texImage->TexFormat == &_mesa_texformat_argb8888) {
+      rrb->cpp = 4;
       rrb->base._ActualFormat = GL_RGBA8;
       rrb->base._BaseFormat = GL_RGBA;
       rrb->base.DataType = GL_UNSIGNED_BYTE;
       DBG("Render to RGBA8 texture OK\n");
    }
    else if (texImage->TexFormat == &_mesa_texformat_rgb565) {
+      rrb->cpp = 2;
       rrb->base._ActualFormat = GL_RGB5;
       rrb->base._BaseFormat = GL_RGB;
       rrb->base.DataType = GL_UNSIGNED_SHORT;
       DBG("Render to RGB5 texture OK\n");
    }
    else if (texImage->TexFormat == &_mesa_texformat_z16) {
+      rrb->cpp = 2;
       rrb->base._ActualFormat = GL_DEPTH_COMPONENT16;
       rrb->base._BaseFormat = GL_DEPTH_COMPONENT;
       rrb->base.DataType = GL_UNSIGNED_SHORT;
       DBG("Render to DEPTH16 texture OK\n");
    }
    else if (texImage->TexFormat == &_mesa_texformat_s8_z24) {
+      rrb->cpp = 4;
       rrb->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT;
       rrb->base._BaseFormat = GL_DEPTH_STENCIL_EXT;
       rrb->base.DataType = GL_UNSIGNED_INT_24_8_EXT;
@@ -406,6 +410,7 @@ radeon_update_wrapper(GLcontext *ctx, struct radeon_renderbuffer *rrb,
       return GL_FALSE;
    }
 
+   rrb->pitch = texImage->Width * rrb->cpp;
    rrb->base.InternalFormat = rrb->base._ActualFormat;
    rrb->base.Width = texImage->Width;
    rrb->base.Height = texImage->Height;
@@ -488,7 +493,7 @@ radeon_render_texture(GLcontext * ctx,
        return;
    }
 
-   DBG("Begin render texture tid %x tex=%u w=%d h=%d refcount=%d\n",
+   fprintf(stderr,"Begin render texture tid %x tex=%u w=%d h=%d refcount=%d\n",
        _glthread_GetID(),
        att->Texture->Name, newImage->Width, newImage->Height,
        rrb->base.RefCount);
@@ -514,7 +519,7 @@ radeon_render_texture(GLcontext * ctx,
    }
 
    /* store that offset in the region */
-   //TODO   radeon_image->mt->draw_offset = imageOffset;
+   rrb->draw_offset = imageOffset;
 
    /* update drawing region, etc */
    radeon_draw_buffer(ctx, fb);
-- 
cgit v1.2.3


From 8c7e30fb950c83f5e9e29e60735e999ac608145a Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 23 Mar 2009 18:27:49 +1000
Subject: raedon/r200/r300: mega-FBO commits.

Re work depth issues.
Do a lot more FBO abstactions
fixup depth/stencil buffer interactions
---
 src/mesa/drivers/dri/r200/r200_context.c           |  10 +
 src/mesa/drivers/dri/r200/r200_context.h           |  15 --
 src/mesa/drivers/dri/r200/r200_ioctl.c             | 230 +---------------
 src/mesa/drivers/dri/r200/r200_state.c             |  31 ++-
 src/mesa/drivers/dri/r200/r200_state_init.c        |   6 -
 src/mesa/drivers/dri/r300/r300_context.c           |   9 +-
 src/mesa/drivers/dri/r300/r300_ioctl.c             | 139 ++++++----
 src/mesa/drivers/dri/r300/r300_state.c             |  31 +--
 src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h  |   5 +-
 src/mesa/drivers/dri/radeon/radeon_common.c        | 297 +++++++++++++++++++--
 src/mesa/drivers/dri/radeon/radeon_common.h        |  19 +-
 .../drivers/dri/radeon/radeon_common_context.c     |  49 +++-
 .../drivers/dri/radeon/radeon_common_context.h     |  22 +-
 src/mesa/drivers/dri/radeon/radeon_context.c       |   9 +
 src/mesa/drivers/dri/radeon/radeon_context.h       |  14 -
 src/mesa/drivers/dri/radeon/radeon_fbo.c           |  27 +-
 src/mesa/drivers/dri/radeon/radeon_ioctl.c         | 217 +--------------
 src/mesa/drivers/dri/radeon/radeon_screen.c        |  40 +--
 src/mesa/drivers/dri/radeon/radeon_span.c          |  83 +++---
 src/mesa/drivers/dri/radeon/radeon_state.c         |  31 ++-
 src/mesa/drivers/dri/radeon/radeon_state_init.c    |   6 -
 21 files changed, 605 insertions(+), 685 deletions(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_common_context.h')

diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c
index bf06c419d1..6fd0575898 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -72,6 +72,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define need_GL_EXT_blend_func_separate
 #define need_GL_NV_vertex_program
 #define need_GL_ARB_point_parameters
+#define need_GL_EXT_framebuffer_object
 #include "extension_helper.h"
 
 #define DRIVER_DATE	"20060602"
@@ -124,6 +125,7 @@ const struct dri_extension card_extensions[] =
     { "GL_EXT_blend_minmax",               GL_EXT_blend_minmax_functions },
     { "GL_EXT_blend_subtract",             NULL },
     { "GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
+    { "GL_EXT_packed_depth_stencil",	   NULL},
     { "GL_EXT_secondary_color",            GL_EXT_secondary_color_functions },
     { "GL_EXT_stencil_wrap",               NULL },
     { "GL_EXT_texture_edge_clamp",         NULL },
@@ -165,6 +167,11 @@ const struct dri_extension point_extensions[] = {
     { NULL,                                NULL }
 };
 
+const struct dri_extension mm_extensions[] = {
+  { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
+  { NULL, NULL }
+};
+
 extern const struct tnl_pipeline_stage _r200_render_stage;
 extern const struct tnl_pipeline_stage _r200_tcl_stage;
 
@@ -418,6 +425,9 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
    _math_matrix_set_identity( &rmesa->tmpmat );
 
    driInitExtensions( ctx, card_extensions, GL_TRUE );
+
+   if (rmesa->radeon.radeonScreen->kernel_mm)
+     driInitExtensions(ctx, mm_extensions, GL_FALSE);
    if (!(rmesa->radeon.radeonScreen->chip_flags & R200_CHIPSET_YCBCR_BROKEN)) {
      /* yuv textures don't work with some chips - R200 / rv280 okay so far
 	others get the bit ordering right but don't actually do YUV-RGB conversion */
diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h
index f7bad2a241..fcbe725d6f 100644
--- a/src/mesa/drivers/dri/r200/r200_context.h
+++ b/src/mesa/drivers/dri/r200/r200_context.h
@@ -621,21 +621,6 @@ struct r200_context {
    GLboolean texmicrotile;
 
   struct ati_fragment_shader *afs_loaded;
-
-  struct {
-      struct gl_fragment_program *bitmap_fp;
-      struct gl_vertex_program *passthrough_vp;
-
-      struct gl_fragment_program *saved_fp;
-      GLboolean saved_fp_enable;
-      struct gl_vertex_program *saved_vp;
-      GLboolean saved_vp_enable;
-
-      GLint saved_vp_x, saved_vp_y;
-      GLsizei saved_vp_width, saved_vp_height;
-      GLenum saved_matrix_mode;
-   } meta;
-
 };
 
 #define R200_CONTEXT(ctx)		((r200ContextPtr)(ctx->DriverCtx))
diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c
index 96ed49665b..ccb56202f6 100644
--- a/src/mesa/drivers/dri/r200/r200_ioctl.c
+++ b/src/mesa/drivers/dri/r200/r200_ioctl.c
@@ -41,19 +41,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "main/context.h"
 #include "swrast/swrast.h"
 
-#include "main/blend.h"
-#include "main/bufferobj.h"
-#include "main/buffers.h"
-#include "main/depth.h"
-#include "main/shaders.h"
-#include "main/texstate.h"
-#include "main/varray.h"
-#include "glapi/dispatch.h"
-#include "swrast/swrast.h"
-#include "main/stencil.h"
-#include "main/matrix.h"
-#include "main/attrib.h"
-#include "main/enable.h"
+
 
 #include "radeon_common.h"
 #include "radeon_lock.h"
@@ -70,217 +58,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define R200_TIMEOUT             512
 #define R200_IDLE_RETRY           16
 
-static void
-r200_meta_set_passthrough_transform(r200ContextPtr r200)
-{
-   GLcontext *ctx = r200->radeon.glCtx;
-
-   r200->meta.saved_vp_x = ctx->Viewport.X;
-   r200->meta.saved_vp_y = ctx->Viewport.Y;
-   r200->meta.saved_vp_width = ctx->Viewport.Width;
-   r200->meta.saved_vp_height = ctx->Viewport.Height;
-   r200->meta.saved_matrix_mode = ctx->Transform.MatrixMode;
-
-   _mesa_Viewport(0, 0, ctx->DrawBuffer->Width, ctx->DrawBuffer->Height);
-
-   _mesa_MatrixMode(GL_PROJECTION);
-   _mesa_PushMatrix();
-   _mesa_LoadIdentity();
-   _mesa_Ortho(0, ctx->DrawBuffer->Width, 0, ctx->DrawBuffer->Height, 1, -1);
-
-   _mesa_MatrixMode(GL_MODELVIEW);
-   _mesa_PushMatrix();
-   _mesa_LoadIdentity();
-}
-
-static void
-r200_meta_restore_transform(r200ContextPtr r200)
-{
-   _mesa_MatrixMode(GL_PROJECTION);
-   _mesa_PopMatrix();
-   _mesa_MatrixMode(GL_MODELVIEW);
-   _mesa_PopMatrix();
-
-   _mesa_MatrixMode(r200->meta.saved_matrix_mode);
-
-   _mesa_Viewport(r200->meta.saved_vp_x, r200->meta.saved_vp_y,
-		  r200->meta.saved_vp_width, r200->meta.saved_vp_height);
-}
-
-/**
- * Perform glClear where mask contains only color, depth, and/or stencil.
- *
- * The implementation is based on calling into Mesa to set GL state and
- * performing normal triangle rendering.  The intent of this path is to
- * have as generic a path as possible, so that any driver could make use of
- * it.
- */
-static void radeon_clear_tris(GLcontext *ctx, GLbitfield mask)
-{
-   r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   GLfloat vertices[4][3];
-   GLfloat color[4][4];
-   GLfloat dst_z;
-   struct gl_framebuffer *fb = ctx->DrawBuffer;
-   int i;
-   GLboolean saved_fp_enable = GL_FALSE, saved_vp_enable = GL_FALSE;
-   GLboolean saved_shader_program = 0;
-   unsigned int saved_active_texture;
-   
-   assert((mask & ~(BUFFER_BIT_BACK_LEFT | BUFFER_BIT_FRONT_LEFT |
-		    BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)) == 0);
-
-   _mesa_PushAttrib(GL_COLOR_BUFFER_BIT |
-		    GL_CURRENT_BIT |
-		    GL_DEPTH_BUFFER_BIT |
-		    GL_ENABLE_BIT |
-		    GL_STENCIL_BUFFER_BIT |
-		    GL_TRANSFORM_BIT |
-		    GL_CURRENT_BIT);
-   _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT);
-   saved_active_texture = ctx->Texture.CurrentUnit;
-  
-  /* Disable existing GL state we don't want to apply to a clear. */
-   _mesa_Disable(GL_ALPHA_TEST);
-   _mesa_Disable(GL_BLEND);
-   _mesa_Disable(GL_CULL_FACE);
-   _mesa_Disable(GL_FOG);
-   _mesa_Disable(GL_POLYGON_SMOOTH);
-   _mesa_Disable(GL_POLYGON_STIPPLE);
-   _mesa_Disable(GL_POLYGON_OFFSET_FILL);
-   _mesa_Disable(GL_LIGHTING);
-   _mesa_Disable(GL_CLIP_PLANE0);
-   _mesa_Disable(GL_CLIP_PLANE1);
-   _mesa_Disable(GL_CLIP_PLANE2);
-   _mesa_Disable(GL_CLIP_PLANE3);
-   _mesa_Disable(GL_CLIP_PLANE4);
-   _mesa_Disable(GL_CLIP_PLANE5);
-   if (ctx->Extensions.ARB_fragment_program && ctx->FragmentProgram.Enabled) {
-      saved_fp_enable = GL_TRUE;
-      _mesa_Disable(GL_FRAGMENT_PROGRAM_ARB);
-   }
-   if (ctx->Extensions.ARB_vertex_program && ctx->VertexProgram.Enabled) {
-      saved_vp_enable = GL_TRUE;
-      _mesa_Disable(GL_VERTEX_PROGRAM_ARB);
-   }
-   if (ctx->Extensions.ARB_shader_objects && ctx->Shader.CurrentProgram) {
-      saved_shader_program = ctx->Shader.CurrentProgram->Name;
-      _mesa_UseProgramObjectARB(0);
-   }
-   
-   if (ctx->Texture._EnabledUnits != 0) {
-      int i;
-      
-      for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
-	 _mesa_ActiveTextureARB(GL_TEXTURE0 + i);
-	 _mesa_Disable(GL_TEXTURE_1D);
-	 _mesa_Disable(GL_TEXTURE_2D);
-	 _mesa_Disable(GL_TEXTURE_3D);
-	 if (ctx->Extensions.ARB_texture_cube_map)
-	    _mesa_Disable(GL_TEXTURE_CUBE_MAP_ARB);
-	 if (ctx->Extensions.NV_texture_rectangle)
-	    _mesa_Disable(GL_TEXTURE_RECTANGLE_NV);
-	 if (ctx->Extensions.MESA_texture_array) {
-	    _mesa_Disable(GL_TEXTURE_1D_ARRAY_EXT);
-	    _mesa_Disable(GL_TEXTURE_2D_ARRAY_EXT);
-	 }
-      }
-   }
-  
-   r200_meta_set_passthrough_transform(rmesa);
-   
-   for (i = 0; i < 4; i++) {
-      color[i][0] = ctx->Color.ClearColor[0];
-      color[i][1] = ctx->Color.ClearColor[1];
-      color[i][2] = ctx->Color.ClearColor[2];
-      color[i][3] = ctx->Color.ClearColor[3];
-   }
-
-   /* convert clear Z from [0,1] to NDC coord in [-1,1] */
-   dst_z = -1.0 + 2.0 * ctx->Depth.Clear;
-   
-   /* Prepare the vertices, which are the same regardless of which buffer we're
-    * drawing to.
-    */
-   vertices[0][0] = fb->_Xmin;
-   vertices[0][1] = fb->_Ymin;
-   vertices[0][2] = dst_z;
-   vertices[1][0] = fb->_Xmax;
-   vertices[1][1] = fb->_Ymin;
-   vertices[1][2] = dst_z;
-   vertices[2][0] = fb->_Xmax;
-   vertices[2][1] = fb->_Ymax;
-   vertices[2][2] = dst_z;
-   vertices[3][0] = fb->_Xmin;
-   vertices[3][1] = fb->_Ymax;
-   vertices[3][2] = dst_z;
-
-   _mesa_ColorPointer(4, GL_FLOAT, 4 * sizeof(GLfloat), &color);
-   _mesa_VertexPointer(3, GL_FLOAT, 3 * sizeof(GLfloat), &vertices);
-   _mesa_Enable(GL_COLOR_ARRAY);
-   _mesa_Enable(GL_VERTEX_ARRAY);
-
-   while (mask != 0) {
-      GLuint this_mask = 0;
-
-      if (mask & BUFFER_BIT_BACK_LEFT)
-	 this_mask = BUFFER_BIT_BACK_LEFT;
-      else if (mask & BUFFER_BIT_FRONT_LEFT)
-	 this_mask = BUFFER_BIT_FRONT_LEFT;
-
-      /* Clear depth/stencil in the same pass as color. */
-      this_mask |= (mask & (BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL));
-
-      /* Select the current color buffer and use the color write mask if
-       * we have one, otherwise don't write any color channels.
-       */
-      if (this_mask & BUFFER_BIT_FRONT_LEFT)
-	 _mesa_DrawBuffer(GL_FRONT_LEFT);
-      else if (this_mask & BUFFER_BIT_BACK_LEFT)
-	 _mesa_DrawBuffer(GL_BACK_LEFT);
-      else
-	 _mesa_ColorMask(GL_FALSE, GL_FALSE, GL_FALSE, GL_FALSE);
-
-      /* Control writing of the depth clear value to depth. */
-      if (this_mask & BUFFER_BIT_DEPTH) {
-	 _mesa_DepthFunc(GL_ALWAYS);
-	 _mesa_Enable(GL_DEPTH_TEST);
-      } else {
-	 _mesa_Disable(GL_DEPTH_TEST);
-	 _mesa_DepthMask(GL_FALSE);
-      }
-
-      /* Control writing of the stencil clear value to stencil. */
-      if (this_mask & BUFFER_BIT_STENCIL) {
-	 _mesa_Enable(GL_STENCIL_TEST);
-	 _mesa_StencilOp(GL_REPLACE, GL_REPLACE, GL_REPLACE);
-	 _mesa_StencilFuncSeparate(GL_FRONT, GL_ALWAYS, ctx->Stencil.Clear,
-				   ctx->Stencil.WriteMask[0]);
-      } else {
-	 _mesa_Disable(GL_STENCIL_TEST);
-      }
-
-      CALL_DrawArrays(ctx->Exec, (GL_TRIANGLE_FAN, 0, 4));
-
-      mask &= ~this_mask;
-   }
-
-   r200_meta_restore_transform(rmesa);
-
-   _mesa_ActiveTextureARB(GL_TEXTURE0 + saved_active_texture);
-   if (saved_fp_enable)
-      _mesa_Enable(GL_FRAGMENT_PROGRAM_ARB);
-   if (saved_vp_enable)
-      _mesa_Enable(GL_VERTEX_PROGRAM_ARB);
-
-   if (saved_shader_program)
-      _mesa_UseProgramObjectARB(saved_shader_program);
-
-   _mesa_PopClientAttrib();
-   _mesa_PopAttrib();
-}
-
-
 static void r200UserClear(GLcontext *ctx, GLuint mask)
 {
    radeon_clear_tris(ctx, mask);
@@ -449,7 +226,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask )
       mask &= ~BUFFER_BIT_DEPTH;
    }
 
-   if ( (mask & BUFFER_BIT_STENCIL) && rmesa->radeon.state.stencil.hwBuffer ) {
+   if ( (mask & BUFFER_BIT_STENCIL) ) {
       flags |= RADEON_STENCIL;
       mask &= ~BUFFER_BIT_STENCIL;
    }
@@ -467,8 +244,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask )
       flags |= RADEON_USE_COMP_ZBUF;
 /*      if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
 	 flags |= RADEON_USE_HIERZ; */
-      if (!(rmesa->radeon.state.stencil.hwBuffer) ||
-	 ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&
+      if (!((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&
 	    ((rmesa->radeon.state.stencil.clear & R200_STENCIL_WRITE_MASK) == R200_STENCIL_WRITE_MASK))) {
 	  flags |= RADEON_CLEAR_FASTZ;
       }
diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c
index 74824b8d24..ca4dee8a5b 100644
--- a/src/mesa/drivers/dri/r200/r200_state.c
+++ b/src/mesa/drivers/dri/r200/r200_state.c
@@ -740,7 +740,8 @@ static void r200PolygonOffset( GLcontext *ctx,
 			       GLfloat factor, GLfloat units )
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   float_ui32_type constant =  { units * rmesa->radeon.state.depth.scale };
+   const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
+   float_ui32_type constant =  { units * depthScale };
    float_ui32_type factoru = { factor };
 
 /*    factor *= 2; */
@@ -1611,6 +1612,7 @@ void r200UpdateWindow( GLcontext *ctx )
    GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
    const GLfloat *v = ctx->Viewport._WindowMap.m;
    const GLboolean render_to_fbo = (ctx->DrawBuffer ? (ctx->DrawBuffer->Name != 0) : 0);
+   const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
    GLfloat y_scale, y_bias;
 
    if (render_to_fbo) {
@@ -1625,8 +1627,8 @@ void r200UpdateWindow( GLcontext *ctx )
    float_ui32_type tx = { v[MAT_TX] + xoffset + SUBPIXEL_X };
    float_ui32_type sy = { v[MAT_SY] * y_scale };
    float_ui32_type ty = { (v[MAT_TY] * y_scale) + y_bias + SUBPIXEL_Y };
-   float_ui32_type sz = { v[MAT_SZ] * rmesa->radeon.state.depth.scale };
-   float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale };
+   float_ui32_type sz = { v[MAT_SZ] * depthScale };
+   float_ui32_type tz = { v[MAT_TZ] * depthScale };
 
    R200_STATECHANGE( rmesa, vpt );
 
@@ -2014,15 +2016,24 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state )
       break;
 
    case GL_STENCIL_TEST:
-      if ( rmesa->radeon.state.stencil.hwBuffer ) {
-	 R200_STATECHANGE( rmesa, ctx );
-	 if ( state ) {
-	    rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |=  R200_STENCIL_ENABLE;
+      {
+	 GLboolean hw_stencil = GL_FALSE;
+	 if (ctx->DrawBuffer) {
+	    struct radeon_renderbuffer *rrbStencil
+	       = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
+	    hw_stencil = (rrbStencil && rrbStencil->bo);
+	 }
+
+	 if (hw_stencil) {
+	    R200_STATECHANGE( rmesa, ctx );
+	    if ( state ) {
+	       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |=  R200_STENCIL_ENABLE;
+	    } else {
+	       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~R200_STENCIL_ENABLE;
+	    }
 	 } else {
-	    rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~R200_STENCIL_ENABLE;
+	    FALLBACK( rmesa, R200_FALLBACK_STENCIL, state );
 	 }
-      } else {
-	 FALLBACK( rmesa, R200_FALLBACK_STENCIL, state );
       }
       break;
 
diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c
index a71f33ca3b..30326c2960 100644
--- a/src/mesa/drivers/dri/r200/r200_state_init.c
+++ b/src/mesa/drivers/dri/r200/r200_state_init.c
@@ -674,21 +674,15 @@ void r200InitState( r200ContextPtr rmesa )
    switch ( ctx->Visual.depthBits ) {
    case 16:
       rmesa->radeon.state.depth.clear = 0x0000ffff;
-      rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff;
       rmesa->radeon.state.stencil.clear = 0x00000000;
       break;
    case 24:
    default:
       rmesa->radeon.state.depth.clear = 0x00ffffff;
-      rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff;
       rmesa->radeon.state.stencil.clear = 0xffff0000;
       break;
    }
 
-   /* Only have hw stencil when depth buffer is 24 bits deep */
-   rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
-				     ctx->Visual.depthBits == 24 );
-
    rmesa->radeon.Fallback = 0;
 
    rmesa->radeon.hw.max_state_size = 0;
diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c
index cf0557d6a2..c6bd69ed14 100644
--- a/src/mesa/drivers/dri/r300/r300_context.c
+++ b/src/mesa/drivers/dri/r300/r300_context.c
@@ -113,7 +113,7 @@ const struct dri_extension card_extensions[] = {
   {"GL_EXT_blend_func_separate",	GL_EXT_blend_func_separate_functions},
   {"GL_EXT_blend_minmax",		GL_EXT_blend_minmax_functions},
   {"GL_EXT_blend_subtract",		NULL},
-   { "GL_EXT_framebuffer_object",       GL_EXT_framebuffer_object_functions },
+  {"GL_EXT_packed_depth_stencil",	NULL},
   {"GL_EXT_fog_coord",			GL_EXT_fog_coord_functions },
   {"GL_EXT_gpu_program_parameters",     GL_EXT_gpu_program_parameters_functions},
   {"GL_EXT_secondary_color", 		GL_EXT_secondary_color_functions},
@@ -141,6 +141,11 @@ const struct dri_extension card_extensions[] = {
 };
 
 
+const struct dri_extension mm_extensions[] = {
+  { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
+  { NULL, NULL }
+};
+
 /**
  * The GL 2.0 functions are needed to make display lists work with
  * functions added by GL_ATI_separate_stencil.
@@ -421,6 +426,8 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 	ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
 
 	driInitExtensions(ctx, card_extensions, GL_TRUE);
+	if (r300->radeon.radeonScreen->kernel_mm)
+	  driInitExtensions(ctx, mm_extensions, GL_FALSE);
 
 	if (driQueryOptionb
 	    (&r300->radeon.optionCache, "disable_stencil_two_side"))
diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c
index d4acbd7e99..71661eef19 100644
--- a/src/mesa/drivers/dri/r300/r300_ioctl.c
+++ b/src/mesa/drivers/dri/r300/r300_ioctl.c
@@ -66,6 +66,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define CLEARBUFFER_DEPTH	0x2
 #define CLEARBUFFER_STENCIL	0x4
 
+static void r300EmitClearState(GLcontext * ctx);
+
+static void r300UserClear(GLcontext *ctx, GLuint mask)
+{
+	radeon_clear_tris(ctx, mask);
+}
+
 static void r300ClearBuffer(r300ContextPtr r300, int flags,
 			    struct radeon_renderbuffer *rrb,
 			    struct radeon_renderbuffer *rrbd)
@@ -534,6 +541,47 @@ static void r300EmitClearState(GLcontext * ctx)
 	}
 }
 
+static void r300KernelClear(GLcontext *ctx, GLuint flags)
+{	  	
+	r300ContextPtr r300 = R300_CONTEXT(ctx);
+	__DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable;
+	struct radeon_framebuffer *rfb = dPriv->driverPrivate;
+	struct radeon_renderbuffer *rrb;
+	struct radeon_renderbuffer *rrbd;
+	int bits = 0;
+
+	/* Make sure it fits there. */
+	rcommonEnsureCmdBufSpace(&r300->radeon, 421 * 3, __FUNCTION__);
+	if (flags || bits)
+		r300EmitClearState(ctx);
+	rrbd = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
+	if (rrbd && (flags & BUFFER_BIT_DEPTH))
+		bits |= CLEARBUFFER_DEPTH;
+
+	if (flags & BUFFER_BIT_COLOR0) {
+		rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_COLOR0);
+		r300ClearBuffer(r300, CLEARBUFFER_COLOR, rrb, NULL);
+		bits = 0;
+	}
+		
+	if (flags & BUFFER_BIT_FRONT_LEFT) {
+		rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT);
+		r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
+		bits = 0;
+	}
+
+	if (flags & BUFFER_BIT_BACK_LEFT) {
+		rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT);
+		r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
+		bits = 0;
+	}
+
+	if (bits)
+		r300ClearBuffer(r300, bits, NULL, rrbd);
+
+	COMMIT_BATCH();
+}
+
 /**
  * Buffer clear
  */
@@ -541,16 +589,15 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask)
 {
 	r300ContextPtr r300 = R300_CONTEXT(ctx);
 	__DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable;
-	struct radeon_framebuffer *rfb = dPriv->driverPrivate;
-	struct radeon_renderbuffer *rrb;
-	struct radeon_renderbuffer *rrbd;
-	int flags = 0;
-	int bits = 0;
+	const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask);
+	GLbitfield swrast_mask = 0, tri_mask = 0;
+	int i;
+	struct gl_framebuffer *fb = ctx->DrawBuffer;
 
 	if (RADEON_DEBUG & DEBUG_IOCTL)
 		fprintf(stderr, "r300Clear\n");
 
-	{
+	if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 		LOCK_HARDWARE(&r300->radeon);
 		UNLOCK_HARDWARE(&r300->radeon);
 		if (dPriv->numClipRects == 0)
@@ -563,68 +610,52 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask)
 	 */
 	R300_NEWPRIM(r300);
 
-	if (mask & BUFFER_BIT_FRONT_LEFT) {
-		flags |= BUFFER_BIT_FRONT_LEFT;
-		mask &= ~BUFFER_BIT_FRONT_LEFT;
-	}
+	if (colorMask == ~0)
+	  tri_mask |= (mask & BUFFER_BITS_COLOR);
 
-	if (mask & BUFFER_BIT_BACK_LEFT) {
-		flags |= BUFFER_BIT_BACK_LEFT;
-		mask &= ~BUFFER_BIT_BACK_LEFT;
-	}
 
-	if (mask & BUFFER_BIT_DEPTH) {
-		bits |= CLEARBUFFER_DEPTH;
-		mask &= ~BUFFER_BIT_DEPTH;
+	/* HW stencil */
+	if (mask & BUFFER_BIT_STENCIL) {
+		tri_mask |= BUFFER_BIT_STENCIL;
 	}
 
-	if ((mask & BUFFER_BIT_STENCIL) && r300->radeon.state.stencil.hwBuffer) {
-		bits |= CLEARBUFFER_STENCIL;
-		mask &= ~BUFFER_BIT_STENCIL;
+	/* HW depth */
+	if (mask & BUFFER_BIT_DEPTH) {
+    	  tri_mask |= BUFFER_BIT_DEPTH;
 	}
 
-	if (mask & BUFFER_BIT_COLOR0) {
-		flags |= BUFFER_BIT_COLOR0;
-		mask &= ~BUFFER_BIT_COLOR0;
-	}
+	/* If we're doing a tri pass for depth/stencil, include a likely color
+	 * buffer with it.
+	 */
 
-	if (mask) {
-		if (RADEON_DEBUG & DEBUG_FALLBACKS)
-			fprintf(stderr, "%s: swrast clear, mask: %x\n",
-				__FUNCTION__, mask);
-		_swrast_Clear(ctx, mask);
+	for (i = 0; i < BUFFER_COUNT; i++) {
+	  GLuint bufBit = 1 << i;
+	  if ((tri_mask) & bufBit) {
+	    if (!fb->Attachment[i].Renderbuffer->ClassID) {
+	      tri_mask &= ~bufBit;
+	      swrast_mask |= bufBit;
+	    }
+	  }
 	}
 
-	/* Make sure it fits there. */
-	rcommonEnsureCmdBufSpace(&r300->radeon, 421 * 3, __FUNCTION__);
-	if (flags || bits)
-		r300EmitClearState(ctx);
-	rrbd = (void *)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer;
+	/* SW fallback clearing */
+	swrast_mask = mask & ~tri_mask;
 
-	if (flags & BUFFER_BIT_COLOR0) {
-		rrb = (void *)rfb->base.Attachment[BUFFER_COLOR0].Renderbuffer;
-		r300ClearBuffer(r300, CLEARBUFFER_COLOR, rrb, NULL);
-		bits = 0;
-	}
-		
-	if (flags & BUFFER_BIT_FRONT_LEFT) {
-		rrb = (void *)rfb->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
-		r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
-		bits = 0;
+	if (tri_mask) {
+		if (r300->radeon.radeonScreen->kernel_mm)
+			r300UserClear(ctx, tri_mask);
+		else
+			r300KernelClear(ctx, tri_mask);
 	}
-
-	if (flags & BUFFER_BIT_BACK_LEFT) {
-		rrb = (void *)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer;
-		r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
-		bits = 0;
+	if (swrast_mask) {
+		if (RADEON_DEBUG & DEBUG_FALLBACKS)
+			fprintf(stderr, "%s: swrast clear, mask: %x\n",
+				__FUNCTION__, swrast_mask);
+		_swrast_Clear(ctx, swrast_mask);
 	}
-
-	if (bits)
-		r300ClearBuffer(r300, bits, NULL, rrbd);
-
-	COMMIT_BATCH();
 }
 
+
 void r300InitIoctlFuncs(struct dd_function_table *functions)
 {
 	functions->Clear = r300Clear;
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index 02f29a0a2f..f49b43c207 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -587,8 +587,14 @@ static void r300SetDepthState(GLcontext * ctx)
 static void r300SetStencilState(GLcontext * ctx, GLboolean state)
 {
 	r300ContextPtr r300 = R300_CONTEXT(ctx);
+	GLboolean hw_stencil = GL_FALSE;
+	if (ctx->DrawBuffer) {
+		struct radeon_renderbuffer *rrbStencil
+			= radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
+		hw_stencil = (rrbStencil && rrbStencil->bo);
+	}
 
-	if (r300->radeon.state.stencil.hwBuffer) {
+	if (hw_stencil) {
 		R300_STATECHANGE(r300, zs);
 		if (state) {
 			r300->hw.zs.cmd[R300_ZS_CNTL_0] |=
@@ -933,7 +939,8 @@ static void r300UpdateWindow(GLcontext * ctx)
 	GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
 	GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
 	const GLfloat *v = ctx->Viewport._WindowMap.m;
-	const GLboolean render_to_fbo = (ctx->DrawBuffer ? (ctx->DrawBuffer->Name != 0) : 0);
+	const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
+	const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
 	GLfloat y_scale, y_bias;
 
 	if (render_to_fbo) {
@@ -948,8 +955,8 @@ static void r300UpdateWindow(GLcontext * ctx)
 	GLfloat tx = v[MAT_TX] + xoffset + SUBPIXEL_X;
 	GLfloat sy = v[MAT_SY] * y_scale;
 	GLfloat ty = (v[MAT_TY] * y_scale) + y_bias + SUBPIXEL_Y;
-	GLfloat sz = v[MAT_SZ] * rmesa->radeon.state.depth.scale;
-	GLfloat tz = v[MAT_TZ] * rmesa->radeon.state.depth.scale;
+	GLfloat sz = v[MAT_SZ] * depthScale;
+	GLfloat tz = v[MAT_TZ] * depthScale;
 
 	R300_STATECHANGE(rmesa, vpt);
 
@@ -2032,7 +2039,7 @@ static void r300ResetHwState(r300ContextPtr r300)
 		fprintf(stderr, "%s\n", __FUNCTION__);
 
 	radeon_firevertices(&r300->radeon);
-	r300UpdateWindow(ctx);
+	//r300UpdateWindow(ctx);
 
 	r300ColorMask(ctx,
 		      ctx->Color.ColorMask[RCOMP],
@@ -2207,16 +2214,6 @@ static void r300ResetHwState(r300ContextPtr r300)
 	r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000;
 	r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff;
 
-	rrb = r300->radeon.state.depth.rrb;
-	if (rrb && rrb->bo && (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)) {
-		/* XXX: Turn off when clearing buffers ? */
-		r300->hw.zb.cmd[R300_ZB_PITCH] |= R300_DEPTHMACROTILE_ENABLE;
-
-		if (ctx->Visual.depthBits == 24)
-			r300->hw.zb.cmd[R300_ZB_PITCH] |=
-			    R300_DEPTHMICROTILE_TILED;
-	}
-
 	r300->hw.zb_depthclearvalue.cmd[1] = 0;
 
 	r300->hw.zstencil_format.cmd[2] = R300_ZTOP_DISABLE;
@@ -2530,10 +2527,6 @@ void r300InitState(r300ContextPtr r300)
 	GLcontext *ctx = r300->radeon.glCtx;
 	GLuint depth_fmt;
 
-	/* Only have hw stencil when depth buffer is 24 bits deep */
-	r300->radeon.state.stencil.hwBuffer = (ctx->Visual.stencilBits > 0 &&
-					       ctx->Visual.depthBits == 24);
-
 	memset(&(r300->state.texture), 0, sizeof(r300->state.texture));
 
 	r300ResetHwState(r300);
diff --git a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h
index f80f0f7b22..42607df967 100644
--- a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h
+++ b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h
@@ -36,7 +36,10 @@ struct drm_radeon_gem_info {
 #endif
 
 
-
+uint32_t radeon_gem_bo_name(struct radeon_bo *dummy)
+{
+  return 0;
+}
 
 static inline void *radeon_bo_manager_gem_ctor(int fd)
 {
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c
index 4fd54c06c3..9f646c4386 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -58,6 +58,21 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "tnl/t_pipeline.h"
 #include "swrast_setup/swrast_setup.h"
 
+#include "main/blend.h"
+#include "main/bufferobj.h"
+#include "main/buffers.h"
+#include "main/depth.h"
+#include "main/shaders.h"
+#include "main/texstate.h"
+#include "main/varray.h"
+#include "glapi/dispatch.h"
+#include "swrast/swrast.h"
+#include "main/stencil.h"
+#include "main/matrix.h"
+#include "main/attrib.h"
+#include "main/enable.h"
+#include "main/viewport.h"
+
 #include "dri_util.h"
 #include "vblank.h"
 
@@ -658,18 +673,20 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
 		/* none */
 	if (fb->Name == 0) {
 		if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) {
-			rrbColor = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+			rrbColor = radeon_renderbuffer(fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer);
 			radeon->front_cliprects = GL_TRUE;
 		} else {
-			rrbColor = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+			rrbColor = radeon_renderbuffer(fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer);
 			radeon->front_cliprects = GL_FALSE;
 		}
 	} else {
 		/* user FBO in theory */
 		struct radeon_renderbuffer *rrb;
-		rrb = (void *)fb->_ColorDrawBuffers[0];
-		offset = rrb->draw_offset;
-		rrbColor = rrb;
+		rrb = radeon_renderbuffer(fb->_ColorDrawBuffers[0]);
+		if (rrb) {
+			offset = rrb->draw_offset;
+			rrbColor = rrb;
+		}
 		radeon->constant_cliprect = GL_TRUE;
 	}
 
@@ -679,9 +696,8 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
 		radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_FALSE);
 
 
-
 	if (fb->_DepthBuffer && fb->_DepthBuffer->Wrapped) {
-		rrbDepth = (struct radeon_renderbuffer *)fb->_DepthBuffer->Wrapped;
+		rrbDepth = radeon_renderbuffer(fb->_DepthBuffer->Wrapped);
 		if (rrbDepth && rrbDepth->bo) {
 			radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_FALSE);
 		} else {
@@ -692,16 +708,11 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
 		rrbDepth = NULL;
 	}
 
-	/* TODO stencil things */
 	if (fb->_StencilBuffer && fb->_StencilBuffer->Wrapped) {
-		rrbStencil = (struct radeon_renderbuffer *)fb->_DepthBuffer->Wrapped;
+		rrbStencil = radeon_renderbuffer(fb->_DepthBuffer->Wrapped);
 		if (rrbStencil && rrbStencil->bo) {
 			radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_FALSE);
 			/* need to re-compute stencil hw state */
-			if (ctx->Driver.Enable != NULL)
-				ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled);
-			else
-				ctx->NewState |= _NEW_STENCIL;
 			if (!rrbDepth)
 				rrbDepth = rrbStencil;
 		} else {
@@ -727,27 +738,28 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
 	 * Update depth test state
 	 */
 	if (ctx->Driver.Enable) {
-		if (ctx->Depth.Test && fb->Visual.depthBits > 0) {
-			ctx->Driver.Enable(ctx, GL_DEPTH_TEST, GL_TRUE);
-		} else {
-			ctx->Driver.Enable(ctx, GL_DEPTH_TEST, GL_FALSE);
-		}
+		ctx->Driver.Enable(ctx, GL_DEPTH_TEST,
+				   (ctx->Depth.Test && fb->Visual.depthBits > 0));
+		ctx->Driver.Enable(ctx, GL_STENCIL_TEST,
+				   (ctx->Stencil._Enabled && fb->Visual.stencilBits > 0));
 	} else {
-		ctx->NewState |= _NEW_DEPTH;
+		ctx->NewState |= (_NEW_DEPTH | _NEW_STENCIL);
 	}
 	
 	radeon->state.depth.rrb = rrbDepth;
-
 	radeon->state.color.rrb = rrbColor;
 	radeon->state.color.draw_offset = offset;
 
+#if 0
 	/* update viewport since it depends on window size */
 	if (ctx->Driver.Viewport) {
 		ctx->Driver.Viewport(ctx, ctx->Viewport.X, ctx->Viewport.Y,
 				     ctx->Viewport.Width, ctx->Viewport.Height);
 	} else {
-		ctx->NewState |= _NEW_VIEWPORT;
+	
 	}
+#endif
+	ctx->NewState |= _NEW_VIEWPORT;
 
 	/* Set state we know depends on drawable parameters:
 	 */
@@ -755,6 +767,19 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
 		ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y,
 				    ctx->Scissor.Width, ctx->Scissor.Height);
 	radeon->NewGLState |= _NEW_SCISSOR;
+
+	if (ctx->Driver.DepthRange)
+		ctx->Driver.DepthRange(ctx,
+				       ctx->Viewport.Near,
+				       ctx->Viewport.Far);
+
+	/* Update culling direction which changes depending on the
+	 * orientation of the buffer:
+	 */
+	if (ctx->Driver.FrontFace)
+		ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace);
+	else
+		ctx->NewState |= _NEW_POLYGON;
 }
 
 /**
@@ -802,10 +827,6 @@ void radeonUpdatePageFlipping(radeonContextPtr radeon)
 
 void radeon_window_moved(radeonContextPtr radeon)
 {
-	GLcontext *ctx = radeon->glCtx;
-	__DRIdrawablePrivate *dPriv = radeon->dri.drawable;
-	struct radeon_framebuffer *rfb = dPriv->driverPrivate;
-
 	if (!radeon->radeonScreen->driScreen->dri2.enabled) {
 		radeonUpdatePageFlipping(radeon);
 	}
@@ -949,8 +970,14 @@ void radeonFinish(GLcontext * ctx)
 	if (radeon->radeonScreen->kernel_mm) {
 		for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
 			struct radeon_renderbuffer *rrb;
-			rrb = (struct radeon_renderbuffer *)fb->_ColorDrawBuffers[i];
-			if (rrb->bo)
+			rrb = radeon_renderbuffer(fb->_ColorDrawBuffers[i]);
+			if (rrb && rrb->bo)
+				radeon_bo_wait(rrb->bo);
+		}
+		{
+			struct radeon_renderbuffer *rrb;
+			rrb = radeon_get_depthbuffer(radeon);
+			if (rrb && rrb->bo)
 				radeon_bo_wait(rrb->bo);
 		}
 	} else if (radeon->do_irqs) {
@@ -1108,3 +1135,219 @@ void rcommonBeginBatch(radeonContextPtr rmesa, int n,
 
 
 
+static void
+radeon_meta_set_passthrough_transform(radeonContextPtr radeon)
+{
+   GLcontext *ctx = radeon->glCtx;
+
+   radeon->meta.saved_vp_x = ctx->Viewport.X;
+   radeon->meta.saved_vp_y = ctx->Viewport.Y;
+   radeon->meta.saved_vp_width = ctx->Viewport.Width;
+   radeon->meta.saved_vp_height = ctx->Viewport.Height;
+   radeon->meta.saved_matrix_mode = ctx->Transform.MatrixMode;
+
+   _mesa_Viewport(0, 0, ctx->DrawBuffer->Width, ctx->DrawBuffer->Height);
+
+   _mesa_MatrixMode(GL_PROJECTION);
+   _mesa_PushMatrix();
+   _mesa_LoadIdentity();
+   _mesa_Ortho(0, ctx->DrawBuffer->Width, 0, ctx->DrawBuffer->Height, 1, -1);
+
+   _mesa_MatrixMode(GL_MODELVIEW);
+   _mesa_PushMatrix();
+   _mesa_LoadIdentity();
+}
+
+static void
+radeon_meta_restore_transform(radeonContextPtr radeon)
+{
+   _mesa_MatrixMode(GL_PROJECTION);
+   _mesa_PopMatrix();
+   _mesa_MatrixMode(GL_MODELVIEW);
+   _mesa_PopMatrix();
+
+   _mesa_MatrixMode(radeon->meta.saved_matrix_mode);
+
+   _mesa_Viewport(radeon->meta.saved_vp_x, radeon->meta.saved_vp_y,
+		  radeon->meta.saved_vp_width, radeon->meta.saved_vp_height);
+}
+
+
+/**
+ * Perform glClear where mask contains only color, depth, and/or stencil.
+ *
+ * The implementation is based on calling into Mesa to set GL state and
+ * performing normal triangle rendering.  The intent of this path is to
+ * have as generic a path as possible, so that any driver could make use of
+ * it.
+ */
+
+
+void radeon_clear_tris(GLcontext *ctx, GLbitfield mask)
+{
+   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+   GLfloat vertices[4][3];
+   GLfloat color[4][4];
+   GLfloat dst_z;
+   struct gl_framebuffer *fb = ctx->DrawBuffer;
+   int i;
+   GLboolean saved_fp_enable = GL_FALSE, saved_vp_enable = GL_FALSE;
+   GLboolean saved_shader_program = 0;
+   unsigned int saved_active_texture;
+
+   assert((mask & ~(TRI_CLEAR_COLOR_BITS | BUFFER_BIT_DEPTH |
+		    BUFFER_BIT_STENCIL)) == 0);   
+
+   _mesa_PushAttrib(GL_COLOR_BUFFER_BIT |
+		    GL_CURRENT_BIT |
+		    GL_DEPTH_BUFFER_BIT |
+		    GL_ENABLE_BIT |
+		    GL_STENCIL_BUFFER_BIT |
+		    GL_TRANSFORM_BIT |
+		    GL_CURRENT_BIT);
+   _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT);
+   saved_active_texture = ctx->Texture.CurrentUnit;
+  
+  /* Disable existing GL state we don't want to apply to a clear. */
+   _mesa_Disable(GL_ALPHA_TEST);
+   _mesa_Disable(GL_BLEND);
+   _mesa_Disable(GL_CULL_FACE);
+   _mesa_Disable(GL_FOG);
+   _mesa_Disable(GL_POLYGON_SMOOTH);
+   _mesa_Disable(GL_POLYGON_STIPPLE);
+   _mesa_Disable(GL_POLYGON_OFFSET_FILL);
+   _mesa_Disable(GL_LIGHTING);
+   _mesa_Disable(GL_CLIP_PLANE0);
+   _mesa_Disable(GL_CLIP_PLANE1);
+   _mesa_Disable(GL_CLIP_PLANE2);
+   _mesa_Disable(GL_CLIP_PLANE3);
+   _mesa_Disable(GL_CLIP_PLANE4);
+   _mesa_Disable(GL_CLIP_PLANE5);
+   if (ctx->Extensions.ARB_fragment_program && ctx->FragmentProgram.Enabled) {
+      saved_fp_enable = GL_TRUE;
+      _mesa_Disable(GL_FRAGMENT_PROGRAM_ARB);
+   }
+   if (ctx->Extensions.ARB_vertex_program && ctx->VertexProgram.Enabled) {
+      saved_vp_enable = GL_TRUE;
+      _mesa_Disable(GL_VERTEX_PROGRAM_ARB);
+   }
+   if (ctx->Extensions.ARB_shader_objects && ctx->Shader.CurrentProgram) {
+      saved_shader_program = ctx->Shader.CurrentProgram->Name;
+      _mesa_UseProgramObjectARB(0);
+   }
+   
+   if (ctx->Texture._EnabledUnits != 0) {
+      int i;
+      
+      for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
+	 _mesa_ActiveTextureARB(GL_TEXTURE0 + i);
+	 _mesa_Disable(GL_TEXTURE_1D);
+	 _mesa_Disable(GL_TEXTURE_2D);
+	 _mesa_Disable(GL_TEXTURE_3D);
+	 if (ctx->Extensions.ARB_texture_cube_map)
+	    _mesa_Disable(GL_TEXTURE_CUBE_MAP_ARB);
+	 if (ctx->Extensions.NV_texture_rectangle)
+	    _mesa_Disable(GL_TEXTURE_RECTANGLE_NV);
+	 if (ctx->Extensions.MESA_texture_array) {
+	    _mesa_Disable(GL_TEXTURE_1D_ARRAY_EXT);
+	    _mesa_Disable(GL_TEXTURE_2D_ARRAY_EXT);
+	 }
+      }
+   }
+  
+   radeon_meta_set_passthrough_transform(rmesa);
+   
+   for (i = 0; i < 4; i++) {
+      color[i][0] = ctx->Color.ClearColor[0];
+      color[i][1] = ctx->Color.ClearColor[1];
+      color[i][2] = ctx->Color.ClearColor[2];
+      color[i][3] = ctx->Color.ClearColor[3];
+   }
+
+   /* convert clear Z from [0,1] to NDC coord in [-1,1] */
+
+   dst_z = -1.0 + 2.0 * ctx->Depth.Clear;
+   /* Prepare the vertices, which are the same regardless of which buffer we're
+    * drawing to.
+    */
+   vertices[0][0] = fb->_Xmin;
+   vertices[0][1] = fb->_Ymin;
+   vertices[0][2] = dst_z;
+   vertices[1][0] = fb->_Xmax;
+   vertices[1][1] = fb->_Ymin;
+   vertices[1][2] = dst_z;
+   vertices[2][0] = fb->_Xmax;
+   vertices[2][1] = fb->_Ymax;
+   vertices[2][2] = dst_z;
+   vertices[3][0] = fb->_Xmin;
+   vertices[3][1] = fb->_Ymax;
+   vertices[3][2] = dst_z;
+
+   _mesa_ColorPointer(4, GL_FLOAT, 4 * sizeof(GLfloat), &color);
+   _mesa_VertexPointer(3, GL_FLOAT, 3 * sizeof(GLfloat), &vertices);
+   _mesa_Enable(GL_COLOR_ARRAY);
+   _mesa_Enable(GL_VERTEX_ARRAY);
+
+   while (mask != 0) {
+      GLuint this_mask = 0;
+      GLuint color_bit;
+
+      color_bit = _mesa_ffs(mask & TRI_CLEAR_COLOR_BITS);
+      if (color_bit != 0)
+	 this_mask |= (1 << (color_bit - 1));
+
+      /* Clear depth/stencil in the same pass as color. */
+      this_mask |= (mask & (BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL));
+
+      /* Select the current color buffer and use the color write mask if
+       * we have one, otherwise don't write any color channels.
+       */
+      if (this_mask & BUFFER_BIT_FRONT_LEFT)
+	 _mesa_DrawBuffer(GL_FRONT_LEFT);
+      else if (this_mask & BUFFER_BIT_BACK_LEFT)
+	 _mesa_DrawBuffer(GL_BACK_LEFT);
+      else if (color_bit != 0)
+	 _mesa_DrawBuffer(GL_COLOR_ATTACHMENT0 +
+			  (color_bit - BUFFER_COLOR0 - 1));
+      else
+	 _mesa_ColorMask(GL_FALSE, GL_FALSE, GL_FALSE, GL_FALSE);
+
+      /* Control writing of the depth clear value to depth. */
+      if (this_mask & BUFFER_BIT_DEPTH) {
+	 _mesa_DepthFunc(GL_ALWAYS);
+	 _mesa_DepthMask(GL_TRUE);
+	 _mesa_Enable(GL_DEPTH_TEST);
+      } else {
+	 _mesa_Disable(GL_DEPTH_TEST);
+	 _mesa_DepthMask(GL_FALSE);
+      }
+
+      /* Control writing of the stencil clear value to stencil. */
+      if (this_mask & BUFFER_BIT_STENCIL) {
+	 _mesa_Enable(GL_STENCIL_TEST);
+	 _mesa_StencilOp(GL_REPLACE, GL_REPLACE, GL_REPLACE);
+	 _mesa_StencilFuncSeparate(GL_FRONT, GL_ALWAYS, ctx->Stencil.Clear,
+				   ctx->Stencil.WriteMask[0]);
+      } else {
+	 _mesa_Disable(GL_STENCIL_TEST);
+      }
+
+      CALL_DrawArrays(ctx->Exec, (GL_TRIANGLE_FAN, 0, 4));
+
+      mask &= ~this_mask;
+   }
+
+   radeon_meta_restore_transform(rmesa);
+
+   _mesa_ActiveTextureARB(GL_TEXTURE0 + saved_active_texture);
+   if (saved_fp_enable)
+      _mesa_Enable(GL_FRAGMENT_PROGRAM_ARB);
+   if (saved_vp_enable)
+      _mesa_Enable(GL_VERTEX_PROGRAM_ARB);
+
+   if (saved_shader_program)
+      _mesa_UseProgramObjectARB(saved_shader_program);
+
+   _mesa_PopClientAttrib();
+   _mesa_PopAttrib();
+}
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h
index c97492d742..f3e2290cab 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common.h
@@ -5,6 +5,18 @@
 #include "radeon_dma.h"
 #include "radeon_texture.h"
 
+
+#define TRI_CLEAR_COLOR_BITS (BUFFER_BIT_BACK_LEFT |			\
+			      BUFFER_BIT_FRONT_LEFT |			\
+			      BUFFER_BIT_COLOR0 |			\
+			      BUFFER_BIT_COLOR1 |			\
+			      BUFFER_BIT_COLOR2 |			\
+			      BUFFER_BIT_COLOR3 |			\
+			      BUFFER_BIT_COLOR4 |			\
+			      BUFFER_BIT_COLOR5 |			\
+			      BUFFER_BIT_COLOR6 |			\
+			      BUFFER_BIT_COLOR7)
+
 void radeonRecalcScissorRects(radeonContextPtr radeon);
 void radeonSetCliprects(radeonContextPtr radeon);
 void radeonUpdateScissor( GLcontext *ctx );
@@ -24,6 +36,8 @@ void radeonFlush(GLcontext *ctx);
 void radeonFinish(GLcontext * ctx);
 void radeonEmitState(radeonContextPtr radeon);
 
+void radeon_clear_tris(GLcontext *ctx, GLbitfield mask);
+
 void radeon_window_moved(radeonContextPtr radeon);
 void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb);
 void radeonDrawBuffer( GLcontext *ctx, GLenum mode );
@@ -35,7 +49,10 @@ void radeon_get_cliprects(radeonContextPtr radeon,
 			  int *x_off, int *y_off);
 
 void radeon_fbo_init(struct radeon_context *radeon);
-struct gl_renderbuffer *
+void
+radeon_renderbuffer_set_bo(struct radeon_renderbuffer *rb,
+			   struct radeon_bo *bo);
+struct radeon_renderbuffer *
 radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv);
 static inline struct radeon_renderbuffer *radeon_renderbuffer(struct gl_renderbuffer *rb)
 {
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index a818440faf..f335eb0313 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -392,6 +392,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 	struct radeon_framebuffer *draw;
 	radeonContextPtr radeon;
 	char *regname;
+	struct radeon_bo *depth_bo, *bo;
 
 	if (RADEON_DEBUG & DEBUG_DRI)
 	    fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable);
@@ -448,7 +449,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 			regname = "dri2 depth buffer";
 			break;
 		case __DRI_BUFFER_STENCIL:
-			rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH);
+			rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL);
 			regname = "dri2 stencil buffer";
 			break;
 		case __DRI_BUFFER_ACCUM:
@@ -463,25 +464,49 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 			continue;
 
 		if (rb->bo) {
-			radeon_bo_unref(rb->bo);
-			rb->bo = NULL;
+			uint32_t name = radeon_gem_name_bo(rb->bo);
+			if (name == buffers[i].name)
+				continue;
 		}
+
+		if (RADEON_DEBUG & DEBUG_DRI)
+			fprintf(stderr,
+				"attaching buffer %s, %d, at %d, cpp %d, pitch %d\n",
+				regname, buffers[i].name, buffers[i].attachment,
+				buffers[i].cpp, buffers[i].pitch);
+
 		rb->cpp = buffers[i].cpp;
 		rb->pitch = buffers[i].pitch;
 		rb->width = drawable->w;
 		rb->height = drawable->h;
 		rb->has_surface = 0;
-		rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
-					buffers[i].name,
-					0,
-					0,
-					RADEON_GEM_DOMAIN_VRAM,
-					buffers[i].flags);
-		if (rb->bo == NULL) {
-			fprintf(stderr, "failed to attach %s %d\n",
-				regname, buffers[i].name);
 
+		if (buffers[i].attachment == __DRI_BUFFER_STENCIL && depth_bo) {
+			if (RADEON_DEBUG & DEBUG_DRI)
+				fprintf(stderr, "(reusing depth buffer as stencil)\n");
+			bo = depth_bo;
+			radeon_bo_ref(bo);
+		} else {
+			bo = radeon_bo_open(radeon->radeonScreen->bom,
+						buffers[i].name,
+						0,
+						0,
+						RADEON_GEM_DOMAIN_VRAM,
+						buffers[i].flags);
+			if (bo == NULL) {
+
+				fprintf(stderr, "failed to attach %s %d\n",
+					regname, buffers[i].name);
+				
+			}
 		}
+
+		if (buffers[i].attachment == __DRI_BUFFER_DEPTH)
+			depth_bo = bo;
+
+		radeon_renderbuffer_set_bo(rb, bo);
+		radeon_bo_unref(bo);
+		    
 	}
 
 	driUpdateFramebufferSize(radeon->glCtx, drawable);
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index 612cc97f25..0ce72c9198 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -123,7 +123,6 @@ struct radeon_colorbuffer_state {
 
 struct radeon_depthbuffer_state {
 	GLuint clear;
-	GLfloat scale;
 	struct radeon_renderbuffer *rrb;
 };
 
@@ -137,7 +136,6 @@ struct radeon_scissor_state {
 };
 
 struct radeon_stencilbuffer_state {
-	GLboolean hwBuffer;
 	GLuint clear;		/* rb3d_stencilrefmask value */
 };
 
@@ -444,9 +442,23 @@ struct radeon_context {
 
    struct radeon_cmdbuf cmdbuf;
 	
-	drm_clip_rect_t fboRect;
-	GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */
-	GLboolean front_cliprects;
+  drm_clip_rect_t fboRect;
+  GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */
+  GLboolean front_cliprects;
+
+  struct {
+      struct gl_fragment_program *bitmap_fp;
+      struct gl_vertex_program *passthrough_vp;
+
+      struct gl_fragment_program *saved_fp;
+      GLboolean saved_fp_enable;
+      struct gl_vertex_program *saved_vp;
+      GLboolean saved_vp_enable;
+
+      GLint saved_vp_x, saved_vp_y;
+      GLsizei saved_vp_width, saved_vp_height;
+      GLenum saved_matrix_mode;
+   } meta;
 
    struct {
 	   void (*get_lock)(radeonContextPtr radeon);
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c
index 3f69de8d27..ac945ecc4d 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -66,6 +66,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define need_GL_EXT_blend_minmax
 #define need_GL_EXT_fog_coord
 #define need_GL_EXT_secondary_color
+#define need_GL_EXT_framebuffer_object
 #include "extension_helper.h"
 
 #define DRIVER_DATE	"20061018"
@@ -88,6 +89,7 @@ const struct dri_extension card_extensions[] =
     { "GL_EXT_blend_logic_op",             NULL },
     { "GL_EXT_blend_subtract",             GL_EXT_blend_minmax_functions },
     { "GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
+    { "GL_EXT_packed_depth_stencil",	   NULL},
     { "GL_EXT_secondary_color",            GL_EXT_secondary_color_functions },
     { "GL_EXT_stencil_wrap",               NULL },
     { "GL_EXT_texture_edge_clamp",         NULL },
@@ -104,6 +106,11 @@ const struct dri_extension card_extensions[] =
     { NULL,                                NULL }
 };
 
+const struct dri_extension mm_extensions[] = {
+  { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
+  { NULL, NULL }
+};
+
 extern const struct tnl_pipeline_stage _radeon_render_stage;
 extern const struct tnl_pipeline_stage _radeon_tcl_stage;
 
@@ -338,6 +345,8 @@ radeonCreateContext( const __GLcontextModes *glVisual,
    }
 
    driInitExtensions( ctx, card_extensions, GL_TRUE );
+   if (rmesa->radeon.radeonScreen->kernel_mm)
+     driInitExtensions(ctx, mm_extensions, GL_FALSE);
    if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100)
       _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" );
    if (rmesa->radeon.glCtx->Mesa_DXTn) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h
index 2015e96a74..5235a6e374 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_context.h
@@ -435,20 +435,6 @@ struct r100_context {
 	GLuint c_textureBytes;
 	GLuint c_vertexBuffers;
 
-  struct {
-      struct gl_fragment_program *bitmap_fp;
-      struct gl_vertex_program *passthrough_vp;
-
-      struct gl_fragment_program *saved_fp;
-      GLboolean saved_fp_enable;
-      struct gl_vertex_program *saved_vp;
-      GLboolean saved_vp_enable;
-
-      GLint saved_vp_x, saved_vp_y;
-      GLsizei saved_vp_width, saved_vp_height;
-      GLenum saved_matrix_mode;
-   } meta;
-
 };
 
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c
index 7342f2295e..f914c8c8d0 100644
--- a/src/mesa/drivers/dri/radeon/radeon_fbo.c
+++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c
@@ -54,7 +54,6 @@ radeon_new_framebuffer(GLcontext *ctx, GLuint name)
 static void
 radeon_delete_renderbuffer(struct gl_renderbuffer *rb)
 {
-  GET_CURRENT_CONTEXT(ctx);
   struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
 
   ASSERT(rrb);
@@ -62,8 +61,6 @@ radeon_delete_renderbuffer(struct gl_renderbuffer *rb)
   if (rrb && rrb->bo) {
     radeon_bo_unref(rrb->bo);
   }
-
-
   _mesa_free(rrb);
 }
 
@@ -255,7 +252,7 @@ radeon_nop_alloc_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
    return GL_FALSE;
 }
 
-struct gl_renderbuffer *
+struct radeon_renderbuffer *
 radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv)
 {
     struct radeon_renderbuffer *rrb;
@@ -325,7 +322,7 @@ radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv)
     rrb->base.GetPointer = radeon_get_pointer;
 
     rrb->bo = NULL;
-    return &rrb->base;
+    return rrb;
 }
 
 static struct gl_renderbuffer *
@@ -383,6 +380,13 @@ radeon_update_wrapper(GLcontext *ctx, struct radeon_renderbuffer *rrb,
       rrb->base.DataType = GL_UNSIGNED_BYTE;
       DBG("Render to RGBA8 texture OK\n");
    }
+   else if (texImage->TexFormat == &_mesa_texformat_argb4444) {
+      rrb->cpp = 2;
+      rrb->base._ActualFormat = GL_RGBA4;
+      rrb->base._BaseFormat = GL_RGBA;
+      rrb->base.DataType = GL_UNSIGNED_BYTE;
+      DBG("Render to RGBA4 texture OK\n");
+   }
    else if (texImage->TexFormat == &_mesa_texformat_rgb565) {
       rrb->cpp = 2;
       rrb->base._ActualFormat = GL_RGB5;
@@ -493,7 +497,7 @@ radeon_render_texture(GLcontext * ctx,
        return;
    }
 
-   fprintf(stderr,"Begin render texture tid %x tex=%u w=%d h=%d refcount=%d\n",
+   DBG("Begin render texture tid %x tex=%u w=%d h=%d refcount=%d\n",
        _glthread_GetID(),
        att->Texture->Name, newImage->Width, newImage->Height,
        rrb->base.RefCount);
@@ -558,4 +562,13 @@ void radeon_fbo_init(struct radeon_context *radeon)
 }
 
   
-  
+void radeon_renderbuffer_set_bo(struct radeon_renderbuffer *rb,
+				struct radeon_bo *bo)
+{
+  struct radeon_bo *old;
+  old = rb->bo;
+  rb->bo = bo;
+  radeon_bo_ref(bo);
+  if (old)
+    radeon_bo_unref(old);
+}
diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
index 22584f4817..f18aa1a4da 100644
--- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
@@ -419,218 +419,6 @@ void radeonEmitAOS( r100ContextPtr rmesa,
  */
 #define RADEON_MAX_CLEARS	256
 
-
-
-static void
-r100_meta_set_passthrough_transform(r100ContextPtr r100)
-{
-   GLcontext *ctx = r100->radeon.glCtx;
-
-   r100->meta.saved_vp_x = ctx->Viewport.X;
-   r100->meta.saved_vp_y = ctx->Viewport.Y;
-   r100->meta.saved_vp_width = ctx->Viewport.Width;
-   r100->meta.saved_vp_height = ctx->Viewport.Height;
-   r100->meta.saved_matrix_mode = ctx->Transform.MatrixMode;
-
-   _mesa_Viewport(0, 0, ctx->DrawBuffer->Width, ctx->DrawBuffer->Height);
-
-   _mesa_MatrixMode(GL_PROJECTION);
-   _mesa_PushMatrix();
-   _mesa_LoadIdentity();
-   _mesa_Ortho(0, ctx->DrawBuffer->Width, 0, ctx->DrawBuffer->Height, 1, -1);
-
-   _mesa_MatrixMode(GL_MODELVIEW);
-   _mesa_PushMatrix();
-   _mesa_LoadIdentity();
-}
-
-static void
-r100_meta_restore_transform(r100ContextPtr r100)
-{
-   _mesa_MatrixMode(GL_PROJECTION);
-   _mesa_PopMatrix();
-   _mesa_MatrixMode(GL_MODELVIEW);
-   _mesa_PopMatrix();
-
-   _mesa_MatrixMode(r100->meta.saved_matrix_mode);
-
-   _mesa_Viewport(r100->meta.saved_vp_x, r100->meta.saved_vp_y,
-		  r100->meta.saved_vp_width, r100->meta.saved_vp_height);
-}
-
-/**
- * Perform glClear where mask contains only color, depth, and/or stencil.
- *
- * The implementation is based on calling into Mesa to set GL state and
- * performing normal triangle rendering.  The intent of this path is to
- * have as generic a path as possible, so that any driver could make use of
- * it.
- */
-static void radeon_clear_tris(GLcontext *ctx, GLbitfield mask)
-{
-   r100ContextPtr rmesa = R100_CONTEXT(ctx);
-   GLfloat vertices[4][3];
-   GLfloat color[4][4];
-   GLfloat dst_z;
-   struct gl_framebuffer *fb = ctx->DrawBuffer;
-   int i;
-   GLboolean saved_fp_enable = GL_FALSE, saved_vp_enable = GL_FALSE;
-   GLboolean saved_shader_program = 0;
-   unsigned int saved_active_texture;
-   
-   assert((mask & ~(BUFFER_BIT_BACK_LEFT | BUFFER_BIT_FRONT_LEFT |
-		    BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)) == 0);
-
-   _mesa_PushAttrib(GL_COLOR_BUFFER_BIT |
-		    GL_CURRENT_BIT |
-		    GL_DEPTH_BUFFER_BIT |
-		    GL_ENABLE_BIT |
-		    GL_STENCIL_BUFFER_BIT |
-		    GL_TRANSFORM_BIT |
-		    GL_CURRENT_BIT);
-   _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT);
-   saved_active_texture = ctx->Texture.CurrentUnit;
-  
-  /* Disable existing GL state we don't want to apply to a clear. */
-   _mesa_Disable(GL_ALPHA_TEST);
-   _mesa_Disable(GL_BLEND);
-   _mesa_Disable(GL_CULL_FACE);
-   _mesa_Disable(GL_FOG);
-   _mesa_Disable(GL_POLYGON_SMOOTH);
-   _mesa_Disable(GL_POLYGON_STIPPLE);
-   _mesa_Disable(GL_POLYGON_OFFSET_FILL);
-   _mesa_Disable(GL_LIGHTING);
-   _mesa_Disable(GL_CLIP_PLANE0);
-   _mesa_Disable(GL_CLIP_PLANE1);
-   _mesa_Disable(GL_CLIP_PLANE2);
-   _mesa_Disable(GL_CLIP_PLANE3);
-   _mesa_Disable(GL_CLIP_PLANE4);
-   _mesa_Disable(GL_CLIP_PLANE5);
-   if (ctx->Extensions.ARB_fragment_program && ctx->FragmentProgram.Enabled) {
-      saved_fp_enable = GL_TRUE;
-      _mesa_Disable(GL_FRAGMENT_PROGRAM_ARB);
-   }
-   if (ctx->Extensions.ARB_vertex_program && ctx->VertexProgram.Enabled) {
-      saved_vp_enable = GL_TRUE;
-      _mesa_Disable(GL_VERTEX_PROGRAM_ARB);
-   }
-   if (ctx->Extensions.ARB_shader_objects && ctx->Shader.CurrentProgram) {
-      saved_shader_program = ctx->Shader.CurrentProgram->Name;
-      _mesa_UseProgramObjectARB(0);
-   }
-   
-   if (ctx->Texture._EnabledUnits != 0) {
-      int i;
-      
-      for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
-	 _mesa_ActiveTextureARB(GL_TEXTURE0 + i);
-	 _mesa_Disable(GL_TEXTURE_1D);
-	 _mesa_Disable(GL_TEXTURE_2D);
-	 _mesa_Disable(GL_TEXTURE_3D);
-	 if (ctx->Extensions.ARB_texture_cube_map)
-	    _mesa_Disable(GL_TEXTURE_CUBE_MAP_ARB);
-	 if (ctx->Extensions.NV_texture_rectangle)
-	    _mesa_Disable(GL_TEXTURE_RECTANGLE_NV);
-	 if (ctx->Extensions.MESA_texture_array) {
-	    _mesa_Disable(GL_TEXTURE_1D_ARRAY_EXT);
-	    _mesa_Disable(GL_TEXTURE_2D_ARRAY_EXT);
-	 }
-      }
-   }
-  
-   r100_meta_set_passthrough_transform(rmesa);
-   
-   for (i = 0; i < 4; i++) {
-      color[i][0] = ctx->Color.ClearColor[0];
-      color[i][1] = ctx->Color.ClearColor[1];
-      color[i][2] = ctx->Color.ClearColor[2];
-      color[i][3] = ctx->Color.ClearColor[3];
-   }
-
-   /* convert clear Z from [0,1] to NDC coord in [-1,1] */
-   dst_z = -1.0 + 2.0 * ctx->Depth.Clear;
-   
-   /* Prepare the vertices, which are the same regardless of which buffer we're
-    * drawing to.
-    */
-   vertices[0][0] = fb->_Xmin;
-   vertices[0][1] = fb->_Ymin;
-   vertices[0][2] = dst_z;
-   vertices[1][0] = fb->_Xmax;
-   vertices[1][1] = fb->_Ymin;
-   vertices[1][2] = dst_z;
-   vertices[2][0] = fb->_Xmax;
-   vertices[2][1] = fb->_Ymax;
-   vertices[2][2] = dst_z;
-   vertices[3][0] = fb->_Xmin;
-   vertices[3][1] = fb->_Ymax;
-   vertices[3][2] = dst_z;
-
-   _mesa_ColorPointer(4, GL_FLOAT, 4 * sizeof(GLfloat), &color);
-   _mesa_VertexPointer(3, GL_FLOAT, 3 * sizeof(GLfloat), &vertices);
-   _mesa_Enable(GL_COLOR_ARRAY);
-   _mesa_Enable(GL_VERTEX_ARRAY);
-
-   while (mask != 0) {
-      GLuint this_mask = 0;
-
-      if (mask & BUFFER_BIT_BACK_LEFT)
-	 this_mask = BUFFER_BIT_BACK_LEFT;
-      else if (mask & BUFFER_BIT_FRONT_LEFT)
-	 this_mask = BUFFER_BIT_FRONT_LEFT;
-
-      /* Clear depth/stencil in the same pass as color. */
-      this_mask |= (mask & (BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL));
-
-      /* Select the current color buffer and use the color write mask if
-       * we have one, otherwise don't write any color channels.
-       */
-      if (this_mask & BUFFER_BIT_FRONT_LEFT)
-	 _mesa_DrawBuffer(GL_FRONT_LEFT);
-      else if (this_mask & BUFFER_BIT_BACK_LEFT)
-	 _mesa_DrawBuffer(GL_BACK_LEFT);
-      else
-	 _mesa_ColorMask(GL_FALSE, GL_FALSE, GL_FALSE, GL_FALSE);
-
-      /* Control writing of the depth clear value to depth. */
-      if (this_mask & BUFFER_BIT_DEPTH) {
-	 _mesa_DepthFunc(GL_ALWAYS);
-	 _mesa_Enable(GL_DEPTH_TEST);
-      } else {
-	 _mesa_Disable(GL_DEPTH_TEST);
-	 _mesa_DepthMask(GL_FALSE);
-      }
-
-      /* Control writing of the stencil clear value to stencil. */
-      if (this_mask & BUFFER_BIT_STENCIL) {
-	 _mesa_Enable(GL_STENCIL_TEST);
-	 _mesa_StencilOp(GL_REPLACE, GL_REPLACE, GL_REPLACE);
-	 _mesa_StencilFuncSeparate(GL_FRONT, GL_ALWAYS, ctx->Stencil.Clear,
-				   ctx->Stencil.WriteMask[0]);
-      } else {
-	 _mesa_Disable(GL_STENCIL_TEST);
-      }
-
-      CALL_DrawArrays(ctx->Exec, (GL_TRIANGLE_FAN, 0, 4));
-
-      mask &= ~this_mask;
-   }
-
-   r100_meta_restore_transform(rmesa);
-
-   _mesa_ActiveTextureARB(GL_TEXTURE0 + saved_active_texture);
-   if (saved_fp_enable)
-      _mesa_Enable(GL_FRAGMENT_PROGRAM_ARB);
-   if (saved_vp_enable)
-      _mesa_Enable(GL_VERTEX_PROGRAM_ARB);
-
-   if (saved_shader_program)
-      _mesa_UseProgramObjectARB(saved_shader_program);
-
-   _mesa_PopClientAttrib();
-   _mesa_PopAttrib();
-}
-
 static void radeonUserClear(GLcontext *ctx, GLuint mask)
 {
    radeon_clear_tris(ctx, mask);
@@ -795,7 +583,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask )
       mask &= ~BUFFER_BIT_DEPTH;
    }
 
-   if ( (mask & BUFFER_BIT_STENCIL) && rmesa->radeon.state.stencil.hwBuffer ) {
+   if ( (mask & BUFFER_BIT_STENCIL) ) {
       flags |= RADEON_STENCIL;
       mask &= ~BUFFER_BIT_STENCIL;
    }
@@ -813,8 +601,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask )
       flags |= RADEON_USE_COMP_ZBUF;
 /*      if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL) 
          flags |= RADEON_USE_HIERZ; */
-      if (!(rmesa->radeon.state.stencil.hwBuffer) ||
-	 ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&
+      if (((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&
 	    ((rmesa->radeon.state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) {
 	  flags |= RADEON_CLEAR_FASTZ;
       }
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index a14a0c3cb2..4725f38ae8 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -1086,6 +1086,9 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv)
    else
       screen->chip_flags |= RADEON_CLASS_R300;
 
+   if (getenv("R300_NO_TCL"))
+     screen->chip_flags &= ~RADEON_CHIPSET_TCL;
+
    i = 0;
    screen->extensions[i++] = &driCopySubBufferExtension.base;
    screen->extensions[i++] = &driFrameTrackingExtension.base;
@@ -1197,7 +1200,6 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
     const GLboolean swStencil = mesaVis->stencilBits > 0 &&
 	mesaVis->depthBits != 24;
     GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8);
-    GLenum depthFormat = GL_NONE;
     struct radeon_framebuffer *rfb;
 
     if (isPixmap)
@@ -1209,37 +1211,35 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
 
     _mesa_initialize_framebuffer(&rfb->base, mesaVis);
 
-    if (mesaVis->depthBits == 16)
-	depthFormat = GL_DEPTH_COMPONENT16;
-    else if (mesaVis->depthBits == 24)
-	depthFormat = GL_DEPTH_COMPONENT24;
-
     /* front color renderbuffer */
-    rfb->color_rb[0] = radeon_renderbuffer(radeon_create_renderbuffer(rgbFormat, driDrawPriv));
+    rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
     _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base);
     rfb->color_rb[0]->has_surface = 1;
 
     /* back color renderbuffer */
     if (mesaVis->doubleBufferMode) {
-      rfb->color_rb[1] = radeon_renderbuffer(radeon_create_renderbuffer(rgbFormat, driDrawPriv));
+      rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
 	_mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base);
 	rfb->color_rb[1]->has_surface = 1;
     }
 
-    /* depth renderbuffer */
-    if (depthFormat != GL_NONE) {
-      struct radeon_renderbuffer *depth = radeon_renderbuffer(
-							      radeon_create_renderbuffer(depthFormat, driDrawPriv));
+    if (mesaVis->depthBits == 24) {
+      if (mesaVis->stencilBits == 8) {
+	struct radeon_renderbuffer *depthStencilRb = radeon_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT, driDrawPriv);
+	_mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base);
+	_mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base);
+	depthStencilRb->has_surface = screen->depthHasSurface;
+      } else {
+	/* depth renderbuffer */
+	struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT24, driDrawPriv);
+	_mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
+	depth->has_surface = screen->depthHasSurface;
+      }
+    } else if (mesaVis->depthBits == 16) {
+      /* just 16-bit depth buffer, no hw stencil */
+	struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT16, driDrawPriv);
 	_mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
 	depth->has_surface = screen->depthHasSurface;
-    }
-
-    /* stencil renderbuffer */
-    if (mesaVis->stencilBits > 0 && !swStencil) {
-      struct radeon_renderbuffer *stencil = radeon_renderbuffer(
-								radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv));
-	_mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &stencil->base);
-	stencil->has_surface = screen->depthHasSurface;
     }
 
     _mesa_add_soft_renderbuffers(&rfb->base,
diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c
index 768a51b51d..3d2c5da4c0 100644
--- a/src/mesa/drivers/dri/radeon/radeon_span.c
+++ b/src/mesa/drivers/dri/radeon/radeon_span.c
@@ -377,33 +377,64 @@ do {									\
 #include "stenciltmp.h"
 
 
-static void map_buffer(struct gl_renderbuffer *rb, GLboolean write)
+void map_unmap_rb(struct gl_renderbuffer *rb, int flag)
 {
-	struct radeon_renderbuffer *rrb = (void*)rb;
+	struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
 	int r;
 	
-	if (rrb->bo) {
-		r = radeon_bo_map(rrb->bo, write);
+	if (rrb == NULL || !rrb->bo)
+		return;
+
+	if (flag) {
+		r = radeon_bo_map(rrb->bo, 1);
 		if (r) {
 			fprintf(stderr, "(%s) error(%d) mapping buffer.\n",
 				__FUNCTION__, r);
 		}
-	}
 
-	radeonSetSpanFunctions(rrb);
+		radeonSetSpanFunctions(rrb);
+	} else {
+		radeon_bo_unmap(rrb->bo);
+		rb->GetRow = NULL;
+		rb->PutRow = NULL;
+	}
 }
 
-static void unmap_buffer(struct gl_renderbuffer *rb)
+static void
+radeon_map_unmap_buffers(GLcontext *ctx, GLboolean map)
 {
-	struct radeon_renderbuffer *rrb = (void*)rb;
+	radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+	GLuint i, j;
 
-	if (rrb->bo) {
-		radeon_bo_unmap(rrb->bo);
+	/* color draw buffers */
+	for (j = 0; j < ctx->DrawBuffer->_NumColorDrawBuffers; j++)
+		map_unmap_rb(ctx->DrawBuffer->_ColorDrawBuffers[j], map);
+
+	/* check for render to textures */
+	for (i = 0; i < BUFFER_COUNT; i++) {
+		struct gl_renderbuffer_attachment *att =
+			ctx->DrawBuffer->Attachment + i;
+		struct gl_texture_object *tex = att->Texture;
+		if (tex) {
+			/* render to texture */
+			ASSERT(att->Renderbuffer);
+			if (map)
+				ctx->Driver.MapTexture(ctx, tex);
+			else
+				ctx->Driver.UnmapTexture(ctx, tex);
+		}
 	}
-	rb->GetRow = NULL;
-	rb->PutRow = NULL;
-}
+	
+	map_unmap_rb(ctx->ReadBuffer->_ColorReadBuffer, map);
+
+	/* depth buffer (Note wrapper!) */
+	if (ctx->DrawBuffer->_DepthBuffer)
+		map_unmap_rb(ctx->DrawBuffer->_DepthBuffer->Wrapped, map);
+	
+	if (ctx->DrawBuffer->_StencilBuffer)
+		map_unmap_rb(ctx->DrawBuffer->_StencilBuffer->Wrapped, map);
 
+}
 static void radeonSpanRenderStart(GLcontext * ctx)
 {
 	radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
@@ -416,18 +447,7 @@ static void radeonSpanRenderStart(GLcontext * ctx)
 			ctx->Driver.MapTexture(ctx, ctx->Texture.Unit[i]._Current);
 	}
 
-	/* color draw buffers */
-	for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
-		map_buffer(ctx->DrawBuffer->_ColorDrawBuffers[i], GL_TRUE);
-	}
-
-	map_buffer(ctx->ReadBuffer->_ColorReadBuffer, GL_FALSE);
-
-	if (ctx->DrawBuffer->_DepthBuffer) {
-		map_buffer(ctx->DrawBuffer->_DepthBuffer->Wrapped, GL_TRUE);
-	}
-	if (ctx->DrawBuffer->_StencilBuffer)
-		map_buffer(ctx->DrawBuffer->_StencilBuffer->Wrapped, GL_TRUE);
+	radeon_map_unmap_buffers(ctx, 1);
 
 	/* The locking and wait for idle should really only be needed in classic mode.
 	 * In a future memory manager based implementation, this should become
@@ -450,16 +470,7 @@ static void radeonSpanRenderFinish(GLcontext * ctx)
 			ctx->Driver.UnmapTexture(ctx, ctx->Texture.Unit[i]._Current);
 	}
 
-	/* color draw buffers */
-	for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++)
-		unmap_buffer(ctx->DrawBuffer->_ColorDrawBuffers[i]);
-
-	unmap_buffer(ctx->ReadBuffer->_ColorReadBuffer);
-
-	if (ctx->DrawBuffer->_DepthBuffer)
-		unmap_buffer(ctx->DrawBuffer->_DepthBuffer->Wrapped);
-	if (ctx->DrawBuffer->_StencilBuffer)
-		unmap_buffer(ctx->DrawBuffer->_StencilBuffer->Wrapped);
+	radeon_map_unmap_buffers(ctx, 0);
 }
 
 void radeonInitSpanFuncs(GLcontext * ctx)
@@ -485,6 +496,8 @@ static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb)
 		radeonInitDepthPointers_z16(&rrb->base);
 	} else if (rrb->base._ActualFormat == GL_DEPTH_COMPONENT24) {
 		radeonInitDepthPointers_z24_s8(&rrb->base);
+	} else if (rrb->base._ActualFormat == GL_DEPTH24_STENCIL8_EXT) {
+		radeonInitStencilPointers_z24_s8(&rrb->base);
 	} else if (rrb->base._ActualFormat == GL_STENCIL_INDEX8_EXT) {
 		radeonInitStencilPointers_z24_s8(&rrb->base);
 	}
diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c
index 635fe43ce4..19ff2688e6 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state.c
@@ -528,7 +528,8 @@ static void radeonPolygonOffset( GLcontext *ctx,
 				 GLfloat factor, GLfloat units )
 {
    r100ContextPtr rmesa = R100_CONTEXT(ctx);
-   float_ui32_type constant =  { units * rmesa->radeon.state.depth.scale };
+   const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
+   float_ui32_type constant =  { units * depthScale };
    float_ui32_type factoru = { factor };
 
    RADEON_STATECHANGE( rmesa, zbs );
@@ -1391,6 +1392,7 @@ void radeonUpdateWindow( GLcontext *ctx )
    GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
    const GLfloat *v = ctx->Viewport._WindowMap.m;
    const GLboolean render_to_fbo = (ctx->DrawBuffer ? (ctx->DrawBuffer->Name != 0) : 0);
+   const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
    GLfloat y_scale, y_bias;
 
    if (render_to_fbo) {
@@ -1405,8 +1407,8 @@ void radeonUpdateWindow( GLcontext *ctx )
    float_ui32_type tx = { v[MAT_TX] + xoffset + SUBPIXEL_X };
    float_ui32_type sy = { v[MAT_SY] * y_scale };
    float_ui32_type ty = { (v[MAT_TY] * y_scale) + y_bias + SUBPIXEL_Y };
-   float_ui32_type sz = { v[MAT_SZ] * rmesa->radeon.state.depth.scale };
-   float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale };
+   float_ui32_type sz = { v[MAT_SZ] * depthScale };
+   float_ui32_type tz = { v[MAT_TZ] * depthScale };
 
    RADEON_STATECHANGE( rmesa, vpt );
 
@@ -1800,15 +1802,24 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state )
       break;
 
    case GL_STENCIL_TEST:
-      if ( rmesa->radeon.state.stencil.hwBuffer ) {
-	 RADEON_STATECHANGE( rmesa, ctx );
-	 if ( state ) {
-	    rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |=  RADEON_STENCIL_ENABLE;
+      {
+	 GLboolean hw_stencil = GL_FALSE;
+	 if (ctx->DrawBuffer) {
+	    struct radeon_renderbuffer *rrbStencil
+	       = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
+	    hw_stencil = (rrbStencil && rrbStencil->bo);
+	 }
+
+	 if (hw_stencil) {
+	    RADEON_STATECHANGE( rmesa, ctx );
+	    if ( state ) {
+	       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |=  RADEON_STENCIL_ENABLE;
+	    } else {
+	       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_STENCIL_ENABLE;
+	    }
 	 } else {
-	    rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_STENCIL_ENABLE;
+	    FALLBACK( rmesa, RADEON_FALLBACK_STENCIL, state );
 	 }
-      } else {
-	 FALLBACK( rmesa, RADEON_FALLBACK_STENCIL, state );
       }
       break;
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c
index 8b6caf19d3..3d0cd8d3f8 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state_init.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c
@@ -592,22 +592,16 @@ void radeonInitState( r100ContextPtr rmesa )
    switch ( ctx->Visual.depthBits ) {
    case 16:
       rmesa->radeon.state.depth.clear = 0x0000ffff;
-      rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff;
       rmesa->radeon.state.stencil.clear = 0x00000000;
       break;
    case 24:
       rmesa->radeon.state.depth.clear = 0x00ffffff;
-      rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff;
       rmesa->radeon.state.stencil.clear = 0xffff0000;
       break;
    default:
       break;
    }
 
-   /* Only have hw stencil when depth buffer is 24 bits deep */
-   rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
-				     ctx->Visual.depthBits == 24 );
-
    rmesa->radeon.Fallback = 0;
 
 
-- 
cgit v1.2.3


From e00ef43d796f0ae0247b1072bf0aa8cdd8e3034d Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 2 Apr 2009 14:25:07 +1000
Subject: radeon/r200/r300: collapse context destruction down to a common path.

Context destruction was nearly the same over all the drivers,
so collapse it down.
---
 src/mesa/drivers/dri/r200/r200_cmdbuf.c            | 96 ++++++++++-----------
 src/mesa/drivers/dri/r200/r200_context.c           | 58 -------------
 src/mesa/drivers/dri/r200/r200_context.h           |  6 --
 src/mesa/drivers/dri/r200/r200_maos.h              |  1 -
 src/mesa/drivers/dri/r200/r200_maos_arrays.c       | 24 ++----
 src/mesa/drivers/dri/r200/r200_state.h             |  4 -
 src/mesa/drivers/dri/r200/r200_state_init.c        | 16 ----
 src/mesa/drivers/dri/r200/r200_swtcl.c             |  4 -
 src/mesa/drivers/dri/r200/r200_swtcl.h             |  1 -
 src/mesa/drivers/dri/r200/r200_tcl.c               | 16 ++--
 src/mesa/drivers/dri/r300/r300_cmdbuf.c            | 13 ---
 src/mesa/drivers/dri/r300/r300_cmdbuf.h            |  2 -
 src/mesa/drivers/dri/r300/r300_context.c           | 48 -----------
 src/mesa/drivers/dri/r300/r300_context.h           |  4 -
 src/mesa/drivers/dri/r300/r300_emit.c              | 21 +----
 src/mesa/drivers/dri/r300/r300_emit.h              |  1 -
 src/mesa/drivers/dri/r300/r300_render.c            | 98 +++++++++++-----------
 src/mesa/drivers/dri/radeon/Makefile               |  3 +-
 .../drivers/dri/radeon/radeon_common_context.c     | 90 +++++++++++++++-----
 .../drivers/dri/radeon/radeon_common_context.h     | 12 ++-
 src/mesa/drivers/dri/radeon/radeon_context.c       | 54 ++----------
 src/mesa/drivers/dri/radeon/radeon_context.h       | 24 ++----
 src/mesa/drivers/dri/radeon/radeon_dma.c           | 17 ++++
 src/mesa/drivers/dri/radeon/radeon_dma.h           |  1 +
 src/mesa/drivers/dri/radeon/radeon_ioctl.c         | 76 ++++++++---------
 src/mesa/drivers/dri/radeon/radeon_maos.h          |  1 -
 src/mesa/drivers/dri/radeon/radeon_maos_arrays.c   | 13 ---
 src/mesa/drivers/dri/radeon/radeon_maos_verts.c    | 29 ++-----
 src/mesa/drivers/dri/radeon/radeon_screen.c        | 46 +++-------
 src/mesa/drivers/dri/radeon/radeon_state.h         |  3 -
 src/mesa/drivers/dri/radeon/radeon_state_init.c    | 16 ----
 src/mesa/drivers/dri/radeon/radeon_swtcl.c         |  4 -
 src/mesa/drivers/dri/radeon/radeon_swtcl.h         |  1 -
 src/mesa/drivers/dri/radeon/radeon_tcl.c           |  8 +-
 34 files changed, 286 insertions(+), 525 deletions(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_common_context.h')

diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
index 83375c88a7..3a11a448ec 100644
--- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c
+++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
@@ -143,18 +143,18 @@ static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type)
 		if (!rmesa->radeon.radeonScreen->kernel_mm) {
 			OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
 			OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
-			OUT_BATCH_RELOC(rmesa->tcl.elt_dma_offset,
-					rmesa->tcl.elt_dma_bo,
-					rmesa->tcl.elt_dma_offset,
+			OUT_BATCH_RELOC(rmesa->radeon.tcl.elt_dma_offset,
+					rmesa->radeon.tcl.elt_dma_bo,
+					rmesa->radeon.tcl.elt_dma_offset,
 					RADEON_GEM_DOMAIN_GTT, 0, 0);
 			OUT_BATCH(vertex_count/2);
 		} else {
 			OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
 			OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
-			OUT_BATCH(rmesa->tcl.elt_dma_offset);
+			OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
 			OUT_BATCH(vertex_count/2);
 			radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
-					      rmesa->tcl.elt_dma_bo,
+					      rmesa->radeon.tcl.elt_dma_bo,
 					      RADEON_GEM_DOMAIN_GTT, 0, 0);
 		}
 		END_BATCH();
@@ -176,12 +176,12 @@ void r200FlushElts(GLcontext *ctx)
 
    nr = elt_used / 2;
 
-   radeon_bo_unmap(rmesa->tcl.elt_dma_bo);
+   radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo);
 
    r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive);
 
-   radeon_bo_unref(rmesa->tcl.elt_dma_bo);
-   rmesa->tcl.elt_dma_bo = NULL;
+   radeon_bo_unref(rmesa->radeon.tcl.elt_dma_bo);
+   rmesa->radeon.tcl.elt_dma_bo = NULL;
 
    if (R200_DEBUG & DEBUG_SYNC) {
       fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
@@ -203,14 +203,14 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
    
    radeonEmitState(&rmesa->radeon);
 
-   rmesa->tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
+   rmesa->radeon.tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
 					  0, R200_ELT_BUF_SZ, 4,
 					  RADEON_GEM_DOMAIN_GTT, 0);
-   rmesa->tcl.elt_dma_offset = 0;
+   rmesa->radeon.tcl.elt_dma_offset = 0;
    rmesa->tcl.elt_used = min_nr * 2;
 
-   radeon_bo_map(rmesa->tcl.elt_dma_bo, 1);
-   retval = rmesa->tcl.elt_dma_bo->ptr + rmesa->tcl.elt_dma_offset;
+   radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1);
+   retval = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset;
    
 
    if (R200_DEBUG & DEBUG_PRIMS)
@@ -264,79 +264,79 @@ void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset)
     
    if (!rmesa->radeon.radeonScreen->kernel_mm) {
       for (i = 0; i + 1 < nr; i += 2) {
-	 OUT_BATCH((rmesa->tcl.aos[i].components << 0) |
-		   (rmesa->tcl.aos[i].stride << 8) |
-		   (rmesa->tcl.aos[i + 1].components << 16) |
-		   (rmesa->tcl.aos[i + 1].stride << 24));
+	 OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
+		   (rmesa->radeon.tcl.aos[i].stride << 8) |
+		   (rmesa->radeon.tcl.aos[i + 1].components << 16) |
+		   (rmesa->radeon.tcl.aos[i + 1].stride << 24));
 			
-	 voffset =  rmesa->tcl.aos[i + 0].offset +
-	    offset * 4 * rmesa->tcl.aos[i + 0].stride;
+	 voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
+	    offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 	 OUT_BATCH_RELOC(voffset,
-			 rmesa->tcl.aos[i].bo,
+			 rmesa->radeon.tcl.aos[i].bo,
 			 voffset,
 			 RADEON_GEM_DOMAIN_GTT,
 			 0, 0);
-	 voffset =  rmesa->tcl.aos[i + 1].offset +
-	    offset * 4 * rmesa->tcl.aos[i + 1].stride;
+	 voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
+	    offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 	 OUT_BATCH_RELOC(voffset,
-			 rmesa->tcl.aos[i+1].bo,
+			 rmesa->radeon.tcl.aos[i+1].bo,
 			 voffset,
 			 RADEON_GEM_DOMAIN_GTT,
 			 0, 0);
       }
       
       if (nr & 1) {
-	 OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) |
-		   (rmesa->tcl.aos[nr - 1].stride << 8));
-	 voffset =  rmesa->tcl.aos[nr - 1].offset +
-	    offset * 4 * rmesa->tcl.aos[nr - 1].stride;
+	 OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
+		   (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
+	 voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
+	    offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 	 OUT_BATCH_RELOC(voffset,
-			 rmesa->tcl.aos[nr - 1].bo,
+			 rmesa->radeon.tcl.aos[nr - 1].bo,
 			 voffset,
 			 RADEON_GEM_DOMAIN_GTT,
 			 0, 0);
       }
    } else {
       for (i = 0; i + 1 < nr; i += 2) {
-	 OUT_BATCH((rmesa->tcl.aos[i].components << 0) |
-		   (rmesa->tcl.aos[i].stride << 8) |
-		   (rmesa->tcl.aos[i + 1].components << 16) |
-		   (rmesa->tcl.aos[i + 1].stride << 24));
+	 OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
+		   (rmesa->radeon.tcl.aos[i].stride << 8) |
+		   (rmesa->radeon.tcl.aos[i + 1].components << 16) |
+		   (rmesa->radeon.tcl.aos[i + 1].stride << 24));
 	 
-	 voffset =  rmesa->tcl.aos[i + 0].offset +
-	    offset * 4 * rmesa->tcl.aos[i + 0].stride;
+	 voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
+	    offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 	 OUT_BATCH(voffset);
-	 voffset =  rmesa->tcl.aos[i + 1].offset +
-	    offset * 4 * rmesa->tcl.aos[i + 1].stride;
+	 voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
+	    offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 	 OUT_BATCH(voffset);
       }
       
       if (nr & 1) {
-	 OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) |
-		   (rmesa->tcl.aos[nr - 1].stride << 8));
-	 voffset =  rmesa->tcl.aos[nr - 1].offset +
-	    offset * 4 * rmesa->tcl.aos[nr - 1].stride;
+	 OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
+		   (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
+	 voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
+	    offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 	 OUT_BATCH(voffset);
       }
       for (i = 0; i + 1 < nr; i += 2) {
-	 voffset =  rmesa->tcl.aos[i + 0].offset +
-	    offset * 4 * rmesa->tcl.aos[i + 0].stride;
+	 voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
+	    offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 	 radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
-			       rmesa->tcl.aos[i+0].bo,
+			       rmesa->radeon.tcl.aos[i+0].bo,
 			       RADEON_GEM_DOMAIN_GTT,
 			       0, 0);
-	 voffset =  rmesa->tcl.aos[i + 1].offset +
-	    offset * 4 * rmesa->tcl.aos[i + 1].stride;
+	 voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
+	    offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 	 radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
-			       rmesa->tcl.aos[i+1].bo,
+			       rmesa->radeon.tcl.aos[i+1].bo,
 			       RADEON_GEM_DOMAIN_GTT,
 			       0, 0);
       }
       if (nr & 1) {
-	 voffset =  rmesa->tcl.aos[nr - 1].offset +
-	    offset * 4 * rmesa->tcl.aos[nr - 1].stride;
+	 voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
+	    offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 	 radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
-			       rmesa->tcl.aos[nr-1].bo,
+			       rmesa->radeon.tcl.aos[nr-1].bo,
 			       RADEON_GEM_DOMAIN_GTT,
 			       0, 0);
       }
diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c
index 564e168290..f80f0d8ac7 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -491,61 +491,3 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
 }
 
 
-/* Destroy the device specific context.
- */
-/* Destroy the Mesa and driver specific context data.
- */
-void r200DestroyContext( __DRIcontextPrivate *driContextPriv )
-{
-   GET_CURRENT_CONTEXT(ctx);
-   r200ContextPtr rmesa = (r200ContextPtr) driContextPriv->driverPrivate;
-   r200ContextPtr current = ctx ? R200_CONTEXT(ctx) : NULL;
-
-   /* check if we're deleting the currently bound context */
-   if (rmesa == current) {
-      radeon_firevertices(&rmesa->radeon);
-      _mesa_make_current(NULL, NULL, NULL);
-   }
-
-   /* Free r200 context resources */
-   assert(rmesa); /* should never be null */
-   if ( rmesa ) {
-
-      _swsetup_DestroyContext( rmesa->radeon.glCtx );
-      _tnl_DestroyContext( rmesa->radeon.glCtx );
-      _vbo_DestroyContext( rmesa->radeon.glCtx );
-      _swrast_DestroyContext( rmesa->radeon.glCtx );
-
-      r200DestroySwtcl( rmesa->radeon.glCtx );
-      r200ReleaseArrays( rmesa->radeon.glCtx, ~0 );
-
-      if (rmesa->radeon.dma.current) {
-	 radeonReleaseDmaRegion( &rmesa->radeon );
-	 rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ );
-      }
-
-      if (rmesa->radeon.state.scissor.pClipRects) {
-	 FREE(rmesa->radeon.state.scissor.pClipRects);
-	 rmesa->radeon.state.scissor.pClipRects = NULL;
-      }
-
-      radeonCleanupContext(&rmesa->radeon);
-
-      FREE( rmesa );
-   }
-}
-
-
-
-/* Force the context `c' to be unbound from its buffer.
- */
-GLboolean
-r200UnbindContext( __DRIcontextPrivate *driContextPriv )
-{
-   r200ContextPtr rmesa = (r200ContextPtr) driContextPriv->driverPrivate;
-
-   if (R200_DEBUG & DEBUG_DRI)
-      fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *)rmesa->radeon.glCtx);
-
-   return GL_TRUE;
-}
diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h
index fcbe725d6f..6267293817 100644
--- a/src/mesa/drivers/dri/r200/r200_context.h
+++ b/src/mesa/drivers/dri/r200/r200_context.h
@@ -526,14 +526,8 @@ struct r200_state {
 struct r200_tcl_info {
    GLuint hw_primitive;
 
-/* hw can handle 12 components max */
-  struct radeon_aos aos[12];
-   GLuint nr_aos_components;
-
    GLuint *Elts;
 
-   struct radeon_bo *elt_dma_bo;
-   int elt_dma_offset; /** Offset into this buffer object, in bytes */
    int elt_used;
 
 };
diff --git a/src/mesa/drivers/dri/r200/r200_maos.h b/src/mesa/drivers/dri/r200/r200_maos.h
index d3ed06d402..16a70475e1 100644
--- a/src/mesa/drivers/dri/r200/r200_maos.h
+++ b/src/mesa/drivers/dri/r200/r200_maos.h
@@ -38,6 +38,5 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "r200_context.h"
 
 extern void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev );
-extern void r200ReleaseArrays( GLcontext *ctx, GLuint newinputs );
 
 #endif
diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c
index 5dbc202330..383a0c4b0d 100644
--- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c
+++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c
@@ -142,17 +142,17 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev )
 	 case 3:
 	    /* special handling to fix up fog. Will get us into trouble with vbos...*/
 	    assert(attrib == VERT_ATTRIB_FOG);
-	    if (!rmesa->tcl.aos[i].bo) {
+	    if (!rmesa->radeon.tcl.aos[i].bo) {
 	       if (ctx->VertexProgram._Enabled)
 		  rcommon_emit_vector( ctx,
-				       &(rmesa->tcl.aos[nr]),
+				       &(rmesa->radeon.tcl.aos[nr]),
 				       (char *)VB->AttribPtr[attrib]->data,
 				       1,
 				       VB->AttribPtr[attrib]->stride,
 				       count);
 	       else
 		 r200_emit_vecfog( ctx,
-				   &(rmesa->tcl.aos[nr]),
+				   &(rmesa->radeon.tcl.aos[nr]),
 				   (char *)VB->AttribPtr[attrib]->data,
 				   VB->AttribPtr[attrib]->stride,
 				   count);
@@ -199,9 +199,9 @@ void r200EmitArrays( GLcontext *ctx, GLubyte *vimap_rev )
 	 default:
 	    assert(0);
 	 }
-	 if (!rmesa->tcl.aos[nr].bo) {
+	 if (!rmesa->radeon.tcl.aos[nr].bo) {
 	   rcommon_emit_vector( ctx,
-				&(rmesa->tcl.aos[nr]),
+				&(rmesa->radeon.tcl.aos[nr]),
 				(char *)VB->AttribPtr[attrib]->data,
 				emitsize,
 				VB->AttribPtr[attrib]->stride,
@@ -220,18 +220,6 @@ after_emit:
       rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = vfmt1;
    }
 
-   rmesa->tcl.nr_aos_components = nr;
+   rmesa->radeon.tcl.aos_count = nr;
 }
 
-
-void r200ReleaseArrays( GLcontext *ctx, GLuint newinputs )
-{
-   r200ContextPtr rmesa = R200_CONTEXT( ctx );
-   int i;
-   for (i = 0; i < rmesa->tcl.nr_aos_components; i++) {
-     if (rmesa->tcl.aos[i].bo) {
-       radeon_bo_unref(rmesa->tcl.aos[i].bo);
-       rmesa->tcl.aos[i].bo = NULL;
-     }
-   }
-}
diff --git a/src/mesa/drivers/dri/r200/r200_state.h b/src/mesa/drivers/dri/r200/r200_state.h
index 1dddbfdbfe..23cf8aea66 100644
--- a/src/mesa/drivers/dri/r200/r200_state.h
+++ b/src/mesa/drivers/dri/r200/r200_state.h
@@ -49,10 +49,6 @@ extern void r200UpdateDrawBuffer(GLcontext *ctx);
 
 extern GLboolean r200ValidateState( GLcontext *ctx );
 
-extern void r200PrintDirty( r200ContextPtr rmesa,
-			      const char *msg );
-
-
 extern void r200Fallback( GLcontext *ctx, GLuint bit, GLboolean mode );
 #define FALLBACK( rmesa, bit, mode ) do {				\
    if ( 0 ) fprintf( stderr, "FALLBACK in %s: #%d=%d\n",		\
diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c
index 2400abe838..75262e46bd 100644
--- a/src/mesa/drivers/dri/r200/r200_state_init.c
+++ b/src/mesa/drivers/dri/r200/r200_state_init.c
@@ -166,22 +166,6 @@ static struct {
 /* =============================================================
  * State initialization
  */
-
-void r200PrintDirty( r200ContextPtr rmesa, const char *msg )
-{
-   struct radeon_state_atom *l;
-
-   fprintf(stderr, msg);
-   fprintf(stderr, ": ");
-
-   foreach(l, &rmesa->radeon.hw.atomlist) {
-      if (l->dirty || rmesa->radeon.hw.all_dirty)
-	 fprintf(stderr, "%s, ", l->name);
-   }
-
-   fprintf(stderr, "\n");
-}
-
 static int cmdpkt( r200ContextPtr rmesa, int id ) 
 {
    drm_radeon_cmd_header_t h;
diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c
index b006409987..712da98077 100644
--- a/src/mesa/drivers/dri/r200/r200_swtcl.c
+++ b/src/mesa/drivers/dri/r200/r200_swtcl.c
@@ -908,7 +908,3 @@ void r200InitSwtcl( GLcontext *ctx )
    rmesa->radeon.swtcl.hw_primitive = 0;
 }
 
-
-void r200DestroySwtcl( GLcontext *ctx )
-{
-}
diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.h b/src/mesa/drivers/dri/r200/r200_swtcl.h
index a4051a4b76..b0905879d7 100644
--- a/src/mesa/drivers/dri/r200/r200_swtcl.h
+++ b/src/mesa/drivers/dri/r200/r200_swtcl.h
@@ -39,7 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "r200_context.h"
 
 extern void r200InitSwtcl( GLcontext *ctx );
-extern void r200DestroySwtcl( GLcontext *ctx );
 
 extern void r200ChooseRenderState( GLcontext *ctx );
 extern void r200ChooseVertexState( GLcontext *ctx );
diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c
index 8e0fb14e70..580370933e 100644
--- a/src/mesa/drivers/dri/r200/r200_tcl.c
+++ b/src/mesa/drivers/dri/r200/r200_tcl.c
@@ -145,7 +145,7 @@ static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr )
    if (rmesa->radeon.dma.flush == r200FlushElts &&
        rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) {
 
-      GLushort *dest = (GLushort *)(rmesa->tcl.elt_dma_bo->ptr +
+      GLushort *dest = (GLushort *)(rmesa->radeon.tcl.elt_dma_bo->ptr +
 				    rmesa->tcl.elt_used);
 
       rmesa->tcl.elt_used += nr*2;
@@ -156,10 +156,10 @@ static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr )
       if (rmesa->radeon.dma.flush)
 	 rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
 
-      rcommonEnsureCmdBufSpace(&rmesa->radeon, AOS_BUFSZ(rmesa->tcl.nr_aos_components), __FUNCTION__);
+      rcommonEnsureCmdBufSpace(&rmesa->radeon, AOS_BUFSZ(rmesa->radeon.tcl.aos_count), __FUNCTION__);
 
       r200EmitAOS( rmesa,
-		   rmesa->tcl.nr_aos_components, 0 );
+		   rmesa->radeon.tcl.aos_count, 0 );
 
       return r200AllocEltsOpenEnded( rmesa, rmesa->tcl.hw_primitive, nr );
    }
@@ -186,13 +186,13 @@ static void r200EmitPrim( GLcontext *ctx,
    r200ContextPtr rmesa = R200_CONTEXT( ctx );
    r200TclPrimitive( ctx, prim, hwprim );
    
-   //   fprintf(stderr,"Emit prim %d\n", rmesa->tcl.nr_aos_components);
+   //   fprintf(stderr,"Emit prim %d\n", rmesa->radeon.tcl.aos_count);
    rcommonEnsureCmdBufSpace( &rmesa->radeon,
-			     AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
+			     AOS_BUFSZ(rmesa->radeon.tcl.aos_count) +
 			     rmesa->radeon.hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ );
 
    r200EmitAOS( rmesa,
-		rmesa->tcl.nr_aos_components,
+		rmesa->radeon.tcl.aos_count,
 		start );
    
    /* Why couldn't this packet have taken an offset param?
@@ -481,7 +481,7 @@ static GLboolean r200_run_tcl_render( GLcontext *ctx,
 
    /* Do the actual work:
     */
-   r200ReleaseArrays( ctx, ~0 /* stage->changed_inputs */ );
+   radeonReleaseArrays( ctx, ~0 /* stage->changed_inputs */ );
    r200EmitArrays( ctx, vimap_rev );
 
    rmesa->tcl.Elts = VB->Elts;
@@ -545,7 +545,7 @@ static void transition_to_swtnl( GLcontext *ctx )
    tnl->Driver.NotifyMaterialChange = 
       _mesa_validate_all_lighting_tables;
 
-   r200ReleaseArrays( ctx, ~0 );
+   radeonReleaseArrays( ctx, ~0 );
 
    /* Still using the D3D based hardware-rasterizer from the radeon;
     * need to put the card into D3D mode to make it work:
diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index fc8a2e7431..1ecbeea489 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -649,16 +649,3 @@ void r300InitCmdBuf(r300ContextPtr r300)
 
 	rcommonInitCmdBuf(&r300->radeon);
 }
-
-/**
- * Destroy the command buffer and state atoms.
- */
-void r300DestroyCmdBuf(r300ContextPtr r300)
-{
-	struct radeon_state_atom *atom;
-
-	foreach(atom, &r300->radeon.hw.atomlist) {
-		FREE(atom->cmd);
-	}
-
-}
diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h
index b7798eb97b..3786813de3 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h
@@ -39,8 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "r300_context.h"
 
 extern void r300InitCmdBuf(r300ContextPtr r300);
-extern void r300DestroyCmdBuf(r300ContextPtr r300);
-
 
 void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom);
 int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom);
diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c
index 5e271c6010..06db7ab8ff 100644
--- a/src/mesa/drivers/dri/r300/r300_context.c
+++ b/src/mesa/drivers/dri/r300/r300_context.c
@@ -470,51 +470,3 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 	return GL_TRUE;
 }
 
-/* Destroy the device specific context.
- */
-void r300DestroyContext(__DRIcontextPrivate * driContextPriv)
-{
-	GET_CURRENT_CONTEXT(ctx);
-	r300ContextPtr r300 = (r300ContextPtr) driContextPriv->driverPrivate;
-	radeonContextPtr radeon = (radeonContextPtr) r300;
-	radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL;
-
-	if (RADEON_DEBUG & DEBUG_DRI) {
-		fprintf(stderr, "Destroying context !\n");
-	}
-
-	/* check if we're deleting the currently bound context */
-	if (&r300->radeon == current) {
-		radeonFlush(r300->radeon.glCtx);
-		_mesa_make_current(NULL, NULL, NULL);
-	}
-
-	/* Free r300 context resources */
-	assert(r300);		/* should never be null */
-
-	if (r300) {
-		_swsetup_DestroyContext(r300->radeon.glCtx);
-		_tnl_DestroyContext(r300->radeon.glCtx);
-		_vbo_DestroyContext(r300->radeon.glCtx);
-		_swrast_DestroyContext(r300->radeon.glCtx);
-
-		radeon_firevertices(&r300->radeon);
-
-		if (radeon->state.scissor.pClipRects) {
-			FREE(radeon->state.scissor.pClipRects);
-			radeon->state.scissor.pClipRects = NULL;
-		}
-
-		r300DestroyCmdBuf(r300);
-
-		radeonCleanupContext(&r300->radeon);
-
-
-		/* the memory manager might be accessed when Mesa frees the shared
-		 * state, so don't destroy it earlier
-		 */
-
-
-		FREE(r300);
-	}
-}
diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h
index 37718f5415..5ef59d258e 100644
--- a/src/mesa/drivers/dri/r300/r300_context.h
+++ b/src/mesa/drivers/dri/r300/r300_context.h
@@ -633,11 +633,7 @@ struct r300_state {
 	struct r300_texture_state texture;
 	int sw_tcl_inputs[VERT_ATTRIB_MAX];
 	struct r300_vertex_shader_state vertex_shader;
-	struct radeon_aos aos[R300_MAX_AOS_ARRAYS];
-	int aos_count;
 
-	struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
-	int elt_dma_offset; /** Offset into this buffer object, in bytes */
 
 	DECLARE_RENDERINPUTS(render_inputs_bitset);	/* actual render inputs that R300 was configured for.
 							   They are the same as tnl->render_inputs for fixed pipeline */
diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c
index 4bf0e7a189..3ce0ba68c9 100644
--- a/src/mesa/drivers/dri/r300/r300_emit.c
+++ b/src/mesa/drivers/dri/r300/r300_emit.c
@@ -302,7 +302,7 @@ int r300EmitArrays(GLcontext * ctx)
 		for (ci = 0; ci < vb->AttribPtr[tab[i]]->size; ci++) {
 			swizzle[i][ci] = ci;
 		}
-		rcommon_emit_vector(ctx, &rmesa->state.aos[i],
+		rcommon_emit_vector(ctx, &rmesa->radeon.tcl.aos[i],
 				    vb->AttribPtr[tab[i]]->data,
 				    vb->AttribPtr[tab[i]]->size,
 				    vb->AttribPtr[tab[i]]->stride, count);
@@ -343,28 +343,11 @@ int r300EmitArrays(GLcontext * ctx)
 	rmesa->hw.vof.cmd[R300_VOF_CNTL_1] =
 	    r300VAPOutputCntl1(ctx, OutputsWritten);
 
-	rmesa->state.aos_count = nr;
+	rmesa->radeon.tcl.aos_count = nr;
 
 	return R300_FALLBACK_NONE;
 }
 
-void r300ReleaseArrays(GLcontext * ctx)
-{
-	r300ContextPtr rmesa = R300_CONTEXT(ctx);
-	int i;
-
-	if (rmesa->state.elt_dma_bo) {
-		radeon_bo_unref(rmesa->state.elt_dma_bo);
-		rmesa->state.elt_dma_bo = NULL;
-	}
-	for (i = 0; i < rmesa->state.aos_count; i++) {
-		if (rmesa->state.aos[i].bo) {
-			radeon_bo_unref(rmesa->state.aos[i].bo);
-			rmesa->state.aos[i].bo = NULL;
-		}
-	}
-}
-
 void r300EmitCacheFlush(r300ContextPtr rmesa)
 {
 	BATCH_LOCALS(&rmesa->radeon);
diff --git a/src/mesa/drivers/dri/r300/r300_emit.h b/src/mesa/drivers/dri/r300/r300_emit.h
index 6bc8f8e944..80c22d5e9a 100644
--- a/src/mesa/drivers/dri/r300/r300_emit.h
+++ b/src/mesa/drivers/dri/r300/r300_emit.h
@@ -218,7 +218,6 @@ void static INLINE cp_wait(radeonContextPtr radeon, unsigned char flags)
 
 extern int r300EmitArrays(GLcontext * ctx);
 
-extern void r300ReleaseArrays(GLcontext * ctx);
 extern int r300PrimitiveType(r300ContextPtr rmesa, int prim);
 extern int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim);
 
diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c
index 829d088033..924305dd12 100644
--- a/src/mesa/drivers/dri/r300/r300_render.c
+++ b/src/mesa/drivers/dri/r300/r300_render.c
@@ -175,12 +175,12 @@ static void r300EmitElts(GLcontext * ctx, void *elts, unsigned long n_elts)
 	r300ContextPtr rmesa = R300_CONTEXT(ctx);
 	void *out;
 
-	radeonAllocDmaRegion(&rmesa->radeon, &rmesa->state.elt_dma_bo,
-			     &rmesa->state.elt_dma_offset, n_elts * 4, 4);
-	radeon_bo_map(rmesa->state.elt_dma_bo, 1);
-	out = rmesa->state.elt_dma_bo->ptr + rmesa->state.elt_dma_offset;
+	radeonAllocDmaRegion(&rmesa->radeon, &rmesa->radeon.tcl.elt_dma_bo,
+			     &rmesa->radeon.tcl.elt_dma_offset, n_elts * 4, 4);
+	radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1);
+	out = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset;
 	memcpy(out, elts, n_elts * 4);
-	radeon_bo_unmap(rmesa->state.elt_dma_bo);
+	radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo);
 }
 
 static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type)
@@ -199,19 +199,19 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type)
 			OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2);
 			OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) |
 	    			 (R300_VAP_PORT_IDX0 >> 2));
-			OUT_BATCH_RELOC(rmesa->state.elt_dma_offset,
-					rmesa->state.elt_dma_bo,
-					rmesa->state.elt_dma_offset,
+			OUT_BATCH_RELOC(rmesa->radeon.tcl.elt_dma_offset,
+					rmesa->radeon.tcl.elt_dma_bo,
+					rmesa->radeon.tcl.elt_dma_offset,
 					RADEON_GEM_DOMAIN_GTT, 0, 0);
 			OUT_BATCH(vertex_count);
 		} else {
 			OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2);
 			OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) |
 	    			 (R300_VAP_PORT_IDX0 >> 2));
-			OUT_BATCH(rmesa->state.elt_dma_offset);
+			OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
 			OUT_BATCH(vertex_count);
 			radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
-					      rmesa->state.elt_dma_bo,
+					      rmesa->radeon.tcl.elt_dma_bo,
 					      RADEON_GEM_DOMAIN_GTT, 0, 0);
 		}
 		END_BATCH();
@@ -236,34 +236,34 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset)
 		OUT_BATCH(nr);
 
 		for (i = 0; i + 1 < nr; i += 2) {
-			OUT_BATCH((rmesa->state.aos[i].components << 0) |
-				  (rmesa->state.aos[i].stride << 8) |
-				  (rmesa->state.aos[i + 1].components << 16) |
-				  (rmesa->state.aos[i + 1].stride << 24));
+			OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
+				  (rmesa->radeon.tcl.aos[i].stride << 8) |
+				  (rmesa->radeon.tcl.aos[i + 1].components << 16) |
+				  (rmesa->radeon.tcl.aos[i + 1].stride << 24));
 			
-			voffset =  rmesa->state.aos[i + 0].offset +
-				offset * 4 * rmesa->state.aos[i + 0].stride;
+			voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
+				offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 			OUT_BATCH_RELOC(voffset,
-					rmesa->state.aos[i].bo,
+					rmesa->radeon.tcl.aos[i].bo,
 					voffset,
 					RADEON_GEM_DOMAIN_GTT,
 					0, 0);
-			voffset =  rmesa->state.aos[i + 1].offset +
-			  offset * 4 * rmesa->state.aos[i + 1].stride;
+			voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
+			  offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 			OUT_BATCH_RELOC(voffset,
-					rmesa->state.aos[i+1].bo,
+					rmesa->radeon.tcl.aos[i+1].bo,
 					voffset,
 					RADEON_GEM_DOMAIN_GTT,
 					0, 0);
 		}
 		
 		if (nr & 1) {
-			OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) |
-				  (rmesa->state.aos[nr - 1].stride << 8));
-			voffset =  rmesa->state.aos[nr - 1].offset +
-				offset * 4 * rmesa->state.aos[nr - 1].stride;
+			OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
+				  (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
+			voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
+				offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 			OUT_BATCH_RELOC(voffset,
-					rmesa->state.aos[nr - 1].bo,
+					rmesa->radeon.tcl.aos[nr - 1].bo,
 					voffset,
 					RADEON_GEM_DOMAIN_GTT,
 					0, 0);
@@ -276,45 +276,45 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset)
 		OUT_BATCH(nr);
 
 		for (i = 0; i + 1 < nr; i += 2) {
-			OUT_BATCH((rmesa->state.aos[i].components << 0) |
-				  (rmesa->state.aos[i].stride << 8) |
-				  (rmesa->state.aos[i + 1].components << 16) |
-				  (rmesa->state.aos[i + 1].stride << 24));
+			OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
+				  (rmesa->radeon.tcl.aos[i].stride << 8) |
+				  (rmesa->radeon.tcl.aos[i + 1].components << 16) |
+				  (rmesa->radeon.tcl.aos[i + 1].stride << 24));
 			
-			voffset =  rmesa->state.aos[i + 0].offset +
-				offset * 4 * rmesa->state.aos[i + 0].stride;
+			voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
+				offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 			OUT_BATCH(voffset);
-			voffset =  rmesa->state.aos[i + 1].offset +
-				offset * 4 * rmesa->state.aos[i + 1].stride;
+			voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
+				offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 			OUT_BATCH(voffset);
 		}
 		
 		if (nr & 1) {
-			OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) |
-			  (rmesa->state.aos[nr - 1].stride << 8));
-			voffset =  rmesa->state.aos[nr - 1].offset +
-				offset * 4 * rmesa->state.aos[nr - 1].stride;
+			OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
+			  (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
+			voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
+				offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 			OUT_BATCH(voffset);
 		}
 		for (i = 0; i + 1 < nr; i += 2) {
-			voffset =  rmesa->state.aos[i + 0].offset +
-				offset * 4 * rmesa->state.aos[i + 0].stride;
+			voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
+				offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 			radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
-					      rmesa->state.aos[i+0].bo,
+					      rmesa->radeon.tcl.aos[i+0].bo,
 					      RADEON_GEM_DOMAIN_GTT,
 					      0, 0);
-			voffset =  rmesa->state.aos[i + 1].offset +
-				offset * 4 * rmesa->state.aos[i + 1].stride;
+			voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
+				offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 			radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
-					      rmesa->state.aos[i+1].bo,
+					      rmesa->radeon.tcl.aos[i+1].bo,
 					      RADEON_GEM_DOMAIN_GTT,
 					      0, 0);
 		}
 		if (nr & 1) {
-			voffset =  rmesa->state.aos[nr - 1].offset +
-				offset * 4 * rmesa->state.aos[nr - 1].stride;
+			voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
+				offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 			radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
-					      rmesa->state.aos[nr-1].bo,
+					      rmesa->radeon.tcl.aos[nr-1].bo,
 					      RADEON_GEM_DOMAIN_GTT,
 					      0, 0);
 		}
@@ -370,10 +370,10 @@ static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx,
 		 * arrays. *sigh*
 		 */
 		r300EmitElts(ctx, vb->Elts, num_verts);
-		r300EmitAOS(rmesa, rmesa->state.aos_count, start);
+		r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start);
 		r300FireEB(rmesa, num_verts, type);
 	} else {
-		r300EmitAOS(rmesa, rmesa->state.aos_count, start);
+		r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start);
 		r300FireAOS(rmesa, num_verts, type);
 	}
 	COMMIT_BATCH();
@@ -408,7 +408,7 @@ static GLboolean r300RunRender(GLcontext * ctx,
 
 	r300EmitCacheFlush(rmesa);
 
-	r300ReleaseArrays(ctx);
+	radeonReleaseArrays(ctx, ~0);
 
 	return GL_FALSE;
 }
diff --git a/src/mesa/drivers/dri/radeon/Makefile b/src/mesa/drivers/dri/radeon/Makefile
index f469c6f43a..ba409ba813 100644
--- a/src/mesa/drivers/dri/radeon/Makefile
+++ b/src/mesa/drivers/dri/radeon/Makefile
@@ -19,7 +19,8 @@ RADEON_COMMON_SOURCES = \
 	radeon_bo_legacy.c \
 	radeon_cs_legacy.c \
 	radeon_mipmap_tree.c \
-	radeon_span.c
+	radeon_span.c \
+	radeon_fbo.c
 
 DRIVER_SOURCES = \
 	radeon_context.c \
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index 9103c8c0f6..4d61b00345 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -37,8 +37,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "utils.h"
 #include "vblank.h"
 #include "drirenderbuffer.h"
+#include "main/context.h"
 #include "main/framebuffer.h"
 #include "main/state.h"
+#include "main/simple_list.h"
+#include "swrast/swrast.h"
+#include "swrast_setup/swrast_setup.h"
+#include "tnl/tnl.h"
 
 #define DRIVER_DATE "20090101"
 
@@ -175,39 +180,81 @@ GLboolean radeonInitContext(radeonContextPtr radeon,
 	return GL_TRUE;
 }
 
+
+
+/**
+ * Destroy the command buffer and state atoms.
+ */
+static void radeon_destroy_atom_list(radeonContextPtr radeon)
+{
+	struct radeon_state_atom *atom;
+
+	foreach(atom, &radeon->hw.atomlist) {
+		FREE(atom->cmd);
+		if (atom->lastcmd)
+			FREE(atom->lastcmd);
+	}
+
+}
+
 /**
  * Cleanup common context fields.
  * Called by r200DestroyContext/r300DestroyContext
  */
-void radeonCleanupContext(radeonContextPtr radeon)
+void radeonDestroyContext(__DRIcontextPrivate *driContextPriv )
 {
 #ifdef RADEON_BO_TRACK
 	FILE *track;
 #endif
-	struct radeon_framebuffer *rfb;
-
-	radeonDestroyBuffer(radeon->dri.drawable);
-	radeonDestroyBuffer(radeon->dri.readable);
-
-	/* free the Mesa context */
-	_mesa_destroy_context(radeon->glCtx);
-
-	/* _mesa_destroy_context() might result in calls to functions that
-	 * depend on the DriverCtx, so don't set it to NULL before.
-	 *
-	 * radeon->glCtx->DriverCtx = NULL;
-	 */
-
+	GET_CURRENT_CONTEXT(ctx);
+	radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
+	radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL;
 
+	if (radeon == current) {
+		radeon_firevertices(radeon);
+		_mesa_make_current(NULL, NULL, NULL);
+	}
+	
+	assert(radeon);
+	if (radeon) {
 
-	/* free the option cache */
-	driDestroyOptionCache(&radeon->optionCache);
+		if (radeon->dma.current) {
+			radeonReleaseDmaRegion( radeon );
+			rcommonFlushCmdBuf( radeon, __FUNCTION__ );
+		}
 
-	rcommonDestroyCmdBuf(radeon);
+		radeonReleaseArrays(ctx, ~0);
 
-	if (radeon->state.scissor.pClipRects) {
-		FREE(radeon->state.scissor.pClipRects);
-		radeon->state.scissor.pClipRects = 0;
+		if (radeon->vtbl.free_context)
+			radeon->vtbl.free_context(radeon->glCtx);
+		_swsetup_DestroyContext( radeon->glCtx );
+		_tnl_DestroyContext( radeon->glCtx );
+		_vbo_DestroyContext( radeon->glCtx );
+		_swrast_DestroyContext( radeon->glCtx );
+	
+		radeonDestroyBuffer(radeon->dri.drawable);
+		radeonDestroyBuffer(radeon->dri.readable);
+
+		/* free atom list */
+		/* free the Mesa context */
+		_mesa_destroy_context(radeon->glCtx);
+		
+		/* _mesa_destroy_context() might result in calls to functions that
+		 * depend on the DriverCtx, so don't set it to NULL before.
+		 *
+		 * radeon->glCtx->DriverCtx = NULL;
+		 */
+		/* free the option cache */
+		driDestroyOptionCache(&radeon->optionCache);
+		
+		rcommonDestroyCmdBuf(radeon);
+
+		radeon_destroy_atom_list(radeon);
+
+		if (radeon->state.scissor.pClipRects) {
+			FREE(radeon->state.scissor.pClipRects);
+			radeon->state.scissor.pClipRects = 0;
+		}
 	}
 #ifdef RADEON_BO_TRACK
 	track = fopen("/tmp/tracklog", "w");
@@ -216,6 +263,7 @@ void radeonCleanupContext(radeonContextPtr radeon)
 		fclose(track);
 	}
 #endif
+	FREE(radeon);
 }
 
 /* Force the context `c' to be unbound from its buffer.
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index 0ce72c9198..c6e6be7484 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -290,6 +290,14 @@ struct radeon_swtcl_info {
 
 };
 
+#define RADEON_MAX_AOS_ARRAYS		16
+struct radeon_tcl_info {
+	struct radeon_aos aos[RADEON_MAX_AOS_ARRAYS];
+	GLuint aos_count;
+	struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
+	int elt_dma_offset; /** Offset into this buffer object, in bytes */
+};
+
 struct radeon_ioctl {
 	GLuint vertex_offset;
         struct radeon_bo *bo;
@@ -367,7 +375,6 @@ struct radeon_dri_mirror {
 #define DEBUG_MEMORY    0x4000
 
 
-
 typedef void (*radeon_tri_func) (radeonContextPtr,
 				 radeonVertex *,
 				 radeonVertex *, radeonVertex *);
@@ -436,6 +443,7 @@ struct radeon_context {
    struct radeon_state state;
 
    struct radeon_swtcl_info swtcl;
+   struct radeon_tcl_info tcl;
    /* Configuration cache
     */
    driOptionCache optionCache;
@@ -468,6 +476,7 @@ struct radeon_context {
 	   void (*pre_emit_atoms)(radeonContextPtr rmesa);
 	   void (*pre_emit_state)(radeonContextPtr rmesa);
 	   void (*fallback)(GLcontext *ctx, GLuint bit, GLboolean mode);
+	   void (*free_context)(GLcontext *ctx);
    } vtbl;
 };
 
@@ -530,6 +539,7 @@ void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
 			    __DRIdrawablePrivate * driDrawPriv,
 			    __DRIdrawablePrivate * driReadPriv);
+extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv);
 
 /* ================================================================
  * Debugging:
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c
index cad2c3e0c1..2600c78df3 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -188,6 +188,11 @@ static void r100_vtbl_pre_emit_state(radeonContextPtr radeon)
    radeon->hw.is_dirty = 1;
 }
 
+static void r100_vtbl_free_context(GLcontext *ctx)
+{
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
+   _mesa_vector4f_free( &rmesa->tcl.ObjClean );
+}
 
 static void r100_init_vtbl(radeonContextPtr radeon)
 {
@@ -202,7 +207,7 @@ static void r100_init_vtbl(radeonContextPtr radeon)
 /* Create the device specific context.
  */
 GLboolean
-radeonCreateContext( const __GLcontextModes *glVisual,
+r100CreateContext( const __GLcontextModes *glVisual,
                      __DRIcontextPrivate *driContextPriv,
                      void *sharedContextPrivate)
 {
@@ -397,50 +402,3 @@ radeonCreateContext( const __GLcontextModes *glVisual,
    }
    return GL_TRUE;
 }
-
-
-/* Destroy the device specific context.
- */
-/* Destroy the Mesa and driver specific context data.
- */
-void radeonDestroyContext( __DRIcontextPrivate *driContextPriv )
-{
-   GET_CURRENT_CONTEXT(ctx);
-   r100ContextPtr rmesa = (r100ContextPtr) driContextPriv->driverPrivate;
-   r100ContextPtr current = ctx ? R100_CONTEXT(ctx) : NULL;
-
-   /* check if we're deleting the currently bound context */
-   if (rmesa == current) {
-      radeon_firevertices(&rmesa->radeon);
-      _mesa_make_current(NULL, NULL, NULL);
-   }
-
-   /* Free radeon context resources */
-   assert(rmesa); /* should never be null */
-   if ( rmesa ) {
-
-      _swsetup_DestroyContext( rmesa->radeon.glCtx );
-      _tnl_DestroyContext( rmesa->radeon.glCtx );
-      _vbo_DestroyContext( rmesa->radeon.glCtx );
-      _swrast_DestroyContext( rmesa->radeon.glCtx );
-
-      radeonDestroySwtcl( rmesa->radeon.glCtx );
-      radeonReleaseArrays( rmesa->radeon.glCtx, ~0 );
-      if (rmesa->radeon.dma.current) {
-	 radeonReleaseDmaRegion( &rmesa->radeon );
-	 rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ );
-      }
-
-      _mesa_vector4f_free( &rmesa->tcl.ObjClean );
-
-      if (rmesa->radeon.state.scissor.pClipRects) {
-	 FREE(rmesa->radeon.state.scissor.pClipRects);
-	 rmesa->radeon.state.scissor.pClipRects = NULL;
-      }
-
-      radeonCleanupContext(&rmesa->radeon);
-
-      FREE( rmesa );
-   }
-}
-
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h
index 5235a6e374..1795d8bdb6 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_context.h
@@ -332,7 +332,7 @@ struct r100_state {
 #define R200_ELT_BUF_SZ  (8*1024)
 /* radeon_tcl.c
  */
-struct radeon_tcl_info {
+struct r100_tcl_info {
 	GLuint vertex_format;
 	GLuint hw_primitive;
 
@@ -341,14 +341,9 @@ struct radeon_tcl_info {
 	 */
 	GLvector4f ObjClean;
 
-        struct radeon_aos aos[8];
-	GLuint nr_aos_components;
-
 	GLuint *Elts;
 
-	struct radeon_bo *indexed_bo;
-
-        int elt_cmd_offset; /** Offset into the cmdbuf */
+        int elt_cmd_offset;
 	int elt_cmd_start;
         int elt_used;
 };
@@ -416,7 +411,7 @@ struct r100_context {
 
 	/* radeon_tcl.c
 	 */
-	struct radeon_tcl_info tcl;
+	struct r100_tcl_info tcl;
 
 	/* radeon_swtcl.c
 	 */
@@ -443,15 +438,10 @@ struct r100_context {
 
 #define RADEON_OLD_PACKETS 1
 
-extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv);
-extern GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
-				     __DRIcontextPrivate * driContextPriv,
-				     void *sharedContextPrivate);
-extern GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
-				   __DRIdrawablePrivate * driDrawPriv,
-				   __DRIdrawablePrivate * driReadPriv);
-extern GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv);
-
+extern GLboolean r100CreateContext( const __GLcontextModes *glVisual,
+				    __DRIcontextPrivate *driContextPriv,
+				    void *sharedContextPrivate);
+  
 
 
 #endif				/* __RADEON_CONTEXT_H__ */
diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c
index 01fc20bd79..47f789e9cd 100644
--- a/src/mesa/drivers/dri/radeon/radeon_dma.c
+++ b/src/mesa/drivers/dri/radeon/radeon_dma.c
@@ -328,3 +328,20 @@ restart:
 	rmesa->swtcl.numverts += nverts;
 	return head;
 }
+
+void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs )
+{
+   radeonContextPtr radeon = RADEON_CONTEXT( ctx );
+   int i;
+
+   if (radeon->tcl.elt_dma_bo) {
+	   radeon_bo_unref(radeon->tcl.elt_dma_bo);
+	   radeon->tcl.elt_dma_bo = NULL;
+   }
+   for (i = 0; i < radeon->tcl.aos_count; i++) {
+      if (radeon->tcl.aos[i].bo) {
+         radeon_bo_unref(radeon->tcl.aos[i].bo);
+         radeon->tcl.aos[i].bo = NULL;
+      }
+   }
+}
diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.h b/src/mesa/drivers/dri/radeon/radeon_dma.h
index cee3744fed..06e388fc1d 100644
--- a/src/mesa/drivers/dri/radeon/radeon_dma.h
+++ b/src/mesa/drivers/dri/radeon/radeon_dma.h
@@ -48,4 +48,5 @@ void radeonReleaseDmaRegion(radeonContextPtr rmesa);
 void rcommon_flush_last_swtcl_prim(GLcontext *ctx);
 
 void *rcommonAllocDmaLowVerts(radeonContextPtr rmesa, int nverts, int vsize);
+void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs );
 #endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
index f18aa1a4da..b5fde6d3de 100644
--- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
@@ -313,9 +313,9 @@ void radeonEmitAOS( r100ContextPtr rmesa,
 {
 #if RADEON_OLD_PACKETS
    assert( nr == 1 );
-   rmesa->ioctl.bo = rmesa->tcl.aos[0].bo;
+   rmesa->ioctl.bo = rmesa->radeon.tcl.aos[0].bo;
    rmesa->ioctl.vertex_offset = 
-     (rmesa->tcl.aos[0].offset + offset * rmesa->tcl.aos[0].stride * 4);
+     (rmesa->radeon.tcl.aos[0].offset + offset * rmesa->radeon.tcl.aos[0].stride * 4);
 #else
    BATCH_LOCALS(&rmesa->radeon);
    uint32_t voffset;
@@ -332,79 +332,79 @@ void radeonEmitAOS( r100ContextPtr rmesa,
 
    if (!rmesa->radeon.radeonScreen->kernel_mm) {
       for (i = 0; i + 1 < nr; i += 2) {
-	 OUT_BATCH((rmesa->tcl.aos[i].components << 0) |
-		   (rmesa->tcl.aos[i].stride << 8) |
-		   (rmesa->tcl.aos[i + 1].components << 16) |
-		   (rmesa->tcl.aos[i + 1].stride << 24));
+	 OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
+		   (rmesa->radeon.tcl.aos[i].stride << 8) |
+		   (rmesa->radeon.tcl.aos[i + 1].components << 16) |
+		   (rmesa->radeon.tcl.aos[i + 1].stride << 24));
 			
-	 voffset =  rmesa->tcl.aos[i + 0].offset +
-	    offset * 4 * rmesa->tcl.aos[i + 0].stride;
+	 voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
+	    offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 	 OUT_BATCH_RELOC(voffset,
-			 rmesa->tcl.aos[i].bo,
+			 rmesa->radeon.tcl.aos[i].bo,
 			 voffset,
 			 RADEON_GEM_DOMAIN_GTT,
 			 0, 0);
-	 voffset =  rmesa->tcl.aos[i + 1].offset +
-	    offset * 4 * rmesa->tcl.aos[i + 1].stride;
+	 voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
+	    offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 	 OUT_BATCH_RELOC(voffset,
-			 rmesa->tcl.aos[i+1].bo,
+			 rmesa->radeon.tcl.aos[i+1].bo,
 			 voffset,
 			 RADEON_GEM_DOMAIN_GTT,
 			 0, 0);
       }
       
       if (nr & 1) {
-	 OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) |
-		   (rmesa->tcl.aos[nr - 1].stride << 8));
-	 voffset =  rmesa->tcl.aos[nr - 1].offset +
-	    offset * 4 * rmesa->tcl.aos[nr - 1].stride;
+	 OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
+		   (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
+	 voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
+	    offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 	 OUT_BATCH_RELOC(voffset,
-			 rmesa->tcl.aos[nr - 1].bo,
+			 rmesa->radeon.tcl.aos[nr - 1].bo,
 			 voffset,
 			 RADEON_GEM_DOMAIN_GTT,
 			 0, 0);
       }
    } else {
       for (i = 0; i + 1 < nr; i += 2) {
-	 OUT_BATCH((rmesa->tcl.aos[i].components << 0) |
-		   (rmesa->tcl.aos[i].stride << 8) |
-		   (rmesa->tcl.aos[i + 1].components << 16) |
-		   (rmesa->tcl.aos[i + 1].stride << 24));
+	 OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
+		   (rmesa->radeon.tcl.aos[i].stride << 8) |
+		   (rmesa->radeon.tcl.aos[i + 1].components << 16) |
+		   (rmesa->radeon.tcl.aos[i + 1].stride << 24));
 	 
-	 voffset =  rmesa->tcl.aos[i + 0].offset +
-	    offset * 4 * rmesa->tcl.aos[i + 0].stride;
+	 voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
+	    offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 	 OUT_BATCH(voffset);
-	 voffset =  rmesa->tcl.aos[i + 1].offset +
-	    offset * 4 * rmesa->tcl.aos[i + 1].stride;
+	 voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
+	    offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 	 OUT_BATCH(voffset);
       }
       
       if (nr & 1) {
-	 OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) |
-		   (rmesa->tcl.aos[nr - 1].stride << 8));
-	 voffset =  rmesa->tcl.aos[nr - 1].offset +
-	    offset * 4 * rmesa->tcl.aos[nr - 1].stride;
+	 OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
+		   (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
+	 voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
+	    offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 	 OUT_BATCH(voffset);
       }
       for (i = 0; i + 1 < nr; i += 2) {
-	 voffset =  rmesa->tcl.aos[i + 0].offset +
-	    offset * 4 * rmesa->tcl.aos[i + 0].stride;
+	 voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
+	    offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 	 radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
-			       rmesa->tcl.aos[i+0].bo,
+			       rmesa->radeon.tcl.aos[i+0].bo,
 			       RADEON_GEM_DOMAIN_GTT,
 			       0, 0);
-	 voffset =  rmesa->tcl.aos[i + 1].offset +
-	    offset * 4 * rmesa->tcl.aos[i + 1].stride;
+	 voffset =  rmesa->radeon.tcl.aos[i + 1].offset +
+	    offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 	 radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
-			       rmesa->tcl.aos[i+1].bo,
+			       rmesa->radeon.tcl.aos[i+1].bo,
 			       RADEON_GEM_DOMAIN_GTT,
 			       0, 0);
       }
       if (nr & 1) {
-	 voffset =  rmesa->tcl.aos[nr - 1].offset +
-	    offset * 4 * rmesa->tcl.aos[nr - 1].stride;
+	 voffset =  rmesa->radeon.tcl.aos[nr - 1].offset +
+	    offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
 	 radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
-			       rmesa->tcl.aos[nr-1].bo,
+			       rmesa->radeon.tcl.aos[nr-1].bo,
 			       RADEON_GEM_DOMAIN_GTT,
 			       0, 0);
       }
diff --git a/src/mesa/drivers/dri/radeon/radeon_maos.h b/src/mesa/drivers/dri/radeon/radeon_maos.h
index b8935e84a0..b88eb198d5 100644
--- a/src/mesa/drivers/dri/radeon/radeon_maos.h
+++ b/src/mesa/drivers/dri/radeon/radeon_maos.h
@@ -38,6 +38,5 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "radeon_context.h"
 
 extern void radeonEmitArrays( GLcontext *ctx, GLuint inputs );
-extern void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs );
 
 #endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c
index 7f5da16b03..7c6ea0530e 100644
--- a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c
+++ b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c
@@ -324,16 +324,3 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs )
    rmesa->tcl.vertex_format = vfmt;
 }
 
-
-void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs )
-{
-   r100ContextPtr rmesa = R100_CONTEXT( ctx );
-   int i;
-
-   for (i = 0; i < rmesa->tcl.nr_aos_components; i++) {
-     if (rmesa->tcl.aos[i].bo) {
-       radeon_bo_unref(rmesa->tcl.aos[i].bo);
-       rmesa->tcl.aos[i].bo = NULL;
-     }
-   }
-}
diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c
index d468a97200..78ec119302 100644
--- a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c
+++ b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c
@@ -374,15 +374,15 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs )
 	 break;
 
    if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format &&
-       rmesa->tcl.aos[0].bo)
+       rmesa->radeon.tcl.aos[0].bo)
       return;
 
-   if (rmesa->tcl.aos[0].bo)
+   if (rmesa->radeon.tcl.aos[0].bo)
       radeonReleaseArrays( ctx, ~0 );
 
    radeonAllocDmaRegion( &rmesa->radeon,
-			 &rmesa->tcl.aos[0].bo,
-			 &rmesa->tcl.aos[0].offset,
+			 &rmesa->radeon.tcl.aos[0].bo,
+			 &rmesa->radeon.tcl.aos[0].offset,
 			 VB->Count * setup_tab[i].vertex_size * 4, 
 			 4);
 
@@ -422,25 +422,12 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs )
 
 
    setup_tab[i].emit( ctx, 0, VB->Count, 
-		      rmesa->tcl.aos[0].bo->ptr + rmesa->tcl.aos[0].offset);
+		      rmesa->radeon.tcl.aos[0].bo->ptr + rmesa->radeon.tcl.aos[0].offset);
 
-   //   rmesa->tcl.aos[0].size = setup_tab[i].vertex_size;
-   rmesa->tcl.aos[0].stride = setup_tab[i].vertex_size;
+   //   rmesa->radeon.tcl.aos[0].size = setup_tab[i].vertex_size;
+   rmesa->radeon.tcl.aos[0].stride = setup_tab[i].vertex_size;
    rmesa->tcl.vertex_format = setup_tab[i].vertex_format;
-   rmesa->tcl.nr_aos_components = 1;
+   rmesa->radeon.tcl.aos_count = 1;
 }
 
 
-
-void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs )
-{
-   r100ContextPtr rmesa = R100_CONTEXT( ctx );
-   int i;
-
-   for (i = 0; i < rmesa->tcl.nr_aos_components; i++) {
-      if (rmesa->tcl.aos[i].bo) {
-         radeon_bo_unref(rmesa->tcl.aos[i].bo);
-         rmesa->tcl.aos[i].bo = NULL;
-      }
-   }
-}
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index ea400a672d..ecfdce9d01 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -1332,7 +1332,6 @@ radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
     _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL);
 }
 
-#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
 /**
  * Choose the appropriate CreateContext function based on the chipset.
  * Eventually, all drivers will go through this process.
@@ -1343,25 +1342,21 @@ static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
 {
 	__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
 	radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
-
+#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
 	if (IS_R300_CLASS(screen))
 		return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
-        return GL_FALSE;
-}
-
-/**
- * Choose the appropriate DestroyContext function based on the chipset.
- */
-static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
-{
-	radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
-
-	if (IS_R300_CLASS(radeon->radeonScreen))
-		return r300DestroyContext(driContextPriv);
-}
+#endif
 
+#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
+	if (IS_R200_CLASS(screen))
+		return r200CreateContext(glVisual, driContextPriv, sharedContextPriv);
+#endif
 
+#if !RADEON_COMMON
+	return r100CreateContext(glVisual, driContextPriv, sharedContextPriv);
 #endif
+	return GL_FALSE;
+}
 
 
 /**
@@ -1547,7 +1542,6 @@ getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
    return 0;
 }
 
-#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
 const struct __DriverAPIRec driDriverAPI = {
    .InitScreen      = radeonInitScreen,
    .DestroyScreen   = radeonDestroyScreen,
@@ -1567,24 +1561,4 @@ const struct __DriverAPIRec driDriverAPI = {
     /* DRI2 */
    .InitScreen2     = radeonInitScreen2,
 };
-#else
-const struct __DriverAPIRec driDriverAPI = {
-   .InitScreen      = radeonInitScreen,
-   .DestroyScreen   = radeonDestroyScreen,
-   .CreateContext   = r200CreateContext,
-   .DestroyContext  = r200DestroyContext,
-   .CreateBuffer    = radeonCreateBuffer,
-   .DestroyBuffer   = radeonDestroyBuffer,
-   .SwapBuffers     = radeonSwapBuffers,
-   .MakeCurrent     = radeonMakeCurrent,
-   .UnbindContext   = radeonUnbindContext,
-   .GetSwapInfo     = getSwapInfo,
-   .GetDrawableMSC  = driDrawableGetMSC32,
-   .WaitForMSC      = driWaitForMSC32,
-   .WaitForSBC      = NULL,
-   .SwapBuffersMSC  = NULL,
-   .CopySubBuffer   = radeonCopySubBuffer,
-   .InitScreen2     = radeonInitScreen2,
-};
-#endif
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_state.h b/src/mesa/drivers/dri/radeon/radeon_state.h
index 17c2b11222..f05fa827d7 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state.h
+++ b/src/mesa/drivers/dri/radeon/radeon_state.h
@@ -52,9 +52,6 @@ extern void radeonUploadTexMatrix( r100ContextPtr rmesa,
 
 extern void radeonValidateState( GLcontext *ctx );
 
-extern void radeonPrintDirty( r100ContextPtr rmesa,
-			      const char *msg );
-
 
 extern void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode );
 #define FALLBACK( rmesa, bit, mode ) do {				\
diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c
index 3d0cd8d3f8..174a7e1862 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state_init.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c
@@ -161,22 +161,6 @@ static struct {
 /* =============================================================
  * State initialization
  */
-
-void radeonPrintDirty( r100ContextPtr rmesa, const char *msg )
-{
-   struct radeon_state_atom *l;
-
-   fprintf(stderr, msg);
-   fprintf(stderr, ": ");
-
-   foreach(l, &rmesa->radeon.hw.atomlist) {
-      if (l->dirty || rmesa->radeon.hw.all_dirty)
-	 fprintf(stderr, "%s, ", l->name);
-   }
-
-   fprintf(stderr, "\n");
-}
-
 static int cmdpkt( r100ContextPtr rmesa, int id ) 
 {
    drm_radeon_cmd_header_t h;
diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c b/src/mesa/drivers/dri/radeon/radeon_swtcl.c
index 2484006f1c..e31f045991 100644
--- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c
@@ -822,7 +822,3 @@ void radeonInitSwtcl( GLcontext *ctx )
    rmesa->radeon.swtcl.hw_primitive = 0;
 }
 
-
-void radeonDestroySwtcl( GLcontext *ctx )
-{
-}
diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.h b/src/mesa/drivers/dri/radeon/radeon_swtcl.h
index 3ada9890b3..da89158eeb 100644
--- a/src/mesa/drivers/dri/radeon/radeon_swtcl.h
+++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.h
@@ -40,7 +40,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "radeon_context.h"
 
 extern void radeonInitSwtcl( GLcontext *ctx );
-extern void radeonDestroySwtcl( GLcontext *ctx );
 
 extern void radeonChooseRenderState( GLcontext *ctx );
 extern void radeonChooseVertexState( GLcontext *ctx );
diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.c b/src/mesa/drivers/dri/radeon/radeon_tcl.c
index 5887ab355d..df6708f05e 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tcl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_tcl.c
@@ -150,10 +150,10 @@ static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr )
 	 rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
 
       rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->radeon.hw.max_state_size + ELTS_BUFSZ(nr) + 
-			       AOS_BUFSZ(rmesa->tcl.nr_aos_components), __FUNCTION__);
+			       AOS_BUFSZ(rmesa->radeon.tcl.aos_count), __FUNCTION__);
 
       radeonEmitAOS( rmesa,
-		     rmesa->tcl.nr_aos_components, 0 );
+		     rmesa->radeon.tcl.aos_count, 0 );
 
       return radeonAllocEltsOpenEnded( rmesa, rmesa->tcl.vertex_format,
 				       rmesa->tcl.hw_primitive, nr );
@@ -177,11 +177,11 @@ static void radeonEmitPrim( GLcontext *ctx,
    radeonTclPrimitive( ctx, prim, hwprim );
    
    rcommonEnsureCmdBufSpace( &rmesa->radeon,
-			     AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
+			     AOS_BUFSZ(rmesa->radeon.tcl.aos_count) +
 			     rmesa->radeon.hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ );
 
    radeonEmitAOS( rmesa,
-		  rmesa->tcl.nr_aos_components,
+		  rmesa->radeon.tcl.aos_count,
 		  start );
    
    /* Why couldn't this packet have taken an offset param?
-- 
cgit v1.2.3


From 05304d41f2d9ab7a66a8b976580c156b7b93a9d3 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 2 Apr 2009 18:58:49 +1000
Subject: radeon/r200/r300: fix up the whole buffer space checking.

This fixes up the buffer validation scheme, so that we keep a list
of buffers to validate so cmdbuf flushes during a pipeline get
all the buffers revalidated on the next emit.

This also fixes radeonFlush to not flush unless we have something
useful to send to the GPU, like a DMA buffer or something not state
---
 src/mesa/drivers/dri/r200/r200_state.c             | 48 ++++++-------------
 src/mesa/drivers/dri/r300/r300_emit.c              |  2 +-
 src/mesa/drivers/dri/r300/r300_texstate.c          | 46 +++++-------------
 src/mesa/drivers/dri/radeon/radeon_common.c        | 56 ++++++++++++++++++++++
 src/mesa/drivers/dri/radeon/radeon_common.h        |  3 ++
 .../drivers/dri/radeon/radeon_common_context.c     |  1 -
 .../drivers/dri/radeon/radeon_common_context.h     |  8 ++++
 src/mesa/drivers/dri/radeon/radeon_dma.c           | 25 ++--------
 src/mesa/drivers/dri/radeon/radeon_state.c         | 50 ++++++++++++++++++-
 src/mesa/drivers/dri/radeon/radeon_state.h         |  2 +-
 10 files changed, 149 insertions(+), 92 deletions(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_common_context.h')

diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c
index ca4dee8a5b..f040713980 100644
--- a/src/mesa/drivers/dri/r200/r200_state.c
+++ b/src/mesa/drivers/dri/r200/r200_state.c
@@ -2273,33 +2273,24 @@ static void update_texturematrix( GLcontext *ctx )
 static GLboolean r200ValidateBuffers(GLcontext *ctx)
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   struct radeon_cs_space_check bos[8];
    struct radeon_renderbuffer *rrb;
-   int num_bo = 0;
    int i;
-   int flushed = 0, ret;
-again:
-   num_bo = 0;
+
+   radeon_validate_reset_bos(&rmesa->radeon);
    
    rrb = radeon_get_colorbuffer(&rmesa->radeon);
    /* color buffer */
    if (rrb && rrb->bo) {
-      bos[num_bo].bo = rrb->bo;
-      bos[num_bo].read_domains = 0;
-      bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM;
-      bos[num_bo].new_accounted = 0;
-      num_bo++;
+     radeon_validate_bo(&rmesa->radeon, rrb->bo,
+			0, RADEON_GEM_DOMAIN_VRAM);
    }
 
    /* depth buffer */
    rrb = radeon_get_depthbuffer(&rmesa->radeon);
    /* color buffer */
    if (rrb && rrb->bo) {
-      bos[num_bo].bo = rrb->bo;
-      bos[num_bo].read_domains = 0;
-      bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM;
-      bos[num_bo].new_accounted = 0;
-      num_bo++;
+     radeon_validate_bo(&rmesa->radeon, rrb->bo,
+			0, RADEON_GEM_DOMAIN_VRAM);
    }
 
    for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) {
@@ -2307,26 +2298,17 @@ again:
       
       if (!ctx->Texture.Unit[i]._ReallyEnabled)
 	 continue;
-      
+
       t = radeon_tex_obj(ctx->Texture.Unit[i]._Current);
-      bos[num_bo].bo = t->mt->bo;
-      bos[num_bo].read_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
-      bos[num_bo].write_domain = 0;
-      bos[num_bo].new_accounted = 0;
-      num_bo++;
+      if (t->image_override && t->bo)
+	radeon_validate_bo(&rmesa->radeon, t->bo,
+			   RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+      else if (t->mt->bo)
+	radeon_validate_bo(&rmesa->radeon, t->mt->bo,
+			   RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
    }
-   
-   ret = radeon_cs_space_check(rmesa->radeon.cmdbuf.cs, bos, num_bo);
-   if (ret == RADEON_CS_SPACE_OP_TO_BIG)
-      return GL_FALSE;
-   if (ret == RADEON_CS_SPACE_FLUSH) {
-      radeonFlush(ctx);
-      if (flushed)
-	 return GL_FALSE;
-      flushed = 1;
-      goto again;
-   }
-   return GL_TRUE;
+
+   return radeon_revalidate_bos(ctx);
 }
 
 GLboolean r200ValidateState( GLcontext *ctx )
diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c
index 3ce0ba68c9..bcf8803875 100644
--- a/src/mesa/drivers/dri/r300/r300_emit.c
+++ b/src/mesa/drivers/dri/r300/r300_emit.c
@@ -352,7 +352,7 @@ void r300EmitCacheFlush(r300ContextPtr rmesa)
 {
 	BATCH_LOCALS(&rmesa->radeon);
 
-	BEGIN_BATCH(4);
+	BEGIN_BATCH_NO_AUTOSTATE(4);
 	OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT,
 		R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
 		R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c
index baaca5f1e5..5a87b5da43 100644
--- a/src/mesa/drivers/dri/r300/r300_texstate.c
+++ b/src/mesa/drivers/dri/r300/r300_texstate.c
@@ -268,40 +268,29 @@ static GLboolean r300_validate_texture(GLcontext * ctx, struct gl_texture_object
 	return GL_TRUE;
 }
 
-
 /**
  * Ensure all enabled and complete textures are uploaded along with any buffers being used.
  */
 GLboolean r300ValidateBuffers(GLcontext * ctx)
 {
 	r300ContextPtr rmesa = R300_CONTEXT(ctx);
-	struct radeon_cs_space_check bos[16];
 	struct radeon_renderbuffer *rrb;
-	int num_bo = 0;
 	int i;
-	int flushed = 0, ret;
-again:
-	num_bo = 0;
+
+	radeon_validate_reset_bos(&rmesa->radeon);
 
 	rrb = radeon_get_colorbuffer(&rmesa->radeon);
 	/* color buffer */
 	if (rrb && rrb->bo) {
-		bos[num_bo].bo = rrb->bo;
-		bos[num_bo].read_domains = 0;
-		bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM;
-		bos[num_bo].new_accounted = 0;
-		num_bo++;
+		radeon_validate_bo(&rmesa->radeon, rrb->bo,
+				   0, RADEON_GEM_DOMAIN_VRAM);
 	}
 
 	/* depth buffer */
 	rrb = radeon_get_depthbuffer(&rmesa->radeon);
-	/* color buffer */
 	if (rrb && rrb->bo) {
-		bos[num_bo].bo = rrb->bo;
-		bos[num_bo].read_domains = 0;
-		bos[num_bo].write_domain = RADEON_GEM_DOMAIN_VRAM;
-		bos[num_bo].new_accounted = 0;
-		num_bo++;
+		radeon_validate_bo(&rmesa->radeon, rrb->bo,
+				   0, RADEON_GEM_DOMAIN_VRAM);
 	}
 	
 	for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) {
@@ -317,26 +306,15 @@ again:
 		}
 		t = radeon_tex_obj(ctx->Texture.Unit[i]._Current);
 		if (t->image_override && t->bo)
-			bos[num_bo].bo = t->bo;
+			radeon_validate_bo(&rmesa->radeon, t->bo,
+					   RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+
 		else if (t->mt->bo)
-			bos[num_bo].bo = t->mt->bo;
-		bos[num_bo].read_domains = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
-		bos[num_bo].write_domain = 0;
-		bos[num_bo].new_accounted = 0;
-		num_bo++;
+			radeon_validate_bo(&rmesa->radeon, t->mt->bo,
+					   RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 	}
 
-	ret = radeon_cs_space_check(rmesa->radeon.cmdbuf.cs, bos, num_bo);
-	if (ret == RADEON_CS_SPACE_OP_TO_BIG)
-		return GL_FALSE;
-	if (ret == RADEON_CS_SPACE_FLUSH) {
-		radeonFlush(ctx);
-		if (flushed)
-			return GL_FALSE;
-		flushed = 1;
-		goto again;
-	}
-	return GL_TRUE;
+	return radeon_revalidate_bos(ctx);
 }
 
 void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c
index 3ce868d2cf..4f7bfebf04 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -906,6 +906,49 @@ static INLINE void radeonEmitAtoms(radeonContextPtr radeon, GLboolean dirty)
 	COMMIT_BATCH();
 }
 
+GLboolean radeon_revalidate_bos(GLcontext *ctx)
+{
+	radeonContextPtr radeon = RADEON_CONTEXT(ctx);
+	int flushed = 0;
+	int ret;
+again:
+	ret = radeon_cs_space_check(radeon->cmdbuf.cs, radeon->state.bos, radeon->state.validated_bo_count);
+	if (ret == RADEON_CS_SPACE_OP_TO_BIG)
+		return GL_FALSE;
+	if (ret == RADEON_CS_SPACE_FLUSH) {
+		radeonFlush(ctx);
+		if (flushed)
+			return GL_FALSE;
+		flushed = 1;
+		goto again;
+	}
+	return GL_TRUE;
+}
+
+void radeon_validate_reset_bos(radeonContextPtr radeon)
+{
+	int i;
+
+	for (i = 0; i < radeon->state.validated_bo_count; i++) {
+		radeon->state.bos[i].bo = NULL;
+		radeon->state.bos[i].read_domains = 0;
+		radeon->state.bos[i].write_domain = 0;
+		radeon->state.bos[i].new_accounted = 0;
+	}
+	radeon->state.validated_bo_count = 0;
+}
+
+void radeon_validate_bo(radeonContextPtr radeon, struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain)
+{
+	radeon->state.bos[radeon->state.validated_bo_count].bo = bo;
+	radeon->state.bos[radeon->state.validated_bo_count].read_domains = read_domains;
+	radeon->state.bos[radeon->state.validated_bo_count].write_domain = write_domain;
+	radeon->state.bos[radeon->state.validated_bo_count].new_accounted = 0;
+	radeon->state.validated_bo_count++;
+
+	assert(radeon->state.validated_bo_count < RADEON_MAX_BOS);
+}
+
 void radeonEmitState(radeonContextPtr radeon)
 {
 	if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS))
@@ -947,6 +990,14 @@ void radeonFlush(GLcontext *ctx)
 	if (RADEON_DEBUG & DEBUG_IOCTL)
 		fprintf(stderr, "%s %d\n", __FUNCTION__, radeon->cmdbuf.cs->cdw);
 
+	/* okay if we have no cmds in the buffer &&
+	   we have no DMA flush &&
+	   we have no DMA buffer allocated.
+	   then no point flushing anything at all.
+	*/
+	if (!radeon->dma.flush && !radeon->cmdbuf.cs->cdw && !radeon->dma.current)
+		return;
+
 	if (radeon->dma.flush)
 		radeon->dma.flush( ctx );
 
@@ -1015,6 +1066,11 @@ int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller)
 	}
 	radeon_cs_erase(rmesa->cmdbuf.cs);
 	rmesa->cmdbuf.flushing = 0;
+
+	if (radeon_revalidate_bos(rmesa->glCtx) == GL_FALSE) {
+		fprintf(stderr,"failed to revalidate buffers\n");
+	}
+
 	return ret;
 }
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h
index f3e2290cab..c2fbb0950d 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common.h
@@ -47,6 +47,9 @@ void radeon_get_cliprects(radeonContextPtr radeon,
 			  struct drm_clip_rect **cliprects,
 			  unsigned int *num_cliprects,
 			  int *x_off, int *y_off);
+GLboolean radeon_revalidate_bos(GLcontext *ctx);
+void radeon_validate_bo(radeonContextPtr radeon, struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain);
+void radeon_validate_reset_bos(radeonContextPtr radeon);
 
 void radeon_fbo_init(struct radeon_context *radeon);
 void
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index ef67c86f0b..ba74c97f2c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -219,7 +219,6 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv )
 	if (radeon) {
 
 		if (radeon->dma.current) {
-			radeonReleaseDmaRegion( radeon );
 			rcommonFlushCmdBuf( radeon, __FUNCTION__ );
 		}
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index c6e6be7484..d32e5af544 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -13,6 +13,10 @@
 #include "dri_util.h"
 #include "tnl/t_vertex.h"
 
+struct radeon_context;
+
+#include "radeon_bocs_wrapper.h"
+
 /* This union is used to avoid warnings/miscompilation
    with float to uint32_t casts due to strict-aliasing */
 typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
@@ -384,11 +388,15 @@ typedef void (*radeon_line_func) (radeonContextPtr,
 
 typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
 
+#define RADEON_MAX_BOS 24
 struct radeon_state {
 	struct radeon_colorbuffer_state color;
 	struct radeon_depthbuffer_state depth;
 	struct radeon_scissor_state scissor;
 	struct radeon_stencilbuffer_state stencil;
+
+	struct radeon_cs_space_check bos[RADEON_MAX_BOS];
+	int validated_bo_count;
 };
 
 /**
diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c
index 47f789e9cd..5ffee86e5a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_dma.c
+++ b/src/mesa/drivers/dri/radeon/radeon_dma.c
@@ -163,8 +163,6 @@ void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos,
 
 void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size)
 {
-	struct radeon_cs_space_check bos[1];
-	int flushed = 0, ret;
 
 	size = MAX2(size, MAX_DMA_BUF_SZ * 16);
 
@@ -200,24 +198,11 @@ again_alloc:
 	rmesa->dma.current_used = 0;
 	rmesa->dma.current_vertexptr = 0;
 	
-	bos[0].bo = rmesa->dma.current;
-	bos[0].read_domains = RADEON_GEM_DOMAIN_GTT;
-	bos[0].write_domain =0 ;
-	bos[0].new_accounted = 0;
-
-	ret = radeon_cs_space_check(rmesa->cmdbuf.cs, bos, 1);
-	if (ret == RADEON_CS_SPACE_OP_TO_BIG) {
-		fprintf(stderr,"Got OPEARTION TO BIG ILLEGAL - this cannot happen");
-		assert(0);
-	} else if (ret == RADEON_CS_SPACE_FLUSH) {
-		rcommonFlushCmdBuf(rmesa, __FUNCTION__);
-		if (flushed) {
-			fprintf(stderr,"flushed but still no space\n");
-			assert(0);
-		}
-		flushed = 1;
-		goto again_alloc;
-	}
+	radeon_validate_bo(rmesa, rmesa->dma.current, RADEON_GEM_DOMAIN_GTT, 0);
+
+	if (radeon_revalidate_bos(rmesa->glCtx) == GL_FALSE)
+	  fprintf(stderr,"failure to revalidate BOs - badness\n");
+	  
 	radeon_bo_map(rmesa->dma.current, 1);
 }
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c
index 19ff2688e6..dcca326c66 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state.c
@@ -47,6 +47,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "swrast_setup/swrast_setup.h"
 
 #include "radeon_context.h"
+#include "radeon_mipmap_tree.h"
 #include "radeon_ioctl.h"
 #include "radeon_state.h"
 #include "radeon_tcl.h"
@@ -2043,8 +2044,48 @@ static void update_texturematrix( GLcontext *ctx )
    }
 }
 
+static GLboolean r100ValidateBuffers(GLcontext *ctx)
+{
+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
+   struct radeon_renderbuffer *rrb;
+   int i;
+
+   radeon_validate_reset_bos(&rmesa->radeon);
+   
+   rrb = radeon_get_colorbuffer(&rmesa->radeon);
+   /* color buffer */
+   if (rrb && rrb->bo) {
+     radeon_validate_bo(&rmesa->radeon, rrb->bo,
+			0, RADEON_GEM_DOMAIN_VRAM);
+   }
+
+   /* depth buffer */
+   rrb = radeon_get_depthbuffer(&rmesa->radeon);
+   /* color buffer */
+   if (rrb && rrb->bo) {
+     radeon_validate_bo(&rmesa->radeon, rrb->bo,
+			0, RADEON_GEM_DOMAIN_VRAM);
+   }
 
-void radeonValidateState( GLcontext *ctx )
+   for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) {
+      radeonTexObj *t;
+      
+      if (!ctx->Texture.Unit[i]._ReallyEnabled)
+	 continue;
+
+      t = radeon_tex_obj(ctx->Texture.Unit[i]._Current);
+      if (t->image_override && t->bo)
+	radeon_validate_bo(&rmesa->radeon, t->bo,
+			   RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+      else if (t->mt->bo)
+	radeon_validate_bo(&rmesa->radeon, t->mt->bo,
+			   RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+   }
+
+   return radeon_revalidate_bos(ctx);
+}
+
+GLboolean radeonValidateState( GLcontext *ctx )
 {
    r100ContextPtr rmesa = R100_CONTEXT(ctx);
    GLuint new_state = rmesa->radeon.NewGLState;
@@ -2061,6 +2102,10 @@ void radeonValidateState( GLcontext *ctx )
       new_state |= rmesa->radeon.NewGLState; /* may add TEXTURE_MATRIX */
    }
 
+   /* we need to do a space check here */
+   if (!r100ValidateBuffers(ctx))
+     return GL_FALSE;
+
    /* Need an event driven matrix update?
     */
    if (new_state & (_NEW_MODELVIEW|_NEW_PROJECTION)) 
@@ -2136,7 +2181,8 @@ static void radeonWrapRunPipeline( GLcontext *ctx )
    /* Validate state:
     */
    if (rmesa->radeon.NewGLState)
-      radeonValidateState( ctx );
+      if (!radeonValidateState( ctx ))
+	 FALLBACK(rmesa, RADEON_FALLBACK_TEXTURE, GL_TRUE);
 
    has_material = (ctx->Light.Enabled && check_material( ctx ));
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_state.h b/src/mesa/drivers/dri/radeon/radeon_state.h
index f05fa827d7..a7c8eef32a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state.h
+++ b/src/mesa/drivers/dri/radeon/radeon_state.h
@@ -50,7 +50,7 @@ extern void radeonUpdateDrawBuffer( GLcontext *ctx );
 extern void radeonUploadTexMatrix( r100ContextPtr rmesa,
 				   int unit, GLboolean swapcols );
 
-extern void radeonValidateState( GLcontext *ctx );
+extern GLboolean radeonValidateState( GLcontext *ctx );
 
 
 extern void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode );
-- 
cgit v1.2.3


From 0b22615c2c860968a027c04519e25864ae69f6cd Mon Sep 17 00:00:00 2001
From: Maciej Cencora <m.cencora@gmail.com>
Date: Sat, 2 May 2009 17:27:03 +0200
Subject: r300: set proper texture row alignment for IGP chips

Looks like r400 based IGP chips require 64 byte alignment
---
 src/mesa/drivers/dri/r300/r300_context.c            |  5 +++++
 src/mesa/drivers/dri/radeon/radeon_common_context.c |  2 ++
 src/mesa/drivers/dri/radeon/radeon_common_context.h |  1 +
 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c    | 11 ++++++-----
 4 files changed, 14 insertions(+), 5 deletions(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_common_context.h')

diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c
index 4d1f10ba4d..70c7730be9 100644
--- a/src/mesa/drivers/dri/r300/r300_context.c
+++ b/src/mesa/drivers/dri/r300/r300_context.c
@@ -412,6 +412,11 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 	if (r300->radeon.radeonScreen->kernel_mm)
 	  driInitExtensions(ctx, mm_extensions, GL_FALSE);
 
+	if (screen->chip_family == CHIP_FAMILY_RS600 ||	screen->chip_family == CHIP_FAMILY_RS690 ||
+		screen->chip_family == CHIP_FAMILY_RS740) {
+		r300->radeon.texture_row_align = 64;
+	}
+
 	r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache,
 						     "def_max_anisotropy");
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index ba74c97f2c..3e713628ec 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -177,6 +177,8 @@ GLboolean radeonInitContext(radeonContextPtr radeon,
                 radeon->texture_depth = ( glVisual->rgbBits > 16 ) ?
 	        DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
 
+	radeon->texture_row_align = 32;
+
 	return GL_TRUE;
 }
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index d32e5af544..181688cbe4 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -421,6 +421,7 @@ struct radeon_context {
     */
    int                   texture_depth;
    float                 initialMaxAnisotropy;
+   uint32_t              texture_row_align;
 
   struct radeon_dma dma;
   struct radeon_hw_state hw;
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index 34d6261706..51538e37fa 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -86,10 +86,11 @@ static int radeon_compressed_num_bytes(GLuint mesaFormat)
  * \param curOffset points to the offset at which the image is to be stored
  * and is updated by this function according to the size of the image.
  */
-static void compute_tex_image_offset(radeon_mipmap_tree *mt,
+static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree *mt,
 	GLuint face, GLuint level, GLuint* curOffset)
 {
 	radeon_mipmap_level *lvl = &mt->levels[level];
+	uint32_t row_align = rmesa->texture_row_align - 1;
 
 	/* Find image size in bytes */
 	if (mt->compressed) {
@@ -107,7 +108,7 @@ static void compute_tex_image_offset(radeon_mipmap_tree *mt,
 		lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31;
 		lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth;
 	} else {
-		lvl->rowstride = (lvl->width * mt->bpp + 31) & ~31;
+		lvl->rowstride = (lvl->width * mt->bpp + row_align) & ~row_align;
 		lvl->size = lvl->rowstride * lvl->height * lvl->depth;
 	}
 	assert(lvl->size > 0);
@@ -131,7 +132,7 @@ static GLuint minify(GLuint size, GLuint levels)
 	return size;
 }
 
-static void calculate_miptree_layout(radeon_mipmap_tree *mt)
+static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
 {
 	GLuint curOffset;
 	GLuint numLevels;
@@ -149,7 +150,7 @@ static void calculate_miptree_layout(radeon_mipmap_tree *mt)
 		mt->levels[i].depth = minify(mt->depth0, i);
 
 		for(face = 0; face < mt->faces; face++)
-			compute_tex_image_offset(mt, face, i, &curOffset);
+			compute_tex_image_offset(rmesa, mt, face, i, &curOffset);
 	}
 
 	/* Note the required size in memory */
@@ -181,7 +182,7 @@ radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, radeonTexObj *
 	mt->tilebits = tilebits;
 	mt->compressed = compressed;
 
-	calculate_miptree_layout(mt);
+	calculate_miptree_layout(rmesa, mt);
 
 	mt->bo = radeon_bo_open(rmesa->radeonScreen->bom,
                             0, mt->totalsize, 1024,
-- 
cgit v1.2.3


From 98bb5c610dc68d8e9a185216ce9d2dc6d278c114 Mon Sep 17 00:00:00 2001
From: Joel Bosveld <joel.bosveld@gmail.com>
Date: Sun, 10 May 2009 18:26:40 +0200
Subject: radeon: add support for new dri2 interfaces & fix single buffer
 rendering

---
 src/mesa/drivers/dri/radeon/radeon_common.c        |  39 +++++++
 .../drivers/dri/radeon/radeon_common_context.c     | 115 ++++++++++++++++++---
 .../drivers/dri/radeon/radeon_common_context.h     |  16 +++
 3 files changed, 154 insertions(+), 16 deletions(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_common_context.h')

diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c
index daf03a9856..decea4518e 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -678,6 +678,7 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
 		if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) {
 			rrbColor = radeon_renderbuffer(fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer);
 			radeon->front_cliprects = GL_TRUE;
+			radeon->front_buffer_dirty = GL_TRUE;
 		} else {
 			rrbColor = radeon_renderbuffer(fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer);
 			radeon->front_cliprects = GL_FALSE;
@@ -793,6 +794,24 @@ void radeonDrawBuffer( GLcontext *ctx, GLenum mode )
 	if (RADEON_DEBUG & DEBUG_DRI)
 		fprintf(stderr, "%s %s\n", __FUNCTION__,
 			_mesa_lookup_enum_by_nr( mode ));
+
+	if (ctx->DrawBuffer->Name == 0) {
+		radeonContextPtr radeon = RADEON_CONTEXT(ctx);
+
+		const GLboolean was_front_buffer_rendering =
+			radeon->is_front_buffer_rendering;
+
+		radeon->is_front_buffer_rendering = (mode == GL_FRONT_LEFT) ||
+                                            (mode == GL_FRONT);
+
+      /* If we weren't front-buffer rendering before but we are now, make sure
+       * that the front-buffer has actually been allocated.
+       */
+		if (!was_front_buffer_rendering && radeon->is_front_buffer_rendering) {
+			radeon_update_renderbuffers(radeon->dri.context,
+				radeon->dri.context->driDrawablePriv);
+      }
+	}
 	
 	radeon_draw_buffer(ctx, ctx->DrawBuffer);
 }
@@ -1046,6 +1065,26 @@ void radeonFlush(GLcontext *ctx)
    
 	if (radeon->cmdbuf.cs->cdw)
 		rcommonFlushCmdBuf(radeon, __FUNCTION__);
+
+	if ((ctx->DrawBuffer->Name == 0) && radeon->front_buffer_dirty) {
+		__DRIscreen *const screen = radeon->radeonScreen->driScreen;
+
+		if (screen->dri2.loader && (screen->dri2.loader->base.version >= 2)
+			&& (screen->dri2.loader->flushFrontBuffer != NULL)) {
+			(*screen->dri2.loader->flushFrontBuffer)(radeon->dri.drawable,
+						  radeon->dri.drawable->loaderPrivate);
+
+			/* Only clear the dirty bit if front-buffer rendering is no longer
+			 * enabled.  This is done so that the dirty bit can only be set in
+			 * glDrawBuffer.  Otherwise the dirty bit would have to be set at
+			 * each of N places that do rendering.  This has worse performances,
+			 * but it is much easier to get correct.
+			 */
+			if (radeon->is_front_buffer_rendering) {
+				radeon->front_buffer_dirty = GL_FALSE;
+			}
+		}
+	}
 }
 
 /* Make sure all commands have been sent to the hardware and have
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index 3e713628ec..124b587bab 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -406,6 +406,23 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon,
 	}
 }
 
+static unsigned
+radeon_bits_per_pixel(const struct radeon_renderbuffer *rb)
+{
+   switch (rb->base._ActualFormat) {
+   case GL_RGB5:
+   case GL_DEPTH_COMPONENT16:
+      return 16;
+   case GL_RGB8:
+   case GL_RGBA8:
+   case GL_DEPTH_COMPONENT24:
+   case GL_DEPTH24_STENCIL8_EXT:
+   case GL_STENCIL_INDEX8_EXT:
+      return 32;
+   default:
+      return 0;
+   }
+}
 
 void
 radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
@@ -426,22 +443,63 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 	draw = drawable->driverPrivate;
 	screen = context->driScreenPriv;
 	radeon = (radeonContextPtr) context->driverPrivate;
-	i = 0;
-	if (draw->color_rb[0])
-		attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
-	if (draw->color_rb[1])
-		attachments[i++] = __DRI_BUFFER_BACK_LEFT;
-	if (radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH))
-		attachments[i++] = __DRI_BUFFER_DEPTH;
-	if (radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL))
-		attachments[i++] = __DRI_BUFFER_STENCIL;
+
+	if ((screen->dri2.loader->base.version > 2)
+	   && (screen->dri2.loader->getBuffersWithFormat != NULL)) {
+		struct radeon_renderbuffer *depth_rb;
+		struct radeon_renderbuffer *stencil_rb;
+
+		i = 0;
+		if ((radeon->is_front_buffer_rendering || !draw->color_rb[1])
+			&& draw->color_rb[0]) {
+			attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
+			attachments[i++] = radeon_bits_per_pixel(draw->color_rb[0]);
+		}
+
+		if (draw->color_rb[1]) {
+			attachments[i++] = __DRI_BUFFER_BACK_LEFT;
+			attachments[i++] = radeon_bits_per_pixel(draw->color_rb[1]);
+		}
+
+		depth_rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH);
+		stencil_rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL);
+
+		if ((depth_rb != NULL) && (stencil_rb != NULL)) {
+			attachments[i++] = __DRI_BUFFER_DEPTH_STENCIL;
+			attachments[i++] = radeon_bits_per_pixel(depth_rb);
+		} else if (depth_rb != NULL) {
+			attachments[i++] = __DRI_BUFFER_DEPTH;
+			attachments[i++] = radeon_bits_per_pixel(depth_rb);
+		} else if (stencil_rb != NULL) {
+			attachments[i++] = __DRI_BUFFER_STENCIL;
+			attachments[i++] = radeon_bits_per_pixel(stencil_rb);
+		}
+
+		buffers = (*screen->dri2.loader->getBuffersWithFormat)(drawable,
+								&drawable->w,
+								&drawable->h,
+								attachments, i / 2,
+								&count,
+								drawable->loaderPrivate);
+	} else {
+		i = 0;
+		if (draw->color_rb[0])
+			attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
+		if (draw->color_rb[1])
+			attachments[i++] = __DRI_BUFFER_BACK_LEFT;
+		if (radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH))
+			attachments[i++] = __DRI_BUFFER_DEPTH;
+		if (radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL))
+			attachments[i++] = __DRI_BUFFER_STENCIL;
 	
-	buffers = (*screen->dri2.loader->getBuffers)(drawable,
-						     &drawable->w,
-						     &drawable->h,
-						     attachments, i,
-						     &count,
-						     drawable->loaderPrivate);
+		buffers = (*screen->dri2.loader->getBuffers)(drawable,
+								 &drawable->w,
+								 &drawable->h,
+								 attachments, i,
+								 &count,
+								 drawable->loaderPrivate);
+	}
+
 	if (buffers == NULL)
 		return;
 
@@ -466,6 +524,10 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 			rb = draw->color_rb[0];
 			regname = "dri2 front buffer";
 			break;
+		case __DRI_BUFFER_FAKE_FRONT_LEFT:
+			rb = draw->color_rb[0];
+			regname = "dri2 fake front buffer";
+			break;
 		case __DRI_BUFFER_BACK_LEFT:
 			rb = draw->color_rb[1];
 			regname = "dri2 back buffer";
@@ -474,6 +536,10 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 			rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH);
 			regname = "dri2 depth buffer";
 			break;
+		case __DRI_BUFFER_DEPTH_STENCIL:
+			rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH);
+			regname = "dri2 depth / stencil buffer";
+			break;
 		case __DRI_BUFFER_STENCIL:
 			rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL);
 			regname = "dri2 stencil buffer";
@@ -535,7 +601,24 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 
 		radeon_renderbuffer_set_bo(rb, bo);
 		radeon_bo_unref(bo);
-		    
+
+		if (buffers[i].attachment == __DRI_BUFFER_DEPTH_STENCIL) {
+			rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL);
+			if (rb != NULL) {
+				struct radeon_bo *stencil_bo = NULL;
+
+				if (rb->bo) {
+					uint32_t name = radeon_gem_name_bo(rb->bo);
+					if (name == buffers[i].name)
+						continue;
+				}
+
+				stencil_bo = bo;
+				radeon_bo_ref(stencil_bo);
+				radeon_renderbuffer_set_bo(rb, stencil_bo);
+				radeon_bo_unref(stencil_bo);
+			}
+		}
 	}
 
 	driUpdateFramebufferSize(radeon->glCtx, drawable);
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index 181688cbe4..446c2f6269 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -463,6 +463,22 @@ struct radeon_context {
   GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */
   GLboolean front_cliprects;
 
+   /**
+    * Set if rendering has occured to the drawable's front buffer.
+    *
+    * This is used in the DRI2 case to detect that glFlush should also copy
+    * the contents of the fake front buffer to the real front buffer.
+    */
+   GLboolean front_buffer_dirty;
+
+   /**
+    * Track whether front-buffer rendering is currently enabled
+    *
+    * A separate flag is used to track this in order to support MRT more
+    * easily.
+    */
+   GLboolean is_front_buffer_rendering;
+
   struct {
       struct gl_fragment_program *bitmap_fp;
       struct gl_vertex_program *passthrough_vp;
-- 
cgit v1.2.3


From 01daeadf8cd8c56820585c3da88cc626dcdc33d0 Mon Sep 17 00:00:00 2001
From: Michel Dänzer <daenzer@vmware.com>
Date: Wed, 20 May 2009 16:39:33 +0200
Subject: radeon: Increase reference count of current renderbuffers.

Fixes

glxinfo: main/renderbuffer.c:2159: _mesa_reference_renderbuffer: Assertion
`oldRb->Magic == 0xaabbccdd' failed.
---
 src/mesa/drivers/dri/radeon/radeon_common.c         | 4 ++--
 src/mesa/drivers/dri/radeon/radeon_common.h         | 4 ++--
 src/mesa/drivers/dri/radeon/radeon_common_context.c | 9 +++++----
 src/mesa/drivers/dri/radeon/radeon_common_context.h | 4 ++--
 4 files changed, 11 insertions(+), 10 deletions(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_common_context.h')

diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c
index 2f55dadcb9..76e884d705 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -752,8 +752,8 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
 		ctx->NewState |= (_NEW_DEPTH | _NEW_STENCIL);
 	}
 	
-	radeon->state.depth.rrb = rrbDepth;
-	radeon->state.color.rrb = rrbColor;
+	_mesa_reference_renderbuffer(&radeon->state.depth.rb, &rrbDepth->base);
+	_mesa_reference_renderbuffer(&radeon->state.color.rb, &rrbColor->base);
 	radeon->state.color.draw_offset = offset;
 
 #if 0
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h
index c2fbb0950d..b60792df0b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common.h
@@ -77,7 +77,7 @@ static inline struct radeon_renderbuffer *radeon_get_renderbuffer(struct gl_fram
 static inline struct radeon_renderbuffer *radeon_get_depthbuffer(radeonContextPtr rmesa)
 {
 	struct radeon_renderbuffer *rrb;
-	rrb = rmesa->state.depth.rrb;
+	rrb = radeon_renderbuffer(rmesa->state.depth.rb);
 	if (!rrb)
 		return NULL;
 
@@ -88,7 +88,7 @@ static inline struct radeon_renderbuffer *radeon_get_colorbuffer(radeonContextPt
 {
 	struct radeon_renderbuffer *rrb;
 
-	rrb = rmesa->state.color.rrb;
+	rrb = radeon_renderbuffer(rmesa->state.color.rb);
 	if (!rrb)
 		return NULL;
 	return rrb;
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index 6fb6f92cb9..622bb98f3e 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -39,6 +39,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "drirenderbuffer.h"
 #include "main/context.h"
 #include "main/framebuffer.h"
+#include "main/renderbuffer.h"
 #include "main/state.h"
 #include "main/simple_list.h"
 #include "swrast/swrast.h"
@@ -651,10 +652,10 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
 		radeon_update_renderbuffers(driContextPriv, driDrawPriv);
 		if (driDrawPriv != driReadPriv)
 			radeon_update_renderbuffers(driContextPriv, driReadPriv);
-		radeon->state.color.rrb =
-			radeon_get_renderbuffer(&drfb->base, BUFFER_BACK_LEFT);
-		radeon->state.depth.rrb =
-			radeon_get_renderbuffer(&drfb->base, BUFFER_DEPTH);
+		_mesa_reference_renderbuffer(&radeon->state.color.rb,
+			&(radeon_get_renderbuffer(&drfb->base, BUFFER_BACK_LEFT)->base));
+		_mesa_reference_renderbuffer(&radeon->state.depth.rb,
+			&(radeon_get_renderbuffer(&drfb->base, BUFFER_DEPTH)->base));
 	} else {
 		radeon_make_renderbuffer_current(radeon, drfb);
 	}
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index 446c2f6269..af05f4ae32 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -121,13 +121,13 @@ struct radeon_framebuffer
 struct radeon_colorbuffer_state {
 	GLuint clear;
 	int roundEnable;
-	struct radeon_renderbuffer *rrb;
+	struct gl_renderbuffer *rb;
 	uint32_t draw_offset; /* offset into color renderbuffer - FBOs */
 };
 
 struct radeon_depthbuffer_state {
 	GLuint clear;
-	struct radeon_renderbuffer *rrb;
+	struct gl_renderbuffer *rb;
 };
 
 struct radeon_scissor_state {
-- 
cgit v1.2.3


From 7dd184dc4da37233471875df6f40cce0560cb7bc Mon Sep 17 00:00:00 2001
From: Nicolai Hähnle <nhaehnle@gmail.com>
Date: Sun, 24 May 2009 14:55:51 +0200
Subject: radeon: Remove drawable & readable from radeon_dri_mirror
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The duplication of state data caused a crash due to double-free on destruction
of context, because a variable wasn't correctly null'ed out.

Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
---
 src/mesa/drivers/dri/r200/r200_ioctl.c             |  30 ++--
 src/mesa/drivers/dri/r200/r200_pixel.c             |  30 ++--
 src/mesa/drivers/dri/r200/r200_state.c             | 152 ++++++++++-----------
 src/mesa/drivers/dri/r200/r200_swtcl.c             |  36 ++---
 src/mesa/drivers/dri/r300/r300_ioctl.c             |  16 +--
 src/mesa/drivers/dri/r300/r300_state.c             |  18 +--
 src/mesa/drivers/dri/radeon/radeon_common.c        |  63 +++++----
 .../drivers/dri/radeon/radeon_common_context.c     |  66 ++++-----
 .../drivers/dri/radeon/radeon_common_context.h     |  27 ++--
 src/mesa/drivers/dri/radeon/radeon_ioctl.c         |  54 ++++----
 src/mesa/drivers/dri/radeon/radeon_lock.c          |   8 +-
 src/mesa/drivers/dri/radeon/radeon_screen.c        |   1 +
 src/mesa/drivers/dri/radeon/radeon_state.c         | 128 ++++++++---------
 13 files changed, 310 insertions(+), 319 deletions(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_common_context.h')

diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c
index 0262aea880..0b3398a730 100644
--- a/src/mesa/drivers/dri/r200/r200_ioctl.c
+++ b/src/mesa/drivers/dri/r200/r200_ioctl.c
@@ -31,7 +31,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  * Authors:
  *   Keith Whitwell <keith@tungstengraphics.com>
  */
- 
+
 #include <sched.h>
 #include <errno.h>
 
@@ -66,7 +66,7 @@ static void r200UserClear(GLcontext *ctx, GLuint mask)
 static void r200KernelClear(GLcontext *ctx, GLuint flags)
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
+   __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon);
    GLint cx, cy, cw, ch, ret;
    GLuint i;
 
@@ -94,7 +94,7 @@ static void r200KernelClear(GLcontext *ctx, GLuint flags)
       if ( rmesa->radeon.sarea->last_clear - clear <= 25 ) {
 	 break;
       }
-      
+
       if (rmesa->radeon.do_usleeps) {
 	 UNLOCK_HARDWARE( &rmesa->radeon );
 	 DO_USLEEP( 1 );
@@ -190,7 +190,7 @@ static void r200KernelClear(GLcontext *ctx, GLuint flags)
 static void r200Clear( GLcontext *ctx, GLbitfield mask )
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
+   __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon);
    GLuint flags = 0;
    GLuint color_mask = 0;
    GLuint orig_mask = mask;
@@ -202,7 +202,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask )
    {
       LOCK_HARDWARE( &rmesa->radeon );
       UNLOCK_HARDWARE( &rmesa->radeon );
-      if ( dPriv->numClipRects == 0 ) 
+      if ( dPriv->numClipRects == 0 )
 	 return;
    }
 
@@ -236,7 +236,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask )
       _swrast_Clear( ctx, mask );
    }
 
-   if ( !flags ) 
+   if ( !flags )
       return;
 
    if (rmesa->using_hyperz) {
@@ -267,7 +267,7 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask )
  * device fd.
  */
 void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size,
-			     GLfloat readfreq, GLfloat writefreq, 
+			     GLfloat readfreq, GLfloat writefreq,
 			     GLfloat priority)
 {
    GET_CURRENT_CONTEXT(ctx);
@@ -277,7 +277,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size,
    int ret;
 
    if (R200_DEBUG & DEBUG_IOCTL)
-      fprintf(stderr, "%s sz %d %f/%f/%f\n", __FUNCTION__, size, readfreq, 
+      fprintf(stderr, "%s sz %d %f/%f/%f\n", __FUNCTION__, size, readfreq,
 	      writefreq, priority);
 
    if (!ctx || !(rmesa = R200_CONTEXT(ctx)) || !rmesa->radeon.radeonScreen->gartTextures.map)
@@ -294,12 +294,12 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size,
    ret = drmCommandWriteRead( rmesa->radeon.radeonScreen->driScreen->fd,
 			      DRM_RADEON_ALLOC,
 			      &alloc, sizeof(alloc));
-   
+
    if (ret) {
       fprintf(stderr, "%s: DRM_RADEON_ALLOC ret %d\n", __FUNCTION__, ret);
       return NULL;
    }
-   
+
    {
       char *region_start = (char *)rmesa->radeon.radeonScreen->gartTextures.map;
       return (void *)(region_start + region_offset);
@@ -326,7 +326,7 @@ void r200FreeMemoryMESA(__DRIscreen *screen, GLvoid *pointer)
 
    region_offset = (char *)pointer - (char *)rmesa->radeon.radeonScreen->gartTextures.map;
 
-   if (region_offset < 0 || 
+   if (region_offset < 0 ||
        region_offset > rmesa->radeon.radeonScreen->gartTextures.size) {
       fprintf(stderr, "offset %d outside range 0..%d\n", region_offset,
 	      rmesa->radeon.radeonScreen->gartTextures.size);
@@ -335,12 +335,12 @@ void r200FreeMemoryMESA(__DRIscreen *screen, GLvoid *pointer)
 
    memfree.region = RADEON_MEM_REGION_GART;
    memfree.region_offset = region_offset;
-   
+
    ret = drmCommandWrite( rmesa->radeon.radeonScreen->driScreen->fd,
 			  DRM_RADEON_FREE,
 			  &memfree, sizeof(memfree));
-   
-   if (ret) 
+
+   if (ret)
       fprintf(stderr, "%s: DRM_RADEON_FREE ret %d\n", __FUNCTION__, ret);
 }
 
@@ -374,7 +374,7 @@ GLboolean r200IsGartMemory( r200ContextPtr rmesa, const GLvoid *pointer,
 
    if (R200_DEBUG & DEBUG_IOCTL)
       fprintf(stderr, "r200IsGartMemory( %p ) : %d\n", pointer, valid );
-   
+
    return valid;
 }
 
diff --git a/src/mesa/drivers/dri/r200/r200_pixel.c b/src/mesa/drivers/dri/r200/r200_pixel.c
index 354daef07f..654f2c6ae9 100644
--- a/src/mesa/drivers/dri/r200/r200_pixel.c
+++ b/src/mesa/drivers/dri/r200/r200_pixel.c
@@ -65,8 +65,8 @@ check_color( const GLcontext *ctx, GLenum type, GLenum format,
       return GL_FALSE;
    }
 
-   if ( type == GL_UNSIGNED_INT_8_8_8_8_REV && 
-	cpp == 4 && 
+   if ( type == GL_UNSIGNED_INT_8_8_8_8_REV &&
+	cpp == 4 &&
 	format == GL_BGRA ) {
       if (R200_DEBUG & DEBUG_PIXEL)
 	 fprintf(stderr, "%s: passed 2\n", __FUNCTION__);
@@ -83,7 +83,7 @@ static GLboolean
 check_color_per_fragment_ops( const GLcontext *ctx )
 {
    int result;
-   result = (!(     ctx->Color.AlphaEnabled || 
+   result = (!(     ctx->Color.AlphaEnabled ||
 		    ctx->Depth.Test ||
 		    ctx->Fog.Enabled ||
 		    ctx->Scissor.Enabled ||
@@ -96,7 +96,7 @@ check_color_per_fragment_ops( const GLcontext *ctx )
 		    ctx->Texture._EnabledUnits
            ) &&
 	   ctx->Current.RasterPosValid);
-   
+
    return result;
 }
 
@@ -163,7 +163,7 @@ r200TryReadPixels( GLcontext *ctx,
 
    /* Only accelerate reading to GART buffers.
     */
-   if ( !r200IsGartMemory(rmesa, pixels, 
+   if ( !r200IsGartMemory(rmesa, pixels,
 			 pitch * height * rmesa->radeon.radeonScreen->cpp ) ) {
       if (R200_DEBUG & DEBUG_PIXEL)
 	 fprintf(stderr, "%s: dest not GART\n", __FUNCTION__);
@@ -224,7 +224,7 @@ r200TryReadPixels( GLcontext *ctx,
       drm_clip_rect_t *box = dPriv->pClipRects;
       int i;
 
-      r200EmitWait( rmesa, RADEON_WAIT_3D ); 
+      r200EmitWait( rmesa, RADEON_WAIT_3D );
 
       y = dPriv->h - y - height;
       x += dPriv->x;
@@ -241,7 +241,7 @@ r200TryReadPixels( GLcontext *ctx,
 	 GLint by = box[i].y1;
 	 GLint bw = box[i].x2 - bx;
 	 GLint bh = box[i].y2 - by;
-	 
+
 	 if (bx < x) bw -= x - bx, bx = x;
 	 if (by < y) bh -= y - by, by = y;
 	 if (bx + bw > x + width) bw = x + width - bx;
@@ -277,9 +277,9 @@ r200ReadPixels( GLcontext *ctx,
    if (R200_DEBUG & DEBUG_PIXEL)
       fprintf(stderr, "%s\n", __FUNCTION__);
 
-   if (!r200TryReadPixels( ctx, x, y, width, height, format, type, pack, 
+   if (!r200TryReadPixels( ctx, x, y, width, height, format, type, pack,
 			   pixels))
-      _swrast_ReadPixels( ctx, x, y, width, height, format, type, pack, 
+      _swrast_ReadPixels( ctx, x, y, width, height, format, type, pack,
 			  pixels);
 }
 
@@ -293,7 +293,7 @@ static void do_draw_pix( GLcontext *ctx,
 			 GLuint planemask)
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
+   __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon);
    drm_clip_rect_t *box = dPriv->pClipRects;
    struct gl_renderbuffer *rb = ctx->ReadBuffer->_ColorDrawBuffers[0];
    driRenderbuffer *drb = (driRenderbuffer *) rb;
@@ -325,7 +325,7 @@ static void do_draw_pix( GLcontext *ctx,
       rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ );
 
    y -= height;			/* cope with pixel zoom */
-   
+
    if (!clip_pixelrect(ctx, ctx->DrawBuffer,
 		       &x, &y, &width, &height,
 		       &size)) {
@@ -409,7 +409,7 @@ r200TryDrawPixels( GLcontext *ctx,
       if (planemask != ~0)
 	 return GL_FALSE;	/* fix me -- should be possible */
 
-      /* Can't do conversions on GART reads/draws. 
+      /* Can't do conversions on GART reads/draws.
        */
       if ( !r200IsGartMemory( rmesa, pixels, size ) ) {
 	 if (R200_DEBUG & DEBUG_PIXEL)
@@ -484,9 +484,9 @@ r200Bitmap( GLcontext *ctx, GLint px, GLint py,
 void r200InitPixelFuncs( GLcontext *ctx )
 {
    if (!getenv("R200_NO_BLITS")) {
-      ctx->Driver.ReadPixels = r200ReadPixels;  
-      ctx->Driver.DrawPixels = r200DrawPixels; 
-      if (getenv("R200_HW_BITMAP")) 
+      ctx->Driver.ReadPixels = r200ReadPixels;
+      ctx->Driver.DrawPixels = r200DrawPixels;
+      if (getenv("R200_HW_BITMAP"))
 	 ctx->Driver.Bitmap = r200Bitmap;
    }
 }
diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c
index 6802e190a7..f8ebe0df57 100644
--- a/src/mesa/drivers/dri/r200/r200_state.c
+++ b/src/mesa/drivers/dri/r200/r200_state.c
@@ -79,7 +79,7 @@ static void r200AlphaFunc( GLcontext *ctx, GLenum func, GLfloat ref )
 
    switch ( func ) {
    case GL_NEVER:
-      pp_misc |= R200_ALPHA_TEST_FAIL; 
+      pp_misc |= R200_ALPHA_TEST_FAIL;
       break;
    case GL_LESS:
       pp_misc |= R200_ALPHA_TEST_LESS;
@@ -479,7 +479,7 @@ static void r200Fogfv( GLcontext *ctx, GLenum pname, const GLfloat *param )
 	 }
       }
       break;
-   case GL_FOG_COLOR: 
+   case GL_FOG_COLOR:
       R200_STATECHANGE( rmesa, ctx );
       UNCLAMPED_FLOAT_TO_RGB_CHAN( col, ctx->Fog.Color );
       i = radeonPackColor( 4, col[0], col[1], col[2], 0 );
@@ -507,7 +507,7 @@ static void r200Fogfv( GLcontext *ctx, GLenum pname, const GLfloat *param )
 
       if (out_0 != rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0]) {
 	 R200_STATECHANGE( rmesa, vtx );
-	 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] = out_0;	 
+	 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] = out_0;
       }
 
       break;
@@ -696,7 +696,7 @@ static void r200LineStipple( GLcontext *ctx, GLint factor, GLushort pattern )
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
 
    R200_STATECHANGE( rmesa, lin );
-   rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = 
+   rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] =
       ((((GLuint)factor & 0xff) << 16) | ((GLuint)pattern));
 }
 
@@ -720,10 +720,10 @@ static void r200ColorMask( GLcontext *ctx,
    if (!(r && g && b && a))
       flag |= R200_PLANE_MASK_ENABLE;
 
-   if ( rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] != flag ) { 
-      R200_STATECHANGE( rmesa, ctx ); 
-      rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = flag; 
-   } 
+   if ( rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] != flag ) {
+      R200_STATECHANGE( rmesa, ctx );
+      rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = flag;
+   }
 
    if ( rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] != mask ) {
       R200_STATECHANGE( rmesa, msk );
@@ -774,7 +774,7 @@ static void r200PolygonStipple( GLcontext *ctx, const GLubyte *mask )
    /* FIXME: Use window x,y offsets into stipple RAM.
     */
    stipple.mask = rmesa->state.stipple.mask;
-   drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_STIPPLE, 
+   drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_STIPPLE,
                     &stipple, sizeof(stipple) );
    UNLOCK_HARDWARE( &rmesa->radeon );
 }
@@ -785,7 +785,7 @@ static void r200PolygonMode( GLcontext *ctx, GLenum face, GLenum mode )
    GLboolean flag = (ctx->_TriangleCaps & DD_TRI_UNFILLED) != 0;
 
    /* Can't generally do unfilled via tcl, but some good special
-    * cases work. 
+    * cases work.
     */
    TCL_FALLBACK( ctx, R200_TCL_FALLBACK_UNFILLED, flag);
    if (rmesa->radeon.TclFallback) {
@@ -827,34 +827,34 @@ static void r200UpdateSpecular( GLcontext *ctx )
 
    if (ctx->Light.Enabled &&
        ctx->Light.Model.ColorControl == GL_SEPARATE_SPECULAR_COLOR) {
-      rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= 
+      rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |=
 	 ((R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT) |
-	  (R200_VTX_FP_RGBA << R200_VTX_COLOR_1_SHIFT));	
+	  (R200_VTX_FP_RGBA << R200_VTX_COLOR_1_SHIFT));
       rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] |= R200_OUTPUT_COLOR_0;
       rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] |= R200_OUTPUT_COLOR_1;
       rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_LIGHTING_ENABLE;
       p |=  R200_SPECULAR_ENABLE;
-      rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &= 
+      rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &=
 	 ~R200_DIFFUSE_SPECULAR_COMBINE;
    }
    else if (ctx->Light.Enabled) {
-      rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= 
-	 ((R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT));	
+      rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |=
+	 ((R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT));
       rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] |= R200_OUTPUT_COLOR_0;
       rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_LIGHTING_ENABLE;
    } else if (ctx->Fog.ColorSumEnabled ) {
-      rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= 
+      rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |=
 	 ((R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT) |
-	  (R200_VTX_FP_RGBA << R200_VTX_COLOR_1_SHIFT));	
+	  (R200_VTX_FP_RGBA << R200_VTX_COLOR_1_SHIFT));
       p |=  R200_SPECULAR_ENABLE;
    } else {
-      rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= 
-	 ((R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT));	
+      rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |=
+	 ((R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT));
    }
 
    if (ctx->Fog.Enabled) {
-      rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= 
-	 ((R200_VTX_FP_RGBA << R200_VTX_COLOR_1_SHIFT));	
+      rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |=
+	 ((R200_VTX_FP_RGBA << R200_VTX_COLOR_1_SHIFT));
       rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] |= R200_OUTPUT_COLOR_1;
    }
 
@@ -865,7 +865,7 @@ static void r200UpdateSpecular( GLcontext *ctx )
 
    /* Update vertex/render formats
     */
-   if (rmesa->radeon.TclFallback) { 
+   if (rmesa->radeon.TclFallback) {
       r200ChooseRenderState( ctx );
       r200ChooseVertexState( ctx );
    }
@@ -877,7 +877,7 @@ static void r200UpdateSpecular( GLcontext *ctx )
  */
 
 
-/* Update on colormaterial, material emmissive/ambient, 
+/* Update on colormaterial, material emmissive/ambient,
  * lightmodel.globalambient
  */
 static void update_global_ambient( GLcontext *ctx )
@@ -891,23 +891,23 @@ static void update_global_ambient( GLcontext *ctx )
     */
    if ((rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] &
        ((3 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) |
-	(3 << R200_FRONT_AMBIENT_SOURCE_SHIFT))) == 0) 
+	(3 << R200_FRONT_AMBIENT_SOURCE_SHIFT))) == 0)
    {
-      COPY_3V( &fcmd[GLT_RED], 
+      COPY_3V( &fcmd[GLT_RED],
 	       ctx->Light.Material.Attrib[MAT_ATTRIB_FRONT_EMISSION]);
       ACC_SCALE_3V( &fcmd[GLT_RED],
 		   ctx->Light.Model.Ambient,
 		   ctx->Light.Material.Attrib[MAT_ATTRIB_FRONT_AMBIENT]);
-   } 
+   }
    else
    {
       COPY_3V( &fcmd[GLT_RED], ctx->Light.Model.Ambient );
    }
-   
+
    R200_DB_STATECHANGE(rmesa, &rmesa->hw.glt);
 }
 
-/* Update on change to 
+/* Update on change to
  *    - light[p].colors
  *    - light[p].enabled
  */
@@ -921,10 +921,10 @@ static void update_light_colors( GLcontext *ctx, GLuint p )
       r200ContextPtr rmesa = R200_CONTEXT(ctx);
       float *fcmd = (float *)R200_DB_STATE( lit[p] );
 
-      COPY_4V( &fcmd[LIT_AMBIENT_RED], l->Ambient );	 
+      COPY_4V( &fcmd[LIT_AMBIENT_RED], l->Ambient );
       COPY_4V( &fcmd[LIT_DIFFUSE_RED], l->Diffuse );
       COPY_4V( &fcmd[LIT_SPECULAR_RED], l->Specular );
-      
+
       R200_DB_STATECHANGE( rmesa, &rmesa->hw.lit[p] );
    }
 }
@@ -944,7 +944,7 @@ static void r200ColorMaterial( GLcontext *ctx, GLenum face, GLenum mode )
 
    if (ctx->Light.ColorMaterialEnabled) {
       GLuint mask = ctx->Light.ColorMaterialBitmask;
-   
+
       if (mask & MAT_BIT_FRONT_EMISSION) {
 	 light_model_ctl1 |= (R200_LM1_SOURCE_VERTEX_COLOR_0 <<
 			     R200_FRONT_EMISSIVE_SOURCE_SHIFT);
@@ -960,7 +960,7 @@ static void r200ColorMaterial( GLcontext *ctx, GLenum face, GLenum mode )
       else
          light_model_ctl1 |= (R200_LM1_SOURCE_MATERIAL_0 <<
 			     R200_FRONT_AMBIENT_SOURCE_SHIFT);
-	 
+
       if (mask & MAT_BIT_FRONT_DIFFUSE) {
 	 light_model_ctl1 |= (R200_LM1_SOURCE_VERTEX_COLOR_0 <<
 			     R200_FRONT_DIFFUSE_SOURCE_SHIFT);
@@ -968,7 +968,7 @@ static void r200ColorMaterial( GLcontext *ctx, GLenum face, GLenum mode )
       else
          light_model_ctl1 |= (R200_LM1_SOURCE_MATERIAL_0 <<
 			     R200_FRONT_DIFFUSE_SOURCE_SHIFT);
-   
+
       if (mask & MAT_BIT_FRONT_SPECULAR) {
 	 light_model_ctl1 |= (R200_LM1_SOURCE_VERTEX_COLOR_0 <<
 			     R200_FRONT_SPECULAR_SOURCE_SHIFT);
@@ -977,7 +977,7 @@ static void r200ColorMaterial( GLcontext *ctx, GLenum face, GLenum mode )
          light_model_ctl1 |= (R200_LM1_SOURCE_MATERIAL_0 <<
 			     R200_FRONT_SPECULAR_SOURCE_SHIFT);
       }
-   
+
       if (mask & MAT_BIT_BACK_EMISSION) {
 	 light_model_ctl1 |= (R200_LM1_SOURCE_VERTEX_COLOR_0 <<
 			     R200_BACK_EMISSIVE_SOURCE_SHIFT);
@@ -1027,8 +1027,8 @@ static void r200ColorMaterial( GLcontext *ctx, GLenum face, GLenum mode )
       R200_STATECHANGE( rmesa, tcl );
       rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] = light_model_ctl1;
    }
-   
-   
+
+
 }
 
 void r200UpdateMaterial( GLcontext *ctx )
@@ -1038,7 +1038,7 @@ void r200UpdateMaterial( GLcontext *ctx )
    GLfloat *fcmd = (GLfloat *)R200_DB_STATE( mtl[0] );
    GLfloat *fcmd2 = (GLfloat *)R200_DB_STATE( mtl[1] );
    GLuint mask = ~0;
-   
+
    /* Might be possible and faster to update everything unconditionally? */
    if (ctx->Light.ColorMaterialEnabled)
       mask &= ~ctx->Light.ColorMaterialBitmask;
@@ -1124,7 +1124,7 @@ void r200UpdateMaterial( GLcontext *ctx )
  *
  * which are calculated in light.c and are correct for the current
  * lighting space (model or eye), hence dependencies on _NEW_MODELVIEW
- * and _MESA_NEW_NEED_EYE_COORDS.  
+ * and _MESA_NEW_NEED_EYE_COORDS.
  */
 static void update_light( GLcontext *ctx )
 {
@@ -1141,8 +1141,8 @@ static void update_light( GLcontext *ctx )
 	 tmp &= ~R200_LIGHT_IN_MODELSPACE;
       else
 	 tmp |= R200_LIGHT_IN_MODELSPACE;
-      
-      if (tmp != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0]) 
+
+      if (tmp != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0])
       {
 	 R200_STATECHANGE( rmesa, tcl );
 	 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] = tmp;
@@ -1166,10 +1166,10 @@ static void update_light( GLcontext *ctx )
 	 if (ctx->Light.Light[p].Enabled) {
 	    struct gl_light *l = &ctx->Light.Light[p];
 	    GLfloat *fcmd = (GLfloat *)R200_DB_STATE( lit[p] );
-	    
+
 	    if (l->EyePosition[3] == 0.0) {
-	       COPY_3FV( &fcmd[LIT_POSITION_X], l->_VP_inf_norm ); 
-	       COPY_3FV( &fcmd[LIT_DIRECTION_X], l->_h_inf_norm ); 
+	       COPY_3FV( &fcmd[LIT_POSITION_X], l->_VP_inf_norm );
+	       COPY_3FV( &fcmd[LIT_DIRECTION_X], l->_h_inf_norm );
 	       fcmd[LIT_POSITION_W] = 0;
 	       fcmd[LIT_DIRECTION_W] = 0;
 	    } else {
@@ -1193,21 +1193,21 @@ static void r200Lightfv( GLcontext *ctx, GLenum light,
    GLint p = light - GL_LIGHT0;
    struct gl_light *l = &ctx->Light.Light[p];
    GLfloat *fcmd = (GLfloat *)rmesa->hw.lit[p].cmd;
-   
+
 
    switch (pname) {
-   case GL_AMBIENT:		
+   case GL_AMBIENT:
    case GL_DIFFUSE:
    case GL_SPECULAR:
       update_light_colors( ctx, p );
       break;
 
-   case GL_SPOT_DIRECTION: 
-      /* picked up in update_light */	
+   case GL_SPOT_DIRECTION:
+      /* picked up in update_light */
       break;
 
    case GL_POSITION: {
-      /* positions picked up in update_light, but can do flag here */	
+      /* positions picked up in update_light, but can do flag here */
       GLuint flag = (p&1)? R200_LIGHT_1_IS_LOCAL : R200_LIGHT_0_IS_LOCAL;
       GLuint idx = TCL_PER_LIGHT_CTL_0 + p/2;
 
@@ -1323,7 +1323,7 @@ static void r200LightModelfv( GLcontext *ctx, GLenum pname,
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
 
    switch (pname) {
-      case GL_LIGHT_MODEL_AMBIENT: 
+      case GL_LIGHT_MODEL_AMBIENT:
 	 update_global_ambient( ctx );
 	 break;
 
@@ -1582,7 +1582,7 @@ static void r200ClearStencil( GLcontext *ctx, GLint s )
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
 
-   rmesa->radeon.state.stencil.clear = 
+   rmesa->radeon.state.stencil.clear =
       ((GLuint) (ctx->Stencil.Clear & 0xff) |
        (0xff << R200_STENCIL_MASK_SHIFT) |
        ((ctx->Stencil.WriteMask[0] & 0xff) << R200_STENCIL_WRITEMASK_SHIFT));
@@ -1607,7 +1607,7 @@ static void r200ClearStencil( GLcontext *ctx, GLint s )
 void r200UpdateWindow( GLcontext *ctx )
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
+   __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon);
    GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
    GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
    const GLfloat *v = ctx->Viewport._WindowMap.m;
@@ -1663,7 +1663,7 @@ static void r200DepthRange( GLcontext *ctx, GLclampd nearval,
 void r200UpdateViewportOffset( GLcontext *ctx )
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
+   __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon);
    GLfloat xoffset = (GLfloat)dPriv->x;
    GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h;
    const GLfloat *v = ctx->Viewport._WindowMap.m;
@@ -1693,8 +1693,8 @@ void r200UpdateViewportOffset( GLcontext *ctx )
                 R200_STIPPLE_Y_OFFSET_MASK);
 
          /* add magic offsets, then invert */
-         stx = 31 - ((rmesa->radeon.dri.drawable->x - 1) & R200_STIPPLE_COORD_MASK);
-         sty = 31 - ((rmesa->radeon.dri.drawable->y + rmesa->radeon.dri.drawable->h - 1)
+         stx = 31 - ((dPriv->x - 1) & R200_STIPPLE_COORD_MASK);
+         sty = 31 - ((dPriv->y + dPriv->h - 1)
                      & R200_STIPPLE_COORD_MASK);
 
          m |= ((stx << R200_STIPPLE_X_OFFSET_SHIFT) |
@@ -1808,7 +1808,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state )
    case GL_CLIP_PLANE2:
    case GL_CLIP_PLANE3:
    case GL_CLIP_PLANE4:
-   case GL_CLIP_PLANE5: 
+   case GL_CLIP_PLANE5:
       p = cap-GL_CLIP_PLANE0;
       R200_STATECHANGE( rmesa, tcl );
       if (state) {
@@ -1860,7 +1860,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state )
 	 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~R200_TCL_FOG_MASK;
       }
       r200UpdateSpecular( ctx ); /* for PK_SPEC */
-      if (rmesa->radeon.TclFallback) 
+      if (rmesa->radeon.TclFallback)
 	 r200ChooseVertexState( ctx );
       _mesa_allow_light_in_model( ctx, !state );
       break;
@@ -1875,13 +1875,13 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state )
    case GL_LIGHT7:
       R200_STATECHANGE(rmesa, tcl);
       p = cap - GL_LIGHT0;
-      if (p&1) 
+      if (p&1)
 	 flag = (R200_LIGHT_1_ENABLE |
-		 R200_LIGHT_1_ENABLE_AMBIENT | 
+		 R200_LIGHT_1_ENABLE_AMBIENT |
 		 R200_LIGHT_1_ENABLE_SPECULAR);
       else
 	 flag = (R200_LIGHT_0_ENABLE |
-		 R200_LIGHT_0_ENABLE_AMBIENT | 
+		 R200_LIGHT_0_ENABLE_AMBIENT |
 		 R200_LIGHT_0_ENABLE_SPECULAR);
 
       if (state)
@@ -1889,7 +1889,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state )
       else
 	 rmesa->hw.tcl.cmd[p/2 + TCL_PER_LIGHT_CTL_0] &= ~flag;
 
-      /* 
+      /*
        */
       update_light_colors( ctx, p );
       break;
@@ -2043,7 +2043,7 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state )
    case GL_TEXTURE_GEN_T:
       /* Picked up in r200UpdateTextureState.
        */
-      rmesa->recheck_texgen[ctx->Texture.CurrentUnit] = GL_TRUE; 
+      rmesa->recheck_texgen[ctx->Texture.CurrentUnit] = GL_TRUE;
       break;
 
    case GL_COLOR_SUM_EXT:
@@ -2160,7 +2160,7 @@ void r200LightingSpaceChange( GLcontext *ctx )
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
    GLboolean tmp;
 
-   if (R200_DEBUG & DEBUG_STATE) 
+   if (R200_DEBUG & DEBUG_STATE)
       fprintf(stderr, "%s %d BEFORE %x\n", __FUNCTION__, ctx->_NeedEyeCoords,
 	      rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0]);
 
@@ -2176,7 +2176,7 @@ void r200LightingSpaceChange( GLcontext *ctx )
       rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &= ~R200_RESCALE_NORMALS;
    }
 
-   if (R200_DEBUG & DEBUG_STATE) 
+   if (R200_DEBUG & DEBUG_STATE)
       fprintf(stderr, "%s %d AFTER %x\n", __FUNCTION__, ctx->_NeedEyeCoords,
 	      rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0]);
 }
@@ -2219,7 +2219,7 @@ static void update_texturematrix( GLcontext *ctx )
    GLuint compsel = rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL];
    int unit;
 
-   if (R200_DEBUG & DEBUG_STATE) 
+   if (R200_DEBUG & DEBUG_STATE)
       fprintf(stderr, "%s before COMPSEL: %x\n", __FUNCTION__,
 	      rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL]);
 
@@ -2227,7 +2227,7 @@ static void update_texturematrix( GLcontext *ctx )
    rmesa->TexMatCompSel = 0;
 
    for (unit = 0 ; unit < ctx->Const.MaxTextureUnits; unit++) {
-      if (!ctx->Texture.Unit[unit]._ReallyEnabled) 
+      if (!ctx->Texture.Unit[unit]._ReallyEnabled)
 	 continue;
 
       if (ctx->TextureMatrixStack[unit].Top->type != MATRIX_IDENTITY) {
@@ -2237,21 +2237,21 @@ static void update_texturematrix( GLcontext *ctx )
 	 rmesa->TexMatCompSel |= R200_OUTPUT_TEX_0 << unit;
 
 	 if (rmesa->TexGenEnabled & (R200_TEXMAT_0_ENABLE << unit)) {
-	    /* Need to preconcatenate any active texgen 
+	    /* Need to preconcatenate any active texgen
 	     * obj/eyeplane matrices:
 	     */
 	    _math_matrix_mul_matrix( &rmesa->tmpmat,
-				     ctx->TextureMatrixStack[unit].Top, 
+				     ctx->TextureMatrixStack[unit].Top,
 				     &rmesa->TexGenMatrix[unit] );
 	    upload_matrix( rmesa, rmesa->tmpmat.m, R200_MTX_TEX0+unit );
-	 } 
+	 }
 	 else {
-	    upload_matrix( rmesa, ctx->TextureMatrixStack[unit].Top->m, 
+	    upload_matrix( rmesa, ctx->TextureMatrixStack[unit].Top->m,
 			   R200_MTX_TEX0+unit );
 	 }
       }
       else if (rmesa->TexGenEnabled & (R200_TEXMAT_0_ENABLE << unit)) {
-	 upload_matrix( rmesa, rmesa->TexGenMatrix[unit].m, 
+	 upload_matrix( rmesa, rmesa->TexGenMatrix[unit].m,
 			R200_MTX_TEX0+unit );
       }
    }
@@ -2277,7 +2277,7 @@ static GLboolean r200ValidateBuffers(GLcontext *ctx)
    int i;
 
    radeon_validate_reset_bos(&rmesa->radeon);
-   
+
    rrb = radeon_get_colorbuffer(&rmesa->radeon);
    /* color buffer */
    if (rrb && rrb->bo) {
@@ -2295,7 +2295,7 @@ static GLboolean r200ValidateBuffers(GLcontext *ctx)
 
    for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) {
       radeonTexObj *t;
-      
+
       if (!ctx->Texture.Unit[i]._ReallyEnabled)
 	 continue;
 
@@ -2323,7 +2323,7 @@ GLboolean r200ValidateState( GLcontext *ctx )
       _mesa_update_framebuffer(ctx);
       /* this updates the DrawBuffer's Width/Height if it's a FBO */
       _mesa_update_draw_buffer_bounds(ctx);
-      
+
       R200_STATECHANGE(rmesa, ctx);
    }
 
@@ -2341,7 +2341,7 @@ GLboolean r200ValidateState( GLcontext *ctx )
 
    /* Need an event driven matrix update?
     */
-   if (new_state & (_NEW_MODELVIEW|_NEW_PROJECTION)) 
+   if (new_state & (_NEW_MODELVIEW|_NEW_PROJECTION))
       upload_matrix( rmesa, ctx->_ModelProjectMatrix.m, R200_MTX_MVP );
 
    /* Need these for lighting (shouldn't upload otherwise)
@@ -2365,7 +2365,7 @@ GLboolean r200ValidateState( GLcontext *ctx )
    /* emit all active clip planes if projection matrix changes.
     */
    if (new_state & (_NEW_PROJECTION)) {
-      if (ctx->Transform.ClipPlanesEnabled) 
+      if (ctx->Transform.ClipPlanesEnabled)
 	 r200UpdateClipPlanes( ctx );
    }
 
@@ -2437,7 +2437,7 @@ static void r200WrapRunPipeline( GLcontext *ctx )
    }
 
    /* Run the pipeline.
-    */ 
+    */
    _tnl_run_pipeline( ctx );
 
    if (has_material) {
diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c
index 712da98077..83e70b586d 100644
--- a/src/mesa/drivers/dri/r200/r200_swtcl.c
+++ b/src/mesa/drivers/dri/r200/r200_swtcl.c
@@ -56,7 +56,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 
 /***********************************************************************
- *                         Initialization 
+ *                         Initialization
  ***********************************************************************/
 
 #define EMIT_ATTR( ATTR, STYLE, F0 )					\
@@ -118,7 +118,7 @@ static void r200SetVertexFormat( GLcontext *ctx )
    }
 
    rmesa->swtcl.coloroffset = offset;
-#if MESA_LITTLE_ENDIAN 
+#if MESA_LITTLE_ENDIAN
    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA, (R200_VTX_PK_RGBA << R200_VTX_COLOR_0_SHIFT) );
 #else
    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR, (R200_VTX_PK_RGBA << R200_VTX_COLOR_0_SHIFT) );
@@ -129,7 +129,7 @@ static void r200SetVertexFormat( GLcontext *ctx )
    if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 ) ||
        RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 
-#if MESA_LITTLE_ENDIAN 
+#if MESA_LITTLE_ENDIAN
       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
 	 rmesa->swtcl.specoffset = offset;
 	 EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB, (R200_VTX_PK_RGBA << R200_VTX_COLOR_1_SHIFT) );
@@ -192,7 +192,7 @@ static void r200SetVertexFormat( GLcontext *ctx )
 
       rmesa->radeon.swtcl.vertex_size =
 	  _tnl_install_attrs( ctx,
-			      rmesa->radeon.swtcl.vertex_attrs, 
+			      rmesa->radeon.swtcl.vertex_attrs,
 			      rmesa->radeon.swtcl.vertex_attr_count,
 			      NULL, 0 );
       rmesa->radeon.swtcl.vertex_size /= 4;
@@ -278,7 +278,7 @@ void r200_swtcl_flush(GLcontext *ctx, uint32_t current_offset)
 		      rmesa->radeon.dma.current,
 		      current_offset);
 
-		      
+
    r200EmitVbufPrim( rmesa,
 		     rmesa->radeon.swtcl.hw_primitive,
 		     rmesa->radeon.swtcl.numverts);
@@ -338,7 +338,7 @@ static void r200ResetLineStipple( GLcontext *ctx );
    r200ContextPtr rmesa = R200_CONTEXT(ctx);		\
    const char *r200verts = (char *)rmesa->radeon.swtcl.verts;
 #define VERT(x) (radeonVertex *)(r200verts + ((x) * vertsize * sizeof(int)))
-#define VERTEX radeonVertex 
+#define VERTEX radeonVertex
 #define DO_DEBUG_VERTS (1 && (R200_DEBUG & DEBUG_VERTS))
 
 #undef TAG
@@ -539,7 +539,7 @@ void r200ChooseRenderState( GLcontext *ctx )
    GLuint index = 0;
    GLuint flags = ctx->_TriangleCaps;
 
-   if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback) 
+   if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback)
       return;
 
    if (flags & DD_TRI_LIGHT_TWOSIDE) index |= R200_TWOSIDE_BIT;
@@ -597,7 +597,7 @@ static void r200RenderPrimitive( GLcontext *ctx, GLenum prim )
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
    rmesa->radeon.swtcl.render_primitive = prim;
-   if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED)) 
+   if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED))
       r200RasterPrimitive( ctx, reduced_hw_prim(ctx, prim) );
 }
 
@@ -695,7 +695,7 @@ void r200Fallback( GLcontext *ctx, GLuint bit, GLboolean mode )
 
 /**
  * Cope with depth operations by drawing individual pixels as points.
- * 
+ *
  * \todo
  * The way the vertex state is set in this routine is hokey.  It seems to
  * work, but it's very hackish.  This whole routine is pretty hackish.  If
@@ -710,14 +710,14 @@ r200PointsBitmap( GLcontext *ctx, GLint px, GLint py,
 		  const GLubyte *bitmap )
 {
    r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   const GLfloat *rc = ctx->Current.RasterColor; 
+   const GLfloat *rc = ctx->Current.RasterColor;
    GLint row, col;
    radeonVertex vert;
    GLuint orig_vte;
    GLuint h;
 
 
-   /* Turn off tcl.  
+   /* Turn off tcl.
     */
    TCL_FALLBACK( ctx, R200_TCL_FALLBACK_BITMAP, 1 );
 
@@ -768,7 +768,7 @@ r200PointsBitmap( GLcontext *ctx, GLint px, GLint py,
 					   R200_VPORT_Z_SCALE_ENA |
 					   R200_VPORT_X_OFFSET_ENA |
 					   R200_VPORT_Y_OFFSET_ENA |
-					   R200_VPORT_Z_OFFSET_ENA); 
+					   R200_VPORT_Z_OFFSET_ENA);
 
    /* Turn off other stuff:  Stipple?, texture?, blending?, etc.
     */
@@ -813,14 +813,14 @@ r200PointsBitmap( GLcontext *ctx, GLint px, GLint py,
     */
    LOCK_HARDWARE( &rmesa->radeon );
    UNLOCK_HARDWARE( &rmesa->radeon );
-   h = rmesa->radeon.dri.drawable->h + rmesa->radeon.dri.drawable->y;
-   px += rmesa->radeon.dri.drawable->x;
+   h = radeon_get_drawable(&rmesa->radeon)->h + radeon_get_drawable(&rmesa->radeon)->y;
+   px += radeon_get_drawable(&rmesa->radeon)->x;
 
    /* Clipping handled by existing mechansims in r200_ioctl.c?
     */
    for (row=0; row<height; row++) {
-      const GLubyte *src = (const GLubyte *) 
-	 _mesa_image_address2d(unpack, bitmap, width, height, 
+      const GLubyte *src = (const GLubyte *)
+	 _mesa_image_address2d(unpack, bitmap, width, height,
                                GL_COLOR_INDEX, GL_BITMAP, row, 0 );
 
       if (unpack->LsbFirst) {
@@ -899,9 +899,9 @@ void r200InitSwtcl( GLcontext *ctx )
    tnl->Driver.Render.Interp = _tnl_interp;
 
    /* FIXME: what are these numbers? */
-   _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12, 
+   _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
 		       36 * sizeof(GLfloat) );
-   
+
    rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf;
    rmesa->radeon.swtcl.RenderIndex = ~0;
    rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES;
diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c
index 6766eb3eae..104079b4db 100644
--- a/src/mesa/drivers/dri/r300/r300_ioctl.c
+++ b/src/mesa/drivers/dri/r300/r300_ioctl.c
@@ -79,7 +79,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags,
 {
 	BATCH_LOCALS(&r300->radeon);
 	GLcontext *ctx = r300->radeon.glCtx;
-	__DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable;
+	__DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
 	GLuint cbpitch = 0;
 	r300ContextPtr rmesa = r300;
 
@@ -200,7 +200,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags,
 		OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]);
 		OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]);
 	}
-	
+
 	r300EmitCacheFlush(rmesa);
 	cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
 
@@ -213,7 +213,7 @@ static void r300EmitClearState(GLcontext * ctx)
 {
 	r300ContextPtr r300 = R300_CONTEXT(ctx);
 	BATCH_LOCALS(&r300->radeon);
-	__DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable;
+	__DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
 	int i;
 	int has_tcl;
 	int is_r500 = 0;
@@ -447,7 +447,7 @@ static void r300EmitClearState(GLcontext * ctx)
 			R500_ALU_RGBA_G_SWIZ_0 |
 			R500_ALU_RGBA_B_SWIZ_0 |
 			R500_ALU_RGBA_A_SWIZ_0;
-		
+
 		r500fp.cmd[7] = 0;
 		emit_r500fp(ctx, &r500fp);
 	}
@@ -541,9 +541,9 @@ static void r300EmitClearState(GLcontext * ctx)
 }
 
 static void r300KernelClear(GLcontext *ctx, GLuint flags)
-{	  	
+{
 	r300ContextPtr r300 = R300_CONTEXT(ctx);
-	__DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable;
+	__DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
 	struct radeon_framebuffer *rfb = dPriv->driverPrivate;
 	struct radeon_renderbuffer *rrb;
 	struct radeon_renderbuffer *rrbd;
@@ -565,7 +565,7 @@ static void r300KernelClear(GLcontext *ctx, GLuint flags)
 		r300ClearBuffer(r300, CLEARBUFFER_COLOR, rrb, NULL);
 		bits = 0;
 	}
-		
+
 	if (flags & BUFFER_BIT_FRONT_LEFT) {
 		rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT);
 		r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
@@ -590,7 +590,7 @@ static void r300KernelClear(GLcontext *ctx, GLuint flags)
 static void r300Clear(GLcontext * ctx, GLbitfield mask)
 {
 	r300ContextPtr r300 = R300_CONTEXT(ctx);
-	__DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable;
+	__DRIdrawablePrivate *dPriv = radeon_get_drawable(&r300->radeon);
 	const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask);
 	GLbitfield swrast_mask = 0, tri_mask = 0;
 	int i;
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index efbe5cacab..582e8c27e3 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -967,7 +967,7 @@ static void r300StencilOpSeparate(GLcontext * ctx, GLenum face,
 static void r300UpdateWindow(GLcontext * ctx)
 {
 	r300ContextPtr rmesa = R300_CONTEXT(ctx);
-	__DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
+	__DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon);
 	GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
 	GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
 	const GLfloat *v = ctx->Viewport._WindowMap.m;
@@ -1020,7 +1020,7 @@ static void r300DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval)
 void r300UpdateViewportOffset(GLcontext * ctx)
 {
 	r300ContextPtr rmesa = R300_CONTEXT(ctx);
-	__DRIdrawablePrivate *dPriv = ((radeonContextPtr) rmesa)->dri.drawable;
+	__DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon);
 	GLfloat xoffset = (GLfloat) dPriv->x;
 	GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
 	const GLfloat *v = ctx->Viewport._WindowMap.m;
@@ -1052,12 +1052,14 @@ r300FetchStateParameter(GLcontext * ctx,
 	switch (state[0]) {
 	case STATE_INTERNAL:
 		switch (state[1]) {
-		case STATE_R300_WINDOW_DIMENSION:
-			value[0] = r300->radeon.dri.drawable->w * 0.5f;	/* width*0.5 */
-			value[1] = r300->radeon.dri.drawable->h * 0.5f;	/* height*0.5 */
-			value[2] = 0.5F;	/* for moving range [-1 1] -> [0 1] */
-			value[3] = 1.0F;	/* not used */
-			break;
+		case STATE_R300_WINDOW_DIMENSION: {
+				__DRIdrawablePrivate * drawable = radeon_get_drawable(&r300->radeon);
+				value[0] = drawable->w * 0.5f;	/* width*0.5 */
+				value[1] = drawable->h * 0.5f;	/* height*0.5 */
+				value[2] = 0.5F;	/* for moving range [-1 1] -> [0 1] */
+				value[3] = 1.0F;	/* not used */
+				break;
+			}
 
 		case STATE_R300_TEXRECT_FACTOR:{
 				struct gl_texture_object *t =
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c
index 76e884d705..e2e0ba07a3 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -153,7 +153,7 @@ void radeon_get_cliprects(radeonContextPtr radeon,
 			  unsigned int *num_cliprects,
 			  int *x_off, int *y_off)
 {
-	__DRIdrawablePrivate *dPriv = radeon->dri.drawable;
+	__DRIdrawablePrivate *dPriv = radeon_get_drawable(radeon);
 	struct radeon_framebuffer *rfb = dPriv->driverPrivate;
 
 	if (radeon->constant_cliprect) {
@@ -185,15 +185,15 @@ void radeon_get_cliprects(radeonContextPtr radeon,
  */
 void radeonSetCliprects(radeonContextPtr radeon)
 {
-	__DRIdrawablePrivate *const drawable = radeon->dri.drawable;
-	__DRIdrawablePrivate *const readable = radeon->dri.readable;
+	__DRIdrawablePrivate *const drawable = radeon_get_drawable(radeon);
+	__DRIdrawablePrivate *const readable = radeon_get_readable(radeon);
 	struct radeon_framebuffer *const draw_rfb = drawable->driverPrivate;
 	struct radeon_framebuffer *const read_rfb = readable->driverPrivate;
 	int x_off, y_off;
 
 	radeon_get_cliprects(radeon, &radeon->pClipRects,
 			     &radeon->numClipRects, &x_off, &y_off);
-	
+
 	if ((draw_rfb->base.Width != drawable->w) ||
 	    (draw_rfb->base.Height != drawable->h)) {
 		_mesa_resize_framebuffer(radeon->glCtx, &draw_rfb->base,
@@ -221,9 +221,9 @@ void radeonUpdateScissor( GLcontext *ctx )
 {
 	radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 
-	if ( rmesa->dri.drawable ) {
-		__DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
-      
+	if ( radeon_get_drawable(rmesa) ) {
+		__DRIdrawablePrivate *dPriv = radeon_get_drawable(rmesa);
+
 		int x = ctx->Scissor.X;
 		int y = dPriv->h - ctx->Scissor.Y - ctx->Scissor.Height;
 		int w = ctx->Scissor.X + ctx->Scissor.Width - 1;
@@ -425,11 +425,11 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv,
 	radeonContextPtr rmesa;
 	struct radeon_framebuffer *rfb;
 	GLint nbox, i, ret;
-   
+
 	assert(dPriv);
 	assert(dPriv->driContextPriv);
 	assert(dPriv->driContextPriv->driverPrivate);
-   
+
 	rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
 
 	LOCK_HARDWARE(rmesa);
@@ -506,7 +506,7 @@ static int radeonScheduleSwap(__DRIdrawablePrivate *dPriv, GLboolean *missed_tar
 
 	UNLOCK_HARDWARE(rmesa);
 	driWaitForVBlank(dPriv, missed_target);
-	
+
 	return 0;
 }
 
@@ -540,7 +540,7 @@ static GLboolean radeonPageFlip( __DRIdrawablePrivate *dPriv )
 	radeon->sarea->nbox = 1;
 
 	ret = drmCommandNone( radeon->dri.fd, DRM_RADEON_FLIP );
-	
+
 	UNLOCK_HARDWARE(radeon);
 
 	if ( ret ) {
@@ -638,7 +638,7 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
 	struct radeon_renderbuffer *rrbDepth = NULL, *rrbStencil = NULL,
 		*rrbColor = NULL;
 	uint32_t offset = 0;
-       
+
 
 	if (!fb) {
 		/* this can happen during the initial context initialization */
@@ -650,7 +650,7 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
 		radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE);
 		return;
 	}
-		
+
 	/* Do this here, note core Mesa, since this function is called from
 	 * many places within the driver.
 	 */
@@ -737,7 +737,7 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
 		ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace);
 	else
 		ctx->NewState |= _NEW_POLYGON;
-	
+
 	/*
 	 * Update depth test state
 	 */
@@ -751,7 +751,7 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
 	} else {
 		ctx->NewState |= (_NEW_DEPTH | _NEW_STENCIL);
 	}
-	
+
 	_mesa_reference_renderbuffer(&radeon->state.depth.rb, &rrbDepth->base);
 	_mesa_reference_renderbuffer(&radeon->state.color.rb, &rrbColor->base);
 	radeon->state.color.draw_offset = offset;
@@ -762,7 +762,7 @@ void radeon_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
 		ctx->Driver.Viewport(ctx, ctx->Viewport.X, ctx->Viewport.Y,
 				     ctx->Viewport.Width, ctx->Viewport.Height);
 	} else {
-	
+
 	}
 #endif
 	ctx->NewState |= _NEW_VIEWPORT;
@@ -814,7 +814,7 @@ void radeonDrawBuffer( GLcontext *ctx, GLenum mode )
 				radeon->dri.context->driDrawablePriv);
       }
 	}
-	
+
 	radeon_draw_buffer(ctx, ctx->DrawBuffer);
 }
 
@@ -836,7 +836,7 @@ void radeonReadBuffer( GLcontext *ctx, GLenum mode )
  */
 void radeonUpdatePageFlipping(radeonContextPtr radeon)
 {
-	struct radeon_framebuffer *rfb = radeon->dri.drawable->driverPrivate;
+	struct radeon_framebuffer *rfb = radeon_get_drawable(radeon)->driverPrivate;
 
 	rfb->pf_active = radeon->sarea->pfState;
 	rfb->pf_current_page = radeon->sarea->pfCurrentPage;
@@ -869,7 +869,6 @@ void radeon_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei width, GLsizei he
 
 	old_viewport = ctx->Driver.Viewport;
 	ctx->Driver.Viewport = NULL;
-	radeon->dri.drawable = driContext->driDrawablePriv;
 	radeon_window_moved(radeon);
 	radeon_draw_buffer(ctx, radeon->glCtx->DrawBuffer);
 	ctx->Driver.Viewport = old_viewport;
@@ -962,7 +961,7 @@ static INLINE void radeonEmitAtoms(radeonContextPtr radeon, GLboolean dirty)
 			}
 		}
 	}
-   
+
 	COMMIT_BATCH();
 }
 
@@ -1032,7 +1031,7 @@ void radeonEmitState(radeonContextPtr radeon)
 	if (!radeon->cmdbuf.cs->cdw) {
 		if (RADEON_DEBUG & DEBUG_STATE)
 			fprintf(stderr, "Begin reemit state\n");
-		
+
 		radeonEmitAtoms(radeon, GL_FALSE);
 	}
 
@@ -1064,7 +1063,7 @@ void radeonFlush(GLcontext *ctx)
 		radeon->dma.flush( ctx );
 
 	radeonEmitState(radeon);
-   
+
 	if (radeon->cmdbuf.cs->cdw)
 		rcommonFlushCmdBuf(radeon, __FUNCTION__);
 
@@ -1073,8 +1072,8 @@ void radeonFlush(GLcontext *ctx)
 
 		if (screen->dri2.loader && (screen->dri2.loader->base.version >= 2)
 			&& (screen->dri2.loader->flushFrontBuffer != NULL)) {
-			(*screen->dri2.loader->flushFrontBuffer)(radeon->dri.drawable,
-						  radeon->dri.drawable->loaderPrivate);
+			__DRIdrawablePrivate * drawable = radeon_get_drawable(radeon);
+			(*screen->dri2.loader->flushFrontBuffer)(drawable, drawable->loaderPrivate);
 
 			/* Only clear the dirty bit if front-buffer rendering is no longer
 			 * enabled.  This is done so that the dirty bit can only be set in
@@ -1161,7 +1160,7 @@ int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller)
 	int ret;
 
 	radeonReleaseDmaRegion(rmesa);
-	
+
 	LOCK_HARDWARE(rmesa);
 	ret = rcommonFlushCmdBufLocked(rmesa, caller);
 	UNLOCK_HARDWARE(rmesa);
@@ -1223,7 +1222,7 @@ void rcommonInitCmdBuf(radeonContextPtr rmesa)
 	rmesa->cmdbuf.cs = radeon_cs_create(rmesa->cmdbuf.csm, size);
 	assert(rmesa->cmdbuf.cs != NULL);
 	rmesa->cmdbuf.size = size;
-	
+
 	if (!rmesa->radeonScreen->kernel_mm) {
 		radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]);
 		radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, rmesa->radeonScreen->gartTextures.size);
@@ -1334,7 +1333,7 @@ void radeon_clear_tris(GLcontext *ctx, GLbitfield mask)
    unsigned int saved_active_texture;
 
    assert((mask & ~(TRI_CLEAR_COLOR_BITS | BUFFER_BIT_DEPTH |
-		    BUFFER_BIT_STENCIL)) == 0);   
+		    BUFFER_BIT_STENCIL)) == 0);
 
    _mesa_PushAttrib(GL_COLOR_BUFFER_BIT |
 		    GL_CURRENT_BIT |
@@ -1346,7 +1345,7 @@ void radeon_clear_tris(GLcontext *ctx, GLbitfield mask)
 		    GL_CURRENT_BIT);
    _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT);
    saved_active_texture = ctx->Texture.CurrentUnit;
-  
+
   /* Disable existing GL state we don't want to apply to a clear. */
    _mesa_Disable(GL_ALPHA_TEST);
    _mesa_Disable(GL_BLEND);
@@ -1375,10 +1374,10 @@ void radeon_clear_tris(GLcontext *ctx, GLbitfield mask)
       saved_shader_program = ctx->Shader.CurrentProgram->Name;
       _mesa_UseProgramObjectARB(0);
    }
-   
+
    if (ctx->Texture._EnabledUnits != 0) {
       int i;
-      
+
       for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
 	 _mesa_ActiveTextureARB(GL_TEXTURE0 + i);
 	 _mesa_Disable(GL_TEXTURE_1D);
@@ -1394,14 +1393,14 @@ void radeon_clear_tris(GLcontext *ctx, GLbitfield mask)
 	 }
       }
    }
-  
+
 #if FEATURE_ARB_vertex_buffer_object
    _mesa_BindBufferARB(GL_ARRAY_BUFFER_ARB, 0);
    _mesa_BindBufferARB(GL_ELEMENT_ARRAY_BUFFER_ARB, 0);
 #endif
 
    radeon_meta_set_passthrough_transform(rmesa);
-   
+
    for (i = 0; i < 4; i++) {
       color[i][0] = ctx->Color.ClearColor[0];
       color[i][1] = ctx->Color.ClearColor[1];
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index 622bb98f3e..e9967986a3 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -147,8 +147,6 @@ GLboolean radeonInitContext(radeonContextPtr radeon,
 	/* DRI fields */
 	radeon->dri.context = driContextPriv;
 	radeon->dri.screen = sPriv;
-	radeon->dri.drawable = NULL;
-	radeon->dri.readable = NULL;
 	radeon->dri.hwContext = driContextPriv->hHWContext;
 	radeon->dri.hwLock = &sPriv->pSAREA->lock;
 	radeon->dri.fd = sPriv->fd;
@@ -171,7 +169,7 @@ GLboolean radeonInitContext(radeonContextPtr radeon,
 			"IRQ's not enabled, falling back to %s: %d %d\n",
 			radeon->do_usleeps ? "usleeps" : "busy waits",
 			fthrottle_mode, radeon->radeonScreen->irq);
-	
+
         radeon->texture_depth = driQueryOptioni (&radeon->optionCache,
 					        "texture_depth");
         if (radeon->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
@@ -217,7 +215,7 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv )
 		radeon_firevertices(radeon);
 		_mesa_make_current(NULL, NULL, NULL);
 	}
-	
+
 	assert(radeon);
 	if (radeon) {
 
@@ -233,14 +231,11 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv )
 		_tnl_DestroyContext( radeon->glCtx );
 		_vbo_DestroyContext( radeon->glCtx );
 		_swrast_DestroyContext( radeon->glCtx );
-	
-		radeonDestroyBuffer(radeon->dri.drawable);
-		radeonDestroyBuffer(radeon->dri.readable);
 
 		/* free atom list */
 		/* free the Mesa context */
 		_mesa_destroy_context(radeon->glCtx);
-		
+
 		/* _mesa_destroy_context() might result in calls to functions that
 		 * depend on the DriverCtx, so don't set it to NULL before.
 		 *
@@ -248,7 +243,7 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv )
 		 */
 		/* free the option cache */
 		driDestroyOptionCache(&radeon->optionCache);
-		
+
 		rcommonDestroyCmdBuf(radeon);
 
 		radeon_destroy_atom_list(radeon);
@@ -346,12 +341,12 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon,
 	int size = 4096*4096*4;
 	/* if radeon->fake */
 	struct radeon_renderbuffer *rb;
-	
+
 	if (radeon->radeonScreen->kernel_mm) {
 		radeon_make_kernel_renderbuffer_current(radeon, draw);
 		return;
 	}
-			
+
 
 	if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
 		if (!rb->bo) {
@@ -440,7 +435,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 
 	if (RADEON_DEBUG & DEBUG_DRI)
 	    fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable);
-	
+
 	draw = drawable->driverPrivate;
 	screen = context->driScreenPriv;
 	radeon = (radeonContextPtr) context->driverPrivate;
@@ -493,7 +488,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 			attachments[i++] = __DRI_BUFFER_DEPTH;
 		if (radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL))
 			attachments[i++] = __DRI_BUFFER_STENCIL;
-	
+
 		buffers = (*screen->dri2.loader->getBuffers)(drawable,
 								 &drawable->w,
 								 &drawable->h,
@@ -591,7 +586,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 
 				fprintf(stderr, "failed to attach %s %d\n",
 					regname, buffers[i].name);
-				
+
 			}
 		}
 
@@ -648,7 +643,7 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
 	drfb = driDrawPriv->driverPrivate;
 	readfb = driReadPriv->driverPrivate;
 
-	if (driContextPriv->driScreenPriv->dri2.enabled) {    
+	if (driContextPriv->driScreenPriv->dri2.enabled) {
 		radeon_update_renderbuffers(driContextPriv, driDrawPriv);
 		if (driDrawPriv != driReadPriv)
 			radeon_update_renderbuffers(driContextPriv, driReadPriv);
@@ -664,9 +659,6 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
 	if (RADEON_DEBUG & DEBUG_DRI)
 	     fprintf(stderr, "%s ctx %p dfb %p rfb %p\n", __FUNCTION__, radeon->glCtx, drfb, readfb);
 
-	if (radeon->dri.readable != driReadPriv)
-		radeon->dri.readable = driReadPriv;
-
 	driUpdateFramebufferSize(radeon->glCtx, driDrawPriv);
 	if (driReadPriv != driDrawPriv)
 		driUpdateFramebufferSize(radeon->glCtx, driReadPriv);
@@ -676,29 +668,25 @@ GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
 	_mesa_update_state(radeon->glCtx);
 
 	if (radeon->glCtx->DrawBuffer == &drfb->base) {
-
-		if (radeon->dri.drawable != driDrawPriv) {
-			if (driDrawPriv->swap_interval == (unsigned)-1) {
-				int i;
-				driDrawPriv->vblFlags =
-					(radeon->radeonScreen->irq != 0)
-					? driGetDefaultVBlankFlags(&radeon->
-								   optionCache)
-					: VBLANK_FLAG_NO_IRQ;
-				    
-				driDrawableInitVBlank(driDrawPriv);
-				drfb->vbl_waited = driDrawPriv->vblSeq;
-
-				for (i = 0; i < 2; i++) {
-					if (drfb->color_rb[i])
-						drfb->color_rb[i]->vbl_pending = driDrawPriv->vblSeq;
-				}
-				    
+		if (driDrawPriv->swap_interval == (unsigned)-1) {
+			int i;
+			driDrawPriv->vblFlags =
+				(radeon->radeonScreen->irq != 0)
+				? driGetDefaultVBlankFlags(&radeon->
+							   optionCache)
+				: VBLANK_FLAG_NO_IRQ;
+
+			driDrawableInitVBlank(driDrawPriv);
+			drfb->vbl_waited = driDrawPriv->vblSeq;
+
+			for (i = 0; i < 2; i++) {
+				if (drfb->color_rb[i])
+					drfb->color_rb[i]->vbl_pending = driDrawPriv->vblSeq;
 			}
-			radeon->dri.drawable = driDrawPriv;
-			
-			radeon_window_moved(radeon);
+
 		}
+
+		radeon_window_moved(radeon);
 		radeon_draw_buffer(radeon->glCtx, &drfb->base);
 	}
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index af05f4ae32..e995062657 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -117,7 +117,7 @@ struct radeon_framebuffer
 
 };
 
- 
+
 struct radeon_colorbuffer_state {
 	GLuint clear;
 	int roundEnable;
@@ -346,16 +346,6 @@ struct radeon_dri_mirror {
 	__DRIcontextPrivate *context;	/* DRI context */
 	__DRIscreenPrivate *screen;	/* DRI screen */
 
-   /**
-    * DRI drawable bound to this context for drawing.
-    */
-	__DRIdrawablePrivate *drawable;
-
-   /**
-    * DRI drawable bound to this context for reading.
-    */
-	__DRIdrawablePrivate *readable;
-
 	drm_context_t hwContext;
 	drm_hw_lock_t *hwLock;
 	int fd;
@@ -416,7 +406,7 @@ struct radeon_cmdbuf {
 struct radeon_context {
    GLcontext *glCtx;
    radeonScreenPtr radeonScreen;	/* Screen private DRI data */
-  
+
    /* Texture object bookkeeping
     */
    int                   texture_depth;
@@ -458,7 +448,7 @@ struct radeon_context {
    driOptionCache optionCache;
 
    struct radeon_cmdbuf cmdbuf;
-	
+
   drm_clip_rect_t fboRect;
   GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */
   GLboolean front_cliprects;
@@ -507,6 +497,17 @@ struct radeon_context {
 
 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
 
+static inline __DRIdrawablePrivate* radeon_get_drawable(radeonContextPtr radeon)
+{
+	return radeon->dri.context->driDrawablePriv;
+}
+
+static inline __DRIdrawablePrivate* radeon_get_readable(radeonContextPtr radeon)
+{
+	return radeon->dri.context->driReadablePriv;
+}
+
+
 /**
  * This function takes a float and packs it into a uint32_t
  */
diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
index b5fde6d3de..caa0c4a896 100644
--- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
@@ -35,7 +35,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include <sched.h>
-#include <errno.h> 
+#include <errno.h>
 
 #include "main/attrib.h"
 #include "main/enable.h"
@@ -114,7 +114,7 @@ void radeonSetUpAtomList( r100ContextPtr rmesa )
 }
 
 /* Fire a section of the retained (indexed_verts) buffer as a regular
- * primtive.  
+ * primtive.
  */
 extern void radeonEmitVbufPrim( r100ContextPtr rmesa,
 				GLuint vertex_format,
@@ -124,7 +124,7 @@ extern void radeonEmitVbufPrim( r100ContextPtr rmesa,
    BATCH_LOCALS(&rmesa->radeon);
 
    assert(!(primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
-   
+
    radeonEmitState(&rmesa->radeon);
 
 #if RADEON_OLD_PACKETS
@@ -135,7 +135,7 @@ extern void radeonEmitVbufPrim( r100ContextPtr rmesa,
    } else {
      OUT_BATCH(rmesa->ioctl.vertex_offset);
    }
-    
+
    OUT_BATCH(vertex_nr);
    OUT_BATCH(vertex_format);
    OUT_BATCH(primitive |  RADEON_CP_VC_CNTL_PRIM_WALK_LIST |
@@ -149,10 +149,10 @@ extern void radeonEmitVbufPrim( r100ContextPtr rmesa,
 			   RADEON_GEM_DOMAIN_GTT,
 			   0, 0);
    }
-   
+
    END_BATCH();
-   
-#else   
+
+#else
    BEGIN_BATCH(4);
    OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_DRAW_VBUF, 1);
    OUT_BATCH(vertex_format);
@@ -173,7 +173,7 @@ void radeonFlushElts( GLcontext *ctx )
    int nr;
    uint32_t *cmd = (uint32_t *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_start);
    int dwords = (rmesa->radeon.cmdbuf.cs->section_ndw - rmesa->radeon.cmdbuf.cs->section_cdw);
-   
+
    if (RADEON_DEBUG & DEBUG_IOCTL)
       fprintf(stderr, "%s\n", __FUNCTION__);
 
@@ -230,9 +230,9 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
       fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive);
 
    assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
-   
+
    radeonEmitState(&rmesa->radeon);
-   
+
    rmesa->tcl.elt_cmd_start = rmesa->radeon.cmdbuf.cs->cdw;
 
    /* round up min_nr to align the state */
@@ -248,7 +248,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
    }
    OUT_BATCH(0xffff);
    OUT_BATCH(vertex_format);
-   OUT_BATCH(primitive | 
+   OUT_BATCH(primitive |
 	     RADEON_CP_VC_CNTL_PRIM_WALK_IND |
 	     RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA |
 	     RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE);
@@ -257,7 +257,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
    BEGIN_BATCH_NO_AUTOSTATE(ELTS_BUFSZ(align_min_nr)/4);
    OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_DRAW_INDX, 0);
    OUT_BATCH(vertex_format);
-   OUT_BATCH(primitive | 
+   OUT_BATCH(primitive |
 	     RADEON_CP_VC_CNTL_PRIM_WALK_IND |
 	     RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA |
 	     RADEON_CP_VC_CNTL_MAOS_ENABLE |
@@ -269,7 +269,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
    rmesa->tcl.elt_used = min_nr;
 
    retval = (GLushort *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_offset);
-   
+
    if (RADEON_DEBUG & DEBUG_PRIMS)
       fprintf(stderr, "%s: header prim %x \n",
 	      __FUNCTION__, primitive);
@@ -305,7 +305,7 @@ void radeonEmitVertexAOS( r100ContextPtr rmesa,
 
 #endif
 }
-		       
+
 
 void radeonEmitAOS( r100ContextPtr rmesa,
 		    GLuint nr,
@@ -314,7 +314,7 @@ void radeonEmitAOS( r100ContextPtr rmesa,
 #if RADEON_OLD_PACKETS
    assert( nr == 1 );
    rmesa->ioctl.bo = rmesa->radeon.tcl.aos[0].bo;
-   rmesa->ioctl.vertex_offset = 
+   rmesa->ioctl.vertex_offset =
      (rmesa->radeon.tcl.aos[0].offset + offset * rmesa->radeon.tcl.aos[0].stride * 4);
 #else
    BATCH_LOCALS(&rmesa->radeon);
@@ -336,7 +336,7 @@ void radeonEmitAOS( r100ContextPtr rmesa,
 		   (rmesa->radeon.tcl.aos[i].stride << 8) |
 		   (rmesa->radeon.tcl.aos[i + 1].components << 16) |
 		   (rmesa->radeon.tcl.aos[i + 1].stride << 24));
-			
+
 	 voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
 	    offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 	 OUT_BATCH_RELOC(voffset,
@@ -352,7 +352,7 @@ void radeonEmitAOS( r100ContextPtr rmesa,
 			 RADEON_GEM_DOMAIN_GTT,
 			 0, 0);
       }
-      
+
       if (nr & 1) {
 	 OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
 		   (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
@@ -370,7 +370,7 @@ void radeonEmitAOS( r100ContextPtr rmesa,
 		   (rmesa->radeon.tcl.aos[i].stride << 8) |
 		   (rmesa->radeon.tcl.aos[i + 1].components << 16) |
 		   (rmesa->radeon.tcl.aos[i + 1].stride << 24));
-	 
+
 	 voffset =  rmesa->radeon.tcl.aos[i + 0].offset +
 	    offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
 	 OUT_BATCH(voffset);
@@ -378,7 +378,7 @@ void radeonEmitAOS( r100ContextPtr rmesa,
 	    offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
 	 OUT_BATCH(voffset);
       }
-      
+
       if (nr & 1) {
 	 OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
 		   (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
@@ -427,7 +427,7 @@ static void radeonUserClear(GLcontext *ctx, GLuint mask)
 static void radeonKernelClear(GLcontext *ctx, GLuint flags)
 {
      r100ContextPtr rmesa = R100_CONTEXT(ctx);
-   __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
+   __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon);
    drm_radeon_sarea_t *sarea = rmesa->radeon.sarea;
    uint32_t clear;
    GLint ret, i;
@@ -529,7 +529,7 @@ static void radeonKernelClear(GLcontext *ctx, GLuint flags)
 	 depth_boxes[n].f[CLEAR_Y1] = (float)b[n].y1;
 	 depth_boxes[n].f[CLEAR_X2] = (float)b[n].x2;
 	 depth_boxes[n].f[CLEAR_Y2] = (float)b[n].y2;
-	 depth_boxes[n].f[CLEAR_DEPTH] = 
+	 depth_boxes[n].f[CLEAR_DEPTH] =
 	    (float)rmesa->radeon.state.depth.clear;
       }
 
@@ -548,7 +548,7 @@ static void radeonKernelClear(GLcontext *ctx, GLuint flags)
 static void radeonClear( GLcontext *ctx, GLbitfield mask )
 {
    r100ContextPtr rmesa = R100_CONTEXT(ctx);
-   __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
+   __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon);
    GLuint flags = 0;
    GLuint color_mask = 0;
    GLuint orig_mask = mask;
@@ -560,11 +560,11 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask )
    {
       LOCK_HARDWARE( &rmesa->radeon );
       UNLOCK_HARDWARE( &rmesa->radeon );
-      if ( dPriv->numClipRects == 0 ) 
+      if ( dPriv->numClipRects == 0 )
 	 return;
    }
-   
-   radeon_firevertices(&rmesa->radeon); 
+
+   radeon_firevertices(&rmesa->radeon);
 
    if ( mask & BUFFER_BIT_FRONT_LEFT ) {
       flags |= RADEON_FRONT;
@@ -594,12 +594,12 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask )
       _swrast_Clear( ctx, mask );
    }
 
-   if ( !flags ) 
+   if ( !flags )
       return;
 
    if (rmesa->using_hyperz) {
       flags |= RADEON_USE_COMP_ZBUF;
-/*      if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL) 
+/*      if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL)
          flags |= RADEON_USE_HIERZ; */
       if (((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&
 	    ((rmesa->radeon.state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c
index fe19218d7a..5774f7ebcf 100644
--- a/src/mesa/drivers/dri/radeon/radeon_lock.c
+++ b/src/mesa/drivers/dri/radeon/radeon_lock.c
@@ -58,8 +58,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 void radeonGetLock(radeonContextPtr rmesa, GLuint flags)
 {
-	__DRIdrawablePrivate *const drawable = rmesa->dri.drawable;
-	__DRIdrawablePrivate *const readable = rmesa->dri.readable;
+	__DRIdrawablePrivate *const drawable = radeon_get_drawable(rmesa);
+	__DRIdrawablePrivate *const readable = radeon_get_readable(rmesa);
 	__DRIscreenPrivate *sPriv = rmesa->dri.screen;
 
 	assert(drawable != NULL);
@@ -95,8 +95,8 @@ void radeon_lock_hardware(radeonContextPtr radeon)
 	struct radeon_framebuffer *rfb = NULL;
 	struct radeon_renderbuffer *rrb = NULL;
 
-	if (radeon->dri.drawable) {
-		rfb = radeon->dri.drawable->driverPrivate;
+	if (radeon_get_drawable(radeon)) {
+		rfb = radeon_get_drawable(radeon)->driverPrivate;
 
 		if (rfb)
 			rrb = radeon_get_renderbuffer(&rfb->base,
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 5aeb968d41..3ba11e848e 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -1374,6 +1374,7 @@ static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
 #endif
 
 #if !RADEON_COMMON
+	(void)screen;
 	return r100CreateContext(glVisual, driContextPriv, sharedContextPriv);
 #endif
 	return GL_FALSE;
diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c
index 34c8cb42fa..06b8c29936 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state.c
@@ -149,7 +149,7 @@ static void radeonBlendFuncSeparate( GLcontext *ctx,
 				     GLenum sfactorA, GLenum dfactorA )
 {
    r100ContextPtr rmesa = R100_CONTEXT(ctx);
-   GLuint b = rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] & 
+   GLuint b = rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] &
       ~(RADEON_SRC_BLEND_MASK | RADEON_DST_BLEND_MASK);
    GLboolean fallback = GL_FALSE;
 
@@ -392,7 +392,7 @@ static void radeonFogfv( GLcontext *ctx, GLenum pname, const GLfloat *param )
 	 rmesa->hw.fog.cmd[FOG_D] = d.i;
       }
       break;
-   case GL_FOG_COLOR: 
+   case GL_FOG_COLOR:
       RADEON_STATECHANGE( rmesa, ctx );
       UNCLAMPED_FLOAT_TO_RGB_CHAN( col, ctx->Fog.Color );
       rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] &= ~RADEON_FOG_COLOR_MASK;
@@ -495,7 +495,7 @@ static void radeonLineStipple( GLcontext *ctx, GLint factor, GLushort pattern )
    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 
    RADEON_STATECHANGE( rmesa, lin );
-   rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = 
+   rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] =
       ((((GLuint)factor & 0xff) << 16) | ((GLuint)pattern));
 }
 
@@ -558,7 +558,7 @@ static void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask )
    /* FIXME: Use window x,y offsets into stipple RAM.
     */
    stipple.mask = rmesa->state.stipple.mask;
-   drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_STIPPLE, 
+   drmCommandWrite( rmesa->radeon.dri.fd, DRM_RADEON_STIPPLE,
                     &stipple, sizeof(drm_radeon_stipple_t) );
    UNLOCK_HARDWARE( &rmesa->radeon );
 }
@@ -569,7 +569,7 @@ static void radeonPolygonMode( GLcontext *ctx, GLenum face, GLenum mode )
    GLboolean flag = (ctx->_TriangleCaps & DD_TRI_UNFILLED) != 0;
 
    /* Can't generally do unfilled via tcl, but some good special
-    * cases work. 
+    * cases work.
     */
    TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_UNFILLED, flag);
    if (rmesa->radeon.TclFallback) {
@@ -617,7 +617,7 @@ static void radeonUpdateSpecular( GLcontext *ctx )
       rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_DIFFUSE;
       rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_LIGHTING_ENABLE;
       p |=  RADEON_SPECULAR_ENABLE;
-      rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= 
+      rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &=
 	 ~RADEON_DIFFUSE_SPECULAR_COMBINE;
    }
    else if (ctx->Light.Enabled) {
@@ -647,7 +647,7 @@ static void radeonUpdateSpecular( GLcontext *ctx )
 	    RADEON_TCL_COMPUTE_SPECULAR) != 0;
       }
    }
- 
+
    TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_FOGCOORDSPEC, flag);
 
    if (NEED_SECONDARY_COLOR(ctx)) {
@@ -663,7 +663,7 @@ static void radeonUpdateSpecular( GLcontext *ctx )
 
    /* Update vertex/render formats
     */
-   if (rmesa->radeon.TclFallback) { 
+   if (rmesa->radeon.TclFallback) {
       radeonChooseRenderState( ctx );
       radeonChooseVertexState( ctx );
    }
@@ -675,7 +675,7 @@ static void radeonUpdateSpecular( GLcontext *ctx )
  */
 
 
-/* Update on colormaterial, material emmissive/ambient, 
+/* Update on colormaterial, material emmissive/ambient,
  * lightmodel.globalambient
  */
 static void update_global_ambient( GLcontext *ctx )
@@ -688,23 +688,23 @@ static void update_global_ambient( GLcontext *ctx )
     */
    if ((rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &
        ((3 << RADEON_EMISSIVE_SOURCE_SHIFT) |
-	(3 << RADEON_AMBIENT_SOURCE_SHIFT))) == 0) 
+	(3 << RADEON_AMBIENT_SOURCE_SHIFT))) == 0)
    {
-      COPY_3V( &fcmd[GLT_RED], 
+      COPY_3V( &fcmd[GLT_RED],
 	       ctx->Light.Material.Attrib[MAT_ATTRIB_FRONT_EMISSION]);
       ACC_SCALE_3V( &fcmd[GLT_RED],
 		   ctx->Light.Model.Ambient,
 		   ctx->Light.Material.Attrib[MAT_ATTRIB_FRONT_AMBIENT]);
-   } 
+   }
    else
    {
       COPY_3V( &fcmd[GLT_RED], ctx->Light.Model.Ambient );
    }
-   
+
    RADEON_DB_STATECHANGE(rmesa, &rmesa->hw.glt);
 }
 
-/* Update on change to 
+/* Update on change to
  *    - light[p].colors
  *    - light[p].enabled
  */
@@ -718,10 +718,10 @@ static void update_light_colors( GLcontext *ctx, GLuint p )
       r100ContextPtr rmesa = R100_CONTEXT(ctx);
       float *fcmd = (float *)RADEON_DB_STATE( lit[p] );
 
-      COPY_4V( &fcmd[LIT_AMBIENT_RED], l->Ambient );	 
+      COPY_4V( &fcmd[LIT_AMBIENT_RED], l->Ambient );
       COPY_4V( &fcmd[LIT_DIFFUSE_RED], l->Diffuse );
       COPY_4V( &fcmd[LIT_SPECULAR_RED], l->Specular );
-      
+
       RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.lit[p] );
    }
 }
@@ -735,7 +735,7 @@ static void check_twoside_fallback( GLcontext *ctx )
 
    if (ctx->Light.Enabled && ctx->Light.Model.TwoSide) {
       if (ctx->Light.ColorMaterialEnabled &&
-	  (ctx->Light.ColorMaterialBitmask & BACK_MATERIAL_BITS) != 
+	  (ctx->Light.ColorMaterialBitmask & BACK_MATERIAL_BITS) !=
 	  ((ctx->Light.ColorMaterialBitmask & FRONT_MATERIAL_BITS)<<1))
 	 fallback = GL_TRUE;
       else {
@@ -743,7 +743,7 @@ static void check_twoside_fallback( GLcontext *ctx )
 	    if (memcmp( ctx->Light.Material.Attrib[i],
 			ctx->Light.Material.Attrib[i+1],
 			sizeof(GLfloat)*4) != 0) {
-	       fallback = GL_TRUE;  
+	       fallback = GL_TRUE;
 	       break;
 	    }
       }
@@ -761,8 +761,8 @@ static void radeonColorMaterial( GLcontext *ctx, GLenum face, GLenum mode )
       light_model_ctl1 &= ~((3 << RADEON_EMISSIVE_SOURCE_SHIFT) |
 			   (3 << RADEON_AMBIENT_SOURCE_SHIFT) |
 			   (3 << RADEON_DIFFUSE_SOURCE_SHIFT) |
-			   (3 << RADEON_SPECULAR_SOURCE_SHIFT)); 
-   
+			   (3 << RADEON_SPECULAR_SOURCE_SHIFT));
+
    if (ctx->Light.ColorMaterialEnabled) {
       GLuint mask = ctx->Light.ColorMaterialBitmask;
 
@@ -783,7 +783,7 @@ static void radeonColorMaterial( GLcontext *ctx, GLenum face, GLenum mode )
 	 light_model_ctl1 |= (RADEON_LM_SOURCE_STATE_MULT <<
 			     RADEON_AMBIENT_SOURCE_SHIFT);
       }
-	 
+
       if (mask & MAT_BIT_FRONT_DIFFUSE) {
 	 light_model_ctl1 |= (RADEON_LM_SOURCE_VERTEX_DIFFUSE <<
 			     RADEON_DIFFUSE_SOURCE_SHIFT);
@@ -792,7 +792,7 @@ static void radeonColorMaterial( GLcontext *ctx, GLenum face, GLenum mode )
 	 light_model_ctl1 |= (RADEON_LM_SOURCE_STATE_MULT <<
 			     RADEON_DIFFUSE_SOURCE_SHIFT);
       }
-   
+
       if (mask & MAT_BIT_FRONT_SPECULAR) {
 	 light_model_ctl1 |= (RADEON_LM_SOURCE_VERTEX_DIFFUSE <<
 			     RADEON_SPECULAR_SOURCE_SHIFT);
@@ -810,10 +810,10 @@ static void radeonColorMaterial( GLcontext *ctx, GLenum face, GLenum mode )
 		   (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) |
 		   (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT);
    }
-   
+
       if (light_model_ctl1 != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL]) {
 	 RADEON_STATECHANGE( rmesa, tcl );
-	 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = light_model_ctl1;      
+	 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = light_model_ctl1;
    }
 }
 
@@ -823,14 +823,14 @@ void radeonUpdateMaterial( GLcontext *ctx )
    GLfloat (*mat)[4] = ctx->Light.Material.Attrib;
    GLfloat *fcmd = (GLfloat *)RADEON_DB_STATE( mtl );
    GLuint mask = ~0;
-   
+
    if (ctx->Light.ColorMaterialEnabled)
       mask &= ~ctx->Light.ColorMaterialBitmask;
 
    if (RADEON_DEBUG & DEBUG_STATE)
       fprintf(stderr, "%s\n", __FUNCTION__);
 
-      
+
    if (mask & MAT_BIT_FRONT_EMISSION) {
       fcmd[MTL_EMMISSIVE_RED]   = mat[MAT_ATTRIB_FRONT_EMISSION][0];
       fcmd[MTL_EMMISSIVE_GREEN] = mat[MAT_ATTRIB_FRONT_EMISSION][1];
@@ -880,7 +880,7 @@ void radeonUpdateMaterial( GLcontext *ctx )
  *
  * which are calculated in light.c and are correct for the current
  * lighting space (model or eye), hence dependencies on _NEW_MODELVIEW
- * and _MESA_NEW_NEED_EYE_COORDS.  
+ * and _MESA_NEW_NEED_EYE_COORDS.
  */
 static void update_light( GLcontext *ctx )
 {
@@ -897,12 +897,12 @@ static void update_light( GLcontext *ctx )
 	 tmp &= ~RADEON_LIGHT_IN_MODELSPACE;
       else
 	 tmp |= RADEON_LIGHT_IN_MODELSPACE;
-      
+
 
       /* Leave this test disabled: (unexplained q3 lockup) (even with
          new packets)
       */
-      if (tmp != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL]) 
+      if (tmp != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL])
       {
 	 RADEON_STATECHANGE( rmesa, tcl );
 	 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = tmp;
@@ -926,10 +926,10 @@ static void update_light( GLcontext *ctx )
 	 if (ctx->Light.Light[p].Enabled) {
 	    struct gl_light *l = &ctx->Light.Light[p];
 	    GLfloat *fcmd = (GLfloat *)RADEON_DB_STATE( lit[p] );
-	    
+
 	    if (l->EyePosition[3] == 0.0) {
-	       COPY_3FV( &fcmd[LIT_POSITION_X], l->_VP_inf_norm ); 
-	       COPY_3FV( &fcmd[LIT_DIRECTION_X], l->_h_inf_norm ); 
+	       COPY_3FV( &fcmd[LIT_POSITION_X], l->_VP_inf_norm );
+	       COPY_3FV( &fcmd[LIT_DIRECTION_X], l->_h_inf_norm );
 	       fcmd[LIT_POSITION_W] = 0;
 	       fcmd[LIT_DIRECTION_W] = 0;
 	    } else {
@@ -953,26 +953,26 @@ static void radeonLightfv( GLcontext *ctx, GLenum light,
    GLint p = light - GL_LIGHT0;
    struct gl_light *l = &ctx->Light.Light[p];
    GLfloat *fcmd = (GLfloat *)rmesa->hw.lit[p].cmd;
-   
+
 
    switch (pname) {
-   case GL_AMBIENT:		
+   case GL_AMBIENT:
    case GL_DIFFUSE:
    case GL_SPECULAR:
       update_light_colors( ctx, p );
       break;
 
-   case GL_SPOT_DIRECTION: 
-      /* picked up in update_light */	
+   case GL_SPOT_DIRECTION:
+      /* picked up in update_light */
       break;
 
    case GL_POSITION: {
-      /* positions picked up in update_light, but can do flag here */	
+      /* positions picked up in update_light, but can do flag here */
       GLuint flag;
       GLuint idx = TCL_PER_LIGHT_CTL_0 + p/2;
 
       /* FIXME: Set RANGE_ATTEN only when needed */
-      if (p&1) 
+      if (p&1)
 	 flag = RADEON_LIGHT_1_IS_LOCAL;
       else
 	 flag = RADEON_LIGHT_0_IS_LOCAL;
@@ -1064,7 +1064,7 @@ static void radeonLightfv( GLcontext *ctx, GLenum light,
    }
 }
 
-		  
+
 
 
 static void radeonLightModelfv( GLcontext *ctx, GLenum pname,
@@ -1073,7 +1073,7 @@ static void radeonLightModelfv( GLcontext *ctx, GLenum pname,
    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 
    switch (pname) {
-      case GL_LIGHT_MODEL_AMBIENT: 
+      case GL_LIGHT_MODEL_AMBIENT:
 	 update_global_ambient( ctx );
 	 break;
 
@@ -1247,14 +1247,14 @@ static void radeonStencilOpSeparate( GLcontext *ctx, GLenum face, GLenum fail,
    /* radeon 7200 have stencil bug, DEC and INC_WRAP will actually both do DEC_WRAP,
       and DEC_WRAP (and INVERT) will do INVERT. No way to get correct INC_WRAP and DEC,
       but DEC_WRAP can be fixed by using DEC and INC_WRAP at least use INC. */
-   
+
    GLuint tempRADEON_STENCIL_FAIL_DEC_WRAP;
    GLuint tempRADEON_STENCIL_FAIL_INC_WRAP;
    GLuint tempRADEON_STENCIL_ZFAIL_DEC_WRAP;
    GLuint tempRADEON_STENCIL_ZFAIL_INC_WRAP;
    GLuint tempRADEON_STENCIL_ZPASS_DEC_WRAP;
    GLuint tempRADEON_STENCIL_ZPASS_INC_WRAP;
-   
+
    if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_BROKEN_STENCIL) {
       tempRADEON_STENCIL_FAIL_DEC_WRAP = RADEON_STENCIL_FAIL_DEC;
       tempRADEON_STENCIL_FAIL_INC_WRAP = RADEON_STENCIL_FAIL_INC;
@@ -1271,7 +1271,7 @@ static void radeonStencilOpSeparate( GLcontext *ctx, GLenum face, GLenum fail,
       tempRADEON_STENCIL_ZPASS_DEC_WRAP = RADEON_STENCIL_ZPASS_DEC_WRAP;
       tempRADEON_STENCIL_ZPASS_INC_WRAP = RADEON_STENCIL_ZPASS_INC_WRAP;
    }
-   
+
    RADEON_STATECHANGE( rmesa, ctx );
    rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~(RADEON_STENCIL_FAIL_MASK |
 					       RADEON_STENCIL_ZFAIL_MASK |
@@ -1363,7 +1363,7 @@ static void radeonClearStencil( GLcontext *ctx, GLint s )
 {
    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 
-   rmesa->radeon.state.stencil.clear = 
+   rmesa->radeon.state.stencil.clear =
       ((GLuint) (ctx->Stencil.Clear & 0xff) |
        (0xff << RADEON_STENCIL_MASK_SHIFT) |
        ((ctx->Stencil.WriteMask[0] & 0xff) << RADEON_STENCIL_WRITEMASK_SHIFT));
@@ -1388,7 +1388,7 @@ static void radeonClearStencil( GLcontext *ctx, GLint s )
 void radeonUpdateWindow( GLcontext *ctx )
 {
    r100ContextPtr rmesa = R100_CONTEXT(ctx);
-   __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
+   __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon);
    GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
    GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
    const GLfloat *v = ctx->Viewport._WindowMap.m;
@@ -1443,7 +1443,7 @@ static void radeonDepthRange( GLcontext *ctx, GLclampd nearval,
 void radeonUpdateViewportOffset( GLcontext *ctx )
 {
    r100ContextPtr rmesa = R100_CONTEXT(ctx);
-   __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
+   __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon);
    GLfloat xoffset = (GLfloat)dPriv->x;
    GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h;
    const GLfloat *v = ctx->Viewport._WindowMap.m;
@@ -1473,8 +1473,8 @@ void radeonUpdateViewportOffset( GLcontext *ctx )
                 RADEON_STIPPLE_Y_OFFSET_MASK);
 
          /* add magic offsets, then invert */
-         stx = 31 - ((rmesa->radeon.dri.drawable->x - 1) & RADEON_STIPPLE_COORD_MASK);
-         sty = 31 - ((rmesa->radeon.dri.drawable->y + rmesa->radeon.dri.drawable->h - 1)
+         stx = 31 - ((dPriv->x - 1) & RADEON_STIPPLE_COORD_MASK);
+         sty = 31 - ((dPriv->y + dPriv->h - 1)
                      & RADEON_STIPPLE_COORD_MASK);
 
          m |= ((stx << RADEON_STIPPLE_X_OFFSET_SHIFT) |
@@ -1613,7 +1613,7 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state )
    case GL_CLIP_PLANE2:
    case GL_CLIP_PLANE3:
    case GL_CLIP_PLANE4:
-   case GL_CLIP_PLANE5: 
+   case GL_CLIP_PLANE5:
       p = cap-GL_CLIP_PLANE0;
       RADEON_STATECHANGE( rmesa, tcl );
       if (state) {
@@ -1678,13 +1678,13 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state )
    case GL_LIGHT7:
       RADEON_STATECHANGE(rmesa, tcl);
       p = cap - GL_LIGHT0;
-      if (p&1) 
+      if (p&1)
 	 flag = (RADEON_LIGHT_1_ENABLE |
-		 RADEON_LIGHT_1_ENABLE_AMBIENT | 
+		 RADEON_LIGHT_1_ENABLE_AMBIENT |
 		 RADEON_LIGHT_1_ENABLE_SPECULAR);
       else
 	 flag = (RADEON_LIGHT_0_ENABLE |
-		 RADEON_LIGHT_0_ENABLE_AMBIENT | 
+		 RADEON_LIGHT_0_ENABLE_AMBIENT |
 		 RADEON_LIGHT_0_ENABLE_SPECULAR);
 
       if (state)
@@ -1692,7 +1692,7 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state )
       else
 	 rmesa->hw.tcl.cmd[p/2 + TCL_PER_LIGHT_CTL_0] &= ~flag;
 
-      /* 
+      /*
        */
       update_light_colors( ctx, p );
       break;
@@ -1730,7 +1730,7 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state )
 	 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ROP_ENABLE;
       }
       break;
-      
+
    case GL_NORMALIZE:
       RADEON_STATECHANGE( rmesa, tcl );
       if ( state ) {
@@ -1830,7 +1830,7 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state )
    case GL_TEXTURE_GEN_T:
       /* Picked up in radeonUpdateTextureState.
        */
-      rmesa->recheck_texgen[ctx->Texture.CurrentUnit] = GL_TRUE; 
+      rmesa->recheck_texgen[ctx->Texture.CurrentUnit] = GL_TRUE;
       break;
 
    case GL_COLOR_SUM_EXT:
@@ -1864,7 +1864,7 @@ static void radeonLightingSpaceChange( GLcontext *ctx )
       rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_RESCALE_NORMALS;
    }
 
-   if (RADEON_DEBUG & DEBUG_STATE) 
+   if (RADEON_DEBUG & DEBUG_STATE)
       fprintf(stderr, "%s %d AFTER %x\n", __FUNCTION__, ctx->_NeedEyeCoords,
 	      rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL]);
 }
@@ -2051,7 +2051,7 @@ static GLboolean r100ValidateBuffers(GLcontext *ctx)
    int i;
 
    radeon_validate_reset_bos(&rmesa->radeon);
-   
+
    rrb = radeon_get_colorbuffer(&rmesa->radeon);
    /* color buffer */
    if (rrb && rrb->bo) {
@@ -2069,7 +2069,7 @@ static GLboolean r100ValidateBuffers(GLcontext *ctx)
 
    for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) {
       radeonTexObj *t;
-      
+
       if (!ctx->Texture.Unit[i]._ReallyEnabled)
 	 continue;
 
@@ -2112,7 +2112,7 @@ GLboolean radeonValidateState( GLcontext *ctx )
 
    /* Need an event driven matrix update?
     */
-   if (new_state & (_NEW_MODELVIEW|_NEW_PROJECTION)) 
+   if (new_state & (_NEW_MODELVIEW|_NEW_PROJECTION))
       upload_matrix( rmesa, ctx->_ModelProjectMatrix.m, MODEL_PROJ );
 
    /* Need these for lighting (shouldn't upload otherwise)
@@ -2136,7 +2136,7 @@ GLboolean radeonValidateState( GLcontext *ctx )
    /* emit all active clip planes if projection matrix changes.
     */
    if (new_state & (_NEW_PROJECTION)) {
-      if (ctx->Transform.ClipPlanesEnabled) 
+      if (ctx->Transform.ClipPlanesEnabled)
 	 radeonUpdateClipPlanes( ctx );
    }
 
@@ -2165,8 +2165,8 @@ static GLboolean check_material( GLcontext *ctx )
    TNLcontext *tnl = TNL_CONTEXT(ctx);
    GLint i;
 
-   for (i = _TNL_ATTRIB_MAT_FRONT_AMBIENT; 
-	i < _TNL_ATTRIB_MAT_BACK_INDEXES; 
+   for (i = _TNL_ATTRIB_MAT_FRONT_AMBIENT;
+	i < _TNL_ATTRIB_MAT_BACK_INDEXES;
 	i++)
       if (tnl->vb.AttribPtr[i] &&
 	  tnl->vb.AttribPtr[i]->stride)
@@ -2174,7 +2174,7 @@ static GLboolean check_material( GLcontext *ctx )
 
    return GL_FALSE;
 }
-      
+
 
 static void radeonWrapRunPipeline( GLcontext *ctx )
 {
@@ -2197,7 +2197,7 @@ static void radeonWrapRunPipeline( GLcontext *ctx )
    }
 
    /* Run the pipeline.
-    */ 
+    */
    _tnl_run_pipeline( ctx );
 
    if (has_material) {
-- 
cgit v1.2.3


From e21e82f42549aa78214f3339a13b79791406dde0 Mon Sep 17 00:00:00 2001
From: Maciej Cencora <m.cencora@gmail.com>
Date: Sun, 7 Jun 2009 21:27:52 +0200
Subject: radeon: increase max bo count

---
 src/mesa/drivers/dri/radeon/radeon_common_context.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_common_context.h')

diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index e995062657..061168fe96 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -378,7 +378,7 @@ typedef void (*radeon_line_func) (radeonContextPtr,
 
 typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
 
-#define RADEON_MAX_BOS 24
+#define RADEON_MAX_BOS 32
 struct radeon_state {
 	struct radeon_colorbuffer_state color;
 	struct radeon_depthbuffer_state depth;
-- 
cgit v1.2.3