From 3a6dd3ebb33a35779b0d5be2c8cab581a56f245a Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Wed, 27 May 2009 21:50:03 +0200 Subject: radeon: emit scissor before emiting vertices --- src/mesa/drivers/dri/radeon/radeon_ioctl.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/radeon/radeon_ioctl.c') diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 8f8878ee10..01c45df2df 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -206,8 +206,6 @@ void radeonFlushElts( GLcontext *ctx ) assert( rmesa->radeon.dma.flush == radeonFlushElts ); rmesa->radeon.dma.flush = NULL; - radeonEmitScissor(rmesa); - nr = rmesa->tcl.elt_used; #if RADEON_OLD_PACKETS @@ -260,6 +258,7 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND)); radeonEmitState(&rmesa->radeon); + radeonEmitScissor(rmesa); rmesa->tcl.elt_cmd_start = rmesa->radeon.cmdbuf.cs->cdw; @@ -280,7 +279,6 @@ GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, RADEON_CP_VC_CNTL_PRIM_WALK_IND | RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE); - #else BEGIN_BATCH_NO_AUTOSTATE(ELTS_BUFSZ(align_min_nr)/4); OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_DRAW_INDX, 0); -- cgit v1.2.3