From cb4bef7ae0b5fe8de82c380bc98f19067394d355 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 18 Apr 2009 01:58:52 +0200 Subject: r300: general cleanup - remove unused fields - remove unused defines and macros - flatten one structure --- src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 28 ++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c') diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index 34d6261706..f7c50e9949 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -61,21 +61,21 @@ static int radeon_compressed_num_bytes(GLuint mesaFormat) { int bytes = 0; switch(mesaFormat) { - + case MESA_FORMAT_RGB_FXT1: case MESA_FORMAT_RGBA_FXT1: case MESA_FORMAT_RGB_DXT1: case MESA_FORMAT_RGBA_DXT1: bytes = 2; break; - + case MESA_FORMAT_RGBA_DXT3: case MESA_FORMAT_RGBA_DXT5: bytes = 4; default: break; } - + return bytes; } @@ -97,18 +97,38 @@ static void compute_tex_image_offset(radeon_mipmap_tree *mt, lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63; lvl->size = radeon_compressed_texture_size(mt->radeon->glCtx, lvl->width, lvl->height, lvl->depth, mt->compressed); + if (lvl->size <= 0) { + int *i = 0; + *i = 0; + } + assert(lvl->size > 0); } else if (mt->target == GL_TEXTURE_RECTANGLE_NV) { lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63; lvl->size = lvl->rowstride * lvl->height; + if (lvl->size <= 0) { + int *i = 0; + *i = 0; + } + assert(lvl->size > 0); } else if (mt->tilebits & RADEON_TXO_MICRO_TILE) { /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned, * though the actual offset may be different (if texture is less than * 32 bytes width) to the untiled case */ lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31; lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth; + if (lvl->size <= 0) { + int *i = 0; + *i = 0; + } + assert(lvl->size > 0); } else { lvl->rowstride = (lvl->width * mt->bpp + 31) & ~31; lvl->size = lvl->rowstride * lvl->height * lvl->depth; + if (lvl->size <= 0) { + int *i = 0; + *i = 0; + } + assert(lvl->size > 0); } assert(lvl->size > 0); @@ -230,7 +250,7 @@ static void calculate_first_last_level(struct gl_texture_object *tObj, tObj->Image[face][level]; assert(baseImage); - + /* These must be signed values. MinLod and MaxLod can be negative numbers, * and having firstLevel and lastLevel as signed prevents the need for * extra sign checks. -- cgit v1.2.3 From bcef4b63eba3b6072df3a699d0c4d5128e2515b9 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sun, 19 Apr 2009 15:26:51 +0200 Subject: r300: revert part of cb4bef7ae0b5fe8de82c380bc98f19067394d355 Some debugging code got there by accident --- src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 28 ++++-------------------- 1 file changed, 4 insertions(+), 24 deletions(-) (limited to 'src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c') diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index f7c50e9949..34d6261706 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -61,21 +61,21 @@ static int radeon_compressed_num_bytes(GLuint mesaFormat) { int bytes = 0; switch(mesaFormat) { - + case MESA_FORMAT_RGB_FXT1: case MESA_FORMAT_RGBA_FXT1: case MESA_FORMAT_RGB_DXT1: case MESA_FORMAT_RGBA_DXT1: bytes = 2; break; - + case MESA_FORMAT_RGBA_DXT3: case MESA_FORMAT_RGBA_DXT5: bytes = 4; default: break; } - + return bytes; } @@ -97,38 +97,18 @@ static void compute_tex_image_offset(radeon_mipmap_tree *mt, lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63; lvl->size = radeon_compressed_texture_size(mt->radeon->glCtx, lvl->width, lvl->height, lvl->depth, mt->compressed); - if (lvl->size <= 0) { - int *i = 0; - *i = 0; - } - assert(lvl->size > 0); } else if (mt->target == GL_TEXTURE_RECTANGLE_NV) { lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63; lvl->size = lvl->rowstride * lvl->height; - if (lvl->size <= 0) { - int *i = 0; - *i = 0; - } - assert(lvl->size > 0); } else if (mt->tilebits & RADEON_TXO_MICRO_TILE) { /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned, * though the actual offset may be different (if texture is less than * 32 bytes width) to the untiled case */ lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31; lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth; - if (lvl->size <= 0) { - int *i = 0; - *i = 0; - } - assert(lvl->size > 0); } else { lvl->rowstride = (lvl->width * mt->bpp + 31) & ~31; lvl->size = lvl->rowstride * lvl->height * lvl->depth; - if (lvl->size <= 0) { - int *i = 0; - *i = 0; - } - assert(lvl->size > 0); } assert(lvl->size > 0); @@ -250,7 +230,7 @@ static void calculate_first_last_level(struct gl_texture_object *tObj, tObj->Image[face][level]; assert(baseImage); - + /* These must be signed values. MinLod and MaxLod can be negative numbers, * and having firstLevel and lastLevel as signed prevents the need for * extra sign checks. -- cgit v1.2.3 From 0b22615c2c860968a027c04519e25864ae69f6cd Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Sat, 2 May 2009 17:27:03 +0200 Subject: r300: set proper texture row alignment for IGP chips Looks like r400 based IGP chips require 64 byte alignment --- src/mesa/drivers/dri/r300/r300_context.c | 5 +++++ src/mesa/drivers/dri/radeon/radeon_common_context.c | 2 ++ src/mesa/drivers/dri/radeon/radeon_common_context.h | 1 + src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 11 ++++++----- 4 files changed, 14 insertions(+), 5 deletions(-) (limited to 'src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c') diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 4d1f10ba4d..70c7730be9 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -412,6 +412,11 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, if (r300->radeon.radeonScreen->kernel_mm) driInitExtensions(ctx, mm_extensions, GL_FALSE); + if (screen->chip_family == CHIP_FAMILY_RS600 || screen->chip_family == CHIP_FAMILY_RS690 || + screen->chip_family == CHIP_FAMILY_RS740) { + r300->radeon.texture_row_align = 64; + } + r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy"); diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index ba74c97f2c..3e713628ec 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -177,6 +177,8 @@ GLboolean radeonInitContext(radeonContextPtr radeon, radeon->texture_depth = ( glVisual->rgbBits > 16 ) ? DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; + radeon->texture_row_align = 32; + return GL_TRUE; } diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index d32e5af544..181688cbe4 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -421,6 +421,7 @@ struct radeon_context { */ int texture_depth; float initialMaxAnisotropy; + uint32_t texture_row_align; struct radeon_dma dma; struct radeon_hw_state hw; diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index 34d6261706..51538e37fa 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -86,10 +86,11 @@ static int radeon_compressed_num_bytes(GLuint mesaFormat) * \param curOffset points to the offset at which the image is to be stored * and is updated by this function according to the size of the image. */ -static void compute_tex_image_offset(radeon_mipmap_tree *mt, +static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree *mt, GLuint face, GLuint level, GLuint* curOffset) { radeon_mipmap_level *lvl = &mt->levels[level]; + uint32_t row_align = rmesa->texture_row_align - 1; /* Find image size in bytes */ if (mt->compressed) { @@ -107,7 +108,7 @@ static void compute_tex_image_offset(radeon_mipmap_tree *mt, lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31; lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth; } else { - lvl->rowstride = (lvl->width * mt->bpp + 31) & ~31; + lvl->rowstride = (lvl->width * mt->bpp + row_align) & ~row_align; lvl->size = lvl->rowstride * lvl->height * lvl->depth; } assert(lvl->size > 0); @@ -131,7 +132,7 @@ static GLuint minify(GLuint size, GLuint levels) return size; } -static void calculate_miptree_layout(radeon_mipmap_tree *mt) +static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt) { GLuint curOffset; GLuint numLevels; @@ -149,7 +150,7 @@ static void calculate_miptree_layout(radeon_mipmap_tree *mt) mt->levels[i].depth = minify(mt->depth0, i); for(face = 0; face < mt->faces; face++) - compute_tex_image_offset(mt, face, i, &curOffset); + compute_tex_image_offset(rmesa, mt, face, i, &curOffset); } /* Note the required size in memory */ @@ -181,7 +182,7 @@ radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, radeonTexObj * mt->tilebits = tilebits; mt->compressed = compressed; - calculate_miptree_layout(mt); + calculate_miptree_layout(rmesa, mt); mt->bo = radeon_bo_open(rmesa->radeonScreen->bom, 0, mt->totalsize, 1024, -- cgit v1.2.3 From d7f62e54055c7b8afaf0683944a4ba907b96d6ec Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 6 May 2009 14:06:13 +1000 Subject: r100/r200: try and allocate miptree correct for hw. This doesn't make things worse but according to sroland it is how the GPU hw expects things on the r100/r200 --- src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 34 +++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c') diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index 51538e37fa..8d1ba1cdba 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -132,7 +132,33 @@ static GLuint minify(GLuint size, GLuint levels) return size; } -static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt) + +static void calculate_miptree_layout_r100(radeonContextPtr rmesa, radeon_mipmap_tree *mt) +{ + GLuint curOffset; + GLuint numLevels; + GLuint i; + GLuint face; + + numLevels = mt->lastLevel - mt->firstLevel + 1; + assert(numLevels <= RADEON_MAX_TEXTURE_LEVELS); + + curOffset = 0; + for(face = 0; face < mt->faces; face++) { + + for(i = 0; i < numLevels; i++) { + mt->levels[i].width = minify(mt->width0, i); + mt->levels[i].height = minify(mt->height0, i); + mt->levels[i].depth = minify(mt->depth0, i); + compute_tex_image_offset(rmesa, mt, face, i, &curOffset); + } + } + + /* Note the required size in memory */ + mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK; +} + +static void calculate_miptree_layout_r300(radeonContextPtr rmesa, radeon_mipmap_tree *mt) { GLuint curOffset; GLuint numLevels; @@ -157,7 +183,6 @@ static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK; } - /** * Create a new mipmap tree, calculate its layout and allocate memory. */ @@ -182,7 +207,10 @@ radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, radeonTexObj * mt->tilebits = tilebits; mt->compressed = compressed; - calculate_miptree_layout(rmesa, mt); + if (rmesa->radeonScreen->chip_family >= CHIP_FAMILY_R300) + calculate_miptree_layout_r300(rmesa, mt); + else + calculate_miptree_layout_r100(rmesa, mt); mt->bo = radeon_bo_open(rmesa->radeonScreen->bom, 0, mt->totalsize, 1024, -- cgit v1.2.3 From a5d92d7ed208d20c788889640503fa61b2d38851 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 12 Jun 2009 11:35:10 +1000 Subject: radeon/r200/r300: fix max texture levels assert use the actual value set in the context --- src/mesa/drivers/dri/r300/r300_context.c | 5 +---- src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 4 ++-- 2 files changed, 3 insertions(+), 6 deletions(-) (limited to 'src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c') diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 9004a3ffab..394521a051 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -265,10 +265,7 @@ static void r300InitConstValues(GLcontext *ctx, radeonScreenPtr screen) driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units"); ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureImageUnits, ctx->Const.MaxTextureCoordUnits); - /* FIXME: When no memory manager is available we should set this - * to some reasonable value based on texture memory pool size */ - /* FIXME: r5xx limit is 4096 */ - ctx->Const.MaxTextureLevels = 12; + ctx->Const.MaxTextureMaxAnisotropy = 16.0; ctx->Const.MaxTextureLodBias = 16.0; diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index 8d1ba1cdba..55aa4502da 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -141,7 +141,7 @@ static void calculate_miptree_layout_r100(radeonContextPtr rmesa, radeon_mipmap_ GLuint face; numLevels = mt->lastLevel - mt->firstLevel + 1; - assert(numLevels <= RADEON_MAX_TEXTURE_LEVELS); + assert(numLevels <= rmesa->glCtx->Const.MaxTextureLevels); curOffset = 0; for(face = 0; face < mt->faces; face++) { @@ -165,7 +165,7 @@ static void calculate_miptree_layout_r300(radeonContextPtr rmesa, radeon_mipmap_ GLuint i; numLevels = mt->lastLevel - mt->firstLevel + 1; - assert(numLevels <= RADEON_MAX_TEXTURE_LEVELS); + assert(numLevels <= rmesa->glCtx->Const.MaxTextureLevels); curOffset = 0; for(i = 0; i < numLevels; i++) { -- cgit v1.2.3