From 33dc14c707734df37fb02b7bcc278ddeb94036f1 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Wed, 21 Jan 2009 02:10:32 +1000
Subject: radeon/r200/r300: start to move to common miptree/texobj

---
 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 319 +++++++++++++++++++++++
 1 file changed, 319 insertions(+)
 create mode 100644 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c

(limited to 'src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c')

diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
new file mode 100644
index 0000000000..955d4b71ed
--- /dev/null
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -0,0 +1,319 @@
+/*
+ * Copyright (C) 2008 Nicolai Haehnle.
+ *
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "radeon_mipmap_tree.h"
+
+#include <errno.h>
+#include <unistd.h>
+
+#include "main/simple_list.h"
+#include "main/texcompress.h"
+#include "main/texformat.h"
+
+#include "radeon_buffer.h"
+
+static GLuint radeon_compressed_texture_size(GLcontext *ctx,
+		GLsizei width, GLsizei height, GLsizei depth,
+		GLuint mesaFormat)
+{
+	GLuint size = _mesa_compressed_texture_size(ctx, width, height, depth, mesaFormat);
+
+	if (mesaFormat == MESA_FORMAT_RGB_DXT1 ||
+	    mesaFormat == MESA_FORMAT_RGBA_DXT1) {
+		if (width + 3 < 8)	/* width one block */
+			size = size * 4;
+		else if (width + 3 < 16)
+			size = size * 2;
+	} else {
+		/* DXT3/5, 16 bytes per block */
+	  //		WARN_ONCE("DXT 3/5 suffers from multitexturing problems!\n");
+		if (width + 3 < 8)
+			size = size * 2;
+	}
+
+	return size;
+}
+
+/**
+ * Compute sizes and fill in offset and blit information for the given
+ * image (determined by \p face and \p level).
+ *
+ * \param curOffset points to the offset at which the image is to be stored
+ * and is updated by this function according to the size of the image.
+ */
+static void compute_tex_image_offset(radeon_mipmap_tree *mt,
+	GLuint face, GLuint level, GLuint* curOffset)
+{
+	radeon_mipmap_level *lvl = &mt->levels[level];
+
+	/* Find image size in bytes */
+	if (mt->compressed) {
+		/* TODO: Is this correct? Need test cases for compressed textures! */
+		GLuint align;
+
+		if (mt->target == GL_TEXTURE_RECTANGLE_NV)
+			align = 64 / mt->bpp;
+		else
+			align = 32 / mt->bpp;
+		lvl->rowstride = (lvl->width + align - 1) & ~(align - 1);
+		lvl->size = radeon_compressed_texture_size(mt->radeon->glCtx,
+			lvl->width, lvl->height, lvl->depth, mt->compressed);
+	} else if (mt->target == GL_TEXTURE_RECTANGLE_NV) {
+		lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63;
+		lvl->size = lvl->rowstride * lvl->height;
+	} else if (mt->tilebits & RADEON_TXO_MICRO_TILE) {
+	  /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned,
+		 * though the actual offset may be different (if texture is less than
+		 * 32 bytes width) to the untiled case */
+		lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31;
+		lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth;
+	} else {
+		lvl->rowstride = (lvl->width * mt->bpp + 31) & ~31;
+		lvl->size = lvl->rowstride * lvl->height * lvl->depth;
+	}
+	assert(lvl->size > 0);
+
+	/* All images are aligned to a 32-byte offset */
+	*curOffset = (*curOffset + 0x1f) & ~0x1f;
+	lvl->faces[face].offset = *curOffset;
+	*curOffset += lvl->size;
+}
+
+static GLuint minify(GLuint size, GLuint levels)
+{
+	size = size >> levels;
+	if (size < 1)
+		size = 1;
+	return size;
+}
+
+static void calculate_miptree_layout(radeon_mipmap_tree *mt)
+{
+	GLuint curOffset;
+	GLuint numLevels;
+	GLuint i;
+
+	numLevels = mt->lastLevel - mt->firstLevel + 1;
+	assert(numLevels <= RADEON_MAX_TEXTURE_LEVELS);
+
+	curOffset = 0;
+	for(i = 0; i < numLevels; i++) {
+		GLuint face;
+
+		mt->levels[i].width = minify(mt->width0, i);
+		mt->levels[i].height = minify(mt->height0, i);
+		mt->levels[i].depth = minify(mt->depth0, i);
+
+		for(face = 0; face < mt->faces; face++)
+			compute_tex_image_offset(mt, face, i, &curOffset);
+	}
+
+	/* Note the required size in memory */
+	mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK;
+}
+
+
+/**
+ * Create a new mipmap tree, calculate its layout and allocate memory.
+ */
+radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, radeonTexObj *t,
+		GLenum target, GLuint firstLevel, GLuint lastLevel,
+		GLuint width0, GLuint height0, GLuint depth0,
+		GLuint bpp, GLuint tilebits, GLuint compressed)
+{
+	radeon_mipmap_tree *mt = CALLOC_STRUCT(_radeon_mipmap_tree);
+
+	mt->radeon = rmesa;
+	mt->refcount = 1;
+	mt->t = t;
+	mt->target = target;
+	mt->faces = (target == GL_TEXTURE_CUBE_MAP) ? 6 : 1;
+	mt->firstLevel = firstLevel;
+	mt->lastLevel = lastLevel;
+	mt->width0 = width0;
+	mt->height0 = height0;
+	mt->depth0 = depth0;
+	mt->bpp = bpp;
+	mt->tilebits = tilebits;
+	mt->compressed = compressed;
+
+	calculate_miptree_layout(mt);
+
+	mt->bo = radeon_bo_open(rmesa->radeonScreen->bom,
+                            0, mt->totalsize, 1024,
+                            RADEON_GEM_DOMAIN_VRAM,
+                            0);
+
+	return mt;
+}
+
+void radeon_miptree_reference(radeon_mipmap_tree *mt)
+{
+	mt->refcount++;
+	assert(mt->refcount > 0);
+}
+
+void radeon_miptree_unreference(radeon_mipmap_tree *mt)
+{
+	if (!mt)
+		return;
+
+	assert(mt->refcount > 0);
+	mt->refcount--;
+	if (!mt->refcount) {
+		radeon_bo_unref(mt->bo);
+		free(mt);
+	}
+}
+
+
+static void calculate_first_last_level(struct gl_texture_object *tObj,
+				       GLuint *pfirstLevel, GLuint *plastLevel)
+{
+	const struct gl_texture_image * const baseImage =
+		tObj->Image[0][tObj->BaseLevel];
+
+	/* These must be signed values.  MinLod and MaxLod can be negative numbers,
+	* and having firstLevel and lastLevel as signed prevents the need for
+	* extra sign checks.
+	*/
+	int   firstLevel;
+	int   lastLevel;
+
+	/* Yes, this looks overly complicated, but it's all needed.
+	*/
+	switch (tObj->Target) {
+	case GL_TEXTURE_1D:
+	case GL_TEXTURE_2D:
+	case GL_TEXTURE_3D:
+	case GL_TEXTURE_CUBE_MAP:
+		if (tObj->MinFilter == GL_NEAREST || tObj->MinFilter == GL_LINEAR) {
+			/* GL_NEAREST and GL_LINEAR only care about GL_TEXTURE_BASE_LEVEL.
+			*/
+			firstLevel = lastLevel = tObj->BaseLevel;
+		} else {
+			firstLevel = tObj->BaseLevel + (GLint)(tObj->MinLod + 0.5);
+			firstLevel = MAX2(firstLevel, tObj->BaseLevel);
+			firstLevel = MIN2(firstLevel, tObj->BaseLevel + baseImage->MaxLog2);
+			lastLevel = tObj->BaseLevel + (GLint)(tObj->MaxLod + 0.5);
+			lastLevel = MAX2(lastLevel, tObj->BaseLevel);
+			lastLevel = MIN2(lastLevel, tObj->BaseLevel + baseImage->MaxLog2);
+			lastLevel = MIN2(lastLevel, tObj->MaxLevel);
+			lastLevel = MAX2(firstLevel, lastLevel); /* need at least one level */
+		}
+		break;
+	case GL_TEXTURE_RECTANGLE_NV:
+	case GL_TEXTURE_4D_SGIS:
+		firstLevel = lastLevel = 0;
+		break;
+	default:
+		return;
+	}
+
+	/* save these values */
+	*pfirstLevel = firstLevel;
+	*plastLevel = lastLevel;
+}
+
+
+/**
+ * Checks whether the given miptree can hold the given texture image at the
+ * given face and level.
+ */
+GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt,
+		struct gl_texture_image *texImage, GLuint face, GLuint level)
+{
+	radeon_mipmap_level *lvl;
+
+	if (face >= mt->faces || level < mt->firstLevel || level > mt->lastLevel)
+		return GL_FALSE;
+
+	if (texImage->TexFormat->TexelBytes != mt->bpp)
+		return GL_FALSE;
+
+	lvl = &mt->levels[level - mt->firstLevel];
+	if (lvl->width != texImage->Width ||
+	    lvl->height != texImage->Height ||
+	    lvl->depth != texImage->Depth)
+		return GL_FALSE;
+
+	return GL_TRUE;
+}
+
+
+/**
+ * Checks whether the given miptree has the right format to store the given texture object.
+ */
+GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_texture_object *texObj)
+{
+	struct gl_texture_image *firstImage;
+	GLuint compressed;
+	GLuint numfaces = 1;
+	GLuint firstLevel, lastLevel;
+
+	calculate_first_last_level(texObj, &firstLevel, &lastLevel);
+	if (texObj->Target == GL_TEXTURE_CUBE_MAP)
+		numfaces = 6;
+
+	firstImage = texObj->Image[0][firstLevel];
+	compressed = firstImage->IsCompressed ? firstImage->TexFormat->MesaFormat : 0;
+
+	return (mt->firstLevel == firstLevel &&
+	        mt->lastLevel == lastLevel &&
+	        mt->width0 == firstImage->Width &&
+	        mt->height0 == firstImage->Height &&
+	        mt->depth0 == firstImage->Depth &&
+	        mt->bpp == firstImage->TexFormat->TexelBytes &&
+	        mt->compressed == compressed);
+}
+
+
+/**
+ * Try to allocate a mipmap tree for the given texture that will fit the
+ * given image in the given position.
+ */
+void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t,
+		struct gl_texture_image *texImage, GLuint face, GLuint level)
+{
+	GLuint compressed = texImage->IsCompressed ? texImage->TexFormat->MesaFormat : 0;
+	GLuint numfaces = 1;
+	GLuint firstLevel, lastLevel;
+
+	assert(!t->mt);
+
+	calculate_first_last_level(&t->base, &firstLevel, &lastLevel);
+	if (t->base.Target == GL_TEXTURE_CUBE_MAP)
+		numfaces = 6;
+
+	if (level != firstLevel || face >= numfaces)
+		return;
+
+	t->mt = radeon_miptree_create(rmesa, t, t->base.Target,
+		firstLevel, lastLevel,
+		texImage->Width, texImage->Height, texImage->Depth,
+		texImage->TexFormat->TexelBytes, t->tile_bits, compressed);
+}
-- 
cgit v1.2.3


From d9cf1319252e053a894dd49583064e4cd063d119 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 3 Feb 2009 09:49:45 +1000
Subject: r300: fixup mipmap + texsubimage issues

This fixes a few regression in piglit, and adds some debug to the mipmap code
---
 src/mesa/drivers/dri/r300/r300_tex.c             |  2 +-
 src/mesa/drivers/dri/r300/r300_texstate.c        |  5 +-
 src/mesa/drivers/dri/radeon/common_misc.c        | 60 +++++++++++++++++++-----
 src/mesa/drivers/dri/radeon/common_misc.h        |  2 +-
 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c |  5 ++
 5 files changed, 58 insertions(+), 16 deletions(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c')

diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c
index 11e89ffd0f..989aa462ae 100644
--- a/src/mesa/drivers/dri/r300/r300_tex.c
+++ b/src/mesa/drivers/dri/r300/r300_tex.c
@@ -334,7 +334,7 @@ void r300InitTextureFuncs(struct dd_function_table *functions)
 	functions->CompressedTexImage2D = radeonCompressedTexImage2D;
 	functions->CompressedTexSubImage2D = radeonCompressedTexSubImage2D;
 
-	functions->GenerateMipmap = radeon_generate_mipmap;
+	functions->GenerateMipmap = radeonGenerateMipmap;
 
 	driInitTextureFormats();
 }
diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c
index 7ffc15fe39..6e2b1309c5 100644
--- a/src/mesa/drivers/dri/r300/r300_texstate.c
+++ b/src/mesa/drivers/dri/r300/r300_texstate.c
@@ -225,8 +225,9 @@ static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t)
 		t->pp_txformat |= R300_TX_FORMAT_3D;
 
 	t->pp_txsize = (((firstImage->Width - 1) << R300_TX_WIDTHMASK_SHIFT)
-		| ((firstImage->Height - 1) << R300_TX_HEIGHTMASK_SHIFT))
-		| ((t->mt->lastLevel - t->mt->firstLevel) << R300_TX_MAX_MIP_LEVEL_SHIFT);
+			| ((firstImage->Height - 1) << R300_TX_HEIGHTMASK_SHIFT)
+			| ((firstImage->DepthLog2) << R300_TX_DEPTHMASK_SHIFT)
+			| ((t->mt->lastLevel - t->mt->firstLevel) << R300_TX_MAX_MIP_LEVEL_SHIFT));
 
 	if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) {
 		unsigned int align = (64 / t->mt->bpp) - 1;
diff --git a/src/mesa/drivers/dri/radeon/common_misc.c b/src/mesa/drivers/dri/radeon/common_misc.c
index bc84b67f00..162057ca9e 100644
--- a/src/mesa/drivers/dri/radeon/common_misc.c
+++ b/src/mesa/drivers/dri/radeon/common_misc.c
@@ -1476,13 +1476,42 @@ GLuint radeon_face_for_target(GLenum target)
  * This relies on internal details of _mesa_generate_mipmap, in particular
  * the fact that the memory for recreated texture images is always freed.
  */
-void radeon_generate_mipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj)
+void radeon_generate_mipmap(GLcontext *ctx, GLenum target,
+			    struct gl_texture_object *texObj)
+{
+	radeonTexObj* t = radeon_tex_obj(texObj);
+	GLuint nr_faces = (t->base.Target == GL_TEXTURE_CUBE_MAP) ? 6 : 1;
+	int i, face;
+
+
+	_mesa_generate_mipmap(ctx, target, texObj);
+
+	for (face = 0; face < nr_faces; face++) {
+		for (i = texObj->BaseLevel + 1; i < texObj->MaxLevel; i++) {
+			radeon_texture_image *image;
+
+			image = get_radeon_texture_image(texObj->Image[face][i]);
+
+			if (image == NULL)
+				break;
+
+			image->mtlevel = i;
+			image->mtface = face;
+
+			radeon_miptree_unreference(image->mt);
+			image->mt = NULL;
+		}
+	}
+	
+}
+
+void radeonGenerateMipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj)
 {
 	GLuint face = radeon_face_for_target(target);
 	radeon_texture_image *baseimage = get_radeon_texture_image(texObj->Image[face][texObj->BaseLevel]);
 
 	radeon_teximage_map(baseimage, GL_FALSE);
-	_mesa_generate_mipmap(ctx, target, texObj);
+	radeon_generate_mipmap(ctx, target, texObj);
 	radeon_teximage_unmap(baseimage);
 }
 
@@ -1803,15 +1832,17 @@ static void radeon_teximage(
 				_mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage");
 		}
 
-		radeon_teximage_unmap(image);
 	}
 
-	_mesa_unmap_teximage_pbo(ctx, packing);
-
 	/* SGIS_generate_mipmap */
 	if (level == texObj->BaseLevel && texObj->GenerateMipmap) {
-		ctx->Driver.GenerateMipmap(ctx, texObj->Target, texObj);
+		radeon_generate_mipmap(ctx, texObj->Target, texObj);
 	}
+	radeon_teximage_unmap(image);
+
+	_mesa_unmap_teximage_pbo(ctx, packing);
+
+
 }
 
 void radeonTexImage1D(GLcontext * ctx, GLenum target, GLint level,
@@ -1878,13 +1909,15 @@ static void radeon_texsubimage(GLcontext* ctx, int dims, int level,
 		const struct gl_pixelstore_attrib *packing,
 		struct gl_texture_object *texObj,
 		struct gl_texture_image *texImage,
-		int compressed)
+			       int compressed)
 {
 	radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+	radeonTexObj* t = radeon_tex_obj(texObj);
 	radeon_texture_image* image = get_radeon_texture_image(texImage);
 
 	rmesa->vtbl.flush_vertices(rmesa);
 
+	t->validated = GL_FALSE;
 	pixels = _mesa_validate_pbo_teximage(ctx, dims,
 		width, height, depth, format, type, pixels, packing, "glTexSubImage1D");
 
@@ -1896,7 +1929,7 @@ static void radeon_texsubimage(GLcontext* ctx, int dims, int level,
 			radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel];
 			dstRowStride = lvl->rowstride;
 		} else {
-			dstRowStride = texImage->Width * texImage->TexFormat->TexelBytes;
+			dstRowStride = texImage->RowStride * texImage->TexFormat->TexelBytes;
 		}
 
 		if (!texImage->TexFormat->StoreImage(ctx, dims, texImage->_BaseFormat,
@@ -1908,15 +1941,18 @@ static void radeon_texsubimage(GLcontext* ctx, int dims, int level,
 				format, type, pixels, packing))
 			_mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage");
 
-		radeon_teximage_unmap(image);
-	}
 
-	_mesa_unmap_teximage_pbo(ctx, packing);
+	}
 
 	/* GL_SGIS_generate_mipmap */
 	if (level == texObj->BaseLevel && texObj->GenerateMipmap) {
-		ctx->Driver.GenerateMipmap(ctx, texObj->Target, texObj);
+		radeon_generate_mipmap(ctx, texObj->Target, texObj);
 	}
+	radeon_teximage_unmap(image);
+
+	_mesa_unmap_teximage_pbo(ctx, packing);
+
+
 }
 
 void radeonTexSubImage1D(GLcontext * ctx, GLenum target, GLint level,
diff --git a/src/mesa/drivers/dri/radeon/common_misc.h b/src/mesa/drivers/dri/radeon/common_misc.h
index 44e464eb13..9bb1d03a09 100644
--- a/src/mesa/drivers/dri/radeon/common_misc.h
+++ b/src/mesa/drivers/dri/radeon/common_misc.h
@@ -42,7 +42,7 @@ void radeon_teximage_map(radeon_texture_image *image, GLboolean write_enable);
 void radeon_teximage_unmap(radeon_texture_image *image);
 void radeonMapTexture(GLcontext *ctx, struct gl_texture_object *texObj);
 void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj);
-void radeon_generate_mipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj);
+void radeonGenerateMipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj);
 int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj);
 GLuint radeon_face_for_target(GLenum target);
 const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx,
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index 955d4b71ed..323726c574 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -101,6 +101,11 @@ static void compute_tex_image_offset(radeon_mipmap_tree *mt,
 	*curOffset = (*curOffset + 0x1f) & ~0x1f;
 	lvl->faces[face].offset = *curOffset;
 	*curOffset += lvl->size;
+
+	if (RADEON_DEBUG & DEBUG_TEXTURE)
+	  fprintf(stderr,
+		  "level %d, face %d: rs:%d %dx%d at %d\n",
+		  level, face, lvl->rowstride, lvl->width, lvl->height, lvl->faces[face].offset);
 }
 
 static GLuint minify(GLuint size, GLuint levels)
-- 
cgit v1.2.3


From dc8a707c672918b88dd4135930bef60ed148d8ce Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 12 Feb 2009 23:52:51 +1000
Subject: radeon/r200/r300: make build with out libdrm_radeon installed for now

---
 src/mesa/drivers/dri/r200/Makefile                 |   2 +-
 src/mesa/drivers/dri/r200/r200_ioctl.h             |   2 +-
 src/mesa/drivers/dri/r200/r200_state.c             |   3 +-
 src/mesa/drivers/dri/r200/r200_swtcl.c             |   1 -
 src/mesa/drivers/dri/r300/Makefile                 |   2 +-
 src/mesa/drivers/dri/r300/r300_cmdbuf.c            |   4 +-
 src/mesa/drivers/dri/r300/r300_cmdbuf.h            |   1 -
 src/mesa/drivers/dri/r300/r300_context.c           |   2 +-
 src/mesa/drivers/dri/r300/r300_context.h           |   1 -
 src/mesa/drivers/dri/r300/r300_state.c             |   1 -
 src/mesa/drivers/dri/r300/r300_texstate.c          |   2 -
 src/mesa/drivers/dri/radeon/radeon_bo_drm.h        | 179 +++++++++++++++++++
 src/mesa/drivers/dri/radeon/radeon_bo_legacy.c     |   4 +-
 src/mesa/drivers/dri/radeon/radeon_bo_legacy.h     |   1 -
 src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h  |  35 ++++
 src/mesa/drivers/dri/radeon/radeon_buffer.h        |  49 -----
 src/mesa/drivers/dri/radeon/radeon_cmdbuf.h        |   2 +-
 src/mesa/drivers/dri/radeon/radeon_common.c        |   8 +-
 src/mesa/drivers/dri/radeon/radeon_common.h        |   1 -
 .../drivers/dri/radeon/radeon_common_context.h     |  16 ++
 src/mesa/drivers/dri/radeon/radeon_cs_drm.h        | 198 +++++++++++++++++++++
 src/mesa/drivers/dri/radeon/radeon_cs_legacy.c     |   5 +-
 src/mesa/drivers/dri/radeon/radeon_cs_legacy.h     |   1 -
 src/mesa/drivers/dri/radeon/radeon_ioctl.c         |   1 -
 src/mesa/drivers/dri/radeon/radeon_ioctl.h         |   2 +-
 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c   |   2 -
 src/mesa/drivers/dri/radeon/radeon_screen.c        |   5 +-
 src/mesa/drivers/dri/radeon/radeon_screen.h        |   1 -
 src/mesa/drivers/dri/radeon/radeon_span.c          |   2 -
 src/mesa/drivers/dri/radeon/radeon_span.h          |   2 -
 src/mesa/drivers/dri/radeon/radeon_state_init.c    |   1 -
 31 files changed, 442 insertions(+), 94 deletions(-)
 create mode 100644 src/mesa/drivers/dri/radeon/radeon_bo_drm.h
 create mode 100644 src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h
 delete mode 100644 src/mesa/drivers/dri/radeon/radeon_buffer.h
 create mode 100644 src/mesa/drivers/dri/radeon/radeon_cs_drm.h

(limited to 'src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c')

diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile
index 4f626c0584..7b5fe95577 100644
--- a/src/mesa/drivers/dri/r200/Makefile
+++ b/src/mesa/drivers/dri/r200/Makefile
@@ -62,9 +62,9 @@ COMMON_SYMLINKS = \
 	radeon_cs_legacy.c \
 	radeon_bo_legacy.h \
 	radeon_cs_legacy.h \
+	radeon_bocs_wrapper.h \
 	radeon_span.h \
 	radeon_span.c \
-	radeon_buffer.h \
 	radeon_lock.c \
 	radeon_lock.h \
 	radeon_common.c \
diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h
index 777fdc38a5..950478e762 100644
--- a/src/mesa/drivers/dri/r200/r200_ioctl.h
+++ b/src/mesa/drivers/dri/r200/r200_ioctl.h
@@ -38,7 +38,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "main/simple_list.h"
 #include "radeon_dri.h"
 
-#include "radeon_cs_legacy.h"
+#include "radeon_bocs_wrapper.h"
 
 #include "xf86drm.h"
 #include "drm.h"
diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c
index 84b0d90c69..559985bc3f 100644
--- a/src/mesa/drivers/dri/r200/r200_state.c
+++ b/src/mesa/drivers/dri/r200/r200_state.c
@@ -47,8 +47,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "tnl/t_pipeline.h"
 #include "swrast_setup/swrast_setup.h"
 
-#include "radeon_buffer.h"
-#include "radeon_cs.h"
+#include "radeon_common.h"
 #include "radeon_mipmap_tree.h"
 #include "r200_context.h"
 #include "r200_ioctl.h"
diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c
index df786561e1..b006409987 100644
--- a/src/mesa/drivers/dri/r200/r200_swtcl.c
+++ b/src/mesa/drivers/dri/r200/r200_swtcl.c
@@ -48,7 +48,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "tnl/t_context.h"
 #include "tnl/t_pipeline.h"
 
-#include "radeon_bo.h"
 #include "r200_context.h"
 #include "r200_ioctl.h"
 #include "r200_state.h"
diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile
index e9264ce77a..20ee195fe7 100644
--- a/src/mesa/drivers/dri/r300/Makefile
+++ b/src/mesa/drivers/dri/r300/Makefile
@@ -75,11 +75,11 @@ COMMON_SYMLINKS = \
 	radeon_screen.h \
 	radeon_span.h \
 	radeon_span.c \
-	radeon_buffer.h \
 	radeon_bo_legacy.c \
 	radeon_cs_legacy.c \
 	radeon_bo_legacy.h \
 	radeon_cs_legacy.h \
+	radeon_bocs_wrapper.h \
 	radeon_lock.c \
 	radeon_lock.h \
 	radeon_common.c \
diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index d6acb39d9f..29b2c2eb25 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -44,17 +44,15 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "drm.h"
 #include "radeon_drm.h"
 
-#include "radeon_buffer.h"
 #include "r300_context.h"
 #include "r300_ioctl.h"
 #include "radeon_reg.h"
 #include "r300_reg.h"
 #include "r300_cmdbuf.h"
 #include "r300_emit.h"
+#include "radeon_bocs_wrapper.h"
 #include "radeon_mipmap_tree.h"
 #include "r300_state.h"
-#include "radeon_cs_legacy.h"
-#include "radeon_cs_gem.h"
 #include "radeon_reg.h"
 
 #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h
index ab5d50f58e..b7798eb97b 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h
@@ -37,7 +37,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define __R300_CMDBUF_H__
 
 #include "r300_context.h"
-#include "radeon_cs.h"
 
 extern void r300InitCmdBuf(r300ContextPtr r300);
 extern void r300DestroyCmdBuf(r300ContextPtr r300);
diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c
index e4dc37debc..449252a930 100644
--- a/src/mesa/drivers/dri/r300/r300_context.c
+++ b/src/mesa/drivers/dri/r300/r300_context.c
@@ -63,7 +63,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "r300_tex.h"
 #include "r300_emit.h"
 #include "r300_swtcl.h"
-#include "radeon_bo_legacy.h"
+#include "radeon_bocs_wrapper.h"
 
 
 #include "vblank.h"
diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h
index 0be3657249..6d3472722d 100644
--- a/src/mesa/drivers/dri/r300/r300_context.h
+++ b/src/mesa/drivers/dri/r300/r300_context.h
@@ -43,7 +43,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "dri_util.h"
 #include "texmem.h"
 #include "radeon_common.h"
-#include "radeon_bo.h"
 
 #include "main/macros.h"
 #include "main/mtypes.h"
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index 4258a61000..fe58ac00a8 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -53,7 +53,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "vbo/vbo.h"
 #include "tnl/tnl.h"
 
-#include "radeon_buffer.h"
 #include "r300_context.h"
 #include "r300_ioctl.h"
 #include "r300_state.h"
diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c
index 50ecc570bd..e5afff0d61 100644
--- a/src/mesa/drivers/dri/r300/r300_texstate.c
+++ b/src/mesa/drivers/dri/r300/r300_texstate.c
@@ -48,10 +48,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "r300_state.h"
 #include "r300_ioctl.h"
 #include "radeon_mipmap_tree.h"
-#include "radeon_cs.h"
 #include "r300_tex.h"
 #include "r300_reg.h"
-#include "radeon_buffer.h"
 
 #define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5			\
 			   || ((f) >= MESA_FORMAT_RGBA_FLOAT32 &&	\
diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_drm.h b/src/mesa/drivers/dri/radeon/radeon_bo_drm.h
new file mode 100644
index 0000000000..3cabdfc4e8
--- /dev/null
+++ b/src/mesa/drivers/dri/radeon/radeon_bo_drm.h
@@ -0,0 +1,179 @@
+/* 
+ * Copyright © 2008 Jérôme Glisse
+ * All Rights Reserved.
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
+ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ */
+/*
+ * Authors:
+ *      Jérôme Glisse <glisse@freedesktop.org>
+ */
+#ifndef RADEON_BO_H
+#define RADEON_BO_H
+
+#include <stdio.h>
+#include <stdint.h>
+#include "radeon_track.h"
+
+/* bo object */
+#define RADEON_BO_FLAGS_MACRO_TILE  1
+#define RADEON_BO_FLAGS_MICRO_TILE  2
+
+struct radeon_bo_manager;
+
+struct radeon_bo {
+    uint32_t                    alignment;
+    uint32_t                    handle;
+    uint32_t                    size;
+    uint32_t                    domains;
+    uint32_t                    flags;
+    unsigned                    cref;
+#ifdef RADEON_BO_TRACK
+    struct radeon_track         *track;
+#endif
+    void                        *ptr;
+    struct radeon_bo_manager    *bom;
+    uint32_t                    space_accounted;
+};
+
+/* bo functions */
+struct radeon_bo_funcs {
+    struct radeon_bo *(*bo_open)(struct radeon_bo_manager *bom,
+                                 uint32_t handle,
+                                 uint32_t size,
+                                 uint32_t alignment,
+                                 uint32_t domains,
+                                 uint32_t flags);
+    void (*bo_ref)(struct radeon_bo *bo);
+    struct radeon_bo *(*bo_unref)(struct radeon_bo *bo);
+    int (*bo_map)(struct radeon_bo *bo, int write);
+    int (*bo_unmap)(struct radeon_bo *bo);
+    int (*bo_wait)(struct radeon_bo *bo);
+};
+
+struct radeon_bo_manager {
+    struct radeon_bo_funcs  *funcs;
+    int                     fd;
+    struct radeon_tracker   tracker;
+};
+    
+static inline void _radeon_bo_debug(struct radeon_bo *bo,
+                                    const char *op,
+                                    const char *file,
+                                    const char *func,
+                                    int line)
+{
+    fprintf(stderr, "%s %p 0x%08X 0x%08X 0x%08X [%s %s %d]\n",
+            op, bo, bo->handle, bo->size, bo->cref, file, func, line);
+}
+
+static inline struct radeon_bo *_radeon_bo_open(struct radeon_bo_manager *bom,
+                                                uint32_t handle,
+                                                uint32_t size,
+                                                uint32_t alignment,
+                                                uint32_t domains,
+                                                uint32_t flags,
+                                                const char *file,
+                                                const char *func,
+                                                int line)
+{
+    struct radeon_bo *bo;
+
+    bo = bom->funcs->bo_open(bom, handle, size, alignment, domains, flags);
+#ifdef RADEON_BO_TRACK
+    if (bo) {
+        bo->track = radeon_tracker_add_track(&bom->tracker, bo->handle);
+        radeon_track_add_event(bo->track, file, func, "open", line);
+    }
+#endif
+    return bo;
+}
+
+static inline void _radeon_bo_ref(struct radeon_bo *bo,
+                                  const char *file,
+                                  const char *func,
+                                  int line)
+{
+    bo->cref++;
+#ifdef RADEON_BO_TRACK
+    radeon_track_add_event(bo->track, file, func, "ref", line); 
+#endif
+    bo->bom->funcs->bo_ref(bo);
+}
+
+static inline struct radeon_bo *_radeon_bo_unref(struct radeon_bo *bo,
+                                                 const char *file,
+                                                 const char *func,
+                                                 int line)
+{
+    bo->cref--;
+#ifdef RADEON_BO_TRACK
+    radeon_track_add_event(bo->track, file, func, "unref", line);
+    if (bo->cref <= 0) {
+        radeon_tracker_remove_track(&bo->bom->tracker, bo->track);
+        bo->track = NULL;
+    }
+#endif
+    return bo->bom->funcs->bo_unref(bo);
+}
+
+static inline int _radeon_bo_map(struct radeon_bo *bo,
+                                 int write,
+                                 const char *file,
+                                 const char *func,
+                                 int line)
+{
+    return bo->bom->funcs->bo_map(bo, write);
+}
+
+static inline int _radeon_bo_unmap(struct radeon_bo *bo,
+                                   const char *file,
+                                   const char *func,
+                                   int line)
+{
+    return bo->bom->funcs->bo_unmap(bo);
+}
+
+static inline int _radeon_bo_wait(struct radeon_bo *bo,
+                                  const char *file,
+                                  const char *func,
+                                  int line)
+{
+    return bo->bom->funcs->bo_wait(bo);
+}
+
+#define radeon_bo_open(bom, h, s, a, d, f)\
+    _radeon_bo_open(bom, h, s, a, d, f, __FILE__, __FUNCTION__, __LINE__)
+#define radeon_bo_ref(bo)\
+    _radeon_bo_ref(bo, __FILE__, __FUNCTION__, __LINE__)
+#define radeon_bo_unref(bo)\
+    _radeon_bo_unref(bo, __FILE__, __FUNCTION__, __LINE__)
+#define radeon_bo_map(bo, w)\
+    _radeon_bo_map(bo, w, __FILE__, __FUNCTION__, __LINE__)
+#define radeon_bo_unmap(bo)\
+    _radeon_bo_unmap(bo, __FILE__, __FUNCTION__, __LINE__)
+#define radeon_bo_debug(bo, opcode)\
+    _radeon_bo_debug(bo, opcode, __FILE__, __FUNCTION__, __LINE__)
+#define radeon_bo_wait(bo) \
+    _radeon_bo_wait(bo, __FILE__, __func__, __LINE__)
+
+#endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
index b7658353af..1d25887e69 100644
--- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
+++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
@@ -45,9 +45,9 @@
 
 #include "drm.h"
 #include "radeon_drm.h"
-#include "radeon_bo.h"
-#include "radeon_bo_legacy.h"
 #include "radeon_common.h"
+#include "radeon_bocs_wrapper.h"
+
 
 struct bo_legacy {
     struct radeon_bo    base;
diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h
index 575979cbec..9187cd7201 100644
--- a/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h
+++ b/src/mesa/drivers/dri/radeon/radeon_bo_legacy.h
@@ -32,7 +32,6 @@
 #ifndef RADEON_BO_LEGACY_H
 #define RADEON_BO_LEGACY_H
 
-#include "radeon_bo.h"
 #include "radeon_screen.h"
 
 void radeon_bo_legacy_pending(struct radeon_bo *bo, uint32_t pending);
diff --git a/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h
new file mode 100644
index 0000000000..36dea3be7b
--- /dev/null
+++ b/src/mesa/drivers/dri/radeon/radeon_bocs_wrapper.h
@@ -0,0 +1,35 @@
+#ifndef RADEON_CS_WRAPPER_H
+#define RADEON_CS_WRAPPER_H
+
+#ifdef HAVE_LIBDRM_RADEON
+
+#include "radeon_bo.h"
+#include "radeon_bo_gem.h"
+#include "radeon_cs.h"
+#include "radeon_cs_gem.h"
+
+#else
+/* to be used to build locally in mesa with no libdrm bits */
+#include "../radeon/radeon_bo_drm.h"
+#include "../radeon/radeon_cs_drm.h"
+
+#define RADEON_GEM_DOMAIN_CPU 0x1   // Cached CPU domain
+#define RADEON_GEM_DOMAIN_GTT 0x2   // GTT or cache flushed
+#define RADEON_GEM_DOMAIN_VRAM 0x4  // VRAM domain
+
+static inline void *radeon_bo_manager_gem_ctor(int fd)
+{
+  return NULL;
+}
+
+static inline void radeon_bo_manager_gem_dtor(void *dummy)
+{
+}
+
+
+#endif
+
+#include "radeon_bo_legacy.h"
+#include "radeon_cs_legacy.h"
+
+#endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_buffer.h b/src/mesa/drivers/dri/radeon/radeon_buffer.h
deleted file mode 100644
index 62cdfad4a0..0000000000
--- a/src/mesa/drivers/dri/radeon/radeon_buffer.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright 2008 Red Hat, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software")
- * to deal in the software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * them Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTIBILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES, OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT, OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *	Adam Jackson <ajax@redhat.com>
- */
-
-#ifndef RADEON_BUFFER_H
-#define RADEON_BUFFER_H
-
-#include "radeon_bo.h"
-#include "dri_util.h"
-
-struct radeon_renderbuffer
-{
-    struct gl_renderbuffer base;
-    struct radeon_bo *bo;
-    unsigned int cpp;
-    /* unsigned int offset; */
-    unsigned int pitch;
-    unsigned int width;
-    unsigned int height;
-
-    /* boo Xorg 6.8.2 compat */
-    int has_surface;
-
-
-    __DRIdrawablePrivate *dPriv;
-};
-
-#endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h
index 5526934209..4b5116c474 100644
--- a/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h
+++ b/src/mesa/drivers/dri/radeon/radeon_cmdbuf.h
@@ -1,7 +1,7 @@
 #ifndef COMMON_CMDBUF_H
 #define COMMON_CMDBUF_H
 
-#include "radeon_cs.h"
+#include "radeon_bocs_wrapper.h"
 
 void rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *caller);
 int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller);
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c
index 87b6dac40b..80e8e0d86d 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -63,13 +63,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "vblank.h"
 
 #include "radeon_common.h"
-#include "radeon_common.h"
-#include "radeon_bo.h"
-#include "radeon_cs.h"
-#include "radeon_bo_legacy.h"
-#include "radeon_cs_legacy.h"
-#include "radeon_bo_gem.h"
-#include "radeon_cs_gem.h"
+#include "radeon_bocs_wrapper.h"
 #include "radeon_drm.h"
 #include "radeon_mipmap_tree.h"
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h
index cc9d579ea1..ead0f5551b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common.h
@@ -2,7 +2,6 @@
 #define COMMON_MISC_H
 
 #include "radeon_common_context.h"
-#include "radeon_buffer.h"
 #include "radeon_dma.h"
 #include "radeon_texture.h"
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index b88aeab051..c9be104578 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -68,6 +68,22 @@ typedef struct radeon_context *radeonContextPtr;
 #include "tnl_dd/t_dd_vertex.h"
 #undef TAG
 
+struct radeon_renderbuffer
+{
+	struct gl_renderbuffer base;
+	struct radeon_bo *bo;
+	unsigned int cpp;
+	/* unsigned int offset; */
+	unsigned int pitch;
+	unsigned int width;
+	unsigned int height;
+
+	/* boo Xorg 6.8.2 compat */
+	int has_surface;
+
+	__DRIdrawablePrivate *dPriv;
+};
+
 struct radeon_colorbuffer_state {
 	GLuint clear;
 	int roundEnable;
diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_drm.h b/src/mesa/drivers/dri/radeon/radeon_cs_drm.h
new file mode 100644
index 0000000000..7cc75d4700
--- /dev/null
+++ b/src/mesa/drivers/dri/radeon/radeon_cs_drm.h
@@ -0,0 +1,198 @@
+/* 
+ * Copyright © 2008 Nicolai Haehnle
+ * Copyright © 2008 Jérôme Glisse
+ * All Rights Reserved.
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ */
+/*
+ * Authors:
+ *      Aapo Tahkola <aet@rasterburn.org>
+ *      Nicolai Haehnle <prefect_@gmx.net>
+ *      Jérôme Glisse <glisse@freedesktop.org>
+ */
+#ifndef RADEON_CS_H
+#define RADEON_CS_H
+
+#include <stdint.h>
+#include "drm.h"
+#include "radeon_drm.h"
+#include "radeon_bo.h"
+
+struct radeon_cs_reloc {
+    struct radeon_bo    *bo;
+    uint32_t            read_domain;
+    uint32_t            write_domain;
+    uint32_t            flags;
+};
+
+
+#define RADEON_CS_SPACE_OK 0
+#define RADEON_CS_SPACE_OP_TO_BIG 1
+#define RADEON_CS_SPACE_FLUSH 2
+
+struct radeon_cs_space_check {
+    struct radeon_bo *bo;
+    uint32_t read_domains;
+    uint32_t write_domain;
+    uint32_t new_accounted;
+};
+
+struct radeon_cs_manager;
+
+struct radeon_cs {
+    struct radeon_cs_manager    *csm;
+    void                        *relocs;
+    uint32_t                    *packets;
+    unsigned                    crelocs;
+    unsigned                    relocs_total_size;
+    unsigned                    cdw;
+    unsigned                    ndw;
+    int                         section;
+    unsigned                    section_ndw;
+    unsigned                    section_cdw;
+    const char                  *section_file;
+    const char                  *section_func;
+    int                         section_line;
+
+};
+
+/* cs functions */
+struct radeon_cs_funcs {
+    struct radeon_cs *(*cs_create)(struct radeon_cs_manager *csm,
+                                   uint32_t ndw);
+    int (*cs_write_reloc)(struct radeon_cs *cs,
+                          struct radeon_bo *bo,
+                          uint32_t read_domain,
+                          uint32_t write_domain,
+                          uint32_t flags);
+    int (*cs_begin)(struct radeon_cs *cs,
+                    uint32_t ndw,
+                    const char *file,
+                    const char *func,
+                    int line);
+    int (*cs_end)(struct radeon_cs *cs,
+                  const char *file,
+                  const char *func,
+                  int line);
+    int (*cs_emit)(struct radeon_cs *cs);
+    int (*cs_destroy)(struct radeon_cs *cs);
+    int (*cs_erase)(struct radeon_cs *cs);
+    int (*cs_need_flush)(struct radeon_cs *cs);
+    void (*cs_print)(struct radeon_cs *cs, FILE *file);
+    int (*cs_space_check)(struct radeon_cs *cs, struct radeon_cs_space_check *bos,
+			  int num_bo);
+};
+
+struct radeon_cs_manager {
+    struct radeon_cs_funcs  *funcs;
+    int                     fd;
+    uint32_t vram_limit, gart_limit;
+    uint32_t vram_write_used, gart_write_used;
+    uint32_t read_used;
+};
+
+static inline struct radeon_cs *radeon_cs_create(struct radeon_cs_manager *csm,
+                                                 uint32_t ndw)
+{
+    return csm->funcs->cs_create(csm, ndw);
+}
+
+static inline int radeon_cs_write_reloc(struct radeon_cs *cs,
+                                        struct radeon_bo *bo,
+                                        uint32_t read_domain,
+                                        uint32_t write_domain,
+                                        uint32_t flags)
+{
+    return cs->csm->funcs->cs_write_reloc(cs,
+                                          bo,
+                                          read_domain,
+                                          write_domain,
+                                          flags);
+}
+
+static inline int radeon_cs_begin(struct radeon_cs *cs,
+                                  uint32_t ndw,
+                                  const char *file,
+                                  const char *func,
+                                  int line)
+{
+    return cs->csm->funcs->cs_begin(cs, ndw, file, func, line);
+}
+
+static inline int radeon_cs_end(struct radeon_cs *cs,
+                                const char *file,
+                                const char *func,
+                                int line)
+{
+    return cs->csm->funcs->cs_end(cs, file, func, line);
+}
+
+static inline int radeon_cs_emit(struct radeon_cs *cs)
+{
+    return cs->csm->funcs->cs_emit(cs);
+}
+
+static inline int radeon_cs_destroy(struct radeon_cs *cs)
+{
+    return cs->csm->funcs->cs_destroy(cs);
+}
+
+static inline int radeon_cs_erase(struct radeon_cs *cs)
+{
+    return cs->csm->funcs->cs_erase(cs);
+}
+
+static inline int radeon_cs_need_flush(struct radeon_cs *cs)
+{
+    return cs->csm->funcs->cs_need_flush(cs);
+}
+
+static inline void radeon_cs_print(struct radeon_cs *cs, FILE *file)
+{
+    cs->csm->funcs->cs_print(cs, file);
+}
+
+static inline int radeon_cs_space_check(struct radeon_cs *cs,
+					    struct radeon_cs_space_check *bos,
+					    int num_bo)
+{
+    return cs->csm->funcs->cs_space_check(cs, bos, num_bo);
+}
+
+static inline void radeon_cs_set_limit(struct radeon_cs *cs, uint32_t domain, uint32_t limit)
+{
+    
+    if (domain == RADEON_GEM_DOMAIN_VRAM)
+	cs->csm->vram_limit = limit;
+    else
+	cs->csm->gart_limit = limit;
+}
+
+static inline void radeon_cs_write_dword(struct radeon_cs *cs, uint32_t dword)
+{
+    cs->packets[cs->cdw++] = dword;
+    if (cs->section) {
+        cs->section_cdw++;
+    }
+}
+
+#endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c
index 2db3f7a68d..0f73dec1e5 100644
--- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c
+++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c
@@ -31,10 +31,7 @@
  */
 #include <errno.h>
 
-#include "radeon_cs.h"
-#include "radeon_cs_legacy.h"
-#include "radeon_bo_legacy.h"
-
+#include "radeon_bocs_wrapper.h"
 
 struct cs_manager_legacy {
     struct radeon_cs_manager    base;
diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h
index 19d904174f..e177b4bafe 100644
--- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h
+++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.h
@@ -32,7 +32,6 @@
 #ifndef RADEON_CS_LEGACY_H
 #define RADEON_CS_LEGACY_H
 
-#include "radeon_cs.h"
 #include "radeon_common.h"
 
 struct radeon_cs_manager *radeon_cs_manager_legacy_ctor(struct radeon_context *ctx);
diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
index 99b1ef332f..fb3a236d7c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
@@ -44,7 +44,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #include "radeon_context.h"
 #include "radeon_common.h"
-#include "radeon_cs.h"
 #include "radeon_state.h"
 #include "radeon_ioctl.h"
 #include "radeon_tcl.h"
diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.h b/src/mesa/drivers/dri/radeon/radeon_ioctl.h
index 6d616bf804..18805d4c57 100644
--- a/src/mesa/drivers/dri/radeon/radeon_ioctl.h
+++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.h
@@ -38,7 +38,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #include "main/simple_list.h"
 #include "radeon_lock.h"
-#include "radeon_cs_legacy.h"
+#include "radeon_bocs_wrapper.h"
 
 extern void radeonEmitVertexAOS( r100ContextPtr rmesa,
 				 GLuint vertex_size,
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index 323726c574..c21d297b22 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -34,8 +34,6 @@
 #include "main/texcompress.h"
 #include "main/texformat.h"
 
-#include "radeon_buffer.h"
-
 static GLuint radeon_compressed_texture_size(GLcontext *ctx,
 		GLsizei width, GLsizei height, GLsizei depth,
 		GLuint mesaFormat)
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 7f0d526ed2..e8cc3b25a8 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -46,7 +46,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "radeon_chipset.h"
 #include "radeon_macros.h"
 #include "radeon_screen.h"
-#include "radeon_buffer.h"
 #include "radeon_common.h"
 #include "radeon_span.h"
 #if !RADEON_COMMON
@@ -66,13 +65,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "vblank.h"
 #include "drirenderbuffer.h"
 
+#include "radeon_bocs_wrapper.h"
+
 #include "GL/internal/dri_interface.h"
 
 /* Radeon configuration
  */
 #include "xmlpool.h"
-#include "radeon_bo_legacy.h"
-#include "radeon_bo_gem.h"
 
 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h
index 3287e125f4..1c0f5bb9bc 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -46,7 +46,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "radeon_reg.h"
 #include "drm_sarea.h"
 #include "xmlconfig.h"
-#include "radeon_bo.h"
 
 
 typedef struct {
diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c
index ebd18a1634..49ec2c378e 100644
--- a/src/mesa/drivers/dri/radeon/radeon_span.c
+++ b/src/mesa/drivers/dri/radeon/radeon_span.c
@@ -47,8 +47,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "radeon_lock.h"
 #include "radeon_span.h"
 
-#include "radeon_buffer.h"
-
 #define DBG 0
 
 static GLubyte *radeon_ptr32(const struct radeon_renderbuffer * rrb,
diff --git a/src/mesa/drivers/dri/radeon/radeon_span.h b/src/mesa/drivers/dri/radeon/radeon_span.h
index dda542c8d1..dd44ab517a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_span.h
+++ b/src/mesa/drivers/dri/radeon/radeon_span.h
@@ -42,8 +42,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #ifndef __RADEON_SPAN_H__
 #define __RADEON_SPAN_H__
 
-#include "radeon_buffer.h"
-
 extern void radeonInitSpanFuncs(GLcontext * ctx);
 
 extern void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb);
diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c
index a397c0824f..fc42318017 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state_init.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c
@@ -38,7 +38,6 @@
 #include "swrast_setup/swrast_setup.h"
 
 #include "radeon_context.h"
-#include "radeon_cs.h"
 #include "radeon_mipmap_tree.h"
 #include "radeon_ioctl.h"
 #include "radeon_state.h"
-- 
cgit v1.2.3


From 9fd8da299b4a62c6baf49f08067d7c1ddebb0ffd Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Fri, 13 Feb 2009 22:49:06 +1000
Subject: radeon: fix compressed texture upload on all radeons

tested on r200, texcmp works. May need more verification
---
 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 42 ++++++++++++++----
 src/mesa/drivers/dri/radeon/radeon_texture.c     | 55 ++++++++++++++++++------
 2 files changed, 75 insertions(+), 22 deletions(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c')

diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index c21d297b22..45c1d71be5 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -56,6 +56,29 @@ static GLuint radeon_compressed_texture_size(GLcontext *ctx,
 	return size;
 }
 
+
+static int radeon_compressed_num_bytes(GLuint mesaFormat)
+{
+   int bytes = 0;
+   switch(mesaFormat) {
+     
+   case MESA_FORMAT_RGB_FXT1:
+   case MESA_FORMAT_RGBA_FXT1:
+   case MESA_FORMAT_RGB_DXT1:
+   case MESA_FORMAT_RGBA_DXT1:
+     bytes = 2;
+     break;
+     
+   case MESA_FORMAT_RGBA_DXT3:
+   case MESA_FORMAT_RGBA_DXT5:
+     bytes = 4;
+   default:
+     break;
+   }
+   
+   return bytes;
+}
+
 /**
  * Compute sizes and fill in offset and blit information for the given
  * image (determined by \p face and \p level).
@@ -73,18 +96,14 @@ static void compute_tex_image_offset(radeon_mipmap_tree *mt,
 		/* TODO: Is this correct? Need test cases for compressed textures! */
 		GLuint align;
 
-		if (mt->target == GL_TEXTURE_RECTANGLE_NV)
-			align = 64 / mt->bpp;
-		else
-			align = 32 / mt->bpp;
-		lvl->rowstride = (lvl->width + align - 1) & ~(align - 1);
+		lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63;
 		lvl->size = radeon_compressed_texture_size(mt->radeon->glCtx,
-			lvl->width, lvl->height, lvl->depth, mt->compressed);
+							   lvl->width, lvl->height, lvl->depth, mt->compressed);
 	} else if (mt->target == GL_TEXTURE_RECTANGLE_NV) {
 		lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63;
 		lvl->size = lvl->rowstride * lvl->height;
 	} else if (mt->tilebits & RADEON_TXO_MICRO_TILE) {
-	  /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned,
+		/* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned,
 		 * though the actual offset may be different (if texture is less than
 		 * 32 bytes width) to the untiled case */
 		lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31;
@@ -160,7 +179,7 @@ radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, radeonTexObj *
 	mt->width0 = width0;
 	mt->height0 = height0;
 	mt->depth0 = depth0;
-	mt->bpp = bpp;
+	mt->bpp = compressed ? radeon_compressed_num_bytes(compressed) : bpp;
 	mt->tilebits = tilebits;
 	mt->compressed = compressed;
 
@@ -255,7 +274,12 @@ GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt,
 	if (face >= mt->faces || level < mt->firstLevel || level > mt->lastLevel)
 		return GL_FALSE;
 
-	if (texImage->TexFormat->TexelBytes != mt->bpp)
+	if (texImage->IsCompressed != mt->compressed)
+		return GL_FALSE;
+
+	if (!texImage->IsCompressed &&
+	    !mt->compressed &&
+	    texImage->TexFormat->TexelBytes != mt->bpp)
 		return GL_FALSE;
 
 	lvl = &mt->levels[level - mt->firstLevel];
diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c
index beb21e7b43..eb87a0dac5 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texture.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texture.c
@@ -32,6 +32,7 @@
 #include "main/imports.h"
 #include "main/context.h"
 #include "main/mipmap.h"
+#include "main/texcompress.h"
 #include "main/texformat.h"
 #include "main/texstore.h"
 #include "main/teximage.h"
@@ -453,16 +454,26 @@ static void radeon_teximage(
 	radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 	radeonTexObj* t = radeon_tex_obj(texObj);
 	radeon_texture_image* image = get_radeon_texture_image(texImage);
+	GLuint dstRowStride;
+	GLint postConvWidth = width;
+	GLint postConvHeight = height;
+	GLuint texelBytes;
 
 	radeon_firevertices(rmesa);
 
 	t->validated = GL_FALSE;
 
+	if (ctx->_ImageTransferState & IMAGE_CONVOLUTION_BIT) {
+	       _mesa_adjust_image_for_convolution(ctx, dims, &postConvWidth,
+						  &postConvHeight);
+	}
+
 	/* Choose and fill in the texture format for this image */
 	texImage->TexFormat = radeonChooseTextureFormat(ctx, internalFormat, format, type);
 	_mesa_set_fetch_functions(texImage, dims);
 
 	if (texImage->TexFormat->TexelBytes == 0) {
+		texelBytes = 0;
 		texImage->IsCompressed = GL_TRUE;
 		texImage->CompressedSize =
 			ctx->Driver.CompressedTextureSize(ctx, texImage->Width,
@@ -471,6 +482,16 @@ static void radeon_teximage(
 	} else {
 		texImage->IsCompressed = GL_FALSE;
 		texImage->CompressedSize = 0;
+
+		texelBytes = texImage->TexFormat->TexelBytes;
+		/* Minimum pitch of 32 bytes */
+		if (postConvWidth * texelBytes < 32) {
+		  postConvWidth = 32 / texelBytes;
+		  texImage->RowStride = postConvWidth;
+		}
+		if (!image->mt) {      
+			assert(texImage->RowStride == postConvWidth);
+		}
 	}
 
 	/* Allocate memory for image */
@@ -479,16 +500,22 @@ static void radeon_teximage(
 	if (!t->mt)
 		radeon_try_alloc_miptree(rmesa, t, texImage, face, level);
 	if (t->mt && radeon_miptree_matches_image(t->mt, texImage, face, level)) {
+		radeon_mipmap_level *lvl;
 		image->mt = t->mt;
 		image->mtlevel = level - t->mt->firstLevel;
 		image->mtface = face;
 		radeon_miptree_reference(t->mt);
+		lvl = &image->mt->levels[image->mtlevel];
+		dstRowStride = lvl->rowstride;
 	} else {
 		int size;
 		if (texImage->IsCompressed) {
 			size = texImage->CompressedSize;
+			dstRowStride =
+			  _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width);
 		} else {
 			size = texImage->Width * texImage->Height * texImage->Depth * texImage->TexFormat->TexelBytes;
+			dstRowStride = postConvWidth * texelBytes;
 		}
 		texImage->Data = _mesa_alloc_texmemory(size);
 	}
@@ -509,13 +536,6 @@ static void radeon_teximage(
 		if (compressed) {
 			memcpy(texImage->Data, pixels, imageSize);
 		} else {
-			GLuint dstRowStride;
-			if (image->mt) {
-				radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel];
-				dstRowStride = lvl->rowstride;
-			} else {
-				dstRowStride = texImage->Width * texImage->TexFormat->TexelBytes;
-			}
 			if (!texImage->TexFormat->StoreImage(ctx, dims,
 						texImage->_BaseFormat,
 						texImage->TexFormat,
@@ -534,11 +554,11 @@ static void radeon_teximage(
 		radeon_generate_mipmap(ctx, texObj->Target, texObj);
 	}
 
-	if (pixels) 
-	  radeon_teximage_unmap(image);
-
 	_mesa_unmap_teximage_pbo(ctx, packing);
 
+	if (pixels)
+	  radeon_teximage_unmap(image);
+
 
 }
 
@@ -579,7 +599,7 @@ void radeonCompressedTexImage2D(GLcontext * ctx, GLenum target,
 	GLuint face = radeon_face_for_target(target);
 
 	radeon_teximage(ctx, 2, face, level, internalFormat, width, height, 1,
-		imageSize, 0, 0, data, 0, texObj, texImage, 1);
+		imageSize, 0, 0, data, &ctx->Unpack, texObj, texImage, 1);
 }
 
 void radeonTexImage3D(GLcontext * ctx, GLenum target, GLint level,
@@ -760,13 +780,22 @@ static void migrate_image_to_miptree(radeon_mipmap_tree *mt, radeon_texture_imag
 
 		radeon_miptree_unreference(image->mt);
 	} else {
-		uint srcrowstride = image->base.Width * image->base.TexFormat->TexelBytes;
+		uint32_t srcrowstride;
+		uint32_t height;
+		/* need to confirm this value is correct */
+		if (mt->compressed) {
+			height = image->base.Height / 4;
+			srcrowstride = image->base.RowStride * mt->bpp;
+		} else {
+			height = image->base.Height * image->base.Depth;
+			srcrowstride = image->base.Width * image->base.TexFormat->TexelBytes;
+		}
 
 //		if (mt->tilebits)
 //			WARN_ONCE("%s: tiling not supported yet", __FUNCTION__);
 
 		copy_rows(dest, dstlvl->rowstride, image->base.Data, srcrowstride,
-			image->base.Height * image->base.Depth, srcrowstride);
+			  height, srcrowstride);
 
 		_mesa_free_texmemory(image->base.Data);
 		image->base.Data = 0;
-- 
cgit v1.2.3


From 2d9471b28159b9af952c6a87868ff648a6055c55 Mon Sep 17 00:00:00 2001
From: Nicolai Haehnle <nhaehnle@gmail.com>
Date: Sat, 14 Feb 2009 20:45:01 +0100
Subject: r300: Fix crash in cubemap tree creation

The mip tree creation would crash if the first baselevel image to be uploaded
was not the positive-x image.

Found with Sauerbraten, also added a regression test to Piglit.

Signed-off-by: Nicolai Haehnle <nhaehnle@gmail.com>
---
 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 26 ++++++++++++++++++------
 1 file changed, 20 insertions(+), 6 deletions(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c')

diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index 45c1d71be5..3203ee1cba 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -213,12 +213,26 @@ void radeon_miptree_unreference(radeon_mipmap_tree *mt)
 }
 
 
+/**
+ * Calculate first and last mip levels for the given texture object,
+ * where the dimensions are taken from the given texture image at
+ * the given level.
+ *
+ * Note: level is the OpenGL level number, which is not necessarily the same
+ * as the first level that is actually present.
+ *
+ * The base level image of the given texture face must be non-null,
+ * or this will fail.
+ */
 static void calculate_first_last_level(struct gl_texture_object *tObj,
-				       GLuint *pfirstLevel, GLuint *plastLevel)
+				       GLuint *pfirstLevel, GLuint *plastLevel,
+				       GLuint face, GLuint level)
 {
 	const struct gl_texture_image * const baseImage =
-		tObj->Image[0][tObj->BaseLevel];
+		tObj->Image[face][level];
 
+	assert(baseImage);
+	
 	/* These must be signed values.  MinLod and MaxLod can be negative numbers,
 	* and having firstLevel and lastLevel as signed prevents the need for
 	* extra sign checks.
@@ -240,10 +254,10 @@ static void calculate_first_last_level(struct gl_texture_object *tObj,
 		} else {
 			firstLevel = tObj->BaseLevel + (GLint)(tObj->MinLod + 0.5);
 			firstLevel = MAX2(firstLevel, tObj->BaseLevel);
-			firstLevel = MIN2(firstLevel, tObj->BaseLevel + baseImage->MaxLog2);
+			firstLevel = MIN2(firstLevel, level + baseImage->MaxLog2);
 			lastLevel = tObj->BaseLevel + (GLint)(tObj->MaxLod + 0.5);
 			lastLevel = MAX2(lastLevel, tObj->BaseLevel);
-			lastLevel = MIN2(lastLevel, tObj->BaseLevel + baseImage->MaxLog2);
+			lastLevel = MIN2(lastLevel, level + baseImage->MaxLog2);
 			lastLevel = MIN2(lastLevel, tObj->MaxLevel);
 			lastLevel = MAX2(firstLevel, lastLevel); /* need at least one level */
 		}
@@ -302,7 +316,7 @@ GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_textu
 	GLuint numfaces = 1;
 	GLuint firstLevel, lastLevel;
 
-	calculate_first_last_level(texObj, &firstLevel, &lastLevel);
+	calculate_first_last_level(texObj, &firstLevel, &lastLevel, 0, texObj->BaseLevel);
 	if (texObj->Target == GL_TEXTURE_CUBE_MAP)
 		numfaces = 6;
 
@@ -332,7 +346,7 @@ void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t,
 
 	assert(!t->mt);
 
-	calculate_first_last_level(&t->base, &firstLevel, &lastLevel);
+	calculate_first_last_level(&t->base, &firstLevel, &lastLevel, face, level);
 	if (t->base.Target == GL_TEXTURE_CUBE_MAP)
 		numfaces = 6;
 
-- 
cgit v1.2.3


From 0968512f8f4abc5bce84c200bd99f8a522d56122 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Sun, 22 Mar 2009 11:56:41 +1000
Subject: radeon: add miptree offset functions

---
 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 26 ++++++++++++++++++++++++
 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h |  6 ++++--
 2 files changed, 30 insertions(+), 2 deletions(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c')

diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index 3203ee1cba..228629e3c4 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -358,3 +358,29 @@ void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t,
 		texImage->Width, texImage->Height, texImage->Depth,
 		texImage->TexFormat->TexelBytes, t->tile_bits, compressed);
 }
+
+/* Although we use the image_offset[] array to store relative offsets
+ * to cube faces, Mesa doesn't know anything about this and expects
+ * each cube face to be treated as a separate image.
+ *
+ * These functions present that view to mesa:
+ */
+const GLuint *
+radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level)
+{
+     static const GLuint zero = 0;
+     if (mt->target != GL_TEXTURE_3D || mt->faces == 1)
+       return &zero;
+     else
+       return mt->levels[level].faces[0].offset;
+}
+
+GLuint
+radeon_miptree_image_offset(radeon_mipmap_tree *mt,
+			    GLuint face, GLuint level)
+{
+   if (mt->target == GL_TEXTURE_CUBE_MAP_ARB)
+      return (mt->levels[level].faces[face].offset);
+   else
+      return mt->levels[level].faces[0].offset;
+}
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
index 43dfa48aa7..d9ad5ad39a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
@@ -92,6 +92,8 @@ GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt,
 GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_texture_object *texObj);
 void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t,
 			      struct gl_texture_image *texImage, GLuint face, GLuint level);
-
-
+GLuint radeon_miptree_image_offset(radeon_mipmap_tree *mt,
+				   GLuint face, GLuint level);
+const GLuint *
+radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level);
 #endif /* __RADEON_MIPMAP_TREE_H_ */
-- 
cgit v1.2.3


From f577c8e462fc924ea436d129ad64c8a1226b5f9c Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Tue, 24 Mar 2009 18:32:46 +1000
Subject: radeon/r200/r300: fix warnings

---
 src/mesa/drivers/dri/r200/r200_cmdbuf.c             | 15 +--------------
 src/mesa/drivers/dri/r200/r200_context.c            |  1 -
 src/mesa/drivers/dri/r200/r200_ioctl.c              |  1 -
 src/mesa/drivers/dri/r300/r300_state.c              |  6 +-----
 src/mesa/drivers/dri/radeon/radeon_common_context.c |  3 ++-
 src/mesa/drivers/dri/radeon/radeon_fbo.c            |  5 +++--
 src/mesa/drivers/dri/radeon/radeon_lock.c           |  2 --
 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c    | 16 ++++++++--------
 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h    |  3 +--
 src/mesa/drivers/dri/radeon/radeon_span.c           |  3 +--
 src/mesa/drivers/dri/radeon/radeon_swtcl.c          |  2 --
 src/mesa/drivers/dri/radeon/radeon_texstate.c       |  7 -------
 12 files changed, 17 insertions(+), 47 deletions(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c')

diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
index ae31bcb831..83375c88a7 100644
--- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c
+++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
@@ -112,7 +112,6 @@ void r200EmitVbufPrim( r200ContextPtr rmesa,
                        GLuint primitive,
                        GLuint vertex_nr )
 {
-   drm_radeon_cmd_header_t *cmd;
    BATCH_LOCALS(&rmesa->radeon);
 
    assert(!(primitive & R200_VF_PRIM_WALK_IND));
@@ -164,8 +163,7 @@ static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type)
 
 void r200FlushElts(GLcontext *ctx)
 {
-  r200ContextPtr rmesa = R200_CONTEXT(ctx);
-   int dwords;
+   r200ContextPtr rmesa = R200_CONTEXT(ctx);
    int nr, elt_used = rmesa->tcl.elt_used;
 
    if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
@@ -345,14 +343,3 @@ void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset)
    }
    END_BATCH();
 }
-
-void r200FireAOS(r200ContextPtr rmesa, int vertex_count, int type)
-{
-	BATCH_LOCALS(&rmesa->radeon);
-
-	BEGIN_BATCH(3);
-	OUT_BATCH_PACKET3(R200_CP_CMD_3D_DRAW_VBUF_2, 0);
-	OUT_BATCH(R200_VF_PRIM_WALK_LIST | (vertex_count << 16) | type);
-	END_BATCH();
-}
-
diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c
index d3898d0900..564e168290 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -243,7 +243,6 @@ static void r200_get_lock(radeonContextPtr radeon)
 {
    r200ContextPtr rmesa = (r200ContextPtr)radeon;
    drm_radeon_sarea_t *sarea = radeon->sarea;
-   int i;
 
    R200_STATECHANGE( rmesa, ctx );
    if (rmesa->radeon.sarea->tiling_enabled) {
diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c
index ccb56202f6..b8e40da475 100644
--- a/src/mesa/drivers/dri/r200/r200_ioctl.c
+++ b/src/mesa/drivers/dri/r200/r200_ioctl.c
@@ -193,7 +193,6 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask )
    __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
    GLuint flags = 0;
    GLuint color_mask = 0;
-   GLint ret;
    GLuint orig_mask = mask;
 
    if ( R200_DEBUG & DEBUG_IOCTL ) {
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index f49b43c207..6796d36d4c 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -42,6 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "main/macros.h"
 #include "main/context.h"
 #include "main/dd.h"
+#include "main/framebuffer.h"
 #include "main/simple_list.h"
 #include "main/api_arrayelt.h"
 #include "main/texformat.h"
@@ -2029,7 +2030,6 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state)
 static void r300ResetHwState(r300ContextPtr r300)
 {
 	GLcontext *ctx = r300->radeon.glCtx;
-	struct radeon_renderbuffer *rrb;
 	int has_tcl = 1;
 
 	if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
@@ -2039,7 +2039,6 @@ static void r300ResetHwState(r300ContextPtr r300)
 		fprintf(stderr, "%s\n", __FUNCTION__);
 
 	radeon_firevertices(&r300->radeon);
-	//r300UpdateWindow(ctx);
 
 	r300ColorMask(ctx,
 		      ctx->Color.ColorMask[RCOMP],
@@ -2524,9 +2523,6 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state)
  */
 void r300InitState(r300ContextPtr r300)
 {
-	GLcontext *ctx = r300->radeon.glCtx;
-	GLuint depth_fmt;
-
 	memset(&(r300->state.texture), 0, sizeof(r300->state.texture));
 
 	r300ResetHwState(r300);
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index 5b23473ab3..9964de7c7c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -36,6 +36,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "xmlpool.h"		/* for symbolic values of enum-type options */
 #include "utils.h"
 #include "vblank.h"
+#include "drirenderbuffer.h"
 #include "main/state.h"
 
 #define DRIVER_DATE "20090101"
@@ -398,7 +399,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 	struct radeon_framebuffer *draw;
 	radeonContextPtr radeon;
 	char *regname;
-	struct radeon_bo *depth_bo, *bo;
+	struct radeon_bo *depth_bo = NULL, *bo;
 
 	if (RADEON_DEBUG & DEBUG_DRI)
 	    fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable);
diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c
index 40945855d9..96ba5d3c60 100644
--- a/src/mesa/drivers/dri/radeon/radeon_fbo.c
+++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c
@@ -510,8 +510,9 @@ radeon_render_texture(GLcontext * ctx,
                                             att->TextureLevel);
 
    if (att->Texture->Target == GL_TEXTURE_3D) {
-      const GLuint *offsets = radeon_miptree_depth_offsets(radeon_image->mt,
-                                                          att->TextureLevel);
+      GLuint offsets[6];
+      radeon_miptree_depth_offsets(radeon_image->mt, att->TextureLevel,
+				   offsets);
       imageOffset += offsets[att->Zoffset];
    }
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c
index e1bb2cd6e2..fe19218d7a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_lock.c
+++ b/src/mesa/drivers/dri/radeon/radeon_lock.c
@@ -61,7 +61,6 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags)
 	__DRIdrawablePrivate *const drawable = rmesa->dri.drawable;
 	__DRIdrawablePrivate *const readable = rmesa->dri.readable;
 	__DRIscreenPrivate *sPriv = rmesa->dri.screen;
-	drm_radeon_sarea_t *sarea = rmesa->sarea;
 
 	assert(drawable != NULL);
 
@@ -92,7 +91,6 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags)
 
 void radeon_lock_hardware(radeonContextPtr radeon)
 {
-	__DRIdrawable *dPriv = radeon->dri.drawable;
 	char ret = 0;
 	struct radeon_framebuffer *rfb = NULL;
 	struct radeon_renderbuffer *rrb = NULL;
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index 228629e3c4..34d6261706 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -94,8 +94,6 @@ static void compute_tex_image_offset(radeon_mipmap_tree *mt,
 	/* Find image size in bytes */
 	if (mt->compressed) {
 		/* TODO: Is this correct? Need test cases for compressed textures! */
-		GLuint align;
-
 		lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63;
 		lvl->size = radeon_compressed_texture_size(mt->radeon->glCtx,
 							   lvl->width, lvl->height, lvl->depth, mt->compressed);
@@ -365,14 +363,16 @@ void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t,
  *
  * These functions present that view to mesa:
  */
-const GLuint *
-radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level)
+void
+radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level, GLuint *offsets)
 {
-     static const GLuint zero = 0;
      if (mt->target != GL_TEXTURE_3D || mt->faces == 1)
-       return &zero;
-     else
-       return mt->levels[level].faces[0].offset;
+        offsets[0] = 0;
+     else {
+	int i;
+	for (i = 0; i < 6; i++)
+		offsets[i] = mt->levels[level].faces[i].offset;
+     }
 }
 
 GLuint
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
index d9ad5ad39a..697010bc02 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
@@ -94,6 +94,5 @@ void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t,
 			      struct gl_texture_image *texImage, GLuint face, GLuint level);
 GLuint radeon_miptree_image_offset(radeon_mipmap_tree *mt,
 				   GLuint face, GLuint level);
-const GLuint *
-radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level);
+void radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level, GLuint *offsets);
 #endif /* __RADEON_MIPMAP_TREE_H_ */
diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c
index 3d2c5da4c0..0b4eaae02b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_span.c
+++ b/src/mesa/drivers/dri/radeon/radeon_span.c
@@ -377,7 +377,7 @@ do {									\
 #include "stenciltmp.h"
 
 
-void map_unmap_rb(struct gl_renderbuffer *rb, int flag)
+static void map_unmap_rb(struct gl_renderbuffer *rb, int flag)
 {
 	struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
 	int r;
@@ -403,7 +403,6 @@ void map_unmap_rb(struct gl_renderbuffer *rb, int flag)
 static void
 radeon_map_unmap_buffers(GLcontext *ctx, GLboolean map)
 {
-	radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 	GLuint i, j;
 
 	/* color draw buffers */
diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c b/src/mesa/drivers/dri/radeon/radeon_swtcl.c
index af933a35f2..2484006f1c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c
@@ -825,6 +825,4 @@ void radeonInitSwtcl( GLcontext *ctx )
 
 void radeonDestroySwtcl( GLcontext *ctx )
 {
-   r100ContextPtr rmesa = R100_CONTEXT(ctx);
-
 }
diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c
index 78e2a08559..9931f01b63 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texstate.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c
@@ -775,11 +775,6 @@ void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPri
 static void disable_tex_obj_state( r100ContextPtr rmesa, 
 				   int unit )
 {
-   /* do not use RADEON_DB_STATE to avoid stale texture caches */
-   uint32_t *cmd = &rmesa->hw.tex[unit].cmd[TEX_CMD_0];
-   GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
-   GLuint *txr_cmd = RADEON_DB_STATE( txr[unit] );
-
    RADEON_STATECHANGE( rmesa, tex[unit] );
 
    RADEON_STATECHANGE( rmesa, tcl );
@@ -1142,8 +1137,6 @@ static GLboolean radeon_validate_texture(GLcontext *ctx, struct gl_texture_objec
 static GLboolean radeonUpdateTextureUnit( GLcontext *ctx, int unit )
 {
    r100ContextPtr rmesa = R100_CONTEXT(ctx);
-   struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
-
 
    if (ctx->Texture.Unit[unit]._ReallyEnabled & TEXTURE_3D_BIT) {
      return GL_FALSE;
-- 
cgit v1.2.3


From cb4bef7ae0b5fe8de82c380bc98f19067394d355 Mon Sep 17 00:00:00 2001
From: Maciej Cencora <m.cencora@gmail.com>
Date: Sat, 18 Apr 2009 01:58:52 +0200
Subject: r300: general cleanup

- remove unused fields
- remove unused defines and macros
- flatten one structure
---
 src/mesa/drivers/dri/r300/r300_context.h         | 41 ++++--------------------
 src/mesa/drivers/dri/r300/r300_emit.c            |  9 ++----
 src/mesa/drivers/dri/r300/r300_state.c           | 16 ++++-----
 src/mesa/drivers/dri/r300/r300_swtcl.c           |  2 +-
 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 28 +++++++++++++---
 5 files changed, 41 insertions(+), 55 deletions(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c')

diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h
index 602f86ba66..c3d91187a7 100644
--- a/src/mesa/drivers/dri/r300/r300_context.h
+++ b/src/mesa/drivers/dri/r300/r300_context.h
@@ -37,24 +37,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #ifndef __R300_CONTEXT_H__
 #define __R300_CONTEXT_H__
 
-#include "tnl/t_vertex.h"
 #include "drm.h"
 #include "radeon_drm.h"
 #include "dri_util.h"
-#include "texmem.h"
 #include "radeon_common.h"
 
-#include "main/macros.h"
 #include "main/mtypes.h"
-#include "main/colormac.h"
 
 struct r300_context;
 typedef struct r300_context r300ContextRec;
 typedef struct r300_context *r300ContextPtr;
 
 
-#include "main/mm.h"
-
 /* From http://gcc. gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
    with other compilers ... GLUE!
@@ -81,9 +75,6 @@ typedef struct r300_context *r300ContextPtr;
 #define R300_BLIT_WIDTH_BYTES 1024
 #define R300_MAX_TEXTURE_UNITS 8
 
-struct r300_texture_state {
-	int tc_count;		/* number of incoming texture coordinates from VAP */
-};
 
 
 #define R300_VPT_CMD_0		0
@@ -303,7 +294,7 @@ struct r300_texture_state {
 struct r300_hw_state {
 	struct radeon_state_atom vpt;	/* viewport (1D98) */
 	struct radeon_state_atom vap_cntl;
-        struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */
+	struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */
 	struct radeon_state_atom vof;	/* VAP output format register 0x2090 */
 	struct radeon_state_atom vte;	/* (20B0) */
 	struct radeon_state_atom vap_vf_max_vtx_indx;	/* Maximum Vertex Indx Clamp (2134) */
@@ -425,12 +416,8 @@ extern int hw_tcl_on;
 #include "tnl_dd/t_dd_vertex.h"
 #undef TAG
 
-//#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
 #define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
 
-/* Should but doesnt work */
-//#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
-
 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
  * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
  */
@@ -623,20 +610,6 @@ struct r500_fragment_program {
 
 #define R300_MAX_AOS_ARRAYS		16
 
-#define REG_COORDS	0
-#define REG_COLOR0	1
-#define REG_TEX0	2
-
-struct r300_state {
-	struct r300_texture_state texture;
-	int sw_tcl_inputs[VERT_ATTRIB_MAX];
-	struct r300_vertex_shader_state vertex_shader;
-
-
-	DECLARE_RENDERINPUTS(render_inputs_bitset);	/* actual render inputs that R300 was configured for.
-							   They are the same as tnl->render_inputs for fixed pipeline */
-
-};
 
 #define R300_FALLBACK_NONE 0
 #define R300_FALLBACK_TCL 1
@@ -664,6 +637,8 @@ struct r300_swtcl_info {
    } vert_attrs[VERT_ATTRIB_MAX];
 
    GLubyte vertex_attr_count;
+
+   int sw_tcl_inputs[VERT_ATTRIB_MAX];
 };
 
 
@@ -675,8 +650,7 @@ struct r300_context {
 
 	struct r300_hw_state hw;
 
-	struct r300_state state;
-	struct gl_vertex_program *curr_vp;
+	struct r300_vertex_shader_state vertex_shader;
 	struct r300_vertex_program *selected_vp;
 
 	/* Vertex buffers
@@ -688,6 +662,8 @@ struct r300_context {
 
 	struct r300_swtcl_info swtcl;
 	GLboolean vap_flush_needed;
+
+	DECLARE_RENDERINPUTS(render_inputs_bitset);
 };
 
 #define R300_CONTEXT(ctx)		((r300ContextPtr)(ctx->DriverCtx))
@@ -703,11 +679,6 @@ extern int r300VertexProgUpdateParams(GLcontext * ctx,
 				      struct r300_vertex_program_cont *vp,
 				      float *dst);
 
-#define RADEON_D_CAPTURE 0
-#define RADEON_D_PLAYBACK 1
-#define RADEON_D_PLAYBACK_RAW 2
-#define RADEON_D_T 3
-
 #define r300PackFloat32 radeonPackFloat32
 #define r300PackFloat24 radeonPackFloat24
 
diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c
index 4fd6ba9b91..a19b0f1960 100644
--- a/src/mesa/drivers/dri/r300/r300_emit.c
+++ b/src/mesa/drivers/dri/r300/r300_emit.c
@@ -127,7 +127,6 @@ GLuint r300VAPInputCntl0(GLcontext * ctx, GLuint InputsRead)
 
 GLuint r300VAPInputCntl1(GLcontext * ctx, GLuint InputsRead)
 {
-	r300ContextPtr rmesa = R300_CONTEXT(ctx);
 	GLuint i, vic_1 = 0;
 
 	if (InputsRead & (1 << VERT_ATTRIB_POS))
@@ -139,10 +138,8 @@ GLuint r300VAPInputCntl1(GLcontext * ctx, GLuint InputsRead)
 	if (InputsRead & (1 << VERT_ATTRIB_COLOR0))
 		vic_1 |= R300_INPUT_CNTL_COLOR;
 
-	rmesa->state.texture.tc_count = 0;
 	for (i = 0; i < ctx->Const.MaxTextureUnits; i++)
 		if (InputsRead & (1 << (VERT_ATTRIB_TEX0 + i))) {
-			rmesa->state.texture.tc_count++;
 			vic_1 |= R300_INPUT_CNTL_TC0 << i;
 		}
 
@@ -222,7 +219,7 @@ int r300EmitArrays(GLcontext * ctx)
 		InputsRead = prog->key.InputsRead;
 		OutputsWritten = prog->key.OutputsWritten;
 	} else {
-		inputs = rmesa->state.sw_tcl_inputs;
+		inputs = rmesa->swtcl.sw_tcl_inputs;
 
 		DECLARE_RENDERINPUTS(render_inputs_bitset);
 		RENDERINPUTS_COPY(render_inputs_bitset, tnl->render_inputs_bitset);
@@ -275,7 +272,7 @@ int r300EmitArrays(GLcontext * ctx)
 			if (InputsRead & (1 << i))
 				inputs[i] = 6 + (i - VERT_ATTRIB_TEX0);
 
-		RENDERINPUTS_COPY(rmesa->state.render_inputs_bitset, render_inputs_bitset);
+		RENDERINPUTS_COPY(rmesa->render_inputs_bitset, render_inputs_bitset);
 	}
 
 	assert(InputsRead);
@@ -330,7 +327,7 @@ int r300EmitArrays(GLcontext * ctx)
 			r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle,
 					   nr);
 	}
-	
+
 	/* Setup INPUT_CNTL. */
 	R300_STATECHANGE(rmesa, vic);
 	rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead);
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index 5ae999b73a..86b85d525f 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -1432,7 +1432,7 @@ static void r300SetupRSUnit(GLcontext * ctx)
 	if (hw_tcl_on)
 		OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten;
 	else
-		RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->state.render_inputs_bitset);
+		RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->render_inputs_bitset);
 
 	if (ctx->FragmentProgram._Current)
 		InputsRead = ctx->FragmentProgram._Current->Base.InputsRead;
@@ -1583,7 +1583,7 @@ static void r500SetupRSUnit(GLcontext * ctx)
 	if (hw_tcl_on)
 		OutputsWritten.vp_outputs = CURRENT_VERTEX_SHADER(ctx)->key.OutputsWritten;
 	else
-		RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->state.render_inputs_bitset);
+		RENDERINPUTS_COPY(OutputsWritten.index_bitset, r300->render_inputs_bitset);
 
 	if (ctx->FragmentProgram._Current)
 		InputsRead = ctx->FragmentProgram._Current->Base.InputsRead;
@@ -1853,7 +1853,7 @@ static void r300VapCntl(r300ContextPtr rmesa, GLuint input_count,
 
 static void r300SetupDefaultVertexProgram(r300ContextPtr rmesa)
 {
-	struct r300_vertex_shader_state *prog = &(rmesa->state.vertex_shader);
+	struct r300_vertex_shader_state *prog = &(rmesa->vertex_shader);
 	GLuint o_reg = 0;
 	GLuint i_reg = 0;
 	int i;
@@ -1862,11 +1862,11 @@ static void r300SetupDefaultVertexProgram(r300ContextPtr rmesa)
 	int program_end = 0;
 
 	for (i = VERT_ATTRIB_POS; i < VERT_ATTRIB_MAX; i++) {
-		if (rmesa->state.sw_tcl_inputs[i] != -1) {
+		if (rmesa->swtcl.sw_tcl_inputs[i] != -1) {
 			prog->program.body.i[program_end + 0] = PVS_OP_DST_OPERAND(VE_MULTIPLY, GL_FALSE, GL_FALSE, o_reg++, VSF_FLAG_ALL, PVS_DST_REG_OUT);
-			prog->program.body.i[program_end + 1] = PVS_SRC_OPERAND(rmesa->state.sw_tcl_inputs[i], PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
-			prog->program.body.i[program_end + 2] = PVS_SRC_OPERAND(rmesa->state.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
-			prog->program.body.i[program_end + 3] = PVS_SRC_OPERAND(rmesa->state.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
+			prog->program.body.i[program_end + 1] = PVS_SRC_OPERAND(rmesa->swtcl.sw_tcl_inputs[i], PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
+			prog->program.body.i[program_end + 2] = PVS_SRC_OPERAND(rmesa->swtcl.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
+			prog->program.body.i[program_end + 3] = PVS_SRC_OPERAND(rmesa->swtcl.sw_tcl_inputs[i], PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_SELECT_FORCE_1, PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
 			program_end += 4;
 			i_reg++;
 		}
@@ -2522,8 +2522,6 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state)
  */
 void r300InitState(r300ContextPtr r300)
 {
-	memset(&(r300->state.texture), 0, sizeof(r300->state.texture));
-
 	r300ResetHwState(r300);
 }
 
diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c
index 553bdb12dd..934e1e2243 100644
--- a/src/mesa/drivers/dri/r300/r300_swtcl.c
+++ b/src/mesa/drivers/dri/r300/r300_swtcl.c
@@ -281,7 +281,7 @@ static void r300SetVertexFormat( GLcontext *ctx )
 
 	rmesa->radeon.swtcl.vertex_size /= 4;
 
-	RENDERINPUTS_COPY(rmesa->state.render_inputs_bitset, tnl->render_inputs_bitset);
+	RENDERINPUTS_COPY(rmesa->render_inputs_bitset, tnl->render_inputs_bitset);
 }
 
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index 34d6261706..f7c50e9949 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -61,21 +61,21 @@ static int radeon_compressed_num_bytes(GLuint mesaFormat)
 {
    int bytes = 0;
    switch(mesaFormat) {
-     
+
    case MESA_FORMAT_RGB_FXT1:
    case MESA_FORMAT_RGBA_FXT1:
    case MESA_FORMAT_RGB_DXT1:
    case MESA_FORMAT_RGBA_DXT1:
      bytes = 2;
      break;
-     
+
    case MESA_FORMAT_RGBA_DXT3:
    case MESA_FORMAT_RGBA_DXT5:
      bytes = 4;
    default:
      break;
    }
-   
+
    return bytes;
 }
 
@@ -97,18 +97,38 @@ static void compute_tex_image_offset(radeon_mipmap_tree *mt,
 		lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63;
 		lvl->size = radeon_compressed_texture_size(mt->radeon->glCtx,
 							   lvl->width, lvl->height, lvl->depth, mt->compressed);
+		if (lvl->size <= 0) {
+			int *i = 0;
+			*i = 0;
+		}
+		assert(lvl->size > 0);
 	} else if (mt->target == GL_TEXTURE_RECTANGLE_NV) {
 		lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63;
 		lvl->size = lvl->rowstride * lvl->height;
+		if (lvl->size <= 0) {
+			int *i = 0;
+			*i = 0;
+		}
+		assert(lvl->size > 0);
 	} else if (mt->tilebits & RADEON_TXO_MICRO_TILE) {
 		/* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned,
 		 * though the actual offset may be different (if texture is less than
 		 * 32 bytes width) to the untiled case */
 		lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31;
 		lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth;
+		if (lvl->size <= 0) {
+			int *i = 0;
+			*i = 0;
+		}
+		assert(lvl->size > 0);
 	} else {
 		lvl->rowstride = (lvl->width * mt->bpp + 31) & ~31;
 		lvl->size = lvl->rowstride * lvl->height * lvl->depth;
+		if (lvl->size <= 0) {
+			int *i = 0;
+			*i = 0;
+		}
+		assert(lvl->size > 0);
 	}
 	assert(lvl->size > 0);
 
@@ -230,7 +250,7 @@ static void calculate_first_last_level(struct gl_texture_object *tObj,
 		tObj->Image[face][level];
 
 	assert(baseImage);
-	
+
 	/* These must be signed values.  MinLod and MaxLod can be negative numbers,
 	* and having firstLevel and lastLevel as signed prevents the need for
 	* extra sign checks.
-- 
cgit v1.2.3


From bcef4b63eba3b6072df3a699d0c4d5128e2515b9 Mon Sep 17 00:00:00 2001
From: Maciej Cencora <m.cencora@gmail.com>
Date: Sun, 19 Apr 2009 15:26:51 +0200
Subject: r300: revert part of cb4bef7ae0b5fe8de82c380bc98f19067394d355

Some debugging code got there by accident
---
 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 28 ++++--------------------
 1 file changed, 4 insertions(+), 24 deletions(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c')

diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index f7c50e9949..34d6261706 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -61,21 +61,21 @@ static int radeon_compressed_num_bytes(GLuint mesaFormat)
 {
    int bytes = 0;
    switch(mesaFormat) {
-
+     
    case MESA_FORMAT_RGB_FXT1:
    case MESA_FORMAT_RGBA_FXT1:
    case MESA_FORMAT_RGB_DXT1:
    case MESA_FORMAT_RGBA_DXT1:
      bytes = 2;
      break;
-
+     
    case MESA_FORMAT_RGBA_DXT3:
    case MESA_FORMAT_RGBA_DXT5:
      bytes = 4;
    default:
      break;
    }
-
+   
    return bytes;
 }
 
@@ -97,38 +97,18 @@ static void compute_tex_image_offset(radeon_mipmap_tree *mt,
 		lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63;
 		lvl->size = radeon_compressed_texture_size(mt->radeon->glCtx,
 							   lvl->width, lvl->height, lvl->depth, mt->compressed);
-		if (lvl->size <= 0) {
-			int *i = 0;
-			*i = 0;
-		}
-		assert(lvl->size > 0);
 	} else if (mt->target == GL_TEXTURE_RECTANGLE_NV) {
 		lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63;
 		lvl->size = lvl->rowstride * lvl->height;
-		if (lvl->size <= 0) {
-			int *i = 0;
-			*i = 0;
-		}
-		assert(lvl->size > 0);
 	} else if (mt->tilebits & RADEON_TXO_MICRO_TILE) {
 		/* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned,
 		 * though the actual offset may be different (if texture is less than
 		 * 32 bytes width) to the untiled case */
 		lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31;
 		lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth;
-		if (lvl->size <= 0) {
-			int *i = 0;
-			*i = 0;
-		}
-		assert(lvl->size > 0);
 	} else {
 		lvl->rowstride = (lvl->width * mt->bpp + 31) & ~31;
 		lvl->size = lvl->rowstride * lvl->height * lvl->depth;
-		if (lvl->size <= 0) {
-			int *i = 0;
-			*i = 0;
-		}
-		assert(lvl->size > 0);
 	}
 	assert(lvl->size > 0);
 
@@ -250,7 +230,7 @@ static void calculate_first_last_level(struct gl_texture_object *tObj,
 		tObj->Image[face][level];
 
 	assert(baseImage);
-
+	
 	/* These must be signed values.  MinLod and MaxLod can be negative numbers,
 	* and having firstLevel and lastLevel as signed prevents the need for
 	* extra sign checks.
-- 
cgit v1.2.3


From 0b22615c2c860968a027c04519e25864ae69f6cd Mon Sep 17 00:00:00 2001
From: Maciej Cencora <m.cencora@gmail.com>
Date: Sat, 2 May 2009 17:27:03 +0200
Subject: r300: set proper texture row alignment for IGP chips

Looks like r400 based IGP chips require 64 byte alignment
---
 src/mesa/drivers/dri/r300/r300_context.c            |  5 +++++
 src/mesa/drivers/dri/radeon/radeon_common_context.c |  2 ++
 src/mesa/drivers/dri/radeon/radeon_common_context.h |  1 +
 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c    | 11 ++++++-----
 4 files changed, 14 insertions(+), 5 deletions(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c')

diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c
index 4d1f10ba4d..70c7730be9 100644
--- a/src/mesa/drivers/dri/r300/r300_context.c
+++ b/src/mesa/drivers/dri/r300/r300_context.c
@@ -412,6 +412,11 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 	if (r300->radeon.radeonScreen->kernel_mm)
 	  driInitExtensions(ctx, mm_extensions, GL_FALSE);
 
+	if (screen->chip_family == CHIP_FAMILY_RS600 ||	screen->chip_family == CHIP_FAMILY_RS690 ||
+		screen->chip_family == CHIP_FAMILY_RS740) {
+		r300->radeon.texture_row_align = 64;
+	}
+
 	r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache,
 						     "def_max_anisotropy");
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index ba74c97f2c..3e713628ec 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -177,6 +177,8 @@ GLboolean radeonInitContext(radeonContextPtr radeon,
                 radeon->texture_depth = ( glVisual->rgbBits > 16 ) ?
 	        DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
 
+	radeon->texture_row_align = 32;
+
 	return GL_TRUE;
 }
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index d32e5af544..181688cbe4 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -421,6 +421,7 @@ struct radeon_context {
     */
    int                   texture_depth;
    float                 initialMaxAnisotropy;
+   uint32_t              texture_row_align;
 
   struct radeon_dma dma;
   struct radeon_hw_state hw;
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index 34d6261706..51538e37fa 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -86,10 +86,11 @@ static int radeon_compressed_num_bytes(GLuint mesaFormat)
  * \param curOffset points to the offset at which the image is to be stored
  * and is updated by this function according to the size of the image.
  */
-static void compute_tex_image_offset(radeon_mipmap_tree *mt,
+static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree *mt,
 	GLuint face, GLuint level, GLuint* curOffset)
 {
 	radeon_mipmap_level *lvl = &mt->levels[level];
+	uint32_t row_align = rmesa->texture_row_align - 1;
 
 	/* Find image size in bytes */
 	if (mt->compressed) {
@@ -107,7 +108,7 @@ static void compute_tex_image_offset(radeon_mipmap_tree *mt,
 		lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31;
 		lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth;
 	} else {
-		lvl->rowstride = (lvl->width * mt->bpp + 31) & ~31;
+		lvl->rowstride = (lvl->width * mt->bpp + row_align) & ~row_align;
 		lvl->size = lvl->rowstride * lvl->height * lvl->depth;
 	}
 	assert(lvl->size > 0);
@@ -131,7 +132,7 @@ static GLuint minify(GLuint size, GLuint levels)
 	return size;
 }
 
-static void calculate_miptree_layout(radeon_mipmap_tree *mt)
+static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
 {
 	GLuint curOffset;
 	GLuint numLevels;
@@ -149,7 +150,7 @@ static void calculate_miptree_layout(radeon_mipmap_tree *mt)
 		mt->levels[i].depth = minify(mt->depth0, i);
 
 		for(face = 0; face < mt->faces; face++)
-			compute_tex_image_offset(mt, face, i, &curOffset);
+			compute_tex_image_offset(rmesa, mt, face, i, &curOffset);
 	}
 
 	/* Note the required size in memory */
@@ -181,7 +182,7 @@ radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, radeonTexObj *
 	mt->tilebits = tilebits;
 	mt->compressed = compressed;
 
-	calculate_miptree_layout(mt);
+	calculate_miptree_layout(rmesa, mt);
 
 	mt->bo = radeon_bo_open(rmesa->radeonScreen->bom,
                             0, mt->totalsize, 1024,
-- 
cgit v1.2.3


From d7f62e54055c7b8afaf0683944a4ba907b96d6ec Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Wed, 6 May 2009 14:06:13 +1000
Subject: r100/r200: try and allocate miptree correct for hw.

This doesn't make things worse but according to sroland it
is how the GPU hw expects things on the r100/r200
---
 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 34 +++++++++++++++++++++---
 1 file changed, 31 insertions(+), 3 deletions(-)

(limited to 'src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c')

diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index 51538e37fa..8d1ba1cdba 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -132,7 +132,33 @@ static GLuint minify(GLuint size, GLuint levels)
 	return size;
 }
 
-static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
+
+static void calculate_miptree_layout_r100(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
+{
+	GLuint curOffset;
+	GLuint numLevels;
+	GLuint i;
+	GLuint face;
+
+	numLevels = mt->lastLevel - mt->firstLevel + 1;
+	assert(numLevels <= RADEON_MAX_TEXTURE_LEVELS);
+
+	curOffset = 0;
+	for(face = 0; face < mt->faces; face++) {
+
+		for(i = 0; i < numLevels; i++) {
+			mt->levels[i].width = minify(mt->width0, i);
+			mt->levels[i].height = minify(mt->height0, i);
+			mt->levels[i].depth = minify(mt->depth0, i);
+			compute_tex_image_offset(rmesa, mt, face, i, &curOffset);
+		}
+	}
+
+	/* Note the required size in memory */
+	mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK;
+}
+
+static void calculate_miptree_layout_r300(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
 {
 	GLuint curOffset;
 	GLuint numLevels;
@@ -157,7 +183,6 @@ static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree
 	mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK;
 }
 
-
 /**
  * Create a new mipmap tree, calculate its layout and allocate memory.
  */
@@ -182,7 +207,10 @@ radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, radeonTexObj *
 	mt->tilebits = tilebits;
 	mt->compressed = compressed;
 
-	calculate_miptree_layout(rmesa, mt);
+	if (rmesa->radeonScreen->chip_family >= CHIP_FAMILY_R300)
+		calculate_miptree_layout_r300(rmesa, mt);
+	else
+		calculate_miptree_layout_r100(rmesa, mt);
 
 	mt->bo = radeon_bo_open(rmesa->radeonScreen->bom,
                             0, mt->totalsize, 1024,
-- 
cgit v1.2.3