From 96ba38a450b77d56730fd293499cbeaa1f511507 Mon Sep 17 00:00:00 2001 From: Roland Scheidegger Date: Thu, 15 Nov 2007 01:13:16 +0100 Subject: fix bogus assumption if ddx has set up surface reg for z buffer this is wrong since even if ddx has not set up a surface reg to cover the z buffer we should pretend it has on those rv100 chips since they presumably do not do z buffer tiling if not using hyperz, so we can use linear addressing just the same. Doesn't seem to fix #13080, but it's wrong anyway and the bug almost certainly broke newer non-tcl chips. --- src/mesa/drivers/dri/radeon/radeon_screen.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/radeon/radeon_screen.c') diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index ceb947c09d..c12eef2024 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -720,8 +720,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->depthPitch = dri_priv->depthPitch; /* Check if ddx has set up a surface reg to cover depth buffer */ - screen->depthHasSurface = ((sPriv->ddx_version.major > 4) && - (screen->chip_flags & RADEON_CHIPSET_TCL)); + screen->depthHasSurface = (sPriv->ddx_version.major > 4); if ( dri_priv->textureSize == 0 ) { screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; -- cgit v1.2.3