From 4d2b392a0ac597f8b7f88006746660e8f0fe09ea Mon Sep 17 00:00:00 2001 From: Roland Scheidegger Date: Fri, 19 Jun 2009 22:55:34 +0200 Subject: radeon: fix cube maps for non-mm path drm cmd checker would refuse cube emits also fix an issue in the cs path which would calculate the register offset off by one dword. Only same testing done as original code (none except compile tested). --- src/mesa/drivers/dri/radeon/radeon_state_init.c | 35 +++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/radeon/radeon_state_init.c') diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index f5d4189d66..c517487098 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -462,6 +462,34 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) } static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r100ContextPtr r100 = R100_CONTEXT(ctx); + BATCH_LOCALS(&r100->radeon); + uint32_t dwords = 3; + int i = atom->idx, j; + radeonTexObj *t = r100->state.texture.unit[i].texobj; + radeon_mipmap_level *lvl; + + if (!(ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) + return; + + if (!t) + return; + + if (!t->mt) + return; + + BEGIN_BATCH_NO_AUTOSTATE(dwords + (5 * 3)); + OUT_BATCH_TABLE(atom->cmd, 3); + lvl = &t->mt->levels[0]; + for (j = 0; j < 5; j++) { + OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset, + RADEON_GEM_DOMAIN_VRAM, 0, 0); + } + END_BATCH(); +} + +static void cube_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) { r100ContextPtr r100 = R100_CONTEXT(ctx); BATCH_LOCALS(&r100->radeon); @@ -490,7 +518,7 @@ static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom) OUT_BATCH_TABLE(atom->cmd, 2); lvl = &t->mt->levels[0]; for (j = 0; j < 5; j++) { - OUT_BATCH(CP_PACKET0(base_reg + (4 * (j-1)), 0)); + OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0)); OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset, RADEON_GEM_DOMAIN_VRAM, 0, 0); } @@ -661,7 +689,10 @@ void radeonInitState( r100ContextPtr rmesa ) ALLOC_STATE_IDX( cube[1], cube1, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); ALLOC_STATE_IDX( cube[2], cube2, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); for (i = 0; i < 3; i++) - rmesa->hw.cube[i].emit = cube_emit; + if (rmesa->radeon.radeonScreen->kernel_mm) + rmesa->hw.cube[i].emit = cube_emit_cs; + else + rmesa->hw.cube[i].emit = cube_emit; } else { -- cgit v1.2.3 From 2ed3eddf9a828f2ff6c74b0913ca37fb60672950 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 2 Jul 2009 20:44:30 +1000 Subject: radeon/r300: use base width/height. I suspect this might break TFP in some way but it makes firecube run here --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 21 +++++++++++---------- src/mesa/drivers/dri/radeon/radeon_state_init.c | 4 ++-- 2 files changed, 13 insertions(+), 12 deletions(-) (limited to 'src/mesa/drivers/dri/radeon/radeon_state_init.c') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index b5c6bd1835..19d240f576 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -232,8 +232,8 @@ void r300_emit_scissor(GLcontext *ctx) } else { x1 = 0; y1 = 0; - x2 = rrb->width - 1; - y2 = rrb->height - 1; + x2 = rrb->base.Width - 1; + y2 = rrb->base.Height - 1; } if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) { x1 += R300_SCISSORS_OFFSET; @@ -263,7 +263,8 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) fprintf(stderr, "no rrb\n"); return; } - + + fprintf(stderr,"rrb is %p %d %dx%d\n", rrb, offset, rrb->base.Width, rrb->base.Height); cbpitch = (rrb->pitch / rrb->cpp); if (rrb->cpp == 4) cbpitch |= R300_COLOR_FORMAT_ARGB8888; @@ -289,14 +290,14 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) BEGIN_BATCH_NO_AUTOSTATE(3); OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2); OUT_BATCH(0); - OUT_BATCH(((rrb->width - 1) << R300_SCISSORS_X_SHIFT) | - ((rrb->height - 1) << R300_SCISSORS_Y_SHIFT)); + OUT_BATCH(((rrb->base.Width - 1) << R300_SCISSORS_X_SHIFT) | + ((rrb->base.Height - 1) << R300_SCISSORS_Y_SHIFT)); END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(16); for (i = 0; i < 4; i++) { OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2); OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT) | (0 << R300_CLIPRECT_Y_SHIFT)); - OUT_BATCH(((rrb->width - 1) << R300_CLIPRECT_X_SHIFT) | ((rrb->height - 1) << R300_CLIPRECT_Y_SHIFT)); + OUT_BATCH(((rrb->base.Width - 1) << R300_CLIPRECT_X_SHIFT) | ((rrb->base.Height - 1) << R300_CLIPRECT_Y_SHIFT)); } OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1); OUT_BATCH(0xAAAA); @@ -308,15 +309,15 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2); OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT)); - OUT_BATCH(((rrb->width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) | - ((rrb->height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT)); + OUT_BATCH(((rrb->base.Width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) | + ((rrb->base.Height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT)); END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(16); for (i = 0; i < 4; i++) { OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2); OUT_BATCH((R300_SCISSORS_OFFSET << R300_CLIPRECT_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_CLIPRECT_Y_SHIFT)); - OUT_BATCH(((R300_SCISSORS_OFFSET + rrb->width - 1) << R300_CLIPRECT_X_SHIFT) | - ((R300_SCISSORS_OFFSET + rrb->height - 1) << R300_CLIPRECT_Y_SHIFT)); + OUT_BATCH(((R300_SCISSORS_OFFSET + rrb->base.Width - 1) << R300_CLIPRECT_X_SHIFT) | + ((R300_SCISSORS_OFFSET + rrb->base.Height - 1) << R300_CLIPRECT_Y_SHIFT)); } OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1); OUT_BATCH(0xAAAA); diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index c517487098..a55cd6dfcb 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -453,8 +453,8 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) OUT_BATCH(0); OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); if (rrb) { - OUT_BATCH(((rrb->width - 1) << RADEON_RE_WIDTH_SHIFT) | - ((rrb->height - 1) << RADEON_RE_HEIGHT_SHIFT)); + OUT_BATCH(((rrb->base.Width - 1) << RADEON_RE_WIDTH_SHIFT) | + ((rrb->base.Height - 1) << RADEON_RE_HEIGHT_SHIFT)); } else { OUT_BATCH(0); } -- cgit v1.2.3 From 33f56b4612e506999a2be8391ba82c0174afa1b3 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Tue, 14 Jul 2009 08:25:27 +0200 Subject: radeon: Differentiate 16 bpp destination formats. Fixes those formats in fbo_firecube. Only tested with r300, radeon and r200 compile tested only. --- src/mesa/drivers/dri/r200/r200_state_init.c | 11 ++++++++++- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 11 ++++++++++- src/mesa/drivers/dri/radeon/radeon_state_init.c | 11 ++++++++++- 3 files changed, 30 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/radeon/radeon_state_init.c') diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index c7df4b2587..bc871d9904 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -484,8 +484,17 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); if (rrb->cpp == 4) atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; - else + else switch (rrb->base._ActualFormat) { + case GL_RGB5: atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; + break; + case GL_RGBA4: + atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444; + break; + case GL_RGB5_A1: + atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555; + break; + } cbpitch = (rrb->pitch / rrb->cpp); if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 90ca45b3e7..248297897d 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -269,8 +269,17 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) cbpitch = (rrb->pitch / rrb->cpp); if (rrb->cpp == 4) cbpitch |= R300_COLOR_FORMAT_ARGB8888; - else + else switch (rrb->base._ActualFormat) { + case GL_RGB5: cbpitch |= R300_COLOR_FORMAT_RGB565; + break; + case GL_RGBA4: + cbpitch |= R300_COLOR_FORMAT_ARGB4444; + break; + case GL_RGB5_A1: + cbpitch |= R300_COLOR_FORMAT_ARGB1555; + break; + } if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) cbpitch |= R300_COLOR_TILE_ENABLE; diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index a55cd6dfcb..aaa82b1d6a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -390,8 +390,17 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); if (rrb->cpp == 4) atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; - else + else switch (rrb->base._ActualFormat) { + case GL_RGB5: atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; + break; + case GL_RGBA4: + atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444; + break; + case GL_RGB5_A1: + atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555; + break; + } cbpitch = (rrb->pitch / rrb->cpp); if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) -- cgit v1.2.3