From 5484428d7267388fde868e64531dcdf98b55fafc Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 26 Aug 2009 13:56:45 +1000 Subject: radeon: add r100 OQ support with kms. This adds OQ support for the r100 chipsets, it requires KMS unless someone wants to make a kernel patch to add support for OQ regs. --- src/mesa/drivers/dri/radeon/radeon_context.c | 21 +++++++++++++++++++++ src/mesa/drivers/dri/radeon/radeon_context.h | 4 ++++ src/mesa/drivers/dri/radeon/radeon_state_init.c | 6 ++++++ src/mesa/drivers/dri/radeon/server/radeon_reg.h | 2 ++ 4 files changed, 33 insertions(+) (limited to 'src/mesa/drivers/dri/radeon') diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index 12e4ed0a95..247e65ba9d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -62,7 +62,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_swtcl.h" #include "radeon_tcl.h" #include "radeon_maos.h" +#include "radeon_queryobj.h" +#define need_GL_ARB_occlusion_query #define need_GL_EXT_blend_minmax #define need_GL_EXT_fog_coord #define need_GL_EXT_secondary_color @@ -80,6 +82,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. const struct dri_extension card_extensions[] = { { "GL_ARB_multitexture", NULL }, + { "GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions}, { "GL_ARB_texture_border_clamp", NULL }, { "GL_ARB_texture_env_add", NULL }, { "GL_ARB_texture_env_combine", NULL }, @@ -194,6 +197,20 @@ static void r100_vtbl_free_context(GLcontext *ctx) _mesa_vector4f_free( &rmesa->tcl.ObjClean ); } +static void r100_emit_query_finish(radeonContextPtr radeon) +{ + BATCH_LOCALS(radeon); + struct radeon_query_object *query = radeon->query.current; + + BEGIN_BATCH_NO_AUTOSTATE(4); + OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0)); + OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0); + END_BATCH(); + query->curr_offset += sizeof(uint32_t); + assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE); + query->emitted_begin = GL_FALSE; +} + static void r100_init_vtbl(radeonContextPtr radeon) { radeon->vtbl.get_lock = r100_get_lock; @@ -203,6 +220,7 @@ static void r100_init_vtbl(radeonContextPtr radeon) radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state; radeon->vtbl.fallback = radeonFallback; radeon->vtbl.free_context = r100_vtbl_free_context; + radeon->vtbl.emit_query_finish = r100_emit_query_finish; } /* Create the device specific context. @@ -369,6 +387,9 @@ r100CreateContext( const __GLcontextModes *glVisual, if (rmesa->radeon.radeonScreen->kernel_mm || rmesa->radeon.dri.drmMinor >= 9) _mesa_enable_extension( ctx, "GL_NV_texture_rectangle"); + if (!rmesa->radeon.radeonScreen->kernel_mm) + _mesa_disable_extension(ctx, "GL_ARB_occlusion_query"); + /* XXX these should really go right after _mesa_init_driver_functions() */ radeon_fbo_init(&rmesa->radeon); radeonInitSpanFuncs( ctx ); diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h index 1795d8bdb6..0845cad519 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -295,6 +295,10 @@ struct radeon_texture_state { #define SHN_SHININESS 1 #define SHN_STATE_SIZE 2 +#define R100_QUERYOBJ_CMD_0 0 +#define R100_QUERYOBJ_DATA_0 1 +#define R100_QUERYOBJ_CMDSIZE 2 + struct r100_hw_state { /* Hardware state, stored as cmdbuf commands: * -- Need to doublebuffer for diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index b34a4e803d..60fdc215a4 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -1143,6 +1143,12 @@ void radeonInitState( r100ContextPtr rmesa ) rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE; rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE; + if (rmesa->radeon.radeonScreen->kernel_mm) { + radeon_init_query_stateobj(&rmesa->radeon, R100_QUERYOBJ_CMDSIZE); + rmesa->radeon.query.queryobj.cmd[R100_QUERYOBJ_CMD_0] = CP_PACKET0(RADEON_RB3D_ZPASS_DATA, 0); + rmesa->radeon.query.queryobj.cmd[R100_QUERYOBJ_DATA_0] = 0; + } + rmesa->radeon.hw.all_dirty = GL_TRUE; rcommonInitCmdBuf(&rmesa->radeon); diff --git a/src/mesa/drivers/dri/radeon/server/radeon_reg.h b/src/mesa/drivers/dri/radeon/server/radeon_reg.h index 866807462a..c9054606eb 100644 --- a/src/mesa/drivers/dri/radeon/server/radeon_reg.h +++ b/src/mesa/drivers/dri/radeon/server/radeon_reg.h @@ -1601,6 +1601,8 @@ # define RADEON_STENCIL_VALUE_MASK (0xff << 16) # define RADEON_STENCIL_WRITEMASK_SHIFT 24 # define RADEON_STENCIL_WRITE_MASK (0xff << 24) +#define RADEON_RB3D_ZPASS_DATA 0x3290 +#define RADEON_RB3D_ZPASS_ADDR 0x3294 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c # define RADEON_DEPTH_FORMAT_MASK (0xf << 0) # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) -- cgit v1.2.3