From a205137423e42010a025c70b05af98a6c0564f28 Mon Sep 17 00:00:00 2001 From: Roland Scheidegger Date: Wed, 26 Jan 2005 18:05:03 +0000 Subject: (Stephane Marchesin, me) Add support for color (framebuffer) tiling to the radeon and r200 driver --- src/mesa/drivers/dri/radeon/radeon_ioctl.c | 3 ++ src/mesa/drivers/dri/radeon/radeon_lock.c | 6 +++ src/mesa/drivers/dri/radeon/radeon_screen.c | 8 +++- src/mesa/drivers/dri/radeon/radeon_screen.h | 2 + src/mesa/drivers/dri/radeon/radeon_span.c | 56 +++++++++++++++---------- src/mesa/drivers/dri/radeon/radeon_state.c | 3 ++ src/mesa/drivers/dri/radeon/radeon_state_init.c | 4 ++ 7 files changed, 58 insertions(+), 24 deletions(-) (limited to 'src/mesa/drivers/dri/radeon') diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 8fe0e8c845..8e411bdaa8 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -1011,6 +1011,9 @@ void radeonPageFlip( const __DRIdrawablePrivate *dPriv ) rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset + rmesa->radeonScreen->fbLocation; rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch; + if (rmesa->sarea->tiling_enabled) { + rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE; + } } diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c index 937a284e10..7dab02e6b5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_lock.c +++ b/src/mesa/drivers/dri/radeon/radeon_lock.c @@ -116,6 +116,12 @@ void radeonGetLock( radeonContextPtr rmesa, GLuint flags ) rmesa->lastStamp = dPriv->lastStamp; } + RADEON_STATECHANGE( rmesa, ctx ); + if (rmesa->sarea->tiling_enabled) { + rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE; + } + else rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= ~RADEON_COLOR_TILE_ENABLE; + if ( sarea->ctx_owner != rmesa->dri.hwContext ) { int i; sarea->ctx_owner = rmesa->dri.hwContext; diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index e51b72911b..9687b7efac 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -355,6 +355,10 @@ radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->depthOffset = dri_priv->depthOffset; screen->depthPitch = dri_priv->depthPitch; + /* Check if ddx has set up a surface reg to cover depth buffer */ + screen->depthHasSurface = ((sPriv->ddxMajor > 4) && + (screen->chipset & RADEON_CHIPSET_TCL)); + screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset + screen->fbLocation; screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize; @@ -538,11 +542,11 @@ void * __driCreateNewScreen( __DRInativeDisplay *dpy, int scrn, __DRIscreen *psc { __DRIscreenPrivate *psp; - static const __DRIversion ddx_expected = { 4, 0, 0 }; + static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; static const __DRIversion dri_expected = { 4, 0, 0 }; static const __DRIversion drm_expected = { 1, 3, 0 }; - if ( ! driCheckDriDdxDrmVersions2( "Radeon", + if ( ! driCheckDriDdxDrmVersions3( "Radeon", dri_version, & dri_expected, ddx_version, & ddx_expected, drm_version, & drm_expected ) ) { diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h index 72edec881d..000e734737 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.h +++ b/src/mesa/drivers/dri/radeon/radeon_screen.h @@ -96,6 +96,8 @@ typedef struct { unsigned int gart_buffer_offset; /* offset in card memory space */ unsigned int gart_texture_offset; /* offset in card memory space */ + GLboolean depthHasSurface; + /* Configuration cache with default values for all contexts */ driOptionCache optionCache; } radeonScreenRec, *radeonScreenPtr; diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 5fa02fa97c..38ba5a50e5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -189,46 +189,58 @@ do { \ * manner as the engine. In each case, the linear block address (ba) * is calculated, and then wired with x and y to produce the final * memory address. + * The chip will do address translation on its own if the surface registers + * are set up correctly. It is not quite enough to get it working with hyperz too... */ static GLuint radeon_mba_z32( radeonContextPtr rmesa, GLint x, GLint y ) { GLuint pitch = rmesa->radeonScreen->frontPitch; - GLuint ba, address = 0; /* a[0..1] = 0 */ + if (rmesa->radeonScreen->depthHasSurface) { + return 4*(x + y*pitch); + } + else { + GLuint ba, address = 0; /* a[0..1] = 0 */ - ba = (y / 16) * (pitch / 16) + (x / 16); + ba = (y / 16) * (pitch / 16) + (x / 16); - address |= (x & 0x7) << 2; /* a[2..4] = x[0..2] */ - address |= (y & 0x3) << 5; /* a[5..6] = y[0..1] */ - address |= - (((x & 0x10) >> 2) ^ (y & 0x4)) << 5; /* a[7] = x[4] ^ y[2] */ - address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */ + address |= (x & 0x7) << 2; /* a[2..4] = x[0..2] */ + address |= (y & 0x3) << 5; /* a[5..6] = y[0..1] */ + address |= + (((x & 0x10) >> 2) ^ (y & 0x4)) << 5; /* a[7] = x[4] ^ y[2] */ + address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */ - address |= (y & 0x8) << 7; /* a[10] = y[3] */ - address |= - (((x & 0x8) << 1) ^ (y & 0x10)) << 7; /* a[11] = x[3] ^ y[4] */ - address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */ + address |= (y & 0x8) << 7; /* a[10] = y[3] */ + address |= + (((x & 0x8) << 1) ^ (y & 0x10)) << 7; /* a[11] = x[3] ^ y[4] */ + address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */ - return address; + return address; + } } static __inline GLuint radeon_mba_z16( radeonContextPtr rmesa, GLint x, GLint y ) { GLuint pitch = rmesa->radeonScreen->frontPitch; - GLuint ba, address = 0; /* a[0] = 0 */ + if (rmesa->radeonScreen->depthHasSurface) { + return 2*(x + y*pitch); + } + else { + GLuint ba, address = 0; /* a[0] = 0 */ - ba = (y / 16) * (pitch / 32) + (x / 32); + ba = (y / 16) * (pitch / 32) + (x / 32); - address |= (x & 0x7) << 1; /* a[1..3] = x[0..2] */ - address |= (y & 0x7) << 4; /* a[4..6] = y[0..2] */ - address |= (x & 0x8) << 4; /* a[7] = x[3] */ - address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */ - address |= (y & 0x8) << 7; /* a[10] = y[3] */ - address |= ((x & 0x10) ^ (y & 0x10)) << 7; /* a[11] = x[4] ^ y[4] */ - address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */ + address |= (x & 0x7) << 1; /* a[1..3] = x[0..2] */ + address |= (y & 0x7) << 4; /* a[4..6] = y[0..2] */ + address |= (x & 0x8) << 4; /* a[7] = x[3] */ + address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */ + address |= (y & 0x8) << 7; /* a[10] = y[3] */ + address |= ((x & 0x10) ^ (y & 0x10)) << 7; /* a[11] = x[4] ^ y[4] */ + address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */ - return address; + return address; + } } diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index ff6f8bc726..06f49eac5c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -1686,6 +1686,9 @@ static void radeonDrawBuffer( GLcontext *ctx, GLenum mode ) rmesa->radeonScreen->fbLocation) & RADEON_COLOROFFSET_MASK); rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch; + if (rmesa->sarea->tiling_enabled) { + rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE; + } } static void radeonReadBuffer( GLcontext *ctx, GLenum mode ) diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index 8db3c88192..9caa8a2b4d 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -385,6 +385,10 @@ void radeonInitState( radeonContextPtr rmesa ) rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch & RADEON_COLORPITCH_MASK) | RADEON_COLOR_ENDIAN_NO_SWAP); + /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */ + if (rmesa->sarea->tiling_enabled) { + rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE; + } rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW | RADEON_BFACE_SOLID | -- cgit v1.2.3