From 0c5b42a99182be05a72c78fa9340b75f3be81220 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <darktama@iinet.net.au>
Date: Mon, 29 Jan 2007 16:39:19 +1100
Subject: nouveau: unhardcode some more NV30TCL_FP_CONTROL values

---
 src/mesa/drivers/dri/nouveau/nouveau_shader.h |  3 ++-
 src/mesa/drivers/dri/nouveau/nv30_fragprog.c  | 20 +++++++++++++++++---
 2 files changed, 19 insertions(+), 4 deletions(-)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/nouveau/nouveau_shader.h b/src/mesa/drivers/dri/nouveau/nouveau_shader.h
index 7329ccd9ea..82eb27b053 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_shader.h
+++ b/src/mesa/drivers/dri/nouveau/nouveau_shader.h
@@ -26,7 +26,8 @@ typedef struct _nvs_fragment_header {
 
 typedef union {
 	struct {
-		uint32_t fp_control;
+		GLboolean uses_kil;
+		GLuint    num_regs;
 	} NV30FP;
 	struct {
 		uint32_t vp_in_reg;
diff --git a/src/mesa/drivers/dri/nouveau/nv30_fragprog.c b/src/mesa/drivers/dri/nouveau/nv30_fragprog.c
index 3c7501dd62..02bd8014cc 100644
--- a/src/mesa/drivers/dri/nouveau/nv30_fragprog.c
+++ b/src/mesa/drivers/dri/nouveau/nv30_fragprog.c
@@ -24,6 +24,7 @@ static void
 NV30FPUploadToHW(GLcontext *ctx, nouveauShader *nvs)
 {
    nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
+   nvsCardPriv *priv = &nvs->card_priv;
    uint32_t offset;
 
    if (!nvs->program_buffer)
@@ -46,8 +47,9 @@ NV30FPUploadToHW(GLcontext *ctx, nouveauShader *nvs)
     */
    BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_FP_ACTIVE_PROGRAM, 1);
    OUT_RING       (offset | 1);
-   BEGIN_RING_SIZE(NvSub3D, 0x1d60, 1);
-   OUT_RING       (nvs->card_priv.NV30FP.fp_control | 0x03000000);
+   BEGIN_RING_SIZE(NvSub3D, 0x1d60 /*NV30_TCL_PRIMITIVE_3D_FP_CONTROL*/, 1);
+   OUT_RING       ((priv->NV30FP.uses_kil <<  7) |
+		   (priv->NV30FP.num_regs << 24));
 }
 
 static void
@@ -95,7 +97,7 @@ static void
 NV30FPSetOpcode(nvsFunc *shader, unsigned int opcode, int slot)
 {
    if (opcode == NV30_FP_OP_OPCODE_KIL)
-      shader->card_priv->NV30FP.fp_control |= (1<<7);
+      shader->card_priv->NV30FP.uses_kil = GL_TRUE;
    shader->inst[0] &= ~NV30_FP_OP_OPCODE_MASK;
    shader->inst[0] |= (opcode << NV30_FP_OP_OPCODE_SHIFT);
 }
@@ -145,6 +147,16 @@ NV30FPSetCondition(nvsFunc *shader, int on, nvsCond cond, int reg,
    shader->inst[1] |= (swz[NVS_SWZ_W] << NV30_FP_OP_COND_SWZ_W_SHIFT);
 }
 
+static void
+NV30FPSetHighReg(nvsFunc *shader, int id)
+{
+   if (shader->card_priv->NV30FP.num_regs < (id+1)) {
+      if (id == 0)
+	 id = 1; /* necessary? */
+      shader->card_priv->NV30FP.num_regs = (id+1);
+   }
+}
+
 static void
 NV30FPSetResult(nvsFunc *shader, nvsRegister *reg, unsigned int mask, int slot)
 {
@@ -163,6 +175,7 @@ NV30FPSetResult(nvsFunc *shader, nvsRegister *reg, unsigned int mask, int slot)
       shader->inst[0] &= ~NV30_FP_OP_UNK0_7;
       hwreg = reg->index;
    }
+   NV30FPSetHighReg(shader, hwreg);
    shader->inst[0] &= ~NV30_FP_OP_OUT_REG_SHIFT;
    shader->inst[0] |= (hwreg  << NV30_FP_OP_OUT_REG_SHIFT);
 }
@@ -176,6 +189,7 @@ NV30FPSetSource(nvsFunc *shader, nvsRegister *reg, int pos)
    case NVS_FILE_TEMP:
       hwsrc |= (NV30_FP_REG_TYPE_TEMP << NV30_FP_REG_TYPE_SHIFT);
       hwsrc |= (reg->index << NV30_FP_REG_SRC_SHIFT);
+      NV30FPSetHighReg(shader, reg->index);
       break;
    case NVS_FILE_ATTRIB:
       {
-- 
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