From 3b3278519af67beb3dc9c134a6bd127370cf82f8 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 9 Jun 2010 17:48:15 -0700 Subject: i965: Move no_batch_wrap assertion out across the area we're trying to verify. It's more likely that we wrap badly in state setup than in the little primitive packet. --- src/mesa/drivers/dri/i965/brw_draw.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 3e305c8968..16331cc3ac 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -151,9 +151,6 @@ static void brw_emit_prim(struct brw_context *brw, prim_packet.start_instance_location = 0; prim_packet.base_vert_location = prim->basevertex; - /* Can't wrap here, since we rely on the validated state. */ - intel->no_batch_wrap = GL_TRUE; - /* If we're set to always flush, do it before and after the primitive emit. * We want to catch both missed flushes that hurt instruction/state cache * and missed flushes of the render cache as it heads to other parts of @@ -169,8 +166,6 @@ static void brw_emit_prim(struct brw_context *brw, if (intel->always_flush_cache) { intel_batchbuffer_emit_mi_flush(intel->batch); } - - intel->no_batch_wrap = GL_FALSE; } static void brw_merge_inputs( struct brw_context *brw, @@ -394,11 +389,14 @@ static GLboolean brw_try_draw_prims( GLcontext *ctx, } } + intel->no_batch_wrap = GL_TRUE; brw_upload_state(brw); } brw_emit_prim(brw, &prim[i], hw_prim); + intel->no_batch_wrap = GL_FALSE; + retval = GL_TRUE; } -- cgit v1.2.3