From 5696710f96f9517d24958208fb90a5a72d145a26 Mon Sep 17 00:00:00 2001 From: Nicolai Haehnle Date: Fri, 15 Oct 2004 20:52:47 +0000 Subject: Huge dumb drop. State: - Color buffer clear is accelerated, but flickers (possibly caused by a recent DDX or Mesa change or bad merge) - Everything else uses software fallback rendering - There should be no clipping-related artifacts with the sw-clipspan-fixes.patch against Mesa (posted on dri-devel) - Multiple clients should be rock solid with a DDX patch that is soon to come (soon = within the next hour or so) --- src/mesa/drivers/dri/r300/Makefile | 1 + src/mesa/drivers/dri/r300/r200_state.h | 2 - src/mesa/drivers/dri/r300/r300_cmdbuf.c | 42 +++++++++------ src/mesa/drivers/dri/r300/r300_context.c | 12 ++--- src/mesa/drivers/dri/r300/r300_context.h | 16 +++++- src/mesa/drivers/dri/r300/r300_ioctl.c | 30 +++++++---- src/mesa/drivers/dri/r300/r300_reg.h | 75 ++++++++++++++++++++++++--- src/mesa/drivers/dri/r300/r300_state.c | 12 +++-- src/mesa/drivers/dri/r300/radeon_ioctl.c | 7 ++- src/mesa/drivers/dri/r300/radeon_lock.c | 15 +++--- src/mesa/drivers/dri/r300/radeon_span.c | 13 +++-- src/mesa/drivers/dri/r300/radeon_state.c | 88 ++++++++++++++++++++++++++++++++ src/mesa/drivers/dri/r300/radeon_state.h | 42 +++++++++++++++ 13 files changed, 296 insertions(+), 59 deletions(-) create mode 100644 src/mesa/drivers/dri/r300/radeon_state.c create mode 100644 src/mesa/drivers/dri/r300/radeon_state.h (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index 3cad8c080f..19e95c2322 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -24,6 +24,7 @@ DRIVER_SOURCES = \ radeon_ioctl.c \ radeon_lock.c \ radeon_span.c \ + radeon_state.c \ \ r300_context.c \ r300_ioctl.c \ diff --git a/src/mesa/drivers/dri/r300/r200_state.h b/src/mesa/drivers/dri/r300/r200_state.h index 50bb51af6c..cba8e497df 100644 --- a/src/mesa/drivers/dri/r300/r200_state.h +++ b/src/mesa/drivers/dri/r300/r200_state.h @@ -1,4 +1,3 @@ -/* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_state.h,v 1.2 2002/11/05 17:46:08 tsi Exp $ */ /* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. @@ -46,7 +45,6 @@ extern void r200InitTnlFuncs(GLcontext * ctx); extern void r200UpdateMaterial(GLcontext * ctx); -extern void r200SetCliprects(r200ContextPtr rmesa, GLenum mode); extern void r200RecalcScissorRects(r200ContextPtr rmesa); extern void r200UpdateViewportOffset(GLcontext * ctx); extern void r200UpdateWindow(GLcontext * ctx); diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 7c51e10a17..7d124d7285 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -66,7 +66,8 @@ int r300FlushCmdBuf(r300ContextPtr r300, const char* caller) start = r300->cmdbuf.count_reemit; if (RADEON_DEBUG & DEBUG_IOCTL) { - fprintf(stderr, "%s from %s\n", __FUNCTION__, caller); + fprintf(stderr, "%s from %s - %i cliprects\n", + __FUNCTION__, caller, r300->radeon.numClipRects); if (RADEON_DEBUG & DEBUG_VERBOSE) for (i = start; i < r300->cmdbuf.count_used; ++i) @@ -91,17 +92,22 @@ int r300FlushCmdBuf(r300ContextPtr r300, const char* caller) } #endif - ret = drmCommandWrite(r300->radeon.dri.fd, - DRM_RADEON_CMDBUF, &cmd, sizeof(cmd)); - if (ret) { - UNLOCK_HARDWARE(&r300->radeon); - fprintf(stderr, "drmCommandWrite: %d\n", ret); - exit(-1); - } + if (cmd.nbox) { + ret = drmCommandWrite(r300->radeon.dri.fd, + DRM_RADEON_CMDBUF, &cmd, sizeof(cmd)); + if (ret) { + UNLOCK_HARDWARE(&r300->radeon); + fprintf(stderr, "drmCommandWrite: %d\n", ret); + exit(-1); + } - if (RADEON_DEBUG & DEBUG_SYNC) { - fprintf(stderr, "Syncing in %s\n\n", __FUNCTION__); - radeonWaitForIdleLocked(&r300->radeon); + if (RADEON_DEBUG & DEBUG_SYNC) { + fprintf(stderr, "Syncing in %s\n\n", __FUNCTION__); + radeonWaitForIdleLocked(&r300->radeon); + } + } else { + if (RADEON_DEBUG & DEBUG_IOCTL) + fprintf(stderr, "%s: No cliprects\n", __FUNCTION__); } UNLOCK_HARDWARE(&r300->radeon); @@ -109,7 +115,7 @@ int r300FlushCmdBuf(r300ContextPtr r300, const char* caller) r300->cmdbuf.count_used = 0; r300->cmdbuf.count_reemit = 0; - return ret; + return 0; } @@ -310,6 +316,8 @@ void r300InitCmdBuf(r300ContextPtr r300) r300->hw.unk4200.cmd[0] = cmducs(0x4200, 4); ALLOC_STATE( unk4214, always, 2, "unk4214", 0 ); r300->hw.unk4214.cmd[0] = cmducs(0x4214, 1); + ALLOC_STATE( ps, always, R300_PS_CMDSIZE, "ps", 0 ); + r300->hw.ps.cmd[0] = cmducs(R300_RE_POINTSIZE, 1); ALLOC_STATE( unk4230, always, 4, "unk4230", 0 ); r300->hw.unk4230.cmd[0] = cmducs(0x4230, 3); ALLOC_STATE( unk4260, always, 4, "unk4260", 0 ); @@ -332,8 +340,8 @@ void r300InitCmdBuf(r300ContextPtr r300) r300->hw.rr.cmd[R300_RR_CMD_0] = cmducs(R300_RS_ROUTE_0, 1); ALLOC_STATE( unk43A4, always, 3, "unk43A4", 0 ); r300->hw.unk43A4.cmd[0] = cmducs(0x43A4, 2); - ALLOC_STATE( unk43E0, always, 4, "unk43E0", 0 ); - r300->hw.unk43E0.cmd[0] = cmducs(0x43E0, 3); + ALLOC_STATE( unk43E8, always, 2, "unk43E8", 0 ); + r300->hw.unk43E8.cmd[0] = cmducs(0x43E8, 1); ALLOC_STATE( fp, always, R300_FP_CMDSIZE, "fp", 0 ); r300->hw.fp.cmd[R300_FP_CMD_0] = cmducs(R300_PFS_CNTL_0, 3); r300->hw.fp.cmd[R300_FP_CMD_1] = cmducs(R300_PFS_NODE_0, 4); @@ -389,6 +397,8 @@ void r300InitCmdBuf(r300ContextPtr r300) r300->hw.vpi.cmd[R300_VPI_CMD_0] = cmdvpu(R300_PVS_UPLOAD_PROGRAM, 0); ALLOC_STATE( vpp, vpu, R300_VPP_CMDSIZE, "vpp", 0 ); r300->hw.vpp.cmd[R300_VPP_CMD_0] = cmdvpu(R300_PVS_UPLOAD_PARAMETERS, 0); + ALLOC_STATE( vps, vpu, R300_VPS_CMDSIZE, "vps", 0 ); + r300->hw.vps.cmd[R300_VPS_CMD_0] = cmdvpu(R300_PVS_UPLOAD_POINTSIZE, 1); /* Setup the atom linked list */ make_empty_list(&r300->hw.atomlist); @@ -413,6 +423,7 @@ void r300InitCmdBuf(r300ContextPtr r300) insert_at_tail(&r300->hw.atomlist, &r300->hw.txe); insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4200); insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4214); + insert_at_tail(&r300->hw.atomlist, &r300->hw.ps); insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4230); insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4260); insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4274); @@ -424,7 +435,7 @@ void r300InitCmdBuf(r300ContextPtr r300) insert_at_tail(&r300->hw.atomlist, &r300->hw.ri); insert_at_tail(&r300->hw.atomlist, &r300->hw.rr); insert_at_tail(&r300->hw.atomlist, &r300->hw.unk43A4); - insert_at_tail(&r300->hw.atomlist, &r300->hw.unk43E0); + insert_at_tail(&r300->hw.atomlist, &r300->hw.unk43E8); insert_at_tail(&r300->hw.atomlist, &r300->hw.fp); insert_at_tail(&r300->hw.atomlist, &r300->hw.unk46A4); insert_at_tail(&r300->hw.atomlist, &r300->hw.fpi[0]); @@ -452,6 +463,7 @@ void r300InitCmdBuf(r300ContextPtr r300) insert_at_tail(&r300->hw.atomlist, &r300->hw.vpi); insert_at_tail(&r300->hw.atomlist, &r300->hw.vpp); + insert_at_tail(&r300->hw.atomlist, &r300->hw.vps); r300->hw.is_dirty = GL_TRUE; r300->hw.all_dirty = GL_TRUE; diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 3604b1181e..271ea17e1e 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -100,14 +100,15 @@ static const char *const card_extensions[] = { NULL }; -//extern const struct tnl_pipeline_stage _r300_render_stage; -//extern const struct tnl_pipeline_stage _r300_tcl_stage; +#if 0 +extern const struct tnl_pipeline_stage _r300_render_stage; +extern const struct tnl_pipeline_stage _r300_tcl_stage; static const struct tnl_pipeline_stage *r300_pipeline[] = { /* Try and go straight to t&l */ - //&_r200_tcl_stage, + &_r300_tcl_stage, /* Catch any t&l fallbacks */ @@ -131,11 +132,11 @@ static const struct tnl_pipeline_stage *r300_pipeline[] = { /* Else do them here. */ - //&_r300_render_stage, + &_r300_render_stage, &_tnl_render_stage, /* FALLBACK */ 0, }; - +#endif /* Create the device specific rendering context. */ @@ -148,7 +149,6 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, struct dd_function_table functions; r300ContextPtr r300; GLcontext *ctx; - int i; int tcl_mode; assert(glVisual); diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index b8523b6772..ce7ccd95d9 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -122,6 +122,10 @@ struct r300_state_atom { #define R300_TXE_ENABLE 1 #define R300_TXE_CMDSIZE 2 +#define R300_PS_CMD_0 0 +#define R300_PS_POINTSIZE 1 +#define R300_PS_CMDSIZE 2 + #define R300_RC_CMD_0 0 #define R300_RC_CNTL_0 1 #define R300_RC_CNTL_1 2 @@ -201,6 +205,13 @@ struct r300_state_atom { #define R300_VPP_PARAM_0 1 #define R300_VPP_CMDSIZE 1025 /* 256 4-component parameters */ +#define R300_VPS_CMD_0 0 +#define R300_VPS_ZERO_0 1 +#define R300_VPS_ZERO_1 2 +#define R300_VPS_POINTSIZE 3 +#define R300_VPS_ZERO_3 4 +#define R300_VPS_CMDSIZE 5 + /** * Cache for hardware register state. */ @@ -229,7 +240,7 @@ struct r300_hw_state { struct r300_state_atom txe; /* tex enable (4104) */ struct r300_state_atom unk4200; /* (4200) */ struct r300_state_atom unk4214; /* (4214) */ - // what about UNKNOWN_421C? (see r300_reg.h) + struct r300_state_atom ps; /* pointsize (421C) */ struct r300_state_atom unk4230; /* (4230) */ struct r300_state_atom unk4260; /* (4260) */ struct r300_state_atom unk4274; /* (4274) */ @@ -241,7 +252,7 @@ struct r300_hw_state { struct r300_state_atom ri; /* rs interpolators (4310) */ struct r300_state_atom rr; /* rs route (4330) */ struct r300_state_atom unk43A4; /* (43A4) */ - struct r300_state_atom unk43E0; /* (43E0) */ + struct r300_state_atom unk43E8; /* (43E8) */ struct r300_state_atom fp; /* fragment program cntl + nodes (4600) */ struct r300_state_atom unk46A4; /* (46A4) */ struct r300_state_atom fpi[4]; /* fp instructions (46C0/47C0/48C0/49C0) */ @@ -266,6 +277,7 @@ struct r300_hw_state { struct r300_state_atom vpi; /* vp instructions */ struct r300_state_atom vpp; /* vp parameters */ + struct r300_state_atom vps; /* vertex point size (?) */ }; diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index a59b1efc9e..8463e4eff3 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -1,5 +1,7 @@ /* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. +Copyright (C) The Weather Channel, Inc. 2002. +Copyright (C) 2004 Nicolai Haehnle. +All Rights Reserved. The Weather Channel (TM) funded Tungsten Graphics to develop the initial release of the Radeon 8500 driver under the XFree86 license. @@ -53,7 +55,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "vblank.h" -static void r300ClearColorBuffer(r300ContextPtr r300, int buffer) +static void r300ClearBuffer(r300ContextPtr r300, int buffer) { GLcontext* ctx = r300->radeon.glCtx; __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable; @@ -62,8 +64,9 @@ static void r300ClearColorBuffer(r300ContextPtr r300, int buffer) drm_r300_cmd_header_t* cmd; if (RADEON_DEBUG & DEBUG_IOCTL) - fprintf(stderr, "%s: %s buffer\n", __FUNCTION__, - buffer ? "back" : "front"); + fprintf(stderr, "%s: %s buffer (%i,%i %ix%i)\n", + __FUNCTION__, buffer ? "back" : "front", + dPriv->x, dPriv->y, dPriv->w, dPriv->h); if (buffer) { cboffset = r300->radeon.radeonScreen->backOffset; @@ -72,7 +75,8 @@ static void r300ClearColorBuffer(r300ContextPtr r300, int buffer) cboffset = r300->radeon.radeonScreen->frontOffset; cbpitch = r300->radeon.radeonScreen->frontPitch; } - cboffset = r300->radeon.radeonScreen->fbLocation; + + cboffset += r300->radeon.radeonScreen->fbLocation; R300_STATECHANGE(r300, vpt); r300->hw.vpt.cmd[R300_VPT_XSCALE] = r300PackFloat32(1.0); @@ -89,6 +93,11 @@ static void r300ClearColorBuffer(r300ContextPtr r300, int buffer) R300_STATECHANGE(r300, unk221C); r300->hw.unk221C.cmd[1] = R300_221C_CLEAR; + R300_STATECHANGE(r300, ps); + r300->hw.ps.cmd[R300_PS_POINTSIZE] = + ((dPriv->w * 6) << R300_POINTSIZE_X_SHIFT) | + ((dPriv->h * 6) << R300_POINTSIZE_Y_SHIFT); + R300_STATECHANGE(r300, ri); for(i = 1; i <= 8; ++i) r300->hw.ri.cmd[i] = R300_RS_INTERP_USED; @@ -97,6 +106,9 @@ static void r300ClearColorBuffer(r300ContextPtr r300, int buffer) ((drm_r300_cmd_header_t*)r300->hw.rr.cmd)->unchecked_state.count = 1; r300->hw.rr.cmd[1] = 0x00004000; + R300_STATECHANGE(r300, cmk); + r300->hw.cmk.cmd[R300_CMK_COLORMASK] = 0xF; + R300_STATECHANGE(r300, fp); r300->hw.fp.cmd[R300_FP_CNTL0] = 0; /* 1 pass, no textures */ r300->hw.fp.cmd[R300_FP_CNTL1] = 0; /* no temporaries */ @@ -153,7 +165,7 @@ static void r300ClearColorBuffer(r300ContextPtr r300, int buffer) cmd = (drm_r300_cmd_header_t*)r300AllocCmdBuf(r300, 9, __FUNCTION__); cmd[0].packet3.cmd_type = R300_CMD_PACKET3; cmd[0].packet3.packet = R300_CMD_PACKET3_CLEAR; - cmd[1].u = r300PackFloat32(dPriv->w / 2.0); /* my guess is as good as yours */ + cmd[1].u = r300PackFloat32(dPriv->w / 2.0); cmd[2].u = r300PackFloat32(dPriv->h / 2.0); cmd[3].u = r300PackFloat32(0.0); cmd[4].u = r300PackFloat32(1.0); @@ -206,12 +218,12 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask, GLboolean all, swapped = r300->radeon.doPageFlip && (r300->radeon.sarea->pfCurrentPage == 1); if (flags & DD_FRONT_LEFT_BIT) - r300ClearColorBuffer(r300, swapped); + r300ClearBuffer(r300, swapped); if (flags & DD_BACK_LEFT_BIT) - r300ClearColorBuffer(r300, swapped ^ 1); + r300ClearBuffer(r300, swapped ^ 1); - /* Recalculate the hardware set. This could be done more efficiently, + /* Recalculate the hardware state. This could be done more efficiently, * but do keep it like this for now. */ r300ResetHwState(r300); diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h index 90c5158b8b..47c5305c4e 100644 --- a/src/mesa/drivers/dri/r300/r300_reg.h +++ b/src/mesa/drivers/dri/r300/r300_reg.h @@ -142,12 +142,16 @@ I am fairly certain that they are correct unless stated otherwise in comments. // Native reported limits and the VPI layout suggest size 256, whereas // difference between known addresses suggests size 512. // +// At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the +// floating point pointsize. The exact purpose of this state is uncertain, +// as there is also the R300_RE_POINTSIZE register. +// // Multiple vertex programs and parameter sets can be loaded at once, // which could explain the size discrepancy. #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200 # define R300_PVS_UPLOAD_PROGRAM 0x00000000 # define R300_PVS_UPLOAD_PARAMETERS 0x00000200 -# define R300_PVS_UPLOAD_UNKNOWN 0x00000400 +# define R300_PVS_UPLOAD_POINTSIZE 0x00000406 /* gap */ #define R300_VAP_PVS_UPLOAD_DATA 0x2208 // END @@ -251,11 +255,14 @@ I am fairly certain that they are correct unless stated otherwise in comments. # define R300_TX_ENABLE_14 (1 << 14) # define R300_TX_ENABLE_15 (1 << 15) -// No idea what the purpose is, but it is set to 421C_CLEAR just before -// issuing the clear command and then reset to 421C_NORMAL afterwards. -#define R300_UNKNOWN_421C 0x421C -# define R300_421C_NORMAL 0x00060006 -# define R300_421C_CLEAR 0x0F000B40 +// The pointsize is given in multiples of 6. The pointsize can be +// enormous: Clear() renders a single point that fills the entire +// framebuffer. +#define R300_RE_POINTSIZE 0x421C +# define R300_POINTSIZE_Y_SHIFT 0 +# define R300_POINTSIZE_Y_MASK (0xFFFF << 0) // GUESS +# define R300_POINTSIZE_X_SHIFT 16 +# define R300_POINTSIZE_X_MASK (0xFFFF << 16) // GUESS // BEGIN: Rasterization / Interpolators - many guesses // So far, 0_UNKOWN_7 has always been set. @@ -327,6 +334,62 @@ I am fairly certain that they are correct unless stated otherwise in comments. # define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 6) // GUESS // END +// BEGIN: Scissors and cliprects +// There are four clipping rectangles. Their corner coordinates are inclusive. +// Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending +// on whether the pixel is inside cliprects 0-3, respectively. For example, +// if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned +// the number 3 (binary 0011). +// Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set, +// the pixel is rasterized. +// +// In addition to this, there is a scissors rectangle. Only pixels inside the +// scissors rectangle are drawn. (coordinates are inclusive) +// +// For some reason, the top-left corner of the framebuffer is at (1440, 1440) +// for the purpose of clipping and scissors. +#define R300_RE_CLIPRECT_TL_0 0x43B0 +#define R300_RE_CLIPRECT_BR_0 0x43B4 +#define R300_RE_CLIPRECT_TL_1 0x43B8 +#define R300_RE_CLIPRECT_BR_1 0x43BC +#define R300_RE_CLIPRECT_TL_2 0x43C0 +#define R300_RE_CLIPRECT_BR_2 0x43C4 +#define R300_RE_CLIPRECT_TL_3 0x43C8 +#define R300_RE_CLIPRECT_BR_3 0x43CC +# define R300_CLIPRECT_OFFSET 1440 +# define R300_CLIPRECT_MASK 0x1FFF +# define R300_CLIPRECT_X_SHIFT 0 +# define R300_CLIPRECT_X_MASK (0x1FFF << 0) +# define R300_CLIPRECT_Y_SHIFT 13 +# define R300_CLIPRECT_Y_MASK (0x1FFF << 13) +#define R300_RE_CLIPRECT_CNTL 0x43D0 +# define R300_CLIP_OUT (1 << 0) +# define R300_CLIP_0 (1 << 1) +# define R300_CLIP_1 (1 << 2) +# define R300_CLIP_10 (1 << 3) +# define R300_CLIP_2 (1 << 4) +# define R300_CLIP_20 (1 << 5) +# define R300_CLIP_21 (1 << 6) +# define R300_CLIP_210 (1 << 7) +# define R300_CLIP_3 (1 << 8) +# define R300_CLIP_30 (1 << 9) +# define R300_CLIP_31 (1 << 10) +# define R300_CLIP_310 (1 << 11) +# define R300_CLIP_32 (1 << 12) +# define R300_CLIP_320 (1 << 13) +# define R300_CLIP_321 (1 << 14) +# define R300_CLIP_3210 (1 << 15) + +/* gap */ +#define R300_RE_SCISSORS_TL 0x43E0 +#define R300_RE_SCISSORS_BR 0x43E4 +# define R300_SCISSORS_OFFSET 1440 +# define R300_SCISSORS_X_SHIFT 0 +# define R300_SCISSORS_X_MASK (0x1FFF << 0) +# define R300_SCISSORS_Y_SHIFT 13 +# define R300_SCISSORS_Y_MASK (0x1FFF << 13) +// END + // BEGIN: Texture specification // The texture specification dwords are grouped by meaning and not by texture unit. // This means that e.g. the offset for texture image unit N is found in register diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index e1cb31da40..43cfe2b69b 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -165,6 +165,9 @@ void r300ResetHwState(r300ContextPtr r300) r300->hw.unk4214.cmd[1] = 0x00050005; + r300->hw.ps.cmd[R300_PS_POINTSIZE] = (6 << R300_POINTSIZE_X_SHIFT) | + (6 << R300_POINTSIZE_Y_SHIFT); + r300->hw.unk4230.cmd[1] = 0x01800000; r300->hw.unk4230.cmd[2] = 0x00020006; r300->hw.unk4230.cmd[3] = r300PackFloat32(1.0 / 192.0); @@ -205,9 +208,7 @@ void r300ResetHwState(r300ContextPtr r300) r300->hw.unk43A4.cmd[1] = 0x0000001C; r300->hw.unk43A4.cmd[2] = 0x2DA49525; - r300->hw.unk43E0.cmd[1] = 0x00000000; - r300->hw.unk43E0.cmd[2] = 0x03FFFFFF; - r300->hw.unk43E0.cmd[3] = 0x00FFFFFF; + r300->hw.unk43E8.cmd[1] = 0x00FFFFFF; r300->hw.fp.cmd[R300_FP_CNTL0] = 0; r300->hw.fp.cmd[R300_FP_CNTL1] = 0; @@ -305,6 +306,11 @@ void r300ResetHwState(r300ContextPtr r300) ((drm_r300_cmd_header_t*)r300->hw.vpp.cmd)->vpu.count = 0; for(i = 1; i < R300_VPP_CMDSIZE; ++i) r300->hw.vpp.cmd[i] = 0; + + r300->hw.vps.cmd[R300_VPS_ZERO_0] = 0; + r300->hw.vps.cmd[R300_VPS_ZERO_1] = 0; + r300->hw.vps.cmd[R300_VPS_POINTSIZE] = r300PackFloat32(1.0); + r300->hw.vps.cmd[R300_VPS_ZERO_3] = 0; //END: TODO r300->hw.all_dirty = GL_TRUE; diff --git a/src/mesa/drivers/dri/r300/radeon_ioctl.c b/src/mesa/drivers/dri/r300/radeon_ioctl.c index 0caf44569d..f75b755184 100644 --- a/src/mesa/drivers/dri/r300/radeon_ioctl.c +++ b/src/mesa/drivers/dri/r300/radeon_ioctl.c @@ -42,6 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "swrast/swrast.h" #include "r200_context.h" +#include "r300_context.h" #include "r200_state.h" #include "radeon_ioctl.h" #include "r200_ioctl.h" @@ -161,6 +162,8 @@ void radeonCopyBuffer(const __DRIdrawablePrivate * dPriv) if (IS_FAMILY_R200(radeon)) R200_FIREVERTICES((r200ContextPtr)radeon); + else + r300Flush(radeon->glCtx); LOCK_HARDWARE(radeon); @@ -190,7 +193,7 @@ void radeonCopyBuffer(const __DRIdrawablePrivate * dPriv) ret = drmCommandNone(radeon->dri.fd, DRM_RADEON_SWAP); if (ret) { - fprintf(stderr, "DRM_R200_SWAP_BUFFERS: return = %d\n", + fprintf(stderr, "DRM_RADEON_SWAP: return = %d\n", ret); UNLOCK_HARDWARE(radeon); exit(1); @@ -201,6 +204,8 @@ void radeonCopyBuffer(const __DRIdrawablePrivate * dPriv) if (IS_FAMILY_R200(radeon)) ((r200ContextPtr)radeon)->hw.all_dirty = GL_TRUE; + else + ((r300ContextPtr)radeon)->hw.all_dirty = GL_TRUE; radeon->swap_count++; (*radeon->get_ust) (&ust); diff --git a/src/mesa/drivers/dri/r300/radeon_lock.c b/src/mesa/drivers/dri/r300/radeon_lock.c index b5fb20ddb4..79b7c5ada2 100644 --- a/src/mesa/drivers/dri/r300/radeon_lock.c +++ b/src/mesa/drivers/dri/r300/radeon_lock.c @@ -38,6 +38,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r200_tex.h" #include "r200_state.h" #include "radeon_ioctl.h" +#include "radeon_state.h" #if DEBUG_LOCKING char *prevLockFile = NULL; @@ -70,7 +71,6 @@ static void radeonUpdatePageFlipping(radeonContextPtr radeon) static void r200RegainedLock(r200ContextPtr r200) { __DRIdrawablePrivate *dPriv = r200->radeon.dri.drawable; - __DRIscreenPrivate *sPriv = r200->radeon.dri.screen; int i; if (r200->radeon.lastStamp != dPriv->lastStamp) { @@ -83,9 +83,9 @@ static void r200RegainedLock(r200ContextPtr r200) r200->radeon.state.color.drawPitch; if (r200->radeon.glCtx->Color._DrawDestMask == DD_BACK_LEFT_BIT) - r200SetCliprects(r200, GL_BACK_LEFT); + radeonSetCliprects(&r200->radeon, GL_BACK_LEFT); else - r200SetCliprects(r200, GL_FRONT_LEFT); + radeonSetCliprects(&r200->radeon, GL_FRONT_LEFT); r200UpdateViewportOffset(r200->radeon.glCtx); r200->radeon.lastStamp = dPriv->lastStamp; } @@ -98,17 +98,16 @@ static void r200RegainedLock(r200ContextPtr r200) static void r300RegainedLock(radeonContextPtr radeon) { __DRIdrawablePrivate *dPriv = radeon->dri.drawable; - __DRIscreenPrivate *sPriv = radeon->dri.screen; - int i; if (radeon->lastStamp != dPriv->lastStamp) { radeonUpdatePageFlipping(radeon); -#if 0 if (radeon->glCtx->Color._DrawDestMask == DD_BACK_LEFT_BIT) - r200SetCliprects(r200, GL_BACK_LEFT); + radeonSetCliprects(radeon, GL_BACK_LEFT); else - r200SetCliprects(r200, GL_FRONT_LEFT); + radeonSetCliprects(radeon, GL_FRONT_LEFT); + +#if 0 r200UpdateViewportOffset(r200->radeon.glCtx); #endif radeon->lastStamp = dPriv->lastStamp; diff --git a/src/mesa/drivers/dri/r300/radeon_span.c b/src/mesa/drivers/dri/r300/radeon_span.c index 9046320cc1..7b548754e6 100644 --- a/src/mesa/drivers/dri/r300/radeon_span.c +++ b/src/mesa/drivers/dri/r300/radeon_span.c @@ -70,8 +70,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. GLuint height = dPriv->h; \ GLuint xo = dPriv->x; \ GLuint yo = dPriv->y; \ - char *buf = (char *)(sPriv->pFB + radeon->radeonScreen->depthOffset); \ - GLuint pitch = radeon->radeonScreen->depthPitch; \ + char *buf = (char *)(sPriv->pFB + radeonScreen->depthOffset); \ + GLuint pitch = radeonScreen->depthPitch; \ (void) buf; (void) pitch #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS @@ -248,10 +248,10 @@ do { \ /* 16-bit depth buffer functions */ #define WRITE_DEPTH( _x, _y, d ) \ - *(GLushort *)(buf + (_x + xo)*2 + (_y + yo)*pitch ) = d; + *(GLushort *)(buf + (_x + xo + (_y + yo)*pitch)*2 ) = d; #define READ_DEPTH( d, _x, _y ) \ - d = *(GLushort *)(buf + (_x + xo)*2 + (_y + yo)*pitch ); + d = *(GLushort *)(buf + (_x + xo + (_y + yo)*pitch)*2 ); #define TAG(x) radeon##x##_16_LINEAR #include "depthtmp.h" @@ -260,7 +260,7 @@ do { \ */ #define WRITE_DEPTH( _x, _y, d ) \ do { \ - GLuint offset = (_x + xo)*4 + (_y + yo)*pitch; \ + GLuint offset = (_x + xo + (_y + yo)*pitch)*4; \ GLuint tmp = *(GLuint *)(buf + offset); \ tmp &= 0xff000000; \ tmp |= ((d) & 0x00ffffff); \ @@ -268,7 +268,7 @@ do { \ } while (0) #define READ_DEPTH( d, _x, _y ) \ - d = *(GLuint *)(buf + (_x + xo)*4 + (_y + yo)*pitch) & 0x00ffffff; + d = *(GLuint *)(buf + (_x + xo + (_y + yo)*pitch)*4) & 0x00ffffff; #define TAG(x) radeon##x##_24_8_LINEAR #include "depthtmp.h" @@ -426,7 +426,6 @@ static void radeonSpanRenderFinish(GLcontext * ctx) void radeonInitSpanFuncs(GLcontext * ctx) { - r200ContextPtr rmesa = R200_CONTEXT(ctx); radeonContextPtr radeon = RADEON_CONTEXT(ctx); struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx); diff --git a/src/mesa/drivers/dri/r300/radeon_state.c b/src/mesa/drivers/dri/r300/radeon_state.c new file mode 100644 index 0000000000..19af781d7b --- /dev/null +++ b/src/mesa/drivers/dri/r300/radeon_state.c @@ -0,0 +1,88 @@ +/************************************************************************** + +Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + +The Weather Channel (TM) funded Tungsten Graphics to develop the +initial release of the Radeon 8500 driver under the XFree86 license. +This notice must be preserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Keith Whitwell + */ + +#include "glheader.h" +#include "imports.h" +#include "api_arrayelt.h" +#include "enums.h" +#include "colormac.h" +#include "light.h" + +#include "swrast/swrast.h" +#include "array_cache/acache.h" +#include "tnl/tnl.h" +#include "tnl/t_pipeline.h" +#include "swrast_setup/swrast_setup.h" + +#include "r200_context.h" +#include "radeon_ioctl.h" +#include "radeon_state.h" +#include "r200_state.h" + + +/** + * Update cliprects and scissors. + */ +void radeonSetCliprects(radeonContextPtr radeon, GLenum mode) +{ + __DRIdrawablePrivate *dPriv = radeon->dri.drawable; + + switch (mode) { + case GL_FRONT_LEFT: + radeon->numClipRects = dPriv->numClipRects; + radeon->pClipRects = dPriv->pClipRects; + break; + case GL_BACK_LEFT: + /* Can't ignore 2d windows if we are page flipping. + */ + if (dPriv->numBackClipRects == 0 || radeon->doPageFlip) { + radeon->numClipRects = dPriv->numClipRects; + radeon->pClipRects = dPriv->pClipRects; + } else { + radeon->numClipRects = dPriv->numBackClipRects; + radeon->pClipRects = dPriv->pBackClipRects; + } + break; + default: + fprintf(stderr, "bad mode in radeonSetCliprects\n"); + return; + } + + if (IS_FAMILY_R200(radeon)) { + if (((r200ContextPtr)radeon)->state.scissor.enabled) + r200RecalcScissorRects((r200ContextPtr)radeon); + } +} + diff --git a/src/mesa/drivers/dri/r300/radeon_state.h b/src/mesa/drivers/dri/r300/radeon_state.h new file mode 100644 index 0000000000..8b2698d9bc --- /dev/null +++ b/src/mesa/drivers/dri/r300/radeon_state.h @@ -0,0 +1,42 @@ +/* +Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + +The Weather Channel (TM) funded Tungsten Graphics to develop the +initial release of the Radeon 8500 driver under the XFree86 license. +This notice must be preserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Keith Whitwell + */ + +#ifndef __RADEON_STATE_H__ +#define __RADEON_STATE_H__ + +#include "radeon_context.h" + +extern void radeonSetCliprects(radeonContextPtr radeon, GLenum mode); + +#endif -- cgit v1.2.3