From 48dad9c93fd6fb46bf33a58a87de79eb5ffd6e67 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Mon, 26 Oct 2009 10:42:45 -0600 Subject: intel: fix GL state bugs in intel_texture_bitmap() Need to push texture state and polygon state too. Fixes rendering glitches seen in progs/demos/engine when changing the rendering mode (wireframe, texture modes). This makes bitmap rendering a little slower, unfortunately. --- src/mesa/drivers/dri/intel/intel_pixel_bitmap.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c index b543a0bbc3..18e6ebd17c 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c @@ -435,13 +435,14 @@ intel_texture_bitmap(GLcontext * ctx, } /* Save GL state before we start setting up our drawing */ - _mesa_PushAttrib(GL_ENABLE_BIT | GL_CURRENT_BIT | - GL_VIEWPORT_BIT); + _mesa_PushAttrib(GL_ENABLE_BIT | GL_CURRENT_BIT | GL_POLYGON_BIT | + GL_TEXTURE_BIT | GL_VIEWPORT_BIT); _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT | GL_CLIENT_PIXEL_STORE_BIT); old_active_texture = ctx->Texture.CurrentUnit; _mesa_Disable(GL_POLYGON_STIPPLE); + _mesa_PolygonMode(GL_FRONT_AND_BACK, GL_FILL); /* Upload our bitmap data to an alpha texture */ _mesa_ActiveTextureARB(GL_TEXTURE0_ARB); @@ -501,8 +502,6 @@ intel_texture_bitmap(GLcontext * ctx, meta_restore_vertex_program(&intel->meta); _mesa_PopClientAttrib(); - _mesa_Disable(GL_TEXTURE_2D); /* asserted that it was disabled at entry */ - _mesa_ActiveTextureARB(GL_TEXTURE0_ARB + old_active_texture); _mesa_PopAttrib(); _mesa_DeleteTextures(1, &texname); -- cgit v1.2.3 From f9e334cb32152fd342ac6b1dd4776215af6e1d49 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 27 Oct 2009 09:27:44 -0600 Subject: Revert "i965: fix hacked Fallback usage in brw_prepare_vertices()" This reverts commit 8810b8f67135185d1044746bb861fe2ff997626c. It turns out the i965 driver uses the intel->Fallback field as a boolean, not as a bitmask. The intelFallback() function is a no-op in the i965 driver. It would have been nice if there were some comments about this. I'll fix that next... --- src/mesa/drivers/dri/i965/brw_context.h | 2 -- src/mesa/drivers/dri/i965/brw_draw_upload.c | 6 ++---- 2 files changed, 2 insertions(+), 6 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index b1e7ec8465..da0e091bfd 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -116,8 +116,6 @@ */ -#define BRW_FALLBACK_DRAW (INTEL_FALLBACK_DRIVER << 0) - #define BRW_MAX_CURBE (32*16) struct brw_context; diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 4f8ceb37bd..9d089e113e 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -375,10 +375,9 @@ static void brw_prepare_vertices(struct brw_context *brw) * isn't an issue at this point. */ if (brw->vb.nr_enabled >= BRW_VEP_MAX) { - FALLBACK(intel, BRW_FALLBACK_DRAW, GL_TRUE); + intel->Fallback = 1; return; } - FALLBACK(intel, BRW_FALLBACK_DRAW, GL_FALSE); for (i = 0; i < brw->vb.nr_enabled; i++) { struct brw_vertex_element *input = brw->vb.enabled[i]; @@ -428,10 +427,9 @@ static void brw_prepare_vertices(struct brw_context *brw) /* Position array not properly enabled: */ if (input->glarray->StrideB == 0) { - FALLBACK(intel, BRW_FALLBACK_DRAW, GL_TRUE); + intel->Fallback = 1; return; } - FALLBACK(intel, BRW_FALLBACK_DRAW, GL_FALSE); interleave = input->glarray->StrideB; ptr = input->glarray->Ptr; -- cgit v1.2.3 From 43dc91f8bbb69499a6a0326a78e434b313f73c2c Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 27 Oct 2009 09:31:31 -0600 Subject: i965: be clear that the Fallback field is a boolean, not a bitfield --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 4 ++-- src/mesa/drivers/dri/i965/brw_fallback.c | 6 +++++- src/mesa/drivers/dri/i965/brw_state_upload.c | 2 +- 3 files changed, 8 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 9d089e113e..348c66154f 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -375,7 +375,7 @@ static void brw_prepare_vertices(struct brw_context *brw) * isn't an issue at this point. */ if (brw->vb.nr_enabled >= BRW_VEP_MAX) { - intel->Fallback = 1; + intel->Fallback = GL_TRUE; /* boolean, not bitfield */ return; } @@ -427,7 +427,7 @@ static void brw_prepare_vertices(struct brw_context *brw) /* Position array not properly enabled: */ if (input->glarray->StrideB == 0) { - intel->Fallback = 1; + intel->Fallback = GL_TRUE; /* boolean, not bitfield */ return; } diff --git a/src/mesa/drivers/dri/i965/brw_fallback.c b/src/mesa/drivers/dri/i965/brw_fallback.c index d27c6c24ca..562a17844b 100644 --- a/src/mesa/drivers/dri/i965/brw_fallback.c +++ b/src/mesa/drivers/dri/i965/brw_fallback.c @@ -133,7 +133,11 @@ const struct brw_tracked_state brw_check_fallback = { -/* Not used: +/** + * Called by the INTEL_FALLBACK() macro. + * NOTE: this is a no-op for the i965 driver. The brw->intel.Fallback + * field is treated as a boolean, not a bitmask. It's only set in a + * couple of places. */ void intelFallback( struct intel_context *intel, GLuint bit, GLboolean mode ) { diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index b817b741e7..ee447afa62 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -308,7 +308,7 @@ void brw_validate_state( struct brw_context *brw ) if (brw->state.dirty.brw & BRW_NEW_CONTEXT) brw_clear_batch_cache(brw); - brw->intel.Fallback = 0; + brw->intel.Fallback = GL_FALSE; /* boolean, not bitfield */ /* do prepare stage for all atoms */ for (i = 0; i < Elements(atoms); i++) { -- cgit v1.2.3 From 70b17db918a2784296434877a43b4c4036be792a Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 27 Oct 2009 10:26:09 -0700 Subject: i915: Fix driver for the miptree x/y offset changes. Bug #24734. --- src/mesa/drivers/dri/i915/i830_texstate.c | 13 ++++++++++--- src/mesa/drivers/dri/i915/i915_texstate.c | 13 ++++++++++--- 2 files changed, 20 insertions(+), 6 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c index 6f998fa6f7..20ff46b0b0 100644 --- a/src/mesa/drivers/dri/i915/i830_texstate.c +++ b/src/mesa/drivers/dri/i915/i830_texstate.c @@ -160,11 +160,18 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) pitch = intelObj->pitchOverride; } else { + GLuint dst_x, dst_y; + + intel_miptree_get_image_offset(intelObj->mt, intelObj->firstLevel, 0, 0, + &dst_x, &dst_y); + dri_bo_reference(intelObj->mt->region->buffer); i830->state.tex_buffer[unit] = intelObj->mt->region->buffer; - i830->state.tex_offset[unit] = intel_miptree_image_offset(intelObj->mt, - 0, intelObj-> - firstLevel); + /* XXX: This calculation is probably broken for tiled images with + * a non-page-aligned offset. + */ + i830->state.tex_offset[unit] = (dst_x + dst_y * intelObj->mt->pitch) * + intelObj->mt->cpp; format = translate_texture_format(firstImage->TexFormat->MesaFormat, firstImage->InternalFormat); diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index 32d4b30cf9..998a04f794 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -171,11 +171,18 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) pitch = intelObj->pitchOverride; } else { + GLuint dst_x, dst_y; + + intel_miptree_get_image_offset(intelObj->mt, intelObj->firstLevel, 0, 0, + &dst_x, &dst_y); + dri_bo_reference(intelObj->mt->region->buffer); i915->state.tex_buffer[unit] = intelObj->mt->region->buffer; - i915->state.tex_offset[unit] = intel_miptree_image_offset(intelObj->mt, - 0, intelObj-> - firstLevel); + /* XXX: This calculation is probably broken for tiled images with + * a non-page-aligned offset. + */ + i915->state.tex_offset[unit] = (dst_x + dst_y * intelObj->mt->pitch) * + intelObj->mt->cpp; format = translate_texture_format(firstImage->TexFormat->MesaFormat, firstImage->InternalFormat, -- cgit v1.2.3 From 22575abdec73312e010e016e381f7cf8761ad652 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 27 Oct 2009 16:39:01 -0600 Subject: intel: fix src offset bug in do_copy_texsubimage() Use src->draw_offset intead of zero. Zero usually worked, except when the src renderbuffer is actually a texture mipmap level higher than zero. Fixes progs/test/blitfb.c test. --- src/mesa/drivers/dri/intel/intel_tex_copy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c index 9d58b11b14..95dee60f9c 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_copy.c +++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c @@ -158,7 +158,7 @@ do_copy_texsubimage(struct intel_context *intel, intelImage->mt->cpp, src_pitch, src->buffer, - 0, + src->draw_offset, src->tiling, intelImage->mt->pitch, dst_bo, -- cgit v1.2.3 From b7eea8c616092f5473a323fba585b04c47ae2010 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 27 Oct 2009 17:34:29 -0600 Subject: intel: added region draw_x/y offsets in x/y_tile_swizzle() funcs This fixes the second part of bug 23552. --- src/mesa/drivers/dri/intel/intel_span.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index 8df4990880..e71366a182 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -163,6 +163,9 @@ static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb, int x_tile_number, y_tile_number; int tile_off, tile_base; + x += irb->region->draw_x; + y += irb->region->draw_y; + tile_stride = (irb->region->pitch * irb->region->cpp) << 3; xbyte = x * irb->region->cpp; @@ -218,6 +221,9 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb, int x_tile_number, y_tile_number; int tile_off, tile_base; + x += irb->region->draw_x; + y += irb->region->draw_y; + tile_stride = (irb->region->pitch * irb->region->cpp) << 5; xbyte = x * irb->region->cpp; -- cgit v1.2.3 From 2643a7ba2972ab8284aa911cc92ab0be163cb92f Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 20 Oct 2009 14:51:53 -0700 Subject: intel: Fix flipped condition in ARB_sync GetSYnciv(GL_SYNC_STATUS). Bug #24435 (cherry picked from commit d56125a298106d81e10674f1c4b3b43b51a5139d) --- src/mesa/drivers/dri/intel/intel_syncobj.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_syncobj.c b/src/mesa/drivers/dri/intel/intel_syncobj.c index 1286fe929b..0d7889d3c2 100644 --- a/src/mesa/drivers/dri/intel/intel_syncobj.c +++ b/src/mesa/drivers/dri/intel/intel_syncobj.c @@ -114,7 +114,7 @@ static void intel_check_sync(GLcontext *ctx, struct gl_sync_object *s) { struct intel_sync_object *sync = (struct intel_sync_object *)s; - if (sync->bo && drm_intel_bo_busy(sync->bo)) { + if (sync->bo && !drm_intel_bo_busy(sync->bo)) { drm_intel_bo_unreference(sync->bo); sync->bo = NULL; s->StatusFlag = 1; -- cgit v1.2.3 From a7d0665c00053839065592c339bfb298187a82be Mon Sep 17 00:00:00 2001 From: Vinson Lee Date: Wed, 28 Oct 2009 11:09:50 -0600 Subject: intel: Fix memory leak in event of mip tree allocation failure Signed-off-by: Brian Paul --- src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index 0589d82db2..459e8fbd4b 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -134,8 +134,10 @@ intel_miptree_create(struct intel_context *intel, /* * pitch == 0 || height == 0 indicates the null texture */ - if (!mt || !mt->pitch || !mt->total_height) + if (!mt || !mt->pitch || !mt->total_height) { + free(mt); return NULL; + } mt->region = intel_region_alloc(intel, tiling, -- cgit v1.2.3