From 881ec3a81455f8449d06429811107e1f955f2c60 Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Sat, 12 Jun 2010 21:30:20 -0700 Subject: i965: Add support for math instructions in the gen6 WM. --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 175899b026..34490b7f16 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -966,10 +966,25 @@ void brw_math_16( struct brw_compile *p, struct brw_reg src, GLuint precision ) { + struct intel_context *intel = &p->brw->intel; struct brw_instruction *insn; GLuint msg_length = (function == BRW_MATH_FUNCTION_POW) ? 2 : 1; GLuint response_length = (function == BRW_MATH_FUNCTION_SINCOS) ? 2 : 1; + if (intel->gen >= 6) { + insn = next_insn(p, BRW_OPCODE_MATH); + + /* Math is the same ISA format as other opcodes, except that CondModifier + * becomes FC[3:0] and ThreadCtrl becomes FC[5:4]. + */ + insn->header.destreg__conditionalmod = function; + + brw_set_dest(insn, dest); + brw_set_src0(insn, src); + brw_set_src1(insn, brw_null_reg()); + return; + } + /* First instruction: */ brw_push_insn_state(p); -- cgit v1.2.3