From 9390af0d9636ed8e985ff22cdbbbf9b12c3a7586 Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Tue, 18 May 2010 16:22:40 +0800 Subject: i965: fix PIPE_CONTROL command for gen6. Signed-off-by: Zou Nan hai Reviewed-by: Eric Anholt --- src/mesa/drivers/dri/intel/intel_batchbuffer.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c index de5134008f..446ce29984 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c @@ -275,7 +275,16 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch) { struct intel_context *intel = batch->intel; - if (intel->gen >= 4) { + if (intel->gen >= 6) { + BEGIN_BATCH(4); + OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH | + PIPE_CONTROL_WRITE_FLUSH | + PIPE_CONTROL_NO_WRITE); + OUT_BATCH(0); /* write address */ + OUT_BATCH(0); /* write data */ + ADVANCE_BATCH(); + } else if (intel->gen >= 4) { BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_PIPE_CONTROL | PIPE_CONTROL_WRITE_FLUSH | -- cgit v1.2.3