From dd9eb8774ad7918187afebf8cd3be6f4b80f0f3b Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 8 Dec 2009 16:15:07 -0800 Subject: i965: Enable the accelerated ReadPixels path on gen4 along with pre-gen4. Passes piglit pbo-read-argb8888, and doesn't otherwise regress quick.tests. --- src/mesa/drivers/dri/intel/intel_pixel_read.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_pixel_read.c b/src/mesa/drivers/dri/intel/intel_pixel_read.c index 4707500180..20424e2e58 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_read.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_read.c @@ -285,11 +285,11 @@ intelReadPixels(GLcontext * ctx, intelFlush(ctx); -#ifdef I915 if (do_blit_readpixels (ctx, x, y, width, height, format, type, pack, pixels)) return; +#ifdef I915 if (do_texture_readpixels (ctx, x, y, width, height, format, type, pack, pixels)) return; -- cgit v1.2.3 From 33a120e4761a661736ea64a3efc2e3831ac5600a Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Wed, 9 Dec 2009 10:51:52 +0200 Subject: r600: fix state size prediction after dc0777d3 --- src/mesa/drivers/dri/r600/r700_chip.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index d8661b4439..dacc2ccc4c 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -1134,7 +1134,11 @@ static int check_blnd(GLcontext *ctx, struct radeon_state_atom *atom) count += 3; if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) { - for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) { + /* targets are enabled in r700SetRenderTarget but state + size is calculated before that. Until MRT's are done + hardcode target0 as enabled. */ + count += 3; + for (ui = 1; ui < R700_MAX_RENDER_TARGETS; ui++) { if (r700->render_target[ui].enabled) count += 3; } -- cgit v1.2.3 From 539a14a1dd5a0d277b193d9cd2d06423ed98dc8a Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 9 Dec 2009 11:36:45 -0800 Subject: intel: Flush the render/texture cache when finishing render to texture. Back when we were flushing the entire batch at BindFramebuffer, the kernel would notice the domain transition when someone went to texture from it and flush for us. We no longer do the batch flushing every time, so we get to do aggressive flushing until we move batchbuffer handling to libdrm. Fixes piglit fbo-flushing. Bug #25377. No noticeable performance loss on cairo-gl (so this is better than batch flushing). --- src/mesa/drivers/dri/intel/intel_fbo.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 5615040946..679fa2f82a 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -37,6 +37,7 @@ #include "drivers/common/meta.h" #include "intel_context.h" +#include "intel_batchbuffer.h" #include "intel_buffers.h" #include "intel_fbo.h" #include "intel_mipmap_tree.h" @@ -591,6 +592,7 @@ static void intel_finish_render_texture(GLcontext * ctx, struct gl_renderbuffer_attachment *att) { + struct intel_context *intel = intel_context(ctx); struct gl_texture_object *tex_obj = att->Texture; struct gl_texture_image *image = tex_obj->Image[att->CubeMapFace][att->TextureLevel]; @@ -598,8 +600,14 @@ intel_finish_render_texture(GLcontext * ctx, /* Flag that this image may now be validated into the object's miptree. */ intel_image->used_as_render_target = GL_FALSE; -} + /* Since we've (probably) rendered to the texture and will (likely) use + * it in the texture domain later on in this batchbuffer, flush the + * batch. Once again, we wish for a domain tracker in libdrm to cover + * usage inside of a batchbuffer like GEM does in the kernel. + */ + intel_batchbuffer_emit_mi_flush(intel->batch); +} /** * Do additional "completeness" testing of a framebuffer object. -- cgit v1.2.3 From 3078bd136d6ee1d9ad16b4c834cad23b005304a4 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 8 Dec 2009 09:57:27 -0800 Subject: intel: Axe intel_renderbuffer::texformat Since the texformat branch merge, the value of intel_renderbuffer::texformat is just a copy of gl_renderbuffer::Format. --- src/mesa/drivers/dri/i915/i830_vtbl.c | 4 ++-- src/mesa/drivers/dri/i915/i915_vtbl.c | 4 ++-- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 ++-- src/mesa/drivers/dri/intel/intel_blit.c | 4 ++-- src/mesa/drivers/dri/intel/intel_fbo.c | 13 ++----------- src/mesa/drivers/dri/intel/intel_fbo.h | 2 -- src/mesa/drivers/dri/intel/intel_span.c | 6 +++--- 7 files changed, 13 insertions(+), 24 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c index a6f554701e..e8c8d5a048 100644 --- a/src/mesa/drivers/dri/i915/i830_vtbl.c +++ b/src/mesa/drivers/dri/i915/i830_vtbl.c @@ -645,7 +645,7 @@ i830_state_draw_region(struct intel_context *intel, DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z); /* .5 */ if (irb != NULL) { - switch (irb->texformat) { + switch (irb->Base.Format) { case MESA_FORMAT_ARGB8888: case MESA_FORMAT_XRGB8888: value |= DV_PF_8888; @@ -661,7 +661,7 @@ i830_state_draw_region(struct intel_context *intel, break; default: _mesa_problem(ctx, "Bad renderbuffer format: %d\n", - irb->texformat); + irb->Base.Format); } } diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index 77ba8d5581..ff97e5a944 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -587,7 +587,7 @@ i915_state_draw_region(struct intel_context *intel, DSTORG_VERT_BIAS(0x8) | /* .5 */ LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL); if (irb != NULL) { - switch (irb->texformat) { + switch (irb->Base.Format) { case MESA_FORMAT_ARGB8888: case MESA_FORMAT_XRGB8888: value |= DV_PF_8888; @@ -603,7 +603,7 @@ i915_state_draw_region(struct intel_context *intel, break; default: _mesa_problem(ctx, "Bad renderbuffer format: %d\n", - irb->texformat); + irb->Base.Format); } } diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 47035cc6fc..b7b6eaec2b 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -537,7 +537,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw, region_bo = region->buffer; key.surface_type = BRW_SURFACE_2D; - switch (irb->texformat) { + switch (irb->Base.Format) { case MESA_FORMAT_ARGB8888: key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; break; @@ -554,7 +554,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw, key.surface_format = BRW_SURFACEFORMAT_B4G4R4A4_UNORM; break; default: - _mesa_problem(ctx, "Bad renderbuffer format: %d\n", irb->texformat); + _mesa_problem(ctx, "Bad renderbuffer format: %d\n", irb->Base.Format); } key.tiling = region->tiling; if (brw->intel.intelScreen->driScrnPriv->dri2.enabled) { diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index 817223da41..9f638b0ef9 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -496,7 +496,7 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]); CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]); - switch (irb->texformat) { + switch (irb->Base.Format) { case MESA_FORMAT_ARGB8888: case MESA_FORMAT_XRGB8888: clearVal = intel->ClearColor8888; @@ -514,7 +514,7 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) break; default: _mesa_problem(ctx, "Unexpected renderbuffer format: %d\n", - irb->texformat); + irb->Base.Format); clearVal = 0; } } diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 679fa2f82a..649fd1a78f 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -117,7 +117,6 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, case GL_RGB5: rb->Format = MESA_FORMAT_RGB565; rb->DataType = GL_UNSIGNED_BYTE; - irb->texformat = MESA_FORMAT_RGB565; cpp = 2; break; case GL_RGB: @@ -125,9 +124,8 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, case GL_RGB10: case GL_RGB12: case GL_RGB16: - rb->Format = MESA_FORMAT_ARGB8888; + rb->Format = MESA_FORMAT_ARGB8888; /* XXX: Need xrgb8888 */ rb->DataType = GL_UNSIGNED_BYTE; - irb->texformat = MESA_FORMAT_ARGB8888; /* XXX: Need xrgb8888 */ cpp = 4; break; case GL_RGBA: @@ -140,7 +138,6 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, case GL_RGBA16: rb->Format = MESA_FORMAT_ARGB8888; rb->DataType = GL_UNSIGNED_BYTE; - irb->texformat = MESA_FORMAT_ARGB8888; cpp = 4; break; case GL_STENCIL_INDEX: @@ -152,13 +149,11 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, rb->Format = MESA_FORMAT_S8_Z24; rb->DataType = GL_UNSIGNED_INT_24_8_EXT; cpp = 4; - irb->texformat = MESA_FORMAT_S8_Z24; break; case GL_DEPTH_COMPONENT16: rb->Format = MESA_FORMAT_Z16; rb->DataType = GL_UNSIGNED_SHORT; cpp = 2; - irb->texformat = MESA_FORMAT_Z16; break; case GL_DEPTH_COMPONENT: case GL_DEPTH_COMPONENT24: @@ -166,14 +161,12 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, rb->Format = MESA_FORMAT_S8_Z24; rb->DataType = GL_UNSIGNED_INT_24_8_EXT; cpp = 4; - irb->texformat = MESA_FORMAT_S8_Z24; break; case GL_DEPTH_STENCIL_EXT: case GL_DEPTH24_STENCIL8_EXT: rb->Format = MESA_FORMAT_S8_Z24; rb->DataType = GL_UNSIGNED_INT_24_8_EXT; cpp = 4; - irb->texformat = MESA_FORMAT_S8_Z24; break; default: _mesa_problem(ctx, @@ -347,7 +340,6 @@ intel_create_renderbuffer(gl_format format) irb->Base.Format = format; irb->Base.InternalFormat = irb->Base._BaseFormat; - irb->texformat = format; /* intel-specific methods */ irb->Base.Delete = intel_delete_renderbuffer; @@ -424,7 +416,6 @@ static GLboolean intel_update_wrapper(GLcontext *ctx, struct intel_renderbuffer *irb, struct gl_texture_image *texImage) { - irb->texformat = texImage->TexFormat; gl_format texFormat; if (texImage->TexFormat == MESA_FORMAT_ARGB8888) { @@ -640,7 +631,7 @@ intel_validate_framebuffer(GLcontext *ctx, struct gl_framebuffer *fb) continue; } - switch (irb->texformat) { + switch (irb->Base.Format) { case MESA_FORMAT_ARGB8888: case MESA_FORMAT_XRGB8888: case MESA_FORMAT_RGB565: diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h index 50a8a95985..fa43077d6a 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.h +++ b/src/mesa/drivers/dri/intel/intel_fbo.h @@ -62,8 +62,6 @@ struct intel_renderbuffer struct gl_renderbuffer Base; struct intel_region *region; - gl_format texformat; - GLuint vbl_pending; /**< vblank sequence number of pending flip */ uint8_t *span_cache; diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index 3607c7dded..f02fbe9875 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -624,7 +624,7 @@ intel_set_span_functions(struct intel_context *intel, tiling = I915_TILING_NONE; if (intel->intelScreen->kernel_exec_fencing) { - switch (irb->texformat) { + switch (irb->Base.Format) { case MESA_FORMAT_RGB565: intel_gttmap_InitPointers_RGB565(rb); break; @@ -667,13 +667,13 @@ intel_set_span_functions(struct intel_context *intel, default: _mesa_problem(NULL, "Unexpected MesaFormat %d in intelSetSpanFunctions", - irb->texformat); + irb->Base.Format); break; } return; } - switch (irb->texformat) { + switch (irb->Base.Format) { case MESA_FORMAT_RGB565: switch (tiling) { case I915_TILING_NONE: -- cgit v1.2.3 From 4eee46efcb7e1f737b7115caf48ddb3b77408626 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 8 Dec 2009 15:51:18 -0800 Subject: intel: softwareBuffer in intel_alloc_renderbuffer_storage was always false, remove --- src/mesa/drivers/dri/intel/intel_fbo.c | 37 ++++++++++++++-------------------- 1 file changed, 15 insertions(+), 22 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 649fd1a78f..9a304b0351 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -106,8 +106,8 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, { struct intel_context *intel = intel_context(ctx); struct intel_renderbuffer *irb = intel_renderbuffer(rb); - GLboolean softwareBuffer = GL_FALSE; int cpp; + GLuint pitch; ASSERT(rb->Name != 0); @@ -184,32 +184,25 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, } /* allocate new memory region/renderbuffer */ - if (softwareBuffer) { - return _mesa_soft_renderbuffer_storage(ctx, rb, internalFormat, - width, height); - } - else { - /* Choose a pitch to match hardware requirements: - */ - GLuint pitch = ((cpp * width + 63) & ~63) / cpp; - /* alloc hardware renderbuffer */ - DBG("Allocating %d x %d Intel RBO (pitch %d)\n", width, - height, pitch); + /* Choose a pitch to match hardware requirements: + */ + pitch = ((cpp * width + 63) & ~63) / cpp; - irb->region = intel_region_alloc(intel, I915_TILING_NONE, - cpp, width, height, pitch, - GL_TRUE); - if (!irb->region) - return GL_FALSE; /* out of memory? */ + /* alloc hardware renderbuffer */ + DBG("Allocating %d x %d Intel RBO (pitch %d)\n", width, height, pitch); - ASSERT(irb->region->buffer); + irb->region = intel_region_alloc(intel, I915_TILING_NONE, cpp, + width, height, pitch, GL_TRUE); + if (!irb->region) + return GL_FALSE; /* out of memory? */ - rb->Width = width; - rb->Height = height; + ASSERT(irb->region->buffer); - return GL_TRUE; - } + rb->Width = width; + rb->Height = height; + + return GL_TRUE; } -- cgit v1.2.3 From 0f01674a584ea6df96acf91d7cd3b8a9b48ee65e Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 8 Dec 2009 16:06:13 -0800 Subject: intel: Use texformat accessor to get bytes-per-pixel --- src/mesa/drivers/dri/intel/intel_fbo.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 9a304b0351..5a67cb1388 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -117,7 +117,6 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, case GL_RGB5: rb->Format = MESA_FORMAT_RGB565; rb->DataType = GL_UNSIGNED_BYTE; - cpp = 2; break; case GL_RGB: case GL_RGB8: @@ -126,7 +125,6 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, case GL_RGB16: rb->Format = MESA_FORMAT_ARGB8888; /* XXX: Need xrgb8888 */ rb->DataType = GL_UNSIGNED_BYTE; - cpp = 4; break; case GL_RGBA: case GL_RGBA2: @@ -138,7 +136,6 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, case GL_RGBA16: rb->Format = MESA_FORMAT_ARGB8888; rb->DataType = GL_UNSIGNED_BYTE; - cpp = 4; break; case GL_STENCIL_INDEX: case GL_STENCIL_INDEX1_EXT: @@ -148,25 +145,21 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, /* alloc a depth+stencil buffer */ rb->Format = MESA_FORMAT_S8_Z24; rb->DataType = GL_UNSIGNED_INT_24_8_EXT; - cpp = 4; break; case GL_DEPTH_COMPONENT16: rb->Format = MESA_FORMAT_Z16; rb->DataType = GL_UNSIGNED_SHORT; - cpp = 2; break; case GL_DEPTH_COMPONENT: case GL_DEPTH_COMPONENT24: case GL_DEPTH_COMPONENT32: rb->Format = MESA_FORMAT_S8_Z24; rb->DataType = GL_UNSIGNED_INT_24_8_EXT; - cpp = 4; break; case GL_DEPTH_STENCIL_EXT: case GL_DEPTH24_STENCIL8_EXT: rb->Format = MESA_FORMAT_S8_Z24; rb->DataType = GL_UNSIGNED_INT_24_8_EXT; - cpp = 4; break; default: _mesa_problem(ctx, @@ -175,6 +168,7 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, } rb->_BaseFormat = _mesa_base_fbo_format(ctx, internalFormat); + cpp = _mesa_get_format_bytes(rb->Format); intelFlush(ctx); -- cgit v1.2.3 From 430876cd3a70d3b701d136b825518140888f96c8 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 8 Dec 2009 17:03:20 -0800 Subject: intel: name in intel_create_renderbuffer was always 0, remove --- src/mesa/drivers/dri/intel/intel_fbo.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 5a67cb1388..970ffb2e4d 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -278,7 +278,6 @@ intel_create_renderbuffer(gl_format format) GET_CURRENT_CONTEXT(ctx); struct intel_renderbuffer *irb; - const GLuint name = 0; irb = CALLOC_STRUCT(intel_renderbuffer); if (!irb) { @@ -286,7 +285,7 @@ intel_create_renderbuffer(gl_format format) return NULL; } - _mesa_init_renderbuffer(&irb->Base, name); + _mesa_init_renderbuffer(&irb->Base, 0); irb->Base.ClassID = INTEL_RB_CLASS; switch (format) { -- cgit v1.2.3 From ffc1f299e9eaa6eaa4b5586b9fb13132564bd3ae Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 8 Dec 2009 21:10:45 -0800 Subject: spantmp2: Add support for GL_BGR / GL_UNSIGNED_INT_8_8_8_8_REV This is really for MESA_FORMAT_XRGB8888. Clearly spantmp2.h needs some re-work. Any volunteers? --- src/mesa/drivers/dri/common/spantmp2.h | 57 ++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/common/spantmp2.h b/src/mesa/drivers/dri/common/spantmp2.h index 95f97414a9..447f3d15b9 100644 --- a/src/mesa/drivers/dri/common/spantmp2.h +++ b/src/mesa/drivers/dri/common/spantmp2.h @@ -356,6 +356,63 @@ } while (0) # endif +#elif (SPANTMP_PIXEL_FMT == GL_BGR) && (SPANTMP_PIXEL_TYPE == GL_UNSIGNED_INT_8_8_8_8_REV) + +/** + ** GL_BGR, GL_UNSIGNED_INT_8_8_8_8_REV + ** + ** This is really for MESA_FORMAT_XRGB8888. The spantmp code needs to be + ** kicked to the curb, and we need to just code-gen this. + **/ + +#ifndef GET_VALUE +#ifndef GET_PTR +#define GET_PTR(_x, _y) ( buf + (_x) * 4 + (_y) * pitch) +#endif + +#define GET_VALUE(_x, _y) *(volatile GLuint *)(GET_PTR(_x, _y)) +#define PUT_VALUE(_x, _y, _v) *(volatile GLuint *)(GET_PTR(_x, _y)) = (_v) +#endif /* GET_VALUE */ + +# define INIT_MONO_PIXEL(p, color) \ + p = PACK_COLOR_8888(0xff, color[0], color[1], color[2]) + +# define WRITE_RGBA(_x, _y, r, g, b, a) \ + PUT_VALUE(_x, _y, ((r << 16) | \ + (g << 8) | \ + (b << 0) | \ + (0xff << 24))) + +#define WRITE_PIXEL(_x, _y, p) PUT_VALUE(_x, _y, p) + +# if defined( USE_X86_ASM ) +# define READ_RGBA(rgba, _x, _y) \ + do { \ + GLuint p = GET_VALUE(_x, _y); \ + __asm__ __volatile__( "bswap %0; rorl $8, %0" \ + : "=r" (p) : "0" (p) ); \ + ((GLuint *)rgba)[0] = p | 0xff000000; \ + } while (0) +# elif defined( MESA_BIG_ENDIAN ) + /* On PowerPC with GCC 3.4.2 the shift madness below becomes a single + * rotlwi instruction. It also produces good code on SPARC. + */ +# define READ_RGBA( rgba, _x, _y ) \ + do { \ + GLuint p = GET_VALUE(_x, _y); \ + *((uint32_t *) rgba) = (t << 8) | 0xff; \ + } while (0) +# else +# define READ_RGBA( rgba, _x, _y ) \ + do { \ + GLuint p = GET_VALUE(_x, _y); \ + rgba[0] = (p >> 16) & 0xff; \ + rgba[1] = (p >> 8) & 0xff; \ + rgba[2] = (p >> 0) & 0xff; \ + rgba[3] = 0xff; \ + } while (0) +# endif + #else #error SPANTMP_PIXEL_FMT must be set to a valid value! #endif -- cgit v1.2.3 From 4f2b2032f46939b6056f837a086e73f0417183fc Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 8 Dec 2009 21:12:18 -0800 Subject: intel: Use spantmp2 GL_BGR / GL_UNSIGNED_INT_8_8_8_8_REV for XRGB8888 --- src/mesa/drivers/dri/intel/intel_span.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index f02fbe9875..725ba5c97d 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -334,7 +334,7 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb, #include "intel_spantmp.h" /* x8r8g8b8 color span and pixel functions */ -#define INTEL_PIXEL_FMT GL_BGRA +#define INTEL_PIXEL_FMT GL_BGR #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV #define INTEL_READ_VALUE(offset) pread_xrgb8888(irb, offset) #define INTEL_WRITE_VALUE(offset, v) pwrite_xrgb8888(irb, offset, v) -- cgit v1.2.3 From eadd9b8e16e3b1ad35fec54f780a0f94ac43988f Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 8 Dec 2009 21:13:05 -0800 Subject: i965: Fix handling of drawing to MESA_FORMAT_XRGB8888 It turns out that 965 and friends cannot actually render to an xRGB surfaces. Instead, the surface has to be RGBA with writes to alpha disabled and the blend function modified to always use 1.0 for destination alpha. --- src/mesa/drivers/dri/i965/brw_cc.c | 34 ++++++++++++++++++++++++ src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 17 +++++++++--- 2 files changed, 48 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c index d4ccd28c9e..ab301b9a3a 100644 --- a/src/mesa/drivers/dri/i965/brw_cc.c +++ b/src/mesa/drivers/dri/i965/brw_cc.c @@ -34,6 +34,7 @@ #include "brw_state.h" #include "brw_defines.h" #include "brw_util.h" +#include "intel_fbo.h" #include "main/macros.h" #include "main/enums.h" @@ -89,6 +90,28 @@ struct brw_cc_unit_key { GLenum depth_func; }; +/** + * Modify blend function to force destination alpha to 1.0 + * + * If \c function specifies a blend function that uses destination alpha, + * replace it with a function that hard-wires destination alpha to 1.0. This + * is used when rendering to xRGB targets. + */ +static GLenum +fix_xRGB_alpha(GLenum function) +{ + switch (function) { + case GL_DST_ALPHA: + return GL_ONE; + + case GL_ONE_MINUS_DST_ALPHA: + case GL_SRC_ALPHA_SATURATE: + return GL_ZERO; + } + + return function; +} + static void cc_unit_populate_key(struct brw_context *brw, struct brw_cc_unit_key *key) { @@ -132,6 +155,17 @@ cc_unit_populate_key(struct brw_context *brw, struct brw_cc_unit_key *key) key->blend_dst_rgb = ctx->Color.BlendDstRGB; key->blend_src_a = ctx->Color.BlendSrcA; key->blend_dst_a = ctx->Color.BlendDstA; + + /* If the renderbuffer is XRGB, we have to frob the blend function to + * force the destination alpha to 1.0. This means replacing GL_DST_ALPHA + * with GL_ONE and GL_ONE_MINUS_DST_ALPAH with GL_ZERO. + */ + if (ctx->Visual.alphaBits == 0) { + key->blend_src_rgb = fix_xRGB_alpha(key->blend_src_rgb); + key->blend_src_a = fix_xRGB_alpha(key->blend_src_a); + key->blend_dst_rgb = fix_xRGB_alpha(key->blend_dst_rgb); + key->blend_dst_a = fix_xRGB_alpha(key->blend_dst_a); + } } key->alpha_enabled = ctx->Color.AlphaEnabled; diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index b7b6eaec2b..74cf66f9f8 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -538,11 +538,15 @@ brw_update_renderbuffer_surface(struct brw_context *brw, key.surface_type = BRW_SURFACE_2D; switch (irb->Base.Format) { + /* XRGB and ARGB are treated the same here because the chips in this + * family cannot render to XRGB targets. This means that we have to + * mask writes to alpha (ala glColorMask) and reconfigure the alpha + * blending hardware to use GL_ONE (or GL_ZERO) for cases where + * GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is used. + */ case MESA_FORMAT_ARGB8888: - key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; - break; case MESA_FORMAT_XRGB8888: - key.surface_format = BRW_SURFACEFORMAT_B8G8R8X8_UNORM; + key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; break; case MESA_FORMAT_RGB565: key.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM; @@ -579,6 +583,13 @@ brw_update_renderbuffer_surface(struct brw_context *brw, /* _NEW_COLOR */ memcpy(key.color_mask, ctx->Color.ColorMask, sizeof(key.color_mask)); + + /* As mentioned above, disable writes to the alpha component when the + * renderbuffer is XRGB. + */ + if (ctx->Visual.alphaBits == 0) + key.color_mask[3] = GL_FALSE; + key.color_blend = (!ctx->Color._LogicOpEnabled && ctx->Color.BlendEnabled); -- cgit v1.2.3 From cbdeb33209e782f011984a4b93cc0d36f567462e Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 8 Dec 2009 21:15:36 -0800 Subject: intel: Make RGB renderbuffers use XRGB8888 like we do for RGB system buffers. --- src/mesa/drivers/dri/intel/intel_fbo.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 970ffb2e4d..608f75b824 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -123,7 +123,7 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, case GL_RGB10: case GL_RGB12: case GL_RGB16: - rb->Format = MESA_FORMAT_ARGB8888; /* XXX: Need xrgb8888 */ + rb->Format = MESA_FORMAT_XRGB8888; rb->DataType = GL_UNSIGNED_BYTE; break; case GL_RGBA: @@ -294,10 +294,6 @@ intel_create_renderbuffer(gl_format format) irb->Base.DataType = GL_UNSIGNED_BYTE; break; case MESA_FORMAT_XRGB8888: - /* XXX this is a hack since XRGB surfaces don't seem to work - * properly yet. Reading the alpha channel returns 0 instead of 1. - */ - format = MESA_FORMAT_ARGB8888; irb->Base._BaseFormat = GL_RGB; irb->Base.DataType = GL_UNSIGNED_BYTE; break; -- cgit v1.2.3 From b4a6169412819cc3a027c6a118f0537911145a30 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 8 Dec 2009 23:24:58 -0800 Subject: intel: Make RGB textures use XRGB8888 --- src/mesa/drivers/dri/intel/intel_tex_format.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_tex_format.c b/src/mesa/drivers/dri/intel/intel_tex_format.c index bfa3dba1f5..87efb72cc5 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_format.c +++ b/src/mesa/drivers/dri/intel/intel_tex_format.c @@ -50,8 +50,7 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, if (format == GL_RGB && type == GL_UNSIGNED_SHORT_5_6_5) { return MESA_FORMAT_RGB565; } - /* XXX use MESA_FORMAT_XRGB8888 someday */ - return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_RGB565; + return do32bpt ? MESA_FORMAT_XRGB8888 : MESA_FORMAT_RGB565; case GL_RGBA8: case GL_RGB10_A2: @@ -70,8 +69,7 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, case GL_RGB10: case GL_RGB12: case GL_RGB16: - /* XXX use MESA_FORMAT_XRGB8888 someday */ - return MESA_FORMAT_ARGB8888; + return MESA_FORMAT_XRGB8888; case GL_RGB5: case GL_RGB4: -- cgit v1.2.3 From e624b77eb2d594cde053c73a530836e05227126a Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 8 Dec 2009 23:25:26 -0800 Subject: intel: Remove ARGB internal_format == GL_RGB hacks Now that XRGB is supported, we don't need to hack around cases of an RGBA format buffer with an internal format of GL_RGB. --- src/mesa/drivers/dri/i915/i830_texstate.c | 5 +-- src/mesa/drivers/dri/i915/i915_texstate.c | 5 +-- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 10 +---- src/mesa/drivers/dri/intel/intel_span.c | 49 +++++++----------------- 4 files changed, 17 insertions(+), 52 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c index f4bbb53b86..ce409b3a60 100644 --- a/src/mesa/drivers/dri/i915/i830_texstate.c +++ b/src/mesa/drivers/dri/i915/i830_texstate.c @@ -55,10 +55,7 @@ translate_texture_format(GLuint mesa_format, GLuint internal_format) case MESA_FORMAT_ARGB4444: return MAPSURF_16BIT | MT_16BIT_ARGB4444; case MESA_FORMAT_ARGB8888: - if (internal_format == GL_RGB) - return MAPSURF_32BIT | MT_32BIT_XRGB8888; - else - return MAPSURF_32BIT | MT_32BIT_ARGB8888; + return MAPSURF_32BIT | MT_32BIT_ARGB8888; case MESA_FORMAT_XRGB8888: return MAPSURF_32BIT | MT_32BIT_XRGB8888; case MESA_FORMAT_YCBCR_REV: diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index d6689af53f..f52ff2bcc4 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -56,10 +56,7 @@ translate_texture_format(gl_format mesa_format, GLuint internal_format, case MESA_FORMAT_ARGB4444: return MAPSURF_16BIT | MT_16BIT_ARGB4444; case MESA_FORMAT_ARGB8888: - if (internal_format == GL_RGB) - return MAPSURF_32BIT | MT_32BIT_XRGB8888; - else - return MAPSURF_32BIT | MT_32BIT_ARGB8888; + return MAPSURF_32BIT | MT_32BIT_ARGB8888; case MESA_FORMAT_XRGB8888: return MAPSURF_32BIT | MT_32BIT_XRGB8888; case MESA_FORMAT_YCBCR_REV: diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 74cf66f9f8..3f9b1fbfdc 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -94,20 +94,14 @@ static GLuint translate_tex_format( gl_format mesa_format, return BRW_SURFACEFORMAT_R8G8B8_UNORM; case MESA_FORMAT_ARGB8888: - if (internal_format == GL_RGB) - return BRW_SURFACEFORMAT_B8G8R8X8_UNORM; - else - return BRW_SURFACEFORMAT_B8G8R8A8_UNORM; + return BRW_SURFACEFORMAT_B8G8R8A8_UNORM; case MESA_FORMAT_XRGB8888: return BRW_SURFACEFORMAT_B8G8R8X8_UNORM; case MESA_FORMAT_RGBA8888_REV: _mesa_problem(NULL, "unexpected format in i965:translate_tex_format()"); - if (internal_format == GL_RGB) - return BRW_SURFACEFORMAT_R8G8B8X8_UNORM; - else - return BRW_SURFACEFORMAT_R8G8B8A8_UNORM; + return BRW_SURFACEFORMAT_R8G8B8A8_UNORM; case MESA_FORMAT_RGB565: return BRW_SURFACEFORMAT_B5G6R5_UNORM; diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index 725ba5c97d..34c3d9df74 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -638,13 +638,7 @@ intel_set_span_functions(struct intel_context *intel, intel_gttmap_InitPointers_xRGB8888(rb); break; case MESA_FORMAT_ARGB8888: - if (rb->_BaseFormat == GL_RGB) { - /* XXX remove this code someday when we enable XRGB surfaces */ - /* 8888 RGBx */ - intel_gttmap_InitPointers_xRGB8888(rb); - } else { - intel_gttmap_InitPointers_ARGB8888(rb); - } + intel_gttmap_InitPointers_ARGB8888(rb); break; case MESA_FORMAT_Z16: intel_gttmap_InitDepthPointers_z16(rb); @@ -731,35 +725,18 @@ intel_set_span_functions(struct intel_context *intel, } break; case MESA_FORMAT_ARGB8888: - if (rb->_BaseFormat == GL_RGB) { - /* XXX remove this code someday when we enable XRGB surfaces */ - /* 8888 RGBx */ - switch (tiling) { - case I915_TILING_NONE: - default: - intelInitPointers_xRGB8888(rb); - break; - case I915_TILING_X: - intel_XTile_InitPointers_xRGB8888(rb); - break; - case I915_TILING_Y: - intel_YTile_InitPointers_xRGB8888(rb); - break; - } - } else { - /* 8888 RGBA */ - switch (tiling) { - case I915_TILING_NONE: - default: - intelInitPointers_ARGB8888(rb); - break; - case I915_TILING_X: - intel_XTile_InitPointers_ARGB8888(rb); - break; - case I915_TILING_Y: - intel_YTile_InitPointers_ARGB8888(rb); - break; - } + /* 8888 RGBA */ + switch (tiling) { + case I915_TILING_NONE: + default: + intelInitPointers_ARGB8888(rb); + break; + case I915_TILING_X: + intel_XTile_InitPointers_ARGB8888(rb); + break; + case I915_TILING_Y: + intel_YTile_InitPointers_ARGB8888(rb); + break; } break; case MESA_FORMAT_Z16: -- cgit v1.2.3 From cb1dcb55f9884431a5e2b90e9208b42558a95611 Mon Sep 17 00:00:00 2001 From: Vinson Lee Date: Thu, 10 Dec 2009 18:21:59 -0800 Subject: i915: Add missing break statement in i915_debug_packet. --- src/mesa/drivers/dri/i915/i915_debug.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i915/i915_debug.c b/src/mesa/drivers/dri/i915/i915_debug.c index f7bb7ea44c..fecfac3033 100644 --- a/src/mesa/drivers/dri/i915/i915_debug.c +++ b/src/mesa/drivers/dri/i915/i915_debug.c @@ -806,6 +806,7 @@ static GLboolean i915_debug_packet( struct debug_stream *stream ) default: return debug(stream, "", 0); } + break; default: assert(0); return 0; -- cgit v1.2.3