From 6697311b21a65dbea9236413a3afc759a592afd7 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Mon, 11 May 2009 09:39:52 -0600
Subject: i965: handle extended swizzle terms (0,1) in get_src_reg()

Fixes failed assertion in progs/glsl/twoside.c (but still wrong rendering).
---
 src/mesa/drivers/dri/i965/brw_wm_glsl.c | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
index efe8b5126c..2b2df7329c 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
@@ -509,6 +509,14 @@ static struct brw_reg get_src_reg(struct brw_wm_compile *c,
     const GLuint nr = 1;
     const GLuint component = GET_SWZ(src->Swizzle, channel);
 
+    /* Extended swizzle terms */
+    if (component == SWIZZLE_ZERO) {
+       return brw_imm_f(0.0F);
+    }
+    else if (component == SWIZZLE_ONE) {
+       return brw_imm_f(1.0F);
+    }
+
     if (c->fp->use_const_buffer &&
         (src->File == PROGRAM_STATE_VAR ||
          src->File == PROGRAM_CONSTANT ||
-- 
cgit v1.2.3


From 64f36ff9fbe7e12c79cd72ceb68ed5967979445f Mon Sep 17 00:00:00 2001
From: Ian Romanick <ian.d.romanick@intel.com>
Date: Tue, 28 Apr 2009 10:08:57 -0700
Subject: Test either GL_FRONT_LEFT or GL_FRONT for front-buffer rendering

For non-stereo visuals, which is all we support, we treat
GL_FRONT_LEFT as GL_FRONT.  However, they are technically different,
and they have different enum values.  Test for either one to determine
if we're in front-buffer rendering mode.

This fix was suggested by Pierre Willenbrock.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit 2085cf24628be7cd297ab0f9ef5ce02bd5a006e2)
---
 src/mesa/drivers/dri/intel/intel_buffers.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/intel/intel_buffers.c b/src/mesa/drivers/dri/intel/intel_buffers.c
index ecac5bf020..b86cafea24 100644
--- a/src/mesa/drivers/dri/intel/intel_buffers.c
+++ b/src/mesa/drivers/dri/intel/intel_buffers.c
@@ -326,7 +326,8 @@ intelDrawBuffer(GLcontext * ctx, GLenum mode)
       const GLboolean was_front_buffer_rendering =
 	intel->is_front_buffer_rendering;
 
-      intel->is_front_buffer_rendering = (mode == GL_FRONT_LEFT);
+      intel->is_front_buffer_rendering = (mode == GL_FRONT_LEFT)
+	|| (mode == GL_FRONT);
 
       /* If we weren't front-buffer rendering before but we are now, make sure
        * that the front-buffer has actually been allocated.
-- 
cgit v1.2.3


From 0fc5fa85bf858ba2ad88995f65cc48b2dab1298d Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 12 May 2009 10:03:08 -0700
Subject: i915: Fix driver after HW glGenerateMipmap commit.

---
 src/mesa/drivers/dri/i915/Makefile | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/i915/Makefile b/src/mesa/drivers/dri/i915/Makefile
index 9f4bd1699f..beaf9a4b12 100644
--- a/src/mesa/drivers/dri/i915/Makefile
+++ b/src/mesa/drivers/dri/i915/Makefile
@@ -19,6 +19,7 @@ DRIVER_SOURCES = \
 	intel_batchbuffer.c \
 	intel_clear.c \
 	intel_extensions.c \
+	intel_generatemipmap.c \
 	intel_mipmap_tree.c \
 	intel_tex_layout.c \
 	intel_tex_image.c \
-- 
cgit v1.2.3


From aa422b262509bc0763a50f63a51a1730139ea52f Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Sun, 10 May 2009 09:45:43 -0700
Subject: intel: Map write-only buffer objects through the GTT when possible.

This looks to be a win of a few percent in cairogears with new vbo code,
thanks to not polluting caches.
---
 src/mesa/drivers/dri/intel/intel_buffer_objects.c | 16 ++++++++++++++--
 src/mesa/drivers/dri/intel/intel_buffer_objects.h |  1 +
 2 files changed, 15 insertions(+), 2 deletions(-)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.c b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
index f6b0d769c6..0db1f392c0 100644
--- a/src/mesa/drivers/dri/intel/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
@@ -214,6 +214,7 @@ intel_bufferobj_map(GLcontext * ctx,
    struct intel_context *intel = intel_context(ctx);
    struct intel_buffer_object *intel_obj = intel_buffer_object(obj);
    GLboolean read_only = (access == GL_READ_ONLY_ARB);
+   GLboolean write_only = (access == GL_WRITE_ONLY_ARB);
 
    assert(intel_obj);
 
@@ -225,7 +226,14 @@ intel_bufferobj_map(GLcontext * ctx,
       return NULL;
    }
 
-   dri_bo_map(intel_obj->buffer, !read_only);
+   if (write_only && intel->intelScreen->kernel_exec_fencing) {
+      drm_intel_gem_bo_map_gtt(intel_obj->buffer);
+      intel_obj->mapped_gtt = GL_TRUE;
+   } else {
+      drm_intel_bo_map(intel_obj->buffer, !read_only);
+      intel_obj->mapped_gtt = GL_FALSE;
+   }
+
    obj->Pointer = intel_obj->buffer->virtual;
    return obj->Pointer;
 }
@@ -243,7 +251,11 @@ intel_bufferobj_unmap(GLcontext * ctx,
    assert(intel_obj);
    if (intel_obj->buffer != NULL) {
       assert(obj->Pointer);
-      dri_bo_unmap(intel_obj->buffer);
+      if (intel_obj->mapped_gtt) {
+	 drm_intel_gem_bo_unmap_gtt(intel_obj->buffer);
+      } else {
+	 drm_intel_bo_unmap(intel_obj->buffer);
+      }
       obj->Pointer = NULL;
    }
    return GL_TRUE;
diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.h b/src/mesa/drivers/dri/intel/intel_buffer_objects.h
index bf6dbd58f2..7ef723833c 100644
--- a/src/mesa/drivers/dri/intel/intel_buffer_objects.h
+++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.h
@@ -46,6 +46,7 @@ struct intel_buffer_object
    struct intel_region *region; /* Is there a zero-copy texture
                                    associated with this (pixel)
                                    buffer object? */
+   GLboolean mapped_gtt;
 };
 
 
-- 
cgit v1.2.3


From d4a42b0ce6455d03be70aa56aacd779be193aca4 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Sun, 10 May 2009 10:08:32 -0700
Subject: intel: Skip the DRI2 renderbuffer update when doing Viewport on an
 FBO.

---
 src/mesa/drivers/dri/intel/intel_context.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 8b3e50f9b6..7c77a1c819 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -393,7 +393,7 @@ intel_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei w, GLsizei h)
     if (!driContext->driScreenPriv->dri2.enabled)
 	return;
 
-    if (!intel->internal_viewport_call) {
+    if (!intel->internal_viewport_call && ctx->DrawBuffer->Name == 0) {
        intel_update_renderbuffers(driContext, driContext->driDrawablePriv);
        if (driContext->driDrawablePriv != driContext->driReadablePriv)
 	  intel_update_renderbuffers(driContext, driContext->driReadablePriv);
-- 
cgit v1.2.3


From 4d244fb8999440a1876281574eb045f0a5895e9e Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Tue, 12 May 2009 09:16:27 -0600
Subject: i965: comment

---
 src/mesa/drivers/dri/i965/brw_wm_iz.c | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/i965/brw_wm_iz.c b/src/mesa/drivers/dri/i965/brw_wm_iz.c
index bd60ac9b31..8fd067abe7 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_iz.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_iz.c
@@ -116,6 +116,10 @@ const struct {
  { C, 0, 1, 1, 1 } 
 };
 
+/**
+ * \param line_aa  AA_NEVER, AA_ALWAYS or AA_SOMETIMES
+ * \param lookup  bitmask of IZ_* flags
+ */
 void brw_wm_lookup_iz( GLuint line_aa,
 		       GLuint lookup,
 		       struct brw_wm_prog_key *key )
-- 
cgit v1.2.3


From 5590798f6d338e93ae6bee82ba5224568237ec18 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Tue, 12 May 2009 14:07:51 -0600
Subject: i965: increase BRW_EU_MAX_INSN

---
 src/mesa/drivers/dri/i965/brw_eu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 62c98bd8bb..bc7756ceab 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -97,7 +97,7 @@ struct brw_glsl_call;
 
 
 #define BRW_EU_MAX_INSN_STACK 5
-#define BRW_EU_MAX_INSN 4000
+#define BRW_EU_MAX_INSN 10000
 
 struct brw_compile {
    struct brw_instruction store[BRW_EU_MAX_INSN];
-- 
cgit v1.2.3


From 10c4a10b979bddd099287dec5b69243c2ade8ade Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Tue, 12 May 2009 14:08:52 -0600
Subject: i965: enable additional code in emit_fb_write()

Not 100% sure this is right, but the invalid assertion is fixed...
---
 src/mesa/drivers/dri/i965/brw_wm_glsl.c | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
index 2b2df7329c..23caf59435 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
@@ -814,27 +814,26 @@ static void emit_fb_write(struct brw_wm_compile *c,
     }
 
     if (c->key.dest_depth_reg) {
-        GLuint comp = c->key.dest_depth_reg / 2;
-        GLuint off = c->key.dest_depth_reg % 2;
+        const GLuint comp = c->key.dest_depth_reg / 2;
+        const GLuint off = c->key.dest_depth_reg % 2;
 
-        assert(comp == 1);
-        assert(off == 0);
-#if 0
-        /* XXX do we need this code?   comp always 1, off always 0, it seems */
         if (off != 0) {
+            /* XXX this code needs review/testing */
+            struct brw_reg arg1_0 = get_src_reg(c, inst, 1, comp);
+            struct brw_reg arg1_1 = get_src_reg(c, inst, 1, comp+1);
+
             brw_push_insn_state(p);
             brw_set_compression_control(p, BRW_COMPRESSION_NONE);
 
-            brw_MOV(p, brw_message_reg(nr), offset(arg1[comp],1));
+            brw_MOV(p, brw_message_reg(nr), offset(arg1_0, 1));
             /* 2nd half? */
-            brw_MOV(p, brw_message_reg(nr+1), arg1[comp+1]);
+            brw_MOV(p, brw_message_reg(nr+1), arg1_1);
             brw_pop_insn_state(p);
         }
         else
-#endif
         {
-           struct brw_reg src =  get_src_reg(c, inst, 1, 1);
-           brw_MOV(p, brw_message_reg(nr), src);
+            struct brw_reg src =  get_src_reg(c, inst, 1, 1);
+            brw_MOV(p, brw_message_reg(nr), src);
         }
         nr += 2;
    }
-- 
cgit v1.2.3


From 2e4e34689022ecfcc7dc107427db90cc52a94d63 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Wed, 13 May 2009 10:28:00 -0600
Subject: intel: create a private gl_array_object for intel_clear_tris(), fix
 bug 21638

gl_array_object encapsulates a set of vertex arrays (see the
GL_APPLE_vertex_array_object extension).
Create a private gl_array_object for drawing the quad for intel_clear_tris()
so we don't have to worry about the user's vertex array state.
This fixes the no-op glClear bug #21638 and removes the need to call
_mesa_PushClientAttrib() and _mesa_PopClientAttrib().
---
 src/mesa/drivers/dri/intel/intel_clear.c   | 93 ++++++++++++++++++++----------
 src/mesa/drivers/dri/intel/intel_context.c |  3 +
 src/mesa/drivers/dri/intel/intel_context.h |  8 +++
 3 files changed, 75 insertions(+), 29 deletions(-)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/intel/intel_clear.c b/src/mesa/drivers/dri/intel/intel_clear.c
index aed95c7c56..eb0d890f47 100644
--- a/src/mesa/drivers/dri/intel/intel_clear.c
+++ b/src/mesa/drivers/dri/intel/intel_clear.c
@@ -30,6 +30,7 @@
 #include "main/enums.h"
 #include "main/image.h"
 #include "main/mtypes.h"
+#include "main/arrayobj.h"
 #include "main/attrib.h"
 #include "main/blend.h"
 #include "main/bufferobj.h"
@@ -66,6 +67,45 @@
 			      BUFFER_BIT_COLOR6 |			\
 			      BUFFER_BIT_COLOR7)
 
+
+/**
+ * Per-context one-time init of things for intl_clear_tris().
+ * Basically set up a private array object for vertex/color arrays.
+ */
+static void
+init_clear(GLcontext *ctx)
+{
+   struct intel_context *intel = intel_context(ctx);
+   struct gl_array_object *arraySave = NULL;
+   const GLuint arrayBuffer = ctx->Array.ArrayBufferObj->Name;
+   const GLuint elementBuffer = ctx->Array.ElementArrayBufferObj->Name;
+
+   /* create new array object */
+   intel->clear.arrayObj = _mesa_new_array_object(ctx, ~0);
+
+   /* save current array object, bind new one */
+   _mesa_reference_array_object(ctx, &arraySave, ctx->Array.ArrayObj);
+   _mesa_reference_array_object(ctx, &ctx->Array.ArrayObj, intel->clear.arrayObj);
+
+   /* one-time setup of vertex arrays (pos, color) */
+   _mesa_BindBufferARB(GL_ARRAY_BUFFER_ARB, 0);
+   _mesa_BindBufferARB(GL_ELEMENT_ARRAY_BUFFER_ARB, 0);
+   _mesa_ColorPointer(4, GL_FLOAT, 4 * sizeof(GLfloat), intel->clear.color);
+   _mesa_VertexPointer(3, GL_FLOAT, 3 * sizeof(GLfloat), intel->clear.vertices);
+   _mesa_Enable(GL_COLOR_ARRAY);
+   _mesa_Enable(GL_VERTEX_ARRAY);
+
+   /* restore original array object */
+   _mesa_reference_array_object(ctx, &ctx->Array.ArrayObj, arraySave);
+   _mesa_reference_array_object(ctx, &arraySave, NULL);
+
+   /* restore original buffer objects */
+   _mesa_BindBufferARB(GL_ARRAY_BUFFER_ARB, arrayBuffer);
+   _mesa_BindBufferARB(GL_ELEMENT_ARRAY_BUFFER_ARB, elementBuffer);
+}
+
+
+
 /**
  * Perform glClear where mask contains only color, depth, and/or stencil.
  *
@@ -78,14 +118,16 @@ void
 intel_clear_tris(GLcontext *ctx, GLbitfield mask)
 {
    struct intel_context *intel = intel_context(ctx);
-   GLfloat vertices[4][3];
-   GLfloat color[4][4];
    GLfloat dst_z;
    struct gl_framebuffer *fb = ctx->DrawBuffer;
    int i;
    GLboolean saved_fp_enable = GL_FALSE, saved_vp_enable = GL_FALSE;
    GLuint saved_shader_program = 0;
    unsigned int saved_active_texture;
+   struct gl_array_object *arraySave = NULL;
+
+   if (!intel->clear.arrayObj)
+      init_clear(ctx);
 
    assert((mask & ~(TRI_CLEAR_COLOR_BITS | BUFFER_BIT_DEPTH |
 		    BUFFER_BIT_STENCIL)) == 0);
@@ -98,7 +140,6 @@ intel_clear_tris(GLcontext *ctx, GLbitfield mask)
 		    GL_STENCIL_BUFFER_BIT |
 		    GL_TRANSFORM_BIT |
 		    GL_CURRENT_BIT);
-   _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT);
    saved_active_texture = ctx->Texture.CurrentUnit;
 
    /* Disable existing GL state we don't want to apply to a clear. */
@@ -149,18 +190,14 @@ intel_clear_tris(GLcontext *ctx, GLbitfield mask)
       }
    }
 
-#if FEATURE_ARB_vertex_buffer_object
-   _mesa_BindBufferARB(GL_ARRAY_BUFFER_ARB, 0);
-   _mesa_BindBufferARB(GL_ELEMENT_ARRAY_BUFFER_ARB, 0);
-#endif
+   /* save current array object, bind our private one */
+   _mesa_reference_array_object(ctx, &arraySave, ctx->Array.ArrayObj);
+   _mesa_reference_array_object(ctx, &ctx->Array.ArrayObj, intel->clear.arrayObj);
 
    intel_meta_set_passthrough_transform(intel);
 
    for (i = 0; i < 4; i++) {
-      color[i][0] = ctx->Color.ClearColor[0];
-      color[i][1] = ctx->Color.ClearColor[1];
-      color[i][2] = ctx->Color.ClearColor[2];
-      color[i][3] = ctx->Color.ClearColor[3];
+      COPY_4FV(intel->clear.color[i], ctx->Color.ClearColor);
    }
 
    /* convert clear Z from [0,1] to NDC coord in [-1,1] */
@@ -169,23 +206,18 @@ intel_clear_tris(GLcontext *ctx, GLbitfield mask)
    /* Prepare the vertices, which are the same regardless of which buffer we're
     * drawing to.
     */
-   vertices[0][0] = fb->_Xmin;
-   vertices[0][1] = fb->_Ymin;
-   vertices[0][2] = dst_z;
-   vertices[1][0] = fb->_Xmax;
-   vertices[1][1] = fb->_Ymin;
-   vertices[1][2] = dst_z;
-   vertices[2][0] = fb->_Xmax;
-   vertices[2][1] = fb->_Ymax;
-   vertices[2][2] = dst_z;
-   vertices[3][0] = fb->_Xmin;
-   vertices[3][1] = fb->_Ymax;
-   vertices[3][2] = dst_z;
-
-   _mesa_ColorPointer(4, GL_FLOAT, 4 * sizeof(GLfloat), &color);
-   _mesa_VertexPointer(3, GL_FLOAT, 3 * sizeof(GLfloat), &vertices);
-   _mesa_Enable(GL_COLOR_ARRAY);
-   _mesa_Enable(GL_VERTEX_ARRAY);
+   intel->clear.vertices[0][0] = fb->_Xmin;
+   intel->clear.vertices[0][1] = fb->_Ymin;
+   intel->clear.vertices[0][2] = dst_z;
+   intel->clear.vertices[1][0] = fb->_Xmax;
+   intel->clear.vertices[1][1] = fb->_Ymin;
+   intel->clear.vertices[1][2] = dst_z;
+   intel->clear.vertices[2][0] = fb->_Xmax;
+   intel->clear.vertices[2][1] = fb->_Ymax;
+   intel->clear.vertices[2][2] = dst_z;
+   intel->clear.vertices[3][0] = fb->_Xmin;
+   intel->clear.vertices[3][1] = fb->_Ymax;
+   intel->clear.vertices[3][2] = dst_z;
 
    while (mask != 0) {
       GLuint this_mask = 0;
@@ -246,8 +278,11 @@ intel_clear_tris(GLcontext *ctx, GLbitfield mask)
    if (saved_shader_program)
       _mesa_UseProgramObjectARB(saved_shader_program);
 
-   _mesa_PopClientAttrib();
    _mesa_PopAttrib();
+
+   /* restore current array object */
+   _mesa_reference_array_object(ctx, &ctx->Array.ArrayObj, arraySave);
+   _mesa_reference_array_object(ctx, &arraySave, NULL);
 }
 
 static const char *buffer_names[] = {
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index a6d8729d8f..07d53aad23 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -28,6 +28,7 @@
 
 #include "main/glheader.h"
 #include "main/context.h"
+#include "main/arrayobj.h"
 #include "main/extensions.h"
 #include "main/framebuffer.h"
 #include "main/imports.h"
@@ -755,6 +756,8 @@ intelDestroyContext(__DRIcontextPrivate * driContextPriv)
 
       INTEL_FIREVERTICES(intel);
 
+      _mesa_delete_array_object(&intel->ctx, intel->clear.arrayObj);
+
       intel->vtbl.destroy(intel);
 
       release_texture_heaps = (intel->ctx.Shared->RefCount == 1);
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index d798225ddd..f45e24ca3a 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -215,6 +215,14 @@ struct intel_context
    GLuint ClearColor565;
    GLuint ClearColor8888;
 
+   /* info for intel_clear_tris() */
+   struct
+   {
+      struct gl_array_object *arrayObj;
+      GLfloat vertices[4][3];
+      GLfloat color[4][4];
+   } clear;
+
    /* Offsets of fields within the current vertex:
     */
    GLuint coloroffset;
-- 
cgit v1.2.3


From a566b6d8ffa45728231f9040b15f86d403304c87 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Wed, 13 May 2009 11:19:00 -0600
Subject: intel: enable GL_APPLE_vertex_array_object

No special driver changes are needed for this extension.
---
 src/mesa/drivers/dri/intel/intel_extensions.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/intel/intel_extensions.c b/src/mesa/drivers/dri/intel/intel_extensions.c
index 9ec1b4ec2f..1e8b1878ab 100644
--- a/src/mesa/drivers/dri/intel/intel_extensions.c
+++ b/src/mesa/drivers/dri/intel/intel_extensions.c
@@ -48,6 +48,7 @@
 #define need_GL_EXT_point_parameters
 #define need_GL_EXT_secondary_color
 #define need_GL_EXT_stencil_two_side
+#define need_GL_APPLE_vertex_array_object
 #define need_GL_ATI_separate_stencil
 #define need_GL_ATI_envmap_bumpmap
 #define need_GL_NV_point_sprite
@@ -95,6 +96,7 @@ static const struct dri_extension card_extensions[] = {
    { "GL_EXT_texture_lod_bias",           NULL },
    { "GL_3DFX_texture_compression_FXT1",  NULL },
    { "GL_APPLE_client_storage",           NULL },
+   { "GL_APPLE_vertex_array_object",      GL_APPLE_vertex_array_object_functions},
    { "GL_MESA_pack_invert",               NULL },
    { "GL_MESA_ycbcr_texture",             NULL },
    { "GL_NV_blend_square",                NULL },
-- 
cgit v1.2.3


From 99960393edb3d6c0d3702cf51b59c2e4189117c7 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Wed, 13 May 2009 11:31:35 -0600
Subject: intel: added null ptr check

Fixes segfault in context tear-down when glClear was never called.
---
 src/mesa/drivers/dri/intel/intel_context.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 07d53aad23..5dc3df395d 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -756,7 +756,8 @@ intelDestroyContext(__DRIcontextPrivate * driContextPriv)
 
       INTEL_FIREVERTICES(intel);
 
-      _mesa_delete_array_object(&intel->ctx, intel->clear.arrayObj);
+      if (intel->clear.arrayObj)
+         _mesa_delete_array_object(&intel->ctx, intel->clear.arrayObj);
 
       intel->vtbl.destroy(intel);
 
-- 
cgit v1.2.3


From 09c04db3c900e4ed833d060853b48c7ca23697e1 Mon Sep 17 00:00:00 2001
From: Michel Dänzer <daenzer@vmware.com>
Date: Thu, 14 May 2009 11:07:49 +0200
Subject: r300: Make sure to drop current hardware state reference to texture
 objects.

Fixes potential texture object leaks.
---
 src/mesa/drivers/dri/r300/r300_context.c  |  7 +++++++
 src/mesa/drivers/dri/r300/r300_texstate.c | 22 ++++++++++++++--------
 2 files changed, 21 insertions(+), 8 deletions(-)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c
index 12bee1a8fb..8f0effd83e 100644
--- a/src/mesa/drivers/dri/r300/r300_context.c
+++ b/src/mesa/drivers/dri/r300/r300_context.c
@@ -43,6 +43,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "main/matrix.h"
 #include "main/extensions.h"
 #include "main/state.h"
+#include "main/texobj.h"
 #include "main/bufferobj.h"
 
 #include "swrast/swrast.h"
@@ -500,6 +501,7 @@ void r300DestroyContext(__DRIcontextPrivate * driContextPriv)
 	r300ContextPtr r300 = (r300ContextPtr) driContextPriv->driverPrivate;
 	radeonContextPtr radeon = (radeonContextPtr) r300;
 	radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL;
+	int i;
 
 	if (RADEON_DEBUG & DEBUG_DRI) {
 		fprintf(stderr, "Destroying context !\n");
@@ -553,6 +555,11 @@ void r300DestroyContext(__DRIcontextPrivate * driContextPriv)
 			assert(is_empty_list(&r300->swapped));
 		}
 
+                /* Drop texture object references from current hardware state */
+		for (i = 0; i < 8; i++) {
+			_mesa_reference_texobj(&r300->state.texture.unit[i].texobj, NULL);
+		}
+
 		radeonCleanupContext(&r300->radeon);
 
 #ifdef USER_BUFFERS
diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c
index abe613e27b..f6ae4b675b 100644
--- a/src/mesa/drivers/dri/r300/r300_texstate.c
+++ b/src/mesa/drivers/dri/r300/r300_texstate.c
@@ -557,12 +557,15 @@ static GLboolean r300UpdateTexture(GLcontext * ctx, int unit)
 {
 	r300ContextPtr rmesa = R300_CONTEXT(ctx);
 	struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
-	struct gl_texture_object *tObj = texUnit->_Current;
-	r300TexObjPtr t = (r300TexObjPtr) tObj->DriverData;
+	struct gl_texture_object *tObj = texUnit->_ReallyEnabled ?
+		texUnit->_Current : NULL;
+	r300TexObjPtr t = tObj ? (r300TexObjPtr) tObj->DriverData : NULL;
 
 	/* Fallback if there's a texture border */
-	if (tObj->Image[0][tObj->BaseLevel]->Border > 0)
-		return GL_FALSE;
+	if (tObj && tObj->Image[0][tObj->BaseLevel]->Border > 0) {
+		tObj = NULL;
+		t = NULL;
+	}
 
 	/* Update state if this is a different texture object to last
 	 * time.
@@ -579,11 +582,14 @@ static GLboolean r300UpdateTexture(GLcontext * ctx, int unit)
 		}
 
 		_mesa_reference_texobj(&rmesa->state.texture.unit[unit].texobj, tObj);
-		t->base.bound |= (1 << unit);
-		driUpdateTextureLRU(&t->base);	/* XXX: should be locked! */
+
+		if (t) {
+			t->base.bound |= (1 << unit);
+			driUpdateTextureLRU(&t->base);	/* XXX: should be locked! */
+		}
 	}
 
-	return !t->border_fallback;
+	return !t || !t->border_fallback;
 }
 
 void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
@@ -651,7 +657,7 @@ static GLboolean r300UpdateTextureUnit(GLcontext * ctx, int unit)
 	} else if (texUnit->_ReallyEnabled) {
 		return GL_FALSE;
 	} else {
-		return GL_TRUE;
+		return r300UpdateTexture(ctx, unit);
 	}
 }
 
-- 
cgit v1.2.3


From bc3270e99f5c39544aaf831742db14796ab83a6a Mon Sep 17 00:00:00 2001
From: Robert Ellison <papillo@vmware.com>
Date: Wed, 13 May 2009 20:38:33 -0600
Subject: i965: send all warnings through _mesa_warning()

One warning message:
   drm_i915_getparam: -22

was still being sent to fprintf().  This causes all Piglit tests to fail,
even with MESA_DEBUG=0.

Using _mesa_warning() to emit the message allows the general Mesa controls
for messages like this to be applied.
---
 src/mesa/drivers/dri/intel/intel_screen.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 65e62947ef..2728823142 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -236,7 +236,7 @@ intel_get_param(__DRIscreenPrivate *psp, int param, int *value)
 
    ret = drmCommandWriteRead(psp->fd, DRM_I915_GETPARAM, &gp, sizeof(gp));
    if (ret) {
-      fprintf(stderr, "drm_i915_getparam: %d\n", ret);
+      _mesa_warning(NULL, "drm_i915_getparam: %d\n", ret);
       return GL_FALSE;
    }
 
-- 
cgit v1.2.3


From ab6c4fa582972e25f8800c77b5dd5b3a83afc996 Mon Sep 17 00:00:00 2001
From: Robert Ellison <papillo@vmware.com>
Date: Wed, 13 May 2009 20:40:23 -0600
Subject: i965: fix 1D texture borders with GL_CLAMP_TO_BORDER

With 1D textures, GL_TEXTURE_WRAP_T should be ignored (only
GL_TEXTURE_WRAP_S should be respected).  But the i965 hardware
seems to follow the value of GL_TEXTURE_WRAP_T even when sampling
1D textures.

This fix forces GL_TEXTURE_WRAP_T to be GL_REPEAT whenever 1D
textures are used; this allows the texture to be sampled
correctly, avoiding "imaginary" border elements in the T direction.

This bug was demonstrated in the Piglit tex1d-2dborder test.
With this fix, that test passes.
---
 src/mesa/drivers/dri/i965/brw_wm_sampler_state.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
index c604ef0162..3fc18ff1f3 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
@@ -178,6 +178,16 @@ static void brw_update_sampler_state(struct wm_sampler_entry *key,
       sampler->ss1.s_wrap_mode = BRW_TEXCOORDMODE_CUBE;
       sampler->ss1.t_wrap_mode = BRW_TEXCOORDMODE_CUBE;
    }
+   else if (key->tex_target == GL_TEXTURE_1D) {
+      /* There's a bug in 1D texture sampling - it actually pays
+       * attention to the wrap_t value, though it should not.
+       * Override the wrap_t value here to GL_REPEAT to keep
+       * any nonexistent border pixels from floating in.
+       */
+      sampler->ss1.r_wrap_mode = translate_wrap_mode(key->wrap_r);
+      sampler->ss1.s_wrap_mode = translate_wrap_mode(key->wrap_s);
+      sampler->ss1.t_wrap_mode = BRW_TEXCOORDMODE_WRAP;
+   }
    else {
       sampler->ss1.r_wrap_mode = translate_wrap_mode(key->wrap_r);
       sampler->ss1.s_wrap_mode = translate_wrap_mode(key->wrap_s);
-- 
cgit v1.2.3


From d866abeffc7e4a29736fa35fb8ac09c3a28a44d6 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 13 May 2009 18:18:29 -0700
Subject: intel: Use GL_FRONT_AND_BACK for stencil clearing.

This comes from a radeon-rewrite fallback fix, but may also fix stencil
clear failure when the polygon winding mode is flipped.
---
 src/mesa/drivers/dri/intel/intel_clear.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/intel/intel_clear.c b/src/mesa/drivers/dri/intel/intel_clear.c
index eb0d890f47..488db2cf45 100644
--- a/src/mesa/drivers/dri/intel/intel_clear.c
+++ b/src/mesa/drivers/dri/intel/intel_clear.c
@@ -256,7 +256,8 @@ intel_clear_tris(GLcontext *ctx, GLbitfield mask)
       if (this_mask & BUFFER_BIT_STENCIL) {
 	 _mesa_Enable(GL_STENCIL_TEST);
 	 _mesa_StencilOp(GL_REPLACE, GL_REPLACE, GL_REPLACE);
-	 _mesa_StencilFuncSeparate(GL_FRONT, GL_ALWAYS, ctx->Stencil.Clear,
+	 _mesa_StencilFuncSeparate(GL_FRONT_AND_BACK, GL_ALWAYS,
+				   ctx->Stencil.Clear,
 				   ctx->Stencil.WriteMask[0]);
       } else {
 	 _mesa_Disable(GL_STENCIL_TEST);
-- 
cgit v1.2.3


From 64980125c76b05501a6fe7fe20fe52438f459129 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 13 May 2009 19:08:17 -0700
Subject: intel: Use FRONT_AND_BACK for StencilOp as well.

---
 src/mesa/drivers/dri/intel/intel_clear.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/intel/intel_clear.c b/src/mesa/drivers/dri/intel/intel_clear.c
index 488db2cf45..4dfaee8a4a 100644
--- a/src/mesa/drivers/dri/intel/intel_clear.c
+++ b/src/mesa/drivers/dri/intel/intel_clear.c
@@ -255,7 +255,8 @@ intel_clear_tris(GLcontext *ctx, GLbitfield mask)
       /* Control writing of the stencil clear value to stencil. */
       if (this_mask & BUFFER_BIT_STENCIL) {
 	 _mesa_Enable(GL_STENCIL_TEST);
-	 _mesa_StencilOp(GL_REPLACE, GL_REPLACE, GL_REPLACE);
+	 _mesa_StencilOpSeparate(GL_FRONT_AND_BACK,
+				 GL_REPLACE, GL_REPLACE, GL_REPLACE);
 	 _mesa_StencilFuncSeparate(GL_FRONT_AND_BACK, GL_ALWAYS,
 				   ctx->Stencil.Clear,
 				   ctx->Stencil.WriteMask[0]);
-- 
cgit v1.2.3


From 0f5113deed91611ecdda6596542530b1849bb161 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 14 May 2009 09:49:45 -0700
Subject: i965: Fix register allocation of GLSL fp inputs.

Before, if the VP output something that is in the attributes coming into
the WM but which isn't used by the WM, then WM would end up reading subsequent
varyings from the wrong places.  This was visible with a GLSL demo
using gl_PointSize in the VS and a varying in the WM, as point size is in
the VUE but not used by the WM.  There is now a regression test in piglit,
glsl-unused-varying.
---
 src/mesa/drivers/dri/i965/brw_wm.c       |  5 ++++-
 src/mesa/drivers/dri/i965/brw_wm.h       |  1 +
 src/mesa/drivers/dri/i965/brw_wm_glsl.c  | 31 +++++++++++++++++++++----------
 src/mesa/drivers/dri/i965/brw_wm_pass2.c |  3 +--
 4 files changed, 27 insertions(+), 13 deletions(-)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index cd65f57bbc..3e476fd3be 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -319,6 +319,9 @@ static void brw_wm_populate_key( struct brw_context *brw,
       key->drawable_height = brw->intel.driDrawable->h;
    }
 
+   /* CACHE_NEW_VS_PROG */
+   key->vp_outputs_written = brw->vs.prog_data->outputs_written & DO_SETUP_BITS;
+
    /* The unique fragment program ID */
    key->program_string_id = fp->id;
 }
@@ -357,7 +360,7 @@ const struct brw_tracked_state brw_wm_prog = {
       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 		BRW_NEW_WM_INPUT_DIMENSIONS |
 		BRW_NEW_REDUCED_PRIMITIVE),
-      .cache = 0
+      .cache = CACHE_NEW_VS_PROG,
    },
    .prepare = brw_prepare_wm_prog
 };
diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h
index 59ead757b5..fb15c03e83 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.h
+++ b/src/mesa/drivers/dri/i965/brw_wm.h
@@ -75,6 +75,7 @@ struct brw_wm_prog_key {
    GLuint program_string_id:32;
    GLuint origin_x, origin_y;
    GLuint drawable_height;
+   GLuint vp_outputs_written;
 };
 
 
diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
index 23caf59435..4936703799 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
@@ -302,7 +302,7 @@ static void prealloc_reg(struct brw_wm_compile *c)
 {
     int i, j;
     struct brw_reg reg;
-    int nr_interp_regs = 0;
+    int urb_read_length = 0;
     GLuint inputs = FRAG_BIT_WPOS | c->fp_interp_emitted | c->fp_deriv_emitted;
     GLuint reg_index = 0;
 
@@ -366,18 +366,29 @@ static void prealloc_reg(struct brw_wm_compile *c)
     }
 
     /* fragment shader inputs */
-    for (i = 0; i < FRAG_ATTRIB_MAX; i++) {
-	if (inputs & (1<<i)) {
-	    nr_interp_regs++;
-	    reg = brw_vec8_grf(reg_index, 0);
-	    for (j = 0; j < 4; j++)
-		set_reg(c, PROGRAM_PAYLOAD, i, j, reg);
-	    reg_index += 2;
-	}
+    for (i = 0; i < VERT_RESULT_MAX; i++) {
+       int fp_input;
+
+       if (i >= VERT_RESULT_VAR0)
+	  fp_input = i - VERT_RESULT_VAR0 + FRAG_ATTRIB_VAR0;
+       else if (i <= VERT_RESULT_TEX7)
+	  fp_input = i;
+       else
+	  fp_input = -1;
+
+       if (fp_input >= 0 && inputs & (1 << fp_input)) {
+	  urb_read_length = reg_index;
+	  reg = brw_vec8_grf(reg_index, 0);
+	  for (j = 0; j < 4; j++)
+	     set_reg(c, PROGRAM_PAYLOAD, fp_input, j, reg);
+       }
+       if (c->key.vp_outputs_written & (1 << i)) {
+	  reg_index += 2;
+       }
     }
 
     c->prog_data.first_curbe_grf = c->key.nr_depth_regs * 2;
-    c->prog_data.urb_read_length = nr_interp_regs * 2;
+    c->prog_data.urb_read_length = urb_read_length;
     c->prog_data.curb_read_length = c->nr_creg;
     c->emit_mask_reg = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, reg_index, 0);
     reg_index++;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass2.c b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
index 780edbc42e..08cac730c2 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_pass2.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
@@ -70,7 +70,6 @@ static void prealloc_reg(struct brw_wm_compile *c,
 static void init_registers( struct brw_wm_compile *c )
 {
    struct brw_context *brw = c->func.brw;
-   GLuint inputs = (brw->vs.prog_data->outputs_written & DO_SETUP_BITS);
    GLuint nr_interp_regs = 0;
    GLuint i = 0;
    GLuint j;
@@ -85,7 +84,7 @@ static void init_registers( struct brw_wm_compile *c )
       prealloc_reg(c, &c->creg[j], i++);
 
    for (j = 0; j < FRAG_ATTRIB_MAX; j++) {
-      if (inputs & (1<<j)) {
+      if (c->key.vp_outputs_written & (1<<j)) {
 	 /* index for vs output and ps input are not the same 
 	    in shader varying */
 	 GLuint index;
-- 
cgit v1.2.3


From dc657f3929fbe03275b3fae4ef84f02e74b51114 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 14 May 2009 10:56:32 -0700
Subject: i965: Fix varying payload reg assignment for the
 non-GLSL-instructions path.

I don't have a testcase for this, but it seems clearly wrong.
---
 src/mesa/drivers/dri/i965/brw_wm_pass2.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass2.c b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
index 08cac730c2..6faea018fb 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_pass2.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
@@ -69,7 +69,6 @@ static void prealloc_reg(struct brw_wm_compile *c,
  */
 static void init_registers( struct brw_wm_compile *c )
 {
-   struct brw_context *brw = c->func.brw;
    GLuint nr_interp_regs = 0;
    GLuint i = 0;
    GLuint j;
@@ -85,15 +84,18 @@ static void init_registers( struct brw_wm_compile *c )
 
    for (j = 0; j < FRAG_ATTRIB_MAX; j++) {
       if (c->key.vp_outputs_written & (1<<j)) {
-	 /* index for vs output and ps input are not the same 
-	    in shader varying */
-	 GLuint index;
-	 if (j > FRAG_ATTRIB_VAR0)
-	     index = j - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
+	 int fp_index;
+
+	 if (j >= VERT_RESULT_VAR0)
+	    fp_index = j - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
+	 else if (j <= VERT_RESULT_TEX7)
+	    fp_index = j;
 	 else
-	     index = j;
+	    fp_index = -1;
+
 	 nr_interp_regs++;
-	 prealloc_reg(c, &c->payload.input_interp[index], i++);
+	 if (fp_index >= 0)
+	    prealloc_reg(c, &c->payload.input_interp[fp_index], i++);
       }
    }
 
-- 
cgit v1.2.3


From 5c5a46884899ea25cdf25545d6ab3d9a74eafa3a Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 15 May 2009 11:41:42 -0700
Subject: i915: Only use the new 945 cube layout for compressed textures.

The docs actually explain this, but not in a terribly clear manner.
This nearly fixes the piglit cubemap testcase, except that something's
going wrong with the nearest filtering at 2x2 sizes in the testcase.
Looks good by visual inspection, though.

Bug #21692
---
 src/mesa/drivers/dri/i915/i915_tex_layout.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/i915/i915_tex_layout.c b/src/mesa/drivers/dri/i915/i915_tex_layout.c
index d44a2f47b3..7cc1c096e4 100644
--- a/src/mesa/drivers/dri/i915/i915_tex_layout.c
+++ b/src/mesa/drivers/dri/i915/i915_tex_layout.c
@@ -454,7 +454,10 @@ i945_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree * mt)
 {
    switch (mt->target) {
    case GL_TEXTURE_CUBE_MAP:
-      i945_miptree_layout_cube(intel, mt);
+      if (mt->compressed)
+	 i945_miptree_layout_cube(intel, mt);
+      else
+	 i915_miptree_layout_cube(intel, mt);
       break;
    case GL_TEXTURE_3D:
       i945_miptree_layout_3d(intel, mt);
-- 
cgit v1.2.3


From 4c6f82989983eecc0b3b724716cb3bcb675664c5 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 15 May 2009 12:32:51 -0700
Subject: i915: Use Stencil.Enabled instead of Stencil._Enabled in DrawBuffers.

The _Enabled field isn't updated at the point that DrawBuffers is called,
and the Driver.Enable() function does the testing for stencil buffer
presence anyway.

bug #21608 for Radeon
---
 src/mesa/drivers/dri/intel/intel_buffers.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/intel/intel_buffers.c b/src/mesa/drivers/dri/intel/intel_buffers.c
index 4f4ea45b74..df5c3fc176 100644
--- a/src/mesa/drivers/dri/intel/intel_buffers.c
+++ b/src/mesa/drivers/dri/intel/intel_buffers.c
@@ -276,7 +276,7 @@ intel_draw_buffer(GLcontext * ctx, struct gl_framebuffer *fb)
       ctx->Driver.Enable(ctx, GL_DEPTH_TEST,
                          (ctx->Depth.Test && fb->Visual.depthBits > 0));
       ctx->Driver.Enable(ctx, GL_STENCIL_TEST,
-                         (ctx->Stencil._Enabled && fb->Visual.stencilBits > 0));
+                         (ctx->Stencil.Enabled && fb->Visual.stencilBits > 0));
    }
    else {
       /* Mesa's Stencil._Enabled field is updated when
-- 
cgit v1.2.3


From b197a8ade3e1e6c67743111f12f27e0a4a985cd9 Mon Sep 17 00:00:00 2001
From: "Steinar H. Gunderson" <sgunderson@bigfoot.com>
Date: Tue, 12 May 2009 11:32:03 -0700
Subject: i915: Fix 945 cube map layout for the small mipmaps along the bottom.

Bug #21691.
---
 src/mesa/drivers/dri/i915/i915_tex_layout.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/i915/i915_tex_layout.c b/src/mesa/drivers/dri/i915/i915_tex_layout.c
index 7cc1c096e4..40bcf7a9af 100644
--- a/src/mesa/drivers/dri/i915/i915_tex_layout.c
+++ b/src/mesa/drivers/dri/i915/i915_tex_layout.c
@@ -55,6 +55,17 @@ static GLint step_offsets[6][2] = {
    [FACE_NEG_Z] = {-1, 1},
 };
 
+
+static GLint bottom_offsets[6] = {
+   [FACE_POS_X] = 16 + 0 * 8,
+   [FACE_POS_Y] = 16 + 1 * 8,
+   [FACE_POS_Z] = 16 + 2 * 8,
+   [FACE_NEG_X] = 16 + 3 * 8,
+   [FACE_NEG_Y] = 16 + 4 * 8,
+   [FACE_NEG_Z] = 16 + 5 * 8,
+};
+
+
 /**
  * Cube texture map layout for i830M-GM915.
  *
@@ -297,7 +308,7 @@ i915_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree * mt)
  * +---+   +---+   +---+   +---+   +---+   +---+
  *
  * The bottom row continues with the remaining 2x2 then the 1x1 mip contents
- * in order, with each of them aligned to a 4x4 block boundary.  Thus, for
+ * in order, with each of them aligned to a 8x8 block boundary.  Thus, for
  * 32x32 cube maps and smaller, the bottom row layout is going to dictate the
  * pitch of the tree.  For a tree with 4x4 images, the pitch is at least
  * 14 * 8 = 112 texels, for 2x2 it is at least 12 * 8 texels, and for 1x1
@@ -375,10 +386,11 @@ i945_miptree_layout_cube(struct intel_context *intel,
 	       x = (face - 4) * 8;
 	       break;
 	    }
+	    break;
 
 	 case 2:
 	    y = mt->total_height - 4;
-	    x = 16 + face * 8;
+	    x = bottom_offsets[face];
 	    break;
 
 	 case 1:
-- 
cgit v1.2.3


From 22690482e692cb5ed2f84d3e69545c09292e3484 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 15 May 2009 17:32:21 -0700
Subject: intel: Don't complain on falling back from PBO fastpaths.

Instead, stash the debug info under the handy debug flag.

Bug #20053
---
 src/mesa/drivers/dri/intel/intel_tex_image.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/mesa/drivers/dri')

diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c
index b71fe2a7ae..ddbb13e74a 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -208,7 +208,7 @@ try_pbo_upload(struct intel_context *intel,
    if (!pbo ||
        intel->ctx._ImageTransferState ||
        unpack->SkipPixels || unpack->SkipRows) {
-      _mesa_printf("%s: failure 1\n", __FUNCTION__);
+      DBG("%s: failure 1\n", __FUNCTION__);
       return GL_FALSE;
    }
 
@@ -264,7 +264,7 @@ try_pbo_zcopy(struct intel_context *intel,
    if (!pbo ||
        intel->ctx._ImageTransferState ||
        unpack->SkipPixels || unpack->SkipRows) {
-      _mesa_printf("%s: failure 1\n", __FUNCTION__);
+      DBG("%s: failure 1\n", __FUNCTION__);
       return GL_FALSE;
    }
 
@@ -283,7 +283,7 @@ try_pbo_zcopy(struct intel_context *intel,
    dst_stride = intelImage->mt->pitch;
 
    if (src_stride != dst_stride || dst_offset != 0 || src_offset != 0) {
-      _mesa_printf("%s: failure 2\n", __FUNCTION__);
+      DBG("%s: failure 2\n", __FUNCTION__);
       return GL_FALSE;
    }
 
-- 
cgit v1.2.3