From 1bc84102ad4df377df6c8bf5734b886b7683b939 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Wed, 3 Oct 2007 10:48:56 +0200 Subject: i915: Work around texture pitch related performance drops on i915 at least. --- src/mesa/drivers/dri/i915/intel_mipmap_tree.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i915/intel_mipmap_tree.c b/src/mesa/drivers/dri/i915/intel_mipmap_tree.c index 74f6b2d851..aefb89ac83 100644 --- a/src/mesa/drivers/dri/i915/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i915/intel_mipmap_tree.c @@ -104,7 +104,16 @@ intel_miptree_create(struct intel_context *intel, * replaced at some point by some scheme to only do this when really * necessary. */ - mt->pitch = ((mt->pitch * cpp + 63) & ~63) / cpp; + mt->pitch = (mt->pitch * cpp + 63) & ~63; + + /* XXX: At least the i915 seems very upset when the pitch is a multiple + * of 1024 and sometimes 512 bytes - performance can drop by several + * times. Go to the next multiple of 64 for now. + */ + if (!(mt->pitch & 511)) + mt->pitch += 64; + + mt->pitch /= cpp; } mt->region = intel_region_alloc(intel->intelScreen, -- cgit v1.2.3 From 58cdd1dc520d211b65f05fd06b5ba472f552853c Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Wed, 3 Oct 2007 11:25:59 +0200 Subject: i915: Only align texture pitch to 64 bytes when textures can be render targets. --- src/mesa/drivers/dri/i915/intel_mipmap_tree.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i915/intel_mipmap_tree.c b/src/mesa/drivers/dri/i915/intel_mipmap_tree.c index aefb89ac83..2c167a9ab7 100644 --- a/src/mesa/drivers/dri/i915/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i915/intel_mipmap_tree.c @@ -99,19 +99,27 @@ intel_miptree_create(struct intel_context *intel, if (ok) { if (!mt->compressed) { - /* XXX: Align pitch to multiple of 64 bytes for now to allow - * render-to-texture to work in all cases. This should probably be - * replaced at some point by some scheme to only do this when really - * necessary. - */ - mt->pitch = (mt->pitch * cpp + 63) & ~63; + int align; + + if (intel->intelScreen->ttm) { + /* XXX: Align pitch to multiple of 64 bytes for now to allow + * render-to-texture to work in all cases. This should probably be + * replaced at some point by some scheme to only do this when really + * necessary. + */ + align = 63; + } else { + align = 3; + } + + mt->pitch = (mt->pitch * cpp + align) & ~align; /* XXX: At least the i915 seems very upset when the pitch is a multiple * of 1024 and sometimes 512 bytes - performance can drop by several - * times. Go to the next multiple of 64 for now. + * times. Go to the next multiple of the required alignment for now. */ if (!(mt->pitch & 511)) - mt->pitch += 64; + mt->pitch += align + 1; mt->pitch /= cpp; } -- cgit v1.2.3 From 10cc229dc2ef61c51f7e242ac2d497916793d265 Mon Sep 17 00:00:00 2001 From: Maarten Maathuis Date: Thu, 4 Oct 2007 19:08:37 +0200 Subject: nouveau: Replace removed device classes with their proper labels. --- src/mesa/drivers/dri/nouveau/nouveau_card_list.h | 66 ++++++++++++------------ 1 file changed, 33 insertions(+), 33 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/nouveau/nouveau_card_list.h b/src/mesa/drivers/dri/nouveau/nouveau_card_list.h index b1a0e7bfd1..94f170e057 100644 --- a/src/mesa/drivers/dri/nouveau/nouveau_card_list.h +++ b/src/mesa/drivers/dri/nouveau/nouveau_card_list.h @@ -72,10 +72,10 @@ static nouveau_card nouveau_card_list[]={ {0x014D, "Quadro FX 550", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, {0x014E, "Quadro FX 540", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, {0x014F, "GeForce 6200", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, -{0x0150, "GeForce2 GTS/Pro", NV11_TCL_PRIMITIVE_3D, NV_15, 0}, -{0x0151, "GeForce2 Ti", NV11_TCL_PRIMITIVE_3D, NV_15, 0}, -{0x0152, "GeForce2 Ultra, Bladerunner", NV11_TCL_PRIMITIVE_3D, NV_15, 0}, -{0x0153, "Quadro2 Pro", NV11_TCL_PRIMITIVE_3D, NV_15, 0}, +{0x0150, "GeForce2 GTS/Pro", NV11_TCL_PRIMITIVE_3D, NV_11, 0}, +{0x0151, "GeForce2 Ti", NV11_TCL_PRIMITIVE_3D, NV_11, 0}, +{0x0152, "GeForce2 Ultra, Bladerunner", NV11_TCL_PRIMITIVE_3D, NV_11, 0}, +{0x0153, "Quadro2 Pro", NV11_TCL_PRIMITIVE_3D, NV_11, 0}, {0x0161, "GeForce 6200 TurboCache(TM)", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, {0x0162, "GeForce 6200 SE TurboCache (TM)", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, {0x0163, "GeForce 6200 LE", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, @@ -132,20 +132,20 @@ static nouveau_card nouveau_card_list[]={ {0x0240, "GeForce 6150", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, {0x0242, "GeForce 6100", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, {0x0244, "Geforce 6150 Go", NV30_TCL_PRIMITIVE_3D|0x4400, NV_44, 0}, -{0x0250, "GeForce4 Ti 4600", NV20_TCL_PRIMITIVE_3D|0x0500, NV_25, 0}, -{0x0251, "GeForce4 Ti 4400", NV20_TCL_PRIMITIVE_3D|0x0500, NV_25, 0}, -{0x0252, "GeForce4 Ti", NV20_TCL_PRIMITIVE_3D|0x0500, NV_25, 0}, -{0x0253, "GeForce4 Ti 4200", NV20_TCL_PRIMITIVE_3D|0x0500, NV_25, 0}, -{0x0258, "Quadro4 900 XGL", NV20_TCL_PRIMITIVE_3D|0x0500, NV_25, 0}, -{0x0259, "Quadro4 750 XGL", NV20_TCL_PRIMITIVE_3D|0x0500, NV_25, 0}, -{0x025B, "Quadro4 700 XGL", NV20_TCL_PRIMITIVE_3D|0x0500, NV_25, 0}, -{0x0280, "GeForce4 Ti 4800", NV20_TCL_PRIMITIVE_3D|0x0500, NV_25, 0}, -{0x0281, "GeForce4 Ti 4200 AGP 8x", NV20_TCL_PRIMITIVE_3D|0x0500, NV_25, 0}, -{0x0282, "GeForce4 Ti 4800 SE", NV20_TCL_PRIMITIVE_3D|0x0500, NV_25, 0}, -{0x0286, "GeForce4 Ti 4200 Go AGP 8x", NV20_TCL_PRIMITIVE_3D|0x0500, NV_25, 0}, -{0x0288, "Quadro4 980 XGL", NV20_TCL_PRIMITIVE_3D|0x0500, NV_25, 0}, -{0x0289, "Quadro4 780 XGL", NV20_TCL_PRIMITIVE_3D|0x0500, NV_25, 0}, -{0x028C, "Quadro4 700 GoGL", NV20_TCL_PRIMITIVE_3D|0x0500, NV_25, 0}, +{0x0250, "GeForce4 Ti 4600", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, +{0x0251, "GeForce4 Ti 4400", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, +{0x0252, "GeForce4 Ti", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, +{0x0253, "GeForce4 Ti 4200", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, +{0x0258, "Quadro4 900 XGL", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, +{0x0259, "Quadro4 750 XGL", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, +{0x025B, "Quadro4 700 XGL", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, +{0x0280, "GeForce4 Ti 4800", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, +{0x0281, "GeForce4 Ti 4200 AGP 8x", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, +{0x0282, "GeForce4 Ti 4800 SE", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, +{0x0286, "GeForce4 Ti 4200 Go AGP 8x", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, +{0x0288, "Quadro4 980 XGL", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, +{0x0289, "Quadro4 780 XGL", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, +{0x028C, "Quadro4 700 GoGL", NV20_TCL_PRIMITIVE_3D|0x0500, NV_20, 0}, {0x0290, "GeForce 7900 GTX", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, {0x0291, "GeForce 7900 GT", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, {0x0292, "GeForce 7900 GS", NV30_TCL_PRIMITIVE_3D|0x4000, NV_40, 0}, @@ -176,21 +176,21 @@ static nouveau_card nouveau_card_list[]={ {0x031D, "NV31GLM", NV30_TCL_PRIMITIVE_3D|0x0300, NV_30, 0}, {0x031E, "NV31GLM Pro", NV30_TCL_PRIMITIVE_3D|0x0300, NV_30, 0}, {0x031F, "NV31GLM Pro", NV30_TCL_PRIMITIVE_3D|0x0300, NV_30, 0}, -{0x0320, "GeForce FX 5200", NV30_TCL_PRIMITIVE_3D|0x0600, NV_34, 0}, -{0x0321, "GeForce FX 5200 Ultra", NV30_TCL_PRIMITIVE_3D|0x0600, NV_34, 0}, -{0x0322, "GeForce FX 5200", NV30_TCL_PRIMITIVE_3D|0x0600, NV_34, 0}, -{0x0323, "GeForce FX 5200LE", NV30_TCL_PRIMITIVE_3D|0x0600, NV_34, 0}, -{0x0324, "GeForce FX Go5200", NV30_TCL_PRIMITIVE_3D|0x0600, NV_34, 0}, -{0x0325, "GeForce FX Go5250", NV30_TCL_PRIMITIVE_3D|0x0600, NV_34, 0}, -{0x0326, "GeForce FX 5500", NV30_TCL_PRIMITIVE_3D|0x0600, NV_34, 0}, -{0x0327, "GeForce FX 5100", NV30_TCL_PRIMITIVE_3D|0x0600, NV_34, 0}, -{0x0328, "GeForce FX Go5200 32M/64M", NV30_TCL_PRIMITIVE_3D|0x0600, NV_34, 0}, -{0x0329, "GeForce FX Go5200", NV30_TCL_PRIMITIVE_3D|0x0600, NV_34, 0}, -{0x032A, "Quadro NVS 280 PCI", NV30_TCL_PRIMITIVE_3D|0x0600, NV_34, 0}, -{0x032B, "Quadro FX 500/600 PCI", NV30_TCL_PRIMITIVE_3D|0x0600, NV_34, 0}, -{0x032C, "GeForce FX Go 5300", NV30_TCL_PRIMITIVE_3D|0x0600, NV_34, 0}, -{0x032D, "GeForce FX Go5100", NV30_TCL_PRIMITIVE_3D|0x0600, NV_34, 0}, -{0x032F, "NV34GL", NV30_TCL_PRIMITIVE_3D|0x0600, NV_34, 0}, +{0x0320, "GeForce FX 5200", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, +{0x0321, "GeForce FX 5200 Ultra", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, +{0x0322, "GeForce FX 5200", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, +{0x0323, "GeForce FX 5200LE", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, +{0x0324, "GeForce FX Go5200", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, +{0x0325, "GeForce FX Go5250", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, +{0x0326, "GeForce FX 5500", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, +{0x0327, "GeForce FX 5100", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, +{0x0328, "GeForce FX Go5200 32M/64M", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, +{0x0329, "GeForce FX Go5200", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, +{0x032A, "Quadro NVS 280 PCI", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, +{0x032B, "Quadro FX 500/600 PCI", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, +{0x032C, "GeForce FX Go 5300", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, +{0x032D, "GeForce FX Go5100", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, +{0x032F, "NV34GL", NV30_TCL_PRIMITIVE_3D|0x0600, NV_30, 0}, {0x0330, "GeForce FX 5900 Ultra", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, {0x0331, "GeForce FX 5900", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, {0x0332, "GeForce FX 5900XT", NV30_TCL_PRIMITIVE_3D|0x0400, NV_30, 0}, -- cgit v1.2.3 From 1f7378ee465eba8d82d224a7bf835e38c5ab6ee2 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 3 Oct 2007 16:30:42 -0700 Subject: Replace some structure-based batch preparation with plain OUT_BATCH. OUT_BATCH is far more amenable to the upcoming relocations being done for TTM support. --- src/mesa/drivers/dri/i965/intel_blit.c | 55 +++++++++++++++------------------- src/mesa/drivers/dri/i965/intel_reg.h | 6 +++- 2 files changed, 29 insertions(+), 32 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index f88cbb2328..da6b68c22b 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -535,9 +535,9 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel, GLshort w, GLshort h, GLenum logic_op) { - struct xy_setup_blit setup; struct xy_text_immediate_blit text; int dwords = ((src_size + 7) & ~7) / 4; + uint32_t opcode, br13; assert( logic_op - GL_CLEAR >= 0 ); assert( logic_op - GL_CLEAR < 0x10 ); @@ -554,31 +554,6 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel, __FUNCTION__, dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords); - memset(&setup, 0, sizeof(setup)); - - setup.br0.client = CLIENT_2D; - setup.br0.opcode = OPCODE_XY_SETUP_BLT; - setup.br0.write_alpha = (cpp == 4); - setup.br0.write_rgb = (cpp == 4); - setup.br0.dst_tiled = dst_tiled; - setup.br0.length = (sizeof(setup) / sizeof(int)) - 2; - - setup.br13.dest_pitch = dst_pitch; - setup.br13.rop = translate_raster_op(logic_op); - setup.br13.color_depth = (cpp == 4) ? BR13_8888 : BR13_565; - setup.br13.clipping_enable = 0; - setup.br13.mono_source_transparency = 1; - - setup.dw2.clip_y1 = 0; - setup.dw2.clip_x1 = 0; - setup.dw3.clip_y2 = 100; - setup.dw3.clip_x2 = 100; - - setup.dest_base_addr = bmBufferOffset(intel, dst_buffer) + dst_offset; - setup.background_color = 0; - setup.foreground_color = fg_color; - setup.pattern_base_addr = 0; - memset(&text, 0, sizeof(text)); text.dw0.client = CLIENT_2D; text.dw0.opcode = OPCODE_XY_TEXT_IMMEDIATE_BLT; @@ -594,15 +569,33 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel, text.dw2.dest_x2 = x + w; intel_batchbuffer_require_space( intel->batch, - sizeof(setup) + + (8 * 4) + sizeof(text) + dwords, INTEL_BATCH_NO_CLIPRECTS ); - intel_batchbuffer_data( intel->batch, - &setup, - sizeof(setup), - INTEL_BATCH_NO_CLIPRECTS ); + opcode = XY_SETUP_BLT_CMD; + if (cpp == 4) + opcode |= XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB; + if (dst_tiled) + opcode |= XY_DST_TILED; + + br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29); + if (cpp == 2) + br13 |= BR13_565 << 24; + else + br13 |= BR13_8888 << 24; + + BEGIN_BATCH(8, INTEL_BATCH_NO_CLIPRECTS); + OUT_BATCH(opcode); + OUT_BATCH(br13); + OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */ + OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */ + OUT_BATCH(bmBufferOffset(intel, dst_buffer) + dst_offset); + OUT_BATCH(0); /* bg */ + OUT_BATCH(fg_color); /* fg */ + OUT_BATCH(0); /* pattern base addr */ + ADVANCE_BATCH(); intel_batchbuffer_data( intel->batch, &text, diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h index 3c448b3559..618afb6cbb 100644 --- a/src/mesa/drivers/dri/i965/intel_reg.h +++ b/src/mesa/drivers/dri/i965/intel_reg.h @@ -32,7 +32,7 @@ #define CMD_3D (0x3<<29) - +#define CMD_2D (0x2<<29) #define _3DPRIMITIVE ((0x3<<29)|(0x1f<<24)) #define PRIM_INDIRECT (1<<23) @@ -73,6 +73,8 @@ #define BR00_OP_SRC_COPY_BLT 0x10C00000 #define BR13_SOLID_PATTERN 0x80000000 +#define XY_SETUP_BLT_CMD (CMD_2D | (1 << 22) | 6) + #define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|0x4) #define XY_COLOR_BLT_WRITE_ALPHA (1<<21) #define XY_COLOR_BLT_WRITE_RGB (1<<20) @@ -81,6 +83,8 @@ #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) +#define XY_BLT_WRITE_ALPHA (1<<21) +#define XY_BLT_WRITE_RGB (1<<20) #define XY_SRC_TILED (1<<15) #define XY_DST_TILED (1<<11) -- cgit v1.2.3 From 6bac9478c39fbe7955d10a21a2d7743697427a56 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 3 Oct 2007 16:59:01 -0700 Subject: Replace duplicated intel_reg.h with a shared header. --- src/mesa/drivers/dri/i915/i915_reg.h | 2 - src/mesa/drivers/dri/i915/intel_batchbuffer.c | 2 +- src/mesa/drivers/dri/i915/intel_blit.c | 18 ++--- src/mesa/drivers/dri/i915/intel_context.h | 3 - src/mesa/drivers/dri/i915/intel_reg.h | 88 ------------------------- src/mesa/drivers/dri/i965/intel_blit.c | 29 +++----- src/mesa/drivers/dri/i965/intel_reg.h | 95 --------------------------- src/mesa/drivers/dri/intel/intel_reg.h | 76 +++++++++++++++++++++ 8 files changed, 94 insertions(+), 219 deletions(-) delete mode 100644 src/mesa/drivers/dri/i915/intel_reg.h delete mode 100644 src/mesa/drivers/dri/i965/intel_reg.h create mode 100644 src/mesa/drivers/dri/intel/intel_reg.h (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i915/i915_reg.h b/src/mesa/drivers/dri/i915/i915_reg.h index a9fa56e8a6..b5585e70e7 100644 --- a/src/mesa/drivers/dri/i915/i915_reg.h +++ b/src/mesa/drivers/dri/i915/i915_reg.h @@ -34,8 +34,6 @@ #define I915_SET_FIELD( var, mask, value ) (var &= ~(mask), var |= value) -#define CMD_3D (0x3<<29) - #define PRIM3D_INLINE (CMD_3D | (0x1f<<24)) #define PRIM3D_TRILIST (0x0<<18) #define PRIM3D_TRISTRIP (0x1<<18) diff --git a/src/mesa/drivers/dri/i915/intel_batchbuffer.c b/src/mesa/drivers/dri/i915/intel_batchbuffer.c index 045ff0a5b0..639457d44a 100644 --- a/src/mesa/drivers/dri/i915/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i915/intel_batchbuffer.c @@ -28,7 +28,7 @@ #include "intel_batchbuffer.h" #include "intel_ioctl.h" #include "intel_decode.h" -#include "i915_debug.h" +#include "intel_reg.h" /* Relocations in kernel space: * - pass dma buffer seperately diff --git a/src/mesa/drivers/dri/i915/intel_blit.c b/src/mesa/drivers/dri/i915/intel_blit.c index 5d97f08434..b00b0d9e1b 100644 --- a/src/mesa/drivers/dri/i915/intel_blit.c +++ b/src/mesa/drivers/dri/i915/intel_blit.c @@ -105,8 +105,7 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv, } else { BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24) | (1 << 25); - CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA | - XY_SRC_COPY_BLT_WRITE_RGB); + CMD = (XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB); } for (i = 0; i < nbox; i++, pbox++) { @@ -184,8 +183,7 @@ intelEmitFillBlit(struct intel_context *intel, break; case 4: BR13 = dst_pitch | (0xF0 << 16) | (1 << 24) | (1 << 25); - CMD = (XY_COLOR_BLT_CMD | XY_COLOR_BLT_WRITE_ALPHA | - XY_COLOR_BLT_WRITE_RGB); + CMD = (XY_COLOR_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB); break; default: return; @@ -273,8 +271,7 @@ intelEmitCopyBlit(struct intel_context *intel, (((GLint) dst_pitch) & 0xffff) | (translate_raster_op(logic_op) << 16) | (1 << 24) | (1 << 25); CMD = - (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA | - XY_SRC_COPY_BLT_WRITE_RGB); + (XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB); break; default: return; @@ -443,15 +440,14 @@ intelClearWithBlit(GLcontext * ctx, GLbitfield mask) if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) { CMD = XY_COLOR_BLT_CMD; if (clearMask & BUFFER_BIT_DEPTH) - CMD |= XY_COLOR_BLT_WRITE_RGB; + CMD |= XY_BLT_WRITE_RGB; if (clearMask & BUFFER_BIT_STENCIL) - CMD |= XY_COLOR_BLT_WRITE_ALPHA; + CMD |= XY_BLT_WRITE_ALPHA; } else { /* clearing RGBA */ - CMD = (XY_COLOR_BLT_CMD | - XY_COLOR_BLT_WRITE_ALPHA | - XY_COLOR_BLT_WRITE_RGB); + CMD = XY_COLOR_BLT_CMD | + XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; } } else { diff --git a/src/mesa/drivers/dri/i915/intel_context.h b/src/mesa/drivers/dri/i915/intel_context.h index 1e9ccd5cdc..c8298dd9c4 100644 --- a/src/mesa/drivers/dri/i915/intel_context.h +++ b/src/mesa/drivers/dri/i915/intel_context.h @@ -460,9 +460,6 @@ extern void intelInitStateFuncs(struct dd_function_table *functions); #define BLENDFACT_INV_CONST_ALPHA 0x0f #define BLENDFACT_MASK 0x0f -#define MI_BATCH_BUFFER_END (0xA<<23) - - extern int intel_translate_compare_func(GLenum func); extern int intel_translate_stencil_op(GLenum op); extern int intel_translate_blend_factor(GLenum factor); diff --git a/src/mesa/drivers/dri/i915/intel_reg.h b/src/mesa/drivers/dri/i915/intel_reg.h deleted file mode 100644 index 7828ba6ad3..0000000000 --- a/src/mesa/drivers/dri/i915/intel_reg.h +++ /dev/null @@ -1,88 +0,0 @@ -/************************************************************************** - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ - - -#ifndef _INTEL_REG_H_ -#define _INTEL_REG_H_ - - - -#define CMD_3D (0x3<<29) - - -#define _3DPRIMITIVE ((0x3<<29)|(0x1f<<24)) -#define PRIM_INDIRECT (1<<23) -#define PRIM_INLINE (0<<23) -#define PRIM_INDIRECT_SEQUENTIAL (0<<17) -#define PRIM_INDIRECT_ELTS (1<<17) - -#define PRIM3D_TRILIST (0x0<<18) -#define PRIM3D_TRISTRIP (0x1<<18) -#define PRIM3D_TRISTRIP_RVRSE (0x2<<18) -#define PRIM3D_TRIFAN (0x3<<18) -#define PRIM3D_POLY (0x4<<18) -#define PRIM3D_LINELIST (0x5<<18) -#define PRIM3D_LINESTRIP (0x6<<18) -#define PRIM3D_RECTLIST (0x7<<18) -#define PRIM3D_POINTLIST (0x8<<18) -#define PRIM3D_DIB (0x9<<18) -#define PRIM3D_MASK (0x1f<<18) - -#define I915PACKCOLOR4444(r,g,b,a) \ - ((((a) & 0xf0) << 8) | (((r) & 0xf0) << 4) | ((g) & 0xf0) | ((b) >> 4)) - -#define I915PACKCOLOR1555(r,g,b,a) \ - ((((r) & 0xf8) << 7) | (((g) & 0xf8) << 2) | (((b) & 0xf8) >> 3) | \ - ((a) ? 0x8000 : 0)) - -#define I915PACKCOLOR565(r,g,b) \ - ((((r) & 0xf8) << 8) | (((g) & 0xfc) << 3) | (((b) & 0xf8) >> 3)) - -#define I915PACKCOLOR8888(r,g,b,a) \ - ((a<<24) | (r<<16) | (g<<8) | b) - - - - -#define BR00_BITBLT_CLIENT 0x40000000 -#define BR00_OP_COLOR_BLT 0x10000000 -#define BR00_OP_SRC_COPY_BLT 0x10C00000 -#define BR13_SOLID_PATTERN 0x80000000 - -#define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|0x4) -#define XY_COLOR_BLT_WRITE_ALPHA (1<<21) -#define XY_COLOR_BLT_WRITE_RGB (1<<20) - -#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) -#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) -#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) - -#define MI_WAIT_FOR_EVENT ((0x3<<23)) -#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) -#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) - -#endif diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index da6b68c22b..962bb24f67 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -110,8 +110,7 @@ void intelCopyBuffer( const __DRIdrawablePrivate *dPriv, } else { BR13 = (0xCC << 16) | (1<<24) | (1<<25); - CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA | - XY_SRC_COPY_BLT_WRITE_RGB); + CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; } if (src->tiled) { @@ -199,8 +198,7 @@ void intelEmitFillBlit( struct intel_context *intel, break; case 4: BR13 = (0xF0 << 16) | (1<<24) | (1<<25); - CMD = (XY_COLOR_BLT_CMD | XY_COLOR_BLT_WRITE_ALPHA | - XY_COLOR_BLT_WRITE_RGB); + CMD = XY_COLOR_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; break; default: return; @@ -290,8 +288,7 @@ void intelEmitCopyBlit( struct intel_context *intel, case 4: BR13 = (translate_raster_op(logic_op) << 16) | (1<<24) | (1<<25); - CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA | - XY_SRC_COPY_BLT_WRITE_RGB); + CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; break; default: return; @@ -388,12 +385,11 @@ void intelClearWithBlit(GLcontext *ctx, GLbitfield flags) break; case 4: BR13 = (0xF0 << 16) | (1<<24) | (1<<25); - BACK_CMD = FRONT_CMD = (XY_COLOR_BLT_CMD | - XY_COLOR_BLT_WRITE_ALPHA | - XY_COLOR_BLT_WRITE_RGB); + BACK_CMD = FRONT_CMD = XY_COLOR_BLT_CMD | + XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; DEPTH_CMD = XY_COLOR_BLT_CMD; - if (flags & BUFFER_BIT_DEPTH) DEPTH_CMD |= XY_COLOR_BLT_WRITE_RGB; - if (flags & BUFFER_BIT_STENCIL) DEPTH_CMD |= XY_COLOR_BLT_WRITE_ALPHA; + if (flags & BUFFER_BIT_DEPTH) DEPTH_CMD |= XY_BLT_WRITE_RGB; + if (flags & BUFFER_BIT_STENCIL) DEPTH_CMD |= XY_BLT_WRITE_ALPHA; break; default: return; @@ -517,11 +513,6 @@ void intelClearWithBlit(GLcontext *ctx, GLbitfield flags) } - -#define BR13_565 0x1 -#define BR13_8888 0x3 - - void intelEmitImmediateColorExpandBlit(struct intel_context *intel, GLuint cpp, @@ -576,15 +567,15 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel, opcode = XY_SETUP_BLT_CMD; if (cpp == 4) - opcode |= XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB; + opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; if (dst_tiled) opcode |= XY_DST_TILED; br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29); if (cpp == 2) - br13 |= BR13_565 << 24; + br13 |= BR13_565; else - br13 |= BR13_8888 << 24; + br13 |= BR13_8888; BEGIN_BATCH(8, INTEL_BATCH_NO_CLIPRECTS); OUT_BATCH(opcode); diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h deleted file mode 100644 index 618afb6cbb..0000000000 --- a/src/mesa/drivers/dri/i965/intel_reg.h +++ /dev/null @@ -1,95 +0,0 @@ -/************************************************************************** - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ - - -#ifndef _INTEL_REG_H_ -#define _INTEL_REG_H_ - - - -#define CMD_3D (0x3<<29) -#define CMD_2D (0x2<<29) - -#define _3DPRIMITIVE ((0x3<<29)|(0x1f<<24)) -#define PRIM_INDIRECT (1<<23) -#define PRIM_INLINE (0<<23) -#define PRIM_INDIRECT_SEQUENTIAL (0<<17) -#define PRIM_INDIRECT_ELTS (1<<17) - -#define PRIM3D_TRILIST (0x0<<18) -#define PRIM3D_TRISTRIP (0x1<<18) -#define PRIM3D_TRISTRIP_RVRSE (0x2<<18) -#define PRIM3D_TRIFAN (0x3<<18) -#define PRIM3D_POLY (0x4<<18) -#define PRIM3D_LINELIST (0x5<<18) -#define PRIM3D_LINESTRIP (0x6<<18) -#define PRIM3D_RECTLIST (0x7<<18) -#define PRIM3D_POINTLIST (0x8<<18) -#define PRIM3D_DIB (0x9<<18) -#define PRIM3D_MASK (0x1f<<18) - -#define I915PACKCOLOR4444(r,g,b,a) \ - ((((a) & 0xf0) << 8) | (((r) & 0xf0) << 4) | ((g) & 0xf0) | ((b) >> 4)) - -#define I915PACKCOLOR1555(r,g,b,a) \ - ((((r) & 0xf8) << 7) | (((g) & 0xf8) << 2) | (((b) & 0xf8) >> 3) | \ - ((a) ? 0x8000 : 0)) - -#define I915PACKCOLOR565(r,g,b) \ - ((((r) & 0xf8) << 8) | (((g) & 0xfc) << 3) | (((b) & 0xf8) >> 3)) - -#define I915PACKCOLOR8888(r,g,b,a) \ - ((a<<24) | (r<<16) | (g<<8) | b) - - - - -#define BR00_BITBLT_CLIENT 0x40000000 -#define BR00_OP_COLOR_BLT 0x10000000 -#define BR00_OP_SRC_COPY_BLT 0x10C00000 -#define BR13_SOLID_PATTERN 0x80000000 - -#define XY_SETUP_BLT_CMD (CMD_2D | (1 << 22) | 6) - -#define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|0x4) -#define XY_COLOR_BLT_WRITE_ALPHA (1<<21) -#define XY_COLOR_BLT_WRITE_RGB (1<<20) - -#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) -#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) -#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) - -#define XY_BLT_WRITE_ALPHA (1<<21) -#define XY_BLT_WRITE_RGB (1<<20) -#define XY_SRC_TILED (1<<15) -#define XY_DST_TILED (1<<11) - -#define FENCE_LINEAR 0 -#define FENCE_XMAJOR 1 -#define FENCE_YMAJOR 2 - -#endif diff --git a/src/mesa/drivers/dri/intel/intel_reg.h b/src/mesa/drivers/dri/intel/intel_reg.h new file mode 100644 index 0000000000..b9bbcdc704 --- /dev/null +++ b/src/mesa/drivers/dri/intel/intel_reg.h @@ -0,0 +1,76 @@ +/************************************************************************** + * + * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + +#define CMD_MI (0x0 << 29) +#define CMD_2D (0x2 << 29) +#define CMD_3D (0x3 << 29) + +#define MI_BATCH_BUFFER_END (CMD_MI | 0xA << 23) + +/* Stalls command execution waiting for the given events to have occurred. */ +#define MI_WAIT_FOR_EVENT (CMD_MI | (0x3 << 23)) +#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) +#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) + +/* Primitive dispatch on 830-945 */ +#define _3DPRIMITIVE (CMD_3D | (0x1f << 24)) +#define PRIM_INDIRECT (1<<23) +#define PRIM_INLINE (0<<23) +#define PRIM_INDIRECT_SEQUENTIAL (0<<17) +#define PRIM_INDIRECT_ELTS (1<<17) + +#define PRIM3D_TRILIST (0x0<<18) +#define PRIM3D_TRISTRIP (0x1<<18) +#define PRIM3D_TRISTRIP_RVRSE (0x2<<18) +#define PRIM3D_TRIFAN (0x3<<18) +#define PRIM3D_POLY (0x4<<18) +#define PRIM3D_LINELIST (0x5<<18) +#define PRIM3D_LINESTRIP (0x6<<18) +#define PRIM3D_RECTLIST (0x7<<18) +#define PRIM3D_POINTLIST (0x8<<18) +#define PRIM3D_DIB (0x9<<18) +#define PRIM3D_MASK (0x1f<<18) + +#define XY_SETUP_BLT_CMD (CMD_2D | (0x011 << 22) | 6) + +#define XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 4) + +#define XY_SRC_COPY_BLT_CMD (CMD_2D | (0x53 << 22) | 6) + +/* BR00 */ +#define XY_BLT_WRITE_ALPHA (1 << 21) +#define XY_BLT_WRITE_RGB (1 << 20) +#define XY_SRC_TILED (1 << 15) +#define XY_DST_TILED (1 << 11) + +/* BR13 */ +#define BR13_565 (0x1 << 24) +#define BR13_8888 (0x3 << 24) + +#define FENCE_LINEAR 0 +#define FENCE_XMAJOR 1 +#define FENCE_YMAJOR 2 -- cgit v1.2.3 From 0fc9efd8f0b1b6c4e3525a50e3478e5aef72531a Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 4 Oct 2007 11:16:50 -0700 Subject: Replace bmBufferOffset usage in batchbuffer setup with OUT_RELOC. This is in preparation for 965 TTM. --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 8 ++++--- src/mesa/drivers/dri/i965/intel_batchbuffer.h | 6 ++++++ src/mesa/drivers/dri/i965/intel_blit.c | 30 ++++++++++++++++----------- 3 files changed, 29 insertions(+), 15 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index fc2e3035af..89cd063d46 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -541,7 +541,8 @@ GLboolean brw_upload_vertices( struct brw_context *brw, for (i = 0; i < nr_enabled; i++) { OUT_BATCH( vbp.vb[i].vb0.dword ); - OUT_BATCH( bmBufferOffset(&brw->intel, vbp.vb[i].buffer) + vbp.vb[i].offset); + OUT_RELOC( vbp.vb[i].buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, + vbp.vb[i].offset); OUT_BATCH( vbp.vb[i].max_index ); OUT_BATCH( vbp.vb[i].instance_data_step_rate ); } @@ -632,8 +633,9 @@ void brw_upload_indices( struct brw_context *brw, BEGIN_BATCH(4, 0); OUT_BATCH( ib.header.dword ); - OUT_BATCH( bmBufferOffset(intel, buffer) + offset ); - OUT_BATCH( bmBufferOffset(intel, buffer) + offset + ib_size ); + OUT_RELOC( buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, offset); + OUT_RELOC( buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, + offset + ib_size); OUT_BATCH( 0 ); ADVANCE_BATCH(); } diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h b/src/mesa/drivers/dri/i965/intel_batchbuffer.h index 25e0a65e99..c40cad9638 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h @@ -121,6 +121,12 @@ void intel_batchbuffer_align( struct intel_batchbuffer *batch, #define BATCH_LOCALS #define BEGIN_BATCH(n, flags) intel_batchbuffer_require_space(intel->batch, n*4, flags) #define OUT_BATCH(d) intel_batchbuffer_emit_dword(intel->batch, d) + +#define OUT_RELOC(buf, flags, delta) do { \ + assert((delta) >= 0); \ + OUT_BATCH(bmBufferOffset(intel, buf) + delta); \ +} while (0) + #define ADVANCE_BATCH() do { } while(0) diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index 962bb24f67..7a9e1a2a3f 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -144,10 +144,10 @@ void intelCopyBuffer( const __DRIdrawablePrivate *dPriv, OUT_BATCH( dst_pitch | BR13 ); OUT_BATCH( (tmp.y1 << 16) | tmp.x1 ); OUT_BATCH( (tmp.y2 << 16) | tmp.x2 ); - OUT_BATCH( bmBufferOffset(intel, dst->buffer) ); + OUT_RELOC( dst->buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, 0 ); OUT_BATCH( (tmp.y1 << 16) | tmp.x1 ); OUT_BATCH( src_pitch ); - OUT_BATCH( bmBufferOffset(intel, src->buffer) ); + OUT_RELOC( src->buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0 ); ADVANCE_BATCH(); } } @@ -214,7 +214,7 @@ void intelEmitFillBlit( struct intel_context *intel, OUT_BATCH( dst_pitch | BR13 ); OUT_BATCH( (y << 16) | x ); OUT_BATCH( ((y+h) << 16) | (x+w) ); - OUT_BATCH( bmBufferOffset(intel, dst_buffer) + dst_offset ); + OUT_RELOC( dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, dst_offset ); OUT_BATCH( color ); ADVANCE_BATCH(); } @@ -325,10 +325,12 @@ void intelEmitCopyBlit( struct intel_context *intel, OUT_BATCH( dst_pitch | BR13 ); OUT_BATCH( (dst_y << 16) | dst_x ); OUT_BATCH( (dst_y2 << 16) | dst_x2 ); - OUT_BATCH( bmBufferOffset(intel, dst_buffer) + dst_offset ); + OUT_RELOC( dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, + dst_offset ); OUT_BATCH( (src_y << 16) | src_x ); OUT_BATCH( src_pitch ); - OUT_BATCH( bmBufferOffset(intel, src_buffer) + src_offset ); + OUT_RELOC( src_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, + src_offset ); ADVANCE_BATCH(); } else { @@ -337,10 +339,11 @@ void intelEmitCopyBlit( struct intel_context *intel, OUT_BATCH( (dst_pitch & 0xffff) | BR13 ); OUT_BATCH( (0 << 16) | dst_x ); OUT_BATCH( (h << 16) | dst_x2 ); - OUT_BATCH( bmBufferOffset(intel, dst_buffer) + dst_offset + dst_y * dst_pitch ); - OUT_BATCH( (0 << 16) | src_x ); + OUT_RELOC( dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, + dst_offset + dst_y * dst_pitch ); OUT_BATCH( (src_pitch & 0xffff) ); - OUT_BATCH( bmBufferOffset(intel, src_buffer) + src_offset + src_y * src_pitch ); + OUT_RELOC( src_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, + src_offset + src_y * src_pitch ); ADVANCE_BATCH(); } } @@ -480,7 +483,8 @@ void intelClearWithBlit(GLcontext *ctx, GLbitfield flags) OUT_BATCH( front_pitch | BR13 ); OUT_BATCH( (b.y1 << 16) | b.x1 ); OUT_BATCH( (b.y2 << 16) | b.x2 ); - OUT_BATCH( bmBufferOffset(intel, front->buffer) ); + OUT_RELOC( front->buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, + 0 ); OUT_BATCH( clear_color ); ADVANCE_BATCH(); } @@ -491,7 +495,8 @@ void intelClearWithBlit(GLcontext *ctx, GLbitfield flags) OUT_BATCH( back_pitch | BR13 ); OUT_BATCH( (b.y1 << 16) | b.x1 ); OUT_BATCH( (b.y2 << 16) | b.x2 ); - OUT_BATCH( bmBufferOffset(intel, back->buffer) ); + OUT_RELOC( back->buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, + 0 ); OUT_BATCH( clear_color ); ADVANCE_BATCH(); } @@ -502,7 +507,8 @@ void intelClearWithBlit(GLcontext *ctx, GLbitfield flags) OUT_BATCH( depth_pitch | BR13 ); OUT_BATCH( (b.y1 << 16) | b.x1 ); OUT_BATCH( (b.y2 << 16) | b.x2 ); - OUT_BATCH( bmBufferOffset(intel, depth->buffer) ); + OUT_RELOC( depth->buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, + 0 ); OUT_BATCH( clear_depth ); ADVANCE_BATCH(); } @@ -582,7 +588,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel, OUT_BATCH(br13); OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */ OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */ - OUT_BATCH(bmBufferOffset(intel, dst_buffer) + dst_offset); + OUT_RELOC(dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, dst_offset); OUT_BATCH(0); /* bg */ OUT_BATCH(fg_color); /* fg */ OUT_BATCH(0); /* pattern base addr */ -- cgit v1.2.3 From 77e0523fb7769df4bf43747e136b1653b2421b97 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 4 Oct 2007 12:07:25 -0700 Subject: [965] Replace various alignment code with a shared ALIGN() macro. In the process, fix some alignment issues: - Scratch space allocation was aligned into units of 1KB, while the allocation wanted units of bytes, so we never allocated enough space for scratch. - GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1. --- src/mesa/drivers/dri/i915/intel_context.h | 2 ++ src/mesa/drivers/dri/i965/brw_clip_state.c | 3 ++- src/mesa/drivers/dri/i965/brw_curbe.c | 2 +- src/mesa/drivers/dri/i965/brw_draw_upload.c | 2 +- src/mesa/drivers/dri/i965/brw_gs_state.c | 3 ++- src/mesa/drivers/dri/i965/brw_sf_state.c | 2 +- src/mesa/drivers/dri/i965/brw_state_cache.c | 2 +- src/mesa/drivers/dri/i965/brw_state_pool.c | 5 ++--- src/mesa/drivers/dri/i965/brw_tex_layout.c | 4 +--- src/mesa/drivers/dri/i965/brw_vs_state.c | 2 +- src/mesa/drivers/dri/i965/brw_wm_state.c | 4 ++-- src/mesa/drivers/dri/i965/bufmgr_fake.c | 2 +- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 4 ++-- src/mesa/drivers/dri/i965/intel_blit.c | 2 +- src/mesa/drivers/dri/i965/intel_context.h | 2 ++ src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 ++-- src/mesa/drivers/dri/i965/intel_pixel_bitmap.c | 9 ++------- src/mesa/drivers/dri/intel/intel_tex_layout.c | 20 +++++++------------- 18 files changed, 33 insertions(+), 41 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i915/intel_context.h b/src/mesa/drivers/dri/i915/intel_context.h index c8298dd9c4..ce9a362944 100644 --- a/src/mesa/drivers/dri/i915/intel_context.h +++ b/src/mesa/drivers/dri/i915/intel_context.h @@ -292,6 +292,8 @@ extern char *__progname; #define SUBPIXEL_X 0.125 #define SUBPIXEL_Y 0.125 +#define ALIGN(value, alignment) ((value + alignment - 1) & ~(alignment - 1)) + #define INTEL_FIREVERTICES(intel) \ do { \ if ((intel)->prim.flush) \ diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c index ae46d7a86e..ba2f0edf51 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_state.c +++ b/src/mesa/drivers/dri/i965/brw_clip_state.c @@ -43,7 +43,8 @@ static void upload_clip_unit( struct brw_context *brw ) memset(&clip, 0, sizeof(clip)); /* CACHE_NEW_CLIP_PROG */ - clip.thread0.grf_reg_count = ((brw->clip.prog_data->total_grf-1) & ~15) / 16; + clip.thread0.grf_reg_count = + ALIGN(brw->clip.prog_data->total_grf, 16) / 16 - 1; clip.thread0.kernel_start_pointer = brw->clip.prog_gs_offset >> 6; clip.thread3.urb_entry_read_length = brw->clip.prog_data->urb_read_length; clip.thread3.const_urb_entry_read_length = brw->clip.prog_data->curb_read_length; diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c index d3c88c1dca..fa4ea42aa6 100644 --- a/src/mesa/drivers/dri/i965/brw_curbe.c +++ b/src/mesa/drivers/dri/i965/brw_curbe.c @@ -304,7 +304,7 @@ static void upload_constant_buffer(struct brw_context *brw) if (!brw_pool_alloc(pool, bufsz, - 6, + 1 << 6, &brw->curbe.gs_offset)) { _mesa_printf("out of GS memory for curbe\n"); assert(0); diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 89cd063d46..b7795703fd 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -290,7 +290,7 @@ static void get_space( struct brw_context *brw, struct gl_buffer_object **vbo_return, GLuint *offset_return ) { - size = (size + 63) & ~63; + size = ALIGN(size, 64); if (brw->vb.upload.offset + size > BRW_UPLOAD_INIT_SIZE) wrap_buffers(brw, size); diff --git a/src/mesa/drivers/dri/i965/brw_gs_state.c b/src/mesa/drivers/dri/i965/brw_gs_state.c index 5826c01d4f..5db4dd4603 100644 --- a/src/mesa/drivers/dri/i965/brw_gs_state.c +++ b/src/mesa/drivers/dri/i965/brw_gs_state.c @@ -46,7 +46,8 @@ static void upload_gs_unit( struct brw_context *brw ) /* CACHE_NEW_GS_PROG */ if (brw->gs.prog_active) { - gs.thread0.grf_reg_count = ((brw->gs.prog_data->total_grf-1) & ~15) / 16; + gs.thread0.grf_reg_count = + ALIGN(brw->gs.prog_data->total_grf, 16) / 16 - 1; gs.thread0.kernel_start_pointer = brw->gs.prog_gs_offset >> 6; gs.thread3.urb_entry_read_length = brw->gs.prog_data->urb_read_length; } diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c index 236c6fd42a..2257916aae 100644 --- a/src/mesa/drivers/dri/i965/brw_sf_state.c +++ b/src/mesa/drivers/dri/i965/brw_sf_state.c @@ -118,7 +118,7 @@ static void upload_sf_unit( struct brw_context *brw ) memset(&sf, 0, sizeof(sf)); /* CACHE_NEW_SF_PROG */ - sf.thread0.grf_reg_count = ((brw->sf.prog_data->total_grf-1) & ~15) / 16; + sf.thread0.grf_reg_count = ALIGN(brw->sf.prog_data->total_grf, 16) / 16 - 1; sf.thread0.kernel_start_pointer = brw->sf.prog_gs_offset >> 6; sf.thread3.urb_entry_read_length = brw->sf.prog_data->urb_read_length; diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c b/src/mesa/drivers/dri/i965/brw_state_cache.c index 98d765ac0e..0e73ff8390 100644 --- a/src/mesa/drivers/dri/i965/brw_state_cache.c +++ b/src/mesa/drivers/dri/i965/brw_state_cache.c @@ -148,7 +148,7 @@ GLuint brw_upload_cache( struct brw_cache *cache, GLuint hash = hash_key(key, key_size); void *tmp = _mesa_malloc(key_size + cache->aux_size); - if (!brw_pool_alloc(cache->pool, data_size, 6, &offset)) { + if (!brw_pool_alloc(cache->pool, data_size, 1 << 6, &offset)) { /* Should not be possible: */ _mesa_printf("brw_pool_alloc failed\n"); diff --git a/src/mesa/drivers/dri/i965/brw_state_pool.c b/src/mesa/drivers/dri/i965/brw_state_pool.c index 708ae857ab..eda92a2fa8 100644 --- a/src/mesa/drivers/dri/i965/brw_state_pool.c +++ b/src/mesa/drivers/dri/i965/brw_state_pool.c @@ -41,10 +41,9 @@ GLboolean brw_pool_alloc( struct brw_mem_pool *pool, GLuint align, GLuint *offset_return) { - GLuint align_mask = (1<offset + align_mask) & ~align_mask) - pool->offset; + GLuint fixup = ALIGN(pool->offset, align) - pool->offset; - size = (size + 3) & ~3; + size = ALIGN(size, 4); if (pool->offset + fixup + size >= pool->size) { _mesa_printf("%s failed\n", __FUNCTION__); diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index 2094a1c8ad..e306c9cf10 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -37,8 +37,6 @@ #include "intel_tex_layout.h" #include "macros.h" -#define ALIGN(value, alignment) ((value + alignment - 1) & ~(alignment - 1)) - GLboolean brw_miptree_layout( struct intel_mipmap_tree *mt ) { /* XXX: these vary depending on image format: @@ -64,7 +62,7 @@ GLboolean brw_miptree_layout( struct intel_mipmap_tree *mt ) mt->pitch = ALIGN(width, align_w); pack_y_pitch = (height + 3) / 4; } else { - mt->pitch = ((mt->width0 * mt->cpp + 3) & ~3) / mt->cpp; + mt->pitch = ALIGN(mt->width0 * mt->cpp, 4) / mt->cpp; pack_y_pitch = ALIGN(mt->height0, align_h); } diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c index c225bf8f5c..f561979138 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_state.c +++ b/src/mesa/drivers/dri/i965/brw_vs_state.c @@ -44,7 +44,7 @@ static void upload_vs_unit( struct brw_context *brw ) /* CACHE_NEW_VS_PROG */ vs.thread0.kernel_start_pointer = brw->vs.prog_gs_offset >> 6; - vs.thread0.grf_reg_count = ((brw->vs.prog_data->total_grf-1) & ~15) / 16; + vs.thread0.grf_reg_count = ALIGN(brw->vs.prog_data->total_grf, 16) / 16 - 1; vs.thread3.urb_entry_read_length = brw->vs.prog_data->urb_read_length; vs.thread3.const_urb_entry_read_length = brw->vs.prog_data->curb_read_length; vs.thread3.dispatch_grf_start_reg = 1; diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c index 5b4f2abd0e..351de6d90e 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c @@ -62,7 +62,7 @@ static void upload_wm_unit(struct brw_context *brw ) memset(&wm, 0, sizeof(wm)); /* CACHE_NEW_WM_PROG */ - wm.thread0.grf_reg_count = ((brw->wm.prog_data->total_grf-1) & ~15) / 16; + wm.thread0.grf_reg_count = ALIGN(brw->wm.prog_data->total_grf, 16) / 16 - 1; wm.thread0.kernel_start_pointer = brw->wm.prog_gs_offset >> 6; wm.thread3.dispatch_grf_start_reg = brw->wm.prog_data->first_curbe_grf; wm.thread3.urb_entry_read_length = brw->wm.prog_data->urb_read_length; @@ -71,7 +71,7 @@ static void upload_wm_unit(struct brw_context *brw ) wm.wm5.max_threads = max_threads; if (brw->wm.prog_data->total_scratch) { - GLuint per_thread = (brw->wm.prog_data->total_scratch + 1023) / 1024; + GLuint per_thread = ALIGN(brw->wm.prog_data->total_scratch, 1024); GLuint total = per_thread * (max_threads + 1); /* Scratch space -- just have to make sure there is sufficient diff --git a/src/mesa/drivers/dri/i965/bufmgr_fake.c b/src/mesa/drivers/dri/i965/bufmgr_fake.c index a85121122f..65760c40d4 100644 --- a/src/mesa/drivers/dri/i965/bufmgr_fake.c +++ b/src/mesa/drivers/dri/i965/bufmgr_fake.c @@ -168,7 +168,7 @@ static GLboolean alloc_from_pool( struct intel_context *intel, if (!block) return GL_FALSE; - sz = (buf->size + align-1) & ~(align-1); + sz = ALIGN(buf->size, align); block->mem = mmAllocMem(pool->heap, sz, diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index fb58c0e708..7a6293b557 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -37,7 +37,7 @@ static void intel_batchbuffer_reset( struct intel_batchbuffer *batch ) assert(batch->map == NULL); batch->offset = (unsigned long)batch->ptr; - batch->offset = (batch->offset + 63) & ~63; + batch->offset = ALIGN(batch->offset, 64); batch->ptr = (unsigned char *) batch->offset; if (BATCH_SZ - batch->offset < BATCH_REFILL) { @@ -208,7 +208,7 @@ void intel_batchbuffer_align( struct intel_batchbuffer *batch, GLuint sz ) { unsigned long ptr = (unsigned long) batch->ptr; - unsigned long aptr = (ptr + align) & ~((unsigned long)align-1); + unsigned long aptr = ALIGN(ptr, align); GLuint fixup = aptr - ptr; if (intel_batchbuffer_space(batch) < fixup + sz) diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index 7a9e1a2a3f..d1c1c8afb6 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -533,7 +533,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel, GLenum logic_op) { struct xy_text_immediate_blit text; - int dwords = ((src_size + 7) & ~7) / 4; + int dwords = ALIGN(src_size, 8) / 4; uint32_t opcode, br13; assert( logic_op - GL_CLEAR >= 0 ); diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h index f63c2f613d..65898caaa7 100644 --- a/src/mesa/drivers/dri/i965/intel_context.h +++ b/src/mesa/drivers/dri/i965/intel_context.h @@ -252,6 +252,8 @@ void UNLOCK_HARDWARE( struct intel_context *intel ); #define SUBPIXEL_X 0.125 #define SUBPIXEL_Y 0.125 +#define ALIGN(value, alignment) ((value + alignment - 1) & ~(alignment - 1)) + /* ================================================================ * Color packing: */ diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 0fb33e27f4..268a982a97 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -233,8 +233,8 @@ GLboolean intel_miptree_image_data(struct intel_context *intel, if (dst->compressed) { alignment = intel_compressed_alignment(dst->internal_format); - src_row_pitch = ((src_row_pitch + alignment - 1) & ~(alignment - 1)); - width = ((width + alignment - 1) & ~(alignment - 1)); + src_row_pitch = ALIGN(src_row_pitch, alignment); + width = ALIGN(width, alignment); height = (height + 3) / 4; } diff --git a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c index 79c1fee9c0..3777422619 100644 --- a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c +++ b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c @@ -91,11 +91,6 @@ static void set_bit( GLubyte *dest, dest[bit/8] |= 1 << (bit % 8); } -static int align(int x, int align) -{ - return (x + align - 1) & ~(align - 1); -} - /* Extract a rectangle's worth of data from the bitmap. Called * per-cliprect. */ @@ -147,7 +142,7 @@ static GLuint get_bitmap_rect(GLsizei width, GLsizei height, } if (row_align) - bit = (bit + row_align - 1) & ~(row_align - 1); + bit = ALIGN(bit, row_align); } return count; @@ -268,7 +263,7 @@ do_blit_bitmap( GLcontext *ctx, for (px = 0; px < box_w; px += DX) { int h = MIN2(DY, box_h - py); int w = MIN2(DX, box_w - px); - GLuint sz = align(align(w,8) * h, 64)/8; + GLuint sz = ALIGN(ALIGN(w,8) * h, 64)/8; GLenum logic_op = ctx->Color.ColorLogicOpEnabled ? ctx->Color.LogicOp : GL_COPY; diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.c b/src/mesa/drivers/dri/intel/intel_tex_layout.c index fdecd3e186..e3c6e1c17c 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_layout.c +++ b/src/mesa/drivers/dri/intel/intel_tex_layout.c @@ -34,12 +34,6 @@ #include "intel_tex_layout.h" #include "macros.h" - -static int align(int value, int alignment) -{ - return (value + alignment - 1) & ~(alignment - 1); -} - GLuint intel_compressed_alignment(GLenum internalFormat) { GLuint alignment = 4; @@ -70,7 +64,7 @@ void i945_miptree_layout_2d( struct intel_mipmap_tree *mt ) if (mt->compressed) { align_w = intel_compressed_alignment(mt->internal_format); - mt->pitch = align(mt->width0, align_w); + mt->pitch = ALIGN(mt->width0, align_w); } /* May need to adjust pitch to accomodate the placement of @@ -82,10 +76,10 @@ void i945_miptree_layout_2d( struct intel_mipmap_tree *mt ) GLuint mip1_width; if (mt->compressed) { - mip1_width = align(minify(mt->width0), align_w) - + align(minify(minify(mt->width0)), align_w); + mip1_width = ALIGN(minify(mt->width0), align_w) + + ALIGN(minify(minify(mt->width0)), align_w); } else { - mip1_width = align(minify(mt->width0), align_w) + mip1_width = ALIGN(minify(mt->width0), align_w) + minify(minify(mt->width0)); } @@ -97,7 +91,7 @@ void i945_miptree_layout_2d( struct intel_mipmap_tree *mt ) /* Pitch must be a whole number of dwords, even though we * express it in texels. */ - mt->pitch = align(mt->pitch * mt->cpp, 4) / mt->cpp; + mt->pitch = ALIGN(mt->pitch * mt->cpp, 4) / mt->cpp; mt->total_height = 0; for ( level = mt->first_level ; level <= mt->last_level ; level++ ) { @@ -109,7 +103,7 @@ void i945_miptree_layout_2d( struct intel_mipmap_tree *mt ) if (mt->compressed) img_height = MAX2(1, height/4); else - img_height = align(height, align_h); + img_height = ALIGN(height, align_h); /* Because the images are packed better, the final offset @@ -120,7 +114,7 @@ void i945_miptree_layout_2d( struct intel_mipmap_tree *mt ) /* Layout_below: step right after second mipmap. */ if (level == mt->first_level + 1) { - x += align(width, align_w); + x += ALIGN(width, align_w); } else { y += img_height; -- cgit v1.2.3 From d85e8b088bda9a118494dd86464c4a495475e407 Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Sat, 6 Oct 2007 02:30:24 +0200 Subject: nouveau: move nv10 clear command, for usage by other gpu --- src/mesa/drivers/dri/nouveau/nouveau_context.c | 36 +++++++++++ src/mesa/drivers/dri/nouveau/nouveau_context.h | 6 +- src/mesa/drivers/dri/nouveau/nouveau_driver.c | 70 ++++++++++++++++++++- src/mesa/drivers/dri/nouveau/nv10_state.c | 86 +++----------------------- 4 files changed, 115 insertions(+), 83 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/nouveau/nouveau_context.c b/src/mesa/drivers/dri/nouveau/nouveau_context.c index f36483a3d4..a8569a9f15 100644 --- a/src/mesa/drivers/dri/nouveau/nouveau_context.c +++ b/src/mesa/drivers/dri/nouveau/nouveau_context.c @@ -378,3 +378,39 @@ void nouveauCopySubBuffer(__DRIdrawablePrivate *dPriv, { } +void nouveauClearBuffer(GLcontext *ctx, nouveau_renderbuffer_t *buffer, + int fill, int mask) +{ + nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); + int dimensions; + + if (!buffer) { + return; + } + + /* FIXME: only support 32 bits atm */ + + /* Surface that we will work on */ + nouveauObjectOnSubchannel(nmesa, NvSubCtxSurf2D, NvCtxSurf2D); + + BEGIN_RING_SIZE(NvSubCtxSurf2D, NV10_CONTEXT_SURFACES_2D_FORMAT, 4); + OUT_RING(0x0b); /* Y32 color format */ + OUT_RING((buffer->pitch<<16)|buffer->pitch); + OUT_RING(buffer->offset); + OUT_RING(buffer->offset); + + /* Now clear a rectangle */ + dimensions = ((buffer->mesa.Height)<<16) | (buffer->mesa.Width); + + nouveauObjectOnSubchannel(nmesa, NvSubGdiRectText, NvGdiRectText); + + BEGIN_RING_SIZE(NvSubGdiRectText, NV04_GDI_RECTANGLE_TEXT_OPERATION, 1); + OUT_RING(3); /* SRCCOPY */ + + BEGIN_RING_SIZE(NvSubGdiRectText, NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL1_TL, 5); + OUT_RING(0); /* top left */ + OUT_RING(dimensions); /* bottom right */ + OUT_RING(fill); + OUT_RING(0); /* top left */ + OUT_RING(dimensions); /* bottom right */ +} diff --git a/src/mesa/drivers/dri/nouveau/nouveau_context.h b/src/mesa/drivers/dri/nouveau/nouveau_context.h index 77fe13a9cd..9aff0ee668 100644 --- a/src/mesa/drivers/dri/nouveau/nouveau_context.h +++ b/src/mesa/drivers/dri/nouveau/nouveau_context.h @@ -133,9 +133,6 @@ typedef struct nouveau_context { nouveau_renderbuffer_t *color_buffer; nouveau_renderbuffer_t *depth_buffer; - /* Color buffer clear value */ - uint32_t clear_color_value; - /* Depth/stencil clear value */ uint32_t clear_value; @@ -234,6 +231,9 @@ extern void nouveauSwapBuffers(__DRIdrawablePrivate *dPriv); extern void nouveauCopySubBuffer(__DRIdrawablePrivate *dPriv, int x, int y, int w, int h); +extern void nouveauClearBuffer(GLcontext *ctx, nouveau_renderbuffer_t *buffer, + int fill, int mask); + /* Debugging utils: */ extern int NOUVEAU_DEBUG; diff --git a/src/mesa/drivers/dri/nouveau/nouveau_driver.c b/src/mesa/drivers/dri/nouveau/nouveau_driver.c index 4851c66835..8b76779002 100644 --- a/src/mesa/drivers/dri/nouveau/nouveau_driver.c +++ b/src/mesa/drivers/dri/nouveau/nouveau_driver.c @@ -35,6 +35,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "framebuffer.h" #include "utils.h" +#include "colormac.h" /* Wrapper for DRM_NOUVEAU_GETPARAM ioctl */ GLboolean nouveauDRMGetParam(nouveauContextPtr nmesa, @@ -135,7 +136,74 @@ static void nouveauFinish( GLcontext *ctx ) /* glClear */ static void nouveauClear( GLcontext *ctx, GLbitfield mask ) { - // XXX we really should do something here... + uint32_t clear_value; + nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); + + /* FIXME: should we clear front buffer, even if asked to do it? */ + if (mask & (BUFFER_BIT_FRONT_LEFT|BUFFER_BIT_BACK_LEFT)) { + GLubyte c[4]; + int color_bits = 32; + int color_mask = 0xffffffff; + + UNCLAMPED_FLOAT_TO_RGBA_CHAN(c,ctx->Color.ClearColor); + clear_value = PACK_COLOR_8888(c[3],c[0],c[1],c[2]); + + if (ctx->DrawBuffer) { + /* FIXME: find correct color buffer, instead of [0][0] */ + if (ctx->DrawBuffer->_ColorDrawBuffers[0][0]) { + color_bits = ctx->DrawBuffer->_ColorDrawBuffers[0][0]->RedBits; + color_bits += ctx->DrawBuffer->_ColorDrawBuffers[0][0]->GreenBits; + color_bits += ctx->DrawBuffer->_ColorDrawBuffers[0][0]->BlueBits; + color_bits += ctx->DrawBuffer->_ColorDrawBuffers[0][0]->AlphaBits; + } + } + + if (color_bits<24) { + clear_value = PACK_COLOR_565(c[0],c[1],c[2]); + color_mask = 0xffff; + } + + nouveauClearBuffer(ctx, nmesa->color_buffer, + clear_value, color_mask); + } + + if (mask & (BUFFER_BIT_DEPTH)) { + int depth_bits = 24; + int depth_mask; + if (ctx->DrawBuffer) { + if (ctx->DrawBuffer->_DepthBuffer) { + depth_bits = ctx->DrawBuffer->_DepthBuffer->DepthBits; + } + } + + switch(depth_bits) { + case 16: + clear_value = (uint32_t) (ctx->Depth.Clear * 32767.0); + depth_mask = 0xffff; + break; + default: + clear_value = ((uint32_t) (ctx->Depth.Clear * 16777215.0)) << 8; + depth_mask = 0xffffff00; + break; + } + + nouveauClearBuffer(ctx, nmesa->depth_buffer, + clear_value, depth_mask); + } + + if (mask & (BUFFER_BIT_STENCIL)) { + int stencil_bits = 0; + if (ctx->DrawBuffer) { + if (ctx->DrawBuffer->_StencilBuffer) { + stencil_bits = ctx->DrawBuffer->_StencilBuffer->StencilBits; + } + } + + if (stencil_bits>0) { + nouveauClearBuffer(ctx, nmesa->depth_buffer, + ctx->Stencil.Clear, (1<pitch<<16)|buffer->pitch); - OUT_RING(buffer->offset); - OUT_RING(buffer->offset); - - /* Now clear a rectangle */ - dimensions = ((buffer->mesa.Height)<<16) | (buffer->mesa.Width); - - nouveauObjectOnSubchannel(nmesa, NvSubGdiRectText, NvGdiRectText); - - BEGIN_RING_SIZE(NvSubGdiRectText, NV04_GDI_RECTANGLE_TEXT_OPERATION, 1); - OUT_RING(3); /* SRCCOPY */ - - BEGIN_RING_SIZE(NvSubGdiRectText, NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL1_TL, 5); - OUT_RING(0); /* top left */ - OUT_RING(dimensions); /* bottom right */ - OUT_RING(fill); - OUT_RING(0); /* top left */ - OUT_RING(dimensions); /* bottom right */ -} - -static void nv10Clear(GLcontext *ctx, GLbitfield mask) -{ - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - - if (mask & (BUFFER_BIT_FRONT_LEFT|BUFFER_BIT_BACK_LEFT)) { - nv10ClearBuffer(ctx, nmesa->color_buffer, - nmesa->clear_color_value, 0xffffffff); - } - /* FIXME: check depth bits */ - if (mask & (BUFFER_BIT_DEPTH)) { - nv10ClearBuffer(ctx, nmesa->depth_buffer, - nmesa->clear_value, 0xffffff00); - } - /* FIXME: check about stencil? */ - if (mask & (BUFFER_BIT_STENCIL)) { - nv10ClearBuffer(ctx, nmesa->depth_buffer, - nmesa->clear_value, 0x000000ff); - } -} - static void nv10ClearColor(GLcontext *ctx, const GLfloat color[4]) { - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - GLubyte c[4]; - UNCLAMPED_FLOAT_TO_RGBA_CHAN(c,color); - nmesa->clear_color_value = PACK_COLOR_8888(c[3],c[0],c[1],c[2]); + /* Not for NV10 */ } static void nv10ClearDepth(GLcontext *ctx, GLclampd d) { - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - -/* switch (ctx->DrawBuffer->_DepthBuffer->DepthBits) { - case 16: - nmesa->clear_value = (uint32_t)(d*0x7FFF); - break; - case 24:*/ - nmesa->clear_value = ((nmesa->clear_value&0x000000FF) | - (((uint32_t)(d*0xFFFFFF))<<8)); -/* break; - }*/ + /* Not for NV10 */ } static void nv10ClearStencil(GLcontext *ctx, GLint s) { - nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); - -/* if (ctx->DrawBuffer->_DepthBuffer->DepthBits == 24) {*/ - nmesa->clear_value = ((nmesa->clear_value&0xFFFFFF00)| - (s&0x000000FF)); -/* }*/ + /* Not for NV10 */ } static void nv10ClipPlane(GLcontext *ctx, GLenum plane, const GLfloat *equation) @@ -1037,10 +965,10 @@ void nv10InitStateFuncs(GLcontext *ctx, struct dd_function_table *func) func->BlendColor = nv10BlendColor; func->BlendEquationSeparate = nv10BlendEquationSeparate; func->BlendFuncSeparate = nv10BlendFuncSeparate; - func->Clear = nv10Clear; - func->ClearColor = nv10ClearColor; - func->ClearDepth = nv10ClearDepth; - func->ClearStencil = nv10ClearStencil; +/* func->Clear = nv10Clear;*/ /* Not for NV10 */ + func->ClearColor = nv10ClearColor; /* Not for NV10 */ + func->ClearDepth = nv10ClearDepth; /* Not for NV10 */ + func->ClearStencil = nv10ClearStencil; /* Not for NV10 */ func->ClipPlane = nv10ClipPlane; func->ColorMask = nv10ColorMask; func->ColorMaterial = nv10ColorMaterial; -- cgit v1.2.3 From 32699696e31234c8d4e4b08f255ba2134ec12db5 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Sun, 7 Oct 2007 22:49:56 +0200 Subject: r300: fragprog tex instruction now take writemask into acount. --- src/mesa/drivers/dri/r300/r300_fragprog.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.c b/src/mesa/drivers/dri/r300/r300_fragprog.c index cce8e68586..78ed44b09c 100644 --- a/src/mesa/drivers/dri/r300/r300_fragprog.c +++ b/src/mesa/drivers/dri/r300/r300_fragprog.c @@ -951,6 +951,10 @@ static void emit_tex(struct r300_fragment_program *fp, if (REG_GET_TYPE(dest) == REG_TYPE_OUTPUT) { rdest = dest; dest = get_temp_reg_tex(fp); + } else if (fpi->DstReg.WriteMask != WRITEMASK_XYZW) { + /* in case write mask isn't XYZW */ + rdest = dest; + dest = get_temp_reg_tex(fp); } hwdest = t_hw_dst(fp, dest, GL_TRUE, @@ -1016,7 +1020,7 @@ static void emit_tex(struct r300_fragment_program *fp, /* Copy from temp to output if needed */ if (REG_GET_VALID(rdest)) { - emit_arith(fp, PFS_OP_MAD, rdest, WRITEMASK_XYZW, dest, + emit_arith(fp, PFS_OP_MAD, rdest, fpi->DstReg.WriteMask, dest, pfs_one, pfs_zero, 0); free_temp(fp, dest); } -- cgit v1.2.3 From 4599683b480d295e407725e0fe99c357a0086092 Mon Sep 17 00:00:00 2001 From: Sergio Monteiro Basto Date: Mon, 8 Oct 2007 11:09:38 -0700 Subject: i915: Fix undefined ALIGN symbol from 77e0523fb7769df4bf43747e136b1653b2421b97. --- src/mesa/drivers/dri/intel/intel_tex_layout.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.c b/src/mesa/drivers/dri/intel/intel_tex_layout.c index e3c6e1c17c..4da636021b 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_layout.c +++ b/src/mesa/drivers/dri/intel/intel_tex_layout.c @@ -32,6 +32,7 @@ #include "intel_mipmap_tree.h" #include "intel_tex_layout.h" +#include "intel_context.h" #include "macros.h" GLuint intel_compressed_alignment(GLenum internalFormat) -- cgit v1.2.3 From de3073d377ee3a0c58fec4b1611cbf893a543c5b Mon Sep 17 00:00:00 2001 From: Mrc Gran Date: Wed, 10 Oct 2007 09:15:42 -0600 Subject: fix force_s3tc_enable option --- src/mesa/drivers/dri/i965/intel_context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c index 2cf311c713..7ec316aa8a 100644 --- a/src/mesa/drivers/dri/i965/intel_context.c +++ b/src/mesa/drivers/dri/i965/intel_context.c @@ -498,7 +498,7 @@ GLboolean intelInitContext( struct intel_context *intel, _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" ); _mesa_enable_extension( ctx, "GL_S3_s3tc" ); } - else if (driQueryOptionb (&intelScreen->optionCache, "force_s3tc_enable")) { + else if (driQueryOptionb (&intel->optionCache, "force_s3tc_enable")) { _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" ); } -- cgit v1.2.3