From c0d6e07909733af054cc592e2cfc6212155b0a9e Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 23 Mar 2009 12:29:02 -0700 Subject: i965: Fix occlusion query when no other WM state updates occur. Turns out that XXX comment was important. We weren't flagging the WM to re-update with the statistics enable, so we got zeroes out of our query. Bug #20740, fixes piglit occlusion_query test. Signed-off-by: Eric Anholt --- src/mesa/drivers/dri/i965/brw_wm_state.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c index 63fc8a004f..5b14074502 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c @@ -113,7 +113,7 @@ wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key) /* temporary sanity check assertion */ ASSERT(bfp->isGLSL == brw_wm_is_glsl(fp)); - /* XXX: This needs a flag to indicate when it changes. */ + /* _NEW_DEPTH */ key->stats_wm = intel->stats_wm; /* _NEW_LINE */ @@ -282,7 +282,8 @@ const struct brw_tracked_state brw_wm_unit = { .mesa = (_NEW_POLYGON | _NEW_POLYGONSTIPPLE | _NEW_LINE | - _NEW_COLOR), + _NEW_COLOR | + _NEW_DEPTH), .brw = (BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_CURBE_OFFSETS | -- cgit v1.2.3 From bae07564c487b3cb02ba060edbb57a895874738a Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 23 Mar 2009 13:48:24 -0700 Subject: i965: Fix trailing "d" in debug output for 3DSTATE_VERTEX_ELEMENTS. --- src/mesa/drivers/dri/intel/intel_decode.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_decode.c b/src/mesa/drivers/dri/intel/intel_decode.c index f2e2e61935..f04638206d 100644 --- a/src/mesa/drivers/dri/intel/intel_decode.c +++ b/src/mesa/drivers/dri/intel/intel_decode.c @@ -1513,7 +1513,7 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, int *failures) for (i = 1; i < len;) { instr_out(data, hw_offset, i, "buffer %d: %svalid, type 0x%04x, " - "src offset 0x%04xd bytes\n", + "src offset 0x%04x bytes\n", data[i] >> 27, data[i] & (1 << 26) ? "" : "in", (data[i] >> 16) & 0x1ff, -- cgit v1.2.3 From b013f945d8514ed827183a4cbfbc4dccc100704f Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 23 Mar 2009 22:30:12 -0700 Subject: i965: Clean up a bit of mess with unneeded variables in emit_interp. --- src/mesa/drivers/dri/i965/brw_wm_fp.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c index 533be3858e..cff50b85e2 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_fp.c +++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c @@ -313,18 +313,13 @@ static void emit_interp( struct brw_wm_compile *c, struct prog_dst_register dst = dst_reg(PROGRAM_INPUT, idx); struct prog_src_register interp = src_reg(PROGRAM_PAYLOAD, idx); struct prog_src_register deltas = get_delta_xy(c); - struct prog_src_register arg2; - GLuint opcode; - + /* Need to use PINTERP on attributes which have been * multiplied by 1/W in the SF program, and LINTERP on those * which have not: */ switch (idx) { case FRAG_ATTRIB_WPOS: - opcode = WM_LINTERP; - arg2 = src_undef(); - /* Have to treat wpos.xy specially: */ emit_op(c, @@ -345,7 +340,7 @@ static void emit_interp( struct brw_wm_compile *c, 0, interp, deltas, - arg2); + src_undef()); break; case FRAG_ATTRIB_COL0: case FRAG_ATTRIB_COL1: -- cgit v1.2.3 From 411d913ccea362dbd75411266d7abb685214ee93 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 23 Mar 2009 22:35:03 -0700 Subject: i965: Fix fog coordinate g,b,a values when glFrontFacing isn't used. Previously, we would sample (f,glFrontFacing,undef,undef) instead of the (f,0,0,1) that fragment.fogcoord is supposed to return. Due to glFrontFacing's presence in FOGC.y, we'll still give bad results there when glFrontFacing is used. Bug #19122, piglit testcase fp-fog. --- src/mesa/drivers/dri/i965/brw_wm_fp.c | 50 +++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c index cff50b85e2..63a7593449 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_fp.c +++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c @@ -363,6 +363,56 @@ static void emit_interp( struct brw_wm_compile *c, src_undef()); } break; + case FRAG_ATTRIB_FOGC: + /* The FOGC input is really special. When a program uses glFogFragCoord, + * the results returned are supposed to be (f,0,0,1). But for Mesa GLSL, + * the glFrontFacing and glPointCoord values are also stashed in FOGC. + * So, write the interpolated fog value to X, then either 0, 1, or the + * stashed values to Y, Z, W. Note that this means that + * glFogFragCoord.yzw can be wrong in those cases! + */ + + /* Interpolate the fog coordinate */ + emit_op(c, + WM_PINTERP, + dst_mask(dst, WRITEMASK_X), + 0, + interp, + deltas, + get_pixel_w(c)); + + /* Move the front facing value into FOGC.y if it's needed. */ + if (c->fp->program.UsesFrontFacing) { + emit_op(c, + WM_PINTERP, + dst_mask(dst, WRITEMASK_Y), + 0, + interp, + deltas, + get_pixel_w(c)); + } else { + emit_op(c, + OPCODE_MOV, + dst_mask(dst, WRITEMASK_Y), + 0, + src_swizzle1(interp, SWIZZLE_ZERO), + src_undef(), + src_undef()); + } + + /* Should do the PointCoord thing here. */ + emit_op(c, + OPCODE_MOV, + dst_mask(dst, WRITEMASK_ZW), + 0, + src_swizzle(interp, + SWIZZLE_ZERO, + SWIZZLE_ZERO, + SWIZZLE_ZERO, + SWIZZLE_ONE), + src_undef(), + src_undef()); + break; default: emit_op(c, WM_PINTERP, -- cgit v1.2.3 From 699db6d842c52d0b3b98b320f8ef1104a65fa783 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 23 Mar 2009 16:29:31 -0700 Subject: i965: Fix glFrontFacing in twoside GLSL demo. This also cuts instructions by just using the existing bit in the payload rather than computing it from the determinant in the SF unit and passing it as a varying down to the WM. Something still goes wrong with getting the backface color right, but a simpler shader appears to get the right result. --- src/mesa/drivers/dri/i965/brw_sf_emit.c | 32 ------------------------------- src/mesa/drivers/dri/i965/brw_wm.c | 2 ++ src/mesa/drivers/dri/i965/brw_wm.h | 3 ++- src/mesa/drivers/dri/i965/brw_wm_debug.c | 3 +++ src/mesa/drivers/dri/i965/brw_wm_emit.c | 32 +++++++++++++++++++++++++++++++ src/mesa/drivers/dri/i965/brw_wm_fp.c | 11 ++++++----- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 33 ++++++++++++++++++++++++++++++++ src/mesa/drivers/dri/i965/brw_wm_pass1.c | 1 + 8 files changed, 79 insertions(+), 38 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_sf_emit.c b/src/mesa/drivers/dri/i965/brw_sf_emit.c index ffdb0ae6df..862835f157 100644 --- a/src/mesa/drivers/dri/i965/brw_sf_emit.c +++ b/src/mesa/drivers/dri/i965/brw_sf_emit.c @@ -59,37 +59,6 @@ static GLboolean have_attr(struct brw_sf_compile *c, return (c->key.attrs & (1<func; - int i; - - if (!have_attr(c, VERT_RESULT_FOGC)) - return; - - brw_push_insn_state(p); - brw_CMP(p, brw_null_reg(), - c->key.frontface_ccw ? BRW_CONDITIONAL_G : BRW_CONDITIONAL_L, - c->det, brw_imm_f(0)); - brw_set_predicate_control(p, BRW_PREDICATE_NONE); - for (i = 0; i < 3; i++) { - struct brw_reg fogc = get_vert_attr(c, c->vert[i],FRAG_ATTRIB_FOGC); - brw_MOV(p, get_element(fogc, 1), brw_imm_f(0)); - brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); - brw_MOV(p, get_element(fogc, 1), brw_imm_f(1)); - brw_set_predicate_control(p, BRW_PREDICATE_NONE); - } - brw_pop_insn_state(p); -} - - /*********************************************************************** * Twoside lighting */ @@ -384,7 +353,6 @@ void brw_emit_tri_setup( struct brw_sf_compile *c, GLboolean allocate) invert_det(c); copy_z_inv_w(c); - do_front_facing(c); if (c->key.do_twoside_color) do_twoside_color(c); diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 1645ca0b70..7909fd65a9 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -40,6 +40,8 @@ GLuint brw_wm_nr_args( GLuint opcode ) { switch (opcode) { + case WM_FRONTFACING: + return 0; case WM_PIXELXY: case WM_CINTERP: case WM_WPOSXY: diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index 7f0e5702f2..03dc08fcca 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -172,7 +172,8 @@ struct brw_wm_instruction { #define WM_CINTERP (MAX_OPCODE + 5) #define WM_WPOSXY (MAX_OPCODE + 6) #define WM_FB_WRITE (MAX_OPCODE + 7) -#define MAX_WM_OPCODE (MAX_OPCODE + 8) +#define WM_FRONTFACING (MAX_OPCODE + 8) +#define MAX_WM_OPCODE (MAX_OPCODE + 9) #define PROGRAM_PAYLOAD (PROGRAM_FILE_MAX) #define PAYLOAD_DEPTH (FRAG_ATTRIB_MAX) diff --git a/src/mesa/drivers/dri/i965/brw_wm_debug.c b/src/mesa/drivers/dri/i965/brw_wm_debug.c index 8f07f89ebc..220821087c 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_debug.c +++ b/src/mesa/drivers/dri/i965/brw_wm_debug.c @@ -130,6 +130,9 @@ void brw_wm_print_insn( struct brw_wm_compile *c, case WM_FB_WRITE: _mesa_printf(" = FB_WRITE"); break; + case WM_FRONTFACING: + _mesa_printf(" = FRONTFACING"); + break; default: _mesa_printf(" = %s", _mesa_opcode_string(inst->opcode)); break; diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index f2dca9caa6..4372ed3d9a 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -254,6 +254,34 @@ static void emit_cinterp( struct brw_compile *p, } } +/* Sets the destination channels to 1.0 or 0.0 according to glFrontFacing. */ +static void emit_frontfacing( struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask ) +{ + struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD); + GLuint i; + + if (!(mask & WRITEMASK_XYZW)) + return; + + for (i = 0; i < 4; i++) { + if (mask & (1<target, inst->eot); break; + case WM_FRONTFACING: + emit_frontfacing(p, dst, dst_flags); + break; + /* Straightforward arithmetic: */ case OPCODE_ADD: diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c index 63a7593449..a7f5f1b9a2 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_fp.c +++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c @@ -58,7 +58,8 @@ static const char *wm_opcode_strings[] = { "PINTERP", "CINTERP", "WPOSXY", - "FB_WRITE" + "FB_WRITE", + "FRONTFACING", }; #if 0 @@ -384,12 +385,12 @@ static void emit_interp( struct brw_wm_compile *c, /* Move the front facing value into FOGC.y if it's needed. */ if (c->fp->program.UsesFrontFacing) { emit_op(c, - WM_PINTERP, + WM_FRONTFACING, dst_mask(dst, WRITEMASK_Y), 0, - interp, - deltas, - get_pixel_w(c)); + src_undef(), + src_undef(), + src_undef()); } else { emit_op(c, OPCODE_MOV, diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 4cf092226c..b3c15fe87f 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -653,6 +653,36 @@ static void emit_pinterp(struct brw_wm_compile *c, } } +/* Sets the destination channels to 1.0 or 0.0 according to glFrontFacing. */ +static void emit_frontfacing(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_compile *p = &c->func; + struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD); + struct brw_reg dst; + GLuint mask = inst->DstReg.WriteMask; + int i; + + for (i = 0; i < 4; i++) { + if (mask & (1< Date: Tue, 24 Mar 2009 09:53:22 -0600 Subject: i965: fix point rasterization when rendering to FBO The FBO pixel coordinate system, with (0,0) as the upper-left pixel, is inverted in Y compared to the normal OpenGL pixel coordinate system, which has (0,0) as its lower-left pixel. Viewport and polygon stipple are sensitive to this inversion; so is point rasterization. The basic fix is simple: when rendering to an FBO, instead of the normal RASTRULE_UPPER_RIGHT that's appropriate for OpenGL windows, use the Y inversion RASTRULE_LOWER_RIGHT. Unfortunately, current Intel documentation has this value listed as "Reserved, but not seen as useful". It does work on at least some i965-class devices, though; and the worst that could happen if an older device didn't support it would be incorrect point rasterization to FBOs, which is what happens already, so this fix is at least no worse than what happens presently, and is better for some (and possibly all) i965-class devices. --- src/gallium/drivers/i965simple/brw_defines.h | 18 ++++++++++++++++++ src/mesa/drivers/dri/i965/brw_defines.h | 18 ++++++++++++++++++ src/mesa/drivers/dri/i965/brw_sf_state.c | 28 +++++++++++++++++++++++++++- 3 files changed, 63 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/gallium/drivers/i965simple/brw_defines.h b/src/gallium/drivers/i965simple/brw_defines.h index 9379a397f6..715d2d2d01 100644 --- a/src/gallium/drivers/i965simple/brw_defines.h +++ b/src/gallium/drivers/i965simple/brw_defines.h @@ -289,6 +289,24 @@ #define BRW_RASTRULE_UPPER_LEFT 0 #define BRW_RASTRULE_UPPER_RIGHT 1 +/* These are listed as "Reserved, but not seen as useful" + * in Intel documentation (page 212, "Point Rasterization Rule", + * section 7.4 "SF Pipeline State Summary", of document + * "Intel® 965 Express Chipset Family and Intel® G35 Express + * Chipset Graphics Controller Programmer's Reference Manual, + * Volume 2: 3D/Media", Revision 1.0b as of January 2008, + * available at + * http://intellinuxgraphics.org/documentation.html + * at the time of this writing). + * + * These appear to be supported on at least some + * i965-family devices, and the BRW_RASTRULE_LOWER_RIGHT + * is useful when using OpenGL to render to a FBO + * (which has the pixel coordinate Y orientation inverted + * with respect to the normal OpenGL pixel coordinate system). + */ +#define BRW_RASTRULE_LOWER_LEFT 2 +#define BRW_RASTRULE_LOWER_RIGHT 3 #define BRW_RENDERTARGET_CLAMPRANGE_UNORM 0 #define BRW_RENDERTARGET_CLAMPRANGE_SNORM 1 diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 590b064c7e..74dbba4fdd 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -225,6 +225,24 @@ #define BRW_RASTRULE_UPPER_LEFT 0 #define BRW_RASTRULE_UPPER_RIGHT 1 +/* These are listed as "Reserved, but not seen as useful" + * in Intel documentation (page 212, "Point Rasterization Rule", + * section 7.4 "SF Pipeline State Summary", of document + * "Intel® 965 Express Chipset Family and Intel® G35 Express + * Chipset Graphics Controller Programmer's Reference Manual, + * Volume 2: 3D/Media", Revision 1.0b as of January 2008, + * available at + * http://intellinuxgraphics.org/documentation.html + * at the time of this writing). + * + * These appear to be supported on at least some + * i965-family devices, and the BRW_RASTRULE_LOWER_RIGHT + * is useful when using OpenGL to render to a FBO + * (which has the pixel coordinate Y orientation inverted + * with respect to the normal OpenGL pixel coordinate system). + */ +#define BRW_RASTRULE_LOWER_LEFT 2 +#define BRW_RASTRULE_LOWER_RIGHT 3 #define BRW_RENDERTARGET_CLAMPRANGE_UNORM 0 #define BRW_RENDERTARGET_CLAMPRANGE_SNORM 1 diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c index 93a9686f71..fc4eddda0a 100644 --- a/src/mesa/drivers/dri/i965/brw_sf_state.c +++ b/src/mesa/drivers/dri/i965/brw_sf_state.c @@ -231,7 +231,33 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key, sf.sf6.line_width = 0; /* _NEW_POINT */ - sf.sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT; /* opengl conventions */ + key->render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0; + if (!key->render_to_fbo) { + /* Rendering to an OpenGL window */ + sf.sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT; + } + else { + /* If rendering to an FBO, the pixel coordinate system is + * inverted with respect to the normal OpenGL coordinate + * system, so BRW_RASTRULE_LOWER_RIGHT is correct. + * But this value is listed as "Reserved, but not seen as useful" + * in Intel documentation (page 212, "Point Rasterization Rule", + * section 7.4 "SF Pipeline State Summary", of document + * "Intel® 965 Express Chipset Family and Intel® G35 Express + * Chipset Graphics Controller Programmer's Reference Manual, + * Volume 2: 3D/Media", Revision 1.0b as of January 2008, + * available at + * http://intellinuxgraphics.org/documentation.html + * at the time of this writing). + * + * It does work on at least some devices, if not all; + * if devices that don't support it can be identified, + * the likely failure case is that points are rasterized + * incorrectly, which is no worse than occurs without + * the value, so we're using it here. + */ + sf.sf6.point_rast_rule = BRW_RASTRULE_LOWER_RIGHT; + } /* XXX clamp max depends on AA vs. non-AA */ sf.sf7.sprite_point = key->point_sprite; -- cgit v1.2.3 From e101959b6a262ba34a12b407ea6f480e6b4d7d72 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Wed, 25 Mar 2009 11:13:28 +0100 Subject: r300: Texture size limit cleanups. Since core Mesa MAX_TEXTURE_LEVELS was bumped, we were incorrectly advertising a maximum texture size of 4096 on older chips, causing corrupted menu text in Extreme Tux Racer or Armagetron. Also make sure our texture image array can actually hold all the mipmap levels we support... --- src/mesa/drivers/dri/r300/r300_context.c | 19 ++++++++++++++++--- src/mesa/drivers/dri/r300/r300_context.h | 6 +++++- src/mesa/drivers/dri/r300/r300_texmem.c | 2 +- src/mesa/drivers/dri/r300/r300_texstate.c | 2 +- 4 files changed, 23 insertions(+), 6 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index fddd87b85f..12bee1a8fb 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -288,10 +288,23 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual, ctx->Const.MaxTextureMaxAnisotropy = 16.0; ctx->Const.MaxTextureLodBias = 16.0; - if (screen->chip_family >= CHIP_FAMILY_RV515) { + if (screen->chip_family >= CHIP_FAMILY_RV515) ctx->Const.MaxTextureLevels = 13; - ctx->Const.MaxTextureRectSize = 4096; - } + else + ctx->Const.MaxTextureLevels = 12; + + driCalculateMaxTextureLevels( r300->texture_heaps, + r300->nr_heaps, + & ctx->Const, + 4, + ctx->Const.MaxTextureLevels - 1, + MIN2(ctx->Const.MaxTextureLevels, + MAX_3D_TEXTURE_LEVELS) - 1, + ctx->Const.MaxTextureLevels - 1, + ctx->Const.MaxTextureLevels - 1, + ctx->Const.MaxTextureLevels - 1, + GL_FALSE, + 2 ); ctx->Const.MinPointSize = 1.0; ctx->Const.MinPointSizeAA = 1.0; diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index c15e9fa300..9c49586998 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -170,6 +170,10 @@ struct r300_dma { typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr; +/* Maximum number of mipmap levels supported by any supported GPU + */ +#define R300_MAX_TEXTURE_LEVELS 13 + /* Texture object in locally shared texture space. */ struct r300_tex_obj { @@ -178,7 +182,7 @@ struct r300_tex_obj { GLuint bufAddr; /* Offset to start of locally shared texture block */ - drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS]; + drm_radeon_tex_image_t image[6][R300_MAX_TEXTURE_LEVELS]; /* Six, for the cube faces */ GLboolean image_override; /* Image overridden by GLX_EXT_tfp */ diff --git a/src/mesa/drivers/dri/r300/r300_texmem.c b/src/mesa/drivers/dri/r300/r300_texmem.c index b03eefaa7c..0fe51b0c68 100644 --- a/src/mesa/drivers/dri/r300/r300_texmem.c +++ b/src/mesa/drivers/dri/r300/r300_texmem.c @@ -306,7 +306,7 @@ static void r300UploadSubImage(r300ContextPtr rmesa, r300TexObjPtr t, ASSERT(face < 6); /* Ensure we have a valid texture to upload */ - if ((hwlevel < 0) || (hwlevel >= RADEON_MAX_TEXTURE_LEVELS)) { + if ((hwlevel < 0) || (hwlevel >= R300_MAX_TEXTURE_LEVELS)) { _mesa_problem(NULL, "bad texture level in %s", __FUNCTION__); return; } diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index e2329f04ec..cadec7f3ec 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -345,7 +345,7 @@ static void r300SetTexImages(r300ContextPtr rmesa, numLevels = t->base.lastLevel - t->base.firstLevel + 1; - assert(numLevels <= RADEON_MAX_TEXTURE_LEVELS); + assert(numLevels <= R300_MAX_TEXTURE_LEVELS); /* Calculate mipmap offsets and dimensions for blitting (uploading) * The idea is that we lay out the mipmap levels within a block of -- cgit v1.2.3 From ff421b6e0b3ef218799350358b9bff5610f17c3a Mon Sep 17 00:00:00 2001 From: Alan Coopersmith Date: Tue, 24 Mar 2009 20:51:53 -0700 Subject: r300_cmdbuf.c: convert cast to a form supported by Sun cc Fixes Sun cc error: "r300_cmdbuf.c", line 142: invalid cast expression Signed-off-by: Alan Coopersmith --- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 3eb2dc8f5a..f4472756f1 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -139,7 +139,7 @@ static void r300PrintStateAtom(r300ContextPtr r300, struct r300_state_atom *stat if (RADEON_DEBUG & DEBUG_VERBOSE) { for (i = 0; i < dwords;) { - cmd = (drm_r300_cmd_header_t) state->cmd[i]; + cmd = *((drm_r300_cmd_header_t *) &state->cmd[i]); reg = (cmd.packet0.reghi << 8) | cmd.packet0.reglo; fprintf(stderr, " %s[%d]: cmdpacket0 (first reg=0x%04x, count=%d)\n", state->name, i, reg, cmd.packet0.count); -- cgit v1.2.3 From 6dd9c221012d5e091b2ede90d9b2a6f0383abd58 Mon Sep 17 00:00:00 2001 From: Alan Coopersmith Date: Mon, 23 Mar 2009 19:38:58 -0700 Subject: Convert u_int*_t to C99 standard uint*_t Signed-off-by: Alan Coopersmith --- include/EGL/eglext.h | 4 ++-- include/EGL/eglplatform.h | 2 +- src/mesa/drivers/dri/common/utils.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/include/EGL/eglext.h b/include/EGL/eglext.h index a4698ccd16..b65f7f2bcc 100644 --- a/include/EGL/eglext.h +++ b/include/EGL/eglext.h @@ -136,8 +136,8 @@ typedef EGLBoolean (EGLAPIENTRYP PFNEGLDESTROYIMAGEKHRPROC) (EGLDisplay dpy, EGL #define EGL_INTERLACED_MESA 0x4008 #define EGL_SCREEN_BIT_MESA 0x08 -typedef u_int32_t EGLScreenMESA; -typedef u_int32_t EGLModeMESA; +typedef uint32_t EGLScreenMESA; +typedef uint32_t EGLModeMESA; #ifdef EGL_EGLEXT_PROTOTYPES EGLAPI EGLBoolean EGLAPIENTRY eglChooseModeMESA(EGLDisplay dpy, EGLScreenMESA screen, const EGLint *attrib_list, EGLModeMESA *modes, EGLint modes_size, EGLint *num_modes); diff --git a/include/EGL/eglplatform.h b/include/EGL/eglplatform.h index d873428d75..0f34da063e 100644 --- a/include/EGL/eglplatform.h +++ b/include/EGL/eglplatform.h @@ -57,7 +57,7 @@ #endif typedef long int32_t; -typedef unsigned long u_int32_t; +typedef unsigned long uint32_t; typedef unsigned char uint8_t; #define snprintf _snprintf #define strcasecmp _stricmp diff --git a/src/mesa/drivers/dri/common/utils.c b/src/mesa/drivers/dri/common/utils.c index c9acd81be7..66f277c10b 100644 --- a/src/mesa/drivers/dri/common/utils.c +++ b/src/mesa/drivers/dri/common/utils.c @@ -481,7 +481,7 @@ driCreateConfigs(GLenum fb_format, GLenum fb_type, const uint8_t * depth_bits, const uint8_t * stencil_bits, unsigned num_depth_stencil_bits, const GLenum * db_modes, unsigned num_db_modes, - const u_int8_t * msaa_samples, unsigned num_msaa_modes) + const uint8_t * msaa_samples, unsigned num_msaa_modes) { static const uint8_t bits_table[4][4] = { /* R G B A */ -- cgit v1.2.3 From 7860b0886c2f650152e5fb56e2a31ed6079665c1 Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Thu, 19 Mar 2009 21:17:01 +0100 Subject: r300: cleanup swtcl a little - remove disabled code - silence compiler warnings (uinitialized values) - remove unneeded code --- src/mesa/drivers/dri/r300/r300_swtcl.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index d463ab3a2d..ba3621b16b 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -504,7 +504,7 @@ do { \ #define LOCAL_VARS(n) \ r300ContextPtr rmesa = R300_CONTEXT(ctx); \ - GLuint color[n], spec[n]; \ + GLuint color[n] = { 0, }, spec[n] = { 0, }; \ GLuint coloroffset = rmesa->swtcl.coloroffset; \ GLuint specoffset = rmesa->swtcl.specoffset; \ (void) color; (void) spec; (void) coloroffset; (void) specoffset; @@ -629,7 +629,6 @@ static void r300ChooseRenderState( GLcontext *ctx ) static void r300RenderStart(GLcontext *ctx) { r300ContextPtr rmesa = R300_CONTEXT( ctx ); - // fprintf(stderr, "%s\n", __FUNCTION__); r300ChooseRenderState(ctx); r300SetVertexFormat(ctx); @@ -669,8 +668,6 @@ static void r300RenderPrimitive(GLcontext *ctx, GLenum prim) return; r300RasterPrimitive( ctx, reduced_prim[prim] ); - // fprintf(stderr, "%s\n", __FUNCTION__); - } static void r300ResetLineStipple(GLcontext *ctx) @@ -713,11 +710,6 @@ void r300InitSwtcl(GLcontext *ctx) _tnl_need_projected_coords( ctx, GL_FALSE ); r300ChooseRenderState(ctx); - - _mesa_validate_all_lighting_tables( ctx ); - - tnl->Driver.NotifyMaterialChange = - _mesa_validate_all_lighting_tables; } void r300DestroySwtcl(GLcontext *ctx) -- cgit v1.2.3 From fd83289dbf747b4d2e0849f77c796323e5517f0b Mon Sep 17 00:00:00 2001 From: Roland Scheidegger Date: Mon, 2 Feb 2009 17:27:47 +0100 Subject: fix various small intel blitter issues use color format constants instead of magic numbers remove handling of cpp 0 or 3 (neither is possible) in various places don't misconfigure 8 bit surface blits as rgb565 --- src/mesa/drivers/dri/intel/intel_blit.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index 4e033082b4..4ae9b118a3 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -98,11 +98,11 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv, ASSERT(src->cpp == dst->cpp); if (cpp == 2) { - BR13 = (0xCC << 16) | (1 << 24); + BR13 = (0xCC << 16) | BR13_565; CMD = XY_SRC_COPY_BLT_CMD; } else { - BR13 = (0xCC << 16) | (1 << 24) | (1 << 25); + BR13 = (0xCC << 16) | BR13_8888; CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; } @@ -194,13 +194,15 @@ intelEmitFillBlit(struct intel_context *intel, switch (cpp) { case 1: + BR13 = (0xF0 << 16); + CMD = XY_COLOR_BLT_CMD; + break; case 2: - case 3: - BR13 = (0xF0 << 16) | (1 << 24); + BR13 = (0xF0 << 16) | BR13_565; CMD = XY_COLOR_BLT_CMD; break; case 4: - BR13 = (0xF0 << 16) | (1 << 24) | (1 << 25); + BR13 = (0xF0 << 16) | BR13_8888; CMD = XY_COLOR_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; break; default: @@ -335,12 +337,11 @@ intelEmitCopyBlit(struct intel_context *intel, CMD = XY_SRC_COPY_BLT_CMD; break; case 2: - case 3: - BR13 |= (1 << 24); + BR13 |= BR13_565; CMD = XY_SRC_COPY_BLT_CMD; break; case 4: - BR13 |= (1 << 24) | (1 << 25); + BR13 |= BR13_8888; CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; break; default: @@ -510,7 +511,7 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) /* Setup the blit command */ if (cpp == 4) { - BR13 |= (1 << 24) | (1 << 25); + BR13 |= BR13_8888; if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) { if (clearMask & BUFFER_BIT_DEPTH) CMD |= XY_BLT_WRITE_RGB; @@ -523,8 +524,8 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) } } else { - ASSERT(cpp == 2 || cpp == 0); - BR13 |= (1 << 24); + ASSERT(cpp == 2); + BR13 |= BR13_565; } #ifndef I915 -- cgit v1.2.3 From 79e2df63af4d231a1223887e79a819b3baac9a6c Mon Sep 17 00:00:00 2001 From: Roland Scheidegger Date: Fri, 27 Mar 2009 22:42:19 +0100 Subject: i965: add support for signed rgba texture format --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 ++++ src/mesa/drivers/dri/intel/intel_extensions.c | 1 + src/mesa/drivers/dri/intel/intel_tex_format.c | 4 ++++ 3 files changed, 9 insertions(+) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index e6113eff87..66ce928955 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -142,6 +142,7 @@ static GLuint translate_tex_format( GLuint mesa_format, GLenum internal_format, case MESA_FORMAT_SRGBA8: return BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB; + case MESA_FORMAT_SRGB_DXT1: return BRW_SURFACEFORMAT_BC1_UNORM_SRGB; @@ -159,6 +160,9 @@ static GLuint translate_tex_format( GLuint mesa_format, GLenum internal_format, case MESA_FORMAT_DUDV8: return BRW_SURFACEFORMAT_R8G8_SNORM; + case MESA_FORMAT_SIGNED_RGBA8888_REV: + return BRW_SURFACEFORMAT_R8G8B8A8_SNORM; + default: assert(0); return 0; diff --git a/src/mesa/drivers/dri/intel/intel_extensions.c b/src/mesa/drivers/dri/intel/intel_extensions.c index 8dd0b2461b..9ec1b4ec2f 100644 --- a/src/mesa/drivers/dri/intel/intel_extensions.c +++ b/src/mesa/drivers/dri/intel/intel_extensions.c @@ -132,6 +132,7 @@ static const struct dri_extension brw_extensions[] = { { "GL_ARB_shading_language_100", GL_VERSION_2_0_functions }, { "GL_ARB_shading_language_120", GL_VERSION_2_1_functions }, { "GL_ARB_shadow", NULL }, + { "GL_MESA_texture_signed_rgba", NULL }, { "GL_ARB_texture_non_power_of_two", NULL }, { "GL_ARB_vertex_shader", GL_ARB_vertex_shader_functions }, { "GL_EXT_shadow_funcs", NULL }, diff --git a/src/mesa/drivers/dri/intel/intel_tex_format.c b/src/mesa/drivers/dri/intel/intel_tex_format.c index 8732354e7a..ce33cdc218 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_format.c +++ b/src/mesa/drivers/dri/intel/intel_tex_format.c @@ -175,9 +175,13 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT5_EXT: return &_mesa_texformat_srgb_dxt1; + /* i915 could also do this */ case GL_DUDV_ATI: case GL_DU8DV8_ATI: return &_mesa_texformat_dudv8; + case GL_RGBA_SNORM: + case GL_RGBA8_SNORM: + return &_mesa_texformat_signed_rgba8888_rev; #endif default: -- cgit v1.2.3 From a693a2998c996f063edec8a83a4f6a175f39c471 Mon Sep 17 00:00:00 2001 From: Roland Scheidegger Date: Sat, 28 Mar 2009 01:43:50 +0100 Subject: i965: srgb texture fixes i965 can either do SRGBA8_REV format or SARGB8 format, but not SRGBA8. Could add SRGBA8_REV support to mesa, but simply use SARGB8 for now. While here, also add true srgb luminance / luminance_alpha support - unfortunately the published docs fail to mention which asics support this, tested on g43 so assume this works on any g4x. --- src/mesa/drivers/dri/i965/brw_defines.h | 8 +++++--- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 10 ++++++++-- src/mesa/drivers/dri/intel/intel_tex_format.c | 19 ++++++++++++++----- 3 files changed, 27 insertions(+), 10 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 74dbba4fdd..98fc909c2a 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -367,9 +367,10 @@ #define BRW_SURFACEFORMAT_L8A8_UNORM 0x114 #define BRW_SURFACEFORMAT_I16_FLOAT 0x115 #define BRW_SURFACEFORMAT_L16_FLOAT 0x116 -#define BRW_SURFACEFORMAT_A16_FLOAT 0x117 -#define BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM 0x119 -#define BRW_SURFACEFORMAT_B5G5R5X1_UNORM 0x11A +#define BRW_SURFACEFORMAT_A16_FLOAT 0x117 +#define BRW_SURFACEFORMAT_L8A8_UNORM_SRGB 0x118 +#define BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM 0x119 +#define BRW_SURFACEFORMAT_B5G5R5X1_UNORM 0x11A #define BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB 0x11B #define BRW_SURFACEFORMAT_R8G8_SSCALED 0x11C #define BRW_SURFACEFORMAT_R8G8_USCALED 0x11D @@ -386,6 +387,7 @@ #define BRW_SURFACEFORMAT_A4P4_UNORM 0x148 #define BRW_SURFACEFORMAT_R8_SSCALED 0x149 #define BRW_SURFACEFORMAT_R8_USCALED 0x14A +#define BRW_SURFACEFORMAT_L8_UNORM_SRGB 0x14C #define BRW_SURFACEFORMAT_R1_UINT 0x181 #define BRW_SURFACEFORMAT_YCRCB_NORMAL 0x182 #define BRW_SURFACEFORMAT_YCRCB_SWAPUVY 0x183 diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 66ce928955..2f1f4c55f9 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -140,8 +140,14 @@ static GLuint translate_tex_format( GLuint mesa_format, GLenum internal_format, case MESA_FORMAT_RGBA_DXT5: return BRW_SURFACEFORMAT_BC3_UNORM; - case MESA_FORMAT_SRGBA8: - return BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB; + case MESA_FORMAT_SARGB8: + return BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB; + + case MESA_FORMAT_SLA8: + return BRW_SURFACEFORMAT_L8A8_UNORM_SRGB; + + case MESA_FORMAT_SL8: + return BRW_SURFACEFORMAT_L8_UNORM_SRGB; case MESA_FORMAT_SRGB_DXT1: return BRW_SURFACEFORMAT_BC1_UNORM_SRGB; diff --git a/src/mesa/drivers/dri/intel/intel_tex_format.c b/src/mesa/drivers/dri/intel/intel_tex_format.c index ce33cdc218..3322a71130 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_format.c +++ b/src/mesa/drivers/dri/intel/intel_tex_format.c @@ -1,5 +1,6 @@ #include "intel_context.h" #include "intel_tex.h" +#include "intel_chipset.h" #include "main/texformat.h" #include "main/enums.h" @@ -160,15 +161,23 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, case GL_SRGB8_EXT: case GL_SRGB_ALPHA_EXT: case GL_SRGB8_ALPHA8_EXT: - case GL_SLUMINANCE_EXT: - case GL_SLUMINANCE8_EXT: - case GL_SLUMINANCE_ALPHA_EXT: - case GL_SLUMINANCE8_ALPHA8_EXT: case GL_COMPRESSED_SRGB_EXT: case GL_COMPRESSED_SRGB_ALPHA_EXT: case GL_COMPRESSED_SLUMINANCE_EXT: case GL_COMPRESSED_SLUMINANCE_ALPHA_EXT: - return &_mesa_texformat_srgba8; + return &_mesa_texformat_sargb8; + case GL_SLUMINANCE_EXT: + case GL_SLUMINANCE8_EXT: + if (IS_G4X(intel->intelScreen->deviceID)) + return &_mesa_texformat_sl8; + else + return &_mesa_texformat_sargb8; + case GL_SLUMINANCE_ALPHA_EXT: + case GL_SLUMINANCE8_ALPHA8_EXT: + if (IS_G4X(intel->intelScreen->deviceID)) + return &_mesa_texformat_sla8; + else + return &_mesa_texformat_sargb8; case GL_COMPRESSED_SRGB_S3TC_DXT1_EXT: case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT1_EXT: case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT3_EXT: -- cgit v1.2.3 From 37fb2d9b23eab5dbbb43a212c3475cb8016837d8 Mon Sep 17 00:00:00 2001 From: Adam Jackson Date: Mon, 30 Mar 2009 16:32:11 -0400 Subject: intel: Avoid mapping the texture image for CopyTex{,Sub}Image We don't upload the pixels with the CPU in that case, so the map will only serve as a way of triggering cache flushes over a bunch of data we don't touch. --- src/mesa/drivers/dri/intel/intel_tex_image.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c index e902187637..61ecabfa68 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_image.c +++ b/src/mesa/drivers/dri/intel/intel_tex_image.c @@ -482,12 +482,13 @@ intelTexImage(GLcontext * ctx, LOCK_HARDWARE(intel); if (intelImage->mt) { - texImage->Data = intel_miptree_image_map(intel, - intelImage->mt, - intelImage->face, - intelImage->level, - &dstRowStride, - intelImage->base.ImageOffsets); + if (pixels) + texImage->Data = intel_miptree_image_map(intel, + intelImage->mt, + intelImage->face, + intelImage->level, + &dstRowStride, + intelImage->base.ImageOffsets); texImage->RowStride = dstRowStride / intelImage->mt->cpp; } else { @@ -537,17 +538,18 @@ intelTexImage(GLcontext * ctx, format, type, pixels, unpack)) { _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage"); } - } - /* GL_SGIS_generate_mipmap */ - if (level == texObj->BaseLevel && texObj->GenerateMipmap) { - intel_generate_mipmap(ctx, target, texObj); + /* GL_SGIS_generate_mipmap */ + if (level == texObj->BaseLevel && texObj->GenerateMipmap) { + intel_generate_mipmap(ctx, target, texObj); + } } _mesa_unmap_teximage_pbo(ctx, unpack); if (intelImage->mt) { - intel_miptree_image_unmap(intel, intelImage->mt); + if (pixels) + intel_miptree_image_unmap(intel, intelImage->mt); texImage->Data = NULL; } -- cgit v1.2.3 From 79c55e55f808d77cb0dff7cda826719d5fda3c7d Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Wed, 11 Mar 2009 19:03:30 -0600 Subject: dri: use BorderColor instead of _BorderChan --- src/mesa/drivers/dri/gamma/gamma_tex.c | 13 +++++++++---- src/mesa/drivers/dri/i810/i810tex.c | 6 +++--- src/mesa/drivers/dri/i915/i830_texstate.c | 14 ++++++++++---- src/mesa/drivers/dri/i915/i915_texstate.c | 22 ++++++++++++++-------- src/mesa/drivers/dri/mach64/mach64_tex.c | 6 +++--- src/mesa/drivers/dri/mga/mgatex.c | 14 +++++++++----- src/mesa/drivers/dri/r128/r128_tex.c | 11 ++++++++--- src/mesa/drivers/dri/r200/r200_tex.c | 11 ++++++++--- src/mesa/drivers/dri/r300/r300_tex.c | 11 ++++++++--- src/mesa/drivers/dri/radeon/radeon_tex.c | 11 ++++++++--- src/mesa/drivers/dri/s3v/s3v_tex.c | 13 +++++++++---- src/mesa/drivers/dri/savage/savagetex.c | 6 +++--- src/mesa/drivers/dri/sis/sis_texstate.c | 15 ++++++++++----- 13 files changed, 102 insertions(+), 51 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/gamma/gamma_tex.c b/src/mesa/drivers/dri/gamma/gamma_tex.c index ca33c1740f..97797d4788 100644 --- a/src/mesa/drivers/dri/gamma/gamma_tex.c +++ b/src/mesa/drivers/dri/gamma/gamma_tex.c @@ -107,9 +107,14 @@ static void gammaSetTexFilter(gammaContextPtr gmesa, static void gammaSetTexBorderColor(gammaContextPtr gmesa, gammaTextureObjectPtr t, - GLubyte color[4]) + const GLfloat color[4]) { - t->TextureBorderColor = PACK_COLOR_8888(color[0], color[1], color[2], color[3]); + GLubyte c[4]; + CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]); + CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]); + CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]); + CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]); + t->TextureBorderColor = PACK_COLOR_8888(c[0], c[1], c[2], c[3]); } @@ -143,7 +148,7 @@ static void gammaTexParameter( GLcontext *ctx, GLenum target, break; case GL_TEXTURE_BORDER_COLOR: - gammaSetTexBorderColor( gmesa, t, tObj->_BorderChan ); + gammaSetTexBorderColor( gmesa, t, tObj->BorderColor ); break; case GL_TEXTURE_BASE_LEVEL: @@ -347,7 +352,7 @@ static void gammaBindTexture( GLcontext *ctx, GLenum target, gammaSetTexWrapping( t, tObj->WrapS, tObj->WrapT ); gammaSetTexFilter( gmesa, t, tObj->MinFilter, tObj->MagFilter, bias ); - gammaSetTexBorderColor( gmesa, t, tObj->_BorderChan ); + gammaSetTexBorderColor( gmesa, t, tObj->BorderColor ); } } diff --git a/src/mesa/drivers/dri/i810/i810tex.c b/src/mesa/drivers/dri/i810/i810tex.c index ba4e6b5b0b..cd6e1a8e6e 100644 --- a/src/mesa/drivers/dri/i810/i810tex.c +++ b/src/mesa/drivers/dri/i810/i810tex.c @@ -162,7 +162,7 @@ static void i810SetTexFilter(i810ContextPtr imesa, static void -i810SetTexBorderColor( i810TextureObjectPtr t, GLubyte color[4] ) +i810SetTexBorderColor( i810TextureObjectPtr t, const GLfloat color[4] ) { /* Need a fallback. */ @@ -211,7 +211,7 @@ i810AllocTexObj( GLcontext *ctx, struct gl_texture_object *texObj ) i810SetTexWrapping( t, texObj->WrapS, texObj->WrapT ); /*i830SetTexMaxAnisotropy( t, texObj->MaxAnisotropy );*/ i810SetTexFilter( imesa, t, texObj->MinFilter, texObj->MagFilter, bias ); - i810SetTexBorderColor( t, texObj->_BorderChan ); + i810SetTexBorderColor( t, texObj->BorderColor ); } return t; @@ -252,7 +252,7 @@ static void i810TexParameter( GLcontext *ctx, GLenum target, break; case GL_TEXTURE_BORDER_COLOR: - i810SetTexBorderColor( t, tObj->_BorderChan ); + i810SetTexBorderColor( t, tObj->BorderColor ); break; case GL_TEXTURE_BASE_LEVEL: diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c index df43b779a7..753c25b57e 100644 --- a/src/mesa/drivers/dri/i915/i830_texstate.c +++ b/src/mesa/drivers/dri/i915/i830_texstate.c @@ -122,6 +122,7 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) struct gl_texture_image *firstImage; GLuint *state = i830->state.Tex[unit], format, pitch; GLint lodbias; + GLubyte border[4]; memset(state, 0, sizeof(state)); @@ -294,11 +295,16 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) (ws))); } + /* convert border color from float to ubyte */ + CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->BorderColor[0]); + CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->BorderColor[1]); + CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->BorderColor[2]); + CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->BorderColor[3]); - state[I830_TEXREG_TM0S4] = INTEL_PACKCOLOR8888(tObj->_BorderChan[0], - tObj->_BorderChan[1], - tObj->_BorderChan[2], - tObj->_BorderChan[3]); + state[I830_TEXREG_TM0S4] = INTEL_PACKCOLOR8888(border[0], + border[1], + border[2], + border[3]); I830_ACTIVESTATE(i830, I830_UPLOAD_TEX(unit), GL_TRUE); diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index 6d25f8dd8e..43f65392b5 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -133,6 +133,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) struct gl_texture_image *firstImage; GLuint *state = i915->state.Tex[unit], format, pitch; GLint lodbias; + GLubyte border[4]; memset(state, 0, sizeof(state)); @@ -318,21 +319,26 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) state[I915_TEXREG_SS3] |= (unit << SS3_TEXTUREMAP_INDEX_SHIFT); } + /* convert border color from float to ubyte */ + CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->BorderColor[0]); + CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->BorderColor[1]); + CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->BorderColor[2]); + CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->BorderColor[3]); if (firstImage->_BaseFormat == GL_DEPTH_COMPONENT) { /* GL specs that border color for depth textures is taken from the * R channel, while the hardware uses A. Spam R into all the channels * for safety. */ - state[I915_TEXREG_SS4] = INTEL_PACKCOLOR8888(tObj->_BorderChan[0], - tObj->_BorderChan[0], - tObj->_BorderChan[0], - tObj->_BorderChan[0]); + state[I915_TEXREG_SS4] = INTEL_PACKCOLOR8888(border[0], + border[0], + border[0], + border[0]); } else { - state[I915_TEXREG_SS4] = INTEL_PACKCOLOR8888(tObj->_BorderChan[0], - tObj->_BorderChan[1], - tObj->_BorderChan[2], - tObj->_BorderChan[3]); + state[I915_TEXREG_SS4] = INTEL_PACKCOLOR8888(border[0], + border[1], + border[2], + border[3]); } diff --git a/src/mesa/drivers/dri/mach64/mach64_tex.c b/src/mesa/drivers/dri/mach64/mach64_tex.c index 9fe267eafd..225d23179e 100644 --- a/src/mesa/drivers/dri/mach64/mach64_tex.c +++ b/src/mesa/drivers/dri/mach64/mach64_tex.c @@ -99,7 +99,7 @@ static void mach64SetTexFilter( mach64TexObjPtr t, } } -static void mach64SetTexBorderColor( mach64TexObjPtr t, GLubyte c[4] ) +static void mach64SetTexBorderColor( mach64TexObjPtr t, const GLfloat c[4] ) { #if 0 GLuint border = mach64PackColor( 4, c[0], c[1], c[2], c[3] ); @@ -131,7 +131,7 @@ mach64AllocTexObj( struct gl_texture_object *texObj ) mach64SetTexWrap( t, texObj->WrapS, texObj->WrapT ); mach64SetTexFilter( t, texObj->MinFilter, texObj->MagFilter ); - mach64SetTexBorderColor( t, texObj->_BorderChan ); + mach64SetTexBorderColor( t, texObj->BorderColor ); return t; } @@ -471,7 +471,7 @@ static void mach64DDTexParameter( GLcontext *ctx, GLenum target, case GL_TEXTURE_BORDER_COLOR: if ( t->base.bound ) FLUSH_BATCH( mmesa ); - mach64SetTexBorderColor( t, tObj->_BorderChan ); + mach64SetTexBorderColor( t, tObj->BorderColor ); break; case GL_TEXTURE_BASE_LEVEL: diff --git a/src/mesa/drivers/dri/mga/mgatex.c b/src/mesa/drivers/dri/mga/mgatex.c index 2392622b90..33eb0be449 100644 --- a/src/mesa/drivers/dri/mga/mgatex.c +++ b/src/mesa/drivers/dri/mga/mgatex.c @@ -153,10 +153,14 @@ mgaSetTexFilter( mgaTextureObjectPtr t, GLenum minf, GLenum magf ) t->setup.texfilter |= val; } -static void mgaSetTexBorderColor(mgaTextureObjectPtr t, GLubyte color[4]) +static void mgaSetTexBorderColor(mgaTextureObjectPtr t, const GLfloat color[4]) { - t->setup.texbordercol = PACK_COLOR_8888(color[3], color[0], - color[1], color[2] ); + GLubyte c[4]; + CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]); + CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]); + CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]); + CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]); + t->setup.texbordercol = PACK_COLOR_8888(c[3], c[0], c[1], c[2] ); } @@ -329,7 +333,7 @@ mgaAllocTexObj( struct gl_texture_object *tObj ) mgaSetTexWrapping( t, tObj->WrapS, tObj->WrapT ); mgaSetTexFilter( t, tObj->MinFilter, tObj->MagFilter ); - mgaSetTexBorderColor( t, tObj->_BorderChan ); + mgaSetTexBorderColor( t, tObj->BorderColor ); } return( t ); @@ -458,7 +462,7 @@ mgaTexParameter( GLcontext *ctx, GLenum target, case GL_TEXTURE_BORDER_COLOR: FLUSH_BATCH(mmesa); - mgaSetTexBorderColor(t, tObj->_BorderChan); + mgaSetTexBorderColor(t, tObj->BorderColor); break; case GL_TEXTURE_BASE_LEVEL: diff --git a/src/mesa/drivers/dri/r128/r128_tex.c b/src/mesa/drivers/dri/r128/r128_tex.c index 3fc9c06cfa..0920270d7b 100644 --- a/src/mesa/drivers/dri/r128/r128_tex.c +++ b/src/mesa/drivers/dri/r128/r128_tex.c @@ -135,8 +135,13 @@ static void r128SetTexFilter( r128TexObjPtr t, GLenum minf, GLenum magf ) } } -static void r128SetTexBorderColor( r128TexObjPtr t, GLubyte c[4] ) +static void r128SetTexBorderColor( r128TexObjPtr t, const GLfloat color[4] ) { + GLubyte c[4]; + CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]); + CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]); + CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]); + CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]); t->setup.tex_border_color = r128PackColor( 4, c[0], c[1], c[2], c[3] ); } @@ -165,7 +170,7 @@ static r128TexObjPtr r128AllocTexObj( struct gl_texture_object *texObj ) r128SetTexWrap( t, texObj->WrapS, texObj->WrapT ); r128SetTexFilter( t, texObj->MinFilter, texObj->MagFilter ); - r128SetTexBorderColor( t, texObj->_BorderChan ); + r128SetTexBorderColor( t, texObj->BorderColor ); } return t; @@ -531,7 +536,7 @@ static void r128TexParameter( GLcontext *ctx, GLenum target, case GL_TEXTURE_BORDER_COLOR: if ( t->base.bound ) FLUSH_BATCH( rmesa ); - r128SetTexBorderColor( t, tObj->_BorderChan ); + r128SetTexBorderColor( t, tObj->BorderColor ); break; case GL_TEXTURE_BASE_LEVEL: diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c index 5a4db33f44..259f35a34c 100644 --- a/src/mesa/drivers/dri/r200/r200_tex.c +++ b/src/mesa/drivers/dri/r200/r200_tex.c @@ -267,8 +267,13 @@ static void r200SetTexFilter( r200TexObjPtr t, GLenum minf, GLenum magf ) } } -static void r200SetTexBorderColor( r200TexObjPtr t, GLubyte c[4] ) +static void r200SetTexBorderColor( r200TexObjPtr t, const GLfloat color[4] ) { + GLubyte c[4]; + CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]); + CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]); + CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]); + CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]); t->pp_border_color = r200PackColor( 4, c[0], c[1], c[2], c[3] ); } @@ -301,7 +306,7 @@ static r200TexObjPtr r200AllocTexObj( struct gl_texture_object *texObj ) r200SetTexWrap( t, texObj->WrapS, texObj->WrapT, texObj->WrapR ); r200SetTexMaxAnisotropy( t, texObj->MaxAnisotropy ); r200SetTexFilter( t, texObj->MinFilter, texObj->MagFilter ); - r200SetTexBorderColor( t, texObj->_BorderChan ); + r200SetTexBorderColor( t, texObj->BorderColor ); } return t; @@ -1056,7 +1061,7 @@ static void r200TexParameter( GLcontext *ctx, GLenum target, break; case GL_TEXTURE_BORDER_COLOR: - r200SetTexBorderColor( t, texObj->_BorderChan ); + r200SetTexBorderColor( t, texObj->BorderColor ); break; case GL_TEXTURE_BASE_LEVEL: diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c index 8ab382c83c..7c699ec572 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.c +++ b/src/mesa/drivers/dri/r300/r300_tex.c @@ -171,8 +171,13 @@ static void r300SetTexFilter(r300TexObjPtr t, GLenum minf, GLenum magf, GLfloat } } -static void r300SetTexBorderColor(r300TexObjPtr t, GLubyte c[4]) +static void r300SetTexBorderColor(r300TexObjPtr t, const GLfloat color[4]) { + GLubyte c[4]; + CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]); + CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]); + CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]); + CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]); t->pp_border_color = PACK_COLOR_8888(c[3], c[0], c[1], c[2]); } @@ -203,7 +208,7 @@ static r300TexObjPtr r300AllocTexObj(struct gl_texture_object *texObj) r300UpdateTexWrap(t); r300SetTexFilter(t, texObj->MinFilter, texObj->MagFilter, texObj->MaxAnisotropy); - r300SetTexBorderColor(t, texObj->_BorderChan); + r300SetTexBorderColor(t, texObj->BorderColor); } return t; @@ -929,7 +934,7 @@ static void r300TexParameter(GLcontext * ctx, GLenum target, break; case GL_TEXTURE_BORDER_COLOR: - r300SetTexBorderColor(t, texObj->_BorderChan); + r300SetTexBorderColor(t, texObj->BorderColor); break; case GL_TEXTURE_BASE_LEVEL: diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c index b0aec21670..f2b6deb9c0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.c +++ b/src/mesa/drivers/dri/radeon/radeon_tex.c @@ -239,8 +239,13 @@ static void radeonSetTexFilter( radeonTexObjPtr t, GLenum minf, GLenum magf ) } } -static void radeonSetTexBorderColor( radeonTexObjPtr t, GLubyte c[4] ) +static void radeonSetTexBorderColor( radeonTexObjPtr t, const GLfloat color[4] ) { + GLubyte c[4]; + CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]); + CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]); + CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]); + CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]); t->pp_border_color = radeonPackColor( 4, c[0], c[1], c[2], c[3] ); } @@ -276,7 +281,7 @@ static radeonTexObjPtr radeonAllocTexObj( struct gl_texture_object *texObj ) radeonSetTexWrap( t, texObj->WrapS, texObj->WrapT ); radeonSetTexMaxAnisotropy( t, texObj->MaxAnisotropy ); radeonSetTexFilter( t, texObj->MinFilter, texObj->MagFilter ); - radeonSetTexBorderColor( t, texObj->_BorderChan ); + radeonSetTexBorderColor( t, texObj->BorderColor ); } return t; @@ -755,7 +760,7 @@ static void radeonTexParameter( GLcontext *ctx, GLenum target, break; case GL_TEXTURE_BORDER_COLOR: - radeonSetTexBorderColor( t, texObj->_BorderChan ); + radeonSetTexBorderColor( t, texObj->BorderColor ); break; case GL_TEXTURE_BASE_LEVEL: diff --git a/src/mesa/drivers/dri/s3v/s3v_tex.c b/src/mesa/drivers/dri/s3v/s3v_tex.c index db66026363..9b92519862 100644 --- a/src/mesa/drivers/dri/s3v/s3v_tex.c +++ b/src/mesa/drivers/dri/s3v/s3v_tex.c @@ -132,8 +132,14 @@ static void s3vSetTexFilter(s3vContextPtr vmesa, static void s3vSetTexBorderColor(s3vContextPtr vmesa, s3vTextureObjectPtr t, - GLubyte color[4]) + const GLfloat color[4]) { + GLubyte c[4]; + CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]); + CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]); + CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]); + CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]); + #if TEX_DEBUG_ON static unsigned int times=0; DEBUG_TEX(("*** s3vSetTexBorderColor: #%i ***\n", ++times)); @@ -143,8 +149,7 @@ static void s3vSetTexBorderColor(s3vContextPtr vmesa, /* switch(t0 ... t->TextureColorMode) */ /* case TEX_COL_ARGB1555: */ - t->TextureBorderColor = - S3VIRGEPACKCOLOR555(color[0], color[1], color[2], color[3]); + t->TextureBorderColor = S3VIRGEPACKCOLOR555(c[0], c[1], c[2], c[3]); DEBUG(("TextureBorderColor = 0x%x\n", t->TextureBorderColor)); @@ -182,7 +187,7 @@ static void s3vTexParameter( GLcontext *ctx, GLenum target, break; case GL_TEXTURE_BORDER_COLOR: - s3vSetTexBorderColor( vmesa, t, tObj->_BorderChan ); + s3vSetTexBorderColor( vmesa, t, tObj->BorderColor ); break; case GL_TEXTURE_BASE_LEVEL: diff --git a/src/mesa/drivers/dri/savage/savagetex.c b/src/mesa/drivers/dri/savage/savagetex.c index a3bebfa8cf..fe239e1b05 100644 --- a/src/mesa/drivers/dri/savage/savagetex.c +++ b/src/mesa/drivers/dri/savage/savagetex.c @@ -474,7 +474,7 @@ static void savageSetTexFilter(savageTexObjPtr t, GLenum minf, GLenum magf) /* Need a fallback ? */ -static void savageSetTexBorderColor(savageTexObjPtr t, GLubyte color[4]) +static void savageSetTexBorderColor(savageTexObjPtr t, const GLfloat color[4]) { /* t->Setup[SAVAGE_TEXREG_TEXBORDERCOL] = */ /*t->setup.borderColor = SAVAGEPACKCOLOR8888(color[0],color[1],color[2],color[3]); */ @@ -512,7 +512,7 @@ savageAllocTexObj( struct gl_texture_object *texObj ) savageSetTexWrapping(t,texObj->WrapS,texObj->WrapT); savageSetTexFilter(t,texObj->MinFilter,texObj->MagFilter); - savageSetTexBorderColor(t,texObj->_BorderChan); + savageSetTexBorderColor(t,texObj->BorderColor); } return t; @@ -2018,7 +2018,7 @@ static void savageTexParameter( GLcontext *ctx, GLenum target, break; case GL_TEXTURE_BORDER_COLOR: - savageSetTexBorderColor(t,tObj->_BorderChan); + savageSetTexBorderColor(t,tObj->BorderColor); break; default: diff --git a/src/mesa/drivers/dri/sis/sis_texstate.c b/src/mesa/drivers/dri/sis/sis_texstate.c index 63f23fc014..46417ce414 100644 --- a/src/mesa/drivers/dri/sis/sis_texstate.c +++ b/src/mesa/drivers/dri/sis/sis_texstate.c @@ -456,11 +456,16 @@ sis_set_texobj_parm( GLcontext *ctx, struct gl_texture_object *texObj, break; } - current->texture[hw_unit].hwTextureBorderColor = - ((GLuint) texObj->_BorderChan[3] << 24) + - ((GLuint) texObj->_BorderChan[0] << 16) + - ((GLuint) texObj->_BorderChan[1] << 8) + - ((GLuint) texObj->_BorderChan[2]); + { + GLubyte c[4]; + CLAMPED_FLOAT_TO_UBYTE(c[0], texObj->BorderColor[0]); + CLAMPED_FLOAT_TO_UBYTE(c[1], texObj->BorderColor[1]); + CLAMPED_FLOAT_TO_UBYTE(c[2], texObj->BorderColor[2]); + CLAMPED_FLOAT_TO_UBYTE(c[3], texObj->BorderColor[3]); + + current->texture[hw_unit].hwTextureBorderColor = + PACK_COLOR_8888(c[3], c[0], c[1], c[2]); + } if (current->texture[hw_unit].hwTextureBorderColor != prev->texture[hw_unit].hwTextureBorderColor) -- cgit v1.2.3 From c952b3e907ab31cd5f95157c18ce2f81626aafe4 Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Thu, 2 Apr 2009 10:30:30 +0200 Subject: dri glx: Propagate driver MakeCurrent errors. Signed-off-by: Thomas Hellstrom --- src/mesa/drivers/dri/common/dri_util.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/common/dri_util.c b/src/mesa/drivers/dri/common/dri_util.c index ae79055405..a9e37ca51e 100644 --- a/src/mesa/drivers/dri/common/dri_util.c +++ b/src/mesa/drivers/dri/common/dri_util.c @@ -200,9 +200,8 @@ static int driBindContext(__DRIcontext *pcp, } /* Call device-specific MakeCurrent */ - (*psp->DriverAPI.MakeCurrent)(pcp, pdp, prp); - return GL_TRUE; + return (*psp->DriverAPI.MakeCurrent)(pcp, pdp, prp); } /*@}*/ -- cgit v1.2.3 From 8e753d04045a82062ac34d3b2622eb9dba8af374 Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Thu, 2 Apr 2009 10:36:40 +0200 Subject: dri glx: Fix dri_util::driBindContext 1) Don't error-check here. It's done in glx makeCurrent. 2) Allow ctx and the dri drawables to be NULL for future use. This is currently blocked in glx makeCurrent. 3) Avoid updating dri drawables unless they are completely uninitialized. Since the updating was done outside of the lock, the driver need to verify and redo it anyway. Signed-off-by: Thomas Hellstrom --- src/mesa/drivers/dri/common/dri_util.c | 32 ++++++++++++++------------------ 1 file changed, 14 insertions(+), 18 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/common/dri_util.c b/src/mesa/drivers/dri/common/dri_util.c index a9e37ca51e..38c2e7b00d 100644 --- a/src/mesa/drivers/dri/common/dri_util.c +++ b/src/mesa/drivers/dri/common/dri_util.c @@ -163,21 +163,18 @@ static int driBindContext(__DRIcontext *pcp, { __DRIscreenPrivate *psp = pcp->driScreenPriv; - /* - ** Assume error checking is done properly in glXMakeCurrent before - ** calling driBindContext. - */ - - if (pcp == NULL || pdp == None || prp == None) - return GL_FALSE; - /* Bind the drawable to the context */ - pcp->driDrawablePriv = pdp; - pcp->driReadablePriv = prp; - pdp->driContextPriv = pcp; - pdp->refcount++; - if ( pdp != prp ) { - prp->refcount++; + + if (pcp) { + pcp->driDrawablePriv = pdp; + pcp->driReadablePriv = prp; + if (pdp) { + pdp->driContextPriv = pcp; + pdp->refcount++; + } + if ( prp && pdp != prp ) { + prp->refcount++; + } } /* @@ -186,17 +183,16 @@ static int driBindContext(__DRIcontext *pcp, */ if (!psp->dri2.enabled) { - if (!pdp->pStamp || *pdp->pStamp != pdp->lastStamp) { + if (pdp && !pdp->pStamp) { DRM_SPINLOCK(&psp->pSAREA->drawable_lock, psp->drawLockID); __driUtilUpdateDrawableInfo(pdp); DRM_SPINUNLOCK(&psp->pSAREA->drawable_lock, psp->drawLockID); } - - if ((pdp != prp) && (!prp->pStamp || *prp->pStamp != prp->lastStamp)) { + if (prp && pdp != prp && !prp->pStamp) { DRM_SPINLOCK(&psp->pSAREA->drawable_lock, psp->drawLockID); __driUtilUpdateDrawableInfo(prp); DRM_SPINUNLOCK(&psp->pSAREA->drawable_lock, psp->drawLockID); - } + } } /* Call device-specific MakeCurrent */ -- cgit v1.2.3 From 9f146943ec3893c9aed1754a59eec45f37ca65cd Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Mon, 23 Mar 2009 09:56:33 -0600 Subject: i965: whitespace changes, comments --- src/mesa/drivers/dri/i965/brw_vs_emit.c | 37 +++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 13 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 3807dff991..ad7431a19b 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -60,7 +60,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c ) /* Deal with curbe alignment: */ - reg += ((6+c->key.nr_userclip+3)/4)*2; + reg += ((6+c->key.nr_userclip + 3) / 4) * 2; } /* Vertex program parameters from curbe: @@ -77,7 +77,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c ) */ c->nr_inputs = 0; for (i = 0; i < VERT_ATTRIB_MAX; i++) { - if (c->prog_data.inputs_read & (1<prog_data.inputs_read & (1 << i)) { c->nr_inputs++; c->regs[PROGRAM_INPUT][i] = brw_vec8_grf(reg, 0); reg++; @@ -91,7 +91,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c ) c->first_output = reg; mrf = 4; for (i = 0; i < VERT_RESULT_MAX; i++) { - if (c->prog_data.outputs_written & (1<prog_data.outputs_written & (1 << i)) { c->nr_outputs++; if (i == VERT_RESULT_HPOS) { c->regs[PROGRAM_OUTPUT][i] = brw_vec8_grf(reg, 0); @@ -133,16 +133,15 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c ) } for (i = 0; i < 128; i++) { - if (c->output_regs[i].used_in_src) { - c->output_regs[i].reg = brw_vec8_grf(reg, 0); - reg++; - } + if (c->output_regs[i].used_in_src) { + c->output_regs[i].reg = brw_vec8_grf(reg, 0); + reg++; + } } c->stack = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, reg, 0); reg += 2; - - + /* Some opcodes need an internal temporary: */ c->first_tmp = reg; @@ -152,9 +151,9 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c ) * urb_read_length is the number of registers read from *each* * vertex urb, so is half the amount: */ - c->prog_data.urb_read_length = (c->nr_inputs+1)/2; + c->prog_data.urb_read_length = (c->nr_inputs + 1) / 2; - c->prog_data.urb_entry_size = (c->nr_outputs+2+3)/4; + c->prog_data.urb_entry_size = (c->nr_outputs + 2 + 3) / 4; c->prog_data.total_grf = reg; if (INTEL_DEBUG & DEBUG_VS) { @@ -187,6 +186,10 @@ static void release_tmps( struct brw_vs_compile *c ) } +/** + * If an instruction uses a temp reg both as a src and the dest, we + * sometimes need to allocate an intermediate temporary. + */ static void unalias1( struct brw_vs_compile *c, struct brw_reg dst, struct brw_reg arg0, @@ -206,6 +209,10 @@ static void unalias1( struct brw_vs_compile *c, } } +/** + * \sa unalias2 + * Checkes if 2-operand instruction needs an intermediate temporary. + */ static void unalias2( struct brw_vs_compile *c, struct brw_reg dst, struct brw_reg arg0, @@ -228,6 +235,10 @@ static void unalias2( struct brw_vs_compile *c, } } +/** + * \sa unalias2 + * Checkes if 3-operand instruction needs an intermediate temporary. + */ static void unalias3( struct brw_vs_compile *c, struct brw_reg dst, struct brw_reg arg0, @@ -981,7 +992,7 @@ post_vs_emit( struct brw_vs_compile *c, } -/* Emit the fragment program instructions here. +/* Emit the vertex program instructions here. */ void brw_vs_emit(struct brw_vs_compile *c ) { @@ -1038,7 +1049,7 @@ void brw_vs_emit(struct brw_vs_compile *c ) struct prog_src_register *src = &inst->SrcReg[i]; index = src->Index; file = src->File; - if (file == PROGRAM_OUTPUT&&c->output_regs[index].used_in_src) + if (file == PROGRAM_OUTPUT && c->output_regs[index].used_in_src) args[i] = c->output_regs[index].reg; else args[i] = get_arg(c, src); -- cgit v1.2.3 From bf28b576cb6aa403b840d8254a1ff3f31d664b46 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Mon, 23 Mar 2009 14:40:51 -0600 Subject: i965: fix indentation --- src/mesa/drivers/dri/i965/brw_wm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index 03dc08fcca..98c22121ec 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -242,8 +242,8 @@ struct brw_wm_compile { /** Mapping from Mesa registers to hardware registers */ struct { - GLboolean inited; - struct brw_reg reg; + GLboolean inited; + struct brw_reg reg; } wm_regs[PROGRAM_PAYLOAD+1][256][4]; struct brw_reg stack; -- cgit v1.2.3 From c82851598f535f5c92885987cafbb5e79a2505db Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Mon, 23 Mar 2009 14:43:51 -0600 Subject: i965: rename scratch_buffer -> scratch_bo to be consistant with other buffers --- src/mesa/drivers/dri/i965/brw_context.h | 2 +- src/mesa/drivers/dri/i965/brw_wm_state.c | 22 +++++++++++----------- 2 files changed, 12 insertions(+), 12 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 48ed4325be..a020b621d6 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -588,7 +588,7 @@ struct brw_context GLuint nr_surfaces; GLuint max_threads; - dri_bo *scratch_buffer; + dri_bo *scratch_bo; GLuint sampler_count; dri_bo *sampler_bo; diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c index 5b14074502..3ef451405c 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c @@ -142,7 +142,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key, if (key->total_scratch != 0) { wm.thread2.scratch_space_base_pointer = - brw->wm.scratch_buffer->offset >> 10; /* reloc */ + brw->wm.scratch_bo->offset >> 10; /* reloc */ wm.thread2.per_thread_scratch_space = key->total_scratch / 1024 - 1; } else { wm.thread2.scratch_space_base_pointer = 0; @@ -220,7 +220,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key, 0, 0, wm.thread2.per_thread_scratch_space, offsetof(struct brw_wm_unit_state, thread2), - brw->wm.scratch_buffer); + brw->wm.scratch_bo); } /* Emit sampler state relocation */ @@ -251,20 +251,20 @@ static void upload_wm_unit( struct brw_context *brw ) if (key.total_scratch) { GLuint total = key.total_scratch * key.max_threads; - if (brw->wm.scratch_buffer && total > brw->wm.scratch_buffer->size) { - dri_bo_unreference(brw->wm.scratch_buffer); - brw->wm.scratch_buffer = NULL; + if (brw->wm.scratch_bo && total > brw->wm.scratch_bo->size) { + dri_bo_unreference(brw->wm.scratch_bo); + brw->wm.scratch_bo = NULL; } - if (brw->wm.scratch_buffer == NULL) { - brw->wm.scratch_buffer = dri_bo_alloc(intel->bufmgr, - "wm scratch", - total, - 4096); + if (brw->wm.scratch_bo == NULL) { + brw->wm.scratch_bo = dri_bo_alloc(intel->bufmgr, + "wm scratch", + total, + 4096); } } reloc_bufs[0] = brw->wm.prog_bo; - reloc_bufs[1] = brw->wm.scratch_buffer; + reloc_bufs[1] = brw->wm.scratch_bo; reloc_bufs[2] = brw->wm.sampler_bo; dri_bo_unreference(brw->wm.state_bo); -- cgit v1.2.3 From 499972102271a08ba41bc34f95e2013311ef8de5 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 24 Mar 2009 09:42:09 -0600 Subject: i965: comments, whitespace changes --- src/mesa/drivers/dri/i965/brw_wm_emit.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index 4372ed3d9a..d65b1332c6 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -1024,8 +1024,8 @@ static void emit_fb_write( struct brw_wm_compile *c, } -/* Post-fragment-program processing. Send the results to the - * framebuffer. +/** + * Move a GPR to scratch memory. */ static void emit_spill( struct brw_wm_compile *c, struct brw_reg reg, @@ -1049,6 +1049,9 @@ static void emit_spill( struct brw_wm_compile *c, } +/** + * Load a GPR from scratch memory. + */ static void emit_unspill( struct brw_wm_compile *c, struct brw_reg reg, GLuint slot ) @@ -1069,13 +1072,14 @@ static void emit_unspill( struct brw_wm_compile *c, brw_dp_READ_16(p, retype(vec16(reg), BRW_REGISTER_TYPE_UW), - 1, + 1, slot); } /** - * Retrieve upto 4 GEN4 register pairs for the given wm reg: + * Retrieve up to 4 GEN4 register pairs for the given wm reg: + * Args with unspill_reg != 0 will be loaded from scratch memory. */ static void get_argument_regs( struct brw_wm_compile *c, struct brw_wm_ref *arg[], @@ -1085,13 +1089,12 @@ static void get_argument_regs( struct brw_wm_compile *c, for (i = 0; i < 4; i++) { if (arg[i]) { - - if (arg[i]->unspill_reg) - emit_unspill(c, + if (arg[i]->unspill_reg) + emit_unspill(c, brw_vec8_grf(arg[i]->unspill_reg, 0), arg[i]->value->spill_slot); - regs[i] = arg[i]->hw_reg; + regs[i] = arg[i]->hw_reg; } else { regs[i] = brw_null_reg(); @@ -1100,6 +1103,9 @@ static void get_argument_regs( struct brw_wm_compile *c, } +/** + * For values that have a spill_slot!=0, write those regs to scratch memory. + */ static void spill_values( struct brw_wm_compile *c, struct brw_wm_value *values, GLuint nr ) -- cgit v1.2.3 From 7709b26e6b615f4e5ace765110eb53ce713b0d6c Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 24 Mar 2009 09:44:10 -0600 Subject: i965: formatting clean-ups --- src/mesa/drivers/dri/i965/brw_vs_emit.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index ad7431a19b..0d6c6ab9a8 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -49,7 +49,8 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c ) /* r0 -- reserved as usual */ - c->r0 = brw_vec8_grf(reg, 0); reg++; + c->r0 = brw_vec8_grf(reg, 0); + reg++; /* User clip planes from curbe: */ @@ -60,7 +61,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c ) /* Deal with curbe alignment: */ - reg += ((6+c->key.nr_userclip + 3) / 4) * 2; + reg += ((6 + c->key.nr_userclip + 3) / 4) * 2; } /* Vertex program parameters from curbe: @@ -69,7 +70,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c ) for (i = 0; i < nr_params; i++) { c->regs[PROGRAM_STATE_VAR][i] = stride( brw_vec4_grf(reg+i/2, (i%2) * 4), 0, 4, 1); } - reg += (nr_params+1)/2; + reg += (nr_params + 1) / 2; c->prog_data.curb_read_length = reg - 1; -- cgit v1.2.3 From 5d7f3ae15c62d46e8857c159978c1c75e07cc59b Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 24 Mar 2009 09:54:48 -0600 Subject: i965: remove unneeded #includes --- src/mesa/drivers/dri/i965/brw_tex.c | 9 --------- 1 file changed, 9 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_tex.c b/src/mesa/drivers/dri/i965/brw_tex.c index ef99e9c1ae..71bff166dd 100644 --- a/src/mesa/drivers/dri/i965/brw_tex.c +++ b/src/mesa/drivers/dri/i965/brw_tex.c @@ -32,21 +32,12 @@ #include "main/glheader.h" #include "main/mtypes.h" -#include "main/imports.h" -#include "main/simple_list.h" -#include "main/enums.h" -#include "main/image.h" #include "main/teximage.h" -#include "main/texstore.h" -#include "main/texformat.h" - -#include "texmem.h" #include "intel_context.h" #include "intel_regions.h" #include "intel_tex.h" #include "brw_context.h" -#include "brw_defines.h" void brw_FrameBufferTexInit( struct brw_context *brw, -- cgit v1.2.3 From d5346a925c569d959eb9ebedda95fdddb9d5350c Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 24 Mar 2009 10:35:40 -0600 Subject: i965: comments, clean-up in prepare_wm_surfaces() --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 26 ++++++++++++++---------- 1 file changed, 15 insertions(+), 11 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 2f1f4c55f9..1fc537ca20 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -477,7 +477,8 @@ static void prepare_wm_surfaces(struct brw_context *brw ) GLuint i; int old_nr_surfaces; - if (brw->state.nr_color_regions > 1) { + /* Update surfaces for drawing buffers */ + if (brw->state.nr_color_regions > 1) { for (i = 0; i < brw->state.nr_color_regions; i++) { brw_update_region_surface(brw, brw->state.color_regions[i], i, GL_FALSE); @@ -489,25 +490,28 @@ static void prepare_wm_surfaces(struct brw_context *brw ) old_nr_surfaces = brw->wm.nr_surfaces; brw->wm.nr_surfaces = MAX_DRAW_BUFFERS; + /* Update surfaces for textures */ for (i = 0; i < BRW_MAX_TEX_UNIT; i++) { - struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i]; + const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i]; + const GLuint j = MAX_DRAW_BUFFERS + i; /* _NEW_TEXTURE, BRW_NEW_TEXDATA */ - if(texUnit->_ReallyEnabled) { + if (texUnit->_ReallyEnabled) { if (texUnit->_Current == intel->frame_buffer_texobj) { - dri_bo_unreference(brw->wm.surf_bo[i+MAX_DRAW_BUFFERS]); - brw->wm.surf_bo[i+MAX_DRAW_BUFFERS] = brw->wm.surf_bo[0]; - dri_bo_reference(brw->wm.surf_bo[i+MAX_DRAW_BUFFERS]); - brw->wm.nr_surfaces = i + MAX_DRAW_BUFFERS + 1; + /* render to texture */ + dri_bo_unreference(brw->wm.surf_bo[j]); + brw->wm.surf_bo[j] = brw->wm.surf_bo[0]; + dri_bo_reference(brw->wm.surf_bo[j]); + brw->wm.nr_surfaces = j + 1; } else { + /* regular texture */ brw_update_texture_surface(ctx, i); - brw->wm.nr_surfaces = i + MAX_DRAW_BUFFERS + 1; + brw->wm.nr_surfaces = j + 1; } } else { - dri_bo_unreference(brw->wm.surf_bo[i+MAX_DRAW_BUFFERS]); - brw->wm.surf_bo[i+MAX_DRAW_BUFFERS] = NULL; + dri_bo_unreference(brw->wm.surf_bo[j]); + brw->wm.surf_bo[j] = NULL; } - } dri_bo_unreference(brw->wm.bind_bo); -- cgit v1.2.3 From f1b9a5cff15abf89c24a0c54481451cb8d23f454 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 24 Mar 2009 14:48:53 -0600 Subject: i965: fix comment typo --- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index b3c15fe87f..350760a1ef 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -2293,7 +2293,7 @@ static void emit_wpos_xy(struct brw_wm_compile *c, } /* TODO - BIAS on SIMD8 not workind yet... + BIAS on SIMD8 not working yet... */ static void emit_txb(struct brw_wm_compile *c, struct prog_instruction *inst) -- cgit v1.2.3 From 966cd4f1af54e560672e7d7614251271fbbb379b Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 24 Mar 2009 16:33:48 -0600 Subject: i965: remove 'nr' param from get_src/dst_reg() functions The value was always 1. --- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 226 ++++++++++++++++---------------- 1 file changed, 114 insertions(+), 112 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 350760a1ef..ffde59e143 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -241,8 +241,9 @@ static void prealloc_reg(struct brw_wm_compile *c) * Convert Mesa dst register to brw register. */ static struct brw_reg get_dst_reg(struct brw_wm_compile *c, - struct prog_instruction *inst, int component, int nr) + struct prog_instruction *inst, int component) { + const int nr = 1; return get_reg(c, inst->DstReg.File, inst->DstReg.Index, component, nr, 0, 0); } @@ -252,8 +253,9 @@ static struct brw_reg get_dst_reg(struct brw_wm_compile *c, * Convert Mesa src register to brw register. */ static struct brw_reg get_src_reg(struct brw_wm_compile *c, - struct prog_src_register *src, int index, int nr) + struct prog_src_register *src, int index) { + const int nr = 1; int component = GET_SWZ(src->Swizzle, index); return get_reg(c, src->File, src->Index, component, nr, src->NegateBase, src->Abs); @@ -332,8 +334,8 @@ static void emit_abs( struct brw_wm_compile *c, for (i = 0; i < 4; i++) { if (inst->DstReg.WriteMask & (1<SrcReg[0], i, 1); + dst = get_dst_reg(c, inst, i); + src = get_src_reg(c, &inst->SrcReg[0], i); brw_MOV(p, dst, brw_abs(src)); } } @@ -350,8 +352,8 @@ static void emit_trunc( struct brw_wm_compile *c, for (i = 0; i < 4; i++) { if (mask & (1<SrcReg[0], i, 1); + dst = get_dst_reg(c, inst, i); + src = get_src_reg(c, &inst->SrcReg[0], i); brw_RNDZ(p, dst, src); } } @@ -368,8 +370,8 @@ static void emit_mov( struct brw_wm_compile *c, for (i = 0; i < 4; i++) { if (mask & (1<SrcReg[0], i, 1); + dst = get_dst_reg(c, inst, i); + src = get_src_reg(c, &inst->SrcReg[0], i); brw_MOV(p, dst, src); } } @@ -386,8 +388,8 @@ static void emit_pixel_xy(struct brw_wm_compile *c, struct brw_compile *p = &c->func; GLuint mask = inst->DstReg.WriteMask; - dst0 = get_dst_reg(c, inst, 0, 1); - dst1 = get_dst_reg(c, inst, 1, 1); + dst0 = get_dst_reg(c, inst, 0); + dst1 = get_dst_reg(c, inst, 1); /* Calculate pixel centers by adding 1 or 0 to each of the * micro-tile coordinates passed in r1. */ @@ -414,10 +416,10 @@ static void emit_delta_xy(struct brw_wm_compile *c, struct brw_compile *p = &c->func; GLuint mask = inst->DstReg.WriteMask; - dst0 = get_dst_reg(c, inst, 0, 1); - dst1 = get_dst_reg(c, inst, 1, 1); - src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1); - src1 = get_src_reg(c, &inst->SrcReg[0], 1, 1); + dst0 = get_dst_reg(c, inst, 0); + dst1 = get_dst_reg(c, inst, 1); + src0 = get_src_reg(c, &inst->SrcReg[0], 0); + src1 = get_src_reg(c, &inst->SrcReg[0], 1); /* Calc delta X,Y by subtracting origin in r1 from the pixel * centers. */ @@ -482,7 +484,7 @@ static void emit_fb_write(struct brw_wm_compile *c, brw_push_insn_state(p); for (channel = 0; channel < 4; channel++) { - src0 = get_src_reg(c, &inst->SrcReg[0], channel, 1); + src0 = get_src_reg(c, &inst->SrcReg[0], channel); /* mov (8) m2.0<1>:ud r28.0<8;8,1>:ud { Align1 } */ /* mov (8) m6.0<1>:ud r29.0<8;8,1>:ud { Align1 SecHalf } */ brw_MOV(p, brw_message_reg(nr + channel), src0); @@ -493,11 +495,11 @@ static void emit_fb_write(struct brw_wm_compile *c, if (c->key.source_depth_to_render_target) { if (c->key.computes_depth) { - src0 = get_src_reg(c, &inst->SrcReg[2], 2, 1); + src0 = get_src_reg(c, &inst->SrcReg[2], 2); brw_MOV(p, brw_message_reg(nr), src0); } else { - src0 = get_src_reg(c, &inst->SrcReg[1], 1, 1); + src0 = get_src_reg(c, &inst->SrcReg[1], 1); brw_MOV(p, brw_message_reg(nr), src0); } @@ -524,7 +526,7 @@ static void emit_fb_write(struct brw_wm_compile *c, else #endif { - struct brw_reg src = get_src_reg(c, &inst->SrcReg[1], 1, 1); + struct brw_reg src = get_src_reg(c, &inst->SrcReg[1], 1); brw_MOV(p, brw_message_reg(nr), src); } nr += 2; @@ -544,10 +546,10 @@ static void emit_pixel_w( struct brw_wm_compile *c, struct brw_reg dst, src0, delta0, delta1; struct brw_reg interp3; - dst = get_dst_reg(c, inst, 3, 1); - src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1); - delta0 = get_src_reg(c, &inst->SrcReg[1], 0, 1); - delta1 = get_src_reg(c, &inst->SrcReg[1], 1, 1); + dst = get_dst_reg(c, inst, 3); + src0 = get_src_reg(c, &inst->SrcReg[0], 0); + delta0 = get_src_reg(c, &inst->SrcReg[1], 0); + delta1 = get_src_reg(c, &inst->SrcReg[1], 1); interp3 = brw_vec1_grf(src0.nr+1, 4); /* Calc 1/w - just linterp wpos[3] optimized by putting the @@ -575,9 +577,9 @@ static void emit_linterp(struct brw_wm_compile *c, struct brw_reg src0; GLuint nr, i; - src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1); - delta0 = get_src_reg(c, &inst->SrcReg[1], 0, 1); - delta1 = get_src_reg(c, &inst->SrcReg[1], 1, 1); + src0 = get_src_reg(c, &inst->SrcReg[0], 0); + delta0 = get_src_reg(c, &inst->SrcReg[1], 0); + delta1 = get_src_reg(c, &inst->SrcReg[1], 1); nr = src0.nr; interp[0] = brw_vec1_grf(nr, 0); @@ -587,7 +589,7 @@ static void emit_linterp(struct brw_wm_compile *c, for(i = 0; i < 4; i++ ) { if (mask & (1<SrcReg[0], 0, 1); + src0 = get_src_reg(c, &inst->SrcReg[0], 0); nr = src0.nr; interp[0] = brw_vec1_grf(nr, 0); @@ -614,7 +616,7 @@ static void emit_cinterp(struct brw_wm_compile *c, for(i = 0; i < 4; i++ ) { if (mask & (1<SrcReg[0], 0, 1); - delta0 = get_src_reg(c, &inst->SrcReg[1], 0, 1); - delta1 = get_src_reg(c, &inst->SrcReg[1], 1, 1); - w = get_src_reg(c, &inst->SrcReg[2], 3, 1); + src0 = get_src_reg(c, &inst->SrcReg[0], 0); + delta0 = get_src_reg(c, &inst->SrcReg[1], 0); + delta1 = get_src_reg(c, &inst->SrcReg[1], 1); + w = get_src_reg(c, &inst->SrcReg[2], 3); nr = src0.nr; interp[0] = brw_vec1_grf(nr, 0); @@ -644,7 +646,7 @@ static void emit_pinterp(struct brw_wm_compile *c, for(i = 0; i < 4; i++ ) { if (mask & (1<SrcReg[0], i2, 1)); - src1 = get_src_reg(c, &inst->SrcReg[1], i1, 1); + dst = get_dst_reg(c, inst, i); + src0 = negate(get_src_reg(c, &inst->SrcReg[0], i2)); + src1 = get_src_reg(c, &inst->SrcReg[1], i1); brw_MUL(p, brw_null_reg(), src0, src1); - src0 = get_src_reg(c, &inst->SrcReg[0], i1, 1); - src1 = get_src_reg(c, &inst->SrcReg[1], i2, 1); + src0 = get_src_reg(c, &inst->SrcReg[0], i1); + src1 = get_src_reg(c, &inst->SrcReg[1], i2); brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF); brw_MAC(p, dst, src0, src1); brw_set_saturate(p, 0); @@ -715,11 +717,11 @@ static void emit_dp3(struct brw_wm_compile *c, int i; struct brw_compile *p = &c->func; for (i = 0; i < 3; i++) { - src0[i] = get_src_reg(c, &inst->SrcReg[0], i, 1); - src1[i] = get_src_reg(c, &inst->SrcReg[1], i, 1); + src0[i] = get_src_reg(c, &inst->SrcReg[0], i); + src1[i] = get_src_reg(c, &inst->SrcReg[1], i); } - dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1); + dst = get_dst_reg(c, inst, get_scalar_dst_index(inst)); brw_MUL(p, brw_null_reg(), src0[0], src1[0]); brw_MAC(p, brw_null_reg(), src0[1], src1[1]); brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); @@ -734,10 +736,10 @@ static void emit_dp4(struct brw_wm_compile *c, int i; struct brw_compile *p = &c->func; for (i = 0; i < 4; i++) { - src0[i] = get_src_reg(c, &inst->SrcReg[0], i, 1); - src1[i] = get_src_reg(c, &inst->SrcReg[1], i, 1); + src0[i] = get_src_reg(c, &inst->SrcReg[0], i); + src1[i] = get_src_reg(c, &inst->SrcReg[1], i); } - dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1); + dst = get_dst_reg(c, inst, get_scalar_dst_index(inst)); brw_MUL(p, brw_null_reg(), src0[0], src1[0]); brw_MAC(p, brw_null_reg(), src0[1], src1[1]); brw_MAC(p, brw_null_reg(), src0[2], src1[2]); @@ -753,10 +755,10 @@ static void emit_dph(struct brw_wm_compile *c, int i; struct brw_compile *p = &c->func; for (i = 0; i < 4; i++) { - src0[i] = get_src_reg(c, &inst->SrcReg[0], i, 1); - src1[i] = get_src_reg(c, &inst->SrcReg[1], i, 1); + src0[i] = get_src_reg(c, &inst->SrcReg[0], i); + src1[i] = get_src_reg(c, &inst->SrcReg[1], i); } - dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1); + dst = get_dst_reg(c, inst, get_scalar_dst_index(inst)); brw_MUL(p, brw_null_reg(), src0[0], src1[0]); brw_MAC(p, brw_null_reg(), src0[1], src1[1]); brw_MAC(p, dst, src0[2], src1[2]); @@ -781,7 +783,7 @@ static void emit_math1(struct brw_wm_compile *c, tmp = alloc_tmp(c); /* Get first component of source register */ - src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1); + src0 = get_src_reg(c, &inst->SrcReg[0], 0); /* tmp = func(src0) */ brw_MOV(p, brw_message_reg(2), src0); @@ -799,7 +801,7 @@ static void emit_math1(struct brw_wm_compile *c, /* replicate tmp value across enabled dest channels */ for (i = 0; i < 4; i++) { if (inst->DstReg.WriteMask & (1 << i)) { - dst = get_dst_reg(c, inst, i, 1); + dst = get_dst_reg(c, inst, i); brw_MOV(p, dst, tmp); } } @@ -853,9 +855,9 @@ static void emit_add(struct brw_wm_compile *c, brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); for (i = 0 ; i < 4; i++) { if (mask & (1<SrcReg[0], i, 1); - src1 = get_src_reg(c, &inst->SrcReg[1], i, 1); + dst = get_dst_reg(c, inst, i); + src0 = get_src_reg(c, &inst->SrcReg[0], i); + src1 = get_src_reg(c, &inst->SrcReg[1], i); brw_ADD(p, dst, src0, src1); } } @@ -872,9 +874,9 @@ static void emit_sub(struct brw_wm_compile *c, brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); for (i = 0 ; i < 4; i++) { if (mask & (1<SrcReg[0], i, 1); - src1 = get_src_reg(c, &inst->SrcReg[1], i, 1); + dst = get_dst_reg(c, inst, i); + src0 = get_src_reg(c, &inst->SrcReg[0], i); + src1 = get_src_reg(c, &inst->SrcReg[1], i); brw_ADD(p, dst, src0, negate(src1)); } } @@ -891,9 +893,9 @@ static void emit_mul(struct brw_wm_compile *c, brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); for (i = 0 ; i < 4; i++) { if (mask & (1<SrcReg[0], i, 1); - src1 = get_src_reg(c, &inst->SrcReg[1], i, 1); + dst = get_dst_reg(c, inst, i); + src0 = get_src_reg(c, &inst->SrcReg[0], i); + src1 = get_src_reg(c, &inst->SrcReg[1], i); brw_MUL(p, dst, src0, src1); } } @@ -910,8 +912,8 @@ static void emit_frc(struct brw_wm_compile *c, brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); for (i = 0 ; i < 4; i++) { if (mask & (1<SrcReg[0], i, 1); + dst = get_dst_reg(c, inst, i); + src0 = get_src_reg(c, &inst->SrcReg[0], i); brw_FRC(p, dst, src0); } } @@ -929,8 +931,8 @@ static void emit_flr(struct brw_wm_compile *c, brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); for (i = 0 ; i < 4; i++) { if (mask & (1<SrcReg[0], i, 1); + dst = get_dst_reg(c, inst, i); + src0 = get_src_reg(c, &inst->SrcReg[0], i); brw_RNDD(p, dst, src0); } } @@ -947,9 +949,9 @@ static void emit_max(struct brw_wm_compile *c, brw_push_insn_state(p); for (i = 0; i < 4; i++) { if (mask & (1<SrcReg[0], i, 1); - src1 = get_src_reg(c, &inst->SrcReg[1], i, 1); + dst = get_dst_reg(c, inst, i); + src0 = get_src_reg(c, &inst->SrcReg[0], i); + src1 = get_src_reg(c, &inst->SrcReg[1], i); brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); brw_MOV(p, dst, src0); brw_set_saturate(p, 0); @@ -975,9 +977,9 @@ static void emit_min(struct brw_wm_compile *c, brw_push_insn_state(p); for (i = 0; i < 4; i++) { if (mask & (1<SrcReg[0], i, 1); - src1 = get_src_reg(c, &inst->SrcReg[1], i, 1); + dst = get_dst_reg(c, inst, i); + src0 = get_src_reg(c, &inst->SrcReg[0], i); + src1 = get_src_reg(c, &inst->SrcReg[1], i); brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); brw_MOV(p, dst, src0); brw_set_saturate(p, 0); @@ -998,9 +1000,9 @@ static void emit_pow(struct brw_wm_compile *c, { struct brw_compile *p = &c->func; struct brw_reg dst, src0, src1; - dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1); - src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1); - src1 = get_src_reg(c, &inst->SrcReg[1], 0, 1); + dst = get_dst_reg(c, inst, get_scalar_dst_index(inst)); + src0 = get_src_reg(c, &inst->SrcReg[0], 0); + src1 = get_src_reg(c, &inst->SrcReg[1], 0); brw_MOV(p, brw_message_reg(2), src0); brw_MOV(p, brw_message_reg(3), src1); @@ -1025,10 +1027,10 @@ static void emit_lrp(struct brw_wm_compile *c, int mark = mark_tmps(c); for (i = 0; i < 4; i++) { if (mask & (1<SrcReg[0], i, 1); + dst = get_dst_reg(c, inst, i); + src0 = get_src_reg(c, &inst->SrcReg[0], i); - src1 = get_src_reg(c, &inst->SrcReg[1], i, 1); + src1 = get_src_reg(c, &inst->SrcReg[1], i); if (src1.nr == dst.nr) { tmp1 = alloc_tmp(c); @@ -1036,7 +1038,7 @@ static void emit_lrp(struct brw_wm_compile *c, } else tmp1 = src1; - src2 = get_src_reg(c, &inst->SrcReg[2], i, 1); + src2 = get_src_reg(c, &inst->SrcReg[2], i); if (src2.nr == dst.nr) { tmp2 = alloc_tmp(c); brw_MOV(p, tmp2, src2); @@ -1078,10 +1080,10 @@ static void emit_mad(struct brw_wm_compile *c, for (i = 0; i < 4; i++) { if (mask & (1<SrcReg[0], i, 1); - src1 = get_src_reg(c, &inst->SrcReg[1], i, 1); - src2 = get_src_reg(c, &inst->SrcReg[2], i, 1); + dst = get_dst_reg(c, inst, i); + src0 = get_src_reg(c, &inst->SrcReg[0], i); + src1 = get_src_reg(c, &inst->SrcReg[1], i); + src2 = get_src_reg(c, &inst->SrcReg[2], i); brw_MUL(p, dst, src0, src1); brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); @@ -1101,9 +1103,9 @@ static void emit_sop(struct brw_wm_compile *c, for (i = 0; i < 4; i++) { if (mask & (1<SrcReg[0], i, 1); - src1 = get_src_reg(c, &inst->SrcReg[1], i, 1); + dst = get_dst_reg(c, inst, i); + src0 = get_src_reg(c, &inst->SrcReg[0], i); + src1 = get_src_reg(c, &inst->SrcReg[1], i); brw_push_insn_state(p); brw_CMP(p, brw_null_reg(), cond, src0, src1); brw_set_predicate_control(p, BRW_PREDICATE_NONE); @@ -1160,8 +1162,8 @@ static void emit_ddx(struct brw_wm_compile *c, struct brw_reg dst; struct brw_reg src0, w; GLuint nr, i; - src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1); - w = get_src_reg(c, &inst->SrcReg[1], 3, 1); + src0 = get_src_reg(c, &inst->SrcReg[0], 0); + w = get_src_reg(c, &inst->SrcReg[1], 3); nr = src0.nr; interp[0] = brw_vec1_grf(nr, 0); interp[1] = brw_vec1_grf(nr, 4); @@ -1170,7 +1172,7 @@ static void emit_ddx(struct brw_wm_compile *c, brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF); for(i = 0; i < 4; i++ ) { if (mask & (1<SrcReg[0], 0, 1); + src0 = get_src_reg(c, &inst->SrcReg[0], 0); nr = src0.nr; - w = get_src_reg(c, &inst->SrcReg[1], 3, 1); + w = get_src_reg(c, &inst->SrcReg[1], 3); interp[0] = brw_vec1_grf(nr, 0); interp[1] = brw_vec1_grf(nr, 4); interp[2] = brw_vec1_grf(nr+1, 0); @@ -1198,7 +1200,7 @@ static void emit_ddy(struct brw_wm_compile *c, brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF); for(i = 0; i < 4; i++ ) { if (mask & (1<SrcReg, 0, 1 ); + src = get_src_reg( c, inst->SrcReg, 0 ); param = alloc_tmp( c ); @@ -1344,7 +1346,7 @@ static void emit_noise1( struct brw_wm_compile *c, brw_set_saturate( p, inst->SaturateMode == SATURATE_ZERO_ONE ); for (i = 0 ; i < 4; i++) { if (mask & (1<SrcReg, 0, 1 ); - src1 = get_src_reg( c, inst->SrcReg, 1, 1 ); + src0 = get_src_reg( c, inst->SrcReg, 0 ); + src1 = get_src_reg( c, inst->SrcReg, 1 ); param0 = alloc_tmp( c ); param1 = alloc_tmp( c ); @@ -1517,7 +1519,7 @@ static void emit_noise2( struct brw_wm_compile *c, brw_set_saturate( p, inst->SaturateMode == SATURATE_ZERO_ONE ); for (i = 0 ; i < 4; i++) { if (mask & (1<SrcReg, 0, 1 ); - src1 = get_src_reg( c, inst->SrcReg, 1, 1 ); - src2 = get_src_reg( c, inst->SrcReg, 2, 1 ); + src0 = get_src_reg( c, inst->SrcReg, 0 ); + src1 = get_src_reg( c, inst->SrcReg, 1 ); + src2 = get_src_reg( c, inst->SrcReg, 2 ); param0 = alloc_tmp( c ); param1 = alloc_tmp( c ); @@ -1823,7 +1825,7 @@ static void emit_noise3( struct brw_wm_compile *c, brw_set_saturate( p, inst->SaturateMode == SATURATE_ZERO_ONE ); for (i = 0 ; i < 4; i++) { if (mask & (1<SrcReg, 0, 1 ); - src1 = get_src_reg( c, inst->SrcReg, 1, 1 ); - src2 = get_src_reg( c, inst->SrcReg, 2, 1 ); - src3 = get_src_reg( c, inst->SrcReg, 3, 1 ); + src0 = get_src_reg( c, inst->SrcReg, 0 ); + src1 = get_src_reg( c, inst->SrcReg, 1 ); + src2 = get_src_reg( c, inst->SrcReg, 2 ); + src3 = get_src_reg( c, inst->SrcReg, 3 ); param0 = alloc_tmp( c ); param1 = alloc_tmp( c ); @@ -2249,7 +2251,7 @@ static void emit_noise4( struct brw_wm_compile *c, brw_set_saturate( p, inst->SaturateMode == SATURATE_ZERO_ONE ); for (i = 0 ; i < 4; i++) { if (mask & (1<DstReg.WriteMask; struct brw_reg src0[2], dst[2]; - dst[0] = get_dst_reg(c, inst, 0, 1); - dst[1] = get_dst_reg(c, inst, 1, 1); + dst[0] = get_dst_reg(c, inst, 0); + dst[1] = get_dst_reg(c, inst, 1); - src0[0] = get_src_reg(c, &inst->SrcReg[0], 0, 1); - src0[1] = get_src_reg(c, &inst->SrcReg[0], 1, 1); + src0[0] = get_src_reg(c, &inst->SrcReg[0], 0); + src0[1] = get_src_reg(c, &inst->SrcReg[0], 1); /* Calculate the pixel offset from window bottom left into destination * X and Y channels. @@ -2305,9 +2307,9 @@ static void emit_txb(struct brw_wm_compile *c, GLuint i; payload_reg = get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, 0, 1, 0, 0); for (i = 0; i < 4; i++) - dst[i] = get_dst_reg(c, inst, i, 1); + dst[i] = get_dst_reg(c, inst, i); for (i = 0; i < 4; i++) - src[i] = get_src_reg(c, &inst->SrcReg[0], i, 1); + src[i] = get_src_reg(c, &inst->SrcReg[0], i); switch (inst->TexSrcTarget) { case TEXTURE_1D_INDEX: @@ -2357,9 +2359,9 @@ static void emit_tex(struct brw_wm_compile *c, payload_reg = get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, 0, 1, 0, 0); for (i = 0; i < 4; i++) - dst[i] = get_dst_reg(c, inst, i, 1); + dst[i] = get_dst_reg(c, inst, i); for (i = 0; i < 4; i++) - src[i] = get_src_reg(c, &inst->SrcReg[0], i, 1); + src[i] = get_src_reg(c, &inst->SrcReg[0], i); switch (inst->TexSrcTarget) { -- cgit v1.2.3 From 154cd7a72363513f2d3d8d83fe19d69518df7d2e Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 24 Mar 2009 17:29:40 -0600 Subject: i965: add support for float literal instruction operands Call the get_src_reg_imm() function when it's permissible to generate a literal value src register. --- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 63 ++++++++++++++++++++++----------- 1 file changed, 43 insertions(+), 20 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index ffde59e143..00f2d3af85 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -258,9 +258,32 @@ static struct brw_reg get_src_reg(struct brw_wm_compile *c, const int nr = 1; int component = GET_SWZ(src->Swizzle, index); return get_reg(c, src->File, src->Index, component, nr, - src->NegateBase, src->Abs); + src->NegateBase, src->Abs); } + +/** + * Same as \sa get_src_reg() but if the register is a literal, emit + * a brw_reg encoding the literal. + * Note that a brw instruction only allows one src operand to be a literal. + * For instructions with more than one operand, only the second can be a literal. + */ +static struct brw_reg get_src_reg_imm(struct brw_wm_compile *c, + struct prog_src_register *src, int index) +{ + if (src->File == PROGRAM_CONSTANT) { + /* a literal */ + const int component = GET_SWZ(src->Swizzle, index); + const GLfloat *param = + c->fp->program.Base.Parameters->ParameterValues[src->Index]; + return brw_imm_f(param[component]); + } + else { + return get_src_reg(c, src, index); + } +} + + /** * Subroutines are minimal support for resusable instruction sequences. * They are implemented as simply as possible to minimise overhead: there @@ -371,7 +394,7 @@ static void emit_mov( struct brw_wm_compile *c, if (mask & (1<SrcReg[0], i); + src = get_src_reg_imm(c, &inst->SrcReg[0], i); brw_MOV(p, dst, src); } } @@ -698,10 +721,10 @@ static void emit_xpd(struct brw_wm_compile *c, struct brw_reg src0, src1, dst; dst = get_dst_reg(c, inst, i); src0 = negate(get_src_reg(c, &inst->SrcReg[0], i2)); - src1 = get_src_reg(c, &inst->SrcReg[1], i1); + src1 = get_src_reg_imm(c, &inst->SrcReg[1], i1); brw_MUL(p, brw_null_reg(), src0, src1); src0 = get_src_reg(c, &inst->SrcReg[0], i1); - src1 = get_src_reg(c, &inst->SrcReg[1], i2); + src1 = get_src_reg_imm(c, &inst->SrcReg[1], i2); brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF); brw_MAC(p, dst, src0, src1); brw_set_saturate(p, 0); @@ -718,7 +741,7 @@ static void emit_dp3(struct brw_wm_compile *c, struct brw_compile *p = &c->func; for (i = 0; i < 3; i++) { src0[i] = get_src_reg(c, &inst->SrcReg[0], i); - src1[i] = get_src_reg(c, &inst->SrcReg[1], i); + src1[i] = get_src_reg_imm(c, &inst->SrcReg[1], i); } dst = get_dst_reg(c, inst, get_scalar_dst_index(inst)); @@ -737,7 +760,7 @@ static void emit_dp4(struct brw_wm_compile *c, struct brw_compile *p = &c->func; for (i = 0; i < 4; i++) { src0[i] = get_src_reg(c, &inst->SrcReg[0], i); - src1[i] = get_src_reg(c, &inst->SrcReg[1], i); + src1[i] = get_src_reg_imm(c, &inst->SrcReg[1], i); } dst = get_dst_reg(c, inst, get_scalar_dst_index(inst)); brw_MUL(p, brw_null_reg(), src0[0], src1[0]); @@ -756,7 +779,7 @@ static void emit_dph(struct brw_wm_compile *c, struct brw_compile *p = &c->func; for (i = 0; i < 4; i++) { src0[i] = get_src_reg(c, &inst->SrcReg[0], i); - src1[i] = get_src_reg(c, &inst->SrcReg[1], i); + src1[i] = get_src_reg_imm(c, &inst->SrcReg[1], i); } dst = get_dst_reg(c, inst, get_scalar_dst_index(inst)); brw_MUL(p, brw_null_reg(), src0[0], src1[0]); @@ -857,7 +880,7 @@ static void emit_add(struct brw_wm_compile *c, if (mask & (1<SrcReg[0], i); - src1 = get_src_reg(c, &inst->SrcReg[1], i); + src1 = get_src_reg_imm(c, &inst->SrcReg[1], i); brw_ADD(p, dst, src0, src1); } } @@ -876,7 +899,7 @@ static void emit_sub(struct brw_wm_compile *c, if (mask & (1<SrcReg[0], i); - src1 = get_src_reg(c, &inst->SrcReg[1], i); + src1 = get_src_reg_imm(c, &inst->SrcReg[1], i); brw_ADD(p, dst, src0, negate(src1)); } } @@ -895,7 +918,7 @@ static void emit_mul(struct brw_wm_compile *c, if (mask & (1<SrcReg[0], i); - src1 = get_src_reg(c, &inst->SrcReg[1], i); + src1 = get_src_reg_imm(c, &inst->SrcReg[1], i); brw_MUL(p, dst, src0, src1); } } @@ -913,7 +936,7 @@ static void emit_frc(struct brw_wm_compile *c, for (i = 0 ; i < 4; i++) { if (mask & (1<SrcReg[0], i); + src0 = get_src_reg_imm(c, &inst->SrcReg[0], i); brw_FRC(p, dst, src0); } } @@ -932,7 +955,7 @@ static void emit_flr(struct brw_wm_compile *c, for (i = 0 ; i < 4; i++) { if (mask & (1<SrcReg[0], i); + src0 = get_src_reg_imm(c, &inst->SrcReg[0], i); brw_RNDD(p, dst, src0); } } @@ -951,7 +974,7 @@ static void emit_max(struct brw_wm_compile *c, if (mask & (1<SrcReg[0], i); - src1 = get_src_reg(c, &inst->SrcReg[1], i); + src1 = get_src_reg_imm(c, &inst->SrcReg[1], i); brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); brw_MOV(p, dst, src0); brw_set_saturate(p, 0); @@ -978,7 +1001,7 @@ static void emit_min(struct brw_wm_compile *c, for (i = 0; i < 4; i++) { if (mask & (1<SrcReg[0], i); + src0 = get_src_reg_imm(c, &inst->SrcReg[0], i); src1 = get_src_reg(c, &inst->SrcReg[1], i); brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); brw_MOV(p, dst, src0); @@ -1001,8 +1024,8 @@ static void emit_pow(struct brw_wm_compile *c, struct brw_compile *p = &c->func; struct brw_reg dst, src0, src1; dst = get_dst_reg(c, inst, get_scalar_dst_index(inst)); - src0 = get_src_reg(c, &inst->SrcReg[0], 0); - src1 = get_src_reg(c, &inst->SrcReg[1], 0); + src0 = get_src_reg_imm(c, &inst->SrcReg[0], 0); + src1 = get_src_reg_imm(c, &inst->SrcReg[1], 0); brw_MOV(p, brw_message_reg(2), src0); brw_MOV(p, brw_message_reg(3), src1); @@ -1030,7 +1053,7 @@ static void emit_lrp(struct brw_wm_compile *c, dst = get_dst_reg(c, inst, i); src0 = get_src_reg(c, &inst->SrcReg[0], i); - src1 = get_src_reg(c, &inst->SrcReg[1], i); + src1 = get_src_reg_imm(c, &inst->SrcReg[1], i); if (src1.nr == dst.nr) { tmp1 = alloc_tmp(c); @@ -1082,8 +1105,8 @@ static void emit_mad(struct brw_wm_compile *c, if (mask & (1<SrcReg[0], i); - src1 = get_src_reg(c, &inst->SrcReg[1], i); - src2 = get_src_reg(c, &inst->SrcReg[2], i); + src1 = get_src_reg_imm(c, &inst->SrcReg[1], i); + src2 = get_src_reg_imm(c, &inst->SrcReg[2], i); brw_MUL(p, dst, src0, src1); brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); @@ -1105,7 +1128,7 @@ static void emit_sop(struct brw_wm_compile *c, if (mask & (1<SrcReg[0], i); - src1 = get_src_reg(c, &inst->SrcReg[1], i); + src1 = get_src_reg_imm(c, &inst->SrcReg[1], i); brw_push_insn_state(p); brw_CMP(p, brw_null_reg(), cond, src0, src1); brw_set_predicate_control(p, BRW_PREDICATE_NONE); -- cgit v1.2.3 From e1a1a5a6385e0bc6f2f20ec0a2e23f81726e232e Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 24 Mar 2009 18:05:29 -0600 Subject: i965: comments for sampling code --- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 56 ++++++++++++++++----------------- 1 file changed, 28 insertions(+), 28 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 00f2d3af85..4e99611be8 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -2336,9 +2336,9 @@ static void emit_txb(struct brw_wm_compile *c, switch (inst->TexSrcTarget) { case TEXTURE_1D_INDEX: - brw_MOV(p, brw_message_reg(2), src[0]); - brw_MOV(p, brw_message_reg(3), brw_imm_f(0)); - brw_MOV(p, brw_message_reg(4), brw_imm_f(0)); + brw_MOV(p, brw_message_reg(2), src[0]); /* s coord */ + brw_MOV(p, brw_message_reg(3), brw_imm_f(0)); /* t coord */ + brw_MOV(p, brw_message_reg(4), brw_imm_f(0)); /* r coord */ break; case TEXTURE_2D_INDEX: case TEXTURE_RECT_INDEX: @@ -2352,19 +2352,19 @@ static void emit_txb(struct brw_wm_compile *c, brw_MOV(p, brw_message_reg(4), src[2]); break; } - brw_MOV(p, brw_message_reg(5), src[3]); - brw_MOV(p, brw_message_reg(6), brw_imm_f(0)); + brw_MOV(p, brw_message_reg(5), src[3]); /* bias */ + brw_MOV(p, brw_message_reg(6), brw_imm_f(0)); /* ref (unused?) */ brw_SAMPLE(p, - retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW), - 1, - retype(payload_reg, BRW_REGISTER_TYPE_UW), - unit + MAX_DRAW_BUFFERS, /* surface */ - unit, /* sampler */ - inst->DstReg.WriteMask, - BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS, - 4, - 4, - 0); + retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW), /* dest */ + 1, /* msg_reg_nr */ + retype(payload_reg, BRW_REGISTER_TYPE_UW), /* src0 */ + unit + MAX_DRAW_BUFFERS, /* surface */ + unit, /* sampler */ + inst->DstReg.WriteMask, /* writemask */ + BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS, /* msg_type */ + 4, /* response_length */ + 4, /* msg_length */ + 0); /* eot */ } static void emit_tex(struct brw_wm_compile *c, @@ -2386,7 +2386,6 @@ static void emit_tex(struct brw_wm_compile *c, for (i = 0; i < 4; i++) src[i] = get_src_reg(c, &inst->SrcReg[0], i); - switch (inst->TexSrcTarget) { case TEXTURE_1D_INDEX: emit = WRITEMASK_X; @@ -2404,6 +2403,7 @@ static void emit_tex(struct brw_wm_compile *c, } msg_len = 1; + /* move/load S, T, R coords */ for (i = 0; i < nr; i++) { static const GLuint swz[4] = {0,1,2,2}; if (emit & (1<DstReg.WriteMask, - BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE, - 4, - shadow ? 6 : 4, - 0); + retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW), /* dest */ + 1, /* msg_reg_nr */ + retype(payload_reg, BRW_REGISTER_TYPE_UW), /* src0 */ + unit + MAX_DRAW_BUFFERS, /* surface */ + unit, /* sampler */ + inst->DstReg.WriteMask, /* writemask */ + BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE, /* msg_type */ + 4, /* response_length */ + shadow ? 6 : 4, /* msg_length */ + 0); /* eot */ if (shadow) brw_MOV(p, dst[3], brw_imm_f(1.0)); -- cgit v1.2.3 From 1146d40b9c35d80c0860c773de1eef27c76e8c01 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 24 Mar 2009 18:05:53 -0600 Subject: i965: comments for brw_SAMPLE() --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 6dce1ca48e..4becdf069f 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -966,7 +966,11 @@ void brw_fb_WRITE(struct brw_compile *p, } - +/** + * Texture sample instruction. + * Note: the msg_type plus msg_length values determine exactly what kind + * of sampling operation is performed. See volume 4, page 161 of docs. + */ void brw_SAMPLE(struct brw_compile *p, struct brw_reg dest, GLuint msg_reg_nr, -- cgit v1.2.3 From 6b18a8d3e7114a1af931a2fc20a1e23cb2d7789c Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 31 Mar 2009 10:49:41 -0600 Subject: i965: new and updated comments --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 46 +++++++++++++++++++++------------ 1 file changed, 29 insertions(+), 17 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 4becdf069f..03e4cdde33 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -320,14 +320,15 @@ static void brw_set_dp_read_message( struct brw_instruction *insn, { brw_set_src1(insn, brw_imm_d(0)); - insn->bits3.dp_read.binding_table_index = binding_table_index; - insn->bits3.dp_read.msg_control = msg_control; - insn->bits3.dp_read.msg_type = msg_type; - insn->bits3.dp_read.target_cache = target_cache; - insn->bits3.dp_read.response_length = response_length; - insn->bits3.dp_read.msg_length = msg_length; - insn->bits3.dp_read.msg_target = BRW_MESSAGE_TARGET_DATAPORT_READ; - insn->bits3.dp_read.end_of_thread = end_of_thread; + insn->bits3.dp_read.binding_table_index = binding_table_index; /*0:7*/ + insn->bits3.dp_read.msg_control = msg_control; /*8:11*/ + insn->bits3.dp_read.msg_type = msg_type; /*12:13*/ + insn->bits3.dp_read.target_cache = target_cache; /*14:15*/ + insn->bits3.dp_read.response_length = response_length; /*16:19*/ + insn->bits3.dp_read.msg_length = msg_length; /*20:23*/ + insn->bits3.dp_read.msg_target = BRW_MESSAGE_TARGET_DATAPORT_READ; /*24:27*/ + insn->bits3.dp_read.pad1 = 0; /*28:30*/ + insn->bits3.dp_read.end_of_thread = end_of_thread; /*31*/ } static void brw_set_sampler_message(struct brw_context *brw, @@ -770,7 +771,7 @@ void brw_CMP(struct brw_compile *p, * Helpers for the various SEND message types: */ -/* Invert 8 values +/** Extended math function, float[8]. */ void brw_math( struct brw_compile *p, struct brw_reg dest, @@ -802,7 +803,9 @@ void brw_math( struct brw_compile *p, data_type); } -/* Use 2 send instructions to invert 16 elements +/** + * Extended math function, float[16]. + * Use 2 send instructions. */ void brw_math_16( struct brw_compile *p, struct brw_reg dest, @@ -855,8 +858,11 @@ void brw_math_16( struct brw_compile *p, } - - +/** + * Write block of 16 dwords/floats to the data port Render Cache scratch buffer. + * Scratch offset should be a multiple of 64. + * Used for register spilling. + */ void brw_dp_WRITE_16( struct brw_compile *p, struct brw_reg src, GLuint msg_reg_nr, @@ -867,6 +873,7 @@ void brw_dp_WRITE_16( struct brw_compile *p, brw_set_mask_control(p, BRW_MASK_DISABLE); brw_set_compression_control(p, BRW_COMPRESSION_NONE); + /* set message header global offset field (reg 0, element 2) */ brw_MOV(p, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_D), brw_imm_d(scratch_offset)); @@ -887,7 +894,7 @@ void brw_dp_WRITE_16( struct brw_compile *p, brw_set_src0(insn, src); brw_set_dp_write_message(insn, - 255, /* bti */ + 255, /* binding table index (255=stateless) */ BRW_DATAPORT_OWORD_BLOCK_4_OWORDS, /* msg_control */ BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE, /* msg_type */ msg_length, @@ -895,10 +902,14 @@ void brw_dp_WRITE_16( struct brw_compile *p, 0, /* response_length */ 0); /* eot */ } - } +/** + * Read block of 16 dwords/floats from the data port Render Cache scratch buffer. + * Scratch offset should be a multiple of 64. + * Used for register spilling. + */ void brw_dp_READ_16( struct brw_compile *p, struct brw_reg dest, GLuint msg_reg_nr, @@ -909,6 +920,7 @@ void brw_dp_READ_16( struct brw_compile *p, brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_set_mask_control(p, BRW_MASK_DISABLE); + /* set message header global offset field (reg 0, element 2) */ brw_MOV(p, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_D), brw_imm_d(scratch_offset)); @@ -927,10 +939,10 @@ void brw_dp_READ_16( struct brw_compile *p, brw_set_src0(insn, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); brw_set_dp_read_message(insn, - 255, /* bti */ - 3, /* msg_control */ + 255, /* binding table index (255=stateless) */ + 3, /* msg_control (3 means 4 Owords) */ BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, /* msg_type */ - 1, /* target cache */ + 1, /* target cache (render/scratch) */ 1, /* msg_length */ 2, /* response_length */ 0); /* eot */ -- cgit v1.2.3 From 8127e49b93820d1768e2d298bbe238dd55c20732 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 31 Mar 2009 10:50:55 -0600 Subject: i965: added new brw_dp_READ_4() function Used to read float[4] vectors from the constant buffer/surface. --- src/mesa/drivers/dri/i965/brw_eu.h | 7 +++++ src/mesa/drivers/dri/i965/brw_eu_emit.c | 50 +++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index eb99c21711..c94889ab1c 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -851,6 +851,13 @@ void brw_dp_READ_16( struct brw_compile *p, GLuint msg_reg_nr, GLuint scratch_offset ); +void brw_dp_READ_4( struct brw_compile *p, + struct brw_reg dest, + GLuint msg_reg_nr, + GLboolean relAddr, + GLuint scratch_offset, + GLuint bind_table_index ); + void brw_dp_WRITE_16( struct brw_compile *p, struct brw_reg src, GLuint msg_reg_nr, diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 03e4cdde33..b149f0f21f 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -950,6 +950,56 @@ void brw_dp_READ_16( struct brw_compile *p, } +/** + * Read a float[4] vector from the data port Data Cache (const buffer). + * Scratch offset should be a multiple of 16. + * Used for fetching shader constants. + * If relAddr is true, we'll do an indirect fetch using the address register. + */ +void brw_dp_READ_4( struct brw_compile *p, + struct brw_reg dest, + GLuint msg_reg_nr, + GLboolean relAddr, + GLuint scratch_offset, + GLuint bind_table_index ) +{ + { + brw_push_insn_state(p); + brw_set_compression_control(p, BRW_COMPRESSION_NONE); + brw_set_mask_control(p, BRW_MASK_DISABLE); + + /* set message header global offset field (reg 0, element 2) */ + brw_MOV(p, + retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD), + brw_imm_d(scratch_offset)); + brw_pop_insn_state(p); + } + + { + struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); + + insn->header.predicate_control = 0; /* XXX */ + insn->header.compression_control = BRW_COMPRESSION_NONE; + insn->header.destreg__conditonalmod = msg_reg_nr; + + /* cast dest to a uword[8] vector */ + dest = retype(vec8(dest), BRW_REGISTER_TYPE_UW); + + brw_set_dest(insn, dest); + brw_set_src0(insn, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); + + brw_set_dp_read_message(insn, + bind_table_index, /* binding table index (255=stateless) */ + 0, /* msg_control (0 means 1 Oword) */ + BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, /* msg_type */ + 0, /* source cache = data cache */ + 1, /* msg_length */ + 2, /* response_length */ + 0); /* eot */ + } +} + + void brw_fb_WRITE(struct brw_compile *p, struct brw_reg dest, GLuint msg_reg_nr, -- cgit v1.2.3 From 1ee0e226469514335b80ff42e4cbef0f355bd8c4 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 31 Mar 2009 10:53:02 -0600 Subject: i965: minor code movement, new comment --- src/mesa/drivers/dri/i965/brw_wm_state.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c index 3ef451405c..58fa6aaf8f 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c @@ -125,6 +125,9 @@ wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key) key->offset_factor = ctx->Polygon.OffsetFactor; } +/** + * Setup wm hardware state. See page 225 of Volume 2 + */ static dri_bo * wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key, dri_bo **reloc_bufs) @@ -151,9 +154,9 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key, wm.thread3.dispatch_grf_start_reg = key->dispatch_grf_start_reg; wm.thread3.urb_entry_read_length = key->urb_entry_read_length; + wm.thread3.urb_entry_read_offset = 0; wm.thread3.const_urb_entry_read_length = key->curb_entry_read_length; wm.thread3.const_urb_entry_read_offset = key->curbe_offset * 2; - wm.thread3.urb_entry_read_offset = 0; wm.wm4.sampler_count = (key->sampler_count + 1) / 4; if (brw->wm.sampler_bo != NULL) { -- cgit v1.2.3 From ed8f54aa65eed2cdef79ddc110dad217d3955ec7 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 31 Mar 2009 10:53:37 -0600 Subject: i965: code to debug/dump instruction immediates --- src/mesa/drivers/dri/i965/brw_eu_debug.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_eu_debug.c b/src/mesa/drivers/dri/i965/brw_eu_debug.c index 91dbbd5af6..29f3f6d02f 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_debug.c +++ b/src/mesa/drivers/dri/i965/brw_eu_debug.c @@ -65,6 +65,7 @@ void brw_print_reg( struct brw_reg hwreg ) hwreg.width == BRW_WIDTH_8 && hwreg.hstride == BRW_HORIZONTAL_STRIDE_1 && hwreg.type == BRW_REGISTER_TYPE_F) { + /* vector register */ _mesa_printf("vec%d", hwreg.nr); } else if (hwreg.file == BRW_GENERAL_REGISTER_FILE && @@ -72,8 +73,12 @@ void brw_print_reg( struct brw_reg hwreg ) hwreg.width == BRW_WIDTH_1 && hwreg.hstride == BRW_HORIZONTAL_STRIDE_0 && hwreg.type == BRW_REGISTER_TYPE_F) { + /* "scalar" register */ _mesa_printf("scl%d.%d", hwreg.nr, hwreg.subnr / 4); } + else if (hwreg.file == BRW_IMMEDIATE_VALUE) { + _mesa_printf("imm %f", hwreg.dw1.f); + } else { _mesa_printf("%s%d.%d<%d;%d,%d>:%s", file[hwreg.file], -- cgit v1.2.3 From 5f1ce6b87e837b9f6bc2a4f3e81cf8feea4af2df Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 31 Mar 2009 10:53:56 -0600 Subject: i965: comments --- src/mesa/drivers/dri/i965/brw_wm.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 7909fd65a9..90d74c2885 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -105,12 +105,17 @@ brw_wm_non_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c) brw_wm_pass1(c); /* Register allocation. + * Divide by two because we operate on 16 pixels at a time and require + * two GRF entries for each logical shader register. */ c->grf_limit = BRW_WM_MAX_GRF / 2; brw_wm_pass2(c); + /* how many general-purpose registers are used */ c->prog_data.total_grf = c->max_wm_grf; + + /* Scratch space is used for register spilling */ if (c->last_scratch) { c->prog_data.total_scratch = c->last_scratch + 0x40; } -- cgit v1.2.3 From a9c62a2340794977a87cba4a352c02fc16f81505 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 31 Mar 2009 14:25:32 -0600 Subject: i965: do negation and Abs in get_src_reg_imm() Fixes regression seen with progs/glsl/bump.c --- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 4e99611be8..67ba59c325 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -276,7 +276,12 @@ static struct brw_reg get_src_reg_imm(struct brw_wm_compile *c, const int component = GET_SWZ(src->Swizzle, index); const GLfloat *param = c->fp->program.Base.Parameters->ParameterValues[src->Index]; - return brw_imm_f(param[component]); + GLfloat value = param[component]; + if (src->NegateBase) + value = -value; + if (src->Abs) + value = FABSF(value); + return brw_imm_f(value); } else { return get_src_reg(c, src, index); -- cgit v1.2.3 From 8c093a1fb0843e152d2a515c5127ccd5999b0d94 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 31 Mar 2009 16:56:55 -0600 Subject: i965: code to setup a constant buffer sampler This code won't actually be used and will be removed in a subsequent commit. Just committing for posterity. --- src/mesa/drivers/dri/i965/brw_wm_sampler_state.c | 43 ++++++++++++++++++++++++ 1 file changed, 43 insertions(+) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c index 68a9296a71..e13eb28011 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c @@ -217,6 +217,45 @@ static void brw_update_sampler_state(struct wm_sampler_entry *key, sampler->ss2.default_color_pointer = sdc_bo->offset >> 5; /* reloc */ } + +#if 0 +/** + * Setup the sampler state for the "constant buffer texture". + * The constant buffer texture is basically a 1D float[4] texture whose + * width == the number of program parameters/constants. + */ +static void +brwm_wm_setup_constant_sampler(struct brw_context *brw, + struct wm_sampler_key *key) +{ + static const GLfloat black[4] = {0.0F, 0.0F, 0.0F, 0.0F}; + const GLuint unit = BRW_MAX_TEX_UNIT - 1; + struct wm_sampler_entry *entry = &key->sampler[unit]; + + entry->tex_target = GL_TEXTURE_1D; + + entry->wrap_r = GL_CLAMP_TO_EDGE; + entry->wrap_s = GL_CLAMP_TO_EDGE; + entry->wrap_t = GL_CLAMP_TO_EDGE; + + entry->maxlod = 0.0F; + entry->minlod = 0.0F; + entry->lod_bias = 0.0F; + entry->max_aniso = 0.0F; + entry->minfilter = GL_NEAREST; + entry->magfilter = GL_NEAREST; + entry->comparemode = GL_NONE; + entry->comparefunc = GL_ALWAYS; + + dri_bo_unreference(brw->wm.sdc_bo[unit]); + + brw->wm.sdc_bo[unit] = upload_default_color(brw, black); + + key->sampler_count = unit + 1; +} +#endif + + /** Sets up the cache key for sampler state for all texture units */ static void brw_wm_sampler_populate_key(struct brw_context *brw, @@ -271,6 +310,10 @@ brw_wm_sampler_populate_key(struct brw_context *brw, key->sampler_count = unit + 1; } } + +#if 0 + brwm_wm_setup_constant_sampler(brw, key); +#endif } /* All samplers must be uploaded in a single contiguous array, which -- cgit v1.2.3 From ba8b25a46cdd52e7b9116cc7d76dc4db4d667464 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 31 Mar 2009 16:57:39 -0600 Subject: i965: remove unused code for sampling a constant buffer --- src/mesa/drivers/dri/i965/brw_wm_sampler_state.c | 42 ------------------------ 1 file changed, 42 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c index e13eb28011..1fc9f01372 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c @@ -218,44 +218,6 @@ static void brw_update_sampler_state(struct wm_sampler_entry *key, } -#if 0 -/** - * Setup the sampler state for the "constant buffer texture". - * The constant buffer texture is basically a 1D float[4] texture whose - * width == the number of program parameters/constants. - */ -static void -brwm_wm_setup_constant_sampler(struct brw_context *brw, - struct wm_sampler_key *key) -{ - static const GLfloat black[4] = {0.0F, 0.0F, 0.0F, 0.0F}; - const GLuint unit = BRW_MAX_TEX_UNIT - 1; - struct wm_sampler_entry *entry = &key->sampler[unit]; - - entry->tex_target = GL_TEXTURE_1D; - - entry->wrap_r = GL_CLAMP_TO_EDGE; - entry->wrap_s = GL_CLAMP_TO_EDGE; - entry->wrap_t = GL_CLAMP_TO_EDGE; - - entry->maxlod = 0.0F; - entry->minlod = 0.0F; - entry->lod_bias = 0.0F; - entry->max_aniso = 0.0F; - entry->minfilter = GL_NEAREST; - entry->magfilter = GL_NEAREST; - entry->comparemode = GL_NONE; - entry->comparefunc = GL_ALWAYS; - - dri_bo_unreference(brw->wm.sdc_bo[unit]); - - brw->wm.sdc_bo[unit] = upload_default_color(brw, black); - - key->sampler_count = unit + 1; -} -#endif - - /** Sets up the cache key for sampler state for all texture units */ static void brw_wm_sampler_populate_key(struct brw_context *brw, @@ -310,10 +272,6 @@ brw_wm_sampler_populate_key(struct brw_context *brw, key->sampler_count = unit + 1; } } - -#if 0 - brwm_wm_setup_constant_sampler(brw, key); -#endif } /* All samplers must be uploaded in a single contiguous array, which -- cgit v1.2.3 From 597cd5b94e4818679af1134d053541f3d2cfb80e Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 31 Mar 2009 17:06:22 -0600 Subject: i965: check-point commit of new constant buffer support Currently, shader constants are stored in the GRF (loaded from the CURBE prior to shader execution). This severly limits the number of constants and temps that we can support. This new code will support (practically) unlimited size constant buffers and free up registers in the GRF. We allocate a new buffer object for the constants and read them with "Read" messages/instructions. When only a small number of constants are used, we can still use the old method. The code works for fragment shaders only (and is actually disabled) for now. Need to do the same thing for vertex shaders and need to add the necessary code-gen to fetch the constants which are referenced by the shader instructions. --- src/mesa/drivers/dri/i965/brw_context.h | 17 ++- src/mesa/drivers/dri/i965/brw_curbe.c | 31 ++++++ src/mesa/drivers/dri/i965/brw_program.c | 20 ++++ src/mesa/drivers/dri/i965/brw_wm_glsl.c | 133 ++++++++++++++++++----- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 122 +++++++++++++++++++-- 5 files changed, 288 insertions(+), 35 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index a020b621d6..01e07c967f 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -167,6 +167,9 @@ struct brw_fragment_program { struct gl_fragment_program program; GLuint id; /**< serial no. to identify frag progs, never re-used */ GLboolean isGLSL; /**< really, any IF/LOOP/CONT/BREAK instructions */ + + /** Program constant buffer/surface */ + dri_bo *const_buffer; }; @@ -238,8 +241,16 @@ struct brw_vs_ouput_sizes { }; +/** Number of texture sampler units */ #define BRW_MAX_TEX_UNIT 16 -#define BRW_WM_MAX_SURF BRW_MAX_TEX_UNIT + MAX_DRAW_BUFFERS + +/** + * Size of our surface binding table. + * This contains pointers to the drawing surfaces and current texture + * objects and shader constant buffer (+1). + */ +#define BRW_WM_MAX_SURF (MAX_DRAW_BUFFERS + BRW_MAX_TEX_UNIT + 1) + enum brw_cache_id { BRW_CC_VP, @@ -513,8 +524,8 @@ struct brw_context /* BRW_NEW_CURBE_OFFSETS: */ struct { - GLuint wm_start; - GLuint wm_size; + GLuint wm_start; /**< pos of first wm const in CURBE buffer */ + GLuint wm_size; /**< number of float[4] consts, multiple of 16 */ GLuint clip_start; GLuint clip_size; GLuint vs_start; diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c index 545dedd34b..39a8610952 100644 --- a/src/mesa/drivers/dri/i965/brw_curbe.c +++ b/src/mesa/drivers/dri/i965/brw_curbe.c @@ -38,6 +38,7 @@ #include "shader/prog_parameter.h" #include "shader/prog_statevars.h" #include "intel_batchbuffer.h" +#include "intel_regions.h" #include "brw_context.h" #include "brw_defines.h" #include "brw_state.h" @@ -251,6 +252,7 @@ static void prepare_constant_buffer(struct brw_context *brw) _mesa_load_state_parameters(ctx, vp->program.Base.Parameters); + /* XXX just use a memcpy here */ for (i = 0; i < nr; i++) { const GLfloat *value = vp->program.Base.Parameters->ParameterValues[i]; buf[offset + i * 4 + 0] = value[0]; @@ -330,11 +332,40 @@ static void prepare_constant_buffer(struct brw_context *brw) } +/** + * Vertex/fragment shader constants are stored in a pseudo 1D texture. + * This function updates the constants in that buffer. + */ +static void +update_texture_constant_buffer(struct brw_context *brw) +{ + struct intel_context *intel = &brw->intel; + struct brw_fragment_program *fp = + (struct brw_fragment_program *) brw->fragment_program; + const struct gl_program_parameter_list *params = fp->program.Base.Parameters; + const int size = params->NumParameters * 4 * sizeof(GLfloat); + + assert(fp->const_buffer); + assert(fp->const_buffer->size >= size); + + /* copy constants into the buffer */ + if (size > 0) { + GLubyte *map; + dri_bo_map(fp->const_buffer, GL_TRUE); + map = fp->const_buffer->virtual; + memcpy(map, params->ParameterValues, size); + dri_bo_unmap(fp->const_buffer); + } +} + + static void emit_constant_buffer(struct brw_context *brw) { struct intel_context *intel = &brw->intel; GLuint sz = brw->curbe.total_size; + update_texture_constant_buffer(brw); + BEGIN_BATCH(2, IGNORE_CLIPRECTS); if (sz == 0) { OUT_BATCH((CMD_CONST_BUFFER << 16) | (2 - 2)); diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c index d90bd82038..457bc2fc7f 100644 --- a/src/mesa/drivers/dri/i965/brw_program.c +++ b/src/mesa/drivers/dri/i965/brw_program.c @@ -111,6 +111,8 @@ static void brwProgramStringNotify( GLcontext *ctx, struct gl_program *prog ) { struct brw_context *brw = brw_context(ctx); + struct intel_context *intel = &brw->intel; + if (target == GL_FRAGMENT_PROGRAM_ARB) { struct gl_fragment_program *fprog = (struct gl_fragment_program *) prog; struct brw_fragment_program *newFP = brw_fragment_program(fprog); @@ -126,6 +128,24 @@ static void brwProgramStringNotify( GLcontext *ctx, brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM; newFP->id = brw->program_id++; newFP->isGLSL = brw_wm_is_glsl(fprog); + + /* alloc constant buffer/surface */ + { + const struct gl_program_parameter_list *params = prog->Parameters; + const int size = params->NumParameters * 4 * sizeof(GLfloat); + + /* free old const buffer if too small */ + if (newFP->const_buffer && newFP->const_buffer->size < size) { + dri_bo_unreference(newFP->const_buffer); + newFP->const_buffer = NULL; + } + + if (!newFP->const_buffer) { + newFP->const_buffer = drm_intel_bo_alloc(intel->bufmgr, + "fp_const_buffer", + size, 64); + } + } } else if (target == GL_VERTEX_PROGRAM_ARB) { struct gl_vertex_program *vprog = (struct gl_vertex_program *) prog; diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 67ba59c325..28ef84e4aa 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -192,28 +192,41 @@ static void prealloc_reg(struct brw_wm_compile *c) /* constants */ { const int nr_params = c->fp->program.Base.Parameters->NumParameters; - const struct gl_program_parameter_list *plist = - c->fp->program.Base.Parameters; - int index = 0; - - /* number of float constants */ - c->prog_data.nr_params = 4 * nr_params; - - /* loop over program constants (float[4]) */ - for (i = 0; i < nr_params; i++) { - /* loop over XYZW channels */ - for (j = 0; j < 4; j++, index++) { - reg = brw_vec1_grf(c->reg_index + index / 8, index % 8); - /* Save pointer to parameter/constant value. - * Constants will be copied in prepare_constant_buffer() - */ - c->prog_data.param[index] = &plist->ParameterValues[i][j]; - set_reg(c, PROGRAM_STATE_VAR, i, j, reg); - } - } - /* number of constant regs used (each reg is float[8]) */ - c->nr_creg = 2 * ((4 * nr_params + 15) / 16); - c->reg_index += c->nr_creg; + + if (1 /* XXX threshold: nr_params <= 8 */) { + const struct gl_program_parameter_list *plist = + c->fp->program.Base.Parameters; + int index = 0; + + /* number of float constants in CURBE */ + c->prog_data.nr_params = 4 * nr_params; + + /* loop over program constants (float[4]) */ + for (i = 0; i < nr_params; i++) { + /* loop over XYZW channels */ + for (j = 0; j < 4; j++, index++) { + reg = brw_vec1_grf(c->reg_index + index / 8, index % 8); + /* Save pointer to parameter/constant value. + * Constants will be copied in prepare_constant_buffer() + */ + c->prog_data.param[index] = &plist->ParameterValues[i][j]; + set_reg(c, PROGRAM_STATE_VAR, i, j, reg); + } + } + /* number of constant regs used (each reg is float[8]) */ + c->nr_creg = 2 * ((4 * nr_params + 15) / 16); + c->reg_index += c->nr_creg; + } + else { + /* number of float constants in CURBE */ + c->prog_data.nr_params = 0; + + /* When there's a lot of FP constanst we'll store them in a + * texture-like buffer instead of using the CURBE buffer. + * This means we won't use GRF registers for constants and we'll + * have to fetch constants with a dataport read. + */ + } } /* fragment shader inputs */ @@ -892,6 +905,19 @@ static void emit_add(struct brw_wm_compile *c, brw_set_saturate(p, 0); } +static void emit_arl(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_compile *p = &c->func; + struct brw_reg src0, addr_reg; + brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); + addr_reg = brw_uw8_reg(BRW_ARCHITECTURE_REGISTER_FILE, + BRW_ARF_ADDRESS, 0); + src0 = get_src_reg(c, &inst->SrcReg[0], 0); /* channel 0 */ + brw_MOV(p, addr_reg, src0); + brw_set_saturate(p, 0); +} + static void emit_sub(struct brw_wm_compile *c, struct prog_instruction *inst) { @@ -2331,9 +2357,10 @@ static void emit_txb(struct brw_wm_compile *c, struct brw_compile *p = &c->func; struct brw_reg dst[4], src[4], payload_reg; GLuint unit = c->fp->program.Base.SamplerUnits[inst->TexSrcUnit]; - GLuint i; + payload_reg = get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, 0, 1, 0, 0); + for (i = 0; i < 4; i++) dst[i] = get_dst_reg(c, inst, i); for (i = 0; i < 4; i++) @@ -2372,13 +2399,13 @@ static void emit_txb(struct brw_wm_compile *c, 0); /* eot */ } + static void emit_tex(struct brw_wm_compile *c, struct prog_instruction *inst) { struct brw_compile *p = &c->func; struct brw_reg dst[4], src[4], payload_reg; GLuint unit = c->fp->program.Base.SamplerUnits[inst->TexSrcUnit]; - GLuint msg_len; GLuint i, nr; GLuint emit; @@ -2419,7 +2446,7 @@ static void emit_tex(struct brw_wm_compile *c, } if (shadow) { - brw_MOV(p, brw_message_reg(5), brw_imm_f(0)); /* lod / bais */ + brw_MOV(p, brw_message_reg(5), brw_imm_f(0)); /* lod / bias */ brw_MOV(p, brw_message_reg(6), src[2]); /* ref value / R coord */ } @@ -2439,6 +2466,49 @@ static void emit_tex(struct brw_wm_compile *c, brw_MOV(p, dst[3], brw_imm_f(1.0)); } + +static void emit_get_constant(struct brw_context *brw, + struct brw_wm_compile *c, + struct prog_instruction *inst, + GLuint constIndex) +{ + struct brw_compile *p = &c->func; + struct brw_reg dst[4]; + GLuint i; + const int mark = mark_tmps( c ); + struct brw_reg writeback_reg[4]; + + /* XXX only need 1 temp reg??? */ + for (i = 0; i < 4; i++) { + writeback_reg[i] = alloc_tmp(c); + } + + for (i = 0; i < 4; i++) { + dst[i] = get_dst_reg(c, inst, i); + } + + /* Get float[4] vector from constant buffer */ + brw_dp_READ_4(p, + writeback_reg[0], /* first writeback dest */ + 1, /* msg_reg */ + GL_FALSE, /* rel addr? */ + 16 * constIndex, /* byte offset */ + BRW_WM_MAX_SURF - 1 /* surface, binding table index */ + ); + + /* Extract the four channel values, smear across dest registers */ + for (i = 0; i < 4; i++) { + /* extract 1 float from the writeback reg */ + struct brw_reg new_src = stride(writeback_reg[0], 0, 1, 0); + new_src.subnr = i * 4; + /* and smear it into the dest register */ + brw_MOV(p, dst[i], new_src); + } + + release_tmps( c, mark ); +} + + /** * Resolve subroutine calls after code emit is done. */ @@ -2504,6 +2574,9 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) case OPCODE_ADD: emit_add(c, inst); break; + case OPCODE_ARL: + emit_arl(c, inst); + break; case OPCODE_SUB: emit_sub(c, inst); break; @@ -2520,7 +2593,17 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) emit_trunc(c, inst); break; case OPCODE_MOV: +#if 0 + /* test hook for new constant buffer code */ + if (inst->SrcReg[0].File == PROGRAM_UNIFORM) { + emit_get_constant(brw, c, inst, inst->SrcReg[0].Index); + } + else { + emit_mov(c, inst); + } +#else emit_mov(c, inst); +#endif break; case OPCODE_DP3: emit_dp3(c, inst); diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 1fc537ca20..e7d55d5dbd 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -33,6 +33,7 @@ #include "main/mtypes.h" #include "main/texformat.h" #include "main/texstore.h" +#include "shader/prog_parameter.h" #include "intel_mipmap_tree.h" #include "intel_batchbuffer.h" @@ -287,6 +288,7 @@ brw_update_texture_surface( GLcontext *ctx, GLuint unit ) struct intel_texture_object *intelObj = intel_texture_object(tObj); struct gl_texture_image *firstImage = tObj->Image[0][intelObj->firstLevel]; struct brw_wm_surface_key key; + const GLuint j = MAX_DRAW_BUFFERS + unit; memset(&key, 0, sizeof(key)); @@ -313,16 +315,111 @@ brw_update_texture_surface( GLcontext *ctx, GLuint unit ) key.cpp = intelObj->mt->cpp; key.tiling = intelObj->mt->region->tiling; - dri_bo_unreference(brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS]); - brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS] = brw_search_cache(&brw->cache, BRW_SS_SURFACE, - &key, sizeof(key), - &key.bo, key.bo ? 1 : 0, - NULL); - if (brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS] == NULL) { - brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS] = brw_create_texture_surface(brw, &key); + dri_bo_unreference(brw->wm.surf_bo[j]); + brw->wm.surf_bo[j] = brw_search_cache(&brw->cache, BRW_SS_SURFACE, + &key, sizeof(key), + &key.bo, key.bo ? 1 : 0, + NULL); + if (brw->wm.surf_bo[j] == NULL) { + brw->wm.surf_bo[j] = brw_create_texture_surface(brw, &key); } } + + +/** + * Create the constant buffer surface. Fragment shader constanst will be + * read from this buffer with Data Port Read instructions/messages. + */ +static dri_bo * +brw_create_constant_surface( struct brw_context *brw, + struct brw_wm_surface_key *key ) +{ + const GLint w = key->width - 1; + struct brw_surface_state surf; + dri_bo *bo; + + memset(&surf, 0, sizeof(surf)); + + surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW; + surf.ss0.surface_type = BRW_SURFACE_BUFFER; + surf.ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT; + + /* This is ok for all textures with channel width 8bit or less: + */ + assert(key->bo); + if (key->bo) + surf.ss1.base_addr = key->bo->offset; /* reloc */ + else + surf.ss1.base_addr = key->offset; + + surf.ss2.width = w & 0x7f; /* bits 6:0 of size or width */ + surf.ss2.height = (w >> 7) & 0x1fff; /* bits 19:7 of size or width */ + surf.ss3.depth = (w >> 20) & 0x7f; /* bits 26:20 of size or width */ + surf.ss3.pitch = (key->pitch * key->cpp) - 1; + brw_set_surface_tiling(&surf, key->tiling); + + bo = brw_upload_cache(&brw->cache, BRW_SS_SURFACE, + key, sizeof(*key), + &key->bo, key->bo ? 1 : 0, + &surf, sizeof(surf), + NULL, NULL); + + if (key->bo) { + /* Emit relocation to surface contents */ + dri_bo_emit_reloc(bo, + I915_GEM_DOMAIN_SAMPLER, 0, + 0, + offsetof(struct brw_surface_state, ss1), + key->bo); + } + + return bo; +} + + +/** + * Update the constant buffer surface. + */ +static void +brw_update_constant_surface( GLcontext *ctx, + const struct brw_fragment_program *fp ) +{ + struct brw_context *brw = brw_context(ctx); + struct brw_wm_surface_key key; + const GLuint j = BRW_WM_MAX_SURF - 1; + const GLuint numParams = fp->program.Base.Parameters->NumParameters; + + memset(&key, 0, sizeof(key)); + + key.format = MESA_FORMAT_RGBA_FLOAT32; + key.internal_format = GL_RGBA; + key.bo = fp->const_buffer; + + key.depthmode = GL_NONE; + key.pitch = numParams; + key.width = numParams; + key.height = 1; + key.depth = 1; + key.cpp = 16; + + /* + printf("%s:\n", __FUNCTION__); + printf(" width %d height %d depth %d cpp %d pitch %d\n", + key.width, key.height, key.depth, key.cpp, key.pitch); + */ + + dri_bo_unreference(brw->wm.surf_bo[j]); + brw->wm.surf_bo[j] = brw_search_cache(&brw->cache, BRW_SS_SURFACE, + &key, sizeof(key), + &key.bo, key.bo ? 1 : 0, + NULL); + if (brw->wm.surf_bo[j] == NULL) { + brw->wm.surf_bo[j] = brw_create_constant_surface(brw, &key); + } +} + + /** * Sets up a surface state structure to point at the given region. * While it is only used for the front/back buffer currently, it should be @@ -514,6 +611,17 @@ static void prepare_wm_surfaces(struct brw_context *brw ) } } + /* Update surface for fragment shader constant buffer */ + { + const GLuint j = BRW_WM_MAX_SURF - 1; + const struct brw_fragment_program *fp = + brw_fragment_program_const(brw->fragment_program); + + brw_update_constant_surface(ctx, fp); + brw->wm.nr_surfaces = j + 1; + } + + dri_bo_unreference(brw->wm.bind_bo); brw->wm.bind_bo = brw_wm_get_binding_table(brw); -- cgit v1.2.3 From 34239862430aa38b0b1b6740c47d66f7260ae3e4 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Wed, 1 Apr 2009 12:25:34 -0600 Subject: i965: change args to get_src_reg() to prep for new constant buffer support --- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 164 +++++++++++++++++--------------- 1 file changed, 85 insertions(+), 79 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 28ef84e4aa..41db3a805b 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -254,7 +254,8 @@ static void prealloc_reg(struct brw_wm_compile *c) * Convert Mesa dst register to brw register. */ static struct brw_reg get_dst_reg(struct brw_wm_compile *c, - struct prog_instruction *inst, int component) + const struct prog_instruction *inst, + GLuint component) { const int nr = 1; return get_reg(c, inst->DstReg.File, inst->DstReg.Index, component, nr, @@ -266,10 +267,13 @@ static struct brw_reg get_dst_reg(struct brw_wm_compile *c, * Convert Mesa src register to brw register. */ static struct brw_reg get_src_reg(struct brw_wm_compile *c, - struct prog_src_register *src, int index) + const struct prog_instruction *inst, + GLuint srcRegIndex, GLuint channel) { - const int nr = 1; - int component = GET_SWZ(src->Swizzle, index); + const struct prog_src_register *src = &inst->SrcReg[srcRegIndex]; + const GLuint nr = 1; + const GLuint component = GET_SWZ(src->Swizzle, channel); + return get_reg(c, src->File, src->Index, component, nr, src->NegateBase, src->Abs); } @@ -282,11 +286,13 @@ static struct brw_reg get_src_reg(struct brw_wm_compile *c, * For instructions with more than one operand, only the second can be a literal. */ static struct brw_reg get_src_reg_imm(struct brw_wm_compile *c, - struct prog_src_register *src, int index) + const struct prog_instruction *inst, + GLuint srcRegIndex, GLuint channel) { + const struct prog_src_register *src = &inst->SrcReg[srcRegIndex]; if (src->File == PROGRAM_CONSTANT) { /* a literal */ - const int component = GET_SWZ(src->Swizzle, index); + const int component = GET_SWZ(src->Swizzle, channel); const GLfloat *param = c->fp->program.Base.Parameters->ParameterValues[src->Index]; GLfloat value = param[component]; @@ -297,7 +303,7 @@ static struct brw_reg get_src_reg_imm(struct brw_wm_compile *c, return brw_imm_f(value); } else { - return get_src_reg(c, src, index); + return get_src_reg(c, inst, srcRegIndex, channel); } } @@ -376,7 +382,7 @@ static void emit_abs( struct brw_wm_compile *c, if (inst->DstReg.WriteMask & (1<SrcReg[0], i); + src = get_src_reg(c, inst, 0, i); brw_MOV(p, dst, brw_abs(src)); } } @@ -394,7 +400,7 @@ static void emit_trunc( struct brw_wm_compile *c, if (mask & (1<SrcReg[0], i); + src = get_src_reg(c, inst, 0, i); brw_RNDZ(p, dst, src); } } @@ -412,7 +418,7 @@ static void emit_mov( struct brw_wm_compile *c, if (mask & (1<SrcReg[0], i); + src = get_src_reg_imm(c, inst, 0, i); brw_MOV(p, dst, src); } } @@ -459,8 +465,8 @@ static void emit_delta_xy(struct brw_wm_compile *c, dst0 = get_dst_reg(c, inst, 0); dst1 = get_dst_reg(c, inst, 1); - src0 = get_src_reg(c, &inst->SrcReg[0], 0); - src1 = get_src_reg(c, &inst->SrcReg[0], 1); + src0 = get_src_reg(c, inst, 0, 0); + src1 = get_src_reg(c, inst, 0, 1); /* Calc delta X,Y by subtracting origin in r1 from the pixel * centers. */ @@ -525,7 +531,7 @@ static void emit_fb_write(struct brw_wm_compile *c, brw_push_insn_state(p); for (channel = 0; channel < 4; channel++) { - src0 = get_src_reg(c, &inst->SrcReg[0], channel); + src0 = get_src_reg(c, inst, 0, channel); /* mov (8) m2.0<1>:ud r28.0<8;8,1>:ud { Align1 } */ /* mov (8) m6.0<1>:ud r29.0<8;8,1>:ud { Align1 SecHalf } */ brw_MOV(p, brw_message_reg(nr + channel), src0); @@ -536,11 +542,11 @@ static void emit_fb_write(struct brw_wm_compile *c, if (c->key.source_depth_to_render_target) { if (c->key.computes_depth) { - src0 = get_src_reg(c, &inst->SrcReg[2], 2); + src0 = get_src_reg(c, inst, 2, 2); brw_MOV(p, brw_message_reg(nr), src0); } else { - src0 = get_src_reg(c, &inst->SrcReg[1], 1); + src0 = get_src_reg(c, inst, 1, 1); brw_MOV(p, brw_message_reg(nr), src0); } @@ -567,7 +573,7 @@ static void emit_fb_write(struct brw_wm_compile *c, else #endif { - struct brw_reg src = get_src_reg(c, &inst->SrcReg[1], 1); + struct brw_reg src = get_src_reg(c, inst, 1, 1); brw_MOV(p, brw_message_reg(nr), src); } nr += 2; @@ -588,9 +594,9 @@ static void emit_pixel_w( struct brw_wm_compile *c, struct brw_reg interp3; dst = get_dst_reg(c, inst, 3); - src0 = get_src_reg(c, &inst->SrcReg[0], 0); - delta0 = get_src_reg(c, &inst->SrcReg[1], 0); - delta1 = get_src_reg(c, &inst->SrcReg[1], 1); + src0 = get_src_reg(c, inst, 0, 0); + delta0 = get_src_reg(c, inst, 1, 0); + delta1 = get_src_reg(c, inst, 1, 1); interp3 = brw_vec1_grf(src0.nr+1, 4); /* Calc 1/w - just linterp wpos[3] optimized by putting the @@ -618,9 +624,9 @@ static void emit_linterp(struct brw_wm_compile *c, struct brw_reg src0; GLuint nr, i; - src0 = get_src_reg(c, &inst->SrcReg[0], 0); - delta0 = get_src_reg(c, &inst->SrcReg[1], 0); - delta1 = get_src_reg(c, &inst->SrcReg[1], 1); + src0 = get_src_reg(c, inst, 0, 0); + delta0 = get_src_reg(c, inst, 1, 0); + delta1 = get_src_reg(c, inst, 1, 1); nr = src0.nr; interp[0] = brw_vec1_grf(nr, 0); @@ -647,7 +653,7 @@ static void emit_cinterp(struct brw_wm_compile *c, struct brw_reg dst, src0; GLuint nr, i; - src0 = get_src_reg(c, &inst->SrcReg[0], 0); + src0 = get_src_reg(c, inst, 0, 0); nr = src0.nr; interp[0] = brw_vec1_grf(nr, 0); @@ -674,10 +680,10 @@ static void emit_pinterp(struct brw_wm_compile *c, struct brw_reg src0, w; GLuint nr, i; - src0 = get_src_reg(c, &inst->SrcReg[0], 0); - delta0 = get_src_reg(c, &inst->SrcReg[1], 0); - delta1 = get_src_reg(c, &inst->SrcReg[1], 1); - w = get_src_reg(c, &inst->SrcReg[2], 3); + src0 = get_src_reg(c, inst, 0, 0); + delta0 = get_src_reg(c, inst, 1, 0); + delta1 = get_src_reg(c, inst, 1, 1); + w = get_src_reg(c, inst, 2, 3); nr = src0.nr; interp[0] = brw_vec1_grf(nr, 0); @@ -738,11 +744,11 @@ static void emit_xpd(struct brw_wm_compile *c, if (mask & (1<SrcReg[0], i2)); - src1 = get_src_reg_imm(c, &inst->SrcReg[1], i1); + src0 = negate(get_src_reg(c, inst, 0, i2)); + src1 = get_src_reg_imm(c, inst, 1, i1); brw_MUL(p, brw_null_reg(), src0, src1); - src0 = get_src_reg(c, &inst->SrcReg[0], i1); - src1 = get_src_reg_imm(c, &inst->SrcReg[1], i2); + src0 = get_src_reg(c, inst, 0, i1); + src1 = get_src_reg_imm(c, inst, 1, i2); brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF); brw_MAC(p, dst, src0, src1); brw_set_saturate(p, 0); @@ -758,8 +764,8 @@ static void emit_dp3(struct brw_wm_compile *c, int i; struct brw_compile *p = &c->func; for (i = 0; i < 3; i++) { - src0[i] = get_src_reg(c, &inst->SrcReg[0], i); - src1[i] = get_src_reg_imm(c, &inst->SrcReg[1], i); + src0[i] = get_src_reg(c, inst, 0, i); + src1[i] = get_src_reg_imm(c, inst, 1, i); } dst = get_dst_reg(c, inst, get_scalar_dst_index(inst)); @@ -777,8 +783,8 @@ static void emit_dp4(struct brw_wm_compile *c, int i; struct brw_compile *p = &c->func; for (i = 0; i < 4; i++) { - src0[i] = get_src_reg(c, &inst->SrcReg[0], i); - src1[i] = get_src_reg_imm(c, &inst->SrcReg[1], i); + src0[i] = get_src_reg(c, inst, 0, i); + src1[i] = get_src_reg_imm(c, inst, 1, i); } dst = get_dst_reg(c, inst, get_scalar_dst_index(inst)); brw_MUL(p, brw_null_reg(), src0[0], src1[0]); @@ -796,8 +802,8 @@ static void emit_dph(struct brw_wm_compile *c, int i; struct brw_compile *p = &c->func; for (i = 0; i < 4; i++) { - src0[i] = get_src_reg(c, &inst->SrcReg[0], i); - src1[i] = get_src_reg_imm(c, &inst->SrcReg[1], i); + src0[i] = get_src_reg(c, inst, 0, i); + src1[i] = get_src_reg_imm(c, inst, 1, i); } dst = get_dst_reg(c, inst, get_scalar_dst_index(inst)); brw_MUL(p, brw_null_reg(), src0[0], src1[0]); @@ -824,7 +830,7 @@ static void emit_math1(struct brw_wm_compile *c, tmp = alloc_tmp(c); /* Get first component of source register */ - src0 = get_src_reg(c, &inst->SrcReg[0], 0); + src0 = get_src_reg(c, inst, 0, 0); /* tmp = func(src0) */ brw_MOV(p, brw_message_reg(2), src0); @@ -897,8 +903,8 @@ static void emit_add(struct brw_wm_compile *c, for (i = 0 ; i < 4; i++) { if (mask & (1<SrcReg[0], i); - src1 = get_src_reg_imm(c, &inst->SrcReg[1], i); + src0 = get_src_reg(c, inst, 0, i); + src1 = get_src_reg_imm(c, inst, 1, i); brw_ADD(p, dst, src0, src1); } } @@ -913,7 +919,7 @@ static void emit_arl(struct brw_wm_compile *c, brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); addr_reg = brw_uw8_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_ADDRESS, 0); - src0 = get_src_reg(c, &inst->SrcReg[0], 0); /* channel 0 */ + src0 = get_src_reg(c, inst, 0, 0); /* channel 0 */ brw_MOV(p, addr_reg, src0); brw_set_saturate(p, 0); } @@ -929,8 +935,8 @@ static void emit_sub(struct brw_wm_compile *c, for (i = 0 ; i < 4; i++) { if (mask & (1<SrcReg[0], i); - src1 = get_src_reg_imm(c, &inst->SrcReg[1], i); + src0 = get_src_reg(c, inst, 0, i); + src1 = get_src_reg_imm(c, inst, 1, i); brw_ADD(p, dst, src0, negate(src1)); } } @@ -948,8 +954,8 @@ static void emit_mul(struct brw_wm_compile *c, for (i = 0 ; i < 4; i++) { if (mask & (1<SrcReg[0], i); - src1 = get_src_reg_imm(c, &inst->SrcReg[1], i); + src0 = get_src_reg(c, inst, 0, i); + src1 = get_src_reg_imm(c, inst, 1, i); brw_MUL(p, dst, src0, src1); } } @@ -967,7 +973,7 @@ static void emit_frc(struct brw_wm_compile *c, for (i = 0 ; i < 4; i++) { if (mask & (1<SrcReg[0], i); + src0 = get_src_reg_imm(c, inst, 0, i); brw_FRC(p, dst, src0); } } @@ -986,7 +992,7 @@ static void emit_flr(struct brw_wm_compile *c, for (i = 0 ; i < 4; i++) { if (mask & (1<SrcReg[0], i); + src0 = get_src_reg_imm(c, inst, 0, i); brw_RNDD(p, dst, src0); } } @@ -1004,8 +1010,8 @@ static void emit_max(struct brw_wm_compile *c, for (i = 0; i < 4; i++) { if (mask & (1<SrcReg[0], i); - src1 = get_src_reg_imm(c, &inst->SrcReg[1], i); + src0 = get_src_reg(c, inst, 0, i); + src1 = get_src_reg_imm(c, inst, 1, i); brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); brw_MOV(p, dst, src0); brw_set_saturate(p, 0); @@ -1032,8 +1038,8 @@ static void emit_min(struct brw_wm_compile *c, for (i = 0; i < 4; i++) { if (mask & (1<SrcReg[0], i); - src1 = get_src_reg(c, &inst->SrcReg[1], i); + src0 = get_src_reg_imm(c, inst, 0, i); + src1 = get_src_reg(c, inst, 1, i); brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); brw_MOV(p, dst, src0); brw_set_saturate(p, 0); @@ -1055,8 +1061,8 @@ static void emit_pow(struct brw_wm_compile *c, struct brw_compile *p = &c->func; struct brw_reg dst, src0, src1; dst = get_dst_reg(c, inst, get_scalar_dst_index(inst)); - src0 = get_src_reg_imm(c, &inst->SrcReg[0], 0); - src1 = get_src_reg_imm(c, &inst->SrcReg[1], 0); + src0 = get_src_reg_imm(c, inst, 0, 0); + src1 = get_src_reg_imm(c, inst, 1, 0); brw_MOV(p, brw_message_reg(2), src0); brw_MOV(p, brw_message_reg(3), src1); @@ -1082,9 +1088,9 @@ static void emit_lrp(struct brw_wm_compile *c, for (i = 0; i < 4; i++) { if (mask & (1<SrcReg[0], i); + src0 = get_src_reg(c, inst, 0, i); - src1 = get_src_reg_imm(c, &inst->SrcReg[1], i); + src1 = get_src_reg_imm(c, inst, 1, i); if (src1.nr == dst.nr) { tmp1 = alloc_tmp(c); @@ -1092,7 +1098,7 @@ static void emit_lrp(struct brw_wm_compile *c, } else tmp1 = src1; - src2 = get_src_reg(c, &inst->SrcReg[2], i); + src2 = get_src_reg(c, inst, 2, i); if (src2.nr == dst.nr) { tmp2 = alloc_tmp(c); brw_MOV(p, tmp2, src2); @@ -1135,9 +1141,9 @@ static void emit_mad(struct brw_wm_compile *c, for (i = 0; i < 4; i++) { if (mask & (1<SrcReg[0], i); - src1 = get_src_reg_imm(c, &inst->SrcReg[1], i); - src2 = get_src_reg_imm(c, &inst->SrcReg[2], i); + src0 = get_src_reg(c, inst, 0, i); + src1 = get_src_reg_imm(c, inst, 1, i); + src2 = get_src_reg_imm(c, inst, 2, i); brw_MUL(p, dst, src0, src1); brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); @@ -1158,8 +1164,8 @@ static void emit_sop(struct brw_wm_compile *c, for (i = 0; i < 4; i++) { if (mask & (1<SrcReg[0], i); - src1 = get_src_reg_imm(c, &inst->SrcReg[1], i); + src0 = get_src_reg(c, inst, 0, i); + src1 = get_src_reg_imm(c, inst, 1, i); brw_push_insn_state(p); brw_CMP(p, brw_null_reg(), cond, src0, src1); brw_set_predicate_control(p, BRW_PREDICATE_NONE); @@ -1216,8 +1222,8 @@ static void emit_ddx(struct brw_wm_compile *c, struct brw_reg dst; struct brw_reg src0, w; GLuint nr, i; - src0 = get_src_reg(c, &inst->SrcReg[0], 0); - w = get_src_reg(c, &inst->SrcReg[1], 3); + src0 = get_src_reg(c, inst, 0, 0); + w = get_src_reg(c, inst, 1, 3); nr = src0.nr; interp[0] = brw_vec1_grf(nr, 0); interp[1] = brw_vec1_grf(nr, 4); @@ -1244,9 +1250,9 @@ static void emit_ddy(struct brw_wm_compile *c, struct brw_reg src0, w; GLuint nr, i; - src0 = get_src_reg(c, &inst->SrcReg[0], 0); + src0 = get_src_reg(c, inst, 0, 0); nr = src0.nr; - w = get_src_reg(c, &inst->SrcReg[1], 3); + w = get_src_reg(c, inst, 1, 3); interp[0] = brw_vec1_grf(nr, 0); interp[1] = brw_vec1_grf(nr, 4); interp[2] = brw_vec1_grf(nr+1, 0); @@ -1388,7 +1394,7 @@ static void emit_noise1( struct brw_wm_compile *c, assert( mark == 0 ); - src = get_src_reg( c, inst->SrcReg, 0 ); + src = get_src_reg( c, inst, 0, 0 ); param = alloc_tmp( c ); @@ -1558,8 +1564,8 @@ static void emit_noise2( struct brw_wm_compile *c, assert( mark == 0 ); - src0 = get_src_reg( c, inst->SrcReg, 0 ); - src1 = get_src_reg( c, inst->SrcReg, 1 ); + src0 = get_src_reg( c, inst, 0, 0 ); + src1 = get_src_reg( c, inst, 0, 1 ); param0 = alloc_tmp( c ); param1 = alloc_tmp( c ); @@ -1861,9 +1867,9 @@ static void emit_noise3( struct brw_wm_compile *c, assert( mark == 0 ); - src0 = get_src_reg( c, inst->SrcReg, 0 ); - src1 = get_src_reg( c, inst->SrcReg, 1 ); - src2 = get_src_reg( c, inst->SrcReg, 2 ); + src0 = get_src_reg( c, inst, 0, 0 ); + src1 = get_src_reg( c, inst, 0, 1 ); + src2 = get_src_reg( c, inst, 0, 2 ); param0 = alloc_tmp( c ); param1 = alloc_tmp( c ); @@ -2284,10 +2290,10 @@ static void emit_noise4( struct brw_wm_compile *c, assert( mark == 0 ); - src0 = get_src_reg( c, inst->SrcReg, 0 ); - src1 = get_src_reg( c, inst->SrcReg, 1 ); - src2 = get_src_reg( c, inst->SrcReg, 2 ); - src3 = get_src_reg( c, inst->SrcReg, 3 ); + src0 = get_src_reg( c, inst, 0, 0 ); + src1 = get_src_reg( c, inst, 0, 1 ); + src2 = get_src_reg( c, inst, 0, 2 ); + src3 = get_src_reg( c, inst, 0, 3 ); param0 = alloc_tmp( c ); param1 = alloc_tmp( c ); @@ -2325,8 +2331,8 @@ static void emit_wpos_xy(struct brw_wm_compile *c, dst[0] = get_dst_reg(c, inst, 0); dst[1] = get_dst_reg(c, inst, 1); - src0[0] = get_src_reg(c, &inst->SrcReg[0], 0); - src0[1] = get_src_reg(c, &inst->SrcReg[0], 1); + src0[0] = get_src_reg(c, inst, 0, 0); + src0[1] = get_src_reg(c, inst, 0, 1); /* Calculate the pixel offset from window bottom left into destination * X and Y channels. @@ -2364,7 +2370,7 @@ static void emit_txb(struct brw_wm_compile *c, for (i = 0; i < 4; i++) dst[i] = get_dst_reg(c, inst, i); for (i = 0; i < 4; i++) - src[i] = get_src_reg(c, &inst->SrcReg[0], i); + src[i] = get_src_reg(c, inst, 0, i); switch (inst->TexSrcTarget) { case TEXTURE_1D_INDEX: @@ -2416,7 +2422,7 @@ static void emit_tex(struct brw_wm_compile *c, for (i = 0; i < 4; i++) dst[i] = get_dst_reg(c, inst, i); for (i = 0; i < 4; i++) - src[i] = get_src_reg(c, &inst->SrcReg[0], i); + src[i] = get_src_reg(c, inst, 0, i); switch (inst->TexSrcTarget) { case TEXTURE_1D_INDEX: -- cgit v1.2.3 From 30adf0518168ded9c7f519a7c772cab728852b1f Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Wed, 1 Apr 2009 12:57:06 -0600 Subject: i965: fix response length param in brw_dp_READ_4() We were accidentally clobbering the next register. --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index b149f0f21f..c58c455410 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -994,7 +994,7 @@ void brw_dp_READ_4( struct brw_compile *p, BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, /* msg_type */ 0, /* source cache = data cache */ 1, /* msg_length */ - 2, /* response_length */ + 1, /* response_length (1 Oword) */ 0); /* eot */ } } -- cgit v1.2.3 From 1e299ff828e808cbb1d92d9fedd528a3a8a3609e Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Wed, 1 Apr 2009 13:36:48 -0600 Subject: i965: another checkpoint commit of new constant buffer support Everything is in place now for using a true constant buffer for GLSL fragment shaders. Still some bugs to find though. --- src/mesa/drivers/dri/i965/brw_wm.h | 8 ++ src/mesa/drivers/dri/i965/brw_wm_glsl.c | 172 ++++++++++++++++++++------------ 2 files changed, 115 insertions(+), 65 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index 98c22121ec..d0ab3bdc65 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -253,6 +253,14 @@ struct brw_wm_compile { GLuint tmp_index; GLuint tmp_max; GLuint subroutines[BRW_WM_MAX_SUBROUTINE]; + + /** using a real constant buffer? */ + GLboolean use_const_buffer; + /** we may need up to 3 constants per instruction (if use_const_buffer) */ + struct { + GLint index; + struct brw_reg reg; + } current_const[3]; }; diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 41db3a805b..01d1f7f0c2 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -193,7 +193,19 @@ static void prealloc_reg(struct brw_wm_compile *c) { const int nr_params = c->fp->program.Base.Parameters->NumParameters; - if (1 /* XXX threshold: nr_params <= 8 */) { + /* use a real constant buffer, or just use a section of the GRF? */ + c->use_const_buffer = GL_FALSE; /* (nr_params > 8);*/ + /*printf("USE CONST BUFFER? %d\n", c->use_const_buffer);*/ + + if (c->use_const_buffer) { + /* We'll use a real constant buffer and fetch constants from + * it with a dataport read message. + */ + + /* number of float constants in CURBE */ + c->prog_data.nr_params = 0; + } + else { const struct gl_program_parameter_list *plist = c->fp->program.Base.Parameters; int index = 0; @@ -217,16 +229,6 @@ static void prealloc_reg(struct brw_wm_compile *c) c->nr_creg = 2 * ((4 * nr_params + 15) / 16); c->reg_index += c->nr_creg; } - else { - /* number of float constants in CURBE */ - c->prog_data.nr_params = 0; - - /* When there's a lot of FP constanst we'll store them in a - * texture-like buffer instead of using the CURBE buffer. - * This means we won't use GRF registers for constants and we'll - * have to fetch constants with a dataport read. - */ - } } /* fragment shader inputs */ @@ -247,6 +249,49 @@ static void prealloc_reg(struct brw_wm_compile *c) c->reg_index++; c->stack = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, c->reg_index, 0); c->reg_index += 2; + + /* An instruction may reference up to three constants. + * They'll be found in these registers. + * XXX alloc these on demand! + */ + if (c->use_const_buffer) { + c->current_const[0].reg = alloc_tmp(c); + c->current_const[1].reg = alloc_tmp(c); + c->current_const[2].reg = alloc_tmp(c); + } + /*printf("AFTER PRE_ALLOC, reg_index = %d\n", c->reg_index);*/ +} + + +/** + * Check if any of the instruction's src registers are constants, uniforms, + * or statevars. If so, fetch any constants that we don't already have in + * the three GRF slots. + */ +static void fetch_constants(struct brw_wm_compile *c, + const struct prog_instruction *inst) +{ + struct brw_compile *p = &c->func; + GLuint i; + + /* loop over instruction src regs */ + for (i = 0; i < 3; i++) { + const struct prog_src_register *src = &inst->SrcReg[i]; + if (src->File == PROGRAM_STATE_VAR || + src->File == PROGRAM_UNIFORM) { + if (c->current_const[i].index != src->Index) { + /* need to fetch the constant now */ + brw_dp_READ_4(p, + c->current_const[i].reg, /* writeback dest */ + 1, /* msg_reg */ + src->RelAddr, /* relative indexing? */ + 16 * src->Index, /* byte offset */ + BRW_WM_MAX_SURF - 1 /* binding table index */ + ); + c->current_const[i].index = src->Index; + } + } + } } @@ -263,6 +308,43 @@ static struct brw_reg get_dst_reg(struct brw_wm_compile *c, } +static struct brw_reg +get_src_reg_const(struct brw_wm_compile *c, + const struct prog_instruction *inst, + GLuint srcRegIndex, GLuint component) +{ + /* We should have already fetched the constant from the constant + * buffer in fetch_constants(). Now we just have to return a + * register description that extracts the needed component and + * smears it across all eight vector components. + */ + const struct prog_src_register *src = &inst->SrcReg[srcRegIndex]; + struct brw_reg const_reg; + + assert(srcRegIndex < 3); + assert(c->current_const[srcRegIndex].index != -1); + const_reg = c->current_const[srcRegIndex].reg; + + /* + printf("get const reg %d in slot %d, comp %d\n", + c->current_const[srcRegIndex].index, + srcRegIndex, + component); + */ + + /* extract desired float from the const_reg, and smear */ + const_reg = stride(const_reg, 0, 1, 0); + const_reg.subnr = component * 4; + + if (src->NegateBase) + const_reg = negate(const_reg); + if (src->Abs) + const_reg = brw_abs(const_reg); + + return const_reg; +} + + /** * Convert Mesa src register to brw register. */ @@ -274,8 +356,16 @@ static struct brw_reg get_src_reg(struct brw_wm_compile *c, const GLuint nr = 1; const GLuint component = GET_SWZ(src->Swizzle, channel); - return get_reg(c, src->File, src->Index, component, nr, - src->NegateBase, src->Abs); + if (c->use_const_buffer && + (src->File == PROGRAM_STATE_VAR || + src->File == PROGRAM_UNIFORM)) { + return get_src_reg_const(c, inst, srcRegIndex, component); + } + else { + /* other type of source register */ + return get_reg(c, src->File, src->Index, component, nr, + src->NegateBase, src->Abs); + } } @@ -2473,48 +2563,6 @@ static void emit_tex(struct brw_wm_compile *c, } -static void emit_get_constant(struct brw_context *brw, - struct brw_wm_compile *c, - struct prog_instruction *inst, - GLuint constIndex) -{ - struct brw_compile *p = &c->func; - struct brw_reg dst[4]; - GLuint i; - const int mark = mark_tmps( c ); - struct brw_reg writeback_reg[4]; - - /* XXX only need 1 temp reg??? */ - for (i = 0; i < 4; i++) { - writeback_reg[i] = alloc_tmp(c); - } - - for (i = 0; i < 4; i++) { - dst[i] = get_dst_reg(c, inst, i); - } - - /* Get float[4] vector from constant buffer */ - brw_dp_READ_4(p, - writeback_reg[0], /* first writeback dest */ - 1, /* msg_reg */ - GL_FALSE, /* rel addr? */ - 16 * constIndex, /* byte offset */ - BRW_WM_MAX_SURF - 1 /* surface, binding table index */ - ); - - /* Extract the four channel values, smear across dest registers */ - for (i = 0; i < 4; i++) { - /* extract 1 float from the writeback reg */ - struct brw_reg new_src = stride(writeback_reg[0], 0, 1, 0); - new_src.subnr = i * 4; - /* and smear it into the dest register */ - brw_MOV(p, dst[i], new_src); - } - - release_tmps( c, mark ); -} - - /** * Resolve subroutine calls after code emit is done. */ @@ -2546,6 +2594,10 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) else brw_set_conditionalmod(p, BRW_CONDITIONAL_NONE); + /* fetch any constants that this instruction needs */ + if (c->use_const_buffer) + fetch_constants(c, inst); + switch (inst->Opcode) { case WM_PIXELXY: emit_pixel_xy(c, inst); @@ -2599,17 +2651,7 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) emit_trunc(c, inst); break; case OPCODE_MOV: -#if 0 - /* test hook for new constant buffer code */ - if (inst->SrcReg[0].File == PROGRAM_UNIFORM) { - emit_get_constant(brw, c, inst, inst->SrcReg[0].Index); - } - else { - emit_mov(c, inst); - } -#else emit_mov(c, inst); -#endif break; case OPCODE_DP3: emit_dp3(c, inst); -- cgit v1.2.3 From a330a6fcd0b018829194ffab260f50956bce4832 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Thu, 2 Apr 2009 11:45:17 -0600 Subject: i965: s/GL_FALSE/BRW_COMPRESSION_NONE/ --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index c58c455410..21ce8369db 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -1127,7 +1127,7 @@ void brw_SAMPLE(struct brw_compile *p, /* mov (8) r9.0<1>:f r9.0<8;8,1>:f { Align1 } */ brw_push_insn_state(p); - brw_set_compression_control(p, GL_FALSE); + brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_MOV(p, reg, reg); brw_pop_insn_state(p); } -- cgit v1.2.3 From 21982a2cd597aeb22d7ee2bd3a5067c58f97ca6f Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Thu, 2 Apr 2009 14:33:45 -0600 Subject: i965: added brw_same_reg() --- src/mesa/drivers/dri/i965/brw_eu.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index c94889ab1c..d05f2e6c41 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -730,6 +730,13 @@ static INLINE struct brw_indirect brw_indirect( GLuint addr_subnr, GLint offset return ptr; } +/** Do two brw_regs refer to the same register? */ +static INLINE GLboolean +brw_same_reg(struct brw_reg r1, struct brw_reg r2) +{ + return r1.file == r2.file && r1.nr == r2.nr; +} + static INLINE struct brw_instruction *current_insn( struct brw_compile *p) { return &p->store[p->nr_insn]; -- cgit v1.2.3 From 0139637975ec210b28b593722eda85c68c89c70d Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Fri, 3 Apr 2009 08:59:38 -0600 Subject: i965: more const buffer debug code --- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 134 ++++++++++++++++++++------------ 1 file changed, 84 insertions(+), 50 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 01d1f7f0c2..575cd45d57 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -195,7 +195,6 @@ static void prealloc_reg(struct brw_wm_compile *c) /* use a real constant buffer, or just use a section of the GRF? */ c->use_const_buffer = GL_FALSE; /* (nr_params > 8);*/ - /*printf("USE CONST BUFFER? %d\n", c->use_const_buffer);*/ if (c->use_const_buffer) { /* We'll use a real constant buffer and fetch constants from @@ -259,7 +258,10 @@ static void prealloc_reg(struct brw_wm_compile *c) c->current_const[1].reg = alloc_tmp(c); c->current_const[2].reg = alloc_tmp(c); } - /*printf("AFTER PRE_ALLOC, reg_index = %d\n", c->reg_index);*/ + /* + printf("USE CONST BUFFER? %d\n", c->use_const_buffer); + printf("AFTER PRE_ALLOC, reg_index = %d\n", c->reg_index); + */ } @@ -278,8 +280,18 @@ static void fetch_constants(struct brw_wm_compile *c, for (i = 0; i < 3; i++) { const struct prog_src_register *src = &inst->SrcReg[i]; if (src->File == PROGRAM_STATE_VAR || + src->File == PROGRAM_CONSTANT || src->File == PROGRAM_UNIFORM) { if (c->current_const[i].index != src->Index) { + + c->current_const[i].index = src->Index; + /*c->current_const[i].reg = alloc_tmp(c);*/ + + /* + printf(" fetch const[%d] for arg %d into reg %d\n", + src->Index, i, c->current_const[i].reg.nr); + */ + /* need to fetch the constant now */ brw_dp_READ_4(p, c->current_const[i].reg, /* writeback dest */ @@ -288,7 +300,26 @@ static void fetch_constants(struct brw_wm_compile *c, 16 * src->Index, /* byte offset */ BRW_WM_MAX_SURF - 1 /* binding table index */ ); - c->current_const[i].index = src->Index; + +#if 0 + /* dependency stall */ + { + int response_length = 1; + int mark = mark_tmps( c ); + struct brw_reg src = c->current_const[i].reg; + struct brw_reg tmp = alloc_tmp(c); + + /* mov (8) r9.0<1>:f r9.0<8;8,1>:f { Align1 } + */ + brw_push_insn_state(p); + brw_set_compression_control(p, BRW_COMPRESSION_NONE); + brw_MOV(p, tmp, src); + brw_MOV(p, src, tmp); + brw_pop_insn_state(p); + + release_tmps( c, mark ); + } +#endif } } } @@ -321,17 +352,11 @@ get_src_reg_const(struct brw_wm_compile *c, const struct prog_src_register *src = &inst->SrcReg[srcRegIndex]; struct brw_reg const_reg; + assert(component < 4); assert(srcRegIndex < 3); assert(c->current_const[srcRegIndex].index != -1); const_reg = c->current_const[srcRegIndex].reg; - /* - printf("get const reg %d in slot %d, comp %d\n", - c->current_const[srcRegIndex].index, - srcRegIndex, - component); - */ - /* extract desired float from the const_reg, and smear */ const_reg = stride(const_reg, 0, 1, 0); const_reg.subnr = component * 4; @@ -341,6 +366,14 @@ get_src_reg_const(struct brw_wm_compile *c, if (src->Abs) const_reg = brw_abs(const_reg); + /* + printf(" form const[%d] for arg %d, comp %d, reg %d\n", + c->current_const[srcRegIndex].index, + srcRegIndex, + component, + const_reg.nr); + */ + return const_reg; } @@ -358,6 +391,7 @@ static struct brw_reg get_src_reg(struct brw_wm_compile *c, if (c->use_const_buffer && (src->File == PROGRAM_STATE_VAR || + src->File == PROGRAM_CONSTANT || src->File == PROGRAM_UNIFORM)) { return get_src_reg_const(c, inst, srcRegIndex, component); } @@ -373,7 +407,10 @@ static struct brw_reg get_src_reg(struct brw_wm_compile *c, * Same as \sa get_src_reg() but if the register is a literal, emit * a brw_reg encoding the literal. * Note that a brw instruction only allows one src operand to be a literal. - * For instructions with more than one operand, only the second can be a literal. + * For instructions with more than one operand, only the second can be a + * literal. This means that we treat some literals as constants/uniforms + * (which why PROGRAM_CONSTANT is checked in fetch_constants()). + * */ static struct brw_reg get_src_reg_imm(struct brw_wm_compile *c, const struct prog_instruction *inst, @@ -390,6 +427,7 @@ static struct brw_reg get_src_reg_imm(struct brw_wm_compile *c, value = -value; if (src->Abs) value = FABSF(value); + /*printf(" form imm reg %f\n", value);*/ return brw_imm_f(value); } else { @@ -1089,60 +1127,53 @@ static void emit_flr(struct brw_wm_compile *c, brw_set_saturate(p, 0); } -static void emit_max(struct brw_wm_compile *c, - struct prog_instruction *inst) -{ - struct brw_compile *p = &c->func; - GLuint mask = inst->DstReg.WriteMask; - struct brw_reg src0, src1, dst; - int i; - brw_push_insn_state(p); - for (i = 0; i < 4; i++) { - if (mask & (1<SaturateMode != SATURATE_OFF) ? 1 : 0); - brw_MOV(p, dst, src0); - brw_set_saturate(p, 0); - - brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, src0, src1); - brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); - brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); - brw_MOV(p, dst, src1); - brw_set_saturate(p, 0); - brw_set_predicate_control_flag_value(p, 0xff); - } - } - brw_pop_insn_state(p); -} -static void emit_min(struct brw_wm_compile *c, - struct prog_instruction *inst) +static void emit_min_max(struct brw_wm_compile *c, + const struct prog_instruction *inst) { struct brw_compile *p = &c->func; - GLuint mask = inst->DstReg.WriteMask; - struct brw_reg src0, src1, dst; + const GLuint mask = inst->DstReg.WriteMask; + const int mark = mark_tmps(c); int i; brw_push_insn_state(p); for (i = 0; i < 4; i++) { if (mask & (1<SaturateMode != SATURATE_OFF) ? 1 : 0); brw_MOV(p, dst, src0); brw_set_saturate(p, 0); - brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, src1, src0); + if (inst->Opcode == OPCODE_MIN) + brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, src1, src0); + else + brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_G, src1, src0); + brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); brw_MOV(p, dst, src1); brw_set_saturate(p, 0); brw_set_predicate_control_flag_value(p, 0xff); + if (use_temp) + brw_MOV(p, real_dst, dst); } } brw_pop_insn_state(p); + release_tmps(c, mark); } static void emit_pow(struct brw_wm_compile *c, @@ -2594,6 +2625,11 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) else brw_set_conditionalmod(p, BRW_CONDITIONAL_NONE); + /* + _mesa_printf("Inst %d: ", i); + _mesa_print_instruction(inst); + */ + /* fetch any constants that this instruction needs */ if (c->use_const_buffer) fetch_constants(c, inst); @@ -2683,11 +2719,9 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) case OPCODE_LG2: emit_lg2(c, inst); break; - case OPCODE_MAX: - emit_max(c, inst); - break; case OPCODE_MIN: - emit_min(c, inst); + case OPCODE_MAX: + emit_min_max(c, inst); break; case OPCODE_DDX: emit_ddx(c, inst); -- cgit v1.2.3 From cbd305394a7a01e12f4a42b2551a154b4d544fe2 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Fri, 3 Apr 2009 09:08:00 -0600 Subject: i965: remove unused var --- src/mesa/drivers/dri/i965/brw_curbe.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c index 39a8610952..a6bfb7507e 100644 --- a/src/mesa/drivers/dri/i965/brw_curbe.c +++ b/src/mesa/drivers/dri/i965/brw_curbe.c @@ -339,7 +339,6 @@ static void prepare_constant_buffer(struct brw_context *brw) static void update_texture_constant_buffer(struct brw_context *brw) { - struct intel_context *intel = &brw->intel; struct brw_fragment_program *fp = (struct brw_fragment_program *) brw->fragment_program; const struct gl_program_parameter_list *params = fp->program.Base.Parameters; -- cgit v1.2.3 From 7391ba1e9d81f15465059db25d1279eefdbeb1a9 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Fri, 3 Apr 2009 10:08:20 -0600 Subject: mesa: rename some gl_light fields to be clearer EyeDirection -> SpotDirection _NormDirection -> _NormSpotDirection --- src/mesa/drivers/dri/r200/r200_state.c | 8 ++++---- src/mesa/drivers/dri/radeon/radeon_lighting.c | 8 ++++---- src/mesa/drivers/dri/radeon/radeon_state.c | 8 ++++---- src/mesa/main/attrib.c | 2 +- src/mesa/main/light.c | 26 +++++++++++++------------- src/mesa/main/mtypes.h | 4 ++-- src/mesa/shader/prog_statevars.c | 4 ++-- src/mesa/tnl/t_rasterpos.c | 2 +- src/mesa/tnl/t_vb_lighttmp.h | 6 +++--- src/mesa/x86/gen_matypes.c | 4 ++-- 10 files changed, 36 insertions(+), 36 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index 0eaaaf69ac..2fcc87c0f5 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -1210,7 +1210,7 @@ void r200UpdateMaterial( GLcontext *ctx ) * _VP_inf_norm * _h_inf_norm * _Position - * _NormDirection + * _NormSpotDirection * _ModelViewInvScale * _NeedEyeCoords * _EyeZDir @@ -1267,9 +1267,9 @@ static void update_light( GLcontext *ctx ) fcmd[LIT_DIRECTION_W] = 0; } else { COPY_4V( &fcmd[LIT_POSITION_X], l->_Position ); - fcmd[LIT_DIRECTION_X] = -l->_NormDirection[0]; - fcmd[LIT_DIRECTION_Y] = -l->_NormDirection[1]; - fcmd[LIT_DIRECTION_Z] = -l->_NormDirection[2]; + fcmd[LIT_DIRECTION_X] = -l->_NormSpotDirection[0]; + fcmd[LIT_DIRECTION_Y] = -l->_NormSpotDirection[1]; + fcmd[LIT_DIRECTION_Z] = -l->_NormSpotDirection[2]; fcmd[LIT_DIRECTION_W] = 0; } diff --git a/src/mesa/drivers/dri/radeon/radeon_lighting.c b/src/mesa/drivers/dri/radeon/radeon_lighting.c index 6d9ccfa24d..ac3b94e4a6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_lighting.c +++ b/src/mesa/drivers/dri/radeon/radeon_lighting.c @@ -246,7 +246,7 @@ void radeonUpdateMaterial( GLcontext *ctx ) * _VP_inf_norm * _h_inf_norm * _Position - * _NormDirection + * _NormSpotDirection * _ModelViewInvScale * _NeedEyeCoords * _EyeZDir @@ -308,9 +308,9 @@ void radeonUpdateLighting( GLcontext *ctx ) fcmd[LIT_DIRECTION_W] = 0; } else { COPY_4V( &fcmd[LIT_POSITION_X], l->_Position ); - fcmd[LIT_DIRECTION_X] = -l->_NormDirection[0]; - fcmd[LIT_DIRECTION_Y] = -l->_NormDirection[1]; - fcmd[LIT_DIRECTION_Z] = -l->_NormDirection[2]; + fcmd[LIT_DIRECTION_X] = -l->_NormSpotDirection[0]; + fcmd[LIT_DIRECTION_Y] = -l->_NormSpotDirection[1]; + fcmd[LIT_DIRECTION_Z] = -l->_NormSpotDirection[2]; fcmd[LIT_DIRECTION_W] = 0; } diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 32bcff3360..b6561001e7 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -967,7 +967,7 @@ void radeonUpdateMaterial( GLcontext *ctx ) * _VP_inf_norm * _h_inf_norm * _Position - * _NormDirection + * _NormSpotDirection * _ModelViewInvScale * _NeedEyeCoords * _EyeZDir @@ -1028,9 +1028,9 @@ static void update_light( GLcontext *ctx ) fcmd[LIT_DIRECTION_W] = 0; } else { COPY_4V( &fcmd[LIT_POSITION_X], l->_Position ); - fcmd[LIT_DIRECTION_X] = -l->_NormDirection[0]; - fcmd[LIT_DIRECTION_Y] = -l->_NormDirection[1]; - fcmd[LIT_DIRECTION_Z] = -l->_NormDirection[2]; + fcmd[LIT_DIRECTION_X] = -l->_NormSpotDirection[0]; + fcmd[LIT_DIRECTION_Y] = -l->_NormSpotDirection[1]; + fcmd[LIT_DIRECTION_Z] = -l->_NormSpotDirection[2]; fcmd[LIT_DIRECTION_W] = 0; } diff --git a/src/mesa/main/attrib.c b/src/mesa/main/attrib.c index 1d2c460488..d5d0a552db 100644 --- a/src/mesa/main/attrib.c +++ b/src/mesa/main/attrib.c @@ -1104,7 +1104,7 @@ _mesa_PopAttrib(void) _mesa_light(ctx, i, GL_DIFFUSE, l->Diffuse); _mesa_light(ctx, i, GL_SPECULAR, l->Specular ); _mesa_light(ctx, i, GL_POSITION, l->EyePosition); - _mesa_light(ctx, i, GL_SPOT_DIRECTION, l->EyeDirection); + _mesa_light(ctx, i, GL_SPOT_DIRECTION, l->SpotDirection); _mesa_light(ctx, i, GL_SPOT_EXPONENT, &l->SpotExponent); _mesa_light(ctx, i, GL_SPOT_CUTOFF, &l->SpotCutoff); _mesa_light(ctx, i, GL_CONSTANT_ATTENUATION, diff --git a/src/mesa/main/light.c b/src/mesa/main/light.c index f72841b8cc..ac604fd12c 100644 --- a/src/mesa/main/light.c +++ b/src/mesa/main/light.c @@ -110,10 +110,10 @@ _mesa_light(GLcontext *ctx, GLuint lnum, GLenum pname, const GLfloat *params) break; case GL_SPOT_DIRECTION: /* NOTE: Direction already transformed by inverse ModelView! */ - if (TEST_EQ_3V(light->EyeDirection, params)) + if (TEST_EQ_3V(light->SpotDirection, params)) return; FLUSH_VERTICES(ctx, _NEW_LIGHT); - COPY_3V(light->EyeDirection, params); + COPY_3V(light->SpotDirection, params); break; case GL_SPOT_EXPONENT: ASSERT(params[0] >= 0.0); @@ -325,7 +325,7 @@ _mesa_GetLightfv( GLenum light, GLenum pname, GLfloat *params ) COPY_4V( params, ctx->Light.Light[l].EyePosition ); break; case GL_SPOT_DIRECTION: - COPY_3V( params, ctx->Light.Light[l].EyeDirection ); + COPY_3V( params, ctx->Light.Light[l].SpotDirection ); break; case GL_SPOT_EXPONENT: params[0] = ctx->Light.Light[l].SpotExponent; @@ -387,9 +387,9 @@ _mesa_GetLightiv( GLenum light, GLenum pname, GLint *params ) params[3] = (GLint) ctx->Light.Light[l].EyePosition[3]; break; case GL_SPOT_DIRECTION: - params[0] = (GLint) ctx->Light.Light[l].EyeDirection[0]; - params[1] = (GLint) ctx->Light.Light[l].EyeDirection[1]; - params[2] = (GLint) ctx->Light.Light[l].EyeDirection[2]; + params[0] = (GLint) ctx->Light.Light[l].SpotDirection[0]; + params[1] = (GLint) ctx->Light.Light[l].SpotDirection[1]; + params[2] = (GLint) ctx->Light.Light[l].SpotDirection[2]; break; case GL_SPOT_EXPONENT: params[0] = (GLint) ctx->Light.Light[l].SpotExponent; @@ -1139,23 +1139,23 @@ compute_light_positions( GLcontext *ctx ) /* Note: we normalize the spot direction now */ if (ctx->_NeedEyeCoords) { - COPY_3V( light->_NormDirection, light->EyeDirection ); - NORMALIZE_3FV( light->_NormDirection ); + COPY_3V( light->_NormSpotDirection, light->SpotDirection ); + NORMALIZE_3FV( light->_NormSpotDirection ); } else { GLfloat spotDir[3]; - COPY_3V(spotDir, light->EyeDirection); + COPY_3V(spotDir, light->SpotDirection); NORMALIZE_3FV(spotDir); - TRANSFORM_NORMAL( light->_NormDirection, + TRANSFORM_NORMAL( light->_NormSpotDirection, spotDir, ctx->ModelviewMatrixStack.Top->m); } - NORMALIZE_3FV( light->_NormDirection ); + NORMALIZE_3FV( light->_NormSpotDirection ); if (!(light->_Flags & LIGHT_POSITIONAL)) { GLfloat PV_dot_dir = - DOT3(light->_VP_inf_norm, - light->_NormDirection); + light->_NormSpotDirection); if (PV_dot_dir > light->_CosCutoff) { double x = PV_dot_dir * (EXP_TABLE_SIZE-1); @@ -1279,7 +1279,7 @@ init_light( struct gl_light *l, GLuint n ) ASSIGN_4V( l->Specular, 0.0, 0.0, 0.0, 1.0 ); } ASSIGN_4V( l->EyePosition, 0.0, 0.0, 1.0, 0.0 ); - ASSIGN_3V( l->EyeDirection, 0.0, 0.0, -1.0 ); + ASSIGN_3V( l->SpotDirection, 0.0, 0.0, -1.0 ); l->SpotExponent = 0.0; _mesa_invalidate_spot_exp_table( l ); l->SpotCutoff = 180.0; diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index 10f0d067e3..3f31590000 100644 --- a/src/mesa/main/mtypes.h +++ b/src/mesa/main/mtypes.h @@ -460,7 +460,7 @@ struct gl_light GLfloat Diffuse[4]; /**< diffuse color */ GLfloat Specular[4]; /**< specular color */ GLfloat EyePosition[4]; /**< position in eye coordinates */ - GLfloat EyeDirection[4]; /**< spotlight dir in eye coordinates */ + GLfloat SpotDirection[4]; /**< spotlight direction in eye coordinates */ GLfloat SpotExponent; GLfloat SpotCutoff; /**< in degrees */ GLfloat _CosCutoffNeg; /**< = cos(SpotCutoff) */ @@ -479,7 +479,7 @@ struct gl_light GLfloat _Position[4]; /**< position in eye/obj coordinates */ GLfloat _VP_inf_norm[3]; /**< Norm direction to infinite light */ GLfloat _h_inf_norm[3]; /**< Norm( _VP_inf_norm + <0,0,1> ) */ - GLfloat _NormDirection[4]; /**< normalized spotlight direction */ + GLfloat _NormSpotDirection[4]; /**< normalized spotlight direction */ GLfloat _VP_inf_spot_attenuation; GLfloat _SpotExpTable[EXP_TABLE_SIZE][2]; /**< to replace a pow() call */ diff --git a/src/mesa/shader/prog_statevars.c b/src/mesa/shader/prog_statevars.c index b93e987f04..37a3f1fc8c 100644 --- a/src/mesa/shader/prog_statevars.c +++ b/src/mesa/shader/prog_statevars.c @@ -112,7 +112,7 @@ _mesa_fetch_state(GLcontext *ctx, const gl_state_index state[], value[3] = ctx->Light.Light[ln].SpotExponent; return; case STATE_SPOT_DIRECTION: - COPY_3V(value, ctx->Light.Light[ln].EyeDirection); + COPY_3V(value, ctx->Light.Light[ln].SpotDirection); value[3] = ctx->Light.Light[ln]._CosCutoff; return; case STATE_SPOT_CUTOFF: @@ -449,7 +449,7 @@ _mesa_fetch_state(GLcontext *ctx, const gl_state_index state[], /* here, state[2] is the light number */ /* pre-normalize spot dir */ const GLuint ln = (GLuint) state[2]; - COPY_3V(value, ctx->Light.Light[ln]._NormDirection); + COPY_3V(value, ctx->Light.Light[ln]._NormSpotDirection); value[3] = ctx->Light.Light[ln]._CosCutoff; } return; diff --git a/src/mesa/tnl/t_rasterpos.c b/src/mesa/tnl/t_rasterpos.c index 04fb1d8f8c..f1fdddf0f5 100644 --- a/src/mesa/tnl/t_rasterpos.c +++ b/src/mesa/tnl/t_rasterpos.c @@ -167,7 +167,7 @@ shade_rastpos(GLcontext *ctx, light->QuadraticAttenuation)); if (light->_Flags & LIGHT_SPOT) { - GLfloat PV_dot_dir = - DOT3(VP, light->_NormDirection); + GLfloat PV_dot_dir = - DOT3(VP, light->_NormSpotDirection); if (PV_dot_dir_CosCutoff) { continue; diff --git a/src/mesa/tnl/t_vb_lighttmp.h b/src/mesa/tnl/t_vb_lighttmp.h index a78f27761f..124ca3c74f 100644 --- a/src/mesa/tnl/t_vb_lighttmp.h +++ b/src/mesa/tnl/t_vb_lighttmp.h @@ -141,7 +141,7 @@ static void TAG(light_rgba_spec)( GLcontext *ctx, /* spotlight attenuation */ if (light->_Flags & LIGHT_SPOT) { - GLfloat PV_dot_dir = - DOT3(VP, light->_NormDirection); + GLfloat PV_dot_dir = - DOT3(VP, light->_NormSpotDirection); if (PV_dot_dir_CosCutoff) { continue; /* this light makes no contribution */ @@ -325,7 +325,7 @@ static void TAG(light_rgba)( GLcontext *ctx, /* spotlight attenuation */ if (light->_Flags & LIGHT_SPOT) { - GLfloat PV_dot_dir = - DOT3(VP, light->_NormDirection); + GLfloat PV_dot_dir = - DOT3(VP, light->_NormSpotDirection); if (PV_dot_dir_CosCutoff) { continue; /* this light makes no contribution */ @@ -721,7 +721,7 @@ static void TAG(light_ci)( GLcontext *ctx, /* spotlight attenuation */ if (light->_Flags & LIGHT_SPOT) { - GLfloat PV_dot_dir = - DOT3(VP, light->_NormDirection); + GLfloat PV_dot_dir = - DOT3(VP, light->_NormSpotDirection); if (PV_dot_dir < light->_CosCutoff) { continue; /* this light makes no contribution */ } diff --git a/src/mesa/x86/gen_matypes.c b/src/mesa/x86/gen_matypes.c index 8c690b4f88..d56b701aa8 100644 --- a/src/mesa/x86/gen_matypes.c +++ b/src/mesa/x86/gen_matypes.c @@ -197,7 +197,7 @@ int main( int argc, char **argv ) OFFSET( "LIGHT_DIFFUSE ", struct gl_light, Diffuse ); OFFSET( "LIGHT_SPECULAR ", struct gl_light, Specular ); OFFSET( "LIGHT_EYE_POSITION ", struct gl_light, EyePosition ); - OFFSET( "LIGHT_EYE_DIRECTION ", struct gl_light, EyeDirection ); + OFFSET( "LIGHT_SPOT_DIRECTION ", struct gl_light, SpotDirection ); OFFSET( "LIGHT_SPOT_EXPONENT ", struct gl_light, SpotExponent ); OFFSET( "LIGHT_SPOT_CUTOFF ", struct gl_light, SpotCutoff ); OFFSET( "LIGHT_COS_CUTOFF ", struct gl_light, _CosCutoff ); @@ -211,7 +211,7 @@ int main( int argc, char **argv ) OFFSET( "LIGHT_POSITION ", struct gl_light, _Position ); OFFSET( "LIGHT_VP_INF_NORM ", struct gl_light, _VP_inf_norm ); OFFSET( "LIGHT_H_INF_NORM ", struct gl_light, _h_inf_norm ); - OFFSET( "LIGHT_NORM_DIRECTION ", struct gl_light, _NormDirection ); + OFFSET( "LIGHT_NORM_DIRECTION ", struct gl_light, _NormSpotDirection ); OFFSET( "LIGHT_VP_INF_SPOT_ATTEN ", struct gl_light, _VP_inf_spot_attenuation ); printf( "\n" ); OFFSET( "LIGHT_SPOT_EXP_TABLE ", struct gl_light, _SpotExpTable ); -- cgit v1.2.3 From 4d363cc16d94b1e356b7cc23bb3b15ca0374d1e3 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Fri, 3 Apr 2009 17:43:03 -0600 Subject: intel: #include texgetimage.h --- src/mesa/drivers/dri/intel/intel_tex_image.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c index 61ecabfa68..71561cf85c 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_image.c +++ b/src/mesa/drivers/dri/intel/intel_tex_image.c @@ -12,6 +12,7 @@ #include "main/simple_list.h" #include "main/texcompress.h" #include "main/texformat.h" +#include "main/texgetimage.h" #include "main/texobj.h" #include "main/texstore.h" #include "main/teximage.h" -- cgit v1.2.3 From e798bf8053612516420a4ec42e2ff58433abd521 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Mon, 6 Apr 2009 08:59:57 +0200 Subject: radeon: Expose a 32 bit RGBA fbconfig even when the screen depth is 16. Otherwise current xserver / libGL no longer expose a 32 bit RGBA GLX visual, and compiz fails. Fixes http://bugs.freedesktop.org/show_bug.cgi?id=20479 . --- src/mesa/drivers/dri/radeon/radeon_screen.c | 35 ++++++++++++++++------------- 1 file changed, 20 insertions(+), 15 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index e964feb9cc..882853344b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -261,8 +261,6 @@ radeonFillInModes( __DRIscreenPrivate *psp, __GLcontextModes *m; unsigned depth_buffer_factor; unsigned back_buffer_factor; - GLenum fb_format; - GLenum fb_type; int i; /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy @@ -293,20 +291,27 @@ radeonFillInModes( __DRIscreenPrivate *psp, depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1; back_buffer_factor = (have_back_buffer) ? 2 : 1; - if ( pixel_bits == 16 ) { - fb_format = GL_RGB; - fb_type = GL_UNSIGNED_SHORT_5_6_5; - } - else { - fb_format = GL_BGRA; - fb_type = GL_UNSIGNED_INT_8_8_8_8_REV; - } + if (pixel_bits == 16) { + __DRIconfig **configs_a8r8g8b8; + __DRIconfig **configs_r5g6b5; + + configs_r5g6b5 = driCreateConfigs(GL_RGB, GL_UNSIGNED_SHORT_5_6_5, + depth_bits_array, stencil_bits_array, + depth_buffer_factor, back_buffer_modes, + back_buffer_factor, msaa_samples_array, + 1); + configs_a8r8g8b8 = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV, + depth_bits_array, stencil_bits_array, + 1, back_buffer_modes, 1, + msaa_samples_array, 1); + configs = driConcatConfigs(configs_r5g6b5, configs_a8r8g8b8); + } else + configs = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV, + depth_bits_array, stencil_bits_array, + depth_buffer_factor, + back_buffer_modes, back_buffer_factor, + msaa_samples_array, 1); - configs = driCreateConfigs(fb_format, fb_type, - depth_bits_array, stencil_bits_array, - depth_buffer_factor, - back_buffer_modes, back_buffer_factor, - msaa_samples_array, 1); if (configs == NULL) { fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", __func__, __LINE__ ); -- cgit v1.2.3 From 5cca1ceb814ea9c5991d8b694d99a588c40b9860 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 6 Apr 2009 09:29:14 -0700 Subject: intel: Clean up some a leftover from sedding of bufmgr context->screen move. --- src/mesa/drivers/dri/intel/intel_screen.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index d20ea15187..752195aa35 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -613,9 +613,6 @@ intel_init_bufmgr(intelScreenPrivate *intelScreen) &intelScreen->sarea->last_dispatch); } - /* XXX bufmgr should be per-screen, not per-context */ - intelScreen->ttm = intelScreen->ttm; - return GL_TRUE; } -- cgit v1.2.3 From e7aef006e50d0b859c621267af8376f5a0f43445 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 6 Apr 2009 09:38:16 -0700 Subject: i965: Use GTT maps when available to upload vertex arrays and system VBOs. This speeds up OA on my GM45 by 21% (more than the original CPU cost of the upload path). We might still be able to squeeze a few more percent out by avoiding repeatedly mapping/unmapping buffers as we upload elements into them. --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 66 +++++++++++++++++++++-------- src/mesa/drivers/dri/intel/intel_screen.c | 6 +++ src/mesa/drivers/dri/intel/intel_screen.h | 1 + 3 files changed, 55 insertions(+), 18 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 02998d5957..b91b20bec6 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -277,6 +277,7 @@ copy_array_to_vbo_array( struct brw_context *brw, struct brw_vertex_element *element, GLuint dst_stride) { + struct intel_context *intel = &brw->intel; GLuint size = element->count * dst_stride; get_space(brw, size, &element->bo, &element->offset); @@ -289,29 +290,52 @@ copy_array_to_vbo_array( struct brw_context *brw, } if (dst_stride == element->glarray->StrideB) { - dri_bo_subdata(element->bo, - element->offset, - size, - element->glarray->Ptr); + if (intel->intelScreen->kernel_exec_fencing) { + drm_intel_gem_bo_map_gtt(element->bo); + memcpy((char *)element->bo->virtual + element->offset, + element->glarray->Ptr, size); + drm_intel_gem_bo_unmap_gtt(element->bo); + } else { + dri_bo_subdata(element->bo, + element->offset, + size, + element->glarray->Ptr); + } } else { - void *data; char *dest; const unsigned char *src = element->glarray->Ptr; int i; - data = _mesa_malloc(dst_stride * element->count); - dest = data; - for (i = 0; i < element->count; i++) { - memcpy(dest, src, dst_stride); - src += element->glarray->StrideB; - dest += dst_stride; - } + if (intel->intelScreen->kernel_exec_fencing) { + drm_intel_gem_bo_map_gtt(element->bo); + dest = element->bo->virtual; + dest += element->offset; - dri_bo_subdata(element->bo, - element->offset, - size, - data); - _mesa_free(data); + for (i = 0; i < element->count; i++) { + memcpy(dest, src, dst_stride); + src += element->glarray->StrideB; + dest += dst_stride; + } + + drm_intel_gem_bo_unmap_gtt(element->bo); + } else { + void *data; + + data = _mesa_malloc(dst_stride * element->count); + dest = data; + for (i = 0; i < element->count; i++) { + memcpy(dest, src, dst_stride); + src += element->glarray->StrideB; + dest += dst_stride; + } + + dri_bo_subdata(element->bo, + element->offset, + size, + data); + + _mesa_free(data); + } } } @@ -563,7 +587,13 @@ static void brw_prepare_indices(struct brw_context *brw) /* Straight upload */ - dri_bo_subdata(bo, offset, ib_size, index_buffer->ptr); + if (intel->intelScreen->kernel_exec_fencing) { + drm_intel_gem_bo_map_gtt(bo); + memcpy((char *)bo->virtual + offset, index_buffer->ptr, ib_size); + drm_intel_gem_bo_unmap_gtt(bo); + } else { + dri_bo_subdata(bo, offset, ib_size, index_buffer->ptr); + } } else { offset = (GLuint) (unsigned long) index_buffer->ptr; diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index 752195aa35..65e62947ef 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -563,6 +563,7 @@ intel_init_bufmgr(intelScreenPrivate *intelScreen) GLboolean gem_supported; struct drm_i915_getparam gp; __DRIscreenPrivate *spriv = intelScreen->driScrnPriv; + int num_fences; intelScreen->no_hw = getenv("INTEL_NO_HW") != NULL; @@ -613,6 +614,11 @@ intel_init_bufmgr(intelScreenPrivate *intelScreen) &intelScreen->sarea->last_dispatch); } + if (intel_get_param(spriv, I915_PARAM_NUM_FENCES_AVAIL, &num_fences)) + intelScreen->kernel_exec_fencing = !!num_fences; + else + intelScreen->kernel_exec_fencing = GL_FALSE; + return GL_TRUE; } diff --git a/src/mesa/drivers/dri/intel/intel_screen.h b/src/mesa/drivers/dri/intel/intel_screen.h index e1036de4db..a9b9e109a6 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.h +++ b/src/mesa/drivers/dri/intel/intel_screen.h @@ -79,6 +79,7 @@ typedef struct GLboolean no_vbo; int ttm; dri_bufmgr *bufmgr; + GLboolean kernel_exec_fencing; /** * Configuration cache with default values for all contexts -- cgit v1.2.3 From 6b187cc8a5041fe2bba1ecc34aa86516ebe8b1b0 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 6 Apr 2009 09:54:29 -0700 Subject: intel: Avoid dri2 GetBuffers round-trips for internal Viewport calls. This gets us the savings for driver-internal viewport calls that dd1c68f15123a889a3ce9d2afe724e272d163e32 was attempting, without relying on Xlib internals or clients handling X events. --- src/mesa/drivers/dri/intel/intel_context.c | 8 +++++--- src/mesa/drivers/dri/intel/intel_context.h | 1 + src/mesa/drivers/dri/intel/intel_pixel.c | 4 ++++ 3 files changed, 10 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri') diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index 888bb3f18f..a664e74936 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -307,9 +307,11 @@ intel_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei w, GLsizei h) if (!driContext->driScreenPriv->dri2.enabled) return; - intel_update_renderbuffers(driContext, driContext->driDrawablePriv); - if (driContext->driDrawablePriv != driContext->driReadablePriv) - intel_update_renderbuffers(driContext, driContext->driReadablePriv); + if (!intel->internal_viewport_call) { + intel_update_renderbuffers(driContext, driContext->driDrawablePriv); + if (driContext->driDrawablePriv != driContext->driReadablePriv) + intel_update_renderbuffers(driContext, driContext->driReadablePriv); + } old_viewport = ctx->Driver.Viewport; ctx->Driver.Viewport = NULL; diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index e520ecf220..d635f3f50d 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -180,6 +180,7 @@ struct intel_context struct intel_region *front_region; struct intel_region *back_region; struct intel_region *depth_region; + GLboolean internal_viewport_call; /** * This value indicates that the kernel memory manager is being used diff --git a/src/mesa/drivers/dri/intel/intel_pixel.c b/src/mesa/drivers/dri/intel/intel_pixel.c index 7041ff389a..fc0ac0b79c 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel.c +++ b/src/mesa/drivers/dri/intel/intel_pixel.c @@ -184,7 +184,9 @@ intel_meta_set_passthrough_transform(struct intel_context *intel) intel->meta.saved_vp_height = ctx->Viewport.Height; intel->meta.saved_matrix_mode = ctx->Transform.MatrixMode; + intel->internal_viewport_call = GL_TRUE; _mesa_Viewport(0, 0, ctx->DrawBuffer->Width, ctx->DrawBuffer->Height); + intel->internal_viewport_call = GL_FALSE; _mesa_MatrixMode(GL_PROJECTION); _mesa_PushMatrix(); @@ -206,8 +208,10 @@ intel_meta_restore_transform(struct intel_context *intel) _mesa_MatrixMode(intel->meta.saved_matrix_mode); + intel->internal_viewport_call = GL_TRUE; _mesa_Viewport(intel->meta.saved_vp_x, intel->meta.saved_vp_y, intel->meta.saved_vp_width, intel->meta.saved_vp_height); + intel->internal_viewport_call = GL_FALSE; } /** -- cgit v1.2.3