From c53705ed7b89e5a2586b534508182de9c72452ea Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Wed, 17 Jun 2009 07:58:35 -0600
Subject: GLX: attempt to fix glean makeCurrent test cases.

Two parts to this:

One we don't keep pointers to possibly freed memory anymore once we unbind the
drawables from the context. Brian I need to figure out what the comment
you made there, can we get a glean/piglit test so we can fix it properly?

If the new gc is the same as the oldGC, we call the unbind even though
we just bound it in that function. doh.

(cherry picked from master, commit 77506dac8e81e9548a7e9680ce367175fe5747af)
---
 src/mesa/drivers/dri/common/dri_util.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/common/dri_util.c b/src/mesa/drivers/dri/common/dri_util.c
index e112720471..576494940f 100644
--- a/src/mesa/drivers/dri/common/dri_util.c
+++ b/src/mesa/drivers/dri/common/dri_util.c
@@ -119,6 +119,9 @@ static int driUnbindContext(__DRIcontext *pcp)
     pdp = pcp->driDrawablePriv;
     prp = pcp->driReadablePriv;
 
+    /* already unbound */
+    if (!pdp && !prp)
+      return GL_TRUE;
     /* Let driver unbind drawable from context */
     (*psp->DriverAPI.UnbindContext)(pcp);
 
@@ -143,9 +146,10 @@ static int driUnbindContext(__DRIcontext *pcp)
      * window we can determine the last context bound to the window and
      * use that context's lock. (BrianP, 2-Dec-2000)
      */
+    pcp->driDrawablePriv = pcp->driReadablePriv = NULL;
+
 #if 0
     /* Unbind the drawable */
-    pcp->driDrawablePriv = NULL;
     pdp->driContextPriv = &psp->dummyContextPriv;
 #endif
 
-- 
cgit v1.2.3


From d18c57aaeac37cde0cb551191ecd3c3a56a0ffba Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Wed, 17 Jun 2009 08:34:24 -0600
Subject: mesa: added null ptr check in Fake_glXCreatePixmap()

Fixes segfault in progs/xdemos/glxgears_pixmap.c
---
 src/mesa/drivers/x11/fakeglx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/x11/fakeglx.c b/src/mesa/drivers/x11/fakeglx.c
index 3b004a3ee2..34e0b8bc8d 100644
--- a/src/mesa/drivers/x11/fakeglx.c
+++ b/src/mesa/drivers/x11/fakeglx.c
@@ -2218,7 +2218,7 @@ Fake_glXCreatePixmap( Display *dpy, GLXFBConfig config, Pixmap pixmap,
    if (!dpy || !config || !pixmap)
       return 0;
 
-   for (attr = attribList; *attr; attr++) {
+   for (attr = attribList; attr && *attr; attr++) {
       switch (*attr) {
       case GLX_TEXTURE_FORMAT_EXT:
          attr++;
-- 
cgit v1.2.3


From 2770107d87ccfd558480c44cd90a75524bdea738 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Sun, 10 May 2009 09:45:43 -0700
Subject: intel: Map write-only buffer objects through the GTT when possible.

This looks to be a win of a few percent in cairogears with new vbo code,
thanks to not polluting caches.
(cherry picked from commit aa422b262509bc0763a50f63a51a1730139ea52f)
---
 src/mesa/drivers/dri/intel/intel_buffer_objects.c | 16 ++++++++++++++--
 src/mesa/drivers/dri/intel/intel_buffer_objects.h |  1 +
 2 files changed, 15 insertions(+), 2 deletions(-)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.c b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
index c849e4869e..1b64c68157 100644
--- a/src/mesa/drivers/dri/intel/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
@@ -205,6 +205,7 @@ intel_bufferobj_map(GLcontext * ctx,
    struct intel_context *intel = intel_context(ctx);
    struct intel_buffer_object *intel_obj = intel_buffer_object(obj);
    GLboolean read_only = (access == GL_READ_ONLY_ARB);
+   GLboolean write_only = (access == GL_WRITE_ONLY_ARB);
 
    assert(intel_obj);
 
@@ -216,7 +217,14 @@ intel_bufferobj_map(GLcontext * ctx,
       return NULL;
    }
 
-   dri_bo_map(intel_obj->buffer, !read_only);
+   if (write_only && intel->intelScreen->kernel_exec_fencing) {
+      drm_intel_gem_bo_map_gtt(intel_obj->buffer);
+      intel_obj->mapped_gtt = GL_TRUE;
+   } else {
+      drm_intel_bo_map(intel_obj->buffer, !read_only);
+      intel_obj->mapped_gtt = GL_FALSE;
+   }
+
    obj->Pointer = intel_obj->buffer->virtual;
    return obj->Pointer;
 }
@@ -234,7 +242,11 @@ intel_bufferobj_unmap(GLcontext * ctx,
    assert(intel_obj);
    if (intel_obj->buffer != NULL) {
       assert(obj->Pointer);
-      dri_bo_unmap(intel_obj->buffer);
+      if (intel_obj->mapped_gtt) {
+	 drm_intel_gem_bo_unmap_gtt(intel_obj->buffer);
+      } else {
+	 drm_intel_bo_unmap(intel_obj->buffer);
+      }
       obj->Pointer = NULL;
    }
    return GL_TRUE;
diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.h b/src/mesa/drivers/dri/intel/intel_buffer_objects.h
index bf6dbd58f2..7ef723833c 100644
--- a/src/mesa/drivers/dri/intel/intel_buffer_objects.h
+++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.h
@@ -46,6 +46,7 @@ struct intel_buffer_object
    struct intel_region *region; /* Is there a zero-copy texture
                                    associated with this (pixel)
                                    buffer object? */
+   GLboolean mapped_gtt;
 };
 
 
-- 
cgit v1.2.3


From 61a2c9668fd59dc301c2b61d46b48c974d0f0109 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Sun, 10 May 2009 10:08:32 -0700
Subject: intel: Skip the DRI2 renderbuffer update when doing Viewport on an
 FBO. (cherry picked from commit d4a42b0ce6455d03be70aa56aacd779be193aca4)

---
 src/mesa/drivers/dri/intel/intel_context.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 5dc3df395d..bff0b05475 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -394,7 +394,7 @@ intel_viewport(GLcontext *ctx, GLint x, GLint y, GLsizei w, GLsizei h)
     if (!driContext->driScreenPriv->dri2.enabled)
 	return;
 
-    if (!intel->internal_viewport_call) {
+    if (!intel->internal_viewport_call && ctx->DrawBuffer->Name == 0) {
        intel_update_renderbuffers(driContext, driContext->driDrawablePriv);
        if (driContext->driDrawablePriv != driContext->driReadablePriv)
 	  intel_update_renderbuffers(driContext, driContext->driReadablePriv);
-- 
cgit v1.2.3


From d9e35d51fd9bb5d67865a451d16cf61c66f16a11 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 13 May 2009 18:18:29 -0700
Subject: intel: Use GL_FRONT_AND_BACK for stencil clearing.

This comes from a radeon-rewrite fallback fix, but may also fix stencil
clear failure when the polygon winding mode is flipped.
(cherry picked from commit d866abeffc7e4a29736fa35fb8ac09c3a28a44d6)
---
 src/mesa/drivers/dri/intel/intel_clear.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/intel/intel_clear.c b/src/mesa/drivers/dri/intel/intel_clear.c
index eb0d890f47..488db2cf45 100644
--- a/src/mesa/drivers/dri/intel/intel_clear.c
+++ b/src/mesa/drivers/dri/intel/intel_clear.c
@@ -256,7 +256,8 @@ intel_clear_tris(GLcontext *ctx, GLbitfield mask)
       if (this_mask & BUFFER_BIT_STENCIL) {
 	 _mesa_Enable(GL_STENCIL_TEST);
 	 _mesa_StencilOp(GL_REPLACE, GL_REPLACE, GL_REPLACE);
-	 _mesa_StencilFuncSeparate(GL_FRONT, GL_ALWAYS, ctx->Stencil.Clear,
+	 _mesa_StencilFuncSeparate(GL_FRONT_AND_BACK, GL_ALWAYS,
+				   ctx->Stencil.Clear,
 				   ctx->Stencil.WriteMask[0]);
       } else {
 	 _mesa_Disable(GL_STENCIL_TEST);
-- 
cgit v1.2.3


From 320a303be0805b5746f357653cf09ad9d7f0e8bc Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 13 May 2009 19:08:17 -0700
Subject: intel: Use FRONT_AND_BACK for StencilOp as well. (cherry picked from
 commit 64980125c76b05501a6fe7fe20fe52438f459129)

---
 src/mesa/drivers/dri/intel/intel_clear.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/intel/intel_clear.c b/src/mesa/drivers/dri/intel/intel_clear.c
index 488db2cf45..4dfaee8a4a 100644
--- a/src/mesa/drivers/dri/intel/intel_clear.c
+++ b/src/mesa/drivers/dri/intel/intel_clear.c
@@ -255,7 +255,8 @@ intel_clear_tris(GLcontext *ctx, GLbitfield mask)
       /* Control writing of the stencil clear value to stencil. */
       if (this_mask & BUFFER_BIT_STENCIL) {
 	 _mesa_Enable(GL_STENCIL_TEST);
-	 _mesa_StencilOp(GL_REPLACE, GL_REPLACE, GL_REPLACE);
+	 _mesa_StencilOpSeparate(GL_FRONT_AND_BACK,
+				 GL_REPLACE, GL_REPLACE, GL_REPLACE);
 	 _mesa_StencilFuncSeparate(GL_FRONT_AND_BACK, GL_ALWAYS,
 				   ctx->Stencil.Clear,
 				   ctx->Stencil.WriteMask[0]);
-- 
cgit v1.2.3


From 988b61be2743de6850c8042516db28d14ee3002f Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 14 May 2009 09:49:45 -0700
Subject: i965: Fix register allocation of GLSL fp inputs.

Before, if the VP output something that is in the attributes coming into
the WM but which isn't used by the WM, then WM would end up reading subsequent
varyings from the wrong places.  This was visible with a GLSL demo
using gl_PointSize in the VS and a varying in the WM, as point size is in
the VUE but not used by the WM.  There is now a regression test in piglit,
glsl-unused-varying.

(cherry picked from commit 0f5113deed91611ecdda6596542530b1849bb161)
---
 src/mesa/drivers/dri/i965/brw_wm.c       |  5 ++++-
 src/mesa/drivers/dri/i965/brw_wm.h       |  1 +
 src/mesa/drivers/dri/i965/brw_wm_glsl.c  | 31 +++++++++++++++++++++----------
 src/mesa/drivers/dri/i965/brw_wm_pass2.c |  3 +--
 4 files changed, 27 insertions(+), 13 deletions(-)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index c0b07da63b..bd296aa2a7 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -312,6 +312,9 @@ static void brw_wm_populate_key( struct brw_context *brw,
       key->drawable_height = brw->intel.driDrawable->h;
    }
 
+   /* CACHE_NEW_VS_PROG */
+   key->vp_outputs_written = brw->vs.prog_data->outputs_written & DO_SETUP_BITS;
+
    /* The unique fragment program ID */
    key->program_string_id = fp->id;
 }
@@ -350,7 +353,7 @@ const struct brw_tracked_state brw_wm_prog = {
       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 		BRW_NEW_WM_INPUT_DIMENSIONS |
 		BRW_NEW_REDUCED_PRIMITIVE),
-      .cache = 0
+      .cache = CACHE_NEW_VS_PROG,
    },
    .prepare = brw_prepare_wm_prog
 };
diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h
index 0408034c38..295fed851b 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.h
+++ b/src/mesa/drivers/dri/i965/brw_wm.h
@@ -75,6 +75,7 @@ struct brw_wm_prog_key {
    GLuint program_string_id:32;
    GLuint origin_x, origin_y;
    GLuint drawable_height;
+   GLuint vp_outputs_written;
 };
 
 
diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
index 117460842a..875683e0aa 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
@@ -177,7 +177,7 @@ static void prealloc_reg(struct brw_wm_compile *c)
 {
     int i, j;
     struct brw_reg reg;
-    int nr_interp_regs = 0;
+    int urb_read_length = 0;
     GLuint inputs = FRAG_BIT_WPOS | c->fp_interp_emitted | c->fp_deriv_emitted;
 
     for (i = 0; i < 4; i++) {
@@ -231,18 +231,29 @@ static void prealloc_reg(struct brw_wm_compile *c)
     }
 
     /* fragment shader inputs */
-    for (i = 0; i < FRAG_ATTRIB_MAX; i++) {
-	if (inputs & (1<<i)) {
-	    nr_interp_regs++;
-	    reg = brw_vec8_grf(c->reg_index, 0);
-	    for (j = 0; j < 4; j++)
-		set_reg(c, PROGRAM_PAYLOAD, i, j, reg);
-	    c->reg_index += 2;
-	}
+    for (i = 0; i < VERT_RESULT_MAX; i++) {
+       int fp_input;
+
+       if (i >= VERT_RESULT_VAR0)
+	  fp_input = i - VERT_RESULT_VAR0 + FRAG_ATTRIB_VAR0;
+       else if (i <= VERT_RESULT_TEX7)
+	  fp_input = i;
+       else
+	  fp_input = -1;
+
+       if (fp_input >= 0 && inputs & (1 << fp_input)) {
+	  urb_read_length = c->reg_index;
+	  reg = brw_vec8_grf(c->reg_index, 0);
+	  for (j = 0; j < 4; j++)
+	     set_reg(c, PROGRAM_PAYLOAD, fp_input, j, reg);
+       }
+       if (c->key.vp_outputs_written & (1 << i)) {
+	  c->reg_index += 2;
+       }
     }
 
     c->prog_data.first_curbe_grf = c->key.nr_depth_regs * 2;
-    c->prog_data.urb_read_length = nr_interp_regs * 2;
+    c->prog_data.urb_read_length = urb_read_length;
     c->prog_data.curb_read_length = c->nr_creg;
     c->emit_mask_reg = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, c->reg_index, 0);
     c->reg_index++;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass2.c b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
index 780edbc42e..08cac730c2 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_pass2.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
@@ -70,7 +70,6 @@ static void prealloc_reg(struct brw_wm_compile *c,
 static void init_registers( struct brw_wm_compile *c )
 {
    struct brw_context *brw = c->func.brw;
-   GLuint inputs = (brw->vs.prog_data->outputs_written & DO_SETUP_BITS);
    GLuint nr_interp_regs = 0;
    GLuint i = 0;
    GLuint j;
@@ -85,7 +84,7 @@ static void init_registers( struct brw_wm_compile *c )
       prealloc_reg(c, &c->creg[j], i++);
 
    for (j = 0; j < FRAG_ATTRIB_MAX; j++) {
-      if (inputs & (1<<j)) {
+      if (c->key.vp_outputs_written & (1<<j)) {
 	 /* index for vs output and ps input are not the same 
 	    in shader varying */
 	 GLuint index;
-- 
cgit v1.2.3


From 6e0df938d4504acc97012dc51002459d1d9f309a Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 14 May 2009 10:56:32 -0700
Subject: i965: Fix varying payload reg assignment for the
 non-GLSL-instructions path.

I don't have a testcase for this, but it seems clearly wrong.
(cherry picked from commit dc657f3929fbe03275b3fae4ef84f02e74b51114)
---
 src/mesa/drivers/dri/i965/brw_wm_pass2.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass2.c b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
index 08cac730c2..6faea018fb 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_pass2.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
@@ -69,7 +69,6 @@ static void prealloc_reg(struct brw_wm_compile *c,
  */
 static void init_registers( struct brw_wm_compile *c )
 {
-   struct brw_context *brw = c->func.brw;
    GLuint nr_interp_regs = 0;
    GLuint i = 0;
    GLuint j;
@@ -85,15 +84,18 @@ static void init_registers( struct brw_wm_compile *c )
 
    for (j = 0; j < FRAG_ATTRIB_MAX; j++) {
       if (c->key.vp_outputs_written & (1<<j)) {
-	 /* index for vs output and ps input are not the same 
-	    in shader varying */
-	 GLuint index;
-	 if (j > FRAG_ATTRIB_VAR0)
-	     index = j - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
+	 int fp_index;
+
+	 if (j >= VERT_RESULT_VAR0)
+	    fp_index = j - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
+	 else if (j <= VERT_RESULT_TEX7)
+	    fp_index = j;
 	 else
-	     index = j;
+	    fp_index = -1;
+
 	 nr_interp_regs++;
-	 prealloc_reg(c, &c->payload.input_interp[index], i++);
+	 if (fp_index >= 0)
+	    prealloc_reg(c, &c->payload.input_interp[fp_index], i++);
       }
    }
 
-- 
cgit v1.2.3


From fbd554d07456cf393a20cb86d1c0e81c416843aa Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 15 May 2009 11:41:42 -0700
Subject: i915: Only use the new 945 cube layout for compressed textures.

The docs actually explain this, but not in a terribly clear manner.
This nearly fixes the piglit cubemap testcase, except that something's
going wrong with the nearest filtering at 2x2 sizes in the testcase.
Looks good by visual inspection, though.

Bug #21692
(cherry picked from commit 5c5a46884899ea25cdf25545d6ab3d9a74eafa3a)
---
 src/mesa/drivers/dri/i915/i915_tex_layout.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/i915/i915_tex_layout.c b/src/mesa/drivers/dri/i915/i915_tex_layout.c
index d44a2f47b3..7cc1c096e4 100644
--- a/src/mesa/drivers/dri/i915/i915_tex_layout.c
+++ b/src/mesa/drivers/dri/i915/i915_tex_layout.c
@@ -454,7 +454,10 @@ i945_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree * mt)
 {
    switch (mt->target) {
    case GL_TEXTURE_CUBE_MAP:
-      i945_miptree_layout_cube(intel, mt);
+      if (mt->compressed)
+	 i945_miptree_layout_cube(intel, mt);
+      else
+	 i915_miptree_layout_cube(intel, mt);
       break;
    case GL_TEXTURE_3D:
       i945_miptree_layout_3d(intel, mt);
-- 
cgit v1.2.3


From 66bfd025c84ca6d4fb73f394adcdd41418ab6b25 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 15 May 2009 12:32:51 -0700
Subject: i915: Use Stencil.Enabled instead of Stencil._Enabled in DrawBuffers.

The _Enabled field isn't updated at the point that DrawBuffers is called,
and the Driver.Enable() function does the testing for stencil buffer
presence anyway.

bug #21608 for Radeon
(cherry picked from commit 4c6f82989983eecc0b3b724716cb3bcb675664c5)
---
 src/mesa/drivers/dri/intel/intel_buffers.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/intel/intel_buffers.c b/src/mesa/drivers/dri/intel/intel_buffers.c
index b86cafea24..d2fad9e4ea 100644
--- a/src/mesa/drivers/dri/intel/intel_buffers.c
+++ b/src/mesa/drivers/dri/intel/intel_buffers.c
@@ -276,7 +276,7 @@ intel_draw_buffer(GLcontext * ctx, struct gl_framebuffer *fb)
       ctx->Driver.Enable(ctx, GL_DEPTH_TEST,
                          (ctx->Depth.Test && fb->Visual.depthBits > 0));
       ctx->Driver.Enable(ctx, GL_STENCIL_TEST,
-                         (ctx->Stencil._Enabled && fb->Visual.stencilBits > 0));
+                         (ctx->Stencil.Enabled && fb->Visual.stencilBits > 0));
    }
    else {
       /* Mesa's Stencil._Enabled field is updated when
-- 
cgit v1.2.3


From 97974b7e5198eb480c0e86474ee177821c462d45 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 15 May 2009 17:32:21 -0700
Subject: intel: Don't complain on falling back from PBO fastpaths.

Instead, stash the debug info under the handy debug flag.

Bug #20053
(cherry picked from commit 22690482e692cb5ed2f84d3e69545c09292e3484)
---
 src/mesa/drivers/dri/intel/intel_tex_image.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c
index 1f192dafbe..66a3b4e492 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -208,7 +208,7 @@ try_pbo_upload(struct intel_context *intel,
    if (!pbo ||
        intel->ctx._ImageTransferState ||
        unpack->SkipPixels || unpack->SkipRows) {
-      _mesa_printf("%s: failure 1\n", __FUNCTION__);
+      DBG("%s: failure 1\n", __FUNCTION__);
       return GL_FALSE;
    }
 
@@ -264,7 +264,7 @@ try_pbo_zcopy(struct intel_context *intel,
    if (!pbo ||
        intel->ctx._ImageTransferState ||
        unpack->SkipPixels || unpack->SkipRows) {
-      _mesa_printf("%s: failure 1\n", __FUNCTION__);
+      DBG("%s: failure 1\n", __FUNCTION__);
       return GL_FALSE;
    }
 
@@ -283,7 +283,7 @@ try_pbo_zcopy(struct intel_context *intel,
    dst_stride = intelImage->mt->pitch;
 
    if (src_stride != dst_stride || dst_offset != 0 || src_offset != 0) {
-      _mesa_printf("%s: failure 2\n", __FUNCTION__);
+      DBG("%s: failure 2\n", __FUNCTION__);
       return GL_FALSE;
    }
 
-- 
cgit v1.2.3


From 7805c3b57b558dac7a92d97b6a2210e037aea792 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 20 May 2009 15:59:07 -0700
Subject: i956: Make state dependency of SF on drawbuffer bounds match Mesa's.

Noticed while debugging a weird 1D FBO testcase that left its existing
viewport and projection matrix in place when switching drawbuffers.  Didn't
fix the testcase, though.
(cherry picked from commit 3a521d84ecc646fcc65fa3fe7c5f1fdbdebe8bc2)
---
 src/mesa/drivers/dri/i965/brw_sf_state.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index 68fa9820b6..c99918724b 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -66,7 +66,9 @@ static void upload_sf_vp(struct brw_context *brw)
    sfv.viewport.m31 = v[MAT_TY] * y_scale + y_bias;
    sfv.viewport.m32 = v[MAT_TZ] * depth_scale;
 
-   /* _NEW_SCISSOR */
+   /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT
+    * for DrawBuffer->_[XY]{min,max}
+    */
 
    /* The scissor only needs to handle the intersection of drawable and
     * scissor rect.  Clipping to the boundaries of static shared buffers
@@ -97,7 +99,8 @@ static void upload_sf_vp(struct brw_context *brw)
 const struct brw_tracked_state brw_sf_vp = {
    .dirty = {
       .mesa  = (_NEW_VIEWPORT | 
-		_NEW_SCISSOR),
+		_NEW_SCISSOR |
+		_NEW_BUFFERS),
       .brw   = 0,
       .cache = 0
    },
-- 
cgit v1.2.3


From cee73ffdaf3a73f54593010dc1cbc77610ba3224 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 26 May 2009 19:48:08 -0700
Subject: i915: Restore the Viewport and DepthRange functions on 8xx.

Fixes failed viewport updates on glxgears (and other apps) resize since
e41780fedc2c1f22b43118da30a0103fa68b769f.

Bug #20473.
(cherry picked from commit 0e83e8f51af07a3066519f169f07d9afbf23252e)
---
 src/mesa/drivers/dri/i915/i830_state.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/i915/i830_state.c b/src/mesa/drivers/dri/i915/i830_state.c
index d9cad0c4bf..8ef6c9144f 100644
--- a/src/mesa/drivers/dri/i915/i830_state.c
+++ b/src/mesa/drivers/dri/i915/i830_state.c
@@ -39,6 +39,7 @@
 #include "intel_screen.h"
 #include "intel_batchbuffer.h"
 #include "intel_fbo.h"
+#include "intel_buffers.h"
 
 #include "i830_context.h"
 #include "i830_reg.h"
@@ -446,6 +447,24 @@ i830DepthMask(GLcontext * ctx, GLboolean flag)
       i830->state.Ctx[I830_CTXREG_ENABLES_2] |= DISABLE_DEPTH_WRITE;
 }
 
+/** Called from ctx->Driver.Viewport() */
+static void
+i830Viewport(GLcontext * ctx,
+              GLint x, GLint y, GLsizei width, GLsizei height)
+{
+   intelCalcViewport(ctx);
+
+   intel_viewport(ctx, x, y, width, height);
+}
+
+
+/** Called from ctx->Driver.DepthRange() */
+static void
+i830DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval)
+{
+   intelCalcViewport(ctx);
+}
+
 /* =============================================================
  * Polygon stipple
  *
@@ -1064,6 +1083,8 @@ i830InitStateFuncs(struct dd_function_table *functions)
    functions->StencilFuncSeparate = i830StencilFuncSeparate;
    functions->StencilMaskSeparate = i830StencilMaskSeparate;
    functions->StencilOpSeparate = i830StencilOpSeparate;
+   functions->DepthRange = i830DepthRange;
+   functions->Viewport = i830Viewport;
 }
 
 void
-- 
cgit v1.2.3


From 1b8e4dd2c8343af391a33be2aff7978366c450df Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 26 May 2009 20:45:29 -0700
Subject: i915: Fall back on NPOT textured metaops on 830-class. (cherry picked
 from commit 8ec6e036792decf5149a209e51cb5e93ccc5c754)

---
 src/mesa/drivers/dri/intel/intel_context.h      |  6 ++++++
 src/mesa/drivers/dri/intel/intel_pixel_bitmap.c |  8 ++++++++
 src/mesa/drivers/dri/intel/intel_pixel_draw.c   | 16 ++++++++++++++++
 3 files changed, 30 insertions(+)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index f45e24ca3a..b5cf7e6648 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -559,4 +559,10 @@ intel_context(GLcontext * ctx)
    return (struct intel_context *) ctx;
 }
 
+static INLINE GLboolean
+is_power_of_two(uint32_t value)
+{
+   return (value & (value - 1)) == 0;
+}
+
 #endif
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
index 1db7f5594e..69e619ac4a 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
@@ -401,6 +401,14 @@ intel_texture_bitmap(GLcontext * ctx,
       return GL_FALSE;
    }
 
+   if (!ctx->Extensions.ARB_texture_non_power_of_two &&
+       (!is_power_of_two(width) || !is_power_of_two(height))) {
+      if (INTEL_DEBUG & DEBUG_FALLBACKS)
+	 fprintf(stderr,
+		 "glBitmap() fallback: NPOT texture\n");
+      return GL_FALSE;
+   }
+
    /* Check that we can load in a texture this big. */
    if (width > (1 << (ctx->Const.MaxTextureLevels - 1)) ||
        height > (1 << (ctx->Const.MaxTextureLevels - 1))) {
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_draw.c b/src/mesa/drivers/dri/intel/intel_pixel_draw.c
index e8d5ac8569..2706ca327f 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_draw.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_draw.c
@@ -120,6 +120,14 @@ intel_texture_drawpixels(GLcontext * ctx,
       return GL_FALSE;
    }
 
+   if (!ctx->Extensions.ARB_texture_non_power_of_two &&
+       (!is_power_of_two(width) || !is_power_of_two(height))) {
+      if (INTEL_DEBUG & DEBUG_FALLBACKS)
+	 fprintf(stderr,
+		 "glDrawPixels() fallback: NPOT texture\n");
+      return GL_FALSE;
+   }
+
    _mesa_PushAttrib(GL_ENABLE_BIT | GL_TEXTURE_BIT |
 		    GL_CURRENT_BIT);
    _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT);
@@ -273,6 +281,14 @@ intel_stencil_drawpixels(GLcontext * ctx,
       return GL_FALSE;
    }
 
+   if (!ctx->Extensions.ARB_texture_non_power_of_two &&
+       (!is_power_of_two(width) || !is_power_of_two(height))) {
+      if (INTEL_DEBUG & DEBUG_FALLBACKS)
+	 fprintf(stderr,
+		 "glDrawPixels(GL_STENCIL_INDEX) fallback: NPOT texture\n");
+      return GL_FALSE;
+   }
+
    _mesa_PushAttrib(GL_ENABLE_BIT | GL_TEXTURE_BIT |
 		    GL_CURRENT_BIT | GL_COLOR_BUFFER_BIT | GL_DEPTH_BUFFER_BIT);
    _mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT);
-- 
cgit v1.2.3


From ff3da0966fc91cd5bcfed994e5edadbf25903c47 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 2 Jun 2009 06:53:40 -0700
Subject: i915: Don't put VBOs in graphics memory unless required for an
 operation.

This saves doing swtnl from uncached memory, which is painful.  Improves
clutter test-text performance by 10% since it started using VBOs.
(cherry picked from commit a945e203d4fe254593bc0c5c5d6caca45e65f9f7)
---
 src/mesa/drivers/dri/intel/intel_buffer_objects.c | 39 ++++++++++++++++++++++-
 src/mesa/drivers/dri/intel/intel_buffer_objects.h |  2 ++
 2 files changed, 40 insertions(+), 1 deletion(-)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.c b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
index 1b64c68157..c31fe91ad6 100644
--- a/src/mesa/drivers/dri/intel/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
@@ -102,6 +102,7 @@ intel_bufferobj_free(GLcontext * ctx, struct gl_buffer_object *obj)
    assert(intel_obj);
    assert(!obj->Pointer); /* Mesa should have unmapped it */
 
+   _mesa_free(intel_obj->sys_buffer);
    if (intel_obj->region) {
       intel_bufferobj_release_region(intel, intel_obj);
    }
@@ -142,7 +143,23 @@ intel_bufferobj_data(GLcontext * ctx,
       dri_bo_unreference(intel_obj->buffer);
       intel_obj->buffer = NULL;
    }
+   _mesa_free(intel_obj->sys_buffer);
+   intel_obj->sys_buffer = NULL;
+
    if (size != 0) {
+#ifdef I915
+      /* On pre-965, stick VBOs in system memory, as we're always doing swtnl
+       * with their contents anyway.
+       */
+      if (target == GL_ARRAY_BUFFER || target == GL_ELEMENT_ARRAY_BUFFER) {
+	 intel_obj->sys_buffer = _mesa_malloc(size);
+	 if (intel_obj->sys_buffer != NULL) {
+	    if (data != NULL)
+	       memcpy(intel_obj->sys_buffer, data, size);
+	    return;
+	 }
+      }
+#endif
       intel_bufferobj_alloc_buffer(intel, intel_obj);
 
       if (data != NULL)
@@ -172,7 +189,10 @@ intel_bufferobj_subdata(GLcontext * ctx,
    if (intel_obj->region)
       intel_bufferobj_cow(intel, intel_obj);
 
-   dri_bo_subdata(intel_obj->buffer, offset, size, data);
+   if (intel_obj->sys_buffer)
+      memcpy((char *)intel_obj->sys_buffer + offset, data, size);
+   else
+      dri_bo_subdata(intel_obj->buffer, offset, size, data);
 }
 
 
@@ -209,6 +229,11 @@ intel_bufferobj_map(GLcontext * ctx,
 
    assert(intel_obj);
 
+   if (intel_obj->sys_buffer) {
+      obj->Pointer = intel_obj->sys_buffer;
+      return obj->Pointer;
+   }
+
    if (intel_obj->region)
       intel_bufferobj_cow(intel, intel_obj);
 
@@ -265,6 +290,18 @@ intel_bufferobj_buffer(struct intel_context *intel,
       }
    }
 
+   if (intel_obj->buffer == NULL) {
+      intel_bufferobj_alloc_buffer(intel, intel_obj);
+      intel_bufferobj_subdata(&intel->ctx,
+			      GL_ARRAY_BUFFER_ARB,
+			      0,
+			      intel_obj->Base.Size,
+			      intel_obj->sys_buffer,
+			      &intel_obj->Base);
+      _mesa_free(intel_obj->sys_buffer);
+      intel_obj->sys_buffer = NULL;
+   }
+
    return intel_obj->buffer;
 }
 
diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.h b/src/mesa/drivers/dri/intel/intel_buffer_objects.h
index 7ef723833c..0431015631 100644
--- a/src/mesa/drivers/dri/intel/intel_buffer_objects.h
+++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.h
@@ -42,6 +42,8 @@ struct intel_buffer_object
 {
    struct gl_buffer_object Base;
    dri_bo *buffer;     /* the low-level buffer manager's buffer handle */
+   /** System memory buffer data, if not using a BO to store the data. */
+   void *sys_buffer;
 
    struct intel_region *region; /* Is there a zero-copy texture
                                    associated with this (pixel)
-- 
cgit v1.2.3


From e15aebe10e20aacce63175b68ec8daa5c1dc4e0c Mon Sep 17 00:00:00 2001
From: Robert Ellison <papillo@vmware.com>
Date: Fri, 8 May 2009 14:40:38 -0600
Subject: i965: fix segfault on low memory conditions

When out of memory (in at least one case, triggered by a longrunning
memory leak), this code will segfault and crash.  By checking for the
out-of-memory condition, the system can continue, and will report
the out-of-memory error later, a much preferable outcome.
(cherry picked from commit 44a4abfd4f8695809eaec07df8eeb191d6e017d7)
---
 src/mesa/drivers/dri/i965/brw_wm.c | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index bd296aa2a7..8a3b7df9c7 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -146,6 +146,13 @@ static void do_wm_prog( struct brw_context *brw,
    if (c == NULL) {
       brw->wm.compile_data = calloc(1, sizeof(*brw->wm.compile_data));
       c = brw->wm.compile_data;
+      if (c == NULL) {
+         /* Ouch - big out of memory problem.  Can't continue
+          * without triggering a segfault, no way to signal,
+          * so just return.
+          */
+         return;
+      }
    } else {
       memset(c, 0, sizeof(*brw->wm.compile_data));
    }
-- 
cgit v1.2.3


From 56235ae5049bee929c83f6932db077afaa5930f8 Mon Sep 17 00:00:00 2001
From: Robert Ellison <papillo@vmware.com>
Date: Wed, 13 May 2009 20:38:33 -0600
Subject: i965: send all warnings through _mesa_warning()

One warning message:
   drm_i915_getparam: -22

was still being sent to fprintf().  This causes all Piglit tests to fail,
even with MESA_DEBUG=0.

Using _mesa_warning() to emit the message allows the general Mesa controls
for messages like this to be applied.
(cherry picked from commit bc3270e99f5c39544aaf831742db14796ab83a6a)
---
 src/mesa/drivers/dri/intel/intel_screen.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 50cb13a482..0b48563776 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -236,7 +236,7 @@ intel_get_param(__DRIscreenPrivate *psp, int param, int *value)
 
    ret = drmCommandWriteRead(psp->fd, DRM_I915_GETPARAM, &gp, sizeof(gp));
    if (ret) {
-      fprintf(stderr, "drm_i915_getparam: %d\n", ret);
+      _mesa_warning(NULL, "drm_i915_getparam: %d\n", ret);
       return GL_FALSE;
    }
 
-- 
cgit v1.2.3


From d446d3acacdffa7c0f744764214b2bea5e191678 Mon Sep 17 00:00:00 2001
From: Robert Ellison <papillo@vmware.com>
Date: Wed, 13 May 2009 20:40:23 -0600
Subject: i965: fix 1D texture borders with GL_CLAMP_TO_BORDER

With 1D textures, GL_TEXTURE_WRAP_T should be ignored (only
GL_TEXTURE_WRAP_S should be respected).  But the i965 hardware
seems to follow the value of GL_TEXTURE_WRAP_T even when sampling
1D textures.

This fix forces GL_TEXTURE_WRAP_T to be GL_REPEAT whenever 1D
textures are used; this allows the texture to be sampled
correctly, avoiding "imaginary" border elements in the T direction.

This bug was demonstrated in the Piglit tex1d-2dborder test.
With this fix, that test passes.
(cherry picked from commit ab6c4fa582972e25f8800c77b5dd5b3a83afc996)
---
 src/mesa/drivers/dri/i965/brw_wm_sampler_state.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
index c604ef0162..3fc18ff1f3 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
@@ -178,6 +178,16 @@ static void brw_update_sampler_state(struct wm_sampler_entry *key,
       sampler->ss1.s_wrap_mode = BRW_TEXCOORDMODE_CUBE;
       sampler->ss1.t_wrap_mode = BRW_TEXCOORDMODE_CUBE;
    }
+   else if (key->tex_target == GL_TEXTURE_1D) {
+      /* There's a bug in 1D texture sampling - it actually pays
+       * attention to the wrap_t value, though it should not.
+       * Override the wrap_t value here to GL_REPEAT to keep
+       * any nonexistent border pixels from floating in.
+       */
+      sampler->ss1.r_wrap_mode = translate_wrap_mode(key->wrap_r);
+      sampler->ss1.s_wrap_mode = translate_wrap_mode(key->wrap_s);
+      sampler->ss1.t_wrap_mode = BRW_TEXCOORDMODE_WRAP;
+   }
    else {
       sampler->ss1.r_wrap_mode = translate_wrap_mode(key->wrap_r);
       sampler->ss1.s_wrap_mode = translate_wrap_mode(key->wrap_s);
-- 
cgit v1.2.3


From 39366ed995310c95d95e0c7a33fb0bec637a00b6 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Mon, 8 Jun 2009 14:41:54 -0600
Subject: intel: remove extra \n from warning string (cherry picked from commit
 42e9bde0fa2276b8f5bb434328eea7665794b127)

---
 src/mesa/drivers/dri/intel/intel_screen.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 0b48563776..0f278b3acd 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -236,7 +236,7 @@ intel_get_param(__DRIscreenPrivate *psp, int param, int *value)
 
    ret = drmCommandWriteRead(psp->fd, DRM_I915_GETPARAM, &gp, sizeof(gp));
    if (ret) {
-      _mesa_warning(NULL, "drm_i915_getparam: %d\n", ret);
+      _mesa_warning(NULL, "drm_i915_getparam: %d", ret);
       return GL_FALSE;
    }
 
-- 
cgit v1.2.3


From 43bb78f2bb6c851d989903e7eb996e87113d878c Mon Sep 17 00:00:00 2001
From: Roland Scheidegger <sroland@vmware.com>
Date: Fri, 19 Jun 2009 20:00:55 +0200
Subject: radeons: use dp4 for position invariant vertex programs

Fixes #22181. R200 requires this since DP4 is used in hw tnl mode.
R300 prefers it (should be faster due to no instruction dependencies), but
both methods should be correct (when sw tcl is used though, MUL/MAD might
be faster). Probably doesn't make much difference for R100 since vertex progs
are executed in software anyway, but let's just keep it the same there too.
---
 src/mesa/drivers/dri/r200/r200_context.c     | 2 ++
 src/mesa/drivers/dri/r300/r300_context.c     | 2 ++
 src/mesa/drivers/dri/radeon/radeon_context.c | 2 ++
 3 files changed, 6 insertions(+)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c
index c06751516e..058296eab2 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -405,6 +405,8 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
 
    ctx->Const.MaxDrawBuffers = 1;
 
+   _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
+
    /* Initialize the software rasterizer and helper modules.
     */
    _swrast_CreateContext( ctx );
diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c
index 8f0effd83e..7d6705058f 100644
--- a/src/mesa/drivers/dri/r300/r300_context.c
+++ b/src/mesa/drivers/dri/r300/r300_context.c
@@ -327,6 +327,8 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 
 	ctx->Const.MaxDrawBuffers = 1;
 
+	_mesa_set_mvp_with_dp4( ctx, GL_TRUE );
+
 	/* Initialize the software rasterizer and helper modules.
 	 */
 	_swrast_CreateContext(ctx);
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c
index ea81a3250b..b67bda7d06 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -355,6 +355,8 @@ radeonCreateContext( const __GLcontextModes *glVisual,
 
    ctx->Const.MaxDrawBuffers = 1;
 
+   _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
+
    /* Initialize the software rasterizer and helper modules.
     */
    _swrast_CreateContext( ctx );
-- 
cgit v1.2.3


From daacac1c24ce5551e074c07f64e14f5c5057d188 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 19 Jun 2009 15:49:24 -0700
Subject: intel: Fix glClear behavior versus display lists.

The CALL_DrawArrays was leaking the clear's primitives into the display
list with GL_COMPILE_AND_EXECUTE.  Use _mesa_DrawArrays instead, which
doesn't appear to leak.  Fixes piglit dlist-clear test.
(cherry picked from commit 64edde1004f7a69e77877bba24d315a92bcd47c8)
---
 src/mesa/drivers/dri/intel/intel_clear.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/intel/intel_clear.c b/src/mesa/drivers/dri/intel/intel_clear.c
index 4dfaee8a4a..19f47632ac 100644
--- a/src/mesa/drivers/dri/intel/intel_clear.c
+++ b/src/mesa/drivers/dri/intel/intel_clear.c
@@ -264,7 +264,7 @@ intel_clear_tris(GLcontext *ctx, GLbitfield mask)
 	 _mesa_Disable(GL_STENCIL_TEST);
       }
 
-      CALL_DrawArrays(ctx->Exec, (GL_TRIANGLE_FAN, 0, 4));
+      _mesa_DrawArrays(GL_TRIANGLE_FAN, 0, 4);
 
       mask &= ~this_mask;
    }
-- 
cgit v1.2.3


From abfd56c24c821e0dec233348ef01aef5b57f2763 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 19 Jun 2009 15:57:03 -0700
Subject: intel: Fix other metaops versus GL_COMPILE_AND_EXECUTE dlists.

Fixes oglconform zbfunc.c and pxtrans-cidraw.c, at least.

(cherry picked from commit 405300bb190f516e16b704050abe3389b366ed27)
---
 src/mesa/drivers/dri/intel/intel_pixel_bitmap.c | 2 +-
 src/mesa/drivers/dri/intel/intel_pixel_draw.c   | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
index 69e619ac4a..a2ccae1b7d 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
@@ -507,7 +507,7 @@ intel_texture_bitmap(GLcontext * ctx,
    _mesa_TexCoordPointer(2, GL_FLOAT, 2 * sizeof(GLfloat), &texcoords);
    _mesa_Enable(GL_VERTEX_ARRAY);
    _mesa_Enable(GL_TEXTURE_COORD_ARRAY);
-   CALL_DrawArrays(ctx->Exec, (GL_TRIANGLE_FAN, 0, 4));
+   _mesa_DrawArrays(GL_TRIANGLE_FAN, 0, 4);
 
    intel_meta_restore_transform(intel);
    intel_meta_restore_fragment_program(intel);
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_draw.c b/src/mesa/drivers/dri/intel/intel_pixel_draw.c
index 2706ca327f..225c5f48a5 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_draw.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_draw.c
@@ -191,7 +191,7 @@ intel_texture_drawpixels(GLcontext * ctx,
    _mesa_TexCoordPointer(2, GL_FLOAT, 2 * sizeof(GLfloat), &texcoords);
    _mesa_Enable(GL_VERTEX_ARRAY);
    _mesa_Enable(GL_TEXTURE_COORD_ARRAY);
-   CALL_DrawArrays(ctx->Exec, (GL_TRIANGLE_FAN, 0, 4));
+   _mesa_DrawArrays(GL_TRIANGLE_FAN, 0, 4);
 
    intel_meta_restore_transform(intel);
 
@@ -383,7 +383,7 @@ intel_stencil_drawpixels(GLcontext * ctx,
    _mesa_TexCoordPointer(2, GL_FLOAT, 2 * sizeof(GLfloat), &texcoords);
    _mesa_Enable(GL_VERTEX_ARRAY);
    _mesa_Enable(GL_TEXTURE_COORD_ARRAY);
-   CALL_DrawArrays(ctx->Exec, (GL_TRIANGLE_FAN, 0, 4));
+   _mesa_DrawArrays(GL_TRIANGLE_FAN, 0, 4);
 
    intel_meta_restore_transform(intel);
 
-- 
cgit v1.2.3


From 19218fe71269d03e1a2e9fcfd0c06a9adb5cb21d Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Tue, 9 Jun 2009 15:07:39 -0600
Subject: i965: added intelFlush() call in intel_get_tex_image()

Fixes the render-to-texture test in progs/tests/getteximage.c
(cherry picked from commit a03b349153660e449daf4f56d750f1caef23b1a5)
---
 src/mesa/drivers/dri/intel/intel_tex_image.c | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c
index 66a3b4e492..5e61e9e95e 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -637,6 +637,12 @@ intel_get_tex_image(GLcontext * ctx, GLenum target, GLint level,
    struct intel_context *intel = intel_context(ctx);
    struct intel_texture_image *intelImage = intel_texture_image(texImage);
 
+   /* If we're reading from a texture that has been rendered to, need to
+    * make sure rendering is complete.
+    * We could probably predicate this on texObj->_RenderToTexture
+    */
+   intelFlush(ctx);
+
    /* Map */
    if (intelImage->mt) {
       /* Image is stored in hardware format in a buffer managed by the
-- 
cgit v1.2.3


From 0584b6e433753dd01101c6824f6f6336c40d0f1f Mon Sep 17 00:00:00 2001
From: Michel Dänzer <daenzer@vmware.com>
Date: Thu, 11 Jun 2009 12:09:10 +0200
Subject: intel: intel_texture_drawpixels() can't handle GL_DEPTH_STENCIL.

Fixes glean depthStencil test.
(cherry picked from commit 3885b708fdbb7bbd5dd3a247c41fb9a75ee7c057)
---
 src/mesa/drivers/dri/intel/intel_pixel_draw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/intel/intel_pixel_draw.c b/src/mesa/drivers/dri/intel/intel_pixel_draw.c
index 225c5f48a5..d80069dd58 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_draw.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_draw.c
@@ -97,7 +97,7 @@ intel_texture_drawpixels(GLcontext * ctx,
    /* We don't have a way to generate fragments with stencil values which
     * will set the resulting stencil value.
     */
-   if (format == GL_STENCIL_INDEX)
+   if (format == GL_STENCIL_INDEX || format == GL_DEPTH_STENCIL)
       return GL_FALSE;
 
    /* Check that we can load in a texture this big. */
-- 
cgit v1.2.3


From 2f184d0d9f4600a20022887674b77f45ee6b728e Mon Sep 17 00:00:00 2001
From: Roland Scheidegger <sroland@vmware.com>
Date: Tue, 16 Jun 2009 21:38:58 +0200
Subject: i965: handle OPCODE_SWZ in the glsl path

glsl compiler will not generate OPCODE_SWZ, and as a first step it would
be translated away to a MOV anyway (why?), but later internally this opcode is
generated (for EXT_texture_swizzling).
(cherry picked from commit 4ef1f8e3b52a06fcf58f78c9c36738531b91dbac)
---
 src/mesa/drivers/dri/i965/brw_wm_glsl.c | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/mesa/drivers')

diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
index 875683e0aa..094c1af2fe 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
@@ -2681,6 +2681,7 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
 		emit_trunc(c, inst);
 		break;
 	    case OPCODE_MOV:
+	    case OPCODE_SWZ:
 		emit_mov(c, inst);
 		break;
 	    case OPCODE_DP3:
-- 
cgit v1.2.3