From 7c26b61f9366a397e353d7b7f1f1d1f6d0dcd0c7 Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keith@tungstengraphics.com>
Date: Thu, 21 Apr 2005 14:46:57 +0000
Subject: Reduce the size of mesa's internal fragment and vertex program
 representations by switching to packed structures for registers and
 instructions.

---
 src/mesa/shader/nvvertprog.h | 75 ++++++++++++++++++++++----------------------
 1 file changed, 37 insertions(+), 38 deletions(-)

(limited to 'src/mesa/shader/nvvertprog.h')

diff --git a/src/mesa/shader/nvvertprog.h b/src/mesa/shader/nvvertprog.h
index 583b901207..ca9930a974 100644
--- a/src/mesa/shader/nvvertprog.h
+++ b/src/mesa/shader/nvvertprog.h
@@ -37,38 +37,36 @@
 /* Vertex program opcodes */
 enum vp_opcode
 {
-   VP_OPCODE_MOV,
-   VP_OPCODE_LIT,
-   VP_OPCODE_RCP,
-   VP_OPCODE_RSQ,
-   VP_OPCODE_EXP,
-   VP_OPCODE_LOG,
-   VP_OPCODE_MUL,
+   VP_OPCODE_ABS,
    VP_OPCODE_ADD,
+   VP_OPCODE_ARL,
    VP_OPCODE_DP3,
    VP_OPCODE_DP4,
+   VP_OPCODE_DPH,
    VP_OPCODE_DST,
-   VP_OPCODE_MIN,
-   VP_OPCODE_MAX,
-   VP_OPCODE_SLT,
-   VP_OPCODE_SGE,
+   VP_OPCODE_END,		/* Placeholder */
+   VP_OPCODE_EX2,		/* ARB only */
+   VP_OPCODE_EXP,
+   VP_OPCODE_FLR,		/* ARB */
+   VP_OPCODE_FRC,		/* ARB */
+   VP_OPCODE_LG2,		/* ARB only */
+   VP_OPCODE_LIT,
+   VP_OPCODE_LOG,
    VP_OPCODE_MAD,
-   VP_OPCODE_ARL,
-   VP_OPCODE_DPH,
+   VP_OPCODE_MAX,
+   VP_OPCODE_MIN,
+   VP_OPCODE_MOV,
+   VP_OPCODE_MUL,
+   VP_OPCODE_POW,		/* ARB only */
+   VP_OPCODE_PRINT,		/* Mesa only */
    VP_OPCODE_RCC,
+   VP_OPCODE_RCP,
+   VP_OPCODE_RSQ,
+   VP_OPCODE_SGE,
+   VP_OPCODE_SLT,
    VP_OPCODE_SUB,
-   VP_OPCODE_ABS,
-   VP_OPCODE_END,
-   /* Additional opcodes for GL_ARB_vertex_program */ 
-   VP_OPCODE_FLR,
-   VP_OPCODE_FRC,
-   VP_OPCODE_EX2,
-   VP_OPCODE_LG2,
-   VP_OPCODE_POW,
-   VP_OPCODE_XPD,
-   VP_OPCODE_SWZ,
-   /* Special Mesa opcodes */
-   VP_OPCODE_PRINT
+   VP_OPCODE_SWZ,		/* ARB only */
+   VP_OPCODE_XPD		/* ARB only */
 };
 
 
@@ -76,34 +74,35 @@ enum vp_opcode
 /* Instruction source register */
 struct vp_src_register
 {
-   enum register_file File;  /* which register file */
-   GLint Index;              /* index into register file */
-   GLubyte Swizzle[4]; /* Each value is 0,1,2,3 for x,y,z,w or */
-                       /* SWIZZLE_ZERO or SWIZZLE_ONE for VP_OPCODE_SWZ. */
-   GLboolean Negate;
-   GLboolean RelAddr;
+   GLuint File:4;
+   GLuint Index:8;
+   GLuint Swizzle:12;
+   GLuint Negate:4;		/* ARB requires component-wise negation. */
+   GLuint RelAddr:1;
+   GLuint pad:3;
 };
 
 
 /* Instruction destination register */
 struct vp_dst_register
 {
-   enum register_file File;  /* which register file */
-   GLint Index;              /* index into register file */
-   GLboolean WriteMask[4];
+   GLuint File:4;
+   GLuint Index:8;
+   GLuint WriteMask:4;
+   GLuint pad:16;
 };
 
 
 /* Vertex program instruction */
 struct vp_instruction
 {
-   enum vp_opcode Opcode;
-   struct vp_src_register SrcReg[3];
-   struct vp_dst_register DstReg;
+   GLshort Opcode;
 #if FEATURE_MESA_program_debug
-   GLint StringPos;
+   GLshort StringPos;
 #endif
    void *Data;  /* some arbitrary data, only used for PRINT instruction now */
+   struct vp_src_register SrcReg[3];
+   struct vp_dst_register DstReg;
 };
 
 
-- 
cgit v1.2.3