From fe57ed4f2566e30384d0c786998842405d8e8990 Mon Sep 17 00:00:00 2001 From: Roland Scheidegger Date: Thu, 1 Jun 2006 22:56:40 +0000 Subject: Fix extended swizzling in vertex programs by introducing special swizzle instruction, extend the 2 bit rsw field to 3 bit like used in other places. While here, also fix up rsw (negation), dph and try to fix up rsq with negative values (doesn't work, bug seems elsewhere) in the sse codegen code. --- src/mesa/tnl/t_vb_arbprogram.h | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'src/mesa/tnl/t_vb_arbprogram.h') diff --git a/src/mesa/tnl/t_vb_arbprogram.h b/src/mesa/tnl/t_vb_arbprogram.h index 60786d6a01..dab725d7f7 100644 --- a/src/mesa/tnl/t_vb_arbprogram.h +++ b/src/mesa/tnl/t_vb_arbprogram.h @@ -61,7 +61,7 @@ #define REG_IN31 63 #define REG_ID 64 /* 0,0,0,1 */ #define REG_ONES 65 /* 1,1,1,1 */ -#define REG_SWZ 66 /* -1,1,0,0 */ +#define REG_SWZ 66 /* 1,-1,0,0 */ #define REG_NEG 67 /* -1,-1,-1,-1 */ #define REG_LIT 68 /* 1,0,0,1 */ #define REG_LIT2 69 /* 1,0,0,1 */ @@ -98,7 +98,7 @@ union instruction { GLuint file0:2; GLuint idx0:7; GLuint neg:4; - GLuint swz:8; /* xyzw only */ + GLuint swz:12; /* xyzw01 */ } rsw; struct { @@ -114,11 +114,8 @@ union instruction { /** - * Reduced swizzle is a 2-bit field; only X/Y/Z/W are allowed, not 0/1. + * Reduced swizzle is a 3-bit field, for simplicity same as normal swizzle, X/Y/Z/W/0/1 allowed. */ -#define RSW_NOOP ((0<<0) | (1<<2) | (2<<4) | (3<<6)) -#define GET_RSW(swz, idx) (((swz) >> ((idx)*2)) & 0x3) - struct input { GLuint idx; -- cgit v1.2.3