From 4e7766992607db215430ee388751f32692401c0a Mon Sep 17 00:00:00 2001
From: Roland Scheidegger <rscheidegger@gmx.ch>
Date: Sat, 25 Feb 2006 02:03:12 +0000
Subject: Add all pci ids known by ddx to radeon dri driver. Remove the entries
not known by ddx (probably secondary ids, non-existant cards and similar).
Add rs400 to the family enum, and configure the rv410 like a 2 quad chip (?)
---
src/mesa/drivers/dri/r300/r300_reg.h | 1 +
src/mesa/drivers/dri/r300/r300_state.c | 8 ++-
src/mesa/drivers/dri/radeon/radeon_chipset.h | 104 +++++++++++++++++++--------
src/mesa/drivers/dri/radeon/radeon_screen.c | 74 ++++++++++++++++---
4 files changed, 145 insertions(+), 42 deletions(-)
(limited to 'src/mesa')
diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h
index 3bed99e456..ddf2ab72b9 100644
--- a/src/mesa/drivers/dri/r300/r300_reg.h
+++ b/src/mesa/drivers/dri/r300/r300_reg.h
@@ -391,6 +391,7 @@ I am fairly certain that they are correct unless stated otherwise in comments.
# define R300_GB_TILE_PIPE_COUNT_RV300 0
# define R300_GB_TILE_PIPE_COUNT_R300 (3<<1)
# define R300_GB_TILE_PIPE_COUNT_R420 (7<<1)
+# define R300_GB_TILE_PIPE_COUNT_RV410 (3<<1)
# define R300_GB_TILE_SIZE_8 0
# define R300_GB_TILE_SIZE_16 (1<<4)
# define R300_GB_TILE_SIZE_32 (2<<4)
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index 06513b17f1..f604ce427d 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -1864,6 +1864,7 @@ void r300ResetHwState(r300ContextPtr r300)
r300->hw.unk2220.cmd[3] = r300PackFloat32(1.0);
r300->hw.unk2220.cmd[4] = r300PackFloat32(1.0);
+ /* what about other chips than r300 or rv350??? */
if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R300)
r300->hw.unk2288.cmd[1] = R300_2288_R300;
else
@@ -1886,10 +1887,15 @@ void r300ResetHwState(r300ContextPtr r300)
r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_0] = 0x66666666;
r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_1] = 0x06666666;
- if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R300)
+ if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R300) ||
+ (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R350))
r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] = R300_GB_TILE_ENABLE
| R300_GB_TILE_PIPE_COUNT_R300
| R300_GB_TILE_SIZE_16;
+ else if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410)
+ r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] = R300_GB_TILE_ENABLE
+ | R300_GB_TILE_PIPE_COUNT_RV410
+ | R300_GB_TILE_SIZE_16;
else if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420)
r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] = R300_GB_TILE_ENABLE
| R300_GB_TILE_PIPE_COUNT_R420
diff --git a/src/mesa/drivers/dri/radeon/radeon_chipset.h b/src/mesa/drivers/dri/radeon/radeon_chipset.h
index fd08ecf93f..7318099093 100644
--- a/src/mesa/drivers/dri/radeon/radeon_chipset.h
+++ b/src/mesa/drivers/dri/radeon/radeon_chipset.h
@@ -9,6 +9,11 @@
* r300 includes R300, RV350, RV370.
* (RS* denotes IGP)
*/
+#define PCI_CHIP_RV380_3150 0x3150
+#define PCI_CHIP_RV380_3152 0x3152
+#define PCI_CHIP_RV380_3154 0x3154
+#define PCI_CHIP_RV380_3E50 0x3E50
+#define PCI_CHIP_RV380_3E54 0x3E54
#define PCI_CHIP_RS100_4136 0x4136
#define PCI_CHIP_RS200_4137 0x4137
#define PCI_CHIP_R300_AD 0x4144
@@ -24,7 +29,7 @@
#define PCI_CHIP_RV350_AR 0x4152
#define PCI_CHIP_RV350_AS 0x4153
#define PCI_CHIP_RV350_AT 0x4154
-#define PCI_CHIP_RV350_AU 0x4155
+#define PCI_CHIP_RV350_AU 0x4155
#define PCI_CHIP_RV350_AV 0x4156
#define PCI_CHIP_RS250_4237 0x4237
#define PCI_CHIP_R200_BB 0x4242
@@ -32,29 +37,29 @@
#define PCI_CHIP_RS100_4336 0x4336
#define PCI_CHIP_RS200_4337 0x4337
#define PCI_CHIP_RS250_4437 0x4437
-#define PCI_CHIP_RV250_Id 0x4964
-#define PCI_CHIP_RV250_Ie 0x4965
#define PCI_CHIP_RV250_If 0x4966
#define PCI_CHIP_RV250_Ig 0x4967
-#define PCI_CHIP_RV410_5E4B 0x5E4B
-#define PCI_CHIP_R420_JH 0x4A48
-#define PCI_CHIP_R420_JI 0x4A49
-#define PCI_CHIP_R420_JJ 0x4A4A
-#define PCI_CHIP_R420_JK 0x4A4B
-#define PCI_CHIP_R420_JL 0x4A4C
-#define PCI_CHIP_R420_JM 0x4A4D
-#define PCI_CHIP_R420_JN 0x4A4E
+#define PCI_CHIP_R420_JH 0x4A48
+#define PCI_CHIP_R420_JI 0x4A49
+#define PCI_CHIP_R420_JJ 0x4A4A
+#define PCI_CHIP_R420_JK 0x4A4B
+#define PCI_CHIP_R420_JL 0x4A4C
+#define PCI_CHIP_R420_JM 0x4A4D
+#define PCI_CHIP_R420_JN 0x4A4E
#define PCI_CHIP_R420_JO 0x4A4F
-#define PCI_CHIP_R420_JP 0x4A50
+#define PCI_CHIP_R420_JP 0x4A50
+#define PCI_CHIP_R420_JT 0x4A54
+#define PCI_CHIP_R481_4B49 0x4B49
+#define PCI_CHIP_R481_4B4A 0x4B4A
+#define PCI_CHIP_R481_4B4B 0x4B4B
+#define PCI_CHIP_R481_4B4C 0x4B4C
#define PCI_CHIP_RADEON_LW 0x4C57
#define PCI_CHIP_RADEON_LX 0x4C58
#define PCI_CHIP_RADEON_LY 0x4C59
#define PCI_CHIP_RADEON_LZ 0x4C5A
#define PCI_CHIP_RV250_Ld 0x4C64
-#define PCI_CHIP_RV250_Le 0x4C65
#define PCI_CHIP_RV250_Lf 0x4C66
#define PCI_CHIP_RV250_Lg 0x4C67
-#define PCI_CHIP_RV250_Ln 0x4C6E
#define PCI_CHIP_R300_ND 0x4E44
#define PCI_CHIP_R300_NE 0x4E45
#define PCI_CHIP_R300_NF 0x4E46
@@ -73,37 +78,75 @@
#define PCI_CHIP_RADEON_QE 0x5145
#define PCI_CHIP_RADEON_QF 0x5146
#define PCI_CHIP_RADEON_QG 0x5147
-#define PCI_CHIP_RADEON_QY 0x5159
-#define PCI_CHIP_RADEON_QZ 0x515A
-#define PCI_CHIP_RN50_515E 0x515E
#define PCI_CHIP_R200_QH 0x5148
-#define PCI_CHIP_R200_QI 0x5149
-#define PCI_CHIP_R200_QJ 0x514A
-#define PCI_CHIP_R200_QK 0x514B
#define PCI_CHIP_R200_QL 0x514C
#define PCI_CHIP_R200_QM 0x514D
-#define PCI_CHIP_R200_QN 0x514E
-#define PCI_CHIP_R200_QO 0x514F
#define PCI_CHIP_RV200_QW 0x5157
#define PCI_CHIP_RV200_QX 0x5158
+#define PCI_CHIP_RADEON_QY 0x5159
+#define PCI_CHIP_RADEON_QZ 0x515A
+#define PCI_CHIP_RN50_515E 0x515E
#define PCI_CHIP_RV370_5460 0x5460
-#define PCI_CHIP_RV370_5464 0x5464
+#define PCI_CHIP_RV370_5462 0x5462
+#define PCI_CHIP_RV370_5464 0x5464
+#define PCI_CHIP_R423_UH 0x5548
+#define PCI_CHIP_R423_UI 0x5549
+#define PCI_CHIP_R423_UJ 0x554A
+#define PCI_CHIP_R423_UK 0x554B
+#define PCI_CHIP_R430_554C 0x554C
+#define PCI_CHIP_R430_554D 0x554D
+#define PCI_CHIP_R430_554E 0x554E
+#define PCI_CHIP_R430_554F 0x554F
+#define PCI_CHIP_R423_5550 0x5550
+#define PCI_CHIP_R423_UQ 0x5551
+#define PCI_CHIP_R423_UR 0x5552
+#define PCI_CHIP_R423_UT 0x5554
+#define PCI_CHIP_RV410_564A 0x564A
+#define PCI_CHIP_RV410_564B 0x564B
+#define PCI_CHIP_RV410_564F 0x564F
+#define PCI_CHIP_RV410_5652 0x5652
+#define PCI_CHIP_RV410_5653 0x5653
#define PCI_CHIP_RS300_5834 0x5834
#define PCI_CHIP_RS300_5835 0x5835
-#define PCI_CHIP_RS300_5836 0x5836
-#define PCI_CHIP_RS300_5837 0x5837
+#define PCI_CHIP_RS480_5954 0x5954
+#define PCI_CHIP_RS480_5955 0x5955
#define PCI_CHIP_RV280_5960 0x5960
#define PCI_CHIP_RV280_5961 0x5961
#define PCI_CHIP_RV280_5962 0x5962
#define PCI_CHIP_RV280_5964 0x5964
-#define PCI_CHIP_RV280_5965 0x5965
+#define PCI_CHIP_RV280_5965 0x5965
#define PCI_CHIP_RN50_5969 0x5969
-#define PCI_CHIP_RV370_5B60 0x5B60
-#define PCI_CHIP_RV370_5B62 0x5B62
-#define PCI_CHIP_RV370_5B64 0x5B64
-#define PCI_CHIP_RV370_5B65 0x5B65
+#define PCI_CHIP_RS482_5974 0x5974
+#define PCI_CHIP_RS482_5975 0x5975
+#define PCI_CHIP_RS400_5A41 0x5A41
+#define PCI_CHIP_RS400_5A42 0x5A42
+#define PCI_CHIP_RC410_5A61 0x5A61
+#define PCI_CHIP_RC410_5A62 0x5A62
+#define PCI_CHIP_RV370_5B60 0x5B60
+#define PCI_CHIP_RV370_5B62 0x5B62
+#define PCI_CHIP_RV370_5B63 0x5B63
+#define PCI_CHIP_RV370_5B64 0x5B64
+#define PCI_CHIP_RV370_5B65 0x5B65
#define PCI_CHIP_RV280_5C61 0x5C61
#define PCI_CHIP_RV280_5C63 0x5C63
+#define PCI_CHIP_R430_5D48 0x5D48
+#define PCI_CHIP_R430_5D49 0x5D49
+#define PCI_CHIP_R430_5D4A 0x5D4A
+#define PCI_CHIP_R480_5D4C 0x5D4C
+#define PCI_CHIP_R480_5D4D 0x5D4D
+#define PCI_CHIP_R480_5D4E 0x5D4E
+#define PCI_CHIP_R480_5D4F 0x5D4F
+#define PCI_CHIP_R480_5D50 0x5D50
+#define PCI_CHIP_R480_5D52 0x5D52
+#define PCI_CHIP_R423_5D57 0x5D57
+#define PCI_CHIP_RV410_5E48 0x5E48
+#define PCI_CHIP_RV410_5E4A 0x5E4A
+#define PCI_CHIP_RV410_5E4B 0x5E4B
+#define PCI_CHIP_RV410_5E4C 0x5E4C
+#define PCI_CHIP_RV410_5E4D 0x5E4D
+#define PCI_CHIP_RV410_5E4F 0x5E4F
+#define PCI_CHIP_RS350_7834 0x7834
+#define PCI_CHIP_RS350_7835 0x7835
enum {
CHIP_FAMILY_R100,
@@ -121,6 +164,7 @@ enum {
CHIP_FAMILY_RV380,
CHIP_FAMILY_R420,
CHIP_FAMILY_RV410,
+ CHIP_FAMILY_RS400,
CHIP_FAMILY_LAST
};
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index d7c6efd349..e0ba164356 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -474,23 +474,15 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
case PCI_CHIP_R200_BB:
case PCI_CHIP_R200_BC:
case PCI_CHIP_R200_QH:
- case PCI_CHIP_R200_QI:
- case PCI_CHIP_R200_QJ:
- case PCI_CHIP_R200_QK:
case PCI_CHIP_R200_QL:
case PCI_CHIP_R200_QM:
- case PCI_CHIP_R200_QN:
- case PCI_CHIP_R200_QO:
screen->chip_family = CHIP_FAMILY_R200;
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
- case PCI_CHIP_RV250_Id:
- case PCI_CHIP_RV250_Ie:
case PCI_CHIP_RV250_If:
case PCI_CHIP_RV250_Ig:
case PCI_CHIP_RV250_Ld:
- case PCI_CHIP_RV250_Le:
case PCI_CHIP_RV250_Lf:
case PCI_CHIP_RV250_Lg:
screen->chip_family = CHIP_FAMILY_RV250;
@@ -510,8 +502,8 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
case PCI_CHIP_RS300_5834:
case PCI_CHIP_RS300_5835:
- case PCI_CHIP_RS300_5836:
- case PCI_CHIP_RS300_5837:
+ case PCI_CHIP_RS350_7834:
+ case PCI_CHIP_RS350_7835:
screen->chip_family = CHIP_FAMILY_RS300;
break;
@@ -557,11 +549,18 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
break;
case PCI_CHIP_RV370_5460:
+ case PCI_CHIP_RV370_5462:
case PCI_CHIP_RV370_5464:
case PCI_CHIP_RV370_5B60:
case PCI_CHIP_RV370_5B62:
+ case PCI_CHIP_RV370_5B63:
case PCI_CHIP_RV370_5B64:
case PCI_CHIP_RV370_5B65:
+ case PCI_CHIP_RV380_3150:
+ case PCI_CHIP_RV380_3152:
+ case PCI_CHIP_RV380_3154:
+ case PCI_CHIP_RV380_3E50:
+ case PCI_CHIP_RV380_3E54:
screen->chip_family = CHIP_FAMILY_RV380;
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
@@ -575,11 +574,64 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
case PCI_CHIP_R420_JM:
case PCI_CHIP_R420_JO:
case PCI_CHIP_R420_JP:
- case PCI_CHIP_RV410_5E4B:
+ case PCI_CHIP_R420_JT:
+ case PCI_CHIP_R481_4B49:
+ case PCI_CHIP_R481_4B4A:
+ case PCI_CHIP_R481_4B4B:
+ case PCI_CHIP_R481_4B4C:
+ case PCI_CHIP_R423_UH:
+ case PCI_CHIP_R423_UI:
+ case PCI_CHIP_R423_UJ:
+ case PCI_CHIP_R423_UK:
+ case PCI_CHIP_R430_554C:
+ case PCI_CHIP_R430_554D:
+ case PCI_CHIP_R430_554E:
+ case PCI_CHIP_R430_554F:
+ case PCI_CHIP_R423_5550:
+ case PCI_CHIP_R423_UQ:
+ case PCI_CHIP_R423_UR:
+ case PCI_CHIP_R423_UT:
+ case PCI_CHIP_R430_5D48:
+ case PCI_CHIP_R430_5D49:
+ case PCI_CHIP_R430_5D4A:
+ case PCI_CHIP_R480_5D4C:
+ case PCI_CHIP_R480_5D4D:
+ case PCI_CHIP_R480_5D4E:
+ case PCI_CHIP_R480_5D4F:
+ case PCI_CHIP_R480_5D50:
+ case PCI_CHIP_R480_5D52:
+ case PCI_CHIP_R423_5D57:
screen->chip_family = CHIP_FAMILY_R420;
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
+ case PCI_CHIP_RV410_564A:
+ case PCI_CHIP_RV410_564B:
+ case PCI_CHIP_RV410_564F:
+ case PCI_CHIP_RV410_5652:
+ case PCI_CHIP_RV410_5653:
+ case PCI_CHIP_RV410_5E48:
+ case PCI_CHIP_RV410_5E4A:
+ case PCI_CHIP_RV410_5E4B:
+ case PCI_CHIP_RV410_5E4C:
+ case PCI_CHIP_RV410_5E4D:
+ case PCI_CHIP_RV410_5E4F:
+ screen->chip_family = CHIP_FAMILY_RV410;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_RS480_5954:
+ case PCI_CHIP_RS480_5955:
+ case PCI_CHIP_RS482_5974:
+ case PCI_CHIP_RS482_5975:
+ case PCI_CHIP_RS400_5A41:
+ case PCI_CHIP_RS400_5A42:
+ case PCI_CHIP_RC410_5A61:
+ case PCI_CHIP_RC410_5A62:
+ screen->chip_family = CHIP_FAMILY_RS400;
+ fprintf(stderr, "Warning, xpress200 detected. Probably won't work.\n");
+ break;
+
default:
fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
dri_priv->deviceID);
--
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