From 35707dbe57873adb5a8088cd47c13bd216e143e4 Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Thu, 12 Apr 2007 09:43:00 +0800 Subject: Initial 965 GLSL support --- src/mesa/drivers/dri/i965/brw_clip.h | 4 +- src/mesa/drivers/dri/i965/brw_context.c | 47 ++++++++ src/mesa/drivers/dri/i965/brw_eu.h | 3 +- src/mesa/drivers/dri/i965/brw_eu_emit.c | 2 +- src/mesa/drivers/dri/i965/brw_gs.h | 4 +- src/mesa/drivers/dri/i965/brw_sf.h | 4 +- src/mesa/drivers/dri/i965/brw_vs.h | 1 + src/mesa/drivers/dri/i965/brw_vs_emit.c | 184 ++++++++++++++++++++++-------- src/mesa/drivers/dri/i965/brw_vs_tnl.c | 2 +- src/mesa/drivers/dri/i965/brw_wm.c | 4 + src/mesa/drivers/dri/i965/brw_wm_emit.c | 82 ++++++++++--- src/mesa/drivers/dri/i965/brw_wm_pass0.c | 4 + src/mesa/drivers/dri/i965/brw_wm_pass1.c | 5 +- src/mesa/drivers/dri/i965/intel_context.c | 4 + src/mesa/shader/slang/slang_codegen.c | 1 + 15 files changed, 276 insertions(+), 75 deletions(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_clip.h b/src/mesa/drivers/dri/i965/brw_clip.h index 49b2770a51..2a65697325 100644 --- a/src/mesa/drivers/dri/i965/brw_clip.h +++ b/src/mesa/drivers/dri/i965/brw_clip.h @@ -42,7 +42,7 @@ * up polygon offset and flatshading at this point: */ struct brw_clip_prog_key { - GLuint attrs:16; + GLuint attrs:32; GLuint primitive:4; GLuint nr_userclip:3; GLuint do_flat_shading:1; @@ -51,7 +51,7 @@ struct brw_clip_prog_key { GLuint fill_ccw:2; /* includes cull information */ GLuint offset_cw:1; GLuint offset_ccw:1; - GLuint pad0:1; + GLuint pad0:17; GLuint copy_bfc_cw:1; GLuint copy_bfc_ccw:1; diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 397a9bd3f5..badf178b68 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -44,6 +44,8 @@ #include "api_noop.h" #include "vtxfmt.h" +#include "shader/shader_api.h" + /*************************************** * Mesa's Driver Functions ***************************************/ @@ -60,12 +62,57 @@ static const struct dri_extension brw_extensions[] = { NULL, NULL } }; +static void brwLinkProgram(GLcontext *ctx, GLuint program) +{ + struct brw_context *brw = brw_context(ctx); + struct brw_vertex_program *vert_prog; + struct brw_fragment_program *frag_prog; + struct gl_shader_program *sh_prog; + _mesa_link_program(ctx, program); + + sh_prog = _mesa_lookup_shader_program(ctx, program); + if (sh_prog) { + sh_prog->FragmentProgram = + _mesa_realloc(sh_prog->FragmentProgram, + sizeof(struct gl_fragment_program), + sizeof(struct brw_fragment_program)); + frag_prog = (struct brw_fragment_program *)sh_prog->FragmentProgram; + frag_prog->id = brw->program_id++; + sh_prog->VertexProgram = _mesa_realloc(sh_prog->VertexProgram, + sizeof(struct gl_vertex_program), + sizeof(struct brw_vertex_program)); + vert_prog = (struct brw_vertex_program *)sh_prog->VertexProgram; + vert_prog->id = brw->program_id++; + } +} + +static void brwUseProgram(GLcontext *ctx, GLuint program) +{ + struct brw_context *brw = brw_context(ctx); + struct gl_shader_program *sh_prog; + _mesa_use_program(ctx, program); + sh_prog = ctx->Shader.CurrentProgram; + if (sh_prog) { + ctx->VertexProgram.Enabled = GL_TRUE; + ctx->FragmentProgram.Enabled = GL_TRUE; + brw->attribs.VertexProgram->Current = sh_prog->VertexProgram; + brw->attribs.FragmentProgram->Current = sh_prog->FragmentProgram; + brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM; + brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM; + } +} +static void brwInitProgFuncs( struct dd_function_table *functions ) +{ + functions->UseProgram = brwUseProgram; + functions->LinkProgram = brwLinkProgram; +} static void brwInitDriverFunctions( struct dd_function_table *functions ) { intelInitDriverFunctions( functions ); brwInitTextureFuncs( functions ); brwInitFragProgFuncs( functions ); + brwInitProgFuncs( functions ); } diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index 52f89d577c..144f209eda 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -860,5 +860,6 @@ void brw_math_invert( struct brw_compile *p, struct brw_reg dst, struct brw_reg src); - +void brw_set_src1( struct brw_instruction *insn, + struct brw_reg reg ); #endif diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 9992b47d8a..0c04bf6c62 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -164,7 +164,7 @@ static void brw_set_src0( struct brw_instruction *insn, } -static void brw_set_src1( struct brw_instruction *insn, +void brw_set_src1( struct brw_instruction *insn, struct brw_reg reg ) { assert(reg.file != BRW_MESSAGE_REGISTER_FILE); diff --git a/src/mesa/drivers/dri/i965/brw_gs.h b/src/mesa/drivers/dri/i965/brw_gs.h index 29a4e80ce1..18a4537c32 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.h +++ b/src/mesa/drivers/dri/i965/brw_gs.h @@ -40,11 +40,11 @@ #define MAX_GS_VERTS (4) struct brw_gs_prog_key { + GLuint attrs:32; GLuint primitive:4; - GLuint attrs:16; GLuint hint_gs_always:1; GLuint need_gs_prog:1; - GLuint pad:10; + GLuint pad:26; }; struct brw_gs_compile { diff --git a/src/mesa/drivers/dri/i965/brw_sf.h b/src/mesa/drivers/dri/i965/brw_sf.h index fb72b84ba8..23b89684b2 100644 --- a/src/mesa/drivers/dri/i965/brw_sf.h +++ b/src/mesa/drivers/dri/i965/brw_sf.h @@ -45,12 +45,12 @@ #define SF_UNFILLED_TRIS 3 struct brw_sf_prog_key { + GLuint attrs:32; GLuint primitive:2; GLuint do_twoside_color:1; GLuint do_flat_shading:1; - GLuint attrs:16; GLuint frontface_ccw:1; - GLuint pad:11; + GLuint pad:27; }; diff --git a/src/mesa/drivers/dri/i965/brw_vs.h b/src/mesa/drivers/dri/i965/brw_vs.h index fdb5785d67..c31a1b6366 100644 --- a/src/mesa/drivers/dri/i965/brw_vs.h +++ b/src/mesa/drivers/dri/i965/brw_vs.h @@ -67,6 +67,7 @@ struct brw_vs_compile { struct brw_reg r1; struct brw_reg regs[PROGRAM_ADDRESS+1][128]; struct brw_reg tmp; + struct brw_reg ret; struct brw_reg userplane[6]; diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 6eb11b19ad..613ee03b2a 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -134,6 +134,17 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c ) WRITEMASK_X); reg++; } + + c->ret = brw_reg(BRW_GENERAL_REGISTER_FILE, + reg, + 0, + BRW_REGISTER_TYPE_D, + BRW_VERTICAL_STRIDE_8, + BRW_WIDTH_8, + BRW_HORIZONTAL_STRIDE_1, + BRW_SWIZZLE_XXXX, + WRITEMASK_X); + reg++; /* Some opcodes need an internal temporary: @@ -213,57 +224,68 @@ static void unalias2( struct brw_vs_compile *c, } } +static void emit_sop( struct brw_compile *p, + struct brw_reg dst, + struct brw_reg arg0, + struct brw_reg arg1, + GLuint cond) +{ + brw_push_insn_state(p); + brw_CMP(p, brw_null_reg(), cond, arg0, arg1); + brw_set_predicate_control(p, BRW_PREDICATE_NONE); + brw_MOV(p, dst, brw_imm_f(1.0f)); + brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); + brw_MOV(p, dst, brw_imm_f(0.0f)); + brw_pop_insn_state(p); +} +static void emit_seq( struct brw_compile *p, + struct brw_reg dst, + struct brw_reg arg0, + struct brw_reg arg1 ) +{ + emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_EQ); +} - +static void emit_sne( struct brw_compile *p, + struct brw_reg dst, + struct brw_reg arg0, + struct brw_reg arg1 ) +{ + emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_NEQ); +} static void emit_slt( struct brw_compile *p, struct brw_reg dst, struct brw_reg arg0, struct brw_reg arg1 ) { - /* Could be done with an if/else/endif, but this method uses half - * the instructions. Note that we are careful to reference the - * arguments before writing the dest. That means we emit the - * instructions in an odd order and have to play with the flag - * values. - */ - brw_push_insn_state(p); - brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_GE, arg0, arg1); - - /* Write all values to 1: - */ - brw_set_predicate_control(p, BRW_PREDICATE_NONE); - brw_MOV(p, dst, brw_imm_f(1.0)); + emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_L); +} - /* Where the test succeeded, overwite with zero: - */ - brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); - brw_MOV(p, dst, brw_imm_f(0.0)); - brw_pop_insn_state(p); +static void emit_sle( struct brw_compile *p, + struct brw_reg dst, + struct brw_reg arg0, + struct brw_reg arg1 ) +{ + emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_LE); } +static void emit_sgt( struct brw_compile *p, + struct brw_reg dst, + struct brw_reg arg0, + struct brw_reg arg1 ) +{ + emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_G); +} static void emit_sge( struct brw_compile *p, struct brw_reg dst, struct brw_reg arg0, struct brw_reg arg1 ) { - brw_push_insn_state(p); - brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_GE, arg0, arg1); - - /* Write all values to zero: - */ - brw_set_predicate_control(p, BRW_PREDICATE_NONE); - brw_MOV(p, dst, brw_imm_f(0)); - - /* Where the test succeeded, overwite with 1: - */ - brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); - brw_MOV(p, dst, brw_imm_f(1.0)); - brw_pop_insn_state(p); + emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_GE); } - static void emit_max( struct brw_compile *p, struct brw_reg dst, struct brw_reg arg0, @@ -592,9 +614,13 @@ static struct brw_reg get_reg( struct brw_vs_compile *c, case PROGRAM_TEMPORARY: case PROGRAM_INPUT: case PROGRAM_OUTPUT: - case PROGRAM_STATE_VAR: assert(c->regs[file][index].nr != 0); return c->regs[file][index]; + case PROGRAM_STATE_VAR: + case PROGRAM_CONSTANT: + case PROGRAM_UNIFORM: + assert(c->regs[PROGRAM_STATE_VAR][index].nr != 0); + return c->regs[PROGRAM_STATE_VAR][index]; case PROGRAM_ADDRESS: assert(index == 0); return c->regs[file][index]; @@ -891,17 +917,46 @@ static void emit_vertex_write( struct brw_vs_compile *c) } - - +static void +post_vs_emit( struct brw_vs_compile *c, struct brw_instruction *end_inst ) +{ + GLuint nr_insns = c->vp->program.Base.NumInstructions; + GLuint insn, target_insn; + struct prog_instruction *inst1, *inst2; + struct brw_instruction *brw_inst1, *brw_inst2; + int offset; + for (insn = 0; insn < nr_insns; insn++) { + inst1 = &c->vp->program.Base.Instructions[insn]; + brw_inst1 = inst1->Data; + switch (inst1->Opcode) { + case OPCODE_CAL: + case OPCODE_BRA: + target_insn = inst1->BranchTarget; + inst2 = &c->vp->program.Base.Instructions[target_insn]; + brw_inst2 = inst2->Data; + offset = brw_inst2 - brw_inst1; + brw_set_src1(brw_inst1, brw_imm_d(offset*16)); + break; + case OPCODE_END: + offset = end_inst - brw_inst1; + brw_set_src1(brw_inst1, brw_imm_d(offset*16)); + break; + default: + break; + } + } +} /* Emit the fragment program instructions here. */ -void brw_vs_emit( struct brw_vs_compile *c ) +void brw_vs_emit(struct brw_vs_compile *c ) { +#define MAX_IFSN 32 struct brw_compile *p = &c->func; GLuint nr_insns = c->vp->program.Base.NumInstructions; - GLuint insn; - + GLuint insn, if_insn = 0; + struct brw_instruction *end_inst; + struct brw_instruction *if_inst[32]; if (INTEL_DEBUG & DEBUG_VS) { _mesa_printf("\n\n\nvs-emit:\n"); @@ -924,6 +979,7 @@ void brw_vs_emit( struct brw_vs_compile *c ) /* Get argument regs. SWZ is special and does this itself. */ + inst->Data = &p->store[p->nr_insn]; if (inst->Opcode != OPCODE_SWZ) for (i = 0; i < 3; i++) args[i] = get_arg(c, inst->SrcReg[i]); @@ -934,7 +990,6 @@ void brw_vs_emit( struct brw_vs_compile *c ) */ dst = get_dst(c, inst->DstReg); - switch (inst->Opcode) { case OPCODE_ABS: brw_MOV(p, dst, brw_abs(args[0])); @@ -1003,12 +1058,25 @@ void brw_vs_emit( struct brw_vs_compile *c ) case OPCODE_RSQ: emit_math1(c, BRW_MATH_FUNCTION_RSQ, dst, args[0], BRW_MATH_PRECISION_FULL); break; + + case OPCODE_SEQ: + emit_seq(p, dst, args[0], args[1]); + break; + case OPCODE_SNE: + emit_sne(p, dst, args[0], args[1]); + break; case OPCODE_SGE: emit_sge(p, dst, args[0], args[1]); break; + case OPCODE_SGT: + emit_sgt(p, dst, args[0], args[1]); + break; case OPCODE_SLT: emit_slt(p, dst, args[0], args[1]); break; + case OPCODE_SLE: + emit_sle(p, dst, args[0], args[1]); + break; case OPCODE_SUB: brw_ADD(p, dst, args[0], negate(args[1])); break; @@ -1021,21 +1089,45 @@ void brw_vs_emit( struct brw_vs_compile *c ) case OPCODE_XPD: emit_xpd(p, dst, args[0], args[1]); break; + case OPCODE_IF: + assert(if_insn < MAX_IFSN); + if_inst[if_insn++] = brw_IF(p, BRW_EXECUTE_8); + break; + case OPCODE_ELSE: + brw_ELSE(p, if_inst[if_insn]); + break; + case OPCODE_ENDIF: + assert(if_insn > 0); + brw_ENDIF(p, if_inst[--if_insn]); + break; + case OPCODE_BRA: + brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); + brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16)); + brw_set_predicate_control_flag_value(p, 0xFF); + break; + case OPCODE_CAL: + brw_ADD(p, c->ret, brw_ip_reg(), brw_imm_d(2*16)); + inst->Data = &p->store[p->nr_insn]; + brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16)); + break; + case OPCODE_RET: + brw_MOV(p, brw_ip_reg(), c->ret); case OPCODE_END: + brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16)); + break; case OPCODE_PRINT: + case OPCODE_BGNSUB: + case OPCODE_ENDSUB: break; default: + _mesa_printf("Unsupport opcode %d in vertex shader\n", inst->Opcode); break; } release_tmps(c); } + end_inst = &p->store[p->nr_insn]; emit_vertex_write(c); - + post_vs_emit(c, end_inst); } - - - - - diff --git a/src/mesa/drivers/dri/i965/brw_vs_tnl.c b/src/mesa/drivers/dri/i965/brw_vs_tnl.c index 35adc4846a..bc0526fab6 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_tnl.c +++ b/src/mesa/drivers/dri/i965/brw_vs_tnl.c @@ -855,7 +855,7 @@ static struct ureg calculate_light_attenuation( struct tnl_program *p, struct ureg slt = get_temp(p); emit_op2(p, OPCODE_DP3, spot, 0, ureg_negate(VPpli), spot_dir_norm); - emit_op2(p, OPCODE_SLT, slt, 0, swizzle1(spot_dir_norm,W), spot); + emit_op2(p, OPCODE_SLT, slt, 0, spot, swizzle1(spot_dir_norm,W)); emit_op2(p, OPCODE_POW, spot, 0, spot, swizzle1(attenuation, W)); emit_op2(p, OPCODE_MUL, att, 0, slt, spot); diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 1497dc7968..a02a0a23af 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -66,7 +66,11 @@ GLuint brw_wm_nr_args( GLuint opcode ) case OPCODE_POW: case OPCODE_SUB: case OPCODE_SGE: + case OPCODE_SGT: + case OPCODE_SLE: case OPCODE_SLT: + case OPCODE_SEQ: + case OPCODE_SNE: case OPCODE_ADD: case OPCODE_MAX: case OPCODE_MIN: diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index fd60515972..197a0ae13d 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -343,11 +343,10 @@ static void emit_lrp( struct brw_compile *p, } } } - - -static void emit_slt( struct brw_compile *p, +static void emit_sop( struct brw_compile *p, const struct brw_reg *dst, GLuint mask, + GLuint cond, const struct brw_reg *arg0, const struct brw_reg *arg1 ) { @@ -356,34 +355,66 @@ static void emit_slt( struct brw_compile *p, for (i = 0; i < 4; i++) { if (mask & (1<opcode); } for (i = 0; i < 4; i++) diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass0.c b/src/mesa/drivers/dri/i965/brw_wm_pass0.c index 00f6f6b9a4..1bfae5a069 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_pass0.c +++ b/src/mesa/drivers/dri/i965/brw_wm_pass0.c @@ -168,6 +168,7 @@ static const struct brw_wm_ref *pass0_get_reg( struct brw_wm_compile *c, case PROGRAM_PAYLOAD: case PROGRAM_TEMPORARY: case PROGRAM_OUTPUT: + case PROGRAM_VARYING: break; case PROGRAM_LOCAL_PARAM: @@ -179,6 +180,8 @@ static const struct brw_wm_ref *pass0_get_reg( struct brw_wm_compile *c, break; case PROGRAM_STATE_VAR: + case PROGRAM_UNIFORM: + case PROGRAM_CONSTANT: case PROGRAM_NAMED_PARAM: { struct gl_program_parameter_list *plist = c->fp->program.Base.Parameters; @@ -197,6 +200,7 @@ static const struct brw_wm_ref *pass0_get_reg( struct brw_wm_compile *c, break; case PROGRAM_STATE_VAR: + case PROGRAM_UNIFORM: /* These may change from run to run: */ ref = get_param_ref(c, &plist->ParameterValues[idx][component] ); diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass1.c b/src/mesa/drivers/dri/i965/brw_wm_pass1.c index d668def700..26c044d400 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_pass1.c +++ b/src/mesa/drivers/dri/i965/brw_wm_pass1.c @@ -155,7 +155,11 @@ void brw_wm_pass1( struct brw_wm_compile *c ) case OPCODE_SUB: case OPCODE_SLT: + case OPCODE_SLE: case OPCODE_SGE: + case OPCODE_SGT: + case OPCODE_SEQ: + case OPCODE_SNE: case OPCODE_ADD: case OPCODE_MAX: case OPCODE_MIN: @@ -257,7 +261,6 @@ void brw_wm_pass1( struct brw_wm_compile *c ) case OPCODE_DST: case OPCODE_TXP: default: - assert(0); break; } diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c index 10eb9a2e28..a94c1dc6d5 100644 --- a/src/mesa/drivers/dri/i965/intel_context.c +++ b/src/mesa/drivers/dri/i965/intel_context.c @@ -81,6 +81,7 @@ int INTEL_DEBUG = (0); #define need_GL_EXT_fog_coord #define need_GL_EXT_multi_draw_arrays #define need_GL_EXT_secondary_color +#define need_GL_VERSION_2_0 #include "extension_helper.h" #ifndef VERBOSE @@ -180,6 +181,9 @@ const struct dri_extension card_extensions[] = { "GL_MESA_ycbcr_texture", NULL }, { "GL_NV_blend_square", NULL }, { "GL_SGIS_generate_mipmap", NULL }, + { "GL_ARB_shading_language_100", GL_VERSION_2_0_functions}, + /* XXX not implement yet, to compile builtin glsl lib */ + { "GL_ARB_draw_buffers", NULL }, { NULL, NULL } }; diff --git a/src/mesa/shader/slang/slang_codegen.c b/src/mesa/shader/slang/slang_codegen.c index fe6b615c5d..30f044e77c 100644 --- a/src/mesa/shader/slang/slang_codegen.c +++ b/src/mesa/shader/slang/slang_codegen.c @@ -1746,6 +1746,7 @@ _slang_gen_var_decl(slang_assemble_ctx *A, slang_variable *var) n->Store->File = PROGRAM_TEMPORARY; n->Store->Size = _slang_sizeof_type_specifier(&n->Var->type.specifier); + A->program->NumTemporaries++; assert(n->Store->Size > 0); } return n; -- cgit v1.2.3 From a78b26fff04026a24189ecad7ec85bfe0df2cce1 Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Mon, 30 Apr 2007 15:24:38 +0800 Subject: support nested function call else instruction fix. --- src/mesa/drivers/dri/i965/brw_vs.h | 2 +- src/mesa/drivers/dri/i965/brw_vs_emit.c | 30 ++++++++++++++++-------------- 2 files changed, 17 insertions(+), 15 deletions(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_vs.h b/src/mesa/drivers/dri/i965/brw_vs.h index c31a1b6366..912ab563f4 100644 --- a/src/mesa/drivers/dri/i965/brw_vs.h +++ b/src/mesa/drivers/dri/i965/brw_vs.h @@ -67,7 +67,7 @@ struct brw_vs_compile { struct brw_reg r1; struct brw_reg regs[PROGRAM_ADDRESS+1][128]; struct brw_reg tmp; - struct brw_reg ret; + struct brw_reg stack; struct brw_reg userplane[6]; diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 613ee03b2a..f8367c4826 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -135,16 +135,8 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c ) reg++; } - c->ret = brw_reg(BRW_GENERAL_REGISTER_FILE, - reg, - 0, - BRW_REGISTER_TYPE_D, - BRW_VERTICAL_STRIDE_8, - BRW_WIDTH_8, - BRW_HORIZONTAL_STRIDE_1, - BRW_SWIZZLE_XXXX, - WRITEMASK_X); - reg++; + c->stack = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, reg, 0); + reg += 2; /* Some opcodes need an internal temporary: @@ -956,7 +948,8 @@ void brw_vs_emit(struct brw_vs_compile *c ) GLuint nr_insns = c->vp->program.Base.NumInstructions; GLuint insn, if_insn = 0; struct brw_instruction *end_inst; - struct brw_instruction *if_inst[32]; + struct brw_instruction *if_inst[MAX_IFSN]; + struct brw_indirect stack_index = brw_indirect(0, 0); if (INTEL_DEBUG & DEBUG_VS) { _mesa_printf("\n\n\nvs-emit:\n"); @@ -970,6 +963,7 @@ void brw_vs_emit(struct brw_vs_compile *c ) /* Static register allocation */ brw_vs_alloc_regs(c); + brw_MOV(p, get_addr_reg(stack_index), brw_address(c->stack)); for (insn = 0; insn < nr_insns; insn++) { @@ -1094,7 +1088,7 @@ void brw_vs_emit(struct brw_vs_compile *c ) if_inst[if_insn++] = brw_IF(p, BRW_EXECUTE_8); break; case OPCODE_ELSE: - brw_ELSE(p, if_inst[if_insn]); + if_inst[if_insn-1] = brw_ELSE(p, if_inst[if_insn-1]); break; case OPCODE_ENDIF: assert(if_insn > 0); @@ -1106,12 +1100,20 @@ void brw_vs_emit(struct brw_vs_compile *c ) brw_set_predicate_control_flag_value(p, 0xFF); break; case OPCODE_CAL: - brw_ADD(p, c->ret, brw_ip_reg(), brw_imm_d(2*16)); + brw_set_access_mode(p, BRW_ALIGN_1); + brw_ADD(p, deref_1uw(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16)); + brw_set_access_mode(p, BRW_ALIGN_16); + brw_ADD(p, get_addr_reg(stack_index), + get_addr_reg(stack_index), brw_imm_d(4)); inst->Data = &p->store[p->nr_insn]; brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16)); break; case OPCODE_RET: - brw_MOV(p, brw_ip_reg(), c->ret); + brw_ADD(p, get_addr_reg(stack_index), + get_addr_reg(stack_index), brw_imm_d(-4)); + brw_set_access_mode(p, BRW_ALIGN_1); + brw_MOV(p, brw_ip_reg(), deref_1uw(stack_index, 0)); + brw_set_access_mode(p, BRW_ALIGN_16); case OPCODE_END: brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16)); break; -- cgit v1.2.3 From 58eac1bbf320b4104c3158aaeca4726f1a59daf9 Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Wed, 9 May 2007 10:08:10 +0800 Subject: Support loop, conditional update fix --- src/mesa/drivers/dri/i965/brw_vs_emit.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index f8367c4826..ffc1a0ea09 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -921,8 +921,10 @@ post_vs_emit( struct brw_vs_compile *c, struct brw_instruction *end_inst ) inst1 = &c->vp->program.Base.Instructions[insn]; brw_inst1 = inst1->Data; switch (inst1->Opcode) { - case OPCODE_CAL: case OPCODE_BRA: + case OPCODE_BRK: + case OPCODE_CAL: + case OPCODE_ENDLOOP: target_insn = inst1->BranchTarget; inst2 = &c->vp->program.Base.Instructions[target_insn]; brw_inst2 = inst2->Data; @@ -943,12 +945,12 @@ post_vs_emit( struct brw_vs_compile *c, struct brw_instruction *end_inst ) */ void brw_vs_emit(struct brw_vs_compile *c ) { -#define MAX_IFSN 32 +#define MAX_IF_DEPTH 32 struct brw_compile *p = &c->func; GLuint nr_insns = c->vp->program.Base.NumInstructions; GLuint insn, if_insn = 0; struct brw_instruction *end_inst; - struct brw_instruction *if_inst[MAX_IFSN]; + struct brw_instruction *if_inst[MAX_IF_DEPTH]; struct brw_indirect stack_index = brw_indirect(0, 0); if (INTEL_DEBUG & DEBUG_VS) { @@ -1083,8 +1085,13 @@ void brw_vs_emit(struct brw_vs_compile *c ) case OPCODE_XPD: emit_xpd(p, dst, args[0], args[1]); break; + + case OPCODE_INT: + /* XXX TODO track type information in shader program */ + brw_MOV(p, dst, args[0]); + break; case OPCODE_IF: - assert(if_insn < MAX_IFSN); + assert(if_insn < MAX_IF_DEPTH); if_inst[if_insn++] = brw_IF(p, BRW_EXECUTE_8); break; case OPCODE_ELSE: @@ -1094,11 +1101,6 @@ void brw_vs_emit(struct brw_vs_compile *c ) assert(if_insn > 0); brw_ENDIF(p, if_inst[--if_insn]); break; - case OPCODE_BRA: - brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); - brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16)); - brw_set_predicate_control_flag_value(p, 0xFF); - break; case OPCODE_CAL: brw_set_access_mode(p, BRW_ALIGN_1); brw_ADD(p, deref_1uw(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16)); @@ -1114,9 +1116,13 @@ void brw_vs_emit(struct brw_vs_compile *c ) brw_set_access_mode(p, BRW_ALIGN_1); brw_MOV(p, brw_ip_reg(), deref_1uw(stack_index, 0)); brw_set_access_mode(p, BRW_ALIGN_16); + case OPCODE_ENDLOOP: + case OPCODE_BRK: + case OPCODE_BRA: case OPCODE_END: brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16)); break; + case OPCODE_BGNLOOP: case OPCODE_PRINT: case OPCODE_BGNSUB: case OPCODE_ENDSUB: @@ -1125,7 +1131,8 @@ void brw_vs_emit(struct brw_vs_compile *c ) _mesa_printf("Unsupport opcode %d in vertex shader\n", inst->Opcode); break; } - + brw_set_predicate_control(p, + inst->CondUpdate?BRW_PREDICATE_NORMAL:BRW_PREDICATE_NONE); release_tmps(c); } -- cgit v1.2.3 From d19d0596daf004b56d80f78fa1a329b43c2ebf94 Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Thu, 21 Jun 2007 10:22:28 +0800 Subject: support branch and loop in pixel shader most of the sample working with some small modification --- progs/glsl/CH06-brick.frag.txt | 6 +- progs/glsl/CH11-bumpmap.frag.txt | 2 +- progs/glsl/CH11-bumpmap.vert.txt | 9 +- progs/glsl/CH11-toyball.frag.txt | 7 +- progs/glsl/CH11-toyball.vert.txt | 7 +- src/mesa/drivers/dri/i965/Makefile | 1 + src/mesa/drivers/dri/i965/brw_eu.h | 8 +- src/mesa/drivers/dri/i965/brw_eu_emit.c | 28 +- src/mesa/drivers/dri/i965/brw_vs.h | 5 + src/mesa/drivers/dri/i965/brw_vs_emit.c | 84 ++- src/mesa/drivers/dri/i965/brw_wm.c | 80 +- src/mesa/drivers/dri/i965/brw_wm.h | 10 + src/mesa/drivers/dri/i965/brw_wm_emit.c | 28 +- src/mesa/drivers/dri/i965/brw_wm_fp.c | 16 +- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 1177 ++++++++++++++++++++++++++++++ src/mesa/drivers/dri/i965/brw_wm_pass2.c | 2 +- src/mesa/drivers/dri/i965/brw_wm_state.c | 7 +- 17 files changed, 1365 insertions(+), 112 deletions(-) create mode 100644 src/mesa/drivers/dri/i965/brw_wm_glsl.c (limited to 'src/mesa') diff --git a/progs/glsl/CH06-brick.frag.txt b/progs/glsl/CH06-brick.frag.txt index 06ef04e3af..388c5f9e66 100644 --- a/progs/glsl/CH06-brick.frag.txt +++ b/progs/glsl/CH06-brick.frag.txt @@ -23,7 +23,11 @@ void main() position = MCposition / BrickSize; - if (fract(position.y * 0.5) > 0.5) +// if (fract(position.y * 0.5) > 0.5) +// position.x += 0.5; + float tmp; + tmp = fract(position.y * 0.5); + if (tmp > 0.5) position.x += 0.5; position = fract(position); diff --git a/progs/glsl/CH11-bumpmap.frag.txt b/progs/glsl/CH11-bumpmap.frag.txt index 063576f5a3..1467f767ec 100644 --- a/progs/glsl/CH11-bumpmap.frag.txt +++ b/progs/glsl/CH11-bumpmap.frag.txt @@ -33,7 +33,7 @@ void main() litColor = SurfaceColor * max(dot(normDelta, LightDir), 0.0); vec3 reflectDir = reflect(LightDir, normDelta); - float spec = max(dot(EyeDir, reflectDir), 0.0); + float spec = max(dot(normalize(EyeDir), reflectDir), 0.0); spec *= SpecularFactor; litColor = min(litColor + spec, vec3(1.0)); diff --git a/progs/glsl/CH11-bumpmap.vert.txt b/progs/glsl/CH11-bumpmap.vert.txt index d3d19f62ac..55cf43ba7d 100644 --- a/progs/glsl/CH11-bumpmap.vert.txt +++ b/progs/glsl/CH11-bumpmap.vert.txt @@ -31,8 +31,9 @@ void main() v.z = dot(LightPosition, n); LightDir = normalize(v); - v.x = dot(EyeDir, t); - v.y = dot(EyeDir, b); - v.z = dot(EyeDir, n); - EyeDir = normalize(v); +/* v.x = dot(EyeDir, t); + v.y = dot(EyeDir, b); + v.z = dot(EyeDir, n); + EyeDir = normalize(EyeDir); +*/ } diff --git a/progs/glsl/CH11-toyball.frag.txt b/progs/glsl/CH11-toyball.frag.txt index 90ec1c27fc..f3cac62fb3 100644 --- a/progs/glsl/CH11-toyball.frag.txt +++ b/progs/glsl/CH11-toyball.frag.txt @@ -49,14 +49,15 @@ void main() inorout += dot(distance, vec4(1.0)); distance.x = dot(p, HalfSpace4); - distance.y = StripeWidth - abs(p.z); +// distance.y = StripeWidth - abs(p.z); + distance.y = StripeWidth - abs(p.y); distance = smoothstep(-FWidth, FWidth, distance); inorout += distance.x; inorout = clamp(inorout, 0.0, 1.0); - surfColor = mix(Yellow, Red, inorout); - surfColor = mix(surfColor, Blue, distance.y); + surfColor = mix(Yellow, Blue, distance.y); + surfColor = mix(surfColor, Red, inorout); // normal = point on surface for sphere at (0,0,0) normal = p; diff --git a/progs/glsl/CH11-toyball.vert.txt b/progs/glsl/CH11-toyball.vert.txt index b7da3ac839..a3ee1b0377 100644 --- a/progs/glsl/CH11-toyball.vert.txt +++ b/progs/glsl/CH11-toyball.vert.txt @@ -14,10 +14,11 @@ uniform vec4 BallCenter; // ball center in modelling coordinates void main() { -//orig: ECposition = gl_ModelViewMatrix * gl_Vertex; + ECposition = gl_ModelViewMatrix * gl_Vertex; - ECposition = gl_TextureMatrix[0] * gl_Vertex; - ECposition = gl_ModelViewMatrix * ECposition; +// ECposition = gl_TextureMatrix[0] * gl_Vertex; +// ECposition = gl_MultiTexCoord0 * gl_Vertex; +// ECposition = gl_ModelViewMatrix * ECposition; ECballCenter = gl_ModelViewMatrix * BallCenter; gl_Position = ftransform(); diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile index 9e4ff112dc..66de6f583c 100644 --- a/src/mesa/drivers/dri/i965/Makefile +++ b/src/mesa/drivers/dri/i965/Makefile @@ -70,6 +70,7 @@ DRIVER_SOURCES = \ brw_wm_emit.c \ brw_wm_fp.c \ brw_wm_iz.c \ + brw_wm_glsl.c \ brw_wm_pass0.c \ brw_wm_pass1.c \ brw_wm_pass2.c \ diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index 144f209eda..9b6581fd93 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -668,7 +668,10 @@ static __inline struct brw_indirect brw_indirect( GLuint addr_subnr, GLint offse return ptr; } - +static __inline struct brw_instruction *current_insn( struct brw_compile *p) +{ + return &p->store[p->nr_insn]; +} void brw_pop_insn_state( struct brw_compile *p ); void brw_push_insn_state( struct brw_compile *p ); @@ -808,9 +811,10 @@ void brw_ENDIF(struct brw_compile *p, struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size); -void brw_WHILE(struct brw_compile *p, +struct brw_instruction *brw_WHILE(struct brw_compile *p, struct brw_instruction *patch_insn); +struct brw_instruction *brw_BREAK(struct brw_compile *p); /* Forward jumps: */ void brw_land_fwd_jump(struct brw_compile *p, diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 0c04bf6c62..7b95fbdac0 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -186,7 +186,7 @@ void brw_set_src1( struct brw_instruction *insn, * in the future: */ assert (reg.address_mode == BRW_ADDRESS_DIRECT); - assert (reg.file == BRW_GENERAL_REGISTER_FILE); + //assert (reg.file == BRW_GENERAL_REGISTER_FILE); if (insn->header.access_mode == BRW_ALIGN_1) { insn->bits3.da1.src1_subreg_nr = reg.subnr; @@ -597,6 +597,20 @@ void brw_ENDIF(struct brw_compile *p, } } +struct brw_instruction *brw_BREAK(struct brw_compile *p) +{ + struct brw_instruction *insn; + insn = next_insn(p, BRW_OPCODE_BREAK); + brw_set_dest(insn, brw_ip_reg()); + brw_set_src0(insn, brw_ip_reg()); + brw_set_src1(insn, brw_imm_d(0x0)); + insn->header.compression_control = BRW_COMPRESSION_NONE; + insn->header.execution_size = BRW_EXECUTE_8; + insn->header.mask_control = BRW_MASK_DISABLE; + insn->bits3.if_else.pad0 = 0; + return insn; +} + /* DO/WHILE loop: */ struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size) @@ -608,13 +622,15 @@ struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size) /* Override the defaults for this instruction: */ - brw_set_dest(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD)); - brw_set_src0(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD)); - brw_set_src1(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD)); + brw_set_dest(insn, brw_null_reg()); + brw_set_src0(insn, brw_null_reg()); + brw_set_src1(insn, brw_null_reg()); insn->header.compression_control = BRW_COMPRESSION_NONE; insn->header.execution_size = execute_size; + insn->header.predicate_control = BRW_PREDICATE_NONE; /* insn->header.mask_control = BRW_MASK_ENABLE; */ + insn->header.mask_control = BRW_MASK_DISABLE; return insn; } @@ -622,7 +638,7 @@ struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size) -void brw_WHILE(struct brw_compile *p, +struct brw_instruction *brw_WHILE(struct brw_compile *p, struct brw_instruction *do_insn) { struct brw_instruction *insn; @@ -653,7 +669,9 @@ void brw_WHILE(struct brw_compile *p, /* insn->header.mask_control = BRW_MASK_ENABLE; */ + insn->header.mask_control = BRW_MASK_DISABLE; p->current->header.predicate_control = BRW_PREDICATE_NONE; + return insn; } diff --git a/src/mesa/drivers/dri/i965/brw_vs.h b/src/mesa/drivers/dri/i965/brw_vs.h index 912ab563f4..36636b5ffd 100644 --- a/src/mesa/drivers/dri/i965/brw_vs.h +++ b/src/mesa/drivers/dri/i965/brw_vs.h @@ -69,6 +69,11 @@ struct brw_vs_compile { struct brw_reg tmp; struct brw_reg stack; + struct { + GLboolean used_in_src; + struct brw_reg reg; + } output_regs[128]; + struct brw_reg userplane[6]; }; diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index ffc1a0ea09..fa94d5b1a8 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -135,6 +135,13 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c ) reg++; } + for (i = 0; i < 128; i++) { + if (c->output_regs[i].used_in_src) { + c->regs[PROGRAM_OUTPUT][i] = brw_vec8_grf(reg, 0); + reg++; + } + } + c->stack = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, reg, 0); reg += 2; @@ -686,28 +693,28 @@ static void emit_arl( struct brw_vs_compile *c, * account. */ static struct brw_reg get_arg( struct brw_vs_compile *c, - struct prog_src_register src ) + struct prog_src_register *src ) { struct brw_reg reg; - if (src.File == PROGRAM_UNDEFINED) + if (src->File == PROGRAM_UNDEFINED) return brw_null_reg(); - if (src.RelAddr) - reg = deref(c, c->regs[PROGRAM_STATE_VAR][0], src.Index); + if (src->RelAddr) + reg = deref(c, c->regs[PROGRAM_STATE_VAR][0], src->Index); else - reg = get_reg(c, src.File, src.Index); + reg = get_reg(c, src->File, src->Index); /* Convert 3-bit swizzle to 2-bit. */ - reg.dw1.bits.swizzle = BRW_SWIZZLE4(GET_SWZ(src.Swizzle, 0), - GET_SWZ(src.Swizzle, 1), - GET_SWZ(src.Swizzle, 2), - GET_SWZ(src.Swizzle, 3)); + reg.dw1.bits.swizzle = BRW_SWIZZLE4(GET_SWZ(src->Swizzle, 0), + GET_SWZ(src->Swizzle, 1), + GET_SWZ(src->Swizzle, 2), + GET_SWZ(src->Swizzle, 3)); /* Note this is ok for non-swizzle instructions: */ - reg.negate = src.NegateBase ? 1 : 0; + reg.negate = src->NegateBase ? 1 : 0; return reg; } @@ -921,10 +928,8 @@ post_vs_emit( struct brw_vs_compile *c, struct brw_instruction *end_inst ) inst1 = &c->vp->program.Base.Instructions[insn]; brw_inst1 = inst1->Data; switch (inst1->Opcode) { - case OPCODE_BRA: - case OPCODE_BRK: case OPCODE_CAL: - case OPCODE_ENDLOOP: + case OPCODE_BRA: target_insn = inst1->BranchTarget; inst2 = &c->vp->program.Base.Instructions[target_insn]; brw_inst2 = inst2->Data; @@ -945,12 +950,12 @@ post_vs_emit( struct brw_vs_compile *c, struct brw_instruction *end_inst ) */ void brw_vs_emit(struct brw_vs_compile *c ) { -#define MAX_IF_DEPTH 32 +#define MAX_IFSN 32 struct brw_compile *p = &c->func; GLuint nr_insns = c->vp->program.Base.NumInstructions; GLuint insn, if_insn = 0; struct brw_instruction *end_inst; - struct brw_instruction *if_inst[MAX_IF_DEPTH]; + struct brw_instruction *if_inst[MAX_IFSN]; struct brw_indirect stack_index = brw_indirect(0, 0); if (INTEL_DEBUG & DEBUG_VS) { @@ -962,6 +967,20 @@ void brw_vs_emit(struct brw_vs_compile *c ) brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_set_access_mode(p, BRW_ALIGN_16); + /* Message registers can't be read, so copy the output into GRF register + if they are used in source registers */ + for (insn = 0; insn < nr_insns; insn++) { + GLuint i; + struct prog_instruction *inst = &c->vp->program.Base.Instructions[insn]; + for (i = 0; i < 3; i++) { + struct prog_src_register *src = &inst->SrcReg[i]; + GLuint index = src->Index; + GLuint file = src->File; + if (file == PROGRAM_OUTPUT && index != VERT_RESULT_HPOS) + c->output_regs[index].used_in_src = GL_TRUE; + } + } + /* Static register allocation */ brw_vs_alloc_regs(c); @@ -977,8 +996,15 @@ void brw_vs_emit(struct brw_vs_compile *c ) */ inst->Data = &p->store[p->nr_insn]; if (inst->Opcode != OPCODE_SWZ) - for (i = 0; i < 3; i++) - args[i] = get_arg(c, inst->SrcReg[i]); + for (i = 0; i < 3; i++) { + struct prog_src_register *src = &inst->SrcReg[i]; + GLuint index = src->Index; + GLuint file = src->File; + if (file == PROGRAM_OUTPUT&&c->output_regs[index].used_in_src) + args[i] = c->output_regs[index].reg; + else + args[i] = get_arg(c, src); + } /* Get dest regs. Note that it is possible for a reg to be both * dst and arg, given the static allocation of registers. So @@ -1085,13 +1111,8 @@ void brw_vs_emit(struct brw_vs_compile *c ) case OPCODE_XPD: emit_xpd(p, dst, args[0], args[1]); break; - - case OPCODE_INT: - /* XXX TODO track type information in shader program */ - brw_MOV(p, dst, args[0]); - break; case OPCODE_IF: - assert(if_insn < MAX_IF_DEPTH); + assert(if_insn < MAX_IFSN); if_inst[if_insn++] = brw_IF(p, BRW_EXECUTE_8); break; case OPCODE_ELSE: @@ -1101,6 +1122,11 @@ void brw_vs_emit(struct brw_vs_compile *c ) assert(if_insn > 0); brw_ENDIF(p, if_inst[--if_insn]); break; + case OPCODE_BRA: + brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); + brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16)); + brw_set_predicate_control_flag_value(p, 0xff); + break; case OPCODE_CAL: brw_set_access_mode(p, BRW_ALIGN_1); brw_ADD(p, deref_1uw(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16)); @@ -1116,13 +1142,9 @@ void brw_vs_emit(struct brw_vs_compile *c ) brw_set_access_mode(p, BRW_ALIGN_1); brw_MOV(p, brw_ip_reg(), deref_1uw(stack_index, 0)); brw_set_access_mode(p, BRW_ALIGN_16); - case OPCODE_ENDLOOP: - case OPCODE_BRK: - case OPCODE_BRA: case OPCODE_END: brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16)); break; - case OPCODE_BGNLOOP: case OPCODE_PRINT: case OPCODE_BGNSUB: case OPCODE_ENDSUB: @@ -1131,8 +1153,12 @@ void brw_vs_emit(struct brw_vs_compile *c ) _mesa_printf("Unsupport opcode %d in vertex shader\n", inst->Opcode); break; } - brw_set_predicate_control(p, - inst->CondUpdate?BRW_PREDICATE_NORMAL:BRW_PREDICATE_NONE); + + if (inst->DstReg.File == PROGRAM_OUTPUT + &&inst->DstReg.Index != VERT_RESULT_HPOS + &&c->output_regs[inst->DstReg.Index].used_in_src) + brw_MOV(p, get_dst(c, inst->DstReg), dst); + release_tmps(c); } diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index a02a0a23af..45ba4eaf32 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -154,47 +154,49 @@ static void do_wm_prog( struct brw_context *brw, c->fp = fp; c->env_param = brw->intel.ctx.FragmentProgram.Parameters; - - /* Augment fragment program. Add instructions for pre- and - * post-fragment-program tasks such as interpolation and fogging. - */ - brw_wm_pass_fp(c); - - /* Translate to intermediate representation. Build register usage - * chains. - */ - brw_wm_pass0(c); - - /* Dead code removal. - */ - brw_wm_pass1(c); - - /* Hal optimization - */ - brw_wm_pass_hal (c); - - /* Register allocation. - */ - c->grf_limit = BRW_WM_MAX_GRF/2; - - /* This is where we start emitting gen4 code: - */ - brw_init_compile(&c->func); - - brw_wm_pass2(c); - - c->prog_data.total_grf = c->max_wm_grf; - if (c->last_scratch) { - c->prog_data.total_scratch = - c->last_scratch + 0x40; + if (brw_wm_is_glsl(&c->fp->program)) { + brw_wm_glsl_emit(c); } else { - c->prog_data.total_scratch = 0; + /* Augment fragment program. Add instructions for pre- and + * post-fragment-program tasks such as interpolation and fogging. + */ + brw_wm_pass_fp(c); + + /* Translate to intermediate representation. Build register usage + * chains. + */ + brw_wm_pass0(c); + + /* Dead code removal. + */ + brw_wm_pass1(c); + + /* Hal optimization + */ + brw_wm_pass_hal (c); + + /* Register allocation. + */ + c->grf_limit = BRW_WM_MAX_GRF/2; + + /* This is where we start emitting gen4 code: + */ + brw_init_compile(&c->func); + + brw_wm_pass2(c); + + c->prog_data.total_grf = c->max_wm_grf; + if (c->last_scratch) { + c->prog_data.total_scratch = + c->last_scratch + 0x40; + } else { + c->prog_data.total_scratch = 0; + } + + /* Emit GEN4 code. + */ + brw_wm_emit(c); } - - /* Emit GEN4 code. - */ - brw_wm_emit(c); - /* get the program */ program = brw_get_program(&c->func, &program_size); diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index f5fddfdb68..4143d5be6c 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -231,6 +231,14 @@ struct brw_wm_compile { GLuint grf_limit; GLuint max_wm_grf; GLuint last_scratch; + + struct { + GLboolean inited; + struct brw_reg reg; + } wm_regs[PROGRAM_PAYLOAD+1][256][4]; + struct brw_reg ret_reg; + GLuint reg_index; + GLuint tmp_index; }; @@ -259,4 +267,6 @@ void brw_wm_lookup_iz( GLuint line_aa, GLuint lookup, struct brw_wm_prog_key *key ); +GLboolean brw_wm_is_glsl(struct gl_fragment_program *fp); +void brw_wm_glsl_emit(struct brw_wm_compile *c); #endif diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index 197a0ae13d..5660b55516 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -229,20 +229,20 @@ static void emit_cinterp( struct brw_compile *p, GLuint mask, const struct brw_reg *arg0 ) { - struct brw_reg interp[4]; - GLuint nr = arg0[0].nr; - GLuint i; - - interp[0] = brw_vec1_grf(nr, 0); - interp[1] = brw_vec1_grf(nr, 4); - interp[2] = brw_vec1_grf(nr+1, 0); - interp[3] = brw_vec1_grf(nr+1, 4); - - for(i = 0; i < 4; i++ ) { - if (mask & (1<Data = (void *)inst0; return inst; } @@ -201,7 +202,6 @@ static struct prog_instruction * emit_op(struct brw_wm_compile *c, inst->SrcReg[0] = src0; inst->SrcReg[1] = src1; inst->SrcReg[2] = src2; - return inst; } @@ -907,8 +907,10 @@ void brw_wm_pass_fp( struct brw_wm_compile *c ) */ out->DstReg.WriteMask = 0; break; - case OPCODE_END: + emit_fog(c); + emit_fb_write(c); + break; case OPCODE_PRINT: break; @@ -917,15 +919,11 @@ void brw_wm_pass_fp( struct brw_wm_compile *c ) break; } } - - emit_fog(c); - emit_fb_write(c); - if (INTEL_DEBUG & DEBUG_WM) { - _mesa_printf("\n\n\npass_fp:\n"); - print_insns( c->prog_instructions, c->nr_fp_insns ); - _mesa_printf("\n"); + _mesa_printf("\n\n\npass_fp:\n"); + print_insns( c->prog_instructions, c->nr_fp_insns ); + _mesa_printf("\n"); } } diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c new file mode 100644 index 0000000000..cdd7976607 --- /dev/null +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -0,0 +1,1177 @@ +#include "macros.h" +#include "shader/prog_parameter.h" +#include "brw_context.h" +#include "brw_eu.h" +#include "brw_wm.h" + +/* Only guess, need a flag in gl_fragment_program later */ +GLboolean brw_wm_is_glsl(struct gl_fragment_program *fp) +{ + int i; + for (i = 0; i < fp->Base.NumInstructions; i++) { + struct prog_instruction *inst = &fp->Base.Instructions[i]; + switch (inst->Opcode) { + case OPCODE_IF: + case OPCODE_ENDIF: + case OPCODE_CAL: + case OPCODE_BRK: + case OPCODE_RET: + case OPCODE_BGNLOOP: + return GL_TRUE; + default: + break; + } + } + return GL_FALSE; +} + +static void set_reg(struct brw_wm_compile *c, int file, int index, + int component, struct brw_reg reg) +{ + c->wm_regs[file][index][component].reg = reg; + c->wm_regs[file][index][component].inited = GL_TRUE; +} + +static int get_scalar_dst_index(struct prog_instruction *inst) +{ + int i; + for (i = 0; i < 4; i++) + if (inst->DstReg.WriteMask & (1<tmp_index--, 0); + return reg; +} + +static void release_tmps(struct brw_wm_compile *c) +{ + c->tmp_index = 127; +} + +static struct brw_reg +get_reg(struct brw_wm_compile *c, int file, int index, int component, int nr, GLuint neg, GLuint abs) +{ + struct brw_reg reg; + switch (file) { + case PROGRAM_STATE_VAR: + case PROGRAM_CONSTANT: + case PROGRAM_UNIFORM: + file = PROGRAM_STATE_VAR; + break; + case PROGRAM_UNDEFINED: + return brw_null_reg(); + default: + break; + } + + if(c->wm_regs[file][index][component].inited) + reg = c->wm_regs[file][index][component].reg; + else + reg = brw_vec8_grf(c->reg_index, 0); + + if(!c->wm_regs[file][index][component].inited) { + set_reg(c, file, index, component, reg); + c->reg_index++; + } + + if (neg & (1<< component)) { + reg = negate(reg); + } + if (abs) + reg = brw_abs(reg); + return reg; +} + +static void prealloc_reg(struct brw_wm_compile *c) +{ + int i, j; + struct brw_reg reg; + int nr_interp_regs = 0; + GLuint inputs = FRAG_BIT_WPOS | c->fp_interp_emitted; + + for (i = 0; i < 4; i++) { + reg = (i < c->key.nr_depth_regs) + ? brw_vec8_grf(i*2, 0) : brw_vec8_grf(0, 0); + set_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, i, reg); + } + c->reg_index += 2*c->key.nr_depth_regs; + { + int nr_params = c->fp->program.Base.Parameters->NumParameters; + struct gl_program_parameter_list *plist = + c->fp->program.Base.Parameters; + int index = 0; + c->prog_data.nr_params = 4*nr_params; + for (i = 0; i < nr_params; i++) { + for (j = 0; j < 4; j++, index++) { + reg = brw_vec1_grf(c->reg_index + index/8, + index%8); + c->prog_data.param[index] = + &plist->ParameterValues[i][j]; + set_reg(c, PROGRAM_STATE_VAR, i, j, reg); + } + } + c->nr_creg = 2*((4*nr_params+15)/16); + c->reg_index += c->nr_creg; + } + for (i = 0; i < FRAG_ATTRIB_MAX; i++) { + if (inputs & (1<reg_index, 0); + for (j = 0; j < 4; j++) + set_reg(c, PROGRAM_PAYLOAD, i, j, reg); + c->reg_index += 2; + + } + } + c->prog_data.first_curbe_grf = c->key.nr_depth_regs * 2; + c->prog_data.urb_read_length = nr_interp_regs * 2; + c->prog_data.curb_read_length = c->nr_creg; + c->ret_reg = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, c->reg_index, 0); + c->reg_index++; +} + +static struct brw_reg get_dst_reg(struct brw_wm_compile *c, + struct prog_instruction *inst, int component, int nr) +{ + return get_reg(c, inst->DstReg.File, inst->DstReg.Index, component, nr, + 0, 0); +} + +static struct brw_reg get_src_reg(struct brw_wm_compile *c, + struct prog_src_register *src, int index, int nr) +{ + int component = GET_SWZ(src->Swizzle, index); + return get_reg(c, src->File, src->Index, component, nr, + src->NegateBase, src->Abs); +} + +static void emit_abs( struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + int i; + struct brw_compile *p = &c->func; + brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF); + for (i = 0; i < 4; i++) { + if (inst->DstReg.WriteMask & (1<SrcReg[0], i, 1); + brw_MOV(p, dst, brw_abs(src)); + } + } + brw_set_saturate(p, 0); +} + +static void emit_mov( struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + int i; + struct brw_compile *p = &c->func; + GLuint mask = inst->DstReg.WriteMask; + brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF); + for (i = 0; i < 4; i++) { + if (mask & (1<SrcReg[0], i, 1); + brw_MOV(p, dst, src); + } + } + brw_set_saturate(p, 0); +} + +static void emit_pixel_xy(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_reg r1 = brw_vec1_grf(1, 0); + struct brw_reg r1_uw = retype(r1, BRW_REGISTER_TYPE_UW); + + struct brw_reg dst0, dst1; + struct brw_compile *p = &c->func; + GLuint mask = inst->DstReg.WriteMask; + + dst0 = get_dst_reg(c, inst, 0, 1); + dst1 = get_dst_reg(c, inst, 1, 1); + /* Calculate pixel centers by adding 1 or 0 to each of the + * micro-tile coordinates passed in r1. + */ + if (mask & WRITEMASK_X) { + brw_ADD(p, + vec8(retype(dst0, BRW_REGISTER_TYPE_UW)), + stride(suboffset(r1_uw, 4), 2, 4, 0), + brw_imm_v(0x10101010)); + } + + if (mask & WRITEMASK_Y) { + brw_ADD(p, + vec8(retype(dst1, BRW_REGISTER_TYPE_UW)), + stride(suboffset(r1_uw, 5), 2, 4, 0), + brw_imm_v(0x11001100)); + } + +} + +static void emit_delta_xy(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_reg r1 = brw_vec1_grf(1, 0); + struct brw_reg dst0, dst1, src0, src1; + struct brw_compile *p = &c->func; + GLuint mask = inst->DstReg.WriteMask; + + dst0 = get_dst_reg(c, inst, 0, 1); + dst1 = get_dst_reg(c, inst, 1, 1); + src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1); + src1 = get_src_reg(c, &inst->SrcReg[0], 1, 1); + /* Calc delta X,Y by subtracting origin in r1 from the pixel + * centers. + */ + if (mask & WRITEMASK_X) { + brw_ADD(p, + dst0, + retype(src0, BRW_REGISTER_TYPE_UW), + negate(r1)); + } + + if (mask & WRITEMASK_Y) { + brw_ADD(p, + dst1, + retype(src1, BRW_REGISTER_TYPE_UW), + negate(suboffset(r1,1))); + + } + +} + + +static void fire_fb_write( struct brw_wm_compile *c, + GLuint base_reg, + GLuint nr ) +{ + struct brw_compile *p = &c->func; + + /* Pass through control information: + */ + /* mov (8) m1.0<1>:ud r1.0<8;8,1>:ud { Align1 NoMask } */ + { + brw_push_insn_state(p); + brw_set_mask_control(p, BRW_MASK_DISABLE); /* ? */ + brw_MOV(p, + brw_message_reg(base_reg + 1), + brw_vec8_grf(1, 0)); + brw_pop_insn_state(p); + } + /* Send framebuffer write message: */ + brw_fb_WRITE(p, + retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW), + base_reg, + retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW), + 0, /* render surface always 0 */ + nr, + 0, + 1); +} + +static void emit_fb_write(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_compile *p = &c->func; + int nr = 2; + int channel; + struct brw_reg src0;//, src1, src2, dst; + + /* Reserve a space for AA - may not be needed: + */ + if (c->key.aa_dest_stencil_reg) + nr += 1; + { + brw_push_insn_state(p); + for (channel = 0; channel < 4; channel++) { + src0 = get_src_reg(c, &inst->SrcReg[0], channel, 1); + /* mov (8) m2.0<1>:ud r28.0<8;8,1>:ud { Align1 } */ + /* mov (8) m6.0<1>:ud r29.0<8;8,1>:ud { Align1 SecHalf } */ + brw_MOV(p, brw_message_reg(nr + channel), src0); + } + /* skip over the regs populated above: */ + nr += 8; + brw_pop_insn_state(p); + } + fire_fb_write(c, 0, nr); +} + +static void emit_pixel_w( struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_compile *p = &c->func; + GLuint mask = inst->DstReg.WriteMask; + if (mask & WRITEMASK_W) { + struct brw_reg dst, src0, delta0, delta1; + struct brw_reg interp3; + + dst = get_dst_reg(c, inst, 3, 1); + src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1); + delta0 = get_src_reg(c, &inst->SrcReg[1], 0, 1); + delta1 = get_src_reg(c, &inst->SrcReg[1], 1, 1); + + interp3 = brw_vec1_grf(src0.nr+1, 4); + /* Calc 1/w - just linterp wpos[3] optimized by putting the + * result straight into a message reg. + */ + brw_LINE(p, brw_null_reg(), interp3, delta0); + brw_MAC(p, brw_message_reg(2), suboffset(interp3, 1), delta1); + + /* Calc w */ + brw_math_16( p, dst, + BRW_MATH_FUNCTION_INV, + BRW_MATH_SATURATE_NONE, + 2, brw_null_reg(), + BRW_MATH_PRECISION_FULL); + } +} + +static void emit_linterp(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_compile *p = &c->func; + GLuint mask = inst->DstReg.WriteMask; + struct brw_reg interp[4]; + struct brw_reg dst, delta0, delta1; + struct brw_reg src0; + + src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1); + delta0 = get_src_reg(c, &inst->SrcReg[1], 0, 1); + delta1 = get_src_reg(c, &inst->SrcReg[1], 1, 1); + GLuint nr = src0.nr; + int i; + + interp[0] = brw_vec1_grf(nr, 0); + interp[1] = brw_vec1_grf(nr, 4); + interp[2] = brw_vec1_grf(nr+1, 0); + interp[3] = brw_vec1_grf(nr+1, 4); + + for(i = 0; i < 4; i++ ) { + if (mask & (1<func; + GLuint mask = inst->DstReg.WriteMask; + + struct brw_reg interp[4]; + struct brw_reg dst, src0; + + src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1); + GLuint nr = src0.nr; + int i; + + interp[0] = brw_vec1_grf(nr, 0); + interp[1] = brw_vec1_grf(nr, 4); + interp[2] = brw_vec1_grf(nr+1, 0); + interp[3] = brw_vec1_grf(nr+1, 4); + + for(i = 0; i < 4; i++ ) { + if (mask & (1<func; + GLuint mask = inst->DstReg.WriteMask; + + struct brw_reg interp[4]; + struct brw_reg dst, delta0, delta1; + struct brw_reg src0, w; + + src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1); + delta0 = get_src_reg(c, &inst->SrcReg[1], 0, 1); + delta1 = get_src_reg(c, &inst->SrcReg[1], 1, 1); + w = get_src_reg(c, &inst->SrcReg[2], 3, 1); + GLuint nr = src0.nr; + int i; + + interp[0] = brw_vec1_grf(nr, 0); + interp[1] = brw_vec1_grf(nr, 4); + interp[2] = brw_vec1_grf(nr+1, 0); + interp[3] = brw_vec1_grf(nr+1, 4); + + for(i = 0; i < 4; i++ ) { + if (mask & (1<func; + GLuint mask = inst->DstReg.WriteMask; + for (i = 0; i < 4; i++) { + GLuint i2 = (i+2)%3; + GLuint i1 = (i+1)%3; + if (mask & (1<SrcReg[0], i2, 1)); + src1 = get_src_reg(c, &inst->SrcReg[1], i1, 1); + brw_MUL(p, brw_null_reg(), src0, src1); + src0 = get_src_reg(c, &inst->SrcReg[0], i1, 1); + src1 = get_src_reg(c, &inst->SrcReg[1], i2, 1); + brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF); + brw_MAC(p, dst, src0, src1); + brw_set_saturate(p, 0); + } + } + brw_set_saturate(p, 0); +} + +static void emit_dp3(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_reg src0[3], src1[3], dst; + int i; + struct brw_compile *p = &c->func; + for (i = 0; i < 3; i++) { + src0[i] = get_src_reg(c, &inst->SrcReg[0], i, 1); + src1[i] = get_src_reg(c, &inst->SrcReg[1], i, 1); + } + + dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1); + brw_MUL(p, brw_null_reg(), src0[0], src1[0]); + brw_MAC(p, brw_null_reg(), src0[1], src1[1]); + brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); + brw_MAC(p, dst, src0[2], src1[2]); + brw_set_saturate(p, 0); +} + +static void emit_dp4(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_reg src0[4], src1[4], dst; + int i; + struct brw_compile *p = &c->func; + for (i = 0; i < 4; i++) { + src0[i] = get_src_reg(c, &inst->SrcReg[0], i, 1); + src1[i] = get_src_reg(c, &inst->SrcReg[1], i, 1); + } + dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1); + brw_MUL(p, brw_null_reg(), src0[0], src1[0]); + brw_MAC(p, brw_null_reg(), src0[1], src1[1]); + brw_MAC(p, brw_null_reg(), src0[2], src1[2]); + brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); + brw_MAC(p, dst, src0[3], src1[3]); + brw_set_saturate(p, 0); +} + +static void emit_dph(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_reg src0[4], src1[4], dst; + int i; + struct brw_compile *p = &c->func; + for (i = 0; i < 4; i++) { + src0[i] = get_src_reg(c, &inst->SrcReg[0], i, 1); + src1[i] = get_src_reg(c, &inst->SrcReg[1], i, 1); + } + dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1); + brw_MUL(p, brw_null_reg(), src0[0], src1[0]); + brw_MAC(p, brw_null_reg(), src0[1], src1[1]); + brw_MAC(p, dst, src0[2], src1[2]); + brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); + brw_ADD(p, dst, src0[3], src1[3]); + brw_set_saturate(p, 0); +} + +static void emit_math1(struct brw_wm_compile *c, + struct prog_instruction *inst, GLuint func) +{ + struct brw_compile *p = &c->func; + struct brw_reg src0, dst; + + src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1); + dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1); + brw_MOV(p, brw_message_reg(2), src0); + brw_math(p, + dst, + func, + (inst->SaturateMode != SATURATE_OFF) ? BRW_MATH_SATURATE_SATURATE : BRW_MATH_SATURATE_NONE, + 2, + brw_null_reg(), + BRW_MATH_DATA_VECTOR, + BRW_MATH_PRECISION_FULL); +} + +static void emit_rcp(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + emit_math1(c, inst, BRW_MATH_FUNCTION_INV); +} + +static void emit_rsq(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + emit_math1(c, inst, BRW_MATH_FUNCTION_RSQ); +} + +static void emit_sin(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + emit_math1(c, inst, BRW_MATH_FUNCTION_SIN); +} + +static void emit_cos(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + emit_math1(c, inst, BRW_MATH_FUNCTION_COS); +} + +static void emit_ex2(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + emit_math1(c, inst, BRW_MATH_FUNCTION_EXP); +} + +static void emit_lg2(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + emit_math1(c, inst, BRW_MATH_FUNCTION_LOG); +} + +static void emit_add(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_compile *p = &c->func; + struct brw_reg src0, src1, dst; + GLuint mask = inst->DstReg.WriteMask; + int i; + brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); + for (i = 0 ; i < 4; i++) { + if (mask & (1<SrcReg[0], i, 1); + src1 = get_src_reg(c, &inst->SrcReg[1], i, 1); + brw_ADD(p, dst, src0, src1); + } + } + brw_set_saturate(p, 0); +} + +static void emit_sub(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_compile *p = &c->func; + struct brw_reg src0, src1, dst; + GLuint mask = inst->DstReg.WriteMask; + int i; + brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); + for (i = 0 ; i < 4; i++) { + if (mask & (1<SrcReg[0], i, 1); + src1 = get_src_reg(c, &inst->SrcReg[1], i, 1); + brw_ADD(p, dst, src0, negate(src1)); + } + } + brw_set_saturate(p, 0); +} + +static void emit_mul(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_compile *p = &c->func; + struct brw_reg src0, src1, dst; + GLuint mask = inst->DstReg.WriteMask; + int i; + brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); + for (i = 0 ; i < 4; i++) { + if (mask & (1<SrcReg[0], i, 1); + src1 = get_src_reg(c, &inst->SrcReg[1], i, 1); + brw_MUL(p, dst, src0, src1); + } + } + brw_set_saturate(p, 0); +} + +static void emit_frc(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_compile *p = &c->func; + struct brw_reg src0, dst; + GLuint mask = inst->DstReg.WriteMask; + int i; + brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); + for (i = 0 ; i < 4; i++) { + if (mask & (1<SrcReg[0], i, 1); + brw_FRC(p, dst, src0); + } + } + if (inst->SaturateMode != SATURATE_OFF) + brw_set_saturate(p, 0); +} + +static void emit_flr(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_compile *p = &c->func; + struct brw_reg src0, dst; + GLuint mask = inst->DstReg.WriteMask; + int i; + brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); + for (i = 0 ; i < 4; i++) { + if (mask & (1<SrcReg[0], i, 1); + brw_RNDD(p, dst, src0); + } + } + brw_set_saturate(p, 0); +} + +static void emit_max(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_compile *p = &c->func; + GLuint mask = inst->DstReg.WriteMask; + struct brw_reg src0, src1, dst; + int i; + brw_push_insn_state(p); + for (i = 0; i < 4; i++) { + if (mask & (1<SrcReg[0], i, 1); + src1 = get_src_reg(c, &inst->SrcReg[1], i, 1); + brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); + brw_MOV(p, dst, src0); + brw_set_saturate(p, 0); + + brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, src0, src1); + brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); + brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); + brw_MOV(p, dst, src1); + brw_set_saturate(p, 0); + brw_set_predicate_control_flag_value(p, 0xff); + } + } + brw_pop_insn_state(p); +} + +static void emit_min(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_compile *p = &c->func; + GLuint mask = inst->DstReg.WriteMask; + struct brw_reg src0, src1, dst; + int i; + brw_push_insn_state(p); + for (i = 0; i < 4; i++) { + if (mask & (1<SrcReg[0], i, 1); + src1 = get_src_reg(c, &inst->SrcReg[1], i, 1); + brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); + brw_MOV(p, dst, src0); + brw_set_saturate(p, 0); + + brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, src1, src0); + brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); + brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); + brw_MOV(p, dst, src1); + brw_set_saturate(p, 0); + brw_set_predicate_control_flag_value(p, 0xff); + } + } + brw_pop_insn_state(p); +} + +static void emit_pow(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_compile *p = &c->func; + struct brw_reg dst, src0, src1; + dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1); + src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1); + src1 = get_src_reg(c, &inst->SrcReg[1], 0, 1); + + brw_MOV(p, brw_message_reg(2), src0); + brw_MOV(p, brw_message_reg(3), src1); + + brw_math(p, + dst, + BRW_MATH_FUNCTION_POW, + (inst->SaturateMode != SATURATE_OFF) ? BRW_MATH_SATURATE_SATURATE : BRW_MATH_SATURATE_NONE, + 2, + brw_null_reg(), + BRW_MATH_DATA_VECTOR, + BRW_MATH_PRECISION_FULL); +} + +static void emit_lrp(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_compile *p = &c->func; + GLuint mask = inst->DstReg.WriteMask; + struct brw_reg dst, tmp1, tmp2, src0, src1, src2; + int i; + for (i = 0; i < 4; i++) { + if (mask & (1<SrcReg[0], i, 1); + + src1 = get_src_reg(c, &inst->SrcReg[1], i, 1); + + if (src1.nr == dst.nr) { + tmp1 = alloc_tmp(c); + brw_MOV(p, tmp1, src1); + } else + tmp1 = src1; + + src2 = get_src_reg(c, &inst->SrcReg[2], i, 1); + if (src2.nr == dst.nr) { + tmp2 = alloc_tmp(c); + brw_MOV(p, tmp2, src2); + } else + tmp2 = src2; + + brw_ADD(p, dst, negate(src0), brw_imm_f(1.0)); + brw_MUL(p, brw_null_reg(), dst, tmp2); + brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); + brw_MAC(p, dst, src0, tmp1); + brw_set_saturate(p, 0); + } + release_tmps(c); + } +} + +static void emit_mad(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_compile *p = &c->func; + GLuint mask = inst->DstReg.WriteMask; + struct brw_reg dst, src0, src1, src2; + int i; + + for (i = 0; i < 4; i++) { + if (mask & (1<SrcReg[0], i, 1); + src1 = get_src_reg(c, &inst->SrcReg[1], i, 1); + src2 = get_src_reg(c, &inst->SrcReg[2], i, 1); + brw_MUL(p, dst, src0, src1); + + brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); + brw_ADD(p, dst, dst, src2); + brw_set_saturate(p, 0); + } + } +} + +static void emit_sop(struct brw_wm_compile *c, + struct prog_instruction *inst, GLuint cond) +{ + struct brw_compile *p = &c->func; + GLuint mask = inst->DstReg.WriteMask; + struct brw_reg dst, src0, src1; + int i; + + for (i = 0; i < 4; i++) { + if (mask & (1<SrcReg[0], i, 1); + src1 = get_src_reg(c, &inst->SrcReg[1], i, 1); + brw_MOV(p, dst, brw_imm_f(0)); + brw_CMP(p, brw_null_reg(), cond, src0, src1); + brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); + brw_MOV(p, dst, brw_imm_f(1.0)); + brw_set_predicate_control_flag_value(p, 0xff); + } + } +} + +static void emit_slt(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + emit_sop(c, inst, BRW_CONDITIONAL_L); +} + +static void emit_sle(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + emit_sop(c, inst, BRW_CONDITIONAL_LE); +} + +static void emit_sgt(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + emit_sop(c, inst, BRW_CONDITIONAL_G); +} + +static void emit_sge(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + emit_sop(c, inst, BRW_CONDITIONAL_GE); +} + +static void emit_seq(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + emit_sop(c, inst, BRW_CONDITIONAL_EQ); +} + +static void emit_sne(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + emit_sop(c, inst, BRW_CONDITIONAL_NEQ); +} +/* TODO + BIAS on SIMD8 not workind yet... + */ +static void emit_txb(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_compile *p = &c->func; + struct brw_reg dst[4], src[4], payload_reg; + GLuint i; + payload_reg = get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, 0, 1, 0, 0); + for (i = 0; i < 4; i++) + dst[i] = get_dst_reg(c, inst, i, 1); + for (i = 0; i < 4; i++) + src[i] = get_src_reg(c, &inst->SrcReg[0], i, 1); + + switch (inst->TexSrcTarget) { + case TEXTURE_1D_INDEX: + brw_MOV(p, brw_message_reg(2), src[0]); + brw_MOV(p, brw_message_reg(3), brw_imm_f(0)); + brw_MOV(p, brw_message_reg(4), brw_imm_f(0)); + break; + case TEXTURE_2D_INDEX: + case TEXTURE_RECT_INDEX: + brw_MOV(p, brw_message_reg(2), src[0]); + brw_MOV(p, brw_message_reg(3), src[1]); + brw_MOV(p, brw_message_reg(4), brw_imm_f(0)); + break; + default: + brw_MOV(p, brw_message_reg(2), src[0]); + brw_MOV(p, brw_message_reg(3), src[1]); + brw_MOV(p, brw_message_reg(4), src[2]); + break; + } + brw_MOV(p, brw_message_reg(5), src[3]); + brw_MOV(p, brw_message_reg(6), brw_imm_f(0)); + brw_SAMPLE(p, + retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW), + 1, + retype(payload_reg, BRW_REGISTER_TYPE_UW), + inst->TexSrcUnit + 1, /* surface */ + inst->TexSrcUnit, /* sampler */ + inst->DstReg.WriteMask, + BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS, + 4, + 4, + 0); +} + +static void emit_tex(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_compile *p = &c->func; + struct brw_reg dst[4], src[4], payload_reg; + GLuint msg_len; + GLuint i, nr; + GLuint emit; + + payload_reg = get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, 0, 1, 0, 0); + for (i = 0; i < 4; i++) + dst[i] = get_dst_reg(c, inst, i, 1); + for (i = 0; i < 4; i++) + src[i] = get_src_reg(c, &inst->SrcReg[0], i, 1); + + + switch (inst->TexSrcTarget) { + case TEXTURE_1D_INDEX: + emit = WRITEMASK_X; + nr = 1; + break; + case TEXTURE_2D_INDEX: + case TEXTURE_RECT_INDEX: + emit = WRITEMASK_XY; + nr = 2; + break; + default: + emit = WRITEMASK_XYZ; + nr = 3; + break; + } + msg_len = 1; + + for (i = 0; i < nr; i++) { + static const GLuint swz[4] = {0,1,2,2}; + if (emit & (1<TexSrcUnit + 1, /* surface */ + inst->TexSrcUnit, /* sampler */ + inst->DstReg.WriteMask, + BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE, + 4, + 4, + 0); +} + +static void post_wm_emit( struct brw_wm_compile *c ) +{ + GLuint nr_insns = c->fp->program.Base.NumInstructions; + GLuint insn, target_insn; + struct prog_instruction *inst1, *inst2; + struct brw_instruction *brw_inst1, *brw_inst2; + int offset; + for (insn = 0; insn < nr_insns; insn++) { + inst1 = &c->fp->program.Base.Instructions[insn]; + brw_inst1 = inst1->Data; + switch (inst1->Opcode) { + case OPCODE_CAL: + target_insn = inst1->BranchTarget; + inst2 = &c->fp->program.Base.Instructions[target_insn]; + brw_inst2 = inst2->Data; + offset = brw_inst2 - brw_inst1; + brw_set_src1(brw_inst1, brw_imm_d(offset*16)); + break; + default: + break; + } + } +} + +static void brw_wm_emit_glsl(struct brw_wm_compile *c) + +{ +#define MAX_IFSN 32 +#define MAX_LOOP_DEPTH 32 + struct brw_instruction *if_inst[MAX_IFSN], *loop_inst[MAX_LOOP_DEPTH]; + struct brw_instruction *inst0, *inst1; + int i, if_insn = 0, loop_insn = 0; + struct brw_compile *p = &c->func; + brw_init_compile(&c->func); + c->reg_index = 0; + prealloc_reg(c); + brw_set_compression_control(p, BRW_COMPRESSION_NONE); + for (i = 0; i < c->nr_fp_insns; i++) { + struct prog_instruction *inst = &c->prog_instructions[i]; + struct prog_instruction *orig_inst; + + if ((orig_inst = inst->Data) != 0) + orig_inst->Data = current_insn(p); + + switch (inst->Opcode) { + case WM_PIXELXY: + emit_pixel_xy(c, inst); + break; + case WM_DELTAXY: + emit_delta_xy(c, inst); + break; + case WM_PIXELW: + emit_pixel_w(c, inst); + break; + case WM_LINTERP: + emit_linterp(c, inst); + break; + case WM_PINTERP: + emit_pinterp(c, inst); + break; + case WM_CINTERP: + emit_cinterp(c, inst); + break; + case WM_FB_WRITE: + emit_fb_write(c, inst); + break; + case OPCODE_ABS: + emit_abs(c, inst); + break; + case OPCODE_ADD: + emit_add(c, inst); + break; + case OPCODE_SUB: + emit_sub(c, inst); + break; + case OPCODE_FRC: + emit_frc(c, inst); + break; + case OPCODE_FLR: + emit_flr(c, inst); + break; + case OPCODE_LRP: + emit_lrp(c, inst); + break; + case OPCODE_MOV: + emit_mov(c, inst); + break; + case OPCODE_DP3: + emit_dp3(c, inst); + break; + case OPCODE_DP4: + emit_dp4(c, inst); + break; + case OPCODE_XPD: + emit_xpd(c, inst); + break; + case OPCODE_DPH: + emit_dph(c, inst); + break; + case OPCODE_RCP: + emit_rcp(c, inst); + break; + case OPCODE_RSQ: + emit_rsq(c, inst); + break; + case OPCODE_SIN: + emit_sin(c, inst); + break; + case OPCODE_COS: + emit_cos(c, inst); + break; + case OPCODE_EX2: + emit_ex2(c, inst); + break; + case OPCODE_LG2: + emit_lg2(c, inst); + break; + case OPCODE_MAX: + emit_max(c, inst); + break; + case OPCODE_MIN: + emit_min(c, inst); + break; + case OPCODE_SLT: + emit_slt(c, inst); + break; + case OPCODE_SLE: + emit_sle(c, inst); + break; + case OPCODE_SGT: + emit_sgt(c, inst); + break; + case OPCODE_SGE: + emit_sge(c, inst); + break; + case OPCODE_SEQ: + emit_seq(c, inst); + break; + case OPCODE_SNE: + emit_sne(c, inst); + break; + case OPCODE_MUL: + emit_mul(c, inst); + break; + case OPCODE_POW: + emit_pow(c, inst); + break; + case OPCODE_MAD: + emit_mad(c, inst); + break; + case OPCODE_TEX: + emit_tex(c, inst); + break; + case OPCODE_TXB: + emit_txb(c, inst); + break; + case OPCODE_IF: + assert(if_insn < MAX_IFSN); + if_inst[if_insn++] = brw_IF(p, BRW_EXECUTE_8); + break; + case OPCODE_ELSE: + if_inst[if_insn-1] = brw_ELSE(p, if_inst[if_insn-1]); + break; + case OPCODE_ENDIF: + assert(if_insn > 0); + brw_ENDIF(p, if_inst[--if_insn]); + break; + case OPCODE_BGNSUB: + case OPCODE_ENDSUB: + break; + case OPCODE_CAL: + brw_push_insn_state(p); + brw_set_mask_control(p, BRW_MASK_DISABLE); + brw_set_predicate_control(p, BRW_PREDICATE_NONE); + brw_ADD(p, c->ret_reg, brw_ip_reg(), brw_imm_d(2*16)); + orig_inst = inst->Data; + orig_inst->Data = current_insn(p); + brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16)); + brw_pop_insn_state(p); + break; + case OPCODE_RET: + brw_push_insn_state(p); + brw_set_mask_control(p, BRW_MASK_DISABLE); + brw_set_predicate_control(p, BRW_PREDICATE_NONE); + brw_MOV(p, brw_ip_reg(), c->ret_reg); + brw_pop_insn_state(p); + break; + case OPCODE_BGNLOOP: + loop_inst[loop_insn++] = brw_DO(p, BRW_EXECUTE_8); + break; + case OPCODE_BRK: + brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); + brw_BREAK(p); + brw_set_predicate_control(p, BRW_PREDICATE_NONE); + break; + case OPCODE_ENDLOOP: + loop_insn--; + inst0 = inst1 = brw_WHILE(p, loop_inst[loop_insn]); + /* patch all the BREAK instructions from + last BEGINLOOP */ + while (inst0 > loop_inst[loop_insn]) { + inst0--; + if (inst0->header.opcode == BRW_OPCODE_BREAK) { + inst0->bits3.if_else.jump_count = inst1 - inst0 + 1; + inst0->bits3.if_else.pop_count = 0; + } + } + break; + default: + _mesa_printf("unsupported IR in fragment shader %d\n", + inst->Opcode); + } + } + post_wm_emit(c); +} + +void brw_wm_glsl_emit(struct brw_wm_compile *c) +{ + brw_wm_pass_fp(c); + c->tmp_index = 127; + brw_wm_emit_glsl(c); + c->prog_data.total_grf = c->reg_index; + c->prog_data.total_scratch = 0; +} diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass2.c b/src/mesa/drivers/dri/i965/brw_wm_pass2.c index a1edbd6168..c1ce6a9b6b 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_pass2.c +++ b/src/mesa/drivers/dri/i965/brw_wm_pass2.c @@ -328,7 +328,7 @@ void brw_wm_pass2( struct brw_wm_compile *c ) c->state = PASS2_DONE; if (INTEL_DEBUG & DEBUG_WM) { - brw_wm_print_program(c, "pass2/done"); + brw_wm_print_program(c, "pass2/done"); } } diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c index ff5cb31bdd..401864fc4e 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c @@ -34,6 +34,7 @@ #include "brw_context.h" #include "brw_state.h" #include "brw_defines.h" +#include "brw_wm.h" #include "bufmgr.h" /*********************************************************************** @@ -134,9 +135,13 @@ static void upload_wm_unit(struct brw_context *brw ) if (fp->UsesKill || brw->attribs.Color->AlphaEnabled) wm.wm5.program_uses_killpixel = 1; + + if (brw_wm_is_glsl(fp)) + wm.wm5.enable_8_pix = 1; + else + wm.wm5.enable_16_pix = 1; } - wm.wm5.enable_16_pix = 1; wm.wm5.thread_dispatch_enable = 1; /* AKA: color_write */ wm.wm5.legacy_line_rast = 0; wm.wm5.legacy_global_depth_bias = 0; -- cgit v1.2.3 From 4fc02ad000a0948ab77306980492924f5beebc0a Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Tue, 3 Jul 2007 15:27:43 +0800 Subject: Fix a nasty bug... --- src/mesa/drivers/dri/i965/brw_vs_emit.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index fa94d5b1a8..7dc6f9bf93 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -137,7 +137,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c ) for (i = 0; i < 128; i++) { if (c->output_regs[i].used_in_src) { - c->regs[PROGRAM_OUTPUT][i] = brw_vec8_grf(reg, 0); + c->output_regs[i].reg = brw_vec8_grf(reg, 0); reg++; } } @@ -958,6 +958,9 @@ void brw_vs_emit(struct brw_vs_compile *c ) struct brw_instruction *if_inst[MAX_IFSN]; struct brw_indirect stack_index = brw_indirect(0, 0); + GLuint index; + GLuint file; + if (INTEL_DEBUG & DEBUG_VS) { _mesa_printf("\n\n\nvs-emit:\n"); _mesa_print_program(&c->vp->program.Base); @@ -998,8 +1001,8 @@ void brw_vs_emit(struct brw_vs_compile *c ) if (inst->Opcode != OPCODE_SWZ) for (i = 0; i < 3; i++) { struct prog_src_register *src = &inst->SrcReg[i]; - GLuint index = src->Index; - GLuint file = src->File; + index = src->Index; + file = src->File; if (file == PROGRAM_OUTPUT&&c->output_regs[index].used_in_src) args[i] = c->output_regs[index].reg; else @@ -1009,8 +1012,13 @@ void brw_vs_emit(struct brw_vs_compile *c ) /* Get dest regs. Note that it is possible for a reg to be both * dst and arg, given the static allocation of registers. So * care needs to be taken emitting multi-operation instructions. - */ - dst = get_dst(c, inst->DstReg); + */ + index = inst->DstReg.Index; + file = inst->DstReg.File; + if (file == PROGRAM_OUTPUT && c->output_regs[index].used_in_src) + dst = c->output_regs[index].reg; + else + dst = get_dst(c, inst->DstReg); switch (inst->Opcode) { case OPCODE_ABS: @@ -1157,7 +1165,7 @@ void brw_vs_emit(struct brw_vs_compile *c ) if (inst->DstReg.File == PROGRAM_OUTPUT &&inst->DstReg.Index != VERT_RESULT_HPOS &&c->output_regs[inst->DstReg.Index].used_in_src) - brw_MOV(p, get_dst(c, inst->DstReg), dst); + brw_MOV(p, dst, c->output_regs[inst->DstReg.Index].reg); release_tmps(c); } -- cgit v1.2.3 From 285b326c606e9b2f90e4fe177b15b3fa23239b86 Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Wed, 4 Jul 2007 10:51:57 +0800 Subject: fix issue with output as src register. --- src/mesa/drivers/dri/i965/brw_vs_emit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 7dc6f9bf93..18ede5f6cd 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -1165,7 +1165,7 @@ void brw_vs_emit(struct brw_vs_compile *c ) if (inst->DstReg.File == PROGRAM_OUTPUT &&inst->DstReg.Index != VERT_RESULT_HPOS &&c->output_regs[inst->DstReg.Index].used_in_src) - brw_MOV(p, dst, c->output_regs[inst->DstReg.Index].reg); + brw_MOV(p, get_dst(c, inst->DstReg), dst); release_tmps(c); } -- cgit v1.2.3 From 575f3e918f00bdc0faa4a173820015b24175696f Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Thu, 5 Jul 2007 11:10:24 +0800 Subject: support "discard"; --- src/mesa/drivers/dri/i965/brw_wm.h | 1 + src/mesa/drivers/dri/i965/brw_wm_glsl.c | 15 +++++++++++++++ 2 files changed, 16 insertions(+) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index 4143d5be6c..931c0038d4 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -237,6 +237,7 @@ struct brw_wm_compile { struct brw_reg reg; } wm_regs[PROGRAM_PAYLOAD+1][256][4]; struct brw_reg ret_reg; + struct brw_reg emit_mask_reg; GLuint reg_index; GLuint tmp_index; }; diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index cdd7976607..4988df2b0e 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -132,6 +132,7 @@ static void prealloc_reg(struct brw_wm_compile *c) c->prog_data.urb_read_length = nr_interp_regs * 2; c->prog_data.curb_read_length = c->nr_creg; c->ret_reg = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, c->reg_index, 0); + c->emit_mask_reg = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, c->reg_index, 1); c->reg_index++; } @@ -768,6 +769,17 @@ static void emit_lrp(struct brw_wm_compile *c, } } +static void emit_kil(struct brw_wm_compile *c) +{ + struct brw_compile *p = &c->func; + struct brw_reg depth = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW); + brw_push_insn_state(p); + brw_set_mask_control(p, BRW_MASK_DISABLE); + brw_NOT(p, c->emit_mask_reg, brw_mask_reg(1)); //IMASK + brw_AND(p, depth, c->emit_mask_reg, depth); + brw_pop_insn_state(p); +} + static void emit_mad(struct brw_wm_compile *c, struct prog_instruction *inst) { @@ -1107,6 +1119,9 @@ static void brw_wm_emit_glsl(struct brw_wm_compile *c) case OPCODE_TXB: emit_txb(c, inst); break; + case OPCODE_KIL_NV: + emit_kil(c); + break; case OPCODE_IF: assert(if_insn < MAX_IFSN); if_inst[if_insn++] = brw_IF(p, BRW_EXECUTE_8); -- cgit v1.2.3 From 719cf0b7958d0dedf8727c97eaddb6a1f31977e1 Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Tue, 17 Jul 2007 11:19:52 +0800 Subject: Use ProgramStringNotify --- src/mesa/drivers/dri/i965/brw_context.c | 27 --------------------------- src/mesa/shader/program.c | 2 ++ 2 files changed, 2 insertions(+), 27 deletions(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index badf178b68..8366f14dbe 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -62,30 +62,6 @@ static const struct dri_extension brw_extensions[] = { NULL, NULL } }; -static void brwLinkProgram(GLcontext *ctx, GLuint program) -{ - struct brw_context *brw = brw_context(ctx); - struct brw_vertex_program *vert_prog; - struct brw_fragment_program *frag_prog; - struct gl_shader_program *sh_prog; - _mesa_link_program(ctx, program); - - sh_prog = _mesa_lookup_shader_program(ctx, program); - if (sh_prog) { - sh_prog->FragmentProgram = - _mesa_realloc(sh_prog->FragmentProgram, - sizeof(struct gl_fragment_program), - sizeof(struct brw_fragment_program)); - frag_prog = (struct brw_fragment_program *)sh_prog->FragmentProgram; - frag_prog->id = brw->program_id++; - sh_prog->VertexProgram = _mesa_realloc(sh_prog->VertexProgram, - sizeof(struct gl_vertex_program), - sizeof(struct brw_vertex_program)); - vert_prog = (struct brw_vertex_program *)sh_prog->VertexProgram; - vert_prog->id = brw->program_id++; - } -} - static void brwUseProgram(GLcontext *ctx, GLuint program) { struct brw_context *brw = brw_context(ctx); @@ -97,15 +73,12 @@ static void brwUseProgram(GLcontext *ctx, GLuint program) ctx->FragmentProgram.Enabled = GL_TRUE; brw->attribs.VertexProgram->Current = sh_prog->VertexProgram; brw->attribs.FragmentProgram->Current = sh_prog->FragmentProgram; - brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM; - brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM; } } static void brwInitProgFuncs( struct dd_function_table *functions ) { functions->UseProgram = brwUseProgram; - functions->LinkProgram = brwLinkProgram; } static void brwInitDriverFunctions( struct dd_function_table *functions ) { diff --git a/src/mesa/shader/program.c b/src/mesa/shader/program.c index 4205919828..03be368a92 100644 --- a/src/mesa/shader/program.c +++ b/src/mesa/shader/program.c @@ -242,6 +242,8 @@ _mesa_init_vertex_program( GLcontext *ctx, struct gl_vertex_program *prog, struct gl_program * _mesa_new_program(GLcontext *ctx, GLenum target, GLuint id) { + if (ctx->Driver.NewProgram) + return ctx->Driver.NewProgram(ctx, target, id); switch (target) { case GL_VERTEX_PROGRAM_ARB: /* == GL_VERTEX_PROGRAM_NV */ return _mesa_init_vertex_program(ctx, CALLOC_STRUCT(gl_vertex_program), -- cgit v1.2.3 From c6d042acc94411b63f922ef68f24aa5426c0a69e Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Tue, 17 Jul 2007 16:52:03 +0800 Subject: Fix SOP in fragment shader, brick is ok now. --- progs/glsl/CH06-brick.frag.txt | 6 +----- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 6 ++++-- 2 files changed, 5 insertions(+), 7 deletions(-) (limited to 'src/mesa') diff --git a/progs/glsl/CH06-brick.frag.txt b/progs/glsl/CH06-brick.frag.txt index 388c5f9e66..06ef04e3af 100644 --- a/progs/glsl/CH06-brick.frag.txt +++ b/progs/glsl/CH06-brick.frag.txt @@ -23,11 +23,7 @@ void main() position = MCposition / BrickSize; -// if (fract(position.y * 0.5) > 0.5) -// position.x += 0.5; - float tmp; - tmp = fract(position.y * 0.5); - if (tmp > 0.5) + if (fract(position.y * 0.5) > 0.5) position.x += 0.5; position = fract(position); diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 4988df2b0e..09e7590367 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -811,18 +811,20 @@ static void emit_sop(struct brw_wm_compile *c, struct brw_reg dst, src0, src1; int i; + brw_push_insn_state(p); for (i = 0; i < 4; i++) { if (mask & (1<SrcReg[0], i, 1); src1 = get_src_reg(c, &inst->SrcReg[1], i, 1); - brw_MOV(p, dst, brw_imm_f(0)); brw_CMP(p, brw_null_reg(), cond, src0, src1); + brw_set_predicate_control(p, BRW_PREDICATE_NONE); + brw_MOV(p, dst, brw_imm_f(0.0)); brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); brw_MOV(p, dst, brw_imm_f(1.0)); - brw_set_predicate_control_flag_value(p, 0xff); } } + brw_pop_insn_state(p); } static void emit_slt(struct brw_wm_compile *c, -- cgit v1.2.3 From c702a7100e2aa83241e89850a97bcc23e1c6fedb Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Tue, 24 Jul 2007 11:09:34 +0800 Subject: DDX DDY support, not very accurate --- src/mesa/drivers/dri/i965/brw_wm.h | 1 + src/mesa/drivers/dri/i965/brw_wm_fp.c | 37 ++++++++++++++++++ src/mesa/drivers/dri/i965/brw_wm_glsl.c | 66 ++++++++++++++++++++++++++++++++- 3 files changed, 103 insertions(+), 1 deletion(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index 931c0038d4..22e77287f4 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -194,6 +194,7 @@ struct brw_wm_compile { GLuint nr_fp_insns; GLuint fp_temp; GLuint fp_interp_emitted; + GLuint fp_deriv_emitted; struct prog_src_register pixel_xy; struct prog_src_register delta_xy; diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c index 403160c494..0a6e516b93 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_fp.c +++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c @@ -361,6 +361,37 @@ static void emit_interp( struct brw_wm_compile *c, c->fp_interp_emitted |= 1<SrcReg[0].Index; + struct prog_src_register interp = src_reg(PROGRAM_PAYLOAD, idx); + + c->fp_deriv_emitted |= 1<DstReg, + 0, 0, 0, + interp, + get_pixel_w(c), + src_undef()); +} + +static void emit_ddy( struct brw_wm_compile *c, + const struct prog_instruction *inst ) +{ + GLuint idx = inst->SrcReg[0].Index; + struct prog_src_register interp = src_reg(PROGRAM_PAYLOAD, idx); + + c->fp_deriv_emitted |= 1<DstReg, + 0, 0, 0, + interp, + get_pixel_w(c), + src_undef()); +} /*********************************************************************** * Hacks to extend the program parameter and constant lists. @@ -907,6 +938,12 @@ void brw_wm_pass_fp( struct brw_wm_compile *c ) */ out->DstReg.WriteMask = 0; break; + case OPCODE_DDX: + emit_ddx(c, inst); + break; + case OPCODE_DDY: + emit_ddy(c, inst); + break; case OPCODE_END: emit_fog(c); emit_fb_write(c); diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 09e7590367..f47f139282 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -16,6 +16,8 @@ GLboolean brw_wm_is_glsl(struct gl_fragment_program *fp) case OPCODE_CAL: case OPCODE_BRK: case OPCODE_RET: + case OPCODE_DDX: + case OPCODE_DDY: case OPCODE_BGNLOOP: return GL_TRUE; default: @@ -92,7 +94,7 @@ static void prealloc_reg(struct brw_wm_compile *c) int i, j; struct brw_reg reg; int nr_interp_regs = 0; - GLuint inputs = FRAG_BIT_WPOS | c->fp_interp_emitted; + GLuint inputs = FRAG_BIT_WPOS | c->fp_interp_emitted | c->fp_deriv_emitted; for (i = 0; i < 4; i++) { reg = (i < c->key.nr_depth_regs) @@ -862,6 +864,62 @@ static void emit_sne(struct brw_wm_compile *c, { emit_sop(c, inst, BRW_CONDITIONAL_NEQ); } + +static void emit_ddx(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_compile *p = &c->func; + GLuint mask = inst->DstReg.WriteMask; + struct brw_reg interp[4]; + struct brw_reg dst; + struct brw_reg src0, w; + GLuint nr, i; + src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1); + w = get_src_reg(c, &inst->SrcReg[1], 3, 1); + nr = src0.nr; + interp[0] = brw_vec1_grf(nr, 0); + interp[1] = brw_vec1_grf(nr, 4); + interp[2] = brw_vec1_grf(nr+1, 0); + interp[3] = brw_vec1_grf(nr+1, 4); + brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF); + for(i = 0; i < 4; i++ ) { + if (mask & (1<func; + GLuint mask = inst->DstReg.WriteMask; + struct brw_reg interp[4]; + struct brw_reg dst; + struct brw_reg src0, w; + GLuint nr, i; + + src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1); + nr = src0.nr; + w = get_src_reg(c, &inst->SrcReg[1], 3, 1); + interp[0] = brw_vec1_grf(nr, 0); + interp[1] = brw_vec1_grf(nr, 4); + interp[2] = brw_vec1_grf(nr+1, 0); + interp[3] = brw_vec1_grf(nr+1, 4); + brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF); + for(i = 0; i < 4; i++ ) { + if (mask & (1< Date: Tue, 18 Sep 2007 11:32:25 +0800 Subject: fix double free in 965-glsl branch --- src/mesa/drivers/dri/i965/brw_vs_emit.c | 2 ++ src/mesa/drivers/dri/i965/brw_wm_glsl.c | 2 ++ src/mesa/drivers/dri/i965/intel_context.c | 2 ++ 3 files changed, 6 insertions(+) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 18ede5f6cd..f689f7b305 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -1173,4 +1173,6 @@ void brw_vs_emit(struct brw_vs_compile *c ) end_inst = &p->store[p->nr_insn]; emit_vertex_write(c); post_vs_emit(c, end_inst); + for (insn = 0; insn < nr_insns; insn++) + c->vp->program.Base.Instructions[insn].Data = NULL; } diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index f47f139282..f03866d9b9 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -1246,6 +1246,8 @@ static void brw_wm_emit_glsl(struct brw_wm_compile *c) } } post_wm_emit(c); + for (i = 0; i < c->fp->program.Base.NumInstructions; i++) + c->fp->program.Base.Instructions[i].Data = NULL; } void brw_wm_glsl_emit(struct brw_wm_compile *c) diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c index 3215cc7218..35babcac23 100644 --- a/src/mesa/drivers/dri/i965/intel_context.c +++ b/src/mesa/drivers/dri/i965/intel_context.c @@ -555,6 +555,8 @@ void intelDestroyContext(__DRIcontextPrivate *driContextPriv) #endif /* free the Mesa context */ + intel->ctx.VertexProgram.Current = NULL; + intel->ctx.FragmentProgram.Current = NULL; _mesa_destroy_context(&intel->ctx); } -- cgit v1.2.3 From ec9e7bc753316cebed9c9ce12aa5513486c6b8d0 Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Tue, 18 Sep 2007 12:59:50 +0800 Subject: ARB_shader_object ARB_vertex_shader ARB_fragment_shader in 965-glsl branch --- src/mesa/drivers/dri/i965/intel_context.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c index 35babcac23..ac8aa5bd52 100644 --- a/src/mesa/drivers/dri/i965/intel_context.c +++ b/src/mesa/drivers/dri/i965/intel_context.c @@ -82,6 +82,9 @@ int INTEL_DEBUG = (0); #define need_GL_EXT_multi_draw_arrays #define need_GL_EXT_secondary_color #define need_GL_VERSION_2_0 +#define need_GL_ARB_shader_objects +#define need_GL_ARB_vertex_shader + #include "extension_helper.h" #ifndef VERBOSE @@ -185,6 +188,9 @@ const struct dri_extension card_extensions[] = { "GL_NV_blend_square", NULL }, { "GL_SGIS_generate_mipmap", NULL }, { "GL_ARB_shading_language_100", GL_VERSION_2_0_functions}, + { "GL_ARB_shader_objects", GL_ARB_shader_objects_functions}, + { "GL_ARB_vertex_shader", GL_ARB_vertex_shader_functions}, + { "GL_ARB_fragment_shader", NULL }, /* XXX not implement yet, to compile builtin glsl lib */ { "GL_ARB_draw_buffers", NULL }, { NULL, NULL } -- cgit v1.2.3 From 35a0634e358baac832d6e5a76630fcae57a948a7 Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Thu, 27 Sep 2007 15:47:00 +0800 Subject: fix issue when only fragment shader or vertex shader is used --- src/mesa/drivers/dri/i965/brw_context.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 8366f14dbe..2031d556c1 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -69,11 +69,18 @@ static void brwUseProgram(GLcontext *ctx, GLuint program) _mesa_use_program(ctx, program); sh_prog = ctx->Shader.CurrentProgram; if (sh_prog) { - ctx->VertexProgram.Enabled = GL_TRUE; - ctx->FragmentProgram.Enabled = GL_TRUE; - brw->attribs.VertexProgram->Current = sh_prog->VertexProgram; - brw->attribs.FragmentProgram->Current = sh_prog->FragmentProgram; - } + if (sh_prog->VertexProgram) { + brw->attribs.VertexProgram->Current = sh_prog->VertexProgram; + ctx->VertexProgram.Enabled = GL_TRUE; + }else + ctx->VertexProgram.Enabled = GL_FALSE; + + if (sh_prog->FragmentProgram) { + brw->attribs.FragmentProgram->Current = sh_prog->FragmentProgram; + ctx->FragmentProgram.Enabled = GL_TRUE; + } else + ctx->VertexProgram.Enabled = GL_FALSE; + } } static void brwInitProgFuncs( struct dd_function_table *functions ) -- cgit v1.2.3 From b1e549d1762536ebb3f7c11461c4554d4613c37a Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Thu, 27 Sep 2007 16:17:24 +0800 Subject: handle INT op, still require high level handle of integer to be correct --- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index f03866d9b9..4bce150491 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -12,6 +12,7 @@ GLboolean brw_wm_is_glsl(struct gl_fragment_program *fp) struct prog_instruction *inst = &fp->Base.Instructions[i]; switch (inst->Opcode) { case OPCODE_IF: + case OPCODE_INT: case OPCODE_ENDIF: case OPCODE_CAL: case OPCODE_BRK: @@ -170,6 +171,24 @@ static void emit_abs( struct brw_wm_compile *c, brw_set_saturate(p, 0); } +static void emit_mov_int( struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + int i; + struct brw_compile *p = &c->func; + GLuint mask = inst->DstReg.WriteMask; + brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF); + for (i = 0; i < 4; i++) { + if (mask & (1<SrcReg[0], i, 1), BRW_REGISTER_TYPE_D); + brw_MOV(p, dst, src); + } + } + brw_set_saturate(p, 0); +} + static void emit_mov( struct brw_wm_compile *c, struct prog_instruction *inst) { @@ -1107,6 +1126,9 @@ static void brw_wm_emit_glsl(struct brw_wm_compile *c) case OPCODE_LRP: emit_lrp(c, inst); break; + case OPCODE_INT: + emit_mov_int(c, inst); + break; case OPCODE_MOV: emit_mov(c, inst); break; -- cgit v1.2.3 From 4087c90effecdf2f466e2ddcf88ec2faf0db034f Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Fri, 28 Sep 2007 16:37:01 +0800 Subject: support nested function call in pixel shader --- src/mesa/drivers/dri/i965/brw_wm.h | 2 +- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 35 +++++++++++++++++++++++---------- 2 files changed, 26 insertions(+), 11 deletions(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index 22e77287f4..ca9bc3a07b 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -237,7 +237,7 @@ struct brw_wm_compile { GLboolean inited; struct brw_reg reg; } wm_regs[PROGRAM_PAYLOAD+1][256][4]; - struct brw_reg ret_reg; + struct brw_reg stack; struct brw_reg emit_mask_reg; GLuint reg_index; GLuint tmp_index; diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 4bce150491..c6fd724921 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -134,9 +134,10 @@ static void prealloc_reg(struct brw_wm_compile *c) c->prog_data.first_curbe_grf = c->key.nr_depth_regs * 2; c->prog_data.urb_read_length = nr_interp_regs * 2; c->prog_data.curb_read_length = c->nr_creg; - c->ret_reg = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, c->reg_index, 0); - c->emit_mask_reg = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, c->reg_index, 1); + c->emit_mask_reg = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, c->reg_index, 0); c->reg_index++; + c->stack = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, c->reg_index, 0); + c->reg_index += 2; } static struct brw_reg get_dst_reg(struct brw_wm_compile *c, @@ -1075,10 +1076,14 @@ static void brw_wm_emit_glsl(struct brw_wm_compile *c) struct brw_instruction *inst0, *inst1; int i, if_insn = 0, loop_insn = 0; struct brw_compile *p = &c->func; + struct brw_indirect stack_index = brw_indirect(0, 0); + brw_init_compile(&c->func); c->reg_index = 0; prealloc_reg(c); brw_set_compression_control(p, BRW_COMPRESSION_NONE); + brw_MOV(p, get_addr_reg(stack_index), brw_address(c->stack)); + for (i = 0; i < c->nr_fp_insns; i++) { struct prog_instruction *inst = &c->prog_instructions[i]; struct prog_instruction *orig_inst; @@ -1227,19 +1232,29 @@ static void brw_wm_emit_glsl(struct brw_wm_compile *c) case OPCODE_CAL: brw_push_insn_state(p); brw_set_mask_control(p, BRW_MASK_DISABLE); - brw_set_predicate_control(p, BRW_PREDICATE_NONE); - brw_ADD(p, c->ret_reg, brw_ip_reg(), brw_imm_d(2*16)); - orig_inst = inst->Data; - orig_inst->Data = current_insn(p); - brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16)); - brw_pop_insn_state(p); + brw_set_predicate_control(p, BRW_PREDICATE_NONE); + brw_set_access_mode(p, BRW_ALIGN_1); + brw_ADD(p, deref_1uw(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16)); + brw_set_access_mode(p, BRW_ALIGN_16); + brw_ADD(p, get_addr_reg(stack_index), + get_addr_reg(stack_index), brw_imm_d(4)); + orig_inst = inst->Data; + orig_inst->Data = &p->store[p->nr_insn]; + brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16)); + brw_pop_insn_state(p); break; + case OPCODE_RET: brw_push_insn_state(p); brw_set_mask_control(p, BRW_MASK_DISABLE); - brw_set_predicate_control(p, BRW_PREDICATE_NONE); - brw_MOV(p, brw_ip_reg(), c->ret_reg); + brw_set_predicate_control(p, BRW_PREDICATE_NONE); + brw_ADD(p, get_addr_reg(stack_index), + get_addr_reg(stack_index), brw_imm_d(-4)); + brw_set_access_mode(p, BRW_ALIGN_1); + brw_MOV(p, brw_ip_reg(), deref_1uw(stack_index, 0)); + brw_set_access_mode(p, BRW_ALIGN_16); brw_pop_insn_state(p); + break; case OPCODE_BGNLOOP: loop_inst[loop_insn++] = brw_DO(p, BRW_EXECUTE_8); -- cgit v1.2.3 From e75ae0dc792b9fe599b68d7a9ea0ab22413da424 Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Fri, 28 Sep 2007 17:04:48 +0800 Subject: fix --- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index c6fd724921..9b0b7aaa55 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -1232,7 +1232,6 @@ static void brw_wm_emit_glsl(struct brw_wm_compile *c) case OPCODE_CAL: brw_push_insn_state(p); brw_set_mask_control(p, BRW_MASK_DISABLE); - brw_set_predicate_control(p, BRW_PREDICATE_NONE); brw_set_access_mode(p, BRW_ALIGN_1); brw_ADD(p, deref_1uw(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16)); brw_set_access_mode(p, BRW_ALIGN_16); @@ -1247,7 +1246,6 @@ static void brw_wm_emit_glsl(struct brw_wm_compile *c) case OPCODE_RET: brw_push_insn_state(p); brw_set_mask_control(p, BRW_MASK_DISABLE); - brw_set_predicate_control(p, BRW_PREDICATE_NONE); brw_ADD(p, get_addr_reg(stack_index), get_addr_reg(stack_index), brw_imm_d(-4)); brw_set_access_mode(p, BRW_ALIGN_1); -- cgit v1.2.3 From b0b48798c7e854d2e36e0317bf94b7385e815242 Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Sat, 29 Sep 2007 15:00:52 +0800 Subject: support continue, fix conditional --- src/mesa/drivers/dri/i965/brw_eu.h | 1 + src/mesa/drivers/dri/i965/brw_eu_emit.c | 14 +++++++++ src/mesa/drivers/dri/i965/brw_wm_glsl.c | 53 +++++++++++++++++++++++++++++++-- 3 files changed, 66 insertions(+), 2 deletions(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index 9b6581fd93..d44217d02f 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -815,6 +815,7 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p, struct brw_instruction *patch_insn); struct brw_instruction *brw_BREAK(struct brw_compile *p); +struct brw_instruction *brw_CONT(struct brw_compile *p); /* Forward jumps: */ void brw_land_fwd_jump(struct brw_compile *p, diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 7b95fbdac0..95f9f02753 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -611,6 +611,20 @@ struct brw_instruction *brw_BREAK(struct brw_compile *p) return insn; } +struct brw_instruction *brw_CONT(struct brw_compile *p) +{ + struct brw_instruction *insn; + insn = next_insn(p, BRW_OPCODE_CONTINUE); + brw_set_dest(insn, brw_ip_reg()); + brw_set_src0(insn, brw_ip_reg()); + brw_set_src1(insn, brw_imm_d(0x0)); + insn->header.compression_control = BRW_COMPRESSION_NONE; + insn->header.execution_size = BRW_EXECUTE_8; + insn->header.mask_control = BRW_MASK_DISABLE; + insn->bits3.if_else.pad0 = 0; + return insn; +} + /* DO/WHILE loop: */ struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size) diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 9b0b7aaa55..1f1e32ee47 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -940,6 +940,37 @@ static void emit_ddy(struct brw_wm_compile *c, brw_set_saturate(p, 0); } +static void emit_wpos_xy(struct brw_wm_compile *c, + struct prog_instruction *inst) +{ + struct brw_compile *p = &c->func; + GLuint mask = inst->DstReg.WriteMask; + struct brw_reg src0[2], dst[2]; + + dst[0] = get_dst_reg(c, inst, 0, 1); + dst[1] = get_dst_reg(c, inst, 1, 1); + + src0[0] = get_src_reg(c, &inst->SrcReg[0], 0, 1); + src0[1] = get_src_reg(c, &inst->SrcReg[0], 1, 1); + + /* Calc delta X,Y by subtracting origin in r1 from the pixel + * centers. + */ + if (mask & WRITEMASK_X) { + brw_MOV(p, + dst[0], + retype(src0[0], BRW_REGISTER_TYPE_UW)); + } + + if (mask & WRITEMASK_Y) { + /* TODO -- window_height - Y */ + brw_MOV(p, + dst[1], + negate(retype(src0[1], BRW_REGISTER_TYPE_UW))); + + } +} + /* TODO BIAS on SIMD8 not workind yet... */ @@ -1091,6 +1122,11 @@ static void brw_wm_emit_glsl(struct brw_wm_compile *c) if ((orig_inst = inst->Data) != 0) orig_inst->Data = current_insn(p); + if (inst->CondUpdate) + brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); + else + brw_set_conditionalmod(p, BRW_CONDITIONAL_NONE); + switch (inst->Opcode) { case WM_PIXELXY: emit_pixel_xy(c, inst); @@ -1110,6 +1146,9 @@ static void brw_wm_emit_glsl(struct brw_wm_compile *c) case WM_CINTERP: emit_cinterp(c, inst); break; + case WM_WPOSXY: + emit_wpos_xy(c, inst); + break; case WM_FB_WRITE: emit_fb_write(c, inst); break; @@ -1258,10 +1297,13 @@ static void brw_wm_emit_glsl(struct brw_wm_compile *c) loop_inst[loop_insn++] = brw_DO(p, BRW_EXECUTE_8); break; case OPCODE_BRK: - brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); brw_BREAK(p); brw_set_predicate_control(p, BRW_PREDICATE_NONE); break; + case OPCODE_CONT: + brw_CONT(p); + brw_set_predicate_control(p, BRW_PREDICATE_NONE); + break; case OPCODE_ENDLOOP: loop_insn--; inst0 = inst1 = brw_WHILE(p, loop_inst[loop_insn]); @@ -1272,13 +1314,20 @@ static void brw_wm_emit_glsl(struct brw_wm_compile *c) if (inst0->header.opcode == BRW_OPCODE_BREAK) { inst0->bits3.if_else.jump_count = inst1 - inst0 + 1; inst0->bits3.if_else.pop_count = 0; - } + } else if (inst0->header.opcode == BRW_OPCODE_CONTINUE) { + inst0->bits3.if_else.jump_count = inst1 - inst0; + inst0->bits3.if_else.pop_count = 0; + } } break; default: _mesa_printf("unsupported IR in fragment shader %d\n", inst->Opcode); } + if (inst->CondUpdate) + brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); + else + brw_set_predicate_control(p, BRW_PREDICATE_NONE); } post_wm_emit(c); for (i = 0; i < c->fp->program.Base.NumInstructions; i++) -- cgit v1.2.3 From 3d6c4109902b555a3f8076170d572c7caeb6cbfe Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Sun, 30 Sep 2007 13:47:05 +0800 Subject: fragment shader function call fix, gl_FragCoord fix --- src/mesa/drivers/dri/i965/brw_eu.h | 5 +++++ src/mesa/drivers/dri/i965/brw_wm_glsl.c | 6 +++--- 2 files changed, 8 insertions(+), 3 deletions(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index d44217d02f..5c98767c3e 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -648,6 +648,11 @@ static __inline struct brw_reg deref_1uw(struct brw_indirect ptr, GLint offset) return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UW); } +static __inline struct brw_reg deref_1ud(struct brw_indirect ptr, GLint offset) +{ + return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UD); +} + static __inline struct brw_reg get_addr_reg(struct brw_indirect ptr) { return brw_address_reg(ptr.addr_subnr); diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 1f1e32ee47..58cdf72e37 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -966,7 +966,7 @@ static void emit_wpos_xy(struct brw_wm_compile *c, /* TODO -- window_height - Y */ brw_MOV(p, dst[1], - negate(retype(src0[1], BRW_REGISTER_TYPE_UW))); + retype(src0[1], BRW_REGISTER_TYPE_UW)); } } @@ -1272,7 +1272,7 @@ static void brw_wm_emit_glsl(struct brw_wm_compile *c) brw_push_insn_state(p); brw_set_mask_control(p, BRW_MASK_DISABLE); brw_set_access_mode(p, BRW_ALIGN_1); - brw_ADD(p, deref_1uw(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16)); + brw_ADD(p, deref_1ud(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16)); brw_set_access_mode(p, BRW_ALIGN_16); brw_ADD(p, get_addr_reg(stack_index), get_addr_reg(stack_index), brw_imm_d(4)); @@ -1288,7 +1288,7 @@ static void brw_wm_emit_glsl(struct brw_wm_compile *c) brw_ADD(p, get_addr_reg(stack_index), get_addr_reg(stack_index), brw_imm_d(-4)); brw_set_access_mode(p, BRW_ALIGN_1); - brw_MOV(p, brw_ip_reg(), deref_1uw(stack_index, 0)); + brw_MOV(p, brw_ip_reg(), deref_1ud(stack_index, 0)); brw_set_access_mode(p, BRW_ALIGN_16); brw_pop_insn_state(p); -- cgit v1.2.3 From ac985708f4820173bdc4509d032bdabeb93a0590 Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Mon, 8 Oct 2007 15:34:03 +0800 Subject: Only vertex program fix, bypass tnl vertex program --- src/mesa/drivers/dri/i965/brw_context.c | 2 +- src/mesa/main/texenvprogram.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 2031d556c1..9266e73570 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -79,7 +79,7 @@ static void brwUseProgram(GLcontext *ctx, GLuint program) brw->attribs.FragmentProgram->Current = sh_prog->FragmentProgram; ctx->FragmentProgram.Enabled = GL_TRUE; } else - ctx->VertexProgram.Enabled = GL_FALSE; + ctx->FragmentProgram.Enabled = GL_FALSE; } } diff --git a/src/mesa/main/texenvprogram.c b/src/mesa/main/texenvprogram.c index 72b54b27d9..126a9e1179 100644 --- a/src/mesa/main/texenvprogram.c +++ b/src/mesa/main/texenvprogram.c @@ -1239,7 +1239,7 @@ _mesa_UpdateTexEnvProgram( GLcontext *ctx ) /* If a conventional fragment program/shader isn't in effect... */ if (!ctx->FragmentProgram._Enabled && - !ctx->Shader.CurrentProgram) { + (!ctx->Shader.CurrentProgram || !ctx->Shader.CurrentProgram->FragmentProgram)) { make_state_key(ctx, &key); hash = hash_key(&key); -- cgit v1.2.3 From 82d4aa40551fe86a04346c3eea944f8ce7ae8d28 Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Tue, 9 Oct 2007 14:14:59 +0800 Subject: shadow sampler fix. 1. spec requite result (0, 0, 0, 1) instead of (0, 0, 0, 0) 2. support shadow sampler in simd8 --- src/mesa/drivers/dri/i965/brw_wm_emit.c | 2 ++ src/mesa/drivers/dri/i965/brw_wm_glsl.c | 12 +++++++++++- 2 files changed, 13 insertions(+), 1 deletion(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index 5660b55516..1f7158f7a7 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -702,6 +702,8 @@ static void emit_tex( struct brw_wm_compile *c, msgLength, 0); + if (shadow) + brw_MOV(p, dst[3], brw_imm_f(1.0)); } diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 58cdf72e37..8133c384f3 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -1027,8 +1027,10 @@ static void emit_tex(struct brw_wm_compile *c, GLuint msg_len; GLuint i, nr; GLuint emit; + GLboolean shadow = (c->key.shadowtex_mask & (1<TexSrcUnit)) ? 1 : 0; payload_reg = get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, 0, 1, 0, 0); + for (i = 0; i < 4; i++) dst[i] = get_dst_reg(c, inst, i, 1); for (i = 0; i < 4; i++) @@ -1061,6 +1063,11 @@ static void emit_tex(struct brw_wm_compile *c, msg_len += 1; } + if (shadow) { + brw_MOV(p, brw_message_reg(5), brw_imm_f(0)); + brw_MOV(p, brw_message_reg(6), src[2]); + } + brw_SAMPLE(p, retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW), 1, @@ -1070,8 +1077,11 @@ static void emit_tex(struct brw_wm_compile *c, inst->DstReg.WriteMask, BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE, 4, - 4, + shadow ? 6 : 4, 0); + + if (shadow) + brw_MOV(p, dst[3], brw_imm_f(1.0)); } static void post_wm_emit( struct brw_wm_compile *c ) -- cgit v1.2.3 From e2dff35f9589dd5616933654a2136584cb30ed18 Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Tue, 9 Oct 2007 14:26:01 +0800 Subject: INT support --- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 8133c384f3..8ed9284096 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -172,7 +172,7 @@ static void emit_abs( struct brw_wm_compile *c, brw_set_saturate(p, 0); } -static void emit_mov_int( struct brw_wm_compile *c, +static void emit_int( struct brw_wm_compile *c, struct prog_instruction *inst) { int i; @@ -184,7 +184,7 @@ static void emit_mov_int( struct brw_wm_compile *c, struct brw_reg src, dst; dst = retype(get_dst_reg(c, inst, i, 1), BRW_REGISTER_TYPE_D); src = retype(get_src_reg(c, &inst->SrcReg[0], i, 1), BRW_REGISTER_TYPE_D); - brw_MOV(p, dst, src); + brw_RNDD(p, dst, src); } } brw_set_saturate(p, 0); @@ -1181,7 +1181,7 @@ static void brw_wm_emit_glsl(struct brw_wm_compile *c) emit_lrp(c, inst); break; case OPCODE_INT: - emit_mov_int(c, inst); + emit_int(c, inst); break; case OPCODE_MOV: emit_mov(c, inst); -- cgit v1.2.3 From ae5aa1f90651a2a6168f687c95a069e78a0231bb Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Tue, 9 Oct 2007 14:35:28 +0800 Subject: fix for prev commit --- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 8ed9284096..4b273fefe9 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -182,8 +182,8 @@ static void emit_int( struct brw_wm_compile *c, for (i = 0; i < 4; i++) { if (mask & (1<SrcReg[0], i, 1), BRW_REGISTER_TYPE_D); + dst = get_dst_reg(c, inst, i, 1) ; + src = get_src_reg(c, &inst->SrcReg[0], i, 1); brw_RNDD(p, dst, src); } } -- cgit v1.2.3 From de803f538c16096c9e241cfdddc092ac2aa2504e Mon Sep 17 00:00:00 2001 From: Zou Nan hai Date: Tue, 9 Oct 2007 15:05:10 +0800 Subject: Non Square Matrix --- src/mesa/drivers/dri/i965/intel_context.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c index ac8aa5bd52..a5d8be8386 100644 --- a/src/mesa/drivers/dri/i965/intel_context.c +++ b/src/mesa/drivers/dri/i965/intel_context.c @@ -82,6 +82,7 @@ int INTEL_DEBUG = (0); #define need_GL_EXT_multi_draw_arrays #define need_GL_EXT_secondary_color #define need_GL_VERSION_2_0 +#define need_GL_VERSION_2_1 #define need_GL_ARB_shader_objects #define need_GL_ARB_vertex_shader @@ -188,6 +189,7 @@ const struct dri_extension card_extensions[] = { "GL_NV_blend_square", NULL }, { "GL_SGIS_generate_mipmap", NULL }, { "GL_ARB_shading_language_100", GL_VERSION_2_0_functions}, + { "GL_ARB_shading_language_120", GL_VERSION_2_1_functions}, { "GL_ARB_shader_objects", GL_ARB_shader_objects_functions}, { "GL_ARB_vertex_shader", GL_ARB_vertex_shader_functions}, { "GL_ARB_fragment_shader", NULL }, -- cgit v1.2.3