From 945d34e88ab7413299227fea56acc746010bb2e9 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 7 Aug 2009 18:09:31 -0700 Subject: intel: Align untiled region height to 2 according to 965 docs. This may or may not be required pre-965, but it doesn't seem unlikely, and I'd rather be safe. (cherry picked from commit b053474378633249be0e9f24010650ffb816229a) --- src/mesa/drivers/dri/intel/intel_regions.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c index 0aa5b8c02c..b8d2dec4cb 100644 --- a/src/mesa/drivers/dri/intel/intel_regions.c +++ b/src/mesa/drivers/dri/intel/intel_regions.c @@ -114,6 +114,13 @@ intel_region_alloc(struct intel_context *intel, { dri_bo *buffer; + /* If we're untiled, we have to align to 2 rows high because the + * data port accesses 2x2 blocks even if the bottom row isn't to be + * rendered, so failure to align means we could walk off the end of the + * GTT and fault. + */ + height = ALIGN(height, 2); + if (expect_accelerated_upload) { buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region", pitch * cpp * height, 64); -- cgit v1.2.3