From bb4f12f53875707a0d3c1eb254745b6250c42951 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 26 Oct 2010 14:49:38 -0700 Subject: i965: Disable register spilling on gen6 until it's fixed. Avoids GPU hang on glsl-fs-convolution-1. --- src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa') diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp index d7acc30fc4..bbb210cd44 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp @@ -225,7 +225,7 @@ fs_visitor::assign_regs() * loop back into here to try again. */ int reg = choose_spill_reg(g); - if (reg == -1) { + if (reg == -1 || intel->gen >= 6) { this->fail = true; } else { spill_reg(reg); -- cgit v1.2.3