From c26ec97b1390deb7c2ae586450e621a7095dac87 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Wed, 12 Nov 2008 17:00:28 +0100 Subject: r300: convert to new relocations format (see libdrm-radeon) --- src/mesa/drivers/dri/r300/Makefile | 2 +- src/mesa/drivers/dri/r300/r300_cmdbuf.c | 10 ++-- src/mesa/drivers/dri/r300/r300_cmdbuf.h | 10 +++- src/mesa/drivers/dri/r300/r300_ioctl.c | 4 +- src/mesa/drivers/dri/r300/r300_render.c | 60 +++++++++++++++-------- src/mesa/drivers/dri/r300/r300_swtcl.c | 2 +- src/mesa/drivers/dri/radeon/radeon_cs_legacy.c | 66 ++++++++++++++++++-------- 7 files changed, 105 insertions(+), 49 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index c041bc6ad0..d0616aaca6 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -80,7 +80,7 @@ COMMON_SYMLINKS = \ radeon_bo_legacy.h \ radeon_cs_legacy.h -DRI_LIB_DEPS += -ldrm_radeon +DRI_LIB_DEPS += -ldrm-radeon ##### TARGETS ##### diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 9552778f54..517860da43 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -297,12 +297,14 @@ static void emit_tex_offsets(r300ContextPtr r300, struct r300_state_atom * atom) OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1); r300TexObj *t = r300->hw.textures[i]; if (t && !t->image_override) { - OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, 0); + OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, + RADEON_GEM_DOMAIN_VRAM, 0, 0); } else if (!t) { OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]); } else { if (t->bo) { - OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, 0); + OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, + RADEON_GEM_DOMAIN_VRAM, 0, 0); } else { OUT_BATCH(t->override_offset); } @@ -339,7 +341,7 @@ static void emit_cb_offset(r300ContextPtr r300, struct r300_state_atom * atom) BEGIN_BATCH(4); OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1); - OUT_BATCH_RELOC(0, rrb->bo, 0, 0); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1); OUT_BATCH(cbpitch); END_BATCH(); @@ -365,7 +367,7 @@ static void emit_zb_offset(r300ContextPtr r300, struct r300_state_atom * atom) BEGIN_BATCH(4); OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1); - OUT_BATCH_RELOC(0, rrb->bo, 0, 0); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch); END_BATCH(); } diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h index b21619fd18..1a249c8d52 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h @@ -84,14 +84,20 @@ void r300BeginBatch(r300ContextPtr r300, /** * Write a relocated dword to the command buffer. */ -#define OUT_BATCH_RELOC(data, bo, offset, flags) \ +#define OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) \ do { \ if (offset) {\ fprintf(stderr, "(%s:%s:%d) offset : %d\n",\ __FILE__, __FUNCTION__, __LINE__, offset);\ }\ radeon_cs_write_dword(b_l_r300->cmdbuf.cs, offset);\ - radeon_cs_write_reloc(b_l_r300->cmdbuf.cs,bo,0,(bo)->size,flags);\ + radeon_cs_write_reloc(b_l_r300->cmdbuf.cs, \ + bo, \ + offset, \ + (bo)->size, \ + rd, \ + wd, \ + flags);\ } while(0) /** diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index a3353db520..5202248ab7 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -101,7 +101,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, assert(rrb != 0); BEGIN_BATCH_NO_AUTOSTATE(4); OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1); - OUT_BATCH_RELOC(0, rrb->bo, 0, 0); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGVAL(R300_RB3D_COLORPITCH0, cbpitch); END_BATCH(); } @@ -117,7 +117,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, } BEGIN_BATCH_NO_AUTOSTATE(4); OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1); - OUT_BATCH_RELOC(0, rrbd->bo, 0, 0); + OUT_BATCH_RELOC(0, rrbd->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, cbpitch); END_BATCH(); } diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c index f281e28e42..a8d42a2391 100644 --- a/src/mesa/drivers/dri/r300/r300_render.c +++ b/src/mesa/drivers/dri/r300/r300_render.c @@ -202,8 +202,10 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) { OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); OUT_BATCH(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2); - OUT_BATCH_RELOC(0, rmesa->state.elt_dma_bo, - rmesa->state.elt_dma_offset, 0); + OUT_BATCH_RELOC(rmesa->state.elt_dma_offset, + rmesa->state.elt_dma_bo, + rmesa->state.elt_dma_offset, + RADEON_GEM_DOMAIN_GTT, 0, 0); OUT_BATCH(vertex_count); } else { OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2); @@ -214,7 +216,7 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type) rmesa->state.elt_dma_bo, 0, rmesa->state.elt_dma_bo->size, - 0); + RADEON_GEM_DOMAIN_GTT, 0, 0); } END_BATCH(); } @@ -245,17 +247,30 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) voffset = rmesa->state.aos[i + 0].offset + offset * 4 * rmesa->state.aos[i + 0].stride; - OUT_BATCH_RELOC(0, rmesa->state.aos[i].bo, voffset, 0); + OUT_BATCH_RELOC(voffset, + rmesa->state.aos[i].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); voffset = rmesa->state.aos[i + 1].offset + offset * 4 * rmesa->state.aos[i + 1].stride; - OUT_BATCH_RELOC(0, rmesa->state.aos[i+1].bo, voffset, 0); + OUT_BATCH_RELOC(voffset, + rmesa->state.aos[i+1].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); } if (nr & 1) { OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) | (rmesa->state.aos[nr - 1].stride << 8)); - OUT_BATCH_RELOC(0, rmesa->state.aos[nr - 1].bo, - rmesa->state.aos[nr - 1].offset + offset * 4 * rmesa->state.aos[nr - 1].stride, 0); + voffset = rmesa->state.aos[nr - 1].offset + + offset * 4 * rmesa->state.aos[nr - 1].stride; + OUT_BATCH_RELOC(voffset, + rmesa->state.aos[nr - 1].bo, + voffset, + RADEON_GEM_DOMAIN_GTT, + 0, 0); } } else { for (i = 0; i + 1 < nr; i += 2) { @@ -275,32 +290,37 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset) if (nr & 1) { OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) | (rmesa->state.aos[nr - 1].stride << 8)); - OUT_BATCH(rmesa->state.aos[nr - 1].offset + offset * 4 * - rmesa->state.aos[nr - 1].stride); + voffset = rmesa->state.aos[nr - 1].offset + + offset * 4 * rmesa->state.aos[nr - 1].stride; + OUT_BATCH(voffset); } for (i = 0; i + 1 < nr; i += 2) { - #if 0 - fprintf(stderr, "3D_LOAD_VBPNTR 0x%08X & 0x%08X\n", - rmesa->state.aos[i+0].bo->handle, - rmesa->state.aos[i+1].bo->handle); - #endif + voffset = rmesa->state.aos[i + 0].offset + + offset * 4 * rmesa->state.aos[i + 0].stride; radeon_cs_write_reloc(rmesa->cmdbuf.cs, rmesa->state.aos[i+0].bo, - 0, + voffset, rmesa->state.aos[i+0].bo->size, - 0); + RADEON_GEM_DOMAIN_GTT, + 0, 0); + voffset = rmesa->state.aos[i + 1].offset + + offset * 4 * rmesa->state.aos[i + 1].stride; radeon_cs_write_reloc(rmesa->cmdbuf.cs, rmesa->state.aos[i+1].bo, - 0, + voffset, rmesa->state.aos[i+1].bo->size, - 0); + RADEON_GEM_DOMAIN_GTT, + 0, 0); } if (nr & 1) { + voffset = rmesa->state.aos[nr - 1].offset + + offset * 4 * rmesa->state.aos[nr - 1].stride; radeon_cs_write_reloc(rmesa->cmdbuf.cs, rmesa->state.aos[nr-1].bo, - 0, + voffset, rmesa->state.aos[nr-1].bo->size, - 0); + RADEON_GEM_DOMAIN_GTT, + 0, 0); } } END_BATCH(); diff --git a/src/mesa/drivers/dri/r300/r300_swtcl.c b/src/mesa/drivers/dri/r300/r300_swtcl.c index 43a2599dfe..fbfa8f452b 100644 --- a/src/mesa/drivers/dri/r300/r300_swtcl.c +++ b/src/mesa/drivers/dri/r300/r300_swtcl.c @@ -646,7 +646,7 @@ void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_b OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, 2); OUT_BATCH(1); OUT_BATCH(vertex_size | (vertex_size << 8)); - OUT_BATCH_RELOC(0, bo, offset, 0); + OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0); END_BATCH(); } diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c index ec3919ced6..b69537bc65 100644 --- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c +++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c @@ -94,19 +94,34 @@ static int cs_write_dword(struct radeon_cs *cs, uint32_t dword) static int cs_write_reloc(struct radeon_cs *cs, struct radeon_bo *bo, - uint32_t soffset, - uint32_t eoffset, - uint32_t domains) + uint32_t start_offset, + uint32_t end_offset, + uint32_t read_domain, + uint32_t write_domain, + uint32_t flags) { struct cs_reloc_legacy *relocs; int i; relocs = (struct cs_reloc_legacy *)cs->relocs; + /* check domains */ + if ((read_domain && write_domain) || (!read_domain && !write_domain)) { + /* in one CS a bo can only be in read or write domain but not + * in read & write domain at the same sime + */ + return -EINVAL; + } + if (read_domain == RADEON_GEM_DOMAIN_CPU) { + return -EINVAL; + } + if (write_domain == RADEON_GEM_DOMAIN_CPU) { + return -EINVAL; + } /* check reloc window */ - if (eoffset > bo->size) { + if (end_offset > bo->size) { return -EINVAL; } - if (soffset > eoffset) { + if (start_offset > end_offset) { return -EINVAL; } /* check if bo is already referenced */ @@ -114,16 +129,28 @@ static int cs_write_reloc(struct radeon_cs *cs, uint32_t *indices; if (relocs[i].base.bo->handle == bo->handle) { - /* update start offset and size */ - if (eoffset > relocs[i].base.eoffset) { - relocs[i].base.eoffset = eoffset; + /* update start and end offset */ + if (start_offset < relocs[i].base.start_offset) { + relocs[i].base.start_offset = start_offset; + } + if (end_offset > relocs[i].base.end_offset) { + relocs[i].base.end_offset = end_offset; } - if (soffset < relocs[i].base.soffset) { - relocs[i].base.soffset = soffset; + /* Check domains must be in read or write. As we check already + * checked that in argument one of the read or write domain was + * set we only need to check that if previous reloc as the read + * domain set then the read_domain should also be set for this + * new relocation. + */ + if (relocs[i].base.read_domain && !read_domain) { + return -EINVAL; + } + if (relocs[i].base.write_domain && !write_domain) { + return -EINVAL; } - relocs[i].base.size = relocs[i].base.eoffset - - relocs[i].base.soffset; - relocs[i].base.domains |= domains; + relocs[i].base.read_domain |= read_domain; + relocs[i].base.write_domain |= write_domain; + /* save indice */ relocs[i].cindices += 1; indices = (uint32_t*)realloc(relocs[i].indices, relocs[i].cindices * 4); @@ -145,10 +172,11 @@ static int cs_write_reloc(struct radeon_cs *cs, } cs->relocs = relocs; relocs[cs->crelocs].base.bo = bo; - relocs[cs->crelocs].base.soffset = soffset; - relocs[cs->crelocs].base.eoffset = eoffset; - relocs[cs->crelocs].base.size = eoffset - soffset; - relocs[cs->crelocs].base.domains = domains; + relocs[cs->crelocs].base.start_offset = start_offset; + relocs[cs->crelocs].base.end_offset = end_offset; + relocs[cs->crelocs].base.read_domain = read_domain; + relocs[cs->crelocs].base.write_domain = write_domain; + relocs[cs->crelocs].base.flags = flags; relocs[cs->crelocs].indices = (uint32_t*)malloc(4); if (relocs[cs->crelocs].indices == NULL) { return -ENOMEM; @@ -221,8 +249,8 @@ static int cs_process_relocs(struct radeon_cs *cs) for (j = 0; j < relocs[i].cindices; j++) { uint32_t soffset, eoffset; - soffset = relocs[i].base.soffset; - eoffset = relocs[i].base.eoffset; + soffset = relocs[i].base.start_offset; + eoffset = relocs[i].base.end_offset; r = radeon_bo_legacy_validate(relocs[i].base.bo, &soffset, &eoffset); if (r) { -- cgit v1.2.3