blob: 42607df9676e0e9ea539582437732085ca5ecdbc (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
|
#ifndef RADEON_CS_WRAPPER_H
#define RADEON_CS_WRAPPER_H
#ifndef RADEON_PARAM_DEVICE_ID
#define RADEON_PARAM_DEVICE_ID 17
#endif
#ifdef HAVE_LIBDRM_RADEON
#include "radeon_bo.h"
#include "radeon_bo_gem.h"
#include "radeon_cs.h"
#include "radeon_cs_gem.h"
#else
#include <stdint.h>
#define RADEON_GEM_DOMAIN_CPU 0x1 // Cached CPU domain
#define RADEON_GEM_DOMAIN_GTT 0x2 // GTT or cache flushed
#define RADEON_GEM_DOMAIN_VRAM 0x4 // VRAM domain
/* to be used to build locally in mesa with no libdrm bits */
#include "../radeon/radeon_bo_drm.h"
#include "../radeon/radeon_cs_drm.h"
#ifndef DRM_RADEON_GEM_INFO
#define DRM_RADEON_GEM_INFO 0x1c
struct drm_radeon_gem_info {
uint64_t gart_start;
uint64_t gart_size;
uint64_t vram_start;
uint64_t vram_size;
uint64_t vram_visible;
};
#endif
uint32_t radeon_gem_bo_name(struct radeon_bo *dummy)
{
return 0;
}
static inline void *radeon_bo_manager_gem_ctor(int fd)
{
return NULL;
}
static inline void radeon_bo_manager_gem_dtor(void *dummy)
{
}
static inline void *radeon_cs_manager_gem_ctor(int fd)
{
return NULL;
}
static inline void radeon_cs_manager_gem_dtor(void *dummy)
{
}
static inline void radeon_tracker_print(void *ptr, int io)
{
}
#endif
#include "radeon_bo_legacy.h"
#include "radeon_cs_legacy.h"
#endif
|
