separate u-boot for at91 arm and everything else

3 files changed, 3397 insertions, 0 deletions

diff --git a/target/u-boot/Config.in b/target/u-boot/Config.in
new file mode 100644
index 000000000..66ebaf50a
--- /dev/null
+++ b/target/u-boot/Config.in
@@ -0,0 +1,72 @@
+config BR2_TARGET_UBOOT
+	bool "Das U-Boot Boot Monitor"
+	depends on !BR2_TARGET_AT91
+	default n
+	help
+	  Build "Das U-Boot" Boot Monitor
+
+config BR2_TARGET_UBOOT_BOARDNAME
+	string "board name"
+	depends on BR2_TARGET_UBOOT
+	default "$(BOARD_NAME)"
+	help
+	  One of U-Boot supported boards to be built.
+	  This will be suffixed with _config to meet U-Boot standard naming.
+
+config BR2_TARGET_UBOOT_CUSTOM_PATCH
+	string "custom patch"
+	depends on BR2_TARGET_UBOOT
+	help
+	  If your board requires a custom patch, add the path to the file here.
+	  Most users may leave this empty
+
+config BR2_TARGET_UBOOT_SERVERIP
+	string "server ip"
+	depends on BR2_TARGET_UBOOT
+	default "10.175.196.221"
+	help
+	  TFTP server ip address
+
+config BR2_TARGET_UBOOT_IPADDR
+	string "ip address"
+	depends on BR2_TARGET_UBOOT
+	default "10.175.196.18"
+	help
+	  Target ip address
+
+config BR2_TARGET_UBOOT_GATEWAY
+	string "gateway ip"
+	depends on BR2_TARGET_UBOOT
+	default "10.175.196.1"
+	help
+	  Gateway ip address
+
+config BR2_TARGET_UBOOT_NETMASK
+	string "netmask"
+	depends on BR2_TARGET_UBOOT
+	default "255.255.255.0"
+	help
+	  Network Mask
+
+config BR2_TARGET_UBOOT_ETHADDR
+	string "ethernet address"
+	depends on BR2_TARGET_UBOOT
+	default "04:25:fe:ed:00:18"
+	help
+	  Target MAC address for the ethernet interface.
+	  This should be changed for production units
+
+config BR2_TARGET_UBOOT_ETH1ADDR
+	string "ethernet 2 address"
+	depends on BR2_TARGET_UBOOT
+	depends on BR2_TARGET_AVR32
+	help
+	  Target MAC address for the second ethernet interface.
+
+config BR2_TARGET_UBOOT_SILENT
+	bool "silent console"
+	depends on BR2_TARGET_UBOOT
+	default n
+	help
+	  If the option has been enabled, the output can be
+	  silenced by setting the environment variable "silent".
diff --git a/target/u-boot/Makefile.in b/target/u-boot/Makefile.in
new file mode 100644
index 000000000..8ae084bdf
--- /dev/null
+++ b/target/u-boot/Makefile.in
@@ -0,0 +1,148 @@
+#############################################################
+#
+# U-Boot
+#
+#############################################################
+U_BOOT_VERSION:=1.3.0
+U_BOOT_SOURCE:=u-boot-$(U_BOOT_VERSION).tar.bz2
+U_BOOT_SITE:=ftp://ftp.denx.de/pub/u-boot
+U_BOOT_DIR:=$(PROJECT_BUILD_DIR)/u-boot-$(U_BOOT_VERSION)
+U_BOOT_PATCH_DIR:=$(PROJECT_BUILD_DIR)/u-boot-patches
+U_BOOT_CAT:=$(BZCAT)
+U_BOOT_BIN:=u-boot.bin
+U_BOOT_TOOLS_BIN:=mkimage
+
+ifneq ($(BR2_TARGET_U_BOOT_CONFIG_BOARD),)
+U_BOOT_INC_CONF_FILE:=$(U_BOOT_DIR)/include/configs/$(subst _config,,$(BR2_TARGET_U_BOOT_CONFIG_BOARD)).h
+else
+U_BOOT_INC_CONF_FILE:=$(U_BOOT_DIR)/include/config.h
+endif
+
+# Define a helper function
+define insert_define
+@echo "#ifdef $(strip $(1))" >> $(U_BOOT_INC_CONF_FILE)
+@echo "#undef $(strip $(1))" >> $(U_BOOT_INC_CONF_FILE)
+@echo "#endif" >> $(U_BOOT_INC_CONF_FILE)
+@echo "#define $(strip $(1)) $(2)" >> $(U_BOOT_INC_CONF_FILE)
+endef
+	
+$(DL_DIR)/$(U_BOOT_SOURCE):
+	 $(WGET) -P $(DL_DIR) $(U_BOOT_SITE)/$(U_BOOT_SOURCE)
+
+$(U_BOOT_DIR)/.unpacked: $(DL_DIR)/$(U_BOOT_SOURCE)
+	$(U_BOOT_CAT) $(DL_DIR)/$(U_BOOT_SOURCE) \
+		| tar -C $(PROJECT_BUILD_DIR) $(TAR_OPTIONS) -
+	touch $@
+
+$(U_BOOT_DIR)/.patched: $(U_BOOT_DIR)/.unpacked
+	toolchain/patch-kernel.sh $(U_BOOT_DIR) target/u-boot/ \
+		u-boot-$(U_BOOT_VERSION)-$(BR2_ARCH)-\*.patch\*
+ifneq ($(strip $(BR2_TARGET_UBOOT_CUSTOM_PATCH)),"")
+	@mkdir -p $(U_BOOT_PATCH_DIR)
+	cp -dpr $(BR2_TARGET_UBOOT_CUSTOM_PATCH) $(U_BOOT_PATCH_DIR)
+	toolchain/patch-kernel.sh $(U_BOOT_DIR) $(U_BOOT_PATCH_DIR) *.patch
+endif
+	touch $@
+
+$(U_BOOT_DIR)/.header_copied: $(U_BOOT_DIR)/.patched
+ifneq ($(strip $(BR2_TARGET_U_BOOT_CONFIG_HEADER_FILE)),)
+	cp -dpf $(BR2_TARGET_U_BOOT_CONFIG_HEADER_FILE) $(U_BOOT_INC_CONF_FILE)
+endif
+	touch $@
+
+$(U_BOOT_DIR)/.configured: $(U_BOOT_DIR)/.header_copied
+	$(TARGET_CONFIGURE_OPTS)		\
+		CFLAGS="$(TARGET_CFLAGS)"	\
+		LDFLAGS="$(TARGET_LDFLAGS)"	\
+		$(MAKE) -C $(U_BOOT_DIR)	\
+		$(BR2_TARGET_UBOOT_BOARDNAME)_config
+	touch $@
+
+$(U_BOOT_DIR)/.header_modified: $(U_BOOT_DIR)/.configured
+	# Modify configuration header in $(U_BOOT_INC_CONF_FILE)
+	
+	@echo >> $(U_BOOT_INC_CONF_FILE)
+	@echo "/* Add a wrapper around the values Buildroot sets. */" >> $(U_BOOT_INC_CONF_FILE)
+	@echo "#ifndef __BR2_ADDED_CONFIG_H" >> $(U_BOOT_INC_CONF_FILE)
+	@echo "#define __BR2_ADDED_CONFIG_H" >> $(U_BOOT_INC_CONF_FILE)
+ifneq ($(strip $(BR2_PROJECT)),"")
+	$(call insert_define, "CONFIG_HOSTNAME", $(BR2_PROJECT))
+endif
+ifneq ($(strip $(BR2_TARGET_UBOOT_SERVERIP)),"")
+	$(call insert_define, "CONFIG_SERVERIP", $(BR2_TARGET_UBOOT_SERVERIP))
+endif
+
+ifneq ($(strip $(BR2_TARGET_UBOOT_IPADDR)),"")
+	$(call insert_define, "CONFIG_IPADDR", $(BR2_TARGET_UBOOT_IPADDR))
+ifneq ($(strip $(BR2_TARGET_UBOOT_GATEWAY)),"")
+	$(call insert_define, "CONFIG_GATEWAYIP", $(BR2_TARGET_UBOOT_GATEWAY))
+endif
+ifneq ($(strip $(BR2_TARGET_UBOOT_NETMASK)),"")
+	$(call insert_define, "CONFIG_NETMASK", $(BR2_TARGET_UBOOT_NETMASK))
+endif
+endif # end BR2_TARGET_U_BOOT_IPADDR
+
+ifneq ($(strip $(BR2_TARGET_UBOOT_ETHADDR)),"")
+	$(call insert_define, "CONFIG_ETHADDR", $(BR2_TARGET_UBOOT_ETHADDR))
+endif
+ifneq ($(strip $(BR2_TARGET_UBOOT_ETH1ADDR)),"")
+	$(call insert_define "CONFIG_ETH2ADDR", $(BR2_TARGET_UBOOT_ETH1ADDR))
+endif
+ifneq ($(strip $(BR2_TARGET_UBOOT_BOOTARGS)),"")
+	$(call insert_define "CONFIG_BOOTARGS", $(BR2_TARGET_UBOOT_BOOTARGS))
+endif
+ifneq ($(strip $(BR2_TARGET_UBOOT_BOOTCMD)),"")
+	$(call insert_define "CONFIG_BOOTCOMMAND", $(BR2_TARGET_UBOOT_BOOTCMD))
+endif
+ifneq ($(strip $(BR2_TARGET_UBOOT_SILENT)),"")
+	$(call insert_define "CONFIG_SILENT_CONSOLE", "")
+endif
+	@echo "#endif /* __BR2_ADDED_CONFIG_H */" >> $(U_BOOT_INC_CONF_FILE)
+	touch $@
+
+$(U_BOOT_DIR)/$(U_BOOT_BIN): $(U_BOOT_DIR)/.header_modified
+	$(TARGET_CONFIGURE_OPTS) \
+		CFLAGS="$(TARGET_CFLAGS)" \
+		LDFLAGS="$(TARGET_LDFLAGS)" \
+		$(MAKE) -C $(U_BOOT_DIR)
+
+$(BINARIES_DIR)/$(U_BOOT_BIN): $(U_BOOT_DIR)/$(U_BOOT_BIN)
+	cp -dpf $(U_BOOT_DIR)/$(U_BOOT_BIN) $(BINARIES_DIR)
+	cp -dpf $(U_BOOT_DIR)/tools/$(U_BOOT_TOOLS_BIN) $(STAGING_DIR)/usr/bin/
+
+u-boot: gcc $(BINARIES_DIR)/$(U_BOOT_BIN)
+
+u-boot-clean:
+	$(MAKE) -C $(U_BOOT_DIR) clean
+
+u-boot-dirclean:
+	rm -rf $(U_BOOT_DIR)
+
+u-boot-source: $(DL_DIR)/$(U_BOOT_SOURCE)
+
+#############################################################
+#
+# Toplevel Makefile options
+#
+#############################################################
+ifeq ($(strip $(BR2_TARGET_UBOOT)),y)
+TARGETS+=u-boot
+endif
+
+u-boot-status:
+	@echo
+	@echo U_BOOT_INC_CONF_FILE = $(U_BOOT_INC_CONF_FILE)
+	@echo
+	@echo BR2_TARGET_U_BOOT_CONFIG_HEADER_FILE = $(BR2_TARGET_U_BOOT_CONFIG_HEADER_FILE)
+	@echo BR2_TARGET_U_BOOT_CONFIG_BOARD = $(BR2_TARGET_U_BOOT_CONFIG_BOARD)
+	@echo BR2_TARGET_UBOOT_SERVERIP = $(BR2_TARGET_UBOOT_SERVERIP)
+	@echo BR2_TARGET_UBOOT_IPADDR = $(BR2_TARGET_UBOOT_IPADDR)
+	@echo BR2_TARGET_UBOOT_GATEWAY = $(BR2_TARGET_UBOOT_GATEWAY)
+	@echo BR2_TARGET_UBOOT_NETMASK = $(BR2_TARGET_UBOOT_NETMASK)
+	@echo BR2_TARGET_UBOOT_ETH0ADDR = $(BR2_TARGET_UBOOT_ETHADDR)
+	@echo BR2_TARGET_UBOOT_ETH1ADDR = $(BR2_TARGET_UBOOT_ETH1ADDR)
+	@echo BR2_TARGET_UBOOT_BOOTARGS = $(BR2_TARGET_UBOOT_BOOTARGS)
+	@echo BR2_TARGET_UBOOT_BOOTCMD = $(BR2_TARGET_UBOOT_BOOTCMD)
+	@echo BR2_TARGET_UBOOT_SILENT = $(BR2_TARGET_UBOOT_SILENT)
+	@echo
+	@exit 0
diff --git a/target/u-boot/u-boot-1.3.0-avr32-100-atmel.2.patch b/target/u-boot/u-boot-1.3.0-avr32-100-atmel.2.patch
new file mode 100644
index 000000000..a6d484b2d
--- /dev/null
+++ b/target/u-boot/u-boot-1.3.0-avr32-100-atmel.2.patch
@@ -0,0 +1,3177 @@
+ MAINTAINERS                                       |    6 +-
+ MAKEALL                                           |    3 +
+ Makefile                                          |   13 +-
+ README                                            |    4 +-
+ board/atmel/atngw100/Makefile                     |   40 ++++
+ board/atmel/atngw100/atngw100.c                   |   73 +++++++
+ board/atmel/atngw100/config.mk                    |    3 +
+ board/atmel/atngw100/eth.c                        |   36 ++++
+ board/atmel/atngw100/flash.c                      |  232 +++++++++++++++++++++
+ board/atmel/atngw100/u-boot.lds                   |   80 +++++++
+ cpu/at32ap/at32ap7000/Makefile                    |   43 ----
+ cpu/at32ap/at32ap7000/gpio.c                      |  137 ------------
+ cpu/at32ap/at32ap700x/Makefile                    |   43 ++++
+ cpu/at32ap/at32ap700x/gpio.c                      |  144 +++++++++++++
+ cpu/at32ap/atmel_mci.c                            |   13 +-
+ include/asm-avr32/arch-at32ap7000/clk.h           |   70 ------
+ include/asm-avr32/arch-at32ap7000/gpio.h          |  212 -------------------
+ include/asm-avr32/arch-at32ap7000/hmatrix2.h      |  232 ---------------------
+ include/asm-avr32/arch-at32ap7000/memory-map.h    |   66 ------
+ include/asm-avr32/arch-at32ap7000/mmc.h           |   96 ---------
+ include/asm-avr32/arch-at32ap700x/chip-features.h |   34 +++
+ include/asm-avr32/arch-at32ap700x/clk.h           |   78 +++++++
+ include/asm-avr32/arch-at32ap700x/gpio.h          |  220 +++++++++++++++++++
+ include/asm-avr32/arch-at32ap700x/hmatrix2.h      |  232 +++++++++++++++++++++
+ include/asm-avr32/arch-at32ap700x/memory-map.h    |   66 ++++++
+ include/asm-avr32/arch-at32ap700x/mmc.h           |   96 +++++++++
+ include/configs/atngw100.h                        |  177 ++++++++++++++++
+ include/configs/atstk1002.h                       |    4 +-
+ include/configs/atstk1003.h                       |  184 ++++++++++++++++
+ include/configs/atstk1004.h                       |  185 ++++++++++++++++
+ lib_avr32/board.c                                 |   10 +
+ net/eth.c                                         |    4 +
+ 32 files changed, 1966 insertions(+), 870 deletions(-)
+ create mode 100644 board/atmel/atngw100/Makefile
+ create mode 100644 board/atmel/atngw100/atngw100.c
+ create mode 100644 board/atmel/atngw100/config.mk
+ create mode 100644 board/atmel/atngw100/eth.c
+ create mode 100644 board/atmel/atngw100/flash.c
+ create mode 100644 board/atmel/atngw100/u-boot.lds
+ delete mode 100644 cpu/at32ap/at32ap7000/Makefile
+ delete mode 100644 cpu/at32ap/at32ap7000/gpio.c
+ create mode 100644 cpu/at32ap/at32ap700x/Makefile
+ create mode 100644 cpu/at32ap/at32ap700x/gpio.c
+ delete mode 100644 include/asm-avr32/arch-at32ap7000/clk.h
+ delete mode 100644 include/asm-avr32/arch-at32ap7000/gpio.h
+ delete mode 100644 include/asm-avr32/arch-at32ap7000/hmatrix2.h
+ delete mode 100644 include/asm-avr32/arch-at32ap7000/memory-map.h
+ delete mode 100644 include/asm-avr32/arch-at32ap7000/mmc.h
+ create mode 100644 include/asm-avr32/arch-at32ap700x/chip-features.h
+ create mode 100644 include/asm-avr32/arch-at32ap700x/clk.h
+ create mode 100644 include/asm-avr32/arch-at32ap700x/gpio.h
+ create mode 100644 include/asm-avr32/arch-at32ap700x/hmatrix2.h
+ create mode 100644 include/asm-avr32/arch-at32ap700x/memory-map.h
+ create mode 100644 include/asm-avr32/arch-at32ap700x/mmc.h
+ create mode 100644 include/configs/atngw100.h
+ create mode 100644 include/configs/atstk1003.h
+ create mode 100644 include/configs/atstk1004.h
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index b8c1fdc..457dce3 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -630,7 +630,11 @@ Hayden Fraser <Hayden.Fraser@freescale.com>
+ 
+ Haavard Skinnemoen <hskinnemoen@atmel.com>
+ 
+-	ATSTK1000		AT32AP7000
++	ATSTK1000		AT32AP7xxx
++	ATSTK1002		AT32AP7000
++	ATSTK1003		AT32AP7001
++	ATSTK1004		AT32AP7002
++	ATNGW100		AT32AP7000
+ 
+ #########################################################################
+ # End of MAINTAINERS list						#
+diff --git a/MAKEALL b/MAKEALL
+index 20ef4e1..1538478 100755
+--- a/MAKEALL
++++ b/MAKEALL
+@@ -641,6 +641,9 @@ LIST_coldfire="			\
+ 
+ LIST_avr32="		\
+ 	atstk1002	\
++	atstk1003	\
++	atstk1004	\
++	atngw100	\
+ "
+ 
+ #########################################################################
+diff --git a/Makefile b/Makefile
+index ac4b430..2db97fd 100644
+--- a/Makefile
++++ b/Makefile
+@@ -24,7 +24,7 @@
+ VERSION = 1
+ PATCHLEVEL = 3
+ SUBLEVEL = 0
+-EXTRAVERSION =
++EXTRAVERSION = .atmel.2
+ U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
+ VERSION_FILE = $(obj)include/version_autogenerated.h
+ 
+@@ -2607,7 +2607,16 @@ bf561-ezkit_config:	unconfig
+ #########################################################################
+ 
+ atstk1002_config	:	unconfig
+-	@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap7000
++	@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
++
++atstk1003_config	:	unconfig
++	@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
++
++atstk1004_config	:	unconfig
++	@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
++
++atngw100_config	:	unconfig
++	@$(MKCONFIG) $(@:_config=) avr32 at32ap atngw100 atmel at32ap700x
+ 
+ #########################################################################
+ #########################################################################
+diff --git a/README b/README
+index 3dad5fc..26f93c2 100644
+--- a/README
++++ b/README
+@@ -235,9 +235,7 @@ The following options need to be configured:
+ - Board Type:	Define exactly one, e.g. CONFIG_MPC8540ADS.
+ 
+ - CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
+-		Define exactly one of
+-		CONFIG_ATSTK1002
+-
++		Define exactly one, e.g. CONFIG_ATSTK1002
+ 
+ - CPU Module Type: (if CONFIG_COGENT is defined)
+ 		Define exactly one of
+diff --git a/board/atmel/atngw100/Makefile b/board/atmel/atngw100/Makefile
+new file mode 100644
+index 0000000..f1ea6e6
+--- /dev/null
++++ b/board/atmel/atngw100/Makefile
+@@ -0,0 +1,40 @@
++#
++# Copyright (C) 2005-2006 Atmel Corporation
++#
++# See file CREDITS for list of people who contributed to this project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++
++include $(TOPDIR)/config.mk
++
++LIB	:= $(obj)lib$(BOARD).a
++
++COBJS	:= $(BOARD).o flash.o eth.o
++
++SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
++
++$(LIB): $(obj).depend $(OBJS)
++	$(AR) $(ARFLAGS) $@ $(OBJS)
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/board/atmel/atngw100/atngw100.c b/board/atmel/atngw100/atngw100.c
+new file mode 100644
+index 0000000..bd4b6b4
+--- /dev/null
++++ b/board/atmel/atngw100/atngw100.c
+@@ -0,0 +1,73 @@
++/*
++ * Copyright (C) 2006 Atmel Corporation
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#include <common.h>
++
++#include <asm/io.h>
++#include <asm/sdram.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/hmatrix2.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++static const struct sdram_info sdram = {
++	.phys_addr	= CFG_SDRAM_BASE,
++	.row_bits	= 13,
++	.col_bits	= 9,
++	.bank_bits	= 2,
++	.cas		= 3,
++	.twr		= 2,
++	.trc		= 7,
++	.trp		= 2,
++	.trcd		= 2,
++	.tras		= 5,
++	.txsr		= 5,
++};
++
++int board_early_init_f(void)
++{
++	/* Set the SDRAM_ENABLE bit in the HEBI SFR */
++	hmatrix2_writel(SFR4, 1 << 1);
++
++	gpio_enable_ebi();
++	gpio_enable_usart1();
++
++#if defined(CONFIG_MACB)
++	gpio_enable_macb0();
++	gpio_enable_macb1();
++#endif
++#if defined(CONFIG_MMC)
++	gpio_enable_mmci();
++#endif
++
++	return 0;
++}
++
++long int initdram(int board_type)
++{
++	return sdram_init(&sdram);
++}
++
++void board_init_info(void)
++{
++	gd->bd->bi_phy_id[0] = 0x01;
++	gd->bd->bi_phy_id[1] = 0x03;
++}
+diff --git a/board/atmel/atngw100/config.mk b/board/atmel/atngw100/config.mk
+new file mode 100644
+index 0000000..9a794e5
+--- /dev/null
++++ b/board/atmel/atngw100/config.mk
+@@ -0,0 +1,3 @@
++TEXT_BASE		= 0x00000000
++PLATFORM_RELFLAGS	+= -ffunction-sections -fdata-sections
++PLATFORM_LDFLAGS	+= --gc-sections
+diff --git a/board/atmel/atngw100/eth.c b/board/atmel/atngw100/eth.c
+new file mode 100644
+index 0000000..d1d57bb
+--- /dev/null
++++ b/board/atmel/atngw100/eth.c
+@@ -0,0 +1,36 @@
++/*
++ * Copyright (C) 2006 Atmel Corporation
++ *
++ * Ethernet initialization for the AVR32 Network Gateway
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#include <common.h>
++
++#include <asm/arch/memory-map.h>
++
++extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
++
++#ifdef CONFIG_CMD_NET
++void atngw100_eth_initialize(bd_t *bi)
++{
++	macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
++	macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]);
++}
++#endif
+diff --git a/board/atmel/atngw100/flash.c b/board/atmel/atngw100/flash.c
+new file mode 100644
+index 0000000..2d9423f
+--- /dev/null
++++ b/board/atmel/atngw100/flash.c
+@@ -0,0 +1,232 @@
++/*
++ * Copyright (C) 2006 Atmel Corporation
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#include <common.h>
++
++#ifdef CONFIG_ATNGW100_EXT_FLASH
++#include <asm/cacheflush.h>
++#include <asm/io.h>
++#include <asm/sections.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++flash_info_t flash_info[1];
++
++static void __flashprog flash_identify(uint16_t *flash, flash_info_t *info)
++{
++	unsigned long flags;
++
++	flags = disable_interrupts();
++
++	dcache_flush_unlocked();
++
++	writew(0xaa, flash + 0x555);
++	writew(0x55, flash + 0xaaa);
++	writew(0x90, flash + 0x555);
++	info->flash_id = readl(flash);
++	writew(0xff, flash);
++
++	readw(flash);
++
++	if (flags)
++		enable_interrupts();
++}
++
++unsigned long flash_init(void)
++{
++	unsigned long addr;
++	unsigned int i;
++
++	flash_info[0].size = CFG_FLASH_SIZE;
++	flash_info[0].sector_count = 135;
++
++	flash_identify(uncached((void *)CFG_FLASH_BASE), &flash_info[0]);
++
++	for (i = 0, addr = 0; i < 8; i++, addr += 0x2000)
++		flash_info[0].start[i] = addr;
++	for (; i < flash_info[0].sector_count; i++, addr += 0x10000)
++		flash_info[0].start[i] = addr;
++
++	return CFG_FLASH_SIZE;
++}
++
++void flash_print_info(flash_info_t *info)
++{
++	printf("Flash: Vendor ID: 0x%02x, Product ID: 0x%02x\n",
++	       info->flash_id >> 16, info->flash_id & 0xffff);
++	printf("Size: %ld MB in %d sectors\n",
++	       info->size >> 10, info->sector_count);
++}
++
++int __flashprog flash_erase(flash_info_t *info, int s_first, int s_last)
++{
++	unsigned long flags;
++	unsigned long start_time;
++	uint16_t *fb, *sb;
++	unsigned int i;
++	int ret;
++	uint16_t status;
++
++	if ((s_first < 0) || (s_first > s_last)
++	    || (s_last >= info->sector_count)) {
++		puts("Error: first and/or last sector out of range\n");
++		return ERR_INVAL;
++	}
++
++	for (i = s_first; i < s_last; i++)
++		if (info->protect[i]) {
++			printf("Error: sector %d is protected\n", i);
++			return ERR_PROTECTED;
++		}
++
++	fb = (uint16_t *)uncached(info->start[0]);
++
++	dcache_flush_unlocked();
++
++	for (i = s_first; (i <= s_last) && !ctrlc(); i++) {
++		printf("Erasing sector %3d...", i);
++
++		sb = (uint16_t *)uncached(info->start[i]);
++
++		flags = disable_interrupts();
++
++		start_time = get_timer(0);
++
++		/* Unlock sector */
++		writew(0xaa, fb + 0x555);
++		writew(0x70, sb);
++
++		/* Erase sector */
++		writew(0xaa, fb + 0x555);
++		writew(0x55, fb + 0xaaa);
++		writew(0x80, fb + 0x555);
++		writew(0xaa, fb + 0x555);
++		writew(0x55, fb + 0xaaa);
++		writew(0x30, sb);
++
++		/* Wait for completion */
++		ret = ERR_OK;
++		do {
++			/* TODO: Timeout */
++			status = readw(sb);
++		} while ((status != 0xffff) && !(status & 0x28));
++
++		writew(0xf0, fb);
++
++		/*
++		 * Make sure the command actually makes it to the bus
++		 * before we re-enable interrupts.
++		 */
++		readw(fb);
++
++		if (flags)
++			enable_interrupts();
++
++		if (status != 0xffff) {
++			printf("Flash erase error at address 0x%p: 0x%02x\n",
++			       sb, status);
++			ret = ERR_PROG_ERROR;
++			break;
++		}
++	}
++
++	if (ctrlc())
++		printf("User interrupt!\n");
++
++	return ERR_OK;
++}
++
++int __flashprog write_buff(flash_info_t *info, uchar *src,
++			   ulong addr, ulong count)
++{
++	unsigned long flags;
++	uint16_t *base, *p, *s, *end;
++	uint16_t word, status, status1;
++	int ret = ERR_OK;
++
++	if (addr < info->start[0]
++	    || (addr + count) > (info->start[0] + info->size)
++	    || (addr + count) < addr) {
++		puts("Error: invalid address range\n");
++		return ERR_INVAL;
++	}
++
++	if (addr & 1 || count & 1 || (unsigned int)src & 1) {
++		puts("Error: misaligned source, destination or count\n");
++		return ERR_ALIGN;
++	}
++
++	base = (uint16_t *)uncached(info->start[0]);
++	end = (uint16_t *)uncached(addr + count);
++
++	flags = disable_interrupts();
++
++	dcache_flush_unlocked();
++	sync_write_buffer();
++
++	for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src;
++	     p < end && !ctrlc(); p++, s++) {
++		word = *s;
++
++		writew(0xaa, base + 0x555);
++		writew(0x55, base + 0xaaa);
++		writew(0xa0, base + 0x555);
++		writew(word, p);
++
++		sync_write_buffer();
++
++		/* Wait for completion */
++		status1 = readw(p);
++		do {
++			/* TODO: Timeout */
++			status = status1;
++			status1 = readw(p);
++		} while (((status ^ status1) & 0x40)	/* toggled */
++			 && !(status1 & 0x28));		/* error bits */
++
++		/*
++		 * We'll need to check once again for toggle bit
++		 * because the toggle bit may stop toggling as I/O5
++		 * changes to "1" (ref at49bv642.pdf p9)
++		 */
++		status1 = readw(p);
++		status = readw(p);
++		if ((status ^ status1) & 0x40) {
++			printf("Flash write error at address 0x%p: "
++			       "0x%02x != 0x%02x\n",
++			       p, status,word);
++			ret = ERR_PROG_ERROR;
++			writew(0xf0, base);
++			readw(base);
++			break;
++		}
++
++		writew(0xf0, base);
++		readw(base);
++	}
++
++	if (flags)
++		enable_interrupts();
++
++	return ret;
++}
++
++#endif /* CONFIG_ATSTK1000_EXT_FLASH */
+diff --git a/board/atmel/atngw100/u-boot.lds b/board/atmel/atngw100/u-boot.lds
+new file mode 100644
+index 0000000..34e347a
+--- /dev/null
++++ b/board/atmel/atngw100/u-boot.lds
+@@ -0,0 +1,80 @@
++/* -*- Fundamental -*-
++ *
++ * Copyright (C) 2005-2006 Atmel Corporation
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
++OUTPUT_ARCH(avr32)
++ENTRY(_start)
++
++SECTIONS
++{
++	. = 0;
++	_text = .;
++	.text : {
++		*(.text)
++		*(.text.*)
++	}
++
++	. = ALIGN(32);
++	__flashprog_start = .;
++	.flashprog : {
++		*(.flashprog)
++	}
++	. = ALIGN(32);
++	__flashprog_end = .;
++	_etext = .;
++
++	.rodata : {
++		*(.rodata)
++		*(.rodata.*)
++	}
++
++	. = ALIGN(8);
++	_data = .;
++	.data : {
++		*(.data)
++		*(.data.*)
++	}
++
++	. = ALIGN(4);
++	__u_boot_cmd_start = .;
++	.u_boot_cmd : {
++		KEEP(*(.u_boot_cmd))
++	}
++	__u_boot_cmd_end = .;
++
++	. = ALIGN(4);
++	_got = .;
++	.got : {
++		*(.got)
++	}
++	_egot = .;
++
++	. = ALIGN(8);
++	_edata = .;
++
++	.bss : {
++		*(.bss)
++		*(.bss.*)
++	}
++	. = ALIGN(8);
++	_end = .;
++}
+diff --git a/cpu/at32ap/at32ap7000/Makefile b/cpu/at32ap/at32ap7000/Makefile
+deleted file mode 100644
+index d276712..0000000
+--- a/cpu/at32ap/at32ap7000/Makefile
++++ /dev/null
+@@ -1,43 +0,0 @@
+-#
+-# Copyright (C) 2005-2006 Atmel Corporation
+-#
+-# See file CREDITS for list of people who contributed to this
+-# project.
+-#
+-# This program is free software; you can redistribute it and/or
+-# modify it under the terms of the GNU General Public License as
+-# published by the Free Software Foundation; either version 2 of
+-# the License, or (at your option) any later version.
+-#
+-# This program is distributed in the hope that it will be useful,
+-# but WITHOUT ANY WARRANTY; without even the implied warranty of
+-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-# GNU General Public License for more details.
+-#
+-# You should have received a copy of the GNU General Public License
+-# along with this program; if not, write to the Free Software
+-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+-# MA 02111-1307 USA
+-#
+-
+-include $(TOPDIR)/config.mk
+-
+-LIB	:= $(obj)lib$(SOC).a
+-
+-COBJS	:= gpio.o
+-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+-
+-all: $(obj).depend $(LIB)
+-
+-$(LIB): $(OBJS)
+-	$(AR) $(ARFLAGS) $@ $^
+-
+-#########################################################################
+-
+-# defines $(obj).depend target
+-include $(SRCTREE)/rules.mk
+-
+-sinclude $(obj).depend
+-
+-#########################################################################
+diff --git a/cpu/at32ap/at32ap7000/gpio.c b/cpu/at32ap/at32ap7000/gpio.c
+deleted file mode 100644
+index 52f5372..0000000
+--- a/cpu/at32ap/at32ap7000/gpio.c
++++ /dev/null
+@@ -1,137 +0,0 @@
+-/*
+- * Copyright (C) 2006 Atmel Corporation
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-#include <common.h>
+-
+-#include <asm/arch/gpio.h>
+-
+-/*
+- * Lots of small functions here. We depend on --gc-sections getting
+- * rid of the ones we don't need.
+- */
+-void gpio_enable_ebi(void)
+-{
+-#ifdef CFG_HSDRAMC
+-#ifndef CFG_SDRAM_16BIT
+-	gpio_select_periph_A(GPIO_PIN_PE0, 0);
+-	gpio_select_periph_A(GPIO_PIN_PE1, 0);
+-	gpio_select_periph_A(GPIO_PIN_PE2, 0);
+-	gpio_select_periph_A(GPIO_PIN_PE3, 0);
+-	gpio_select_periph_A(GPIO_PIN_PE4, 0);
+-	gpio_select_periph_A(GPIO_PIN_PE5, 0);
+-	gpio_select_periph_A(GPIO_PIN_PE6, 0);
+-	gpio_select_periph_A(GPIO_PIN_PE7, 0);
+-	gpio_select_periph_A(GPIO_PIN_PE8, 0);
+-	gpio_select_periph_A(GPIO_PIN_PE9, 0);
+-	gpio_select_periph_A(GPIO_PIN_PE10, 0);
+-	gpio_select_periph_A(GPIO_PIN_PE11, 0);
+-	gpio_select_periph_A(GPIO_PIN_PE12, 0);
+-	gpio_select_periph_A(GPIO_PIN_PE13, 0);
+-	gpio_select_periph_A(GPIO_PIN_PE14, 0);
+-	gpio_select_periph_A(GPIO_PIN_PE15, 0);
+-#endif
+-	gpio_select_periph_A(GPIO_PIN_PE26, 0);
+-#endif
+-}
+-
+-void gpio_enable_usart0(void)
+-{
+-	gpio_select_periph_B(GPIO_PIN_PA8, 0);
+-	gpio_select_periph_B(GPIO_PIN_PA9, 0);
+-}
+-
+-void gpio_enable_usart1(void)
+-{
+-	gpio_select_periph_A(GPIO_PIN_PA17, 0);
+-	gpio_select_periph_A(GPIO_PIN_PA18, 0);
+-}
+-
+-void gpio_enable_usart2(void)
+-{
+-	gpio_select_periph_B(GPIO_PIN_PB26, 0);
+-	gpio_select_periph_B(GPIO_PIN_PB27, 0);
+-}
+-
+-void gpio_enable_usart3(void)
+-{
+-	gpio_select_periph_B(GPIO_PIN_PB18, 0);
+-	gpio_select_periph_B(GPIO_PIN_PB19, 0);
+-}
+-
+-void gpio_enable_macb0(void)
+-{
+-	gpio_select_periph_A(GPIO_PIN_PC3,  0);	/* TXD0	*/
+-	gpio_select_periph_A(GPIO_PIN_PC4,  0);	/* TXD1	*/
+-	gpio_select_periph_A(GPIO_PIN_PC7,  0);	/* TXEN	*/
+-	gpio_select_periph_A(GPIO_PIN_PC8,  0);	/* TXCK */
+-	gpio_select_periph_A(GPIO_PIN_PC9,  0);	/* RXD0	*/
+-	gpio_select_periph_A(GPIO_PIN_PC10, 0);	/* RXD1	*/
+-	gpio_select_periph_A(GPIO_PIN_PC13, 0);	/* RXER	*/
+-	gpio_select_periph_A(GPIO_PIN_PC15, 0);	/* RXDV	*/
+-	gpio_select_periph_A(GPIO_PIN_PC16, 0);	/* MDC	*/
+-	gpio_select_periph_A(GPIO_PIN_PC17, 0);	/* MDIO	*/
+-#if !defined(CONFIG_RMII)
+-	gpio_select_periph_A(GPIO_PIN_PC0,  0);	/* COL	*/
+-	gpio_select_periph_A(GPIO_PIN_PC1,  0);	/* CRS	*/
+-	gpio_select_periph_A(GPIO_PIN_PC2,  0);	/* TXER	*/
+-	gpio_select_periph_A(GPIO_PIN_PC5,  0);	/* TXD2	*/
+-	gpio_select_periph_A(GPIO_PIN_PC6,  0);	/* TXD3 */
+-	gpio_select_periph_A(GPIO_PIN_PC11, 0);	/* RXD2	*/
+-	gpio_select_periph_A(GPIO_PIN_PC12, 0);	/* RXD3	*/
+-	gpio_select_periph_A(GPIO_PIN_PC14, 0);	/* RXCK	*/
+-	gpio_select_periph_A(GPIO_PIN_PC18, 0);	/* SPD	*/
+-#endif
+-}
+-
+-void gpio_enable_macb1(void)
+-{
+-	gpio_select_periph_B(GPIO_PIN_PD13, 0);	/* TXD0	*/
+-	gpio_select_periph_B(GPIO_PIN_PD14, 0);	/* TXD1	*/
+-	gpio_select_periph_B(GPIO_PIN_PD11, 0);	/* TXEN	*/
+-	gpio_select_periph_B(GPIO_PIN_PD12, 0);	/* TXCK */
+-	gpio_select_periph_B(GPIO_PIN_PD10, 0);	/* RXD0	*/
+-	gpio_select_periph_B(GPIO_PIN_PD6,  0);	/* RXD1	*/
+-	gpio_select_periph_B(GPIO_PIN_PD5,  0);	/* RXER	*/
+-	gpio_select_periph_B(GPIO_PIN_PD4,  0);	/* RXDV	*/
+-	gpio_select_periph_B(GPIO_PIN_PD3,  0);	/* MDC	*/
+-	gpio_select_periph_B(GPIO_PIN_PD2,  0);	/* MDIO	*/
+-#if !defined(CONFIG_RMII)
+-	gpio_select_periph_B(GPIO_PIN_PC19, 0);	/* COL	*/
+-	gpio_select_periph_B(GPIO_PIN_PC23, 0);	/* CRS	*/
+-	gpio_select_periph_B(GPIO_PIN_PC26, 0);	/* TXER	*/
+-	gpio_select_periph_B(GPIO_PIN_PC27, 0);	/* TXD2	*/
+-	gpio_select_periph_B(GPIO_PIN_PC28, 0);	/* TXD3 */
+-	gpio_select_periph_B(GPIO_PIN_PC29, 0);	/* RXD2	*/
+-	gpio_select_periph_B(GPIO_PIN_PC30, 0);	/* RXD3	*/
+-	gpio_select_periph_B(GPIO_PIN_PC24, 0);	/* RXCK	*/
+-	gpio_select_periph_B(GPIO_PIN_PD15, 0);	/* SPD	*/
+-#endif
+-}
+-
+-void gpio_enable_mmci(void)
+-{
+-	gpio_select_periph_A(GPIO_PIN_PA10, 0);	/* CLK	 */
+-	gpio_select_periph_A(GPIO_PIN_PA11, 0);	/* CMD	 */
+-	gpio_select_periph_A(GPIO_PIN_PA12, 0);	/* DATA0 */
+-	gpio_select_periph_A(GPIO_PIN_PA13, 0);	/* DATA1 */
+-	gpio_select_periph_A(GPIO_PIN_PA14, 0);	/* DATA2 */
+-	gpio_select_periph_A(GPIO_PIN_PA15, 0);	/* DATA3 */
+-}
+diff --git a/cpu/at32ap/at32ap700x/Makefile b/cpu/at32ap/at32ap700x/Makefile
+new file mode 100644
+index 0000000..d276712
+--- /dev/null
++++ b/cpu/at32ap/at32ap700x/Makefile
+@@ -0,0 +1,43 @@
++#
++# Copyright (C) 2005-2006 Atmel Corporation
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB	:= $(obj)lib$(SOC).a
++
++COBJS	:= gpio.o
++SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
++
++all: $(obj).depend $(LIB)
++
++$(LIB): $(OBJS)
++	$(AR) $(ARFLAGS) $@ $^
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/cpu/at32ap/at32ap700x/gpio.c b/cpu/at32ap/at32ap700x/gpio.c
+new file mode 100644
+index 0000000..859124a
+--- /dev/null
++++ b/cpu/at32ap/at32ap700x/gpio.c
+@@ -0,0 +1,144 @@
++/*
++ * Copyright (C) 2006 Atmel Corporation
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#include <common.h>
++
++#include <asm/arch/chip-features.h>
++#include <asm/arch/gpio.h>
++
++/*
++ * Lots of small functions here. We depend on --gc-sections getting
++ * rid of the ones we don't need.
++ */
++void gpio_enable_ebi(void)
++{
++#ifdef CFG_HSDRAMC
++#ifndef CFG_SDRAM_16BIT
++	gpio_select_periph_A(GPIO_PIN_PE0, 0);
++	gpio_select_periph_A(GPIO_PIN_PE1, 0);
++	gpio_select_periph_A(GPIO_PIN_PE2, 0);
++	gpio_select_periph_A(GPIO_PIN_PE3, 0);
++	gpio_select_periph_A(GPIO_PIN_PE4, 0);
++	gpio_select_periph_A(GPIO_PIN_PE5, 0);
++	gpio_select_periph_A(GPIO_PIN_PE6, 0);
++	gpio_select_periph_A(GPIO_PIN_PE7, 0);
++	gpio_select_periph_A(GPIO_PIN_PE8, 0);
++	gpio_select_periph_A(GPIO_PIN_PE9, 0);
++	gpio_select_periph_A(GPIO_PIN_PE10, 0);
++	gpio_select_periph_A(GPIO_PIN_PE11, 0);
++	gpio_select_periph_A(GPIO_PIN_PE12, 0);
++	gpio_select_periph_A(GPIO_PIN_PE13, 0);
++	gpio_select_periph_A(GPIO_PIN_PE14, 0);
++	gpio_select_periph_A(GPIO_PIN_PE15, 0);
++#endif
++	gpio_select_periph_A(GPIO_PIN_PE26, 0);
++#endif
++}
++
++#ifdef AT32AP700x_CHIP_HAS_USART
++void gpio_enable_usart0(void)
++{
++	gpio_select_periph_B(GPIO_PIN_PA8, 0);
++	gpio_select_periph_B(GPIO_PIN_PA9, 0);
++}
++
++void gpio_enable_usart1(void)
++{
++	gpio_select_periph_A(GPIO_PIN_PA17, 0);
++	gpio_select_periph_A(GPIO_PIN_PA18, 0);
++}
++
++void gpio_enable_usart2(void)
++{
++	gpio_select_periph_B(GPIO_PIN_PB26, 0);
++	gpio_select_periph_B(GPIO_PIN_PB27, 0);
++}
++
++void gpio_enable_usart3(void)
++{
++	gpio_select_periph_B(GPIO_PIN_PB17, 0);
++	gpio_select_periph_B(GPIO_PIN_PB18, 0);
++}
++#endif
++
++#ifdef AT32AP700x_CHIP_HAS_MACB
++void gpio_enable_macb0(void)
++{
++	gpio_select_periph_A(GPIO_PIN_PC3,  0);	/* TXD0	*/
++	gpio_select_periph_A(GPIO_PIN_PC4,  0);	/* TXD1	*/
++	gpio_select_periph_A(GPIO_PIN_PC7,  0);	/* TXEN	*/
++	gpio_select_periph_A(GPIO_PIN_PC8,  0);	/* TXCK */
++	gpio_select_periph_A(GPIO_PIN_PC9,  0);	/* RXD0	*/
++	gpio_select_periph_A(GPIO_PIN_PC10, 0);	/* RXD1	*/
++	gpio_select_periph_A(GPIO_PIN_PC13, 0);	/* RXER	*/
++	gpio_select_periph_A(GPIO_PIN_PC15, 0);	/* RXDV	*/
++	gpio_select_periph_A(GPIO_PIN_PC16, 0);	/* MDC	*/
++	gpio_select_periph_A(GPIO_PIN_PC17, 0);	/* MDIO	*/
++#if !defined(CONFIG_RMII)
++	gpio_select_periph_A(GPIO_PIN_PC0,  0);	/* COL	*/
++	gpio_select_periph_A(GPIO_PIN_PC1,  0);	/* CRS	*/
++	gpio_select_periph_A(GPIO_PIN_PC2,  0);	/* TXER	*/
++	gpio_select_periph_A(GPIO_PIN_PC5,  0);	/* TXD2	*/
++	gpio_select_periph_A(GPIO_PIN_PC6,  0);	/* TXD3 */
++	gpio_select_periph_A(GPIO_PIN_PC11, 0);	/* RXD2	*/
++	gpio_select_periph_A(GPIO_PIN_PC12, 0);	/* RXD3	*/
++	gpio_select_periph_A(GPIO_PIN_PC14, 0);	/* RXCK	*/
++	gpio_select_periph_A(GPIO_PIN_PC18, 0);	/* SPD	*/
++#endif
++}
++
++void gpio_enable_macb1(void)
++{
++	gpio_select_periph_B(GPIO_PIN_PD13, 0);	/* TXD0	*/
++	gpio_select_periph_B(GPIO_PIN_PD14, 0);	/* TXD1	*/
++	gpio_select_periph_B(GPIO_PIN_PD11, 0);	/* TXEN	*/
++	gpio_select_periph_B(GPIO_PIN_PD12, 0);	/* TXCK */
++	gpio_select_periph_B(GPIO_PIN_PD10, 0);	/* RXD0	*/
++	gpio_select_periph_B(GPIO_PIN_PD6,  0);	/* RXD1	*/
++	gpio_select_periph_B(GPIO_PIN_PD5,  0);	/* RXER	*/
++	gpio_select_periph_B(GPIO_PIN_PD4,  0);	/* RXDV	*/
++	gpio_select_periph_B(GPIO_PIN_PD3,  0);	/* MDC	*/
++	gpio_select_periph_B(GPIO_PIN_PD2,  0);	/* MDIO	*/
++#if !defined(CONFIG_RMII)
++	gpio_select_periph_B(GPIO_PIN_PC19, 0);	/* COL	*/
++	gpio_select_periph_B(GPIO_PIN_PC23, 0);	/* CRS	*/
++	gpio_select_periph_B(GPIO_PIN_PC26, 0);	/* TXER	*/
++	gpio_select_periph_B(GPIO_PIN_PC27, 0);	/* TXD2	*/
++	gpio_select_periph_B(GPIO_PIN_PC28, 0);	/* TXD3 */
++	gpio_select_periph_B(GPIO_PIN_PC29, 0);	/* RXD2	*/
++	gpio_select_periph_B(GPIO_PIN_PC30, 0);	/* RXD3	*/
++	gpio_select_periph_B(GPIO_PIN_PC24, 0);	/* RXCK	*/
++	gpio_select_periph_B(GPIO_PIN_PD15, 0);	/* SPD	*/
++#endif
++}
++#endif
++
++#ifdef AT32AP700x_CHIP_HAS_MMCI
++void gpio_enable_mmci(void)
++{
++	gpio_select_periph_A(GPIO_PIN_PA10, 0);	/* CLK	 */
++	gpio_select_periph_A(GPIO_PIN_PA11, 0);	/* CMD	 */
++	gpio_select_periph_A(GPIO_PIN_PA12, 0);	/* DATA0 */
++	gpio_select_periph_A(GPIO_PIN_PA13, 0);	/* DATA1 */
++	gpio_select_periph_A(GPIO_PIN_PA14, 0);	/* DATA2 */
++	gpio_select_periph_A(GPIO_PIN_PA15, 0);	/* DATA3 */
++}
++#endif
+diff --git a/cpu/at32ap/atmel_mci.c b/cpu/at32ap/atmel_mci.c
+index cf48be1..f59dfb5 100644
+--- a/cpu/at32ap/atmel_mci.c
++++ b/cpu/at32ap/atmel_mci.c
+@@ -198,11 +198,11 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
+ 
+ 	/* Put the device into Transfer state */
+ 	ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR);
+-	if (ret) goto fail;
++	if (ret) goto out;
+ 
+ 	/* Set block length */
+ 	ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR);
+-	if (ret) goto fail;
++	if (ret) goto out;
+ 
+ 	pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR));
+ 
+@@ -211,7 +211,7 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
+ 			      start * mmc_blkdev.blksz, resp,
+ 			      (R1 | NCR | TRCMD_START | TRDIR_READ
+ 			       | TRTYP_BLOCK));
+-		if (ret) goto fail;
++		if (ret) goto out;
+ 
+ 		ret = -EIO;
+ 		wordcount = 0;
+@@ -219,7 +219,7 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
+ 			do {
+ 				status = mmci_readl(SR);
+ 				if (status & (ERROR_FLAGS | MMCI_BIT(OVRE)))
+-					goto fail;
++					goto read_error;
+ 			} while (!(status & MMCI_BIT(RXRDY)));
+ 
+ 			if (status & MMCI_BIT(RXRDY)) {
+@@ -244,9 +244,10 @@ out:
+ 	mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR);
+ 	return i;
+ 
+-fail:
++read_error:
+ 	mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR);
+-	printf("mmc: bread failed, card status = %08x\n", card_status);
++	printf("mmc: bread failed, status = %08x, card status = %08x\n",
++	       status, card_status);
+ 	goto out;
+ }
+ 
+diff --git a/include/asm-avr32/arch-at32ap7000/clk.h b/include/asm-avr32/arch-at32ap7000/clk.h
+deleted file mode 100644
+index 7e20d97..0000000
+--- a/include/asm-avr32/arch-at32ap7000/clk.h
++++ /dev/null
+@@ -1,70 +0,0 @@
+-/*
+- * Copyright (C) 2006 Atmel Corporation
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-#ifndef __ASM_AVR32_ARCH_CLK_H__
+-#define __ASM_AVR32_ARCH_CLK_H__
+-
+-#ifdef CONFIG_PLL
+-#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
+-#else
+-#define MAIN_CLK_RATE (CFG_OSC0_HZ)
+-#endif
+-
+-static inline unsigned long get_cpu_clk_rate(void)
+-{
+-	return MAIN_CLK_RATE >> CFG_CLKDIV_CPU;
+-}
+-static inline unsigned long get_hsb_clk_rate(void)
+-{
+-	return MAIN_CLK_RATE >> CFG_CLKDIV_HSB;
+-}
+-static inline unsigned long get_pba_clk_rate(void)
+-{
+-	return MAIN_CLK_RATE >> CFG_CLKDIV_PBA;
+-}
+-static inline unsigned long get_pbb_clk_rate(void)
+-{
+-	return MAIN_CLK_RATE >> CFG_CLKDIV_PBB;
+-}
+-
+-/* Accessors for specific devices. More will be added as needed. */
+-static inline unsigned long get_sdram_clk_rate(void)
+-{
+-	return get_hsb_clk_rate();
+-}
+-static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
+-{
+-	return get_pba_clk_rate();
+-}
+-static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
+-{
+-	return get_pbb_clk_rate();
+-}
+-static inline unsigned long get_macb_hclk_rate(unsigned int dev_id)
+-{
+-	return get_hsb_clk_rate();
+-}
+-static inline unsigned long get_mci_clk_rate(void)
+-{
+-	return get_pbb_clk_rate();
+-}
+-
+-#endif /* __ASM_AVR32_ARCH_CLK_H__ */
+diff --git a/include/asm-avr32/arch-at32ap7000/gpio.h b/include/asm-avr32/arch-at32ap7000/gpio.h
+deleted file mode 100644
+index e4812d4..0000000
+--- a/include/asm-avr32/arch-at32ap7000/gpio.h
++++ /dev/null
+@@ -1,212 +0,0 @@
+-/*
+- * Copyright (C) 2006 Atmel Corporation
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-#ifndef __ASM_AVR32_ARCH_GPIO_H__
+-#define __ASM_AVR32_ARCH_GPIO_H__
+-
+-#include <asm/arch/memory-map.h>
+-
+-#define NR_GPIO_CONTROLLERS	5
+-
+-/*
+- * Pin numbers identifying specific GPIO pins on the chip.
+- */
+-#define GPIO_PIOA_BASE	(0)
+-#define GPIO_PIN_PA0	(GPIO_PIOA_BASE +  0)
+-#define GPIO_PIN_PA1	(GPIO_PIOA_BASE +  1)
+-#define GPIO_PIN_PA2	(GPIO_PIOA_BASE +  2)
+-#define GPIO_PIN_PA3	(GPIO_PIOA_BASE +  3)
+-#define GPIO_PIN_PA4	(GPIO_PIOA_BASE +  4)
+-#define GPIO_PIN_PA5	(GPIO_PIOA_BASE +  5)
+-#define GPIO_PIN_PA6	(GPIO_PIOA_BASE +  6)
+-#define GPIO_PIN_PA7	(GPIO_PIOA_BASE +  7)
+-#define GPIO_PIN_PA8	(GPIO_PIOA_BASE +  8)
+-#define GPIO_PIN_PA9	(GPIO_PIOA_BASE +  9)
+-#define GPIO_PIN_PA10	(GPIO_PIOA_BASE + 10)
+-#define GPIO_PIN_PA11	(GPIO_PIOA_BASE + 11)
+-#define GPIO_PIN_PA12	(GPIO_PIOA_BASE + 12)
+-#define GPIO_PIN_PA13	(GPIO_PIOA_BASE + 13)
+-#define GPIO_PIN_PA14	(GPIO_PIOA_BASE + 14)
+-#define GPIO_PIN_PA15	(GPIO_PIOA_BASE + 15)
+-#define GPIO_PIN_PA16	(GPIO_PIOA_BASE + 16)
+-#define GPIO_PIN_PA17	(GPIO_PIOA_BASE + 17)
+-#define GPIO_PIN_PA18	(GPIO_PIOA_BASE + 18)
+-#define GPIO_PIN_PA19	(GPIO_PIOA_BASE + 19)
+-#define GPIO_PIN_PA20	(GPIO_PIOA_BASE + 20)
+-#define GPIO_PIN_PA21	(GPIO_PIOA_BASE + 21)
+-#define GPIO_PIN_PA22	(GPIO_PIOA_BASE + 22)
+-#define GPIO_PIN_PA23	(GPIO_PIOA_BASE + 23)
+-#define GPIO_PIN_PA24	(GPIO_PIOA_BASE + 24)
+-#define GPIO_PIN_PA25	(GPIO_PIOA_BASE + 25)
+-#define GPIO_PIN_PA26	(GPIO_PIOA_BASE + 26)
+-#define GPIO_PIN_PA27	(GPIO_PIOA_BASE + 27)
+-#define GPIO_PIN_PA28	(GPIO_PIOA_BASE + 28)
+-#define GPIO_PIN_PA29	(GPIO_PIOA_BASE + 29)
+-#define GPIO_PIN_PA30	(GPIO_PIOA_BASE + 30)
+-#define GPIO_PIN_PA31	(GPIO_PIOA_BASE + 31)
+-
+-#define GPIO_PIOB_BASE	(GPIO_PIOA_BASE + 32)
+-#define GPIO_PIN_PB0	(GPIO_PIOB_BASE +  0)
+-#define GPIO_PIN_PB1	(GPIO_PIOB_BASE +  1)
+-#define GPIO_PIN_PB2	(GPIO_PIOB_BASE +  2)
+-#define GPIO_PIN_PB3	(GPIO_PIOB_BASE +  3)
+-#define GPIO_PIN_PB4	(GPIO_PIOB_BASE +  4)
+-#define GPIO_PIN_PB5	(GPIO_PIOB_BASE +  5)
+-#define GPIO_PIN_PB6	(GPIO_PIOB_BASE +  6)
+-#define GPIO_PIN_PB7	(GPIO_PIOB_BASE +  7)
+-#define GPIO_PIN_PB8	(GPIO_PIOB_BASE +  8)
+-#define GPIO_PIN_PB9	(GPIO_PIOB_BASE +  9)
+-#define GPIO_PIN_PB10	(GPIO_PIOB_BASE + 10)
+-#define GPIO_PIN_PB11	(GPIO_PIOB_BASE + 11)
+-#define GPIO_PIN_PB12	(GPIO_PIOB_BASE + 12)
+-#define GPIO_PIN_PB13	(GPIO_PIOB_BASE + 13)
+-#define GPIO_PIN_PB14	(GPIO_PIOB_BASE + 14)
+-#define GPIO_PIN_PB15	(GPIO_PIOB_BASE + 15)
+-#define GPIO_PIN_PB16	(GPIO_PIOB_BASE + 16)
+-#define GPIO_PIN_PB17	(GPIO_PIOB_BASE + 17)
+-#define GPIO_PIN_PB18	(GPIO_PIOB_BASE + 18)
+-#define GPIO_PIN_PB19	(GPIO_PIOB_BASE + 19)
+-#define GPIO_PIN_PB20	(GPIO_PIOB_BASE + 20)
+-#define GPIO_PIN_PB21	(GPIO_PIOB_BASE + 21)
+-#define GPIO_PIN_PB22	(GPIO_PIOB_BASE + 22)
+-#define GPIO_PIN_PB23	(GPIO_PIOB_BASE + 23)
+-#define GPIO_PIN_PB24	(GPIO_PIOB_BASE + 24)
+-#define GPIO_PIN_PB25	(GPIO_PIOB_BASE + 25)
+-#define GPIO_PIN_PB26	(GPIO_PIOB_BASE + 26)
+-#define GPIO_PIN_PB27	(GPIO_PIOB_BASE + 27)
+-#define GPIO_PIN_PB28	(GPIO_PIOB_BASE + 28)
+-#define GPIO_PIN_PB29	(GPIO_PIOB_BASE + 29)
+-#define GPIO_PIN_PB30	(GPIO_PIOB_BASE + 30)
+-
+-#define GPIO_PIOC_BASE	(GPIO_PIOB_BASE + 32)
+-#define GPIO_PIN_PC0	(GPIO_PIOC_BASE +  0)
+-#define GPIO_PIN_PC1	(GPIO_PIOC_BASE +  1)
+-#define GPIO_PIN_PC2	(GPIO_PIOC_BASE +  2)
+-#define GPIO_PIN_PC3	(GPIO_PIOC_BASE +  3)
+-#define GPIO_PIN_PC4	(GPIO_PIOC_BASE +  4)
+-#define GPIO_PIN_PC5	(GPIO_PIOC_BASE +  5)
+-#define GPIO_PIN_PC6	(GPIO_PIOC_BASE +  6)
+-#define GPIO_PIN_PC7	(GPIO_PIOC_BASE +  7)
+-#define GPIO_PIN_PC8	(GPIO_PIOC_BASE +  8)
+-#define GPIO_PIN_PC9	(GPIO_PIOC_BASE +  9)
+-#define GPIO_PIN_PC10	(GPIO_PIOC_BASE + 10)
+-#define GPIO_PIN_PC11	(GPIO_PIOC_BASE + 11)
+-#define GPIO_PIN_PC12	(GPIO_PIOC_BASE + 12)
+-#define GPIO_PIN_PC13	(GPIO_PIOC_BASE + 13)
+-#define GPIO_PIN_PC14	(GPIO_PIOC_BASE + 14)
+-#define GPIO_PIN_PC15	(GPIO_PIOC_BASE + 15)
+-#define GPIO_PIN_PC16	(GPIO_PIOC_BASE + 16)
+-#define GPIO_PIN_PC17	(GPIO_PIOC_BASE + 17)
+-#define GPIO_PIN_PC18	(GPIO_PIOC_BASE + 18)
+-#define GPIO_PIN_PC19	(GPIO_PIOC_BASE + 19)
+-#define GPIO_PIN_PC20	(GPIO_PIOC_BASE + 20)
+-#define GPIO_PIN_PC21	(GPIO_PIOC_BASE + 21)
+-#define GPIO_PIN_PC22	(GPIO_PIOC_BASE + 22)
+-#define GPIO_PIN_PC23	(GPIO_PIOC_BASE + 23)
+-#define GPIO_PIN_PC24	(GPIO_PIOC_BASE + 24)
+-#define GPIO_PIN_PC25	(GPIO_PIOC_BASE + 25)
+-#define GPIO_PIN_PC26	(GPIO_PIOC_BASE + 26)
+-#define GPIO_PIN_PC27	(GPIO_PIOC_BASE + 27)
+-#define GPIO_PIN_PC28	(GPIO_PIOC_BASE + 28)
+-#define GPIO_PIN_PC29	(GPIO_PIOC_BASE + 29)
+-#define GPIO_PIN_PC30	(GPIO_PIOC_BASE + 30)
+-#define GPIO_PIN_PC31	(GPIO_PIOC_BASE + 31)
+-
+-#define GPIO_PIOD_BASE	(GPIO_PIOC_BASE + 32)
+-#define GPIO_PIN_PD0	(GPIO_PIOD_BASE +  0)
+-#define GPIO_PIN_PD1	(GPIO_PIOD_BASE +  1)
+-#define GPIO_PIN_PD2	(GPIO_PIOD_BASE +  2)
+-#define GPIO_PIN_PD3	(GPIO_PIOD_BASE +  3)
+-#define GPIO_PIN_PD4	(GPIO_PIOD_BASE +  4)
+-#define GPIO_PIN_PD5	(GPIO_PIOD_BASE +  5)
+-#define GPIO_PIN_PD6	(GPIO_PIOD_BASE +  6)
+-#define GPIO_PIN_PD7	(GPIO_PIOD_BASE +  7)
+-#define GPIO_PIN_PD8	(GPIO_PIOD_BASE +  8)
+-#define GPIO_PIN_PD9	(GPIO_PIOD_BASE +  9)
+-#define GPIO_PIN_PD10	(GPIO_PIOD_BASE + 10)
+-#define GPIO_PIN_PD11	(GPIO_PIOD_BASE + 11)
+-#define GPIO_PIN_PD12	(GPIO_PIOD_BASE + 12)
+-#define GPIO_PIN_PD13	(GPIO_PIOD_BASE + 13)
+-#define GPIO_PIN_PD14	(GPIO_PIOD_BASE + 14)
+-#define GPIO_PIN_PD15	(GPIO_PIOD_BASE + 15)
+-#define GPIO_PIN_PD16	(GPIO_PIOD_BASE + 16)
+-#define GPIO_PIN_PD17	(GPIO_PIOD_BASE + 17)
+-
+-#define GPIO_PIOE_BASE	(GPIO_PIOD_BASE + 32)
+-#define GPIO_PIN_PE0	(GPIO_PIOE_BASE +  0)
+-#define GPIO_PIN_PE1	(GPIO_PIOE_BASE +  1)
+-#define GPIO_PIN_PE2	(GPIO_PIOE_BASE +  2)
+-#define GPIO_PIN_PE3	(GPIO_PIOE_BASE +  3)
+-#define GPIO_PIN_PE4	(GPIO_PIOE_BASE +  4)
+-#define GPIO_PIN_PE5	(GPIO_PIOE_BASE +  5)
+-#define GPIO_PIN_PE6	(GPIO_PIOE_BASE +  6)
+-#define GPIO_PIN_PE7	(GPIO_PIOE_BASE +  7)
+-#define GPIO_PIN_PE8	(GPIO_PIOE_BASE +  8)
+-#define GPIO_PIN_PE9	(GPIO_PIOE_BASE +  9)
+-#define GPIO_PIN_PE10	(GPIO_PIOE_BASE + 10)
+-#define GPIO_PIN_PE11	(GPIO_PIOE_BASE + 11)
+-#define GPIO_PIN_PE12	(GPIO_PIOE_BASE + 12)
+-#define GPIO_PIN_PE13	(GPIO_PIOE_BASE + 13)
+-#define GPIO_PIN_PE14	(GPIO_PIOE_BASE + 14)
+-#define GPIO_PIN_PE15	(GPIO_PIOE_BASE + 15)
+-#define GPIO_PIN_PE16	(GPIO_PIOE_BASE + 16)
+-#define GPIO_PIN_PE17	(GPIO_PIOE_BASE + 17)
+-#define GPIO_PIN_PE18	(GPIO_PIOE_BASE + 18)
+-#define GPIO_PIN_PE19	(GPIO_PIOE_BASE + 19)
+-#define GPIO_PIN_PE20	(GPIO_PIOE_BASE + 20)
+-#define GPIO_PIN_PE21	(GPIO_PIOE_BASE + 21)
+-#define GPIO_PIN_PE22	(GPIO_PIOE_BASE + 22)
+-#define GPIO_PIN_PE23	(GPIO_PIOE_BASE + 23)
+-#define GPIO_PIN_PE24	(GPIO_PIOE_BASE + 24)
+-#define GPIO_PIN_PE25	(GPIO_PIOE_BASE + 25)
+-#define GPIO_PIN_PE26	(GPIO_PIOE_BASE + 26)
+-
+-static inline void *gpio_pin_to_addr(unsigned int pin)
+-{
+-	switch (pin >> 5) {
+-	case 0:
+-		return (void *)PIOA_BASE;
+-	case 1:
+-		return (void *)PIOB_BASE;
+-	case 2:
+-		return (void *)PIOC_BASE;
+-	case 3:
+-		return (void *)PIOD_BASE;
+-	case 4:
+-		return (void *)PIOE_BASE;
+-	default:
+-		return NULL;
+-	}
+-}
+-
+-void gpio_select_periph_A(unsigned int pin, int use_pullup);
+-void gpio_select_periph_B(unsigned int pin, int use_pullup);
+-
+-void gpio_enable_ebi(void);
+-void gpio_enable_usart0(void);
+-void gpio_enable_usart1(void);
+-void gpio_enable_usart2(void);
+-void gpio_enable_usart3(void);
+-void gpio_enable_macb0(void);
+-void gpio_enable_macb1(void);
+-void gpio_enable_mmci(void);
+-
+-#endif /* __ASM_AVR32_ARCH_GPIO_H__ */
+diff --git a/include/asm-avr32/arch-at32ap7000/hmatrix2.h b/include/asm-avr32/arch-at32ap7000/hmatrix2.h
+deleted file mode 100644
+index b0e787a..0000000
+--- a/include/asm-avr32/arch-at32ap7000/hmatrix2.h
++++ /dev/null
+@@ -1,232 +0,0 @@
+-/*
+- * Register definition for the High-speed Bus Matrix
+- */
+-#ifndef __ASM_AVR32_HMATRIX2_H__
+-#define __ASM_AVR32_HMATRIX2_H__
+-
+-/* HMATRIX2 register offsets */
+-#define HMATRIX2_MCFG0				0x0000
+-#define HMATRIX2_MCFG1				0x0004
+-#define HMATRIX2_MCFG2				0x0008
+-#define HMATRIX2_MCFG3				0x000c
+-#define HMATRIX2_MCFG4				0x0010
+-#define HMATRIX2_MCFG5				0x0014
+-#define HMATRIX2_MCFG6				0x0018
+-#define HMATRIX2_MCFG7				0x001c
+-#define HMATRIX2_MCFG8				0x0020
+-#define HMATRIX2_MCFG9				0x0024
+-#define HMATRIX2_MCFG10				0x0028
+-#define HMATRIX2_MCFG11				0x002c
+-#define HMATRIX2_MCFG12				0x0030
+-#define HMATRIX2_MCFG13				0x0034
+-#define HMATRIX2_MCFG14				0x0038
+-#define HMATRIX2_MCFG15				0x003c
+-#define HMATRIX2_SCFG0				0x0040
+-#define HMATRIX2_SCFG1				0x0044
+-#define HMATRIX2_SCFG2				0x0048
+-#define HMATRIX2_SCFG3				0x004c
+-#define HMATRIX2_SCFG4				0x0050
+-#define HMATRIX2_SCFG5				0x0054
+-#define HMATRIX2_SCFG6				0x0058
+-#define HMATRIX2_SCFG7				0x005c
+-#define HMATRIX2_SCFG8				0x0060
+-#define HMATRIX2_SCFG9				0x0064
+-#define HMATRIX2_SCFG10				0x0068
+-#define HMATRIX2_SCFG11				0x006c
+-#define HMATRIX2_SCFG12				0x0070
+-#define HMATRIX2_SCFG13				0x0074
+-#define HMATRIX2_SCFG14				0x0078
+-#define HMATRIX2_SCFG15				0x007c
+-#define HMATRIX2_PRAS0				0x0080
+-#define HMATRIX2_PRBS0				0x0084
+-#define HMATRIX2_PRAS1				0x0088
+-#define HMATRIX2_PRBS1				0x008c
+-#define HMATRIX2_PRAS2				0x0090
+-#define HMATRIX2_PRBS2				0x0094
+-#define HMATRIX2_PRAS3				0x0098
+-#define HMATRIX2_PRBS3				0x009c
+-#define HMATRIX2_PRAS4				0x00a0
+-#define HMATRIX2_PRBS4				0x00a4
+-#define HMATRIX2_PRAS5				0x00a8
+-#define HMATRIX2_PRBS5				0x00ac
+-#define HMATRIX2_PRAS6				0x00b0
+-#define HMATRIX2_PRBS6				0x00b4
+-#define HMATRIX2_PRAS7				0x00b8
+-#define HMATRIX2_PRBS7				0x00bc
+-#define HMATRIX2_PRAS8				0x00c0
+-#define HMATRIX2_PRBS8				0x00c4
+-#define HMATRIX2_PRAS9				0x00c8
+-#define HMATRIX2_PRBS9				0x00cc
+-#define HMATRIX2_PRAS10				0x00d0
+-#define HMATRIX2_PRBS10				0x00d4
+-#define HMATRIX2_PRAS11				0x00d8
+-#define HMATRIX2_PRBS11				0x00dc
+-#define HMATRIX2_PRAS12				0x00e0
+-#define HMATRIX2_PRBS12				0x00e4
+-#define HMATRIX2_PRAS13				0x00e8
+-#define HMATRIX2_PRBS13				0x00ec
+-#define HMATRIX2_PRAS14				0x00f0
+-#define HMATRIX2_PRBS14				0x00f4
+-#define HMATRIX2_PRAS15				0x00f8
+-#define HMATRIX2_PRBS15				0x00fc
+-#define HMATRIX2_MRCR				0x0100
+-#define HMATRIX2_SFR0				0x0110
+-#define HMATRIX2_SFR1				0x0114
+-#define HMATRIX2_SFR2				0x0118
+-#define HMATRIX2_SFR3				0x011c
+-#define HMATRIX2_SFR4				0x0120
+-#define HMATRIX2_SFR5				0x0124
+-#define HMATRIX2_SFR6				0x0128
+-#define HMATRIX2_SFR7				0x012c
+-#define HMATRIX2_SFR8				0x0130
+-#define HMATRIX2_SFR9				0x0134
+-#define HMATRIX2_SFR10				0x0138
+-#define HMATRIX2_SFR11				0x013c
+-#define HMATRIX2_SFR12				0x0140
+-#define HMATRIX2_SFR13				0x0144
+-#define HMATRIX2_SFR14				0x0148
+-#define HMATRIX2_SFR15				0x014c
+-#define HMATRIX2_VERSION			0x01fc
+-
+-/* Bitfields in MCFG0 */
+-#define HMATRIX2_ULBT_OFFSET			0
+-#define HMATRIX2_ULBT_SIZE			3
+-
+-/* Bitfields in SCFG0 */
+-#define HMATRIX2_SLOT_CYCLE_OFFSET		0
+-#define HMATRIX2_SLOT_CYCLE_SIZE		8
+-#define HMATRIX2_DEFMSTR_TYPE_OFFSET		16
+-#define HMATRIX2_DEFMSTR_TYPE_SIZE		2
+-#define HMATRIX2_FIXED_DEFMSTR_OFFSET		18
+-#define HMATRIX2_FIXED_DEFMSTR_SIZE		4
+-#define HMATRIX2_ARBT_OFFSET			24
+-#define HMATRIX2_ARBT_SIZE			2
+-
+-/* Bitfields in PRAS0 */
+-#define HMATRIX2_M0PR_OFFSET			0
+-#define HMATRIX2_M0PR_SIZE			4
+-#define HMATRIX2_M1PR_OFFSET			4
+-#define HMATRIX2_M1PR_SIZE			4
+-#define HMATRIX2_M2PR_OFFSET			8
+-#define HMATRIX2_M2PR_SIZE			4
+-#define HMATRIX2_M3PR_OFFSET			12
+-#define HMATRIX2_M3PR_SIZE			4
+-#define HMATRIX2_M4PR_OFFSET			16
+-#define HMATRIX2_M4PR_SIZE			4
+-#define HMATRIX2_M5PR_OFFSET			20
+-#define HMATRIX2_M5PR_SIZE			4
+-#define HMATRIX2_M6PR_OFFSET			24
+-#define HMATRIX2_M6PR_SIZE			4
+-#define HMATRIX2_M7PR_OFFSET			28
+-#define HMATRIX2_M7PR_SIZE			4
+-
+-/* Bitfields in PRBS0 */
+-#define HMATRIX2_M8PR_OFFSET			0
+-#define HMATRIX2_M8PR_SIZE			4
+-#define HMATRIX2_M9PR_OFFSET			4
+-#define HMATRIX2_M9PR_SIZE			4
+-#define HMATRIX2_M10PR_OFFSET			8
+-#define HMATRIX2_M10PR_SIZE			4
+-#define HMATRIX2_M11PR_OFFSET			12
+-#define HMATRIX2_M11PR_SIZE			4
+-#define HMATRIX2_M12PR_OFFSET			16
+-#define HMATRIX2_M12PR_SIZE			4
+-#define HMATRIX2_M13PR_OFFSET			20
+-#define HMATRIX2_M13PR_SIZE			4
+-#define HMATRIX2_M14PR_OFFSET			24
+-#define HMATRIX2_M14PR_SIZE			4
+-#define HMATRIX2_M15PR_OFFSET			28
+-#define HMATRIX2_M15PR_SIZE			4
+-
+-/* Bitfields in MRCR */
+-#define HMATRIX2_RBC0_OFFSET			0
+-#define HMATRIX2_RBC0_SIZE			1
+-#define HMATRIX2_RBC1_OFFSET			1
+-#define HMATRIX2_RBC1_SIZE			1
+-#define HMATRIX2_RBC2_OFFSET			2
+-#define HMATRIX2_RBC2_SIZE			1
+-#define HMATRIX2_RBC3_OFFSET			3
+-#define HMATRIX2_RBC3_SIZE			1
+-#define HMATRIX2_RBC4_OFFSET			4
+-#define HMATRIX2_RBC4_SIZE			1
+-#define HMATRIX2_RBC5_OFFSET			5
+-#define HMATRIX2_RBC5_SIZE			1
+-#define HMATRIX2_RBC6_OFFSET			6
+-#define HMATRIX2_RBC6_SIZE			1
+-#define HMATRIX2_RBC7_OFFSET			7
+-#define HMATRIX2_RBC7_SIZE			1
+-#define HMATRIX2_RBC8_OFFSET			8
+-#define HMATRIX2_RBC8_SIZE			1
+-#define HMATRIX2_RBC9_OFFSET			9
+-#define HMATRIX2_RBC9_SIZE			1
+-#define HMATRIX2_RBC10_OFFSET			10
+-#define HMATRIX2_RBC10_SIZE			1
+-#define HMATRIX2_RBC11_OFFSET			11
+-#define HMATRIX2_RBC11_SIZE			1
+-#define HMATRIX2_RBC12_OFFSET			12
+-#define HMATRIX2_RBC12_SIZE			1
+-#define HMATRIX2_RBC13_OFFSET			13
+-#define HMATRIX2_RBC13_SIZE			1
+-#define HMATRIX2_RBC14_OFFSET			14
+-#define HMATRIX2_RBC14_SIZE			1
+-#define HMATRIX2_RBC15_OFFSET			15
+-#define HMATRIX2_RBC15_SIZE			1
+-
+-/* Bitfields in SFR0 */
+-#define HMATRIX2_SFR_OFFSET			0
+-#define HMATRIX2_SFR_SIZE			32
+-
+-/* Bitfields in SFR4 */
+-#define HMATRIX2_CS1A_OFFSET			1
+-#define HMATRIX2_CS1A_SIZE			1
+-#define HMATRIX2_CS3A_OFFSET			3
+-#define HMATRIX2_CS3A_SIZE			1
+-#define HMATRIX2_CS4A_OFFSET			4
+-#define HMATRIX2_CS4A_SIZE			1
+-#define HMATRIX2_CS5A_OFFSET			5
+-#define HMATRIX2_CS5A_SIZE			1
+-#define HMATRIX2_DBPUC_OFFSET			8
+-#define HMATRIX2_DBPUC_SIZE			1
+-
+-/* Bitfields in VERSION */
+-#define HMATRIX2_VERSION_OFFSET			0
+-#define HMATRIX2_VERSION_SIZE			12
+-#define HMATRIX2_MFN_OFFSET			16
+-#define HMATRIX2_MFN_SIZE			3
+-
+-/* Constants for ULBT */
+-#define HMATRIX2_ULBT_INFINITE			0
+-#define HMATRIX2_ULBT_SINGLE			1
+-#define HMATRIX2_ULBT_FOUR_BEAT			2
+-#define HMATRIX2_ULBT_SIXTEEN_BEAT		4
+-
+-/* Constants for DEFMSTR_TYPE */
+-#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT	0
+-#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT	1
+-#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT	2
+-
+-/* Constants for ARBT */
+-#define HMATRIX2_ARBT_ROUND_ROBIN		0
+-#define HMATRIX2_ARBT_FIXED_PRIORITY		1
+-
+-/* Bit manipulation macros */
+-#define HMATRIX2_BIT(name)					\
+-	(1 << HMATRIX2_##name##_OFFSET)
+-#define HMATRIX2_BF(name,value)					\
+-	(((value) & ((1 << HMATRIX2_##name##_SIZE) - 1))	\
+-	 << HMATRIX2_##name##_OFFSET)
+-#define HMATRIX2_BFEXT(name,value)				\
+-	(((value) >> HMATRIX2_##name##_OFFSET)			\
+-	 & ((1 << HMATRIX2_##name##_SIZE) - 1))
+-#define HMATRIX2_BFINS(name,value,old)				\
+-	(((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1)		\
+-		    << HMATRIX2_##name##_OFFSET))		\
+-	 | HMATRIX2_BF(name,value))
+-
+-/* Register access macros */
+-#define hmatrix2_readl(reg)					\
+-	readl((void *)HMATRIX_BASE + HMATRIX2_##reg)
+-#define hmatrix2_writel(reg,value)				\
+-	writel((value), (void *)HMATRIX_BASE + HMATRIX2_##reg)
+-
+-#endif /* __ASM_AVR32_HMATRIX2_H__ */
+diff --git a/include/asm-avr32/arch-at32ap7000/memory-map.h b/include/asm-avr32/arch-at32ap7000/memory-map.h
+deleted file mode 100644
+index 5513e88..0000000
+--- a/include/asm-avr32/arch-at32ap7000/memory-map.h
++++ /dev/null
+@@ -1,66 +0,0 @@
+-/*
+- * Copyright (C) 2005-2006 Atmel Corporation
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-#ifndef __AT32AP7000_MEMORY_MAP_H__
+-#define __AT32AP7000_MEMORY_MAP_H__
+-
+-/* Devices on the High Speed Bus (HSB) */
+-#define LCDC_BASE				0xFF000000
+-#define DMAC_BASE				0xFF200000
+-#define USB_FIFO				0xFF300000
+-
+-/* Devices on Peripheral Bus A (PBA) */
+-#define SPI0_BASE				0xFFE00000
+-#define SPI1_BASE				0xFFE00400
+-#define TWI_BASE				0xFFE00800
+-#define USART0_BASE				0xFFE00C00
+-#define USART1_BASE				0xFFE01000
+-#define USART2_BASE				0xFFE01400
+-#define USART3_BASE				0xFFE01800
+-#define SSC0_BASE				0xFFE01C00
+-#define SSC1_BASE				0xFFE02000
+-#define SSC2_BASE				0xFFE02400
+-#define PIOA_BASE				0xFFE02800
+-#define PIOB_BASE				0xFFE02C00
+-#define PIOC_BASE				0xFFE03000
+-#define PIOD_BASE				0xFFE03400
+-#define PIOE_BASE				0xFFE03800
+-#define PSIF_BASE				0xFFE03C00
+-
+-/* Devices on Peripheral Bus B (PBB) */
+-#define SM_BASE					0xFFF00000
+-#define INTC_BASE				0xFFF00400
+-#define HMATRIX_BASE				0xFFF00800
+-#define TIMER0_BASE				0xFFF00C00
+-#define TIMER1_BASE				0xFFF01000
+-#define PWM_BASE				0xFFF01400
+-#define MACB0_BASE				0xFFF01800
+-#define MACB1_BASE				0xFFF01C00
+-#define DAC_BASE				0xFFF02000
+-#define MMCI_BASE				0xFFF02400
+-#define AUDIOC_BASE				0xFFF02800
+-#define HISI_BASE				0xFFF02C00
+-#define USB_BASE				0xFFF03000
+-#define HSMC_BASE				0xFFF03400
+-#define HSDRAMC_BASE				0xFFF03800
+-#define ECC_BASE				0xFFF03C00
+-
+-#endif /* __AT32AP7000_MEMORY_MAP_H__ */
+diff --git a/include/asm-avr32/arch-at32ap7000/mmc.h b/include/asm-avr32/arch-at32ap7000/mmc.h
+deleted file mode 100644
+index fcfbbb3..0000000
+--- a/include/asm-avr32/arch-at32ap7000/mmc.h
++++ /dev/null
+@@ -1,96 +0,0 @@
+-/*
+- * Copyright (C) 2004-2006 Atmel Corporation
+- *
+- * See file CREDITS for list of people who contributed to this
+- * project.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation; either version 2 of
+- * the License, or (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+- * MA 02111-1307 USA
+- */
+-#ifndef __ASM_AVR32_MMC_H
+-#define __ASM_AVR32_MMC_H
+-
+-struct mmc_cid {
+-	unsigned long psn;
+-	unsigned short oid;
+-	unsigned char mid;
+-	unsigned char prv;
+-	unsigned char mdt;
+-	char pnm[7];
+-};
+-
+-struct mmc_csd
+-{
+-	u8	csd_structure:2,
+-		spec_vers:4,
+-		rsvd1:2;
+-	u8	taac;
+-	u8	nsac;
+-	u8	tran_speed;
+-	u16	ccc:12,
+-		read_bl_len:4;
+-	u64	read_bl_partial:1,
+-		write_blk_misalign:1,
+-		read_blk_misalign:1,
+-		dsr_imp:1,
+-		rsvd2:2,
+-		c_size:12,
+-		vdd_r_curr_min:3,
+-		vdd_r_curr_max:3,
+-		vdd_w_curr_min:3,
+-		vdd_w_curr_max:3,
+-		c_size_mult:3,
+-		sector_size:5,
+-		erase_grp_size:5,
+-		wp_grp_size:5,
+-		wp_grp_enable:1,
+-		default_ecc:2,
+-		r2w_factor:3,
+-		write_bl_len:4,
+-		write_bl_partial:1,
+-		rsvd3:5;
+-	u8	file_format_grp:1,
+-		copy:1,
+-		perm_write_protect:1,
+-		tmp_write_protect:1,
+-		file_format:2,
+-		ecc:2;
+-	u8	crc:7;
+-	u8	one:1;
+-};
+-
+-/* MMC Command numbers */
+-#define MMC_CMD_GO_IDLE_STATE		0
+-#define MMC_CMD_SEND_OP_COND		1
+-#define MMC_CMD_ALL_SEND_CID 		2
+-#define MMC_CMD_SET_RELATIVE_ADDR	3
+-#define MMC_CMD_SD_SEND_RELATIVE_ADDR	3
+-#define MMC_CMD_SET_DSR			4
+-#define MMC_CMD_SELECT_CARD		7
+-#define MMC_CMD_SEND_CSD 		9
+-#define MMC_CMD_SEND_CID 		10
+-#define MMC_CMD_SEND_STATUS		13
+-#define MMC_CMD_SET_BLOCKLEN		16
+-#define MMC_CMD_READ_SINGLE_BLOCK	17
+-#define MMC_CMD_READ_MULTIPLE_BLOCK	18
+-#define MMC_CMD_WRITE_BLOCK		24
+-#define MMC_CMD_APP_CMD			55
+-
+-#define MMC_ACMD_SD_SEND_OP_COND	41
+-
+-#define R1_ILLEGAL_COMMAND		(1 << 22)
+-#define R1_APP_CMD			(1 << 5)
+-
+-#endif /* __ASM_AVR32_MMC_H */
+diff --git a/include/asm-avr32/arch-at32ap700x/chip-features.h b/include/asm-avr32/arch-at32ap700x/chip-features.h
+new file mode 100644
+index 0000000..29b1fd6
+--- /dev/null
++++ b/include/asm-avr32/arch-at32ap700x/chip-features.h
+@@ -0,0 +1,34 @@
++/*
++ * Copyright (C) 2007 Atmel Corporation
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#ifndef __ASM_AVR32_ARCH_CHIP_FEATURES_H__
++#define __ASM_AVR32_ARCH_CHIP_FEATURES_H__
++
++/* Currently, all the AP700x chips have these */
++#define AT32AP700x_CHIP_HAS_USART
++#define AT32AP700x_CHIP_HAS_MMCI
++
++/* Only AP7000 has ethernet interface */
++#ifdef CONFIG_AT32AP7000
++#define AT32AP700x_CHIP_HAS_MACB
++#endif
++
++#endif /* __ASM_AVR32_ARCH_CHIP_FEATURES_H__ */
+diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h
+new file mode 100644
+index 0000000..ea84c08
+--- /dev/null
++++ b/include/asm-avr32/arch-at32ap700x/clk.h
+@@ -0,0 +1,78 @@
++/*
++ * Copyright (C) 2006 Atmel Corporation
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#ifndef __ASM_AVR32_ARCH_CLK_H__
++#define __ASM_AVR32_ARCH_CLK_H__
++
++#include <asm/arch/chip-features.h>
++
++#ifdef CONFIG_PLL
++#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
++#else
++#define MAIN_CLK_RATE (CFG_OSC0_HZ)
++#endif
++
++static inline unsigned long get_cpu_clk_rate(void)
++{
++	return MAIN_CLK_RATE >> CFG_CLKDIV_CPU;
++}
++static inline unsigned long get_hsb_clk_rate(void)
++{
++	return MAIN_CLK_RATE >> CFG_CLKDIV_HSB;
++}
++static inline unsigned long get_pba_clk_rate(void)
++{
++	return MAIN_CLK_RATE >> CFG_CLKDIV_PBA;
++}
++static inline unsigned long get_pbb_clk_rate(void)
++{
++	return MAIN_CLK_RATE >> CFG_CLKDIV_PBB;
++}
++
++/* Accessors for specific devices. More will be added as needed. */
++static inline unsigned long get_sdram_clk_rate(void)
++{
++	return get_hsb_clk_rate();
++}
++#ifdef AT32AP700x_CHIP_HAS_USART
++static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
++{
++	return get_pba_clk_rate();
++}
++#endif
++#ifdef AT32AP700x_CHIP_HAS_USART
++static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
++{
++	return get_pbb_clk_rate();
++}
++static inline unsigned long get_macb_hclk_rate(unsigned int dev_id)
++{
++	return get_hsb_clk_rate();
++}
++#endif
++#ifdef AT32AP700x_CHIP_HAS_MMCI
++static inline unsigned long get_mci_clk_rate(void)
++{
++	return get_pbb_clk_rate();
++}
++#endif
++
++#endif /* __ASM_AVR32_ARCH_CLK_H__ */
+diff --git a/include/asm-avr32/arch-at32ap700x/gpio.h b/include/asm-avr32/arch-at32ap700x/gpio.h
+new file mode 100644
+index 0000000..b10a3e4
+--- /dev/null
++++ b/include/asm-avr32/arch-at32ap700x/gpio.h
+@@ -0,0 +1,220 @@
++/*
++ * Copyright (C) 2006 Atmel Corporation
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#ifndef __ASM_AVR32_ARCH_GPIO_H__
++#define __ASM_AVR32_ARCH_GPIO_H__
++
++#include <asm/arch/chip-features.h>
++#include <asm/arch/memory-map.h>
++
++#define NR_GPIO_CONTROLLERS	5
++
++/*
++ * Pin numbers identifying specific GPIO pins on the chip.
++ */
++#define GPIO_PIOA_BASE	(0)
++#define GPIO_PIN_PA0	(GPIO_PIOA_BASE +  0)
++#define GPIO_PIN_PA1	(GPIO_PIOA_BASE +  1)
++#define GPIO_PIN_PA2	(GPIO_PIOA_BASE +  2)
++#define GPIO_PIN_PA3	(GPIO_PIOA_BASE +  3)
++#define GPIO_PIN_PA4	(GPIO_PIOA_BASE +  4)
++#define GPIO_PIN_PA5	(GPIO_PIOA_BASE +  5)
++#define GPIO_PIN_PA6	(GPIO_PIOA_BASE +  6)
++#define GPIO_PIN_PA7	(GPIO_PIOA_BASE +  7)
++#define GPIO_PIN_PA8	(GPIO_PIOA_BASE +  8)
++#define GPIO_PIN_PA9	(GPIO_PIOA_BASE +  9)
++#define GPIO_PIN_PA10	(GPIO_PIOA_BASE + 10)
++#define GPIO_PIN_PA11	(GPIO_PIOA_BASE + 11)
++#define GPIO_PIN_PA12	(GPIO_PIOA_BASE + 12)
++#define GPIO_PIN_PA13	(GPIO_PIOA_BASE + 13)
++#define GPIO_PIN_PA14	(GPIO_PIOA_BASE + 14)
++#define GPIO_PIN_PA15	(GPIO_PIOA_BASE + 15)
++#define GPIO_PIN_PA16	(GPIO_PIOA_BASE + 16)
++#define GPIO_PIN_PA17	(GPIO_PIOA_BASE + 17)
++#define GPIO_PIN_PA18	(GPIO_PIOA_BASE + 18)
++#define GPIO_PIN_PA19	(GPIO_PIOA_BASE + 19)
++#define GPIO_PIN_PA20	(GPIO_PIOA_BASE + 20)
++#define GPIO_PIN_PA21	(GPIO_PIOA_BASE + 21)
++#define GPIO_PIN_PA22	(GPIO_PIOA_BASE + 22)
++#define GPIO_PIN_PA23	(GPIO_PIOA_BASE + 23)
++#define GPIO_PIN_PA24	(GPIO_PIOA_BASE + 24)
++#define GPIO_PIN_PA25	(GPIO_PIOA_BASE + 25)
++#define GPIO_PIN_PA26	(GPIO_PIOA_BASE + 26)
++#define GPIO_PIN_PA27	(GPIO_PIOA_BASE + 27)
++#define GPIO_PIN_PA28	(GPIO_PIOA_BASE + 28)
++#define GPIO_PIN_PA29	(GPIO_PIOA_BASE + 29)
++#define GPIO_PIN_PA30	(GPIO_PIOA_BASE + 30)
++#define GPIO_PIN_PA31	(GPIO_PIOA_BASE + 31)
++
++#define GPIO_PIOB_BASE	(GPIO_PIOA_BASE + 32)
++#define GPIO_PIN_PB0	(GPIO_PIOB_BASE +  0)
++#define GPIO_PIN_PB1	(GPIO_PIOB_BASE +  1)
++#define GPIO_PIN_PB2	(GPIO_PIOB_BASE +  2)
++#define GPIO_PIN_PB3	(GPIO_PIOB_BASE +  3)
++#define GPIO_PIN_PB4	(GPIO_PIOB_BASE +  4)
++#define GPIO_PIN_PB5	(GPIO_PIOB_BASE +  5)
++#define GPIO_PIN_PB6	(GPIO_PIOB_BASE +  6)
++#define GPIO_PIN_PB7	(GPIO_PIOB_BASE +  7)
++#define GPIO_PIN_PB8	(GPIO_PIOB_BASE +  8)
++#define GPIO_PIN_PB9	(GPIO_PIOB_BASE +  9)
++#define GPIO_PIN_PB10	(GPIO_PIOB_BASE + 10)
++#define GPIO_PIN_PB11	(GPIO_PIOB_BASE + 11)
++#define GPIO_PIN_PB12	(GPIO_PIOB_BASE + 12)
++#define GPIO_PIN_PB13	(GPIO_PIOB_BASE + 13)
++#define GPIO_PIN_PB14	(GPIO_PIOB_BASE + 14)
++#define GPIO_PIN_PB15	(GPIO_PIOB_BASE + 15)
++#define GPIO_PIN_PB16	(GPIO_PIOB_BASE + 16)
++#define GPIO_PIN_PB17	(GPIO_PIOB_BASE + 17)
++#define GPIO_PIN_PB18	(GPIO_PIOB_BASE + 18)
++#define GPIO_PIN_PB19	(GPIO_PIOB_BASE + 19)
++#define GPIO_PIN_PB20	(GPIO_PIOB_BASE + 20)
++#define GPIO_PIN_PB21	(GPIO_PIOB_BASE + 21)
++#define GPIO_PIN_PB22	(GPIO_PIOB_BASE + 22)
++#define GPIO_PIN_PB23	(GPIO_PIOB_BASE + 23)
++#define GPIO_PIN_PB24	(GPIO_PIOB_BASE + 24)
++#define GPIO_PIN_PB25	(GPIO_PIOB_BASE + 25)
++#define GPIO_PIN_PB26	(GPIO_PIOB_BASE + 26)
++#define GPIO_PIN_PB27	(GPIO_PIOB_BASE + 27)
++#define GPIO_PIN_PB28	(GPIO_PIOB_BASE + 28)
++#define GPIO_PIN_PB29	(GPIO_PIOB_BASE + 29)
++#define GPIO_PIN_PB30	(GPIO_PIOB_BASE + 30)
++
++#define GPIO_PIOC_BASE	(GPIO_PIOB_BASE + 32)
++#define GPIO_PIN_PC0	(GPIO_PIOC_BASE +  0)
++#define GPIO_PIN_PC1	(GPIO_PIOC_BASE +  1)
++#define GPIO_PIN_PC2	(GPIO_PIOC_BASE +  2)
++#define GPIO_PIN_PC3	(GPIO_PIOC_BASE +  3)
++#define GPIO_PIN_PC4	(GPIO_PIOC_BASE +  4)
++#define GPIO_PIN_PC5	(GPIO_PIOC_BASE +  5)
++#define GPIO_PIN_PC6	(GPIO_PIOC_BASE +  6)
++#define GPIO_PIN_PC7	(GPIO_PIOC_BASE +  7)
++#define GPIO_PIN_PC8	(GPIO_PIOC_BASE +  8)
++#define GPIO_PIN_PC9	(GPIO_PIOC_BASE +  9)
++#define GPIO_PIN_PC10	(GPIO_PIOC_BASE + 10)
++#define GPIO_PIN_PC11	(GPIO_PIOC_BASE + 11)
++#define GPIO_PIN_PC12	(GPIO_PIOC_BASE + 12)
++#define GPIO_PIN_PC13	(GPIO_PIOC_BASE + 13)
++#define GPIO_PIN_PC14	(GPIO_PIOC_BASE + 14)
++#define GPIO_PIN_PC15	(GPIO_PIOC_BASE + 15)
++#define GPIO_PIN_PC16	(GPIO_PIOC_BASE + 16)
++#define GPIO_PIN_PC17	(GPIO_PIOC_BASE + 17)
++#define GPIO_PIN_PC18	(GPIO_PIOC_BASE + 18)
++#define GPIO_PIN_PC19	(GPIO_PIOC_BASE + 19)
++#define GPIO_PIN_PC20	(GPIO_PIOC_BASE + 20)
++#define GPIO_PIN_PC21	(GPIO_PIOC_BASE + 21)
++#define GPIO_PIN_PC22	(GPIO_PIOC_BASE + 22)
++#define GPIO_PIN_PC23	(GPIO_PIOC_BASE + 23)
++#define GPIO_PIN_PC24	(GPIO_PIOC_BASE + 24)
++#define GPIO_PIN_PC25	(GPIO_PIOC_BASE + 25)
++#define GPIO_PIN_PC26	(GPIO_PIOC_BASE + 26)
++#define GPIO_PIN_PC27	(GPIO_PIOC_BASE + 27)
++#define GPIO_PIN_PC28	(GPIO_PIOC_BASE + 28)
++#define GPIO_PIN_PC29	(GPIO_PIOC_BASE + 29)
++#define GPIO_PIN_PC30	(GPIO_PIOC_BASE + 30)
++#define GPIO_PIN_PC31	(GPIO_PIOC_BASE + 31)
++
++#define GPIO_PIOD_BASE	(GPIO_PIOC_BASE + 32)
++#define GPIO_PIN_PD0	(GPIO_PIOD_BASE +  0)
++#define GPIO_PIN_PD1	(GPIO_PIOD_BASE +  1)
++#define GPIO_PIN_PD2	(GPIO_PIOD_BASE +  2)
++#define GPIO_PIN_PD3	(GPIO_PIOD_BASE +  3)
++#define GPIO_PIN_PD4	(GPIO_PIOD_BASE +  4)
++#define GPIO_PIN_PD5	(GPIO_PIOD_BASE +  5)
++#define GPIO_PIN_PD6	(GPIO_PIOD_BASE +  6)
++#define GPIO_PIN_PD7	(GPIO_PIOD_BASE +  7)
++#define GPIO_PIN_PD8	(GPIO_PIOD_BASE +  8)
++#define GPIO_PIN_PD9	(GPIO_PIOD_BASE +  9)
++#define GPIO_PIN_PD10	(GPIO_PIOD_BASE + 10)
++#define GPIO_PIN_PD11	(GPIO_PIOD_BASE + 11)
++#define GPIO_PIN_PD12	(GPIO_PIOD_BASE + 12)
++#define GPIO_PIN_PD13	(GPIO_PIOD_BASE + 13)
++#define GPIO_PIN_PD14	(GPIO_PIOD_BASE + 14)
++#define GPIO_PIN_PD15	(GPIO_PIOD_BASE + 15)
++#define GPIO_PIN_PD16	(GPIO_PIOD_BASE + 16)
++#define GPIO_PIN_PD17	(GPIO_PIOD_BASE + 17)
++
++#define GPIO_PIOE_BASE	(GPIO_PIOD_BASE + 32)
++#define GPIO_PIN_PE0	(GPIO_PIOE_BASE +  0)
++#define GPIO_PIN_PE1	(GPIO_PIOE_BASE +  1)
++#define GPIO_PIN_PE2	(GPIO_PIOE_BASE +  2)
++#define GPIO_PIN_PE3	(GPIO_PIOE_BASE +  3)
++#define GPIO_PIN_PE4	(GPIO_PIOE_BASE +  4)
++#define GPIO_PIN_PE5	(GPIO_PIOE_BASE +  5)
++#define GPIO_PIN_PE6	(GPIO_PIOE_BASE +  6)
++#define GPIO_PIN_PE7	(GPIO_PIOE_BASE +  7)
++#define GPIO_PIN_PE8	(GPIO_PIOE_BASE +  8)
++#define GPIO_PIN_PE9	(GPIO_PIOE_BASE +  9)
++#define GPIO_PIN_PE10	(GPIO_PIOE_BASE + 10)
++#define GPIO_PIN_PE11	(GPIO_PIOE_BASE + 11)
++#define GPIO_PIN_PE12	(GPIO_PIOE_BASE + 12)
++#define GPIO_PIN_PE13	(GPIO_PIOE_BASE + 13)
++#define GPIO_PIN_PE14	(GPIO_PIOE_BASE + 14)
++#define GPIO_PIN_PE15	(GPIO_PIOE_BASE + 15)
++#define GPIO_PIN_PE16	(GPIO_PIOE_BASE + 16)
++#define GPIO_PIN_PE17	(GPIO_PIOE_BASE + 17)
++#define GPIO_PIN_PE18	(GPIO_PIOE_BASE + 18)
++#define GPIO_PIN_PE19	(GPIO_PIOE_BASE + 19)
++#define GPIO_PIN_PE20	(GPIO_PIOE_BASE + 20)
++#define GPIO_PIN_PE21	(GPIO_PIOE_BASE + 21)
++#define GPIO_PIN_PE22	(GPIO_PIOE_BASE + 22)
++#define GPIO_PIN_PE23	(GPIO_PIOE_BASE + 23)
++#define GPIO_PIN_PE24	(GPIO_PIOE_BASE + 24)
++#define GPIO_PIN_PE25	(GPIO_PIOE_BASE + 25)
++#define GPIO_PIN_PE26	(GPIO_PIOE_BASE + 26)
++
++static inline void *gpio_pin_to_addr(unsigned int pin)
++{
++	switch (pin >> 5) {
++	case 0:
++		return (void *)PIOA_BASE;
++	case 1:
++		return (void *)PIOB_BASE;
++	case 2:
++		return (void *)PIOC_BASE;
++	case 3:
++		return (void *)PIOD_BASE;
++	case 4:
++		return (void *)PIOE_BASE;
++	default:
++		return NULL;
++	}
++}
++
++void gpio_select_periph_A(unsigned int pin, int use_pullup);
++void gpio_select_periph_B(unsigned int pin, int use_pullup);
++
++void gpio_enable_ebi(void);
++
++#ifdef AT32AP700x_CHIP_HAS_USART
++void gpio_enable_usart0(void);
++void gpio_enable_usart1(void);
++void gpio_enable_usart2(void);
++void gpio_enable_usart3(void);
++#endif
++#ifdef AT32AP700x_CHIP_HAS_MACB
++void gpio_enable_macb0(void);
++void gpio_enable_macb1(void);
++#endif
++#ifdef AT32AP700x_CHIP_HAS_MMCI
++void gpio_enable_mmci(void);
++#endif
++
++#endif /* __ASM_AVR32_ARCH_GPIO_H__ */
+diff --git a/include/asm-avr32/arch-at32ap700x/hmatrix2.h b/include/asm-avr32/arch-at32ap700x/hmatrix2.h
+new file mode 100644
+index 0000000..b0e787a
+--- /dev/null
++++ b/include/asm-avr32/arch-at32ap700x/hmatrix2.h
+@@ -0,0 +1,232 @@
++/*
++ * Register definition for the High-speed Bus Matrix
++ */
++#ifndef __ASM_AVR32_HMATRIX2_H__
++#define __ASM_AVR32_HMATRIX2_H__
++
++/* HMATRIX2 register offsets */
++#define HMATRIX2_MCFG0				0x0000
++#define HMATRIX2_MCFG1				0x0004
++#define HMATRIX2_MCFG2				0x0008
++#define HMATRIX2_MCFG3				0x000c
++#define HMATRIX2_MCFG4				0x0010
++#define HMATRIX2_MCFG5				0x0014
++#define HMATRIX2_MCFG6				0x0018
++#define HMATRIX2_MCFG7				0x001c
++#define HMATRIX2_MCFG8				0x0020
++#define HMATRIX2_MCFG9				0x0024
++#define HMATRIX2_MCFG10				0x0028
++#define HMATRIX2_MCFG11				0x002c
++#define HMATRIX2_MCFG12				0x0030
++#define HMATRIX2_MCFG13				0x0034
++#define HMATRIX2_MCFG14				0x0038
++#define HMATRIX2_MCFG15				0x003c
++#define HMATRIX2_SCFG0				0x0040
++#define HMATRIX2_SCFG1				0x0044
++#define HMATRIX2_SCFG2				0x0048
++#define HMATRIX2_SCFG3				0x004c
++#define HMATRIX2_SCFG4				0x0050
++#define HMATRIX2_SCFG5				0x0054
++#define HMATRIX2_SCFG6				0x0058
++#define HMATRIX2_SCFG7				0x005c
++#define HMATRIX2_SCFG8				0x0060
++#define HMATRIX2_SCFG9				0x0064
++#define HMATRIX2_SCFG10				0x0068
++#define HMATRIX2_SCFG11				0x006c
++#define HMATRIX2_SCFG12				0x0070
++#define HMATRIX2_SCFG13				0x0074
++#define HMATRIX2_SCFG14				0x0078
++#define HMATRIX2_SCFG15				0x007c
++#define HMATRIX2_PRAS0				0x0080
++#define HMATRIX2_PRBS0				0x0084
++#define HMATRIX2_PRAS1				0x0088
++#define HMATRIX2_PRBS1				0x008c
++#define HMATRIX2_PRAS2				0x0090
++#define HMATRIX2_PRBS2				0x0094
++#define HMATRIX2_PRAS3				0x0098
++#define HMATRIX2_PRBS3				0x009c
++#define HMATRIX2_PRAS4				0x00a0
++#define HMATRIX2_PRBS4				0x00a4
++#define HMATRIX2_PRAS5				0x00a8
++#define HMATRIX2_PRBS5				0x00ac
++#define HMATRIX2_PRAS6				0x00b0
++#define HMATRIX2_PRBS6				0x00b4
++#define HMATRIX2_PRAS7				0x00b8
++#define HMATRIX2_PRBS7				0x00bc
++#define HMATRIX2_PRAS8				0x00c0
++#define HMATRIX2_PRBS8				0x00c4
++#define HMATRIX2_PRAS9				0x00c8
++#define HMATRIX2_PRBS9				0x00cc
++#define HMATRIX2_PRAS10				0x00d0
++#define HMATRIX2_PRBS10				0x00d4
++#define HMATRIX2_PRAS11				0x00d8
++#define HMATRIX2_PRBS11				0x00dc
++#define HMATRIX2_PRAS12				0x00e0
++#define HMATRIX2_PRBS12				0x00e4
++#define HMATRIX2_PRAS13				0x00e8
++#define HMATRIX2_PRBS13				0x00ec
++#define HMATRIX2_PRAS14				0x00f0
++#define HMATRIX2_PRBS14				0x00f4
++#define HMATRIX2_PRAS15				0x00f8
++#define HMATRIX2_PRBS15				0x00fc
++#define HMATRIX2_MRCR				0x0100
++#define HMATRIX2_SFR0				0x0110
++#define HMATRIX2_SFR1				0x0114
++#define HMATRIX2_SFR2				0x0118
++#define HMATRIX2_SFR3				0x011c
++#define HMATRIX2_SFR4				0x0120
++#define HMATRIX2_SFR5				0x0124
++#define HMATRIX2_SFR6				0x0128
++#define HMATRIX2_SFR7				0x012c
++#define HMATRIX2_SFR8				0x0130
++#define HMATRIX2_SFR9				0x0134
++#define HMATRIX2_SFR10				0x0138
++#define HMATRIX2_SFR11				0x013c
++#define HMATRIX2_SFR12				0x0140
++#define HMATRIX2_SFR13				0x0144
++#define HMATRIX2_SFR14				0x0148
++#define HMATRIX2_SFR15				0x014c
++#define HMATRIX2_VERSION			0x01fc
++
++/* Bitfields in MCFG0 */
++#define HMATRIX2_ULBT_OFFSET			0
++#define HMATRIX2_ULBT_SIZE			3
++
++/* Bitfields in SCFG0 */
++#define HMATRIX2_SLOT_CYCLE_OFFSET		0
++#define HMATRIX2_SLOT_CYCLE_SIZE		8
++#define HMATRIX2_DEFMSTR_TYPE_OFFSET		16
++#define HMATRIX2_DEFMSTR_TYPE_SIZE		2
++#define HMATRIX2_FIXED_DEFMSTR_OFFSET		18
++#define HMATRIX2_FIXED_DEFMSTR_SIZE		4
++#define HMATRIX2_ARBT_OFFSET			24
++#define HMATRIX2_ARBT_SIZE			2
++
++/* Bitfields in PRAS0 */
++#define HMATRIX2_M0PR_OFFSET			0
++#define HMATRIX2_M0PR_SIZE			4
++#define HMATRIX2_M1PR_OFFSET			4
++#define HMATRIX2_M1PR_SIZE			4
++#define HMATRIX2_M2PR_OFFSET			8
++#define HMATRIX2_M2PR_SIZE			4
++#define HMATRIX2_M3PR_OFFSET			12
++#define HMATRIX2_M3PR_SIZE			4
++#define HMATRIX2_M4PR_OFFSET			16
++#define HMATRIX2_M4PR_SIZE			4
++#define HMATRIX2_M5PR_OFFSET			20
++#define HMATRIX2_M5PR_SIZE			4
++#define HMATRIX2_M6PR_OFFSET			24
++#define HMATRIX2_M6PR_SIZE			4
++#define HMATRIX2_M7PR_OFFSET			28
++#define HMATRIX2_M7PR_SIZE			4
++
++/* Bitfields in PRBS0 */
++#define HMATRIX2_M8PR_OFFSET			0
++#define HMATRIX2_M8PR_SIZE			4
++#define HMATRIX2_M9PR_OFFSET			4
++#define HMATRIX2_M9PR_SIZE			4
++#define HMATRIX2_M10PR_OFFSET			8
++#define HMATRIX2_M10PR_SIZE			4
++#define HMATRIX2_M11PR_OFFSET			12
++#define HMATRIX2_M11PR_SIZE			4
++#define HMATRIX2_M12PR_OFFSET			16
++#define HMATRIX2_M12PR_SIZE			4
++#define HMATRIX2_M13PR_OFFSET			20
++#define HMATRIX2_M13PR_SIZE			4
++#define HMATRIX2_M14PR_OFFSET			24
++#define HMATRIX2_M14PR_SIZE			4
++#define HMATRIX2_M15PR_OFFSET			28
++#define HMATRIX2_M15PR_SIZE			4
++
++/* Bitfields in MRCR */
++#define HMATRIX2_RBC0_OFFSET			0
++#define HMATRIX2_RBC0_SIZE			1
++#define HMATRIX2_RBC1_OFFSET			1
++#define HMATRIX2_RBC1_SIZE			1
++#define HMATRIX2_RBC2_OFFSET			2
++#define HMATRIX2_RBC2_SIZE			1
++#define HMATRIX2_RBC3_OFFSET			3
++#define HMATRIX2_RBC3_SIZE			1
++#define HMATRIX2_RBC4_OFFSET			4
++#define HMATRIX2_RBC4_SIZE			1
++#define HMATRIX2_RBC5_OFFSET			5
++#define HMATRIX2_RBC5_SIZE			1
++#define HMATRIX2_RBC6_OFFSET			6
++#define HMATRIX2_RBC6_SIZE			1
++#define HMATRIX2_RBC7_OFFSET			7
++#define HMATRIX2_RBC7_SIZE			1
++#define HMATRIX2_RBC8_OFFSET			8
++#define HMATRIX2_RBC8_SIZE			1
++#define HMATRIX2_RBC9_OFFSET			9
++#define HMATRIX2_RBC9_SIZE			1
++#define HMATRIX2_RBC10_OFFSET			10
++#define HMATRIX2_RBC10_SIZE			1
++#define HMATRIX2_RBC11_OFFSET			11
++#define HMATRIX2_RBC11_SIZE			1
++#define HMATRIX2_RBC12_OFFSET			12
++#define HMATRIX2_RBC12_SIZE			1
++#define HMATRIX2_RBC13_OFFSET			13
++#define HMATRIX2_RBC13_SIZE			1
++#define HMATRIX2_RBC14_OFFSET			14
++#define HMATRIX2_RBC14_SIZE			1
++#define HMATRIX2_RBC15_OFFSET			15
++#define HMATRIX2_RBC15_SIZE			1
++
++/* Bitfields in SFR0 */
++#define HMATRIX2_SFR_OFFSET			0
++#define HMATRIX2_SFR_SIZE			32
++
++/* Bitfields in SFR4 */
++#define HMATRIX2_CS1A_OFFSET			1
++#define HMATRIX2_CS1A_SIZE			1
++#define HMATRIX2_CS3A_OFFSET			3
++#define HMATRIX2_CS3A_SIZE			1
++#define HMATRIX2_CS4A_OFFSET			4
++#define HMATRIX2_CS4A_SIZE			1
++#define HMATRIX2_CS5A_OFFSET			5
++#define HMATRIX2_CS5A_SIZE			1
++#define HMATRIX2_DBPUC_OFFSET			8
++#define HMATRIX2_DBPUC_SIZE			1
++
++/* Bitfields in VERSION */
++#define HMATRIX2_VERSION_OFFSET			0
++#define HMATRIX2_VERSION_SIZE			12
++#define HMATRIX2_MFN_OFFSET			16
++#define HMATRIX2_MFN_SIZE			3
++
++/* Constants for ULBT */
++#define HMATRIX2_ULBT_INFINITE			0
++#define HMATRIX2_ULBT_SINGLE			1
++#define HMATRIX2_ULBT_FOUR_BEAT			2
++#define HMATRIX2_ULBT_SIXTEEN_BEAT		4
++
++/* Constants for DEFMSTR_TYPE */
++#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT	0
++#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT	1
++#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT	2
++
++/* Constants for ARBT */
++#define HMATRIX2_ARBT_ROUND_ROBIN		0
++#define HMATRIX2_ARBT_FIXED_PRIORITY		1
++
++/* Bit manipulation macros */
++#define HMATRIX2_BIT(name)					\
++	(1 << HMATRIX2_##name##_OFFSET)
++#define HMATRIX2_BF(name,value)					\
++	(((value) & ((1 << HMATRIX2_##name##_SIZE) - 1))	\
++	 << HMATRIX2_##name##_OFFSET)
++#define HMATRIX2_BFEXT(name,value)				\
++	(((value) >> HMATRIX2_##name##_OFFSET)			\
++	 & ((1 << HMATRIX2_##name##_SIZE) - 1))
++#define HMATRIX2_BFINS(name,value,old)				\
++	(((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1)		\
++		    << HMATRIX2_##name##_OFFSET))		\
++	 | HMATRIX2_BF(name,value))
++
++/* Register access macros */
++#define hmatrix2_readl(reg)					\
++	readl((void *)HMATRIX_BASE + HMATRIX2_##reg)
++#define hmatrix2_writel(reg,value)				\
++	writel((value), (void *)HMATRIX_BASE + HMATRIX2_##reg)
++
++#endif /* __ASM_AVR32_HMATRIX2_H__ */
+diff --git a/include/asm-avr32/arch-at32ap700x/memory-map.h b/include/asm-avr32/arch-at32ap700x/memory-map.h
+new file mode 100644
+index 0000000..5513e88
+--- /dev/null
++++ b/include/asm-avr32/arch-at32ap700x/memory-map.h
+@@ -0,0 +1,66 @@
++/*
++ * Copyright (C) 2005-2006 Atmel Corporation
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#ifndef __AT32AP7000_MEMORY_MAP_H__
++#define __AT32AP7000_MEMORY_MAP_H__
++
++/* Devices on the High Speed Bus (HSB) */
++#define LCDC_BASE				0xFF000000
++#define DMAC_BASE				0xFF200000
++#define USB_FIFO				0xFF300000
++
++/* Devices on Peripheral Bus A (PBA) */
++#define SPI0_BASE				0xFFE00000
++#define SPI1_BASE				0xFFE00400
++#define TWI_BASE				0xFFE00800
++#define USART0_BASE				0xFFE00C00
++#define USART1_BASE				0xFFE01000
++#define USART2_BASE				0xFFE01400
++#define USART3_BASE				0xFFE01800
++#define SSC0_BASE				0xFFE01C00
++#define SSC1_BASE				0xFFE02000
++#define SSC2_BASE				0xFFE02400
++#define PIOA_BASE				0xFFE02800
++#define PIOB_BASE				0xFFE02C00
++#define PIOC_BASE				0xFFE03000
++#define PIOD_BASE				0xFFE03400
++#define PIOE_BASE				0xFFE03800
++#define PSIF_BASE				0xFFE03C00
++
++/* Devices on Peripheral Bus B (PBB) */
++#define SM_BASE					0xFFF00000
++#define INTC_BASE				0xFFF00400
++#define HMATRIX_BASE				0xFFF00800
++#define TIMER0_BASE				0xFFF00C00
++#define TIMER1_BASE				0xFFF01000
++#define PWM_BASE				0xFFF01400
++#define MACB0_BASE				0xFFF01800
++#define MACB1_BASE				0xFFF01C00
++#define DAC_BASE				0xFFF02000
++#define MMCI_BASE				0xFFF02400
++#define AUDIOC_BASE				0xFFF02800
++#define HISI_BASE				0xFFF02C00
++#define USB_BASE				0xFFF03000
++#define HSMC_BASE				0xFFF03400
++#define HSDRAMC_BASE				0xFFF03800
++#define ECC_BASE				0xFFF03C00
++
++#endif /* __AT32AP7000_MEMORY_MAP_H__ */
+diff --git a/include/asm-avr32/arch-at32ap700x/mmc.h b/include/asm-avr32/arch-at32ap700x/mmc.h
+new file mode 100644
+index 0000000..fcfbbb3
+--- /dev/null
++++ b/include/asm-avr32/arch-at32ap700x/mmc.h
+@@ -0,0 +1,96 @@
++/*
++ * Copyright (C) 2004-2006 Atmel Corporation
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#ifndef __ASM_AVR32_MMC_H
++#define __ASM_AVR32_MMC_H
++
++struct mmc_cid {
++	unsigned long psn;
++	unsigned short oid;
++	unsigned char mid;
++	unsigned char prv;
++	unsigned char mdt;
++	char pnm[7];
++};
++
++struct mmc_csd
++{
++	u8	csd_structure:2,
++		spec_vers:4,
++		rsvd1:2;
++	u8	taac;
++	u8	nsac;
++	u8	tran_speed;
++	u16	ccc:12,
++		read_bl_len:4;
++	u64	read_bl_partial:1,
++		write_blk_misalign:1,
++		read_blk_misalign:1,
++		dsr_imp:1,
++		rsvd2:2,
++		c_size:12,
++		vdd_r_curr_min:3,
++		vdd_r_curr_max:3,
++		vdd_w_curr_min:3,
++		vdd_w_curr_max:3,
++		c_size_mult:3,
++		sector_size:5,
++		erase_grp_size:5,
++		wp_grp_size:5,
++		wp_grp_enable:1,
++		default_ecc:2,
++		r2w_factor:3,
++		write_bl_len:4,
++		write_bl_partial:1,
++		rsvd3:5;
++	u8	file_format_grp:1,
++		copy:1,
++		perm_write_protect:1,
++		tmp_write_protect:1,
++		file_format:2,
++		ecc:2;
++	u8	crc:7;
++	u8	one:1;
++};
++
++/* MMC Command numbers */
++#define MMC_CMD_GO_IDLE_STATE		0
++#define MMC_CMD_SEND_OP_COND		1
++#define MMC_CMD_ALL_SEND_CID 		2
++#define MMC_CMD_SET_RELATIVE_ADDR	3
++#define MMC_CMD_SD_SEND_RELATIVE_ADDR	3
++#define MMC_CMD_SET_DSR			4
++#define MMC_CMD_SELECT_CARD		7
++#define MMC_CMD_SEND_CSD 		9
++#define MMC_CMD_SEND_CID 		10
++#define MMC_CMD_SEND_STATUS		13
++#define MMC_CMD_SET_BLOCKLEN		16
++#define MMC_CMD_READ_SINGLE_BLOCK	17
++#define MMC_CMD_READ_MULTIPLE_BLOCK	18
++#define MMC_CMD_WRITE_BLOCK		24
++#define MMC_CMD_APP_CMD			55
++
++#define MMC_ACMD_SD_SEND_OP_COND	41
++
++#define R1_ILLEGAL_COMMAND		(1 << 22)
++#define R1_APP_CMD			(1 << 5)
++
++#endif /* __ASM_AVR32_MMC_H */
+diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
+new file mode 100644
+index 0000000..0be5fcb
+--- /dev/null
++++ b/include/configs/atngw100.h
+@@ -0,0 +1,177 @@
++/*
++ * Copyright (C) 2006 Atmel Corporation
++ *
++ * Configuration settings for the AVR32 Network Gateway
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#define CONFIG_AVR32			1
++#define CONFIG_AT32AP			1
++#define CONFIG_AT32AP7000		1
++#define CONFIG_ATNGW100			1
++
++#define CONFIG_ATNGW100_EXT_FLASH	1
++
++#define CFG_HZ				1000
++
++/*
++ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
++ * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
++ * and the PBA bus to run at 1/4 the PLL frequency.
++ */
++#define CONFIG_PLL			1
++#define CFG_POWER_MANAGER		1
++#define CFG_OSC0_HZ			20000000
++#define CFG_PLL0_DIV			1
++#define CFG_PLL0_MUL			7
++#define CFG_PLL0_SUPPRESS_CYCLES	16
++#define CFG_CLKDIV_CPU			0
++#define CFG_CLKDIV_HSB			1
++#define CFG_CLKDIV_PBA			2
++#define CFG_CLKDIV_PBB			1
++
++/*
++ * The PLLOPT register controls the PLL like this:
++ *   icp = PLLOPT<2>
++ *   ivco = PLLOPT<1:0>
++ *
++ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
++ */
++#define CFG_PLL0_OPT			0x04
++
++#define CONFIG_USART1			1
++
++/* User serviceable stuff */
++#define CONFIG_DOS_PARTITION		1
++
++#define CONFIG_CMDLINE_TAG		1
++#define CONFIG_SETUP_MEMORY_TAGS	1
++#define CONFIG_INITRD_TAG		1
++
++#define CONFIG_STACKSIZE		(2048)
++
++#define CONFIG_BAUDRATE			115200
++#define CONFIG_BOOTARGS							\
++	"console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2"
++#define CONFIG_BOOTCOMMAND						\
++	"fsload; bootm"
++
++/*
++ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
++ * data on the serial line may interrupt the boot sequence.
++ */
++#define CONFIG_BOOTDELAY		1
++#define CONFIG_AUTOBOOT			1
++#define CONFIG_AUTOBOOT_KEYED		1
++#define CONFIG_AUTOBOOT_PROMPT				\
++        "Press SPACE to abort autoboot in %d seconds\n"
++#define CONFIG_AUTOBOOT_DELAY_STR	"d"
++#define CONFIG_AUTOBOOT_STOP_STR	" "
++
++/*
++ * After booting the board for the first time, new ethernet addresses
++ * should be generated and assigned to the environment variables
++ * "ethaddr" and "eth1addr". This is normally done during production.
++ */
++#define CONFIG_OVERWRITE_ETHADDR_ONCE	1
++#define CONFIG_NET_MULTI		1
++
++/*
++ * BOOTP/DHCP options
++ */
++#define CONFIG_BOOTP_SUBNETMASK
++#define CONFIG_BOOTP_GATEWAY
++
++#define CONFIG_DOS_PARTITION		1
++
++/*
++ * Command line configuration.
++ */
++#include <config_cmd_default.h>
++
++#define CONFIG_CMD_ASKENV
++#define CONFIG_CMD_DHCP
++#define CONFIG_CMD_EXT2
++#define CONFIG_CMD_FAT
++#define CONFIG_CMD_JFFS2
++#define CONFIG_CMD_MMC
++#undef CONFIG_CMD_FPGA
++#undef CONFIG_CMD_SETGETDCR
++
++#define CONFIG_ATMEL_USART		1
++#define CONFIG_MACB			1
++#define CONFIG_PIO2			1
++#define CFG_NR_PIOS			5
++#define CFG_HSDRAMC			1
++#define CONFIG_MMC			1
++
++#define CFG_DCACHE_LINESZ		32
++#define CFG_ICACHE_LINESZ		32
++
++#define CONFIG_NR_DRAM_BANKS		1
++
++#define CFG_FLASH_BASE			0x00000000
++#define CFG_FLASH_SIZE			0x800000
++#define CFG_MAX_FLASH_BANKS		1
++#define CFG_MAX_FLASH_SECT		135
++
++#define CFG_MONITOR_BASE		CFG_FLASH_BASE
++
++#define CFG_INTRAM_BASE			0x24000000
++#define CFG_INTRAM_SIZE			0x8000
++
++#define CFG_SDRAM_BASE			0x10000000
++#define CFG_SDRAM_16BIT			1
++
++#define CFG_ENV_IS_IN_FLASH		1
++#define CFG_ENV_SIZE			65536
++#define CFG_ENV_ADDR			(CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
++
++#define CFG_INIT_SP_ADDR		(CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
++
++#define CFG_MALLOC_LEN			(256*1024)
++#define CFG_MALLOC_END							\
++	({								\
++		DECLARE_GLOBAL_DATA_PTR;				\
++		CFG_SDRAM_BASE + gd->sdram_size;			\
++	})
++#define CFG_MALLOC_START		(CFG_MALLOC_END - CFG_MALLOC_LEN)
++
++#define CFG_DMA_ALLOC_LEN		(16384)
++
++/* Allow 4MB for the kernel run-time image */
++#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00400000)
++#define CFG_BOOTPARAMS_LEN		(16 * 1024)
++
++/* Other configuration settings that shouldn't have to change all that often */
++#define CFG_PROMPT			"Uboot> "
++#define CFG_CBSIZE			256
++#define CFG_MAXARGS			16
++#define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
++#define CFG_LONGHELP			1
++
++#define CFG_MEMTEST_START		CFG_SDRAM_BASE
++#define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x1f00000)
++
++#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
++
++#endif /* __CONFIG_H */
+diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
+index b33e26f..95aeab6 100644
+--- a/include/configs/atstk1002.h
++++ b/include/configs/atstk1002.h
+@@ -184,8 +184,8 @@
+ #define CFG_MALLOC_LEN			(256*1024)
+ #define CFG_DMA_ALLOC_LEN		(16384)
+ 
+-/* Allow 2MB for the kernel run-time image */
+-#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00200000)
++/* Allow 4MB for the kernel run-time image */
++#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00400000)
+ #define CFG_BOOTPARAMS_LEN		(16 * 1024)
+ 
+ /* Other configuration settings that shouldn't have to change all that often */
+diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h
+new file mode 100644
+index 0000000..194788b
+--- /dev/null
++++ b/include/configs/atstk1003.h
+@@ -0,0 +1,184 @@
++/*
++ * Copyright (C) 2007 Atmel Corporation
++ *
++ * Configuration settings for the ATSTK1003 CPU daughterboard
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#define CONFIG_AVR32			1
++#define CONFIG_AT32AP			1
++#define CONFIG_AT32AP7001		1
++#define CONFIG_ATSTK1003		1
++#define CONFIG_ATSTK1000		1
++
++#define CONFIG_ATSTK1000_EXT_FLASH	1
++
++/*
++ * Timer clock frequency. We're using the CPU-internal COUNT register
++ * for this, so this is equivalent to the CPU core clock frequency
++ */
++#define CFG_HZ				1000
++
++/*
++ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
++ * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
++ * PLL frequency.
++ * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
++ */
++#define CONFIG_PLL			1
++#define CFG_POWER_MANAGER		1
++#define CFG_OSC0_HZ			20000000
++#define CFG_PLL0_DIV			1
++#define CFG_PLL0_MUL			7
++#define CFG_PLL0_SUPPRESS_CYCLES	16
++/*
++ * Set the CPU running at:
++ * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
++ */
++#define CFG_CLKDIV_CPU			0
++/*
++ * Set the HSB running at:
++ * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
++ */
++#define CFG_CLKDIV_HSB			1
++/*
++ * Set the PBA running at:
++ * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
++ */
++#define CFG_CLKDIV_PBA			2
++/*
++ * Set the PBB running at:
++ * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
++ */
++#define CFG_CLKDIV_PBB			1
++
++/*
++ * The PLLOPT register controls the PLL like this:
++ *   icp = PLLOPT<2>
++ *   ivco = PLLOPT<1:0>
++ *
++ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
++ */
++#define CFG_PLL0_OPT			0x04
++
++#undef CONFIG_USART0
++#define CONFIG_USART1			1
++#undef CONFIG_USART2
++#undef CONFIG_USART3
++
++/* User serviceable stuff */
++#define CONFIG_DOS_PARTITION		1
++
++#define CONFIG_CMDLINE_TAG		1
++#define CONFIG_SETUP_MEMORY_TAGS	1
++#define CONFIG_INITRD_TAG		1
++
++#define CONFIG_STACKSIZE		(2048)
++
++#define CONFIG_BAUDRATE			115200
++#define CONFIG_BOOTARGS							\
++	"console=ttyS0 root=/dev/mmcblk0p1 rootwait"
++
++#define CONFIG_BOOTCOMMAND						\
++	"mmcinit; ext2load mmc 0:1 0x10400000 /boot/uImage; bootm"
++
++/*
++ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
++ * data on the serial line may interrupt the boot sequence.
++ */
++#define CONFIG_BOOTDELAY		1
++#define CONFIG_AUTOBOOT			1
++#define CONFIG_AUTOBOOT_KEYED		1
++#define CONFIG_AUTOBOOT_PROMPT				\
++	"Press SPACE to abort autoboot in %d seconds\n"
++#define CONFIG_AUTOBOOT_DELAY_STR	"d"
++#define CONFIG_AUTOBOOT_STOP_STR	" "
++
++/*
++ * Command line configuration.
++ */
++#include <config_cmd_default.h>
++
++#define CONFIG_CMD_ASKENV
++#define CONFIG_CMD_EXT2
++#define CONFIG_CMD_FAT
++#define CONFIG_CMD_JFFS2
++#define CONFIG_CMD_MMC
++
++#undef CONFIG_CMD_FPGA
++#undef CONFIG_CMD_NET
++#undef CONFIG_CMD_NFS
++#undef CONFIG_CMD_SETGETDCR
++#undef CONFIG_CMD_XIMG
++
++#define CONFIG_ATMEL_USART		1
++#define CONFIG_PIO2			1
++#define CFG_HSDRAMC			1
++#define CONFIG_MMC			1
++
++#define CFG_DCACHE_LINESZ		32
++#define CFG_ICACHE_LINESZ		32
++
++#define CONFIG_NR_DRAM_BANKS		1
++
++/* External flash on STK1000 */
++#if 0
++#define CFG_FLASH_CFI			1
++#define CFG_FLASH_CFI_DRIVER		1
++#endif
++
++#define CFG_FLASH_BASE			0x00000000
++#define CFG_FLASH_SIZE			0x800000
++#define CFG_MAX_FLASH_BANKS		1
++#define CFG_MAX_FLASH_SECT		135
++
++#define CFG_MONITOR_BASE		CFG_FLASH_BASE
++
++#define CFG_INTRAM_BASE			0x24000000
++#define CFG_INTRAM_SIZE			0x8000
++
++#define CFG_SDRAM_BASE			0x10000000
++
++#define CFG_ENV_IS_IN_FLASH		1
++#define CFG_ENV_SIZE			65536
++#define CFG_ENV_ADDR			(CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
++
++#define CFG_INIT_SP_ADDR		(CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
++
++#define CFG_MALLOC_LEN			(256*1024)
++
++/* Allow 4MB for the kernel run-time image */
++#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00400000)
++#define CFG_BOOTPARAMS_LEN		(16 * 1024)
++
++/* Other configuration settings that shouldn't have to change all that often */
++#define CFG_PROMPT			"Uboot> "
++#define CFG_CBSIZE			256
++#define CFG_MAXARGS			16
++#define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
++#define CFG_LONGHELP			1
++
++#define CFG_MEMTEST_START		CFG_SDRAM_BASE
++#define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x700000)
++#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
++
++#endif /* __CONFIG_H */
+diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h
+new file mode 100644
+index 0000000..b81fc21
+--- /dev/null
++++ b/include/configs/atstk1004.h
+@@ -0,0 +1,185 @@
++/*
++ * Copyright (C) 2007 Atmel Corporation
++ *
++ * Configuration settings for the ATSTK1003 CPU daughterboard
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#define CONFIG_AVR32			1
++#define CONFIG_AT32AP			1
++#define CONFIG_AT32AP7002		1
++#define CONFIG_ATSTK1004		1
++#define CONFIG_ATSTK1000		1
++
++#define CONFIG_ATSTK1000_EXT_FLASH	1
++
++/*
++ * Timer clock frequency. We're using the CPU-internal COUNT register
++ * for this, so this is equivalent to the CPU core clock frequency
++ */
++#define CFG_HZ				1000
++
++/*
++ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
++ * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
++ * PLL frequency.
++ * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
++ */
++#define CONFIG_PLL			1
++#define CFG_POWER_MANAGER		1
++#define CFG_OSC0_HZ			20000000
++#define CFG_PLL0_DIV			1
++#define CFG_PLL0_MUL			7
++#define CFG_PLL0_SUPPRESS_CYCLES	16
++/*
++ * Set the CPU running at:
++ * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
++ */
++#define CFG_CLKDIV_CPU			0
++/*
++ * Set the HSB running at:
++ * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
++ */
++#define CFG_CLKDIV_HSB			1
++/*
++ * Set the PBA running at:
++ * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
++ */
++#define CFG_CLKDIV_PBA			2
++/*
++ * Set the PBB running at:
++ * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
++ */
++#define CFG_CLKDIV_PBB			1
++
++/*
++ * The PLLOPT register controls the PLL like this:
++ *   icp = PLLOPT<2>
++ *   ivco = PLLOPT<1:0>
++ *
++ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
++ */
++#define CFG_PLL0_OPT			0x04
++
++#undef CONFIG_USART0
++#define CONFIG_USART1			1
++#undef CONFIG_USART2
++#undef CONFIG_USART3
++
++/* User serviceable stuff */
++#define CONFIG_DOS_PARTITION		1
++
++#define CONFIG_CMDLINE_TAG		1
++#define CONFIG_SETUP_MEMORY_TAGS	1
++#define CONFIG_INITRD_TAG		1
++
++#define CONFIG_STACKSIZE		(2048)
++
++#define CONFIG_BAUDRATE			115200
++#define CONFIG_BOOTARGS							\
++	"console=ttyS0 root=/dev/mmcblk0p1 rootwait"
++
++#define CONFIG_BOOTCOMMAND						\
++	"mmcinit; ext2load mmc 0:1 0x10200000 /boot/uImage; bootm"
++
++/*
++ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
++ * data on the serial line may interrupt the boot sequence.
++ */
++#define CONFIG_BOOTDELAY		1
++#define CONFIG_AUTOBOOT			1
++#define CONFIG_AUTOBOOT_KEYED		1
++#define CONFIG_AUTOBOOT_PROMPT				\
++	"Press SPACE to abort autoboot in %d seconds\n"
++#define CONFIG_AUTOBOOT_DELAY_STR	"d"
++#define CONFIG_AUTOBOOT_STOP_STR	" "
++
++/*
++ * Command line configuration.
++ */
++#include <config_cmd_default.h>
++
++#define CONFIG_CMD_ASKENV
++#define CONFIG_CMD_EXT2
++#define CONFIG_CMD_FAT
++#define CONFIG_CMD_JFFS2
++#define CONFIG_CMD_MMC
++
++#undef CONFIG_CMD_FPGA
++#undef CONFIG_CMD_NET
++#undef CONFIG_CMD_NFS
++#undef CONFIG_CMD_SETGETDCR
++#undef CONFIG_CMD_XIMG
++
++#define CONFIG_ATMEL_USART		1
++#define CONFIG_PIO2			1
++#define CFG_HSDRAMC			1
++#define CONFIG_MMC			1
++
++#define CFG_DCACHE_LINESZ		32
++#define CFG_ICACHE_LINESZ		32
++
++#define CONFIG_NR_DRAM_BANKS		1
++
++/* External flash on STK1000 */
++#if 0
++#define CFG_FLASH_CFI			1
++#define CFG_FLASH_CFI_DRIVER		1
++#endif
++
++#define CFG_FLASH_BASE			0x00000000
++#define CFG_FLASH_SIZE			0x800000
++#define CFG_MAX_FLASH_BANKS		1
++#define CFG_MAX_FLASH_SECT		135
++
++#define CFG_MONITOR_BASE		CFG_FLASH_BASE
++
++#define CFG_INTRAM_BASE			0x24000000
++#define CFG_INTRAM_SIZE			0x8000
++
++#define CFG_SDRAM_BASE			0x10000000
++#define CFG_SDRAM_16BIT			1
++
++#define CFG_ENV_IS_IN_FLASH		1
++#define CFG_ENV_SIZE			65536
++#define CFG_ENV_ADDR			(CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
++
++#define CFG_INIT_SP_ADDR		(CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
++
++#define CFG_MALLOC_LEN			(256*1024)
++
++/* Allow 2MB for the kernel run-time image */
++#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00200000)
++#define CFG_BOOTPARAMS_LEN		(16 * 1024)
++
++/* Other configuration settings that shouldn't have to change all that often */
++#define CFG_PROMPT			"Uboot> "
++#define CFG_CBSIZE			256
++#define CFG_MAXARGS			16
++#define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
++#define CFG_LONGHELP			1
++
++#define CFG_MEMTEST_START		CFG_SDRAM_BASE
++#define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x700000)
++#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
++
++#endif /* __CONFIG_H */
+diff --git a/lib_avr32/board.c b/lib_avr32/board.c
+index 11d864f..4729e58 100644
+--- a/lib_avr32/board.c
++++ b/lib_avr32/board.c
+@@ -264,6 +264,7 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
+ #ifndef CFG_ENV_IS_NOWHERE
+ 	extern char * env_name_spec;
+ #endif
++	char *s;
+ 	cmd_tbl_t *cmdtp;
+ 	bd_t *bd;
+ 
+@@ -334,11 +335,20 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
+ 	/* initialize environment */
+ 	env_relocate();
+ 
++	bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
++
+ 	devices_init();
+ 	jumptable_init();
+ 	console_init_r();
+ 
++	s = getenv("loadaddr");
++	if (s)
++		load_addr = simple_strtoul(s, NULL, 16);
++
+ #if defined(CONFIG_CMD_NET)
++	s = getenv("bootfile");
++	if (s)
++		copy_filename(BootFile, s, sizeof(BootFile));
+ #if defined(CONFIG_NET_MULTI)
+ 	puts("Net:   ");
+ #endif
+diff --git a/net/eth.c b/net/eth.c
+index 1b56a35..3e24a4c 100644
+--- a/net/eth.c
++++ b/net/eth.c
+@@ -60,6 +60,7 @@ extern int npe_initialize(bd_t *);
+ extern int uec_initialize(int);
+ extern int bfin_EMAC_initialize(bd_t *);
+ extern int atstk1000_eth_initialize(bd_t *);
++extern int atngw100_eth_initialize(bd_t *);
+ extern int mcffec_initialize(bd_t*);
+ 
+ static struct eth_device *eth_devices, *eth_current;
+@@ -254,6 +255,9 @@ int eth_initialize(bd_t *bis)
+ #if defined(CONFIG_ATSTK1000)
+ 	atstk1000_eth_initialize(bis);
+ #endif
++#if defined(CONFIG_ATNGW100)
++	atngw100_eth_initialize(bis);
++#endif
+ #if defined(CONFIG_MCFFEC)
+ 	mcffec_initialize(bis);
+ #endif