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authorEric Anholt <eric@anholt.net>2010-05-13 23:01:17 -0700
committerEric Anholt <eric@anholt.net>2010-05-14 11:27:59 -0700
commit1c25353bc66902ed684b41bb8198b9787c0ce25b (patch)
treef7ccf388c976e81770d9ec541f92f54167226ac0
parentf5bd48cf673456ffea730f28c9b95c6883399162 (diff)
i965: Parse the ff_sync URB send opcode on Ironlake disasm.
-rw-r--r--src/mesa/drivers/dri/i965/brw_disasm.c16
1 files changed, 15 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index 9c600f28bd..ff12daf497 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -323,6 +323,11 @@ char *math_precision[2] = {
[1] = "partial_precision"
};
+char *urb_opcode[2] = {
+ [0] = "urb_write",
+ [1] = "ff_sync",
+};
+
char *urb_swizzle[4] = {
[BRW_URB_SWIZZLE_NONE] = "",
[BRW_URB_SWIZZLE_INTERLEAVE] = "interleave",
@@ -872,8 +877,17 @@ int brw_disasm (FILE *file, struct brw_instruction *inst, int gen)
inst->bits3.dp_write.send_commit_msg);
break;
case BRW_MESSAGE_TARGET_URB:
- format (file, " %d", inst->bits3.urb.offset);
+ if (gen >= 5) {
+ format (file, " %d", inst->bits3.urb_gen5.offset);
+ } else {
+ format (file, " %d", inst->bits3.urb.offset);
+ }
+
space = 1;
+ if (gen >= 5) {
+ err |= control (file, "urb opcode", urb_opcode,
+ inst->bits3.urb_gen5.opcode, &space);
+ }
err |= control (file, "urb swizzle", urb_swizzle,
inst->bits3.urb.swizzle_control, &space);
err |= control (file, "urb allocate", urb_allocate,